a 3 V/5 V, CMOS, 500 Signal Conditioning ADC AD7714

a 3 V/5 V, CMOS, 500 Signal Conditioning ADC AD7714

a

FEATURES

Charge Balancing ADC

24 Bits No Missing Codes

0.0015% Nonlinearity

Five-Channel Programmable Gain Front End

Gains from 1 to 128

Can Be Configured as Three Fully Differential

Inputs or Five Pseudo-Differential Inputs

Three-Wire Serial Interface

SPI™, QSPI™, MICROWIRE™ and DSP Compatible

3 V (AD7714-3) or 5 V (AD7714-5) Operation

Low Noise (<150 nV rms)

Low Current (350␣

A typ) with Power-Down (5 A typ)

AD7714Y Grade:

+2.7 V to 3.3 V or +4.75 V to +5.25 V Operation

0.0010% Linearity Error

–40

C to +105C Temperature Range

Schmitt Trigger on SCLK and DIN

Low Current (226␣

A typ) with Power-Down (4 A typ)

Lower Power Dissipation than Standard AD7714

Available in 24-Lead TSSOP Package

Low-Pass Filter with Programmable Filter Cutoffs

Ability to Read/Write Calibration Coefficients

APPLICATIONS

Portable Industrial Instruments

Portable Weigh Scales

Loop-Powered Systems

Pressure Transducers

GENERAL DESCRIPTION†

The AD7714 is a complete analog front end for low-frequency measurement applications. The device accepts low level signals directly from a transducer and outputs a serial digital word. It employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an onchip digital filter. The first notch of this digital filter can be programmed via the on-chip control register allowing adjustment of the filter cutoff and settling time.

The part features three differential analog inputs (which can also be configured as five pseudo-differential analog inputs) as well as a differential reference input. It operates from a single supply (+3␣ V or +5␣ V). The AD7714 thus performs all signal conditioning and conversion for a system consisting of up to five channels.

The AD7714 is ideal for use in smart, microcontroller- or DSPbased systems. It features a serial interface that can be configured

†See page 39 for data sheet index.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

3 V/5 V, CMOS, 500

A

Signal Conditioning ADC

AD7714

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

FUNCTIONAL BLOCK DIAGRAM

AV

DD

DV

DD

REF IN(–) REF IN(+)

AV

DD

1

m

A

AGND

1

m

A

BUFFER PGA

CHARGE

BALANCING

A/D CONVERTER

Σ

-

MODULATOR

DIGITAL FILTER

A = 1–128

SERIAL INTERFACE

REGISTER BANK

STANDBY

SYNC

BUFFER

MCLK IN

MCLK OUT

CLOCK

GENERATION

AD7714

SCLK

CS

DIN

DOUT

AGND

DGND POL

DRDY RESET

for three-wire operation. Gain settings, signal polarity and channel selection can be configured in software using the serial port. The

AD7714 provides self-calibration, system calibration and background calibration options and also allows the user to read and write the on-chip calibration registers.

CMOS construction ensures very low power dissipation, and the power-down mode reduces the standby power consumption to

15␣

µ

W typ. The part is available in a 24-pin, 0.3 inch-wide, plastic dual-in-line package (DIP); a 24-lead small outline (SOIC) package, a 28-lead shrink small outline package (SSOP) and a

24-lead thin shrink small outline package (TSSOP).

PRODUCT HIGHLIGHTS

1. The AD7714Y offers the following features in addition to the standard AD7714: wider temperature range, Schmitt trigger on SCLK and DIN, operation down to 2.7 V, lower power consumption, better linearity, and availability in 24-lead

TSSOP package.

2. The AD7714 consumes less than 500

µ

A (f

CLK IN

= 1␣ MHz) or 1 mA (f

CLK IN

= 2.5␣ MHz) in total supply current, making it ideal for use in loop-powered systems.

3. The programmable gain channels allow the AD7714 to accept input signals directly from a strain gage or transducer removing a considerable amount of signal conditioning.

4. The AD7714 is ideal for microcontroller or DSP processor applications with a three-wire serial interface reducing the number of interconnect lines and reducing the number of optocouplers required in isolated systems. The part contains on-chip registers that allow control over filter cutoff, input gain, channel selection, signal polarity and calibration modes.

5. The part features excellent static performance specifications with 24-bit no missing codes,

±

0.0015% accuracy and low rms noise (140 nV). Endpoint errors and the effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

© Analog Devices, Inc., 1998

AD7714-5–SPECIFICATIONS

(AV

DD

= +5␣ V, DV

DD

= +3.3␣ V or +5␣ V, REF IN(+) = +2.5␣ V; REF␣ IN(–) = AGND; f

CLK IN

= 2.4576␣ MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter A Versions

1

Units Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Output Noise

Integral Nonlinearity

Unipolar Offset Error

Unipolar Offset Drift

Bipolar Zero Error

Bipolar Zero Drift

3

Positive Full-Scale Error

Full-Scale Drift

Gain Error

Gain Drift

6

3, 7

3, 5

3

4

Bipolar Negative Full-Scale Error

Bipolar Negative Full-Scale Drift

3

24

22

18

15

12

See Tables I to IV

±

0.0015

See Note 2

0.5

0.3

See Note 2

0.5

0.3

See Note 2

0.5

0.3

See Note 2

0.5

±

0.0015

1

0.6

ANALOG INPUTS/REFERENCE INPUTS

Input Common-Mode Rejection (CMR) 90

Normal-Mode 50 Hz Rejection

8

100

Normal-Mode 60 Hz Rejection

8

Common-Mode 50 Hz Rejection

8

100

150

Common-Mode 60 Hz Rejection

8

Common-Mode Voltage Range

9

Absolute AIN/REF IN Voltage

9

150

AGND to AV

DD

AGND – 30 mV

Absolute/Common-Mode AIN Voltage

AIN Input Current

8

AIN Sampling Capacitance

8

AIN Differential Voltage Range

10

AIN Input Sampling Rate, f

S

REF IN(+) – REF IN(–) Voltage

9

AV

DD

+ 30 mV

AGND + 50 mV

AV

DD

– 1.5 V

1

7

0 to +V

REF

/GAIN

±

V

REF

/GAIN

GAIN

×

f

CLK␣ IN

/64 f

CLK␣ IN

/8

+2.5

11

REF IN Input Sampling Rate, f

S f

CLK IN

/64

LOGIC INPUTS

Input Current

All Inputs Except MCLK IN

V

INL

, Input Low Voltage

V

INL

, Input Low Voltage

V

INH

, Input High Voltage

V

INH

, Input High Voltage

MCLK IN Only

V

INL

, Input Low Voltage

V

INL

, Input Low Voltage

V

INH

, Input High Voltage

V

INH

, Input High Voltage

LOGIC OUTPUTS (Including MCLK OUT)

V

OL

, Output Low Voltage

V

OL

, Output Low Voltage

V

OH

, Output High Voltage

V

OH

, Output High Voltage

Floating State Leakage Current

Floating State Output Capacitance

13

Data Output Coding

±

10

0.8

0.4

2.4

2.0

0.8

0.4

3.5

2.5

0.4

0.4

4.0

DV

DD

– 0.6 V

±

10

9

Binary

Offset Binary

Bits min

Bits min

Bits min

Bits min

Bits min

% of FSR max

µ

µ

µ

µ

µ

µ

µ

V/

V/

V/

V/

V/

V/

°

°

°

°

°

°

C typ

C typ

C typ

C typ

C typ

C typ ppm of FSR/

% of FSR max

µ

V/

°

C typ

µ

V/

°

C typ dB min dB min dB min dB min dB min

V nom

A max

V max

V max

V min

V min

V max

V max

V min

V min

V max

V max

V min

V min

µ

A max pF typ

°

C typ

V min to V max

V min

V max

V min

V max nA max pF max nom nom

Guaranteed by Design. Bipolar Mode. For Filter Notches

For Filter Notch = 100 Hz

For Filter Notch = 250 Hz

For Filter Notch = 500 Hz

For Filter Notch = 1 kHz

Depends on Filter Cutoffs and Selected Gain

Filter Notches

60 Hz

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

Typically

±

0.0004%

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

Specifications for AIN and REF IN Unless Noted

At DC. Typically 102 dB

For Filter Notches of 10 Hz , 25 Hz , 50 Hz,

±

0.02

×

f

For Filter Notches of 10 Hz , 30 Hz , 60 Hz,

±

0.02

×

f

NOTCH

For Filter Notches of 10 Hz , 25 Hz , 50 Hz,

±

0.02

×

f

NOTCH

For Filter Notches of 10 Hz , 30 Hz , 60 Hz,

±

0.02

×

f

NOTCH

NOTCH

AIN for BUFFER = 0 and REF IN

AIN for BUFFER = 0 and REF IN

BUFFER = 1. A Version

A Version

Bipolar Input Range (B/U Bit of Filter High Register = 0)

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

±

1% for Specified Performance. Functional with Lower V

DV

DV

DD

= +3.3␣ V

DV

DD

= +5 V

DV

DV

DV

DD

= +3.3␣ V

DV

DD

= +5␣ V

DV

I

SINK

= 800␣

µ

A Except for MCLK OUT.

12

DV

DD

I

I

DD

DD

DD

DD

= +3.3␣ V

SINK

= +5 V

= +3.3 V

= +5␣ V

= 100␣

SOURCE

µ

A Except for MCLK OUT.

12

= +5 V

Unipolar Input Range (B/U Bit of Filter High Register = 1)

60 Hz

REF

DV

DD

= +3.3 V

= 200

µ

A Except for MCLK OUT.

12

DV

I

SOURCE

= 100

µ

A Except for MCLK OUT.

12

DV

DD

= +5␣ V

DD

= +3.3␣ V

Unipolar Mode

Bipolar Mode

NOTES

1

Temperature range is as follows: A Versions: –40

°

C to +85

°

C.

2

A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.

3

Recalibration at any temperature will remove these drift errors.

4

Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.

5

Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

6

Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for bipolar ranges.

REV. C

–2–

AD7714

AD7714-3–SPECIFICATIONS

(AV

DD

= +3.3␣ V, DV

DD

= +3.3␣ V, REF IN(+) = +1.25␣ V; REF␣ IN(–) = AGND;

unless otherwise noted.) f

CLK IN

= 2.4576␣ MHz unless otherwise noted. All specifications T

MIN

to T

MAX

Parameter

STATIC PERFORMANCE

No Missing Codes

Output Noise

Integral Nonlinearity

Unipolar Offset Error

Unipolar Offset Drift

3

Bipolar Zero Error

Bipolar Zero Drift

Positive Full-Scale Error

Full-Scale Drift

3, 5

3

4

A Versions

24

22

18

15

12

See Tables I to IV

±

0.0015

See Note 2

0.4

0.1

See Note 2

0.4

0.1

See Note 2

0.4

0.1

See Note 2

0.2

±

0.003

1

0.6

Units

Bits min

Bits min

Bits min

Bits min

Bits min

% of FSR max

µ

µ

µ

µ

V/

V/

V/

V/

°

°

°

°

C typ

C typ

C typ

C typ

µ

V/

°

C typ

µ

V/

°

C typ

Conditions/Comments

Guaranteed by Design. Bipolar Mode. For Filter Notches

For Filter Notch = 100 Hz

For Filter Notch = 250 Hz

For Filter Notch = 500 Hz

For Filter Notch = 1 kHz

Depends on Filter Cutoffs and Selected Gain

Filter Notches

60 Hz

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

60 Hz

Gain Error

6

Gain Drift

3, 7

Bipolar Negative Full-Scale Error

Bipolar Negative Full-Scale Drift

3

ANALOG INPUTS/REFERENCE INPUTS

Input Common-Mode Rejection (CMR)

Normal-Mode 50 Hz Rejection

Normal-Mode 60 Hz Rejection

8

8

Common-Mode 50 Hz Rejection

Common-Mode 60 Hz Rejection

Common-Mode Voltage Range

Absolute AIN/REF IN Voltage

9

9

Absolute/Common-Mode AIN Voltage

AIN Input Current

8

AIN Sampling Capacitance

8

AIN Differential Voltage Range

10

8

8

9

90

100

100

150

150

AGND to AV

DD

AGND – 30 mV

AV

DD

+ 30 mV

AGND + 50 mV

AV

DD

– 1.5 V

1

7

0 to +V

REF

/GAIN

11

±

V

REF

/GAIN

GAIN

×

f

CLK␣ IN

/64 f

CLK␣ IN

/8

+1.25

ppm of FSR/

°

C typ

% of FSR max

µ

µ

V/

V/

°

°

C typ

C typ dB min dB min dB min dB min dB min

V min to V max

V min

V max

V min

V max nA max pF max nom nom

Typically

±

0.0004%

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

Specifications for AIN and REF IN Unless Noted

At DC. Typically 102 dB.

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

±

0.02

×

f

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

±

0.02

×

f

NOTCH

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

±

0.02

×

f

NOTCH

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

±

0.02

×

f

NOTCH

NOTCH

AIN for BUFFER = 0 and REF IN

AIN for BUFFER = 0 and REF IN

BUFFER = 1

AIN Input Sampling Rate, f

S

REF IN(+) – REF IN(–) Voltage V nom

Unipolar Input Range (B/U Bit of Filter High Register = 1)

Bipolar Input Range (B/U Bit of Filter High Register = 0)

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

±

1% for Specified Performance. Part Functions with

Lower V

REF

REF IN Input Sampling Rate, f

S

LOGIC INPUTS

Input Current

All Inputs Except MCLK IN

V

INL

, Input Low Voltage

V

INH

, Input High Voltage

MCLK IN Only

V

INL

, Input Low Voltage

V

INH

, Input High Voltage

LOGIC OUTPUTS (Including MCLK OUT)

V

OL

, Output Low Voltage

V

OH

, Output High Voltage

Floating State Leakage Current

Floating State Output Capacitance

Data Output Coding

13 f

±

CLK IN

10

0.4

2.0

0.4

2.5

/64

0.4

DV

DD

±

10

– 0.6

9

Binary

Offset Binary

µ

A max

V max

V min

V max

V min

V max

V min

µ

A max pF typ

I

SINK

= 100␣

µ

A Except for MCLK OUT

I

SOURCE

12

= 100

µ

A Except for MCLK OUT

12

Unipolar Mode

Bipolar Mode

NOTES

7

Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.

8

These numbers are guaranteed by design and/or characterization.

9

The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.

10

The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which inputs form differential pairs.

11

V

REF

= REF IN(+) – REF IN(–).

12

These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.

13

Sample tested at +25

°

C to ensure compliance.

14

See Burnout Current section.

REV. C

–3–

AD7714–SPECIFICATIONS

(AV

DD

= + 3.3␣ V to +5␣ V, DV

DD

= +3.3␣ V to +5␣ V, REF IN(+) = +1.25␣ V (AD7714-3) or +2.5␣ V

(AD7714-5); REF␣ IN(–) = AGND; MCLK␣ IN = 1␣ MHz to 2.4576␣ MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter

TRANSDUCER BURNOUT

14

Current

Initial Tolerance

Drift

A Versions

1

±

10

0.1

Units

µ

A nom

% typ

%/

°

C typ

Conditions/Comments

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit

Negative Full-Scale Calibration Limit

Offset Calibration Limit

Input Span

16

16

15

15

(1.05

×

V

REF

)/GAIN V max

–(1.05

×

V

REF

)/GAIN V max

–(1.05

×

V

REF

)/GAIN V max

0.8

×

V

REF

/GAIN V min

(2.1

×

V

REF

)/GAIN V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

POWER REQUIREMENTS

Power Supply Voltages

AV

DD

Voltage (AD7714-3)

AV

DD

Voltage (AD7714-5)

DV

DD

Voltage

Power Supply Currents

AV

DD

Current

DV

DD

Current

18

Power Supply Rejection

19

Normal-Mode Power Dissipation

Normal-Mode Power Dissipation

Standby (Power-Down) Current

Standby (Power-Down) Current

18

21

21

+3 to +3.6

+4.75 to +5.25

+3 to +5.25

0.27

0.6

0.5

1.1

0.23

0.4

0.5

0.8

See Note 20

1.65

2.75

2.55

3.65

3.35

5

5.35

7

40

10

V

V

V

For Specified Performance

For Specified Performance

For Specified Performance mA max mA max mA max mA max mA max mA max mA max mA max dB typ

AV

DD

= 3.3␣ V or 5␣ V. BST Bit of Filter High Register = 0

17

Typically 0.2 mA. BUFFER = 0 V. f

CLK IN

= 1␣ MHz or 2.4576␣ MHz

Typically 0.4 mA. BUFFER = DV

DD

. f

CLK IN

= 1␣ MHz or 2.4576␣ MHz

AV

DD

= 3.3␣ V or 5␣ V. BST Bit of Filter High Register = 1

17

Typically 0.3␣ mA. BUFFER = 0␣ V. f

CLK IN

= 2.4576␣ MHz

Typically 0.8␣ mA. BUFFER = DV

DD

. f

CLK IN

= 2.4576␣ MHz

Digital I/Ps = 0␣ V or DV

DD.

External MCLK IN

Typically 0.15␣ mA. DV

Typically 0.3␣ mA. DV

Typically 0.4␣ mA. DV

Typically 0.6␣ mA. DV

DD

DD

DD

DD

= 3.3␣ V. f

= 5␣ V. f

= 3.3␣ V. f

= 5␣ V. f

CLK IN

CLK IN

CLK IN

CLK IN

= 1␣ MHz

= 1␣ MHz

= 2.4576␣ MHz

= 2.4576␣ MHz mW max mW max mW max mW max

AV

DD

= DV

DD

= +3.3␣ V. Digital I/Ps = 0␣ V or DV

DD

. External MCLK IN

Typically 1.25␣ mW. BUFFER = 0␣ V. f

Typically 2␣ mW. BUFFER = 0␣ V. f

CLK IN

Typically 1.8␣ mW. BUFFER = +3.3␣ V. f

CLK IN

= 1␣ MHz. BST Bit = 0

CLK IN

= 1␣ MHz. BST Bit = 0

= 2.4576␣ MHz. BST Bit = 0

Typically 2.6␣ mW. BUFFER = +3.3␣ V. f

CLK IN

= 2.4576␣ MHz. BST Bit = 0

AV

DD

= DV

DD

= +5␣ V. Digital I/Ps = 0␣ V or DV

DD

. External MCLK IN mW max Typically 2.5␣ mW. BUFFER = 0␣ V. f

CLK IN

= 1␣ MHz. BST Bit = 0 mW max Typically 3.5␣ mW. BUFFER = +5␣ V. f

CLK IN

= 1␣ MHz. BST Bit = 0 mW max Typically 4␣ mW. BUFFER = 0␣ V. f

CLK IN

= 2.4576␣ MHz. BST Bit = 0 mW max Typically 5␣ mW. BUFFER = +5␣ V. f

CLK IN

= 2.4576␣ MHz. BST Bit = 0

µ

A max

µ

A max

External MCLK IN = 0 V or DV

DD

. Typically 20␣

µ

A. V

External MCLK IN = 0 V or DV

DD

. Typically 5␣

µ

A. V

DD

DD

= +5 V

= +3.3 V

NOTES

15

After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.

16

These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV

DD

+ 30␣ mV or go more negative than AGND␣ –␣ 30␣ mV. The

17

18 offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

For higher gains (

8) at f

CLK␣ IN

= 2.4576␣ MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV

DD

current and power dissipation will vary depending on the crystal or resonator type (see Clocking and Oscillator Circuit section).

19

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.

20

PSRR depends on gain. For Gain of 1 : 70 dB typ: For Gain of 2 : 75 dB typ; For Gain of 4 : 80 dB typ; For Gains of 8 to 128 : 85 dB typ.

21

If the external master clock continues to run in standby mode, the standby current increases to 150

µ

A typical with 5 V supplies and 75

µ

A typical with 3.3 V supplies. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see Standby Mode section).

Specifications subject to change without notice.

–4– REV. C

AD7714

AD7714Y–SPECIFICATIONS

(AV

DD

= DV

DD

= +2.7␣ V to +3.3␣ V or 4.75 V to 5.25 V, REF IN(+) = +1.25␣ V; with AV

DD

= 3 V and +2.5 V with AV

DD

= 5 V; REF␣ IN(–) = AGND; MCLK IN = 2.4576␣ MHz unless otherwise noted. All specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter

STATIC PERFORMANCE

No Missing Codes

Output Noise

Integral Nonlinearity

Unipolar Offset Error

Unipolar Offset Drift

Bipolar Zero Error

Bipolar Zero Drift

Positive Full-Scale Error

Full-Scale Drift

Gain Error

Gain Drift

6

3, 7

3, 5

3

3

4

Bipolar Negative Full-Scale Error

Bipolar Negative Full-Scale Drift

3

2

ANALOG INPUTS/REFERENCE INPUTS

Input Common-Mode Rejection (CMR)

8

Normal-Mode 50 Hz Rejection

8

Normal-Mode 60 Hz Rejection

8

Common-Mode 50 Hz Rejection

8

Common-Mode 60 Hz Rejection

8

Absolute/Common-Mode REF IN Voltage

8

Absolute/Common-Mode AIN Voltage

8,

Absolute/Common-Mode AIN Voltage

AIN DC Input Current

8

AIN Sampling Capacitance

AIN Differential Voltage Range

AIN Input Sampling Rate, f

8

S

10

9

8, 9

Y Versions

Reference Input Range

REF IN(+) – REF IN(–) Voltage

REF IN(+) – REF IN(–) Voltage

REF IN Input Sampling Rate, f

S

LOGIC INPUTS

Input Current

All Inputs Except MCLK IN

V

INL

, Input Low Voltage

1/1.75

1/3.5

f

CLK IN

/64

±

10

V

INH

, Input High Voltage

0.8

0.4

2.4

2

SCLK & DIN Only (Schmitt Triggered Input)

V

T+

V

T–

V

T+

– V

T–

SCLK & DIN Only (Schmitt Triggered Input)

V

T+

V

T–

V

T+

– V

T–

MCLK In Only

V

INL

, Input Low Voltage

V

INH

, Input High Voltage

MCLK In Only

V

INL

, Input Low Voltage

V

INH

, Input High Voltage

LOGIC OUTPUTS (Including MCLK OUT)

V

OL

, Output Low Voltage

V

OL

, Output Low Voltage

V

OH

, Output High Voltage

1.4/3

0.8/1.4

0.4/0.8

1/2.5

0.4/1.1

0.375/0.8

0.8

3.5

0.4

2.5

0.4

0.4

4

1

Units Conditions/Comments

24

22

18

15

12

See Tables I to IV

±

0.001

See Note 2

0.4

0.1

See Note 2

0.4

0.1

See Note 2

0.4

0.1

See Note 2

0.2

Bits min

Bits min

Bits min

Bits min

Bits min

Guaranteed by Design. For Filter Notches

60 Hz

For Filter Notch = 100 Hz

For Filter Notch = 250 Hz

For Filter Notch = 500 Hz

For Filter Notch = 1 kHz

Depends on Filter Cutoffs and Selected Gain

% of FSR max Filter Notches

60 Hz.

µ

µ

µ

µ

µ

µ

V/

V/

V/

V/

V/

V/

°

°

°

°

°

°

C typ

C typ

C typ

C typ

C typ

C typ

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

For Gains of 1, 2, 4

For Gains of 8, 16, 32, 64, 128

±

±

1

0.0015

0.003

0.6

90

100

100

150 ppm of FSR/

°

C typ

% of FSR max AV

DD

= 5 V. Typically

±

0.0004%

% of FSR max AV

DD

= 3 V. Typically

±

0.0004%

µ

V/

°

C typ

µ

V/

°

C typ

For Gains of 1 to 4

For Gains of 8 to 128 dB min dB min dB min dB min

150

AGND to AV

DD

1

7

0 to +V

REF

/GAIN

11

±

V

REF

/GAIN

GAIN

×

f

CLK␣ IN

/64 f

CLK␣ IN

/8 dB min

V min to V max

AGND – 30 mV V min

AV

DD

+ 30 mV V max

AGND + 50 mV V min

AV

DD

– 1.5 V V max nA max pF max nom nom

Specifications for AIN and REF IN Unless Noted

At DC. Typically 102 dB.

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

±

0.02

×

f

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

±

0.02

×

f

NOTCH

For Filter Notches of 10 Hz, 25 Hz, 50 Hz,

±

0.02

×

f

NOTCH

For Filter Notches of 10 Hz, 30 Hz, 60 Hz,

±

0.02

×

f

NOTCH

NOTCH

BUF Bit of Setup Register = 0

BUF Bit of Setup Register = 1

Unipolar Input Range (B/U Bit of Filter High Register = 1)

Bipolar Input Range (B/U Bit of Filter High Register = 0)

For Gains of 1 to 4

For Gains of 8 to 128

V min/max

V min/max

µ

A max

V max

V max

V min

V min

V min/V max

V min/V max

V min/V max

V min/V max

V min/V max

V min/V max

V max

V min

V max

V min

V max

V max

V min

I

I

AV

AV

DV

DV

DV

DV

DD

= 2.7 V to 3.3 V. V

REF

= 1.25

±

1% for Specified Performance

DD

= 4.75 V to 5.25 V. V

REF

= 2.5

±

1% for Specified Performance

DD

DV

DD

DV

DD

DV

DV

DD

DD

DD

DD

DD

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V NOMINAL

= 3 V NOMINAL

= 5 V NOMINAL

= 3 V NOMINAL

SINK

= 800␣

µ

A with DV

SINK

= 100␣

µ

A with DV

DD

= 5 V. Except for MCLK OUT

DD

= 3 V. Except for MCLK OUT

I

SOURCE

= 200

µ

A with DV

DD

12

12

= 5 V. Except for MCLK OUT

12

REV. C

–5–

AD7714Y

Parameter Y Versions Units Conditions/Comments

LOGIC OUTPUTS (Continued))

V

OH

, Output High Voltage

Floating State Leakage Current

Floating State Output Capacitance

13

D ata Output Coding

DV

DD

±

10

– 0.6

9

Binary

Offset Binary

V min

µ

A max pF typ

I

SOURCE

= 100

µ

A with DV

Unipolar Mode

Bipolar Mode

DD

= 3 V. Except for MCLK OUT

12

TRANSDUCER BURNOUT

14

Current

Initial Tolerance

Drift

1

±

10

0.1

µ

A nom

% typ

%/

°

C typ

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit

Negative Full-Scale Calibration Limit

Offset Calibration Limit

Input Span

16

16

15

15

(1.05

×

V

–(1.05

×

REF

V

)/GAIN V max

REF

)/GAIN V max

–(1.05

×

V

REF

)/GAIN V max

0.8

×

V

REF

/GAIN V min

(2.1

×

V

REF

)/GAIN V max

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

GAIN Is the Selected PGA Gain (Between 1 and 128)

POWER REQUIREMENTS

Power Supply Voltages

AV

AV

DV

DD

DD

DD

Voltage

DV

DD

Voltage

Power Supply Currents

Current

Current

18

Power Supply Rejection

19

Normal-Mode Power Dissipation

Normal-Mode Power Dissipation

Standby (Power-Down) Current

Standby (Power-Down) Current

18

21

21

+2.7 to +3.3 or

+4.75 to +5.25

+2.7 to +5.25

0.28

0.6

0.5

1.1

0.080

0.16

0.18

0.35

See Note 20

1.05

2.04

1.35

2.34

2.1

3.75

3.1

4.75

18

10

V

V

V

For Specified Performance

For Specified Performance

AV

DD

= 3 V or 5␣ V. BST Bit of Filter High Register = 0

17

, CLKDIS = 1 mA max Typically 0.22 mA. BUFFER = 0 V. f

CLK IN

= 1␣ MHz or 2.4576␣ MHz mA max Typically 0.45 mA. BUFFER = DV

DD

. f

CLK IN

= 1␣ MHz or 2.4576␣ MHz

AV

DD

= 3 V or 5␣ V. BST Bit of Filter High Register = 1

17 mA max Typically 0.38␣ mA. BUFFER = 0␣ V. f

CLK IN

= 2.4576␣ MHz mA max Typically 0.8␣ mA. BUFFER = DV

DD

. f

CLK IN

= 2.4576␣ MHz mA max

Digital I/Ps = 0␣ V or DV

DD.

External MCLK IN, CLKDIS = 1

Typically 0.06␣ mA. DV

DD

= 3 V. f

CLK IN

= 1␣ MHz mA max Typically 0.13␣ mA. DV

DD

= 5␣ V. f

CLK IN

= 1␣ MHz mA max Typically 0.15␣ mA. DV

DD

= 3 V. f

CLK IN

= 2.4576␣ MHz mA max Typically 0.3 mA. DV

DD

= 5␣ V. f

CLK IN

= 2.4576␣ MHz dB typ

AV

DD

= DV

DD

= +3 V. Digital I/Ps = 0␣ V or DV

BST Bit of Filter High Register = 0

17

DD

. External MCLK IN mW max Typically 0.84␣ mW. BUFFER = 0␣ V. f

CLK IN

= 1␣ MHz. BST Bit = 0 mW max Typically 1.53␣ mW. BUFFER = +3 V. f

CLK IN

= 1␣ MHz. BST Bit = 0 mW max Typically 1.11␣ mW. BUFFER = 0␣ V. f

CLK IN

= 2.4576␣ MHz. BST Bit = 0 mW max Typically 1.9␣ mW. BUFFER = +3 V. f

CLK IN

= 2.4576␣ MHz. BST Bit = 0

AV

DD

= DV

DD

= +5␣ V. Digital I/Ps = 0␣ V or DV

DD

. External MCLK IN mW max Typically 1.75 mW. BUFFER = 0␣ V. f

CLK IN

= 1␣ MHz. BST Bit = 0 mW max Typically 2.9 mW. BUFFER = +5␣ V. f

CLK IN

= 1␣ MHz. BST Bit = 0 mW max Typically 2.6␣ mW. BUFFER = 0␣ V. f

CLK IN

= 2.4576␣ MHz. BST Bit = 0 mW max Typically 3.75␣ mW. BUFFER = +5␣ V. f

µ

A max External MCLK IN = 0 V or DV

DD

CLK IN

= 2.4576␣ MHz. BST Bit = 0

. Typically 9␣

µ

A. V

DD

= +5 V

µ

A max External MCLK IN = 0 V or DV

DD

. Typically 4␣

µ

A. V

DD

= +3 V

NOTES

1

2

Temperature range is as follows: Y Version: –40

°

C to +105

°

C.

A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.

3

Recalibration at any temperature will remove these drift errors.

4

Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.

5

Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

6

Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for bipolar ranges.

7

Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.

8

9

10

These numbers are guaranteed by design and/or characterization.

The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.

The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which

11 inputs form differential pairs.

V

REF

= REF IN(+) – REF IN(–).

12

These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.

13

Sample tested at +25

°

C to ensure compliance.

14

See Burnout Current section.

15

After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.

16

These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV

DD

+ 30␣ mV or go more negative than AGND␣ –␣ 30␣ mV. The offset calibration

17 limit applies to both the unipolar zero point and the bipolar zero point.

For higher gains (

8) at f

CLK␣ IN

= 2.4576␣ MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.

18

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV

DD

current and power dissipation will vary depending on the crystal or resonator type (see Clocking and Oscillator Circuit section).

19

Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.

20

PSRR depends on gain.

Gain

AV

DD

= 3 V

AV

DD

= 5 V

1

86 dB

90 dB

2

78 dB

78 dB

4

85 dB

84 dB

8–128

93 dB

91 dB

21

If the external master clock continues to run in standby mode, the standby current increases to 150

µ

A typical with 5 V supplies and 75

µ

A typical with 3.3 V supplies. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see Standby Mode section).

Specifications subject to change without notice.

–6– REV. C

AD7714

TIMING CHARACTERISTICS

1, 2

(AV

DD

= DV

DD

= +2.7 V to +5.25 V; AGND = DGND = 0 V; f

CLKIN

= 2.5␣ MHz; Input Logic 0 = 0 V,

Logic 1 = DV

DD

unless otherwise noted.)

f

Parameter

CLKIN

3, 4 t

6 t

7 t t

8

9

7 t

CLK IN LO t

CLK IN HI t

DRDY t

1 t

2

Read Operation t

3 t t

4

5

6

Limit at T

MIN

, T

MAX

(A, Y Versions)

400

2.5

0.4

0.4

×

×

t

t

500

×

t

100

100

CLK IN

CLK IN

CLK IN

Units

kHz min

MHz max ns min ns min ns nom ns min ns min

Conditions/Comments

Master Clock Frequency: Crystal/Resonator or Externally

Supplied

For Specified Performance

Master Clock Input Low Time. t

CLK IN

= 1/f

CLK IN

Master Clock Input High Time

DRDY High Time

SYNC Pulsewidth

RESET Pulsewidth

0

30

20

100

100

0

0

0

0

80

100

100

100

0

10

60

100

100 ns min ns min ns min ns max ns max ns min ns min ns min ns min ns max ns max ns max ns min ns min ns min ns min ns min ns min

DRDY to CS Setup Time

CS Falling Edge to SCLK Active Edge Setup Time

5

SCLK Active Edge to Data Valid Delay

5

DV

DD

= +5␣ V

DV

DD

= +3␣ V

SCLK High Pulsewidth

SCLK Low Pulsewidth

CS Rising Edge to SCLK Active Edge Hold Time

5

Bus Relinquish Time after SCLK Active Edge

5

DV

DD

= +5␣ V

DV

DD

= +3␣ V

SCLK Active Edge to

DRDY High

5, 8 t

10

Write Operation t

11 t

12 t

13 t

14 t

15 t

16

CS Falling Edge to SCLK Active Edge Setup Time

Data Valid to SCLK Edge Setup Time

Data Valid to SCLK Edge Hold Time

SCLK High Pulsewidth

SCLK Low Pulsewidth

CS Rising Edge to SCLK Edge Hold Time

5

NOTES

1

Sample tested at +25

°

C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV

2

See Figures 6 and 7. Timing applies for all grades.

DD

) and timed from a voltage level of 1.6 V.

3

CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated.

4

The AD7714 is production tested with f

CLKIN

at 2.4576␣ MHz (1␣ MHz for some I

DD

tests). It is guaranteed by characterization to operate at 400␣ kHz.

5

SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.

6

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V

OL

or V

OH

limits.

7

These numbers are derived from the measured time taken by the data output to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

8 relinquish times of the part and as such are independent of external bus loading capacitances.

DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care should be taken that subsequent reads do not occur close to the next output update.

Specifications subject to change without notice.

ORDERING GUIDE

TO OUTPUT

PIN

Figure 1. Load Circuit for Access Time and Bus

Relinquish Time

REV. C

50pF

I

SINK

(800

m

A AT DV

DD

= +5V

100

m

A AT DV

DD

= +3.3V)

+1.6V

I

SOURCE

(200

m

A AT DV

DD

= +5V

100

m

A AT DV

DD

= +3.3V)

–7–

Model

AV

DD

Temperature

Supply Range

Package

Option*

AD7714AN-5

AD7714AR-5

AD7714ARS-5

AD7714AN-3

AD7714AR-3

AD7714ARS-3

AD7714YN

AD7714YR

AD7714YRU

AD7714AChips-5

AD7714AChips-3

5 V

5 V

5 V

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

N-24

R-24

RS-28

3 V

3 V

3 V

–40

°

C to +85

°

C

–40

°

C to +85

°

C

N-24

R-24

RS-28

3 V/5 V –40

°

C to +105

°

C N-24

3 V/5 V –40

°

C to +105

°

C R-24

3 V/5 V –40

°

C to +105

°

C RU-24

5 V

3 V

–40

°

C to +85

°

C

–40

°

C to +85

°

C

Die

Die

EVAL-AD7714-5EB 5 V Evaluation Board

EVAL-AD7714-3EB 3 V Evaluation Board

*N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline.

2

AD7714

ABSOLUTE MAXIMUM RATINGS*

(T

A

= +25

°

C unless otherwise noted)

AV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

DV

DD

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

DV

DD

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7␣ V

Analog Input Voltage to AGND . . . . . –0.3 V to AV

DD

+ 0.3␣ V

Reference Input Voltage to AGND . . . –0.3 V to AV

DD

+ 0.3␣ V

Digital Input Voltage to DGND . . . . . –0.3 V to DV

DD

+ 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to DV

DD

+ 0.3 V

Operating Temperature Range

Commercial (A Version) . . . . . . . . . . . . . . . –40

°

C to +85

°

C

Extended (Y Version) . . . . . . . . . . . . . . . . . –40

°

C to +105

°

C

Storage Temperature Range . . . . . . . . . . . . . –65

°

C to +150

°

C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150

°

C

Plastic DIP Package, Power Dissipation . . . . . . . . . . . 450 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105

°

C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +260

°

C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75

°

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

°

C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

°

C

SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 109

°

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

°

C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

°

C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128

°

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

°

C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

°

C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.

Although these devices feature proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

DIP and SOIC/TSSOP

PIN CONFIGURATIONS

SSOP

WARNING!

ESD SENSITIVE DEVICE

SCLK

MCLK IN

MCLK OUT

POL

SYNC

RESET

AIN1

AIN2

AIN3

AIN4

STANDBY

AV

DD

AD7714

TOP VIEW

(Not to Scale)

DGND

DV

DD

DIN

DOUT

DRDY

CS

AGND

AIN6

AIN5

REF IN(+)

REF IN(–)

BUFFER

SCLK

MCLK IN

MCLK OUT

POL

SYNC

RESET

NC

NC

AIN1

AIN2

AIN3

AIN4

STANDBY

AV

DD

AD7714

TOP VIEW

(Not to Scale)

DGND

DV

DD

DIN

DOUT

DRDY

CS

NC

NC

AGND

AIN6

AIN5

REF IN(+)

REF IN(–)

BUFFER

NC = NO CONNECT

–8– REV. C

AD7714

PIN FUNCTION DESCRIPTION

DIP/SOIC PIN NUMBERS

Pin

No. Mnemonic Function

1

2

SCLK Serial Clock. Logic Input. An external serial clock is applied to this input to access serial data from the

AD7714. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses.

Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7714 in smaller batches of data.

MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with clock input frequencies of both 1 MHz and 2.4576 MHz.

MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK 3

4

5

6

7

POL

SYNC

RESET

AIN1

IN and MCLK␣ OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuits.

Clock Polarity. Logic Input. With this input low, the first transition of the serial clock in a data transfer operation is from a low to a high. In microcontroller applications, this means that the serial clock should idle low between data transfers. With this input high, the first transition of the serial clock in a data transfer operation is from a high to a low. In microcontroller applications, this means that the serial clock should idle high between data transfers.

Logic Input which allows for synchronization of the digital filters and analog modulators when using a number of AD7714s. While

SYNC is low, the nodes of the digital filter, the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state.

SYNC does not affect the digital interface and does not reset

DRDY if it is low.

Logic Input. Active low input which resets the control logic, interface logic, digital filter and analog modulator of the part to power-on status.

Analog Input Channel 1. Programmable-gain analog input which can be used as a pseudo-differential input when used with AIN6 or as the positive input of a differential analog input pair when used with AIN2 (see

Communications Register section).

8

9

AIN2

AIN3

Analog Input Channel 2. Programmable-gain analog input which can be used as a pseudo-differential input when used with AIN6 or as the negative input of a differential analog input pair when used with AIN1 (see

Communications Register section).

Analog Input Channel 3. Programmable-gain analog input which can be used as a pseudo-differential input when used with AIN6 or as the positive input of a differential analog input pair when used with AIN4 (see

Communications Register section).

10 AIN4 Analog Input Channel 4. Programmable-gain analog input which can be used as a pseudo-differential input when used with AIN6 or as the negative input of a differential analog input pair when used with AIN3 (see

Communications Register section).

11

STANDBY

Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to typically 5

µ

A.

12 AV

DD

Analog Positive Supply Voltage, A Grade Versions: +3.3␣ V nominal (AD7714-3) or +5␣ V nominal (AD7714-5);

Y Grade Versions: 3 V or 5 V nominal.

13 BUFFER Buffer Option Select. Logic Input. With this input low, the on-chip buffer on the analog input (after the multiplexer and before the analog modulator) is shorted out. With the buffer shorted out the current flowing in the AV

DD

line is reduced to 270

µ

A. With this input high, the on-chip buffer is in series with the analog input allowing the inputs to handle higher source impedances.

14 REF IN(–) Reference Input. Negative input of the differential reference input to the AD7714. The REF IN(–) can lie anywhere between AV

DD

and AGND provided REF␣ IN(+) is greater than REF IN(–).

15 REF IN(+) Reference Input. Positive input of the differential reference input to the AD7714. The reference input is

16 AIN5 differential with the provision that REF IN(+) must be greater than REF IN(–). REF IN(+) can lie anywhere between AV

DD

and AGND.

Analog Input Channel 5. Programmable-gain analog input which is the positive input of a differential analog input pair when used with AIN6 (see Communications Register section).

17 AIN6

18 AGND

Analog Input Channel 6. Reference point for AIN1 through AIN4 in pseudo-differential mode or as the negative input of a differential input pair when used with AIN5 (see Communications Register section).

Ground reference point for analog circuitry.

REV. C

–9–

2

AD7714

PIN FUNCTION DESCRIPTION (Continued)

Pin

No. Mnemonic Function

19

CS

20

21

22

23

24

DRDY

DOUT

DIN

DV

DD

DGND

Chip Select. Active low Logic Input used to select the AD7714. With this input hard-wired low, the AD7714 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device.

CS

can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7714.

Logic output. A logic low on this output indicates that a new output word is available from the AD7714 data register. The

DRDY pin will return high upon completion of a read operation of a full output word. If no data read has taken place, after an output update, the

DRDY line will return high for 500

×

t

CLK␣ IN

cycles prior to the next output update. This gives an indication of when a read operation should not be attempted to avoid reading from the data register as it is being updated.

DRDY is also used to indicate when the AD7714 has completed its on-chip calibration sequence.

Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from the calibration registers, mode register, communications register, filter selection registers or data register depending on the register selection bits of the Communications Register.

Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift register is transferred to the calibration registers, mode register, communications register or filter selection registers depending on the register selection bits of the Communications Register.

Digital Supply Voltage, A Grade Versions: +3.3␣ V or +5 V nominal; Y Grade Versions: 3 V or 5 V nominal.

Ground reference point for digital circuitry.

TERMINOLOGY*

INTEGRAL NONLINEARITY

This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 LSB below the first code transition (000 . . . 000 to 000 . . . 001) and full scale, a point

0.5 LSB above the last code transition (111 . . . 110 to

111 . . . 111). The error is expressed as a percentage of full scale.

POSITIVE FULL-SCALE ERROR

Positive Full-Scale Error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage

(AIN(–) + V

REF

/GAIN – 3/2 LSBs). It applies to both unipolar and bipolar analog input ranges.

UNIPOLAR OFFSET ERROR

Unipolar Offset Error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when operating in the unipolar mode.

BIPOLAR ZERO ERROR

This is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) –

0.5 LSB) when operating in the bipolar mode.

GAIN ERROR

This is a measure of the span error of the ADC. It includes fullscale errors but not zero-scale errors. For unipolar input ranges it is defined as (full-scale error – unipolar offset error) while for bipolar input ranges it is defined as (full-scale error – bipolar zero error).

BIPOLAR NEGATIVE FULL-SCALE ERROR

This is the deviation of the first code transition from the ideal

AIN(+) voltage (AIN(–) – V

REF

/GAIN + 0.5␣ LSB) when operating in the bipolar mode.

POSITIVE FULL-SCALE OVERRANGE

Positive Full-Scale Overrange is the amount of overhead available to handle input voltages on AIN(+) input greater than

AIN(–) + V

REF

/GAIN (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modulator or overflowing the digital filter.

NEGATIVE FULL-SCALE OVERRANGE

This is the amount of overhead available to handle voltages on

AIN(+) below AIN(–) – V

REF

/GAIN without overloading the analog modulator or overflowing the digital filter. Note that the analog input will accept negative voltage peaks even in the unipolar mode provided that AIN(+) is greater than AIN(–) and greater than AGND – 30␣ mV.

OFFSET CALIBRATION RANGE

In the system calibration modes, the AD7714 calibrates its offset with respect to the analog input. The Offset Calibration

Range specification defines the range of voltages that the

AD7714 can accept and still calibrate offset accurately.

FULL-SCALE CALIBRATION RANGE

This is the range of voltages that the AD7714 can accept in the system calibration mode and still calibrate full scale correctly.

INPUT SPAN

In system calibration schemes, two voltages applied in sequence to the AD7714’s analog input define the analog input range.

The input span specification defines the minimum and maximum input voltages from zero to full scale that the AD7714 can accept and still calibrate gain accurately.

*AIN(–) refers to the negative input of the differential input pairs or to AIN6 when referring to the pseudo-differential input configurations.

–10– REV. C

AD7714

AD7714-5 OUTPUT NOISE

Table Ia shows the output rms noise and effective resolution for some typical notch and –3␣ dB frequencies for the AD7714-5 with f

CLK␣ IN

= 2.4576␣ MHz while Table Ib gives the information for f

CLK IN

= 1␣ MHz. The numbers given are for the bipolar input ranges with a V

REF

of +2.5␣ V and with BUFFER = 0. These numbers are typical and are generated at an analog input voltage of 0␣ V. The numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5␣ LSB). The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale (i.e.,

2 ×

V

REF

/GAIN

).

It should be noted that it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as quoted in the tables.

The output noise from the part comes from two sources. The first is the electrical noise in the semiconductor devices used in the implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quantization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter notch settings (below 100␣ Hz approximately for f

CLK IN

= 2.4576␣ MHz and below 40␣ Hz approximately for f

CLK IN

= 1␣ MHz) tend to be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff frequency in the quantization-noise dominated region results in a more dramatic improvement in noise performance than it does in the device-noise dominated region as shown in Table I. Furthermore, quantization noise is added after the PGA, so effective resolution is largely independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, therefore, effective resolution reduces at high gains for lower notch frequencies. Additionally, in the device-noise dominated region, the output noise (in

µ

V) is largely independent of reference voltage while in the quantization-noise dominated region, the noise is proportional to the value of the reference. It is possible to do post-filtering on the device to improve the output data rate for a given

–3␣ dB frequency and also to further reduce the output noise.

At the lower filter notch settings (below 60␣ Hz for f

CLK IN

= 2.4576␣ MHz and below 25␣ Hz for f

CLK IN

= 1␣ MHz), the no missing codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1␣ kHz notch setting for f

CLK␣ IN

= 2.4576␣ MHz (400␣ Hz for f

CLK IN

= 1␣ MHz), no missing codes performance is only guaranteed to the 12-bit level.

Table Ia. AD7714-5 Output Noise/Resolution vs. Gain and First Notch for f

CLK IN

= 2.4576␣ MHz, BUFFER = 0

Filter First

Notch & O/P –3␣ dB

Data Rate Frequency

5␣ Hz

10␣ Hz

25␣ Hz

30␣ Hz

50␣ Hz

60␣ Hz

100␣ Hz

250␣ Hz

500␣ Hz

1␣ kHz

1.31␣ Hz

2.62␣ Hz

6.55␣ Hz

7.86␣ Hz

Gain of

1 2

Typical Output RMS Noise in

Gain of Gain of

4

Gain of

8

V (Effective Resolution in Bits)

Gain of

16

Gain of

32

Gain of

64

Gain of

128

0.87

(22.5) 0.48

(22.5) 0.24 (22.5) 0.2

(21.5) 0.18 (20.5) 0.17 (20) 0.17 (19) 0.17 (18)

1.0

(22.5) 0.78

(21.5) 0.48 (21.5) 0.33 (21) 0.25 (20.5) 0.25 (19.5) 0.25 (18.5) 0.25 (17.5)

1.8

(21.5) 1.1

(21) 0.63 (21) 0.5

(20) 0.44 (19.5) 0.41 (18.5) 0.38 (17.5) 0.38 (16.5)

2.5

(21) 1.31

(21) 0.84 (20.5) 0.57 (20) 0.46 (19.5) 0.43 (18.5) 0.4

(17.5) 0.4

(16.5)

13.1␣ Hz 4.33

(20) 2.06

(20) 1.2

(20) 0.64 (20) 0.54 (19) 0.46 (18.5) 0.46 (17.5) 0.46 (16.5)

15.72␣ Hz 5.28

(20) 2.36

(20) 1.33 (20) 0.87 (19.5) 0.63 (19) 0.62 (18) 0.6

(17) 0.56 (16)

26.2␣ Hz

65.5␣ Hz

12.1

127

(18.5)

(15.5)

5.9

58

(18.5)

(15.5)

2.86 (19)

29

1.91 (18.5) 1.06 (18)

(15.5) 15.9 (15.5) 6.7

0.83 (17.5) 0.82 (16.5) 0.76 (15.5)

(15.5) 3.72 (15.5) 1.96 (15.5) 1.5

(14.5)

131␣ Hz

262␣ Hz

533 (13) 267 (13) 137 (13) 66 (13) 38 (13) 20 (13) 8.6

(13) 4.4

(13)

2,850 (11) 1,258 (11) 680 (11) 297 (11) 131 (11) 99 (10.5) 53 (10.5) 28 (10.5)

2

Table Ib. AD7714-5 Output Noise/Resolution vs. Gain and First Notch for f

CLK IN

= 1␣ MHz, BUFFER = 0

Filter First

Notch & O/P –3␣ dB

Data Rate Frequency

2␣ Hz

4␣ Hz

10␣ Hz

25 Hz

30␣ Hz

50␣ Hz

60␣ Hz

100␣ Hz

200␣ Hz

400␣ Hz

0.52␣ Hz

1.05␣ Hz

2.62␣ Hz

6.55␣ Hz

Gain of

1 2

Typical Output RMS Noise in

Gain of Gain of

4

Gain of

8

V (Effective Resolution in Bits)

Gain of

16

Gain of

32

Gain of

64

Gain of

128

0.75

(22.5) 0.56

(22) 0.31 (22) 0.19 (21.5) 0.17 (21) 0.14 (20) 0.14 (19) 0.14 (18)

1.04

(22) 0.88

(21.5) 0.45 (21.5) 0.28 (21) 0.21 (20.5) 0.21 (19.5) 0.21 (18.5) 0.21 (17.5)

1.66

(21.5) 1.01

(21.5) 0.77 (20.5) 0.41 (20.5) 0.37 (19.5) 0.35 (19) 0.35 (18) 0.35 (17)

5.2

(20) 2.06

(20) 1.4

(20) 0.86 (19.5) 0.63 (19) 0.61 (18) 0.59 (17) 0.59 (16)

7.86␣ Hz

13.1␣ Hz

7.1

(19.5) 3.28

(19.5) 1.42 (19.5) 1.07 (19) 0.78 (18.5) 0.64 (18) 0.61 (17) 0.61 (16)

19.4

(18) 9.11

(18) 4.2

(18) 2.45 (18) 1.56 (17.5) 1.1

(17) 0.82 (16.5) 0.8

(15.5)

15.72␣ Hz 25

26.2␣ Hz 102

(17.5)

(15.5)

16

58

(17.5)

(15.5)

6.5

25

(17.5)

(15.5)

2.9

(17.5) 1.93 (17.5) 1.4

13.5 (15.5) 5.7

(15.5) 3.9

(17) 1.1

(15.5) 2.1

(16)

(15)

0.98 (15.5)

1.3

(15)

52.4␣ Hz 637 (13) 259 (13) 130 (13) 76 (13) 33 (13) 16 (13) 11 (13) 6 (12.5)

104.8␣ Hz 2,830 (11) 1,430 (11) 720 (11) 334 (11) 220 (10.5) 94 (10.5) 54 (10.5) 25 (10.5)

REV. C

–11–

AD7714

AD7714-3 OUTPUT NOISE

Table IIa shows the output rms noise and effective resolution for some typical notch and –3␣ dB frequencies for the AD7714-3 with f

CLK␣ IN

= 2.4576␣ MHz while Table IIb gives the information for f

CLK IN

= 1␣ MHz. The numbers given are for the bipolar input ranges with a V

REF

of +1.25␣ V and BUFFER = 0. These numbers are typical and are generated at an analog input voltage of 0␣ V.

The numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5␣ LSB). The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale (i.e., 2

×

V

REF

/GAIN). It should be noted that it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as quoted in the tables.

The output noise from the part comes from two sources. The first is the electrical noise in the semiconductor devices used in the implementation of the modulator (device noise). Secondly, when the analog input signal is converted into the digital domain, quantization noise is added. The device noise is at a low level and is largely independent of frequency. The quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. Consequently, lower filter notch settings (below 100␣ Hz approximately for f

CLK IN

= 2.4576␣ MHz and below 40␣ Hz approximately for f

CLK IN

= 1␣ MHz) tend to be device noise dominated while higher notch settings are dominated by quantization noise. Changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement in noise performance than it does in the device-noise dominated region as shown in Table II. Furthermore, quantization noise is added after the PGA, so effective resolution is largely independent of gain for the higher filter notch frequencies. Meanwhile, device noise is added in the PGA and, therefore, effective resolution suffers a little at high gains for lower notch frequencies. Additionally, in the device-noise dominated region, the output noise (in

µ

V) is largely independent of reference voltage while in the quantization-noise dominated region, the noise is proportional to the value of the reference. It is possible to do post-filtering on the device to improve the output data rate for a given

–3␣ dB frequency and also to further reduce the output noise.

At the lower filter notch settings (below 60␣ Hz for f

CLK IN

= 2.4576␣ MHz and below 25␣ Hz for f

CLK IN

= 1␣ MHz), the no missing codes performance of the device is at the 24-bit level. At the higher settings, more codes will be missed until at 1␣ kHz notch setting for f

CLK␣ IN

= 2.4576␣ MHz (400␣ Hz for f

CLK IN

= 1␣ MHz), no missing codes performance is only guaranteed to the 12-bit level.

Table IIa. AD7714-3 Output Noise/Resolution vs. Gain and First Notch for f

CLK IN

= 2.4576␣ MHz, BUFFER = 0

Filter First

Notch & O/P –3␣ dB

Data Rate Frequency

5␣ Hz

10␣ Hz

25␣ Hz

30␣ Hz

50␣ Hz

60␣ Hz

100␣ Hz

250␣ Hz

500␣ Hz

1␣ kHz

1.31␣ Hz

2.62␣ Hz

6.55␣ Hz

7.86␣ Hz

Gain of

1 2

Typical Output RMS Noise in

Gain of Gain of

4

Gain of

8

V (Effective Resolution in Bits)

Gain of

16

Gain of

32

Gain of

64

Gain of

128

1.07

(21) 0.68

(21) 0.29 (21) 0.24 (20) 0.22 (19.5) 0.22 (18.5) 0.22 (17.5) 0.22 (16.5)

1.69

(20.5) 1.1

(20) 0.56 (20) 0.35 (19.5) 0.33 (19) 0.33 (18) 0.33 (17) 0.33 (16)

3.03

(19.5) 1.7

(19.5) 0.89 (19.5) 0.55 (19) 0.49 (18.5) 0.46 (17.5) 0.46 (16.5) 0.45 (15.5)

3.55

(19.5) 2.1

(19) 1.1

(19) 0.61 (18.5) 0.58 (18) 0.57 (17) 0.55 (16) 0.55 (15)

13.1␣ Hz 4.72

(19) 2.3

(19) 1.5

(18.5) 0.84 (18.5) 0.7

(18) 0.68 (17) 0.67 (16) 0.66 (15)

15.72␣ Hz 5.12

(19) 3.1

(18.5) 1.6

(18) 0.98 (18) 0.9

(17.5) 0.7

(17) 0.69 (16) 0.68 (15)

26.2␣ Hz

65.5␣ Hz

9.68

44

(18)

(16)

5.6

31

(18)

(15.5)

2.4

15

(18)

(15.5)

1.3

5.8

(18) 1.1

(15.5) 3.7

(17) 0.95 (16.5) 0.88 (15.5) 0.9

(15.5) 2.4

(15) 1.8

(14.5) 1.8

(14.5)

(13.5)

131␣ Hz

262␣ Hz

304 (13) 129 (13) 76 (13) 33 (13) 20 (13) 11 (13) 6.3

(12.5) 3 (12.5)

1410 (11) 715 (11) 350 (11) 177 (11) 101 (10.5) 51 (10.5) 31 (10.5) 12 (10.5)

Table IIb. AD7714-3 Output Noise/Resolution vs. Gain and First Notch for f

CLK IN

= 1␣ MHz, BUFFER = 0

Filter First

Notch & O/P –3␣ dB

Data Rate Frequency

2␣ Hz

4␣ Hz

10␣ Hz

25␣ Hz

30␣ Hz

50␣ Hz

60␣ Hz

100␣ Hz

200␣ Hz

400 Hz

0.52␣ Hz

1.05␣ Hz

2.62␣ Hz

6.55␣ Hz

Gain of

1 2

Typical Output RMS Noise in

Gain of Gain of

4

Gain of

8

V (Effective Resolution in Bits)

Gain of

16

Gain of

32

Gain of

64

Gain of

128

0.86

(21.5) 0.58

(21) 0.32 (21) 0.21 (20.5) 0.2

(19.5) 0.2

(18.5) 0.2

(17.5) 0.2

(16.5)

1.26

(21) 0.74

(20.5) 0.44 (20.5) 0.35 (20) 0.3

(19) 0.3

(18) 0.3

(17) 0.3

(16)

1.68

(20.5) 1.33

(20) 0.73 (20) 0.5

(19) 0.49 (18.5) 0.49 (17.5) 0.48 (16.5) 0.47 (15.5)

3.82

(19.5) 2.0

(19.5) 1.2

(19) 0.88 (18.5) 0.66 (18) 0.57 (17) 0.55 (16) 0.55 (15)

7.86␣ Hz

13.1␣ Hz

4.88

(19) 2.1

(19) 1.3

(19) 0.93 (18.5) 0.82 (17.5) 0.69 (17) 0.68 (16) 0.66 (15)

11 (18) 4.8

(18) 2.4

(18) 1.4

(18) 1.4

(17) 0.73 (16.5) 0.71 (15.5) 0.7

(15)

15.72␣ Hz 14.7

(17.5) 7.5

(17.5) 3.8

(17.5) 2.6

(17) 1.5

(16.5) 0.95 (16.5) 0.88 (15) 0.9

(14.5)

26.2␣ Hz 61 (15.5) 30 (15.5) 12 (15.5) 6.1

(15.5) 2.9

(15.5) 2.4

(15) 1.8

(14.5) 1.8

(13.5)

52.4␣ Hz 275 (13) 130 (13) 65 (13) 33 (13) 17 (13) 11 (13) 6.3

(12.5) 3 (12.5)

104.8␣ Hz 1435 (11) 720 (11) 362 (11) 175 (11) 110 (10.5) 51 (10.5) 31 (10.5) 12 (10.5)

–12– REV. C

AD7714

BUFFERED MODE NOISE

Table III shows the typical output rms noise and effective resolution for some typical notch and –3␣ dB frequencies for the AD7714-

5 with f

CLK␣ IN

= 2.4576␣ MHz and BUFFER = +5 V. Table IV gives the information for the AD7714-3 again with f

CLK IN

= 2.4576

MHz and BUFFER = +5␣ V. The numbers given are for the bipolar input ranges and are generated with a differential analog input voltage of 0␣ V. For the AD7714-5, the V

REF

voltage is +2.5␣ V while for the AD7714 the V

REF

voltage is +1.25␣ V. The numbers in brackets in each table are for the effective resolution of the part (rounded to the nearest 0.5 LSB). The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale (i.e., 2

×

V

REF

/GAIN). It should be noted that it is not calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise as quoted in the tables.

Table III. AD7714-5 Buffered Mode Output Noise/Resolution for f

CLK IN

= 2.4576␣ MHz

Filter First

Notch & O/P –3␣ dB

Data Rate Frequency

5␣ Hz

10␣ Hz

25␣ Hz

30␣ Hz

50␣ Hz

60␣ Hz

100␣ Hz

250␣ Hz

500␣ Hz

1␣ kHz

1.31␣ Hz

2.62␣ Hz

6.55␣ Hz

7.86␣ Hz

Gain of

1 2

Typical Output RMS Noise in

Gain of Gain of

4

Gain of

8

V (Effective Resolution in Bits)

Gain of

16

Gain of

32

Gain of

64

Gain of

128

0.99

(22.5) 0.68

(22) 0.46 (21.5) 0.26 (21) 0.26 (20) 0.26 (19) 0.26 (18) 0.26 (17)

1.5

(21.5) 0.95

(21.5) 0.63 (21) 0.41 (20.5) 0.39 (19.5) 0.36 (18.5) 0.36 (17.5) 0.36 (16.5)

2.5

(21) 1.7

(20.5) 0.88 (20.5) 0.75 (19.5) 0.57 (19) 0.57 (18) 0.57 (17) 0.56 (16)

2.9

(20.5) 1.8

(20.5) 1 (20) 0.87 (19.5) 0.75 (18.5) 0.72 (17.5) 0.72 (16.5) 0.71 (15.5)

13.1␣ Hz 4.2

(20) 2.5

(20) 1.5

(19.5) 1.1

(19) 0.94 (18.5) 0.94 (17.5) 0.94 (16.5) 0.87 (15.5)

15.72␣ Hz 6.1

(19.5) 2.9

(19.5) 2 (19.5) 1.2

(19) 1 (18.5) 0.97 (17.5) 0.95 (16.5) 0.94 (15.5)

26.2␣ Hz

65.5␣ Hz

13.8

87

(18.5)

(16)

6.5

56

(18.5)

(15.5)

3.5

25

(18.5) 2.2

(15.5) 11

(18) 1.3

(15.5) 5.7

(18) 1.2

(15.5) 3.6

(17) 1.3

(15.5) 2.4

(16)

(15)

1.1

2.1

(15)

(14)

131␣ Hz

262␣ Hz

508 (13.5) 241 (13.5) 117 (13.5) 73 (13) 34 (13) 16 (13) 8.5

(13) 5.2

(13)

2860 (11) 1700 (10.5) 745 (10.5) 480 (10.5) 197 (10.5) 94 (10.5) 53 (10.5) 23 (10.5)

2

Table IV. AD7714-3 Buffered Mode Output Noise/Resolution for f

CLK IN

= 2.4576␣ MHz

Filter First

Notch & O/P –3␣ dB

Data Rate Frequency

5␣ Hz

10␣ Hz

25␣ Hz

30␣ Hz

50␣ Hz

60␣ Hz

100␣ Hz

250␣ Hz

500␣ Hz

1␣ kHz

1.31␣ Hz

2.62␣ Hz

6.55␣ Hz

7.86␣ Hz

Gain of

1 2

Typical Output RMS Noise in

Gain of Gain of

4

Gain of

8

V (Effective Resolution in Bits)

Gain of

16

Gain of

32

Gain of

64

Gain of

128

1.16

(21) 0.76

(20.5) 0.34 (20) 0.29 (20) 0.29 (19) 0.28 (18) 0.26 (17) 0.26 (16)

1.7

(20.5) 1 (20.5) 0.7

(20) 0.46 (19.5) 0.45 (18.5) 0.4

(17.5) 0.4

(16.5) 0.4

(15.5)

3.5

(19.5) 1.8

(19.5) 1.1

(19) 0.74 (18.5) 0.63 (18) 0.6

(17) 0.6

(16) 0.6

(15)

3.7

(19.5) 2.2

(19) 1.3

(19) 0.76 (18.5) 0.68 (18) 0.66 (17) 0.66 (16) 0.66 (15)

13.1␣ Hz 4.5

(19) 3 (18.5) 1.7

(18.5) 1.0

(18) 0.92 (17.5) 0.9

(16.5) 0.89 (15.5) 0.89 (14.5)

15.72␣ Hz 5.3

(19) 3.3

(18.5) 1.8

(18.5) 1.1

(18) 1 (17) 0.96 (16.5) 0.96 (15.5) 0.96 (14.5)

26.2␣ Hz

65.5␣ Hz

10

47

(18)

(15.5)

4.9

29

(18)

(15.5)

3.1

15

(17.5) 1.5

(15.5) 7.5

(17.5) 1.2

(15.5) 4.7

(17)

(15)

1.2

2.6

(16)

(15)

1.2

2.5

(15)

(14)

1.2

1.6

(14)

(13.5)

131␣ Hz

262␣ Hz

300 (13.5) 171 (13) 74 (13) 35 (13) 21 (13) 8.6

(13) 5.6

(13) 3.1

(12.5)

1722 (10.5) 735 (10.5) 380 (10.5) 230 (10.5) 93 (10.5) 55 (10.5) 30 (10.5) 12 (10.5)

REV. C

–13–

AD7714

ON-CHIP REGISTERS

The AD7714 contains eight on-chip registers which can be accessed via the serial port of the part. The first of these is a Communications Register which controls the channel selection, decides whether the next operation is a read or write operation and also decides which register the next read or write operation accesses. All communications to the part must start with a write operation to the

Communications Register. After power-on or

RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the

Communications Register followed by a write to the selected register. A read operation from any other register on the part (including the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register. The communications register also controls channel selection and the

DRDY status is also available by reading from the

Communications Register. The second register is a Mode Register which determines calibration mode and gain setting. The third register is labelled the Filter High Register and this determines the word length, bipolar/unipolar operation and contains the upper 4 bits of the filter selection word. The fourth register is labelled the Filter Low Register and contains the lower 8 bits of the filter selection word. The fifth register is a Test Register which is accessed when testing the device. The sixth register is the Data Register from which the output data from the part is accessed. The final registers allow access to the part’s calibration registers. The Zero Scale

Calibration Register allows access to the zero scale calibration coefficients for the selected input channel while the Full Scale Calibration Register allows access to the full scale calibration coefficients for the selected input channel. The registers are discussed in more detail in the following sections.

Communications Register (RS2-RS0 = 0, 0, 0)

The Communications Register is an 8-bit register from which data can either be read or to which data can be written. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation and to which register this operation takes place. Once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface, and on power-up or after a

RESET, the AD7714 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, if a write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7714 returns to this default state. Table V outlines the bit designations for the Communications Register.

Table V. Communications Register

0/

DRDY

RS2 RS1 RS0 R/

W

CH2 CH1 CH0

0/

DRDY

RS2–RS0

RS2

1

1

1

1

0

0

0

0

For a write operation, a 0 must be written to this bit so that the write operation to the Communications Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits will be loaded to the

Communications Register. For a read operation, this bit provides the status of the

DRDY flag from the part. The status of this bit is the same as the

DRDY output pin.

Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which one of eight on-chip registers the next read or write operation takes place as shown in Table VI along with the register size.

RS1

1

1

0

0

1

1

0

0

RS0

0

1

0

1

0

1

0

1

Table VI. Register Selection

Register

Communications Register

Mode Register

Filter High Register

Filter Low Register

Test Register

Data Register

Zero-Scale Calibration Register

Full-Scale Calibration Register

Register Size

8 Bits

8 Bits

8 Bits

8 Bits

8 Bits

16 Bits or 24 Bits

24 Bits

24 Bits

–14– REV. C

CH2

1

1

0

1

1

0

0

0

CH2–CH0

CH1

0

1

1

0

1

0

0

1

AD7714

Channel Select. These three bits select a channel either for conversion or for access to calibration coefficients as outlined in Table VII. There are three pairs of calibration registers on the part. In fully differential mode, the part has three input channels so each channel has its own pair of calibration registers. In pseudo-differential mode, the

AD7714 has five input channels with some of the input channel combinations sharing calibration registers. With

CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself. This can be used as a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the AIN6 input should be connected to an external voltage within the allowable common-mode range for the part. The

Power-On or RESET status of these bits is 1,0,0 selecting the differential pair AIN1 and AIN2.

2

CH0

1

0

1

0

1

0

1

0

AIN(+)

AIN1

AIN2

AIN3

AIN4

AIN1

AIN3

AIN5

AIN6

Table VII. Channel Selection

AIN(–)

AIN6

AIN6

AIN6

AIN6

AIN2

AIN4

AIN6

AIN6

Type

Pseudo Differential

Pseudo Differential

Pseudo Differential

Pseudo Differential

Fully Differential

Fully Differential

Fully Differential

Test Mode

Calibration Register Pair

Register Pair 0

Register Pair 1

Register Pair 2

Register Pair 2

Register Pair 0

Register Pair 1

Register Pair 2

Register Pair 2

Mode Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 00␣ Hex

The Mode Register is an eight bit register from which data can either be read or to which data can be written. Table VIII outlines the bit designations for the Mode Register.

Table VIII. Mode Register

MD2 MD1 MD0 G2 G1 G0 BO FSYNC

MD2 MD1 MD0 Operating Mode

0

0

0

0

0

0

1

1

0

1

0

1

Normal Mode; this is the normal mode of operation of the device whereby the device is performing normal conversions. This is the default condition of these bits after Power-On or

RESET.

Self-Calibration; this activates self-calibration on the channel selected by CH2, CH1 and CH0 of the

Communications Register. This is a one step calibration sequence and when complete the part returns to

Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The

DRDY output or bit goes high when calibration is initiated and returns low when this self-calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internallygenerated V

REF

/Selected Gain.

Zero-Scale System Calibration; this activates zero scale system calibration on the channel selected by

CH2, CH1 and CH0 of the Communications Register. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The

DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Normal Mode with MD2, MD1 and

MD0 returning to 0, 0, 0.

Full-Scale System Calibration; this activates full-scale system calibration on the selected input channel.

Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. Once again, the

DRDY output or bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0.

REV. C

–15–

AD7714

MD2

1

1

1

1

BO

FSYNC

MD1 MD0 Operating Mode (continued)

0

0

1

1

0

1

0

1

System-Offset Calibration; this activates system-offset calibration on the channel selected by CH2, CH1 and CH0 of the Communications Register. This is a one step calibration sequence and when complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The

DRDY output or bit goes high when calibration is initiated and returns low when this system offset calibration is complete and a new valid word is available in the data register. For this calibration type, the zero-scale calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The full-scale calibration is performed at the selected gain on an internally generated V

REF

/Selected Gain.

Background Calibration; this activates background calibration on the channel selected by CH2, CH1 and CH0 of the Communications Register. If the background calibration mode is on, then the AD7714 provides continuous self-calibration of the shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of six.

Its major advantage is that the user does not have to worry about recalibrating the offset of the device when there is a change in the ambient temperature or supplies. In this mode, the zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs. The calibrations are interleaved with normal conversions and the calibration registers of the device are automatically updated. Because the background calibration does not perform full-scale calibrations, a self-calibration should be performed before placing the part in the background calibration mode.

Zero-Scale Self-Calibration; this activates zero-scale self-calibration on the channel selected by CH2,

CH1 and CH0 of the Communications Register. This zero-scale self-calibration is performed at the selected gain on internally shorted (zeroed) inputs. This is a one step calibration sequence and when complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The

DRDY

output or bit goes high when calibration is initiated and returns low when this zero-scale self-calibration is complete and a new valid word is available in the data register.

Full-Scale Self-Calibration; this activates full-scale self-calibration on the channel selected by CH2,

CH1 and CH0 of the Communications Register. This full-scale self-calibration is performed at the selected gain on an internally-generated V

REF

/Selected Gain. This is a one step calibration sequence and when complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The

DRDY output or bit goes high when calibration is initiated and returns low when this full-scale selfcalibration is complete and a new valid word is available in the data register.

G2

1

1

0

1

1

0

0

0

G1

0

1

1

0

1

0

0

1

G0

1

0

1

0

1

0

1

0

Gain Setting

1

2

4

8

16

32

64

128

Burnout Current. A 0 in this bit turns off the on-chip burnout currents. This is the default (Power-On or RESET) status of this bit. A 1 in this bit activates the burnout currents. When active, the burnout currents connect to the selected analog input pair, one to the AIN(+) input and one to the AIN(–) input.

Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and the calibration control logic are held in a reset state and the analog modulator is also held in its reset state. When this bit goes low, the modulator and filter start to process data and a valid word is available in 3

×

1/(output update rate), i.e., the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the

DRDY output if it is low.

–16– REV. C

AD7714

Filter Registers. Power On/Reset Status: Filter High Register: 01␣ Hex. Filter Low Register: 40␣ Hex.

There are two 8-bit Filter Registers on the AD7714 from which data can either be read or to which data can be written. Tables IX and X outline the bit designations for the Filter Registers.

Table IX. Filter High Register (RS2–RS0 = 0, 1, 0)

B/U

B/U

WL

WL

BST

BST

ZERO FS11

CLKDIS FS11

FS10

FS10

FS9

FS9

FS8

FS8

A Versions

Y Versions

FS7 FS6

Table X. Filter Low Register (RS2–RS0 = 0, 1, 1)

FS5 FS4 FS3 FS2 FS1 FS0 All Versions

B/U

WL

BST

ZERO

CLKDIS

FS11–FS0

REV. C

Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or RESET) status of this bit. A 1 in this bit selects unipolar operation.

Word Length. A 0 in this bit selects 16-bit word length when reading from the data register (i.e.,

DRDY returns high after 16 serial clock cycles in the read operation). This is the default (Power-On or RESET) status of this bit. A 1 in this bit selects 24-bit word length.

Current Boost. A 0 in this bit reduces the current taken by the analog front end. When the part is operated with f

CLK IN

= 1␣ MHz or at gains of 1 to 4 with f

CLK IN

= 2.4576␣ MHz, this bit should be 0 to reduce the current drawn from AV

DD

, although the device will operate just as well with this bit at a 1. When the AD7714 is operated at gains of 8 to 128 with f

CLK IN

= 2.4576␣ MHz, this bit must be 1 to ensure correct operation of the device. The Power-On or RESET status of this bit is 0.

To ensure correct operation of the A Versions of the part, a 0 must be written to this bit.

Master Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLKOUT pin. When disabled, the MCLKOUT pin is forced low. This feature allows the user the flexibility of using the

MCLKOUT as a clock source for other devices in the system or for turning off the MCLKOUT as a power saving feature. When using an external master clock or the MCLKIN pin, the AD7714 continues to have internal clocks and will convert normally with its CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the MCLK IN or MCLKOUT pins, the AD7714 clock is stopped and no conversions take place when the CLKDIS bit is active.

Filter Selection. The on-chip digital filter provides a Sinc

3

(or (Sinx/x)

3

) filter response. The 12 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selection, it also determines the output noise (and hence the effective resolution) of the device.

The first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency =␣ (f

CLK␣ IN

/128)/code where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 4,000. With the nominal f

CLK IN

of 2.4576␣ MHz, this results in a first notch frequency range from 4.8␣ Hz to 1.01␣ kHz. To ensure correct operation of the AD7714, the value of the code loaded to these bits must be within this range.

Failure to do this will result in unspecified operation of the device.

Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I through IV show the effect of the filter notch frequency and gain on the effective resolution of the AD7714. The output data rate

(or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50␣ Hz then a new word is available at a 50 Hz rate or every

20␣ ms. If the first notch is at 1␣ kHz, a new word is available every 1␣ ms.

The settling time of the filter to a full-scale step input change is worst case 4

×

1/(output data rate). For example, with the first filter notch at 50␣ Hz, the settling time of the filter to a full-scale step input change is

80␣ ms max. This settling time can be reduced to 3

×

1/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with the

SYNC input low or the FSYNC bit high, the settling time will be 3

×

1/(output data rate) from when

SYNC returns high or

FSYNC returns low. If a change of channel takes place, the settling time is 3

×

1/(output data rate) regardless of the

SYNC or FSYNC status as the part issues an internal SYNC command when requested to change channels.

The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency = 0.262

×

filter first notch frequency.

–17–

2

AD7714

Test Register (RS2–RS0 = 1, 0, 0)

The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the part enters one of its test modes, exercising

RESET will exit the part from the mode. An alternative scheme for getting the part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and then write all 0s to the Test Register.

Data Register (RS2–RS0 = 1, 0, 1)

The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7714. The register can be programmed to be either 16-bits or 24-bits wide, determined by the status of the WL bit of the Mode Register. If the

Communications Register data sets up the part for a write operation to this register, a write operation must actually take place in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the interface).

However, the 16 or 24 bits of data written to the part will be ignored by the AD7714.

Zero-Scale Calibration Register (RS2–RS0 = 1, 1, 0); Power On/Reset Status: 1F4000␣ Hex

The AD7714 contains three zero-scale calibration registers, labelled Zero-Scale Calibration Register 0 to Zero Scale Calibration

Register␣ 2. The three registers are totally independent of each other such that in fully differential mode there is a zero-scale register for each of the input channels. Each of these registers is a 24-bit read/write register and, when writing to the registers, 24 bits must be written; otherwise no data will be transferred to the register. The register is used in conjunction with the associated full-scale calibration register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table VII.

While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a read or write operation to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking either the

SYNC input low or the FSYNC bit of the Mode Register high before the calibration register operation and taking them either high or low respectively after the operation is complete.

Full-Scale Calibration Register (RS2–RS0 = 1, 1, 1); Power On/Reset Status: 5761AB␣ Hex

The AD7714 contains three full-scale calibration registers, labelled Full-Scale Calibration Register 0 to Full-Scale Calibration Register 2. The three registers are totally independent of each other such that in fully differential mode there is a full-scale register for each of the input channels. Each of these registers is a 24-bit read/write register and, when writing to the registers, 24 bits must be written, otherwise no data will be transferred to the register. The register is used in conjunction with the associated zero-scale calibration register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table␣ VII.

While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a read or write operation to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking either the

SYNC input low or the FSYNC bit of the Mode Register high before the calibration register operation and taking them either high or low respectively after the operation is complete.

CALIBRATION OPERATIONS

The AD7714 contains a number of calibration options as outlined previously. Table XI summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor when

DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete but also that the part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the calibration sequence. The second method of determining when calibration is complete is to monitor the MD2, MD1 and MD0 bits of the

Mode Register. When these bits return to 0, 0, 0 following a calibration command, it indicates that the calibration sequence is complete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier

indication that calibration is complete than

DRDY. The time to when the Mode Bits (MD2, MD1 and MD0) return to 0, 0, 0

represents the duration of the calibration. The sequence to when

DRDY goes low also includes a normal conversion and a pipeline delay, t

P

(2000

×

t

CLK IN

), to correctly scale the results of this first conversion. The time for both methods is given in the table.

Table XI. Calibration Operations

Calibration Type

Self Calibration

ZS System Calibration

FS System Calibration

System-Offset Calibration

Background Calibration

ZS Self Calibration

FS Self Calibration

MD2, MD1, MD0

0, 0, 1

0, 1, 0

0, 1, 1

1, 0, 0

1, 0, 1

1, 1, 0

1, 1, 1

Calibration Sequence

Internal ZS Cal @ Selected Gain +

Internal FS Cal @ Selected Gain

ZS Cal on AIN @ Selected Gain

FS Cal on AIN @ Selected Gain

ZS Cal on AIN @ Selected Gain +

Internal FS Cal @ Selected Gain

Internal ZS Cal @ Selected Gain +

Normal Conversion

Internal ZS Cal @ Selected Gain

Internal FS Cal @ Selected Gain

–18–

Duration to Mode Bits

6

×

1/Output Rate

3

×

1/Output Rate

3

×

1/Output Rate

6

×

1/Output Rate

Bits Not Reset

3

×

1/Output Rate

3

×

1/Output Rate

Duration to

DRDY

9

×

1/Output Rate + t p

4

×

1/Output Rate + t

P

4

×

1/Output Rate + t

9

×

1/Output Rate + t

P

P

6

×

1/Output Rate

6

×

1/Output Rate + t

P

6

×

1/Output Rate + t

P

REV. C

CIRCUIT DESCRIPTION

The AD7714 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, pressure transducer, industrial control or process control applications. It contains a sigma-delta (or charge-balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port. The part consumes only 500

µ

A of power supply current and features a standby mode which requires only 10

µ

A, making it ideal for battery-powered or loop-powered instruments. The part comes in two versions, the AD7714-5, which is specified for operation from a nominal +5␣ V analog supply

(AV

DD

), and the AD7714-3, which is specified for operation from a nominal +3.3␣ V analog supply. Both versions can be operated with a digital supply (DV

DD

) voltage of either +3.3␣ V or +5␣ V. AD7714Y grade parts operate with a nominal AV

DD of 3 V or 5 V and can be operated with a digital supply voltage of either 3 V or 5 V.

The part contains three programmable-gain fully differential analog input channels that can be reconfigured as five pseudodifferential inputs. The gain range on all channels is from 1 to

128, allowing the part to accept unipolar signals of between

0 mV to +20␣ mV and 0 V to +2.5␣ V. In bipolar mode, the part handles genuine bipolar signals of

±

20 mV and quasi-bipolar signals up to

±

2.5 V when the reference input voltage equals

+2.5␣ V. With a reference voltage of +1.25␣ V, the input ranges are from 0 mV to +10 mV to 0 V to +1.25␣ V in unipolar mode, while in bipolar mode, the part handles genuine bipolar signals of

±

10 mV and quasi-bipolar signals up to

±

1.25 V.

The part employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The sigma-delta

AD7714

modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. The programmable gain function on the analog input is also incorporated in this sigma-delta modulator with the input sampling frequency of the modulator being modified to give the higher gains. A sinc

3

digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the first notch frequency of this filter. The output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. The first notch of this digital filter, its –3␣ dB frequency and its output rate can be programmed via the filter high and filter low registers. With a master clock frequency of 2.4576 MHz, the programmable range for this first notch frequency and output rate is from 4.8␣ Hz to 1.01 kHz giving a programmable range for the –3␣ dB frequency of 1.26 Hz to 265␣ Hz.

The basic connection diagram for the part is shown in Figure 2.

This shows both the AV

DD

and DV

DD

pins of the AD7714 being driven from the analog +3␣ V or +5␣ V supply. Some applications will have AV

DD

and DV

DD

driven from separate supplies. In the connection diagram shown, the AD7714’s analog inputs are configured as three fully differential inputs. The part is set up for unbuffered mode on the these analog inputs. An AD780, precision +2.5 V reference, provides the reference source for the part. On the digital side, the part is configured for three-wire operation with

CS tied to DGND. A quartz crystal or ceramic resonator provides the master clock source for the part. It may be necessary to connect capacitors on the crystal or resonator to ensure that it does not oscillate at overtones of its fundamental operating frequency. The values of capacitors will vary depending on the manufacturer’s specifications.

ANALOG

+5V SUPPLY

10

m

F 0.1

m

F

0.1

m

F

2

ANALOG

+5V SUPPLY

V

IN

V

OUT

AD780

GND

DIFFERENTIAL

ANALOG INPUT 1

DIFFERENTIAL

ANALOG INPUT 2

DIFFERENTIAL

ANALOG INPUT 3

ANALOG

GROUND

DIGITAL

GROUND

10

m

F 0.1

m

F

AV

DD

AIN1

AIN2

DV

DD

DRDY

CS

AIN3

AIN4

DOUT

AIN5

AIN6

DIN

SCLK

AD7714

AGND

RESET

SYNC

DGND

STANDBY

REF IN(+)

POL

MCLK IN

REF IN(–)

MCLK OUT

BUFFER

Figure 2. Basic Connection Diagram

DATA

READY

RECEIVE

(READ)

SERIAL

DATA

SERIAL

CLOCK

+5V

CRYSTAL OR

CERAMIC

RESONATOR

REV. C

–19–

AD7714

ANALOG INPUT

Analog Input Ranges

The AD7714 contains six analog input pins (labelled AIN1 to

AIN6) which can be configured as either three fully differential input channels or five pseudo-differential input channels. Bits

CH0, CH1 and CH2 of the Communications Register configure the analog input arrangement and the channel selection is as outlined previously in Table VII. The input pairs (either differential or pseudo-differential) provide programmable-gain, input channels which can handle either unipolar or bipolar input signals. It should be noted that the bipolar input signals are referenced to the respective AIN(–) input of the input pair.

In unbuffered mode, the common-mode range of these inputs is from AGND to AV

DD

provided that the absolute value of the analog input voltage lies between AGND␣ –␣ 30␣ mV and AV

DD

+ 30␣ mV.

This means that in unbuffered mode the part can handle both unipolar and bipolar input ranges for all gains. In buffered mode, the analog inputs can handle much larger source impedances, but the absolute input voltage range is restricted to between AGND␣ + 50␣ mV to AV

DD

– 1.5␣ V which also places restrictions on the common-mode range. This means that in buffered mode there are some restrictions on the allowable gains for bipolar input ranges. Care must be taken in setting up the common-mode voltage and input voltage range so that the above limits are not exceeded, otherwise there will be a degradation in linearity performance.

In unbuffered mode, the analog inputs look directly into the

7␣ pF input sampling capacitor, C

SAMP

. The dc input leakage current in this unbuffered mode is 1␣ nA maximum. As a result, the analog inputs see a dynamic load which is switched at the input sample rate (see Figure 3). This sample rate depends on master clock frequency and selected gain. C

SAMP

is charged to

AIN(+) and discharged to AIN(–) every input sample cycle.

The effective on-resistance of the switch, R

SW

, is typically 7␣ k

.

AIN(+)

AIN(–)

R

SW

(7k

V

TYP)

C

SAMP

(7pF )

V

BIAS

SWITCHING FREQUENCY DEPENDS ON f

CLKIN

AND SELECTED GAIN

HIGH

IMPEDANCE

>1G

V

Figure 3. Unbuffered Analog Input Structure

C

SAMP

must be charged through R

SW

and through any external source impedances every input sample cycle. Therefore, in unbuffered mode, source impedances mean a longer charge time for

C

SAMP

and this may result in gain errors on the part. Table XII shows the allowable external resistance/capacitance values, for unbuffered mode, such that no gain error to the 16-bit level is introduced on the part. Table XIII shows the allowable external resistance/capacitance values, once again for unbuffered mode, such that no gain error to the 20-bit level is introduced.

Table XII. External R, C Combination for No 16-Bit Gain

Error (Unbuffered Mode Only)

Gain External Capacitance (pF)

0 50 100 500 1000 5000

1

2

4

368 k

90.6 k

54.2 k

14.6 k

8.2 k

2.2 k

177.2 k

44.2 k

26.4 k

7.2 k

4 k

1.12 k

82.8 k

21.2 k

12.6 k

3.4 k

1.94 k

540

8–128 35.2 k

9.6 k

5.8 k

1.58 k

880

240

Table XIII. External R, C Combination for No 20-Bit Gain

Error (Unbuffered Mode Only)

Gain External Capacitance (pF)

0 50 100 500 1000 5000

1

2

4

290 k

69 k

141 k

33.8 k

63.6 k

16 k

40.8 k

10.4 k

5.6 k

1.4 k

20 k

5 k

2.8 k

700

9.6 k

2.4 k

1.34 k

340

8–128 26.8 k

7.2 k

4.4 k

1.1 k

600

160

In buffered mode, the analog inputs look into the high impedance inputs stage of the on-chip buffer amplifier. C

SAMP

is charged via this buffer amplifier such that source impedances do not affect the charging of C

SAMP

. This buffer amplifier has an offset leakage current of 1␣ nA. In this buffered mode, large source impedances result in a dc offset voltage developed across the source impedance but not in a gain error.

Input Sample Rate

The modulator sample frequency for the AD7714 remains at f

CLK␣ IN

/128 (19.2␣ kHz @ f

CLK IN

= 2.4576␣ MHz) regardless of the selected gain. However, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see Table XIV). In buffered mode, the input is buffered before the input sampling capacitor. In unbuffered mode, where the analog input looks directly into the sampling capacitor, the effective input impedance is 1/C

SAMP

×

f

S

where C

SAMP

is the input sampling capacitance and f

S

is the input sample rate.

–20– REV. C

AD7714

Gain

4

8

1

2

16

32

64

128

Table XIV. Input Sampling Frequency vs. Gain

Input Sampling Freq (f

S

)

for the AD7714-3. The part is functional with V

REF

voltages down to 1 V but with degraded performance as the output noise will, in terms of LSB size, be larger. REF␣ IN(+) must always be greater than REF␣ IN(–) for correct operation of the AD7714.

f

CLK IN

2

×

f

/64 (38.4␣ kHz @ f

CLK IN

CLK IN

/64 (76.8␣ kHz @ f

= 2.4576␣ MHz)

CLK IN

= 2.4576␣ MHz)

4

×

f

CLK IN

/64 (153.6␣ kHz @ f

CLK IN

8

×

f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

8

×

f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

8

×

f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

8

×

f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

8

×

f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

= 2.4576␣ MHz)

= 2.4576␣ MHz)

= 2.4576␣ MHz)

= 2.4576␣ MHz)

= 2.4576␣ MHz)

Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is

±

1 nA over temperature and source resistance may result in gain errors on the part. In this case, the sampling switch resistance is 5␣ k

typ and the reference capacitor (C

REF

) varies with gain. The sample rate on the reference inputs is f

CLK IN

/64 and does not vary with gain. For gains of 1 to 8, C

REF

is 8 pF; for a gain of 16, it is 5.5 pF, for a gain of 32, it is 4.25 pF, for a gain of 64, it is 3.625 pF and for a gain of 128, it is 3.3125 pF.

Burnout Current

The AD7714 contains two 1␣

µ

A currents, one source current from AV

DD to AIN(+) and one sink from AIN(–) to AGND. The currents are either both on or off depending on the BO bit of the

Mode Register. These currents can be used in checking that a transducer has not burned out nor gone open-circuit before attempting to take measurements on that channel. If the currents are turned on, allowed flow in the transducer, a measurement of the input voltage on the analog input taken and the voltage measured is full scale, it indicates that the transducer has gone open-circuit; if the voltage measured is zero, it indicates that the transducer has gone short-circuit. For normal operation, these burnout currents are turned off by writing a 0 to the

BO bit. For the source current to work correctly, the applied voltage on AIN(+) should not go within 500␣ mV of AV

DD

. For the sink current to work correctly, the applied voltage on the

AIN(–) input should not go within 500␣ mV of AGND.

The output noise performance outlined in Tables I through IV is for an analog input of 0 V and is unaffected by noise on the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7714. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7714. In applications where the excitation voltage for the bridge transducer on the analog input also derives the reference voltage for the part, the effect of the noise in the excitation voltage will be removed as the application is ratiometric. Recommended reference voltage sources for the

AD7714-5 and AD7714Y grade with AV

DD

= 5 V include the

AD780, REF43 and REF192 while the recommended reference sources for the AD7714-3 and AD7714Y with AV

DD

= 3 V include the AD589 and AD1580. It is generally recommended to decouple the output of these references to further reduce the noise level.

Bipolar/Unipolar Inputs

The analog inputs on the AD7714 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages on its analog inputs, since the analog input cannot go more negative than –30␣ mV to ensure correct operation of the part. The input channels are either fully differential or pseudo-differential (all other channels referenced to AIN6). In either case, the input channels are arranged in pairs with an AIN(+) and AIN(–). As a result, the voltage to which the unipolar and bipolar signals on the AIN(+) input are referenced is the voltage on the respective AIN(–) input. For example, if AIN(–) is +2.5␣ V and the AD7714 is configured for unipolar operation with a gain of 2 and a V

REF

of

+2.5␣ V, the input voltage range on the AIN(+) input is +2.5 V to

+3.75␣ V. If AIN(–) is +2.5␣ V and the AD7714 is configured for bipolar mode with a gain of 2 and a V

REF

of +2.5␣ V, the analog input range on the AIN(+) input is +1.25␣ V to +3.75 V (i.e.,

2.5␣ V

±

1.25␣ V). If AIN(–) is at AGND, the part cannot be configured for bipolar ranges in excess of

±

30␣ mV.

DIGITAL FILTERING

The AD7714 contains an on-chip low-pass digital filter which processes the output of the part’s sigma-delta modulator. Therefore, the part not only provides the analog-to-digital conversion function but it also provides a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain rather than the analog domain and the user should be aware of these.

First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, the digital filter can be made programmable far more readily than an analog filter. Depending on the digital filter design, this gives the user the capability of programming cutoff frequency and output update rate.

Bipolar or unipolar options are chosen by programming the B/U bit of the Filter High Register. This programs the selected channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur.

REFERENCE INPUT

The AD7714’s reference inputs, REF␣ IN(+) and REF␣ IN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AV

DD

.

The nominal reference voltage, V

REF

(REF␣ IN(+)␣ –REF␣ IN(–)), for specified operation is +2.5␣ V for the AD7714-5 and +1.25␣ V

REV. C

–21–

On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7714 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%).

2

AD7714

In addition, the digital filter does not provide any rejection at integer multiples of the digital filter’s sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter’s sampling frequency so that the unattenuated bands actually occur around multiples of the input sampling frequency f

S

(as defined in Table XIV). Thus, the unattenuated bands occur at n

×

f

S

(where n = 1, 2, 3. . .). At these frequencies, there are frequency bands,

± f

3 dB

wide (f

3 dB

is the cutoff frequency of the digital filter) at either side where noise passes unattenuated to the output.

Filter Characteristics

The AD7714’s digital filter is a low-pass filter with a (sinx/x)

3 response (also called sinc

3

). The transfer function for this filter is described in the z-domain by:

H(z )

=

1

N

and in the frequency domain by:

×

1

Z

N

1

Z

1

3

=

1

N

×

Sin N

π

f f

Sin

π

f f

S

)

S

)

3

Figure 4 shows the filter frequency response for a cutoff frequency of 2.62␣ Hz which corresponds to a first filter notch frequency of 10␣ Hz. The plot is shown from dc to 65␣ Hz.

This response is repeated at either side of the input sampling frequency and at either side of multiples of the input sampling frequency.

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

–220

–240

0 10 20 30 40

FREQUENCY – Hz

50 60

Figure 4. Frequency Response of AD7714 Filter

The response of the filter is similar to that of an averaging filter but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. Thus, for the plot of Figure 4 where the output rate is 10␣ Hz, the first notch of the filter is at 10␣ Hz. The notches of this (sinx/x)

3 filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches. For the example given, if the first notch is at

10␣ Hz, there will be notches (and hence >100␣ dB rejection) at both 50␣ Hz and 60␣ Hz.

The cutoff frequency of the digital filter is determined by the value loaded to bits FS0 to FS11 in the Filter High and Filter

Low Registers. Programming a different cutoff frequency via

FS0 – FS11 does not alter the profile of the filter response; it changes the frequency of the notches as outlined in the Filter

Registers section. The output update and first notch correspond and are determined by the relationship:

Output Rate = f

CLK IN

/(N.128) where N is the decimal equivalent of the word loaded to the

FS0 to FS11 bits of the Filter Registers while the –3␣ dB frequency is determined by the relationship:

–3␣ dB frequency = 0.262

×

filter first notch frequency

The filter provides a linear phase response with a group delay determined by:

Group Delay = –3

π

.(N.f/f

MOD

)

where N is the decimal equivalent of the word loaded to the

FS0 to FS11 bits of the Filter Registers and f

MOD

= f

CLK IN

/128.

Since the AD7714 contains this on-chip, low-pass filtering, a settling time is associated with step function inputs and data on the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the output rate chosen for the filter. The settling time of the filter to a fullscale step input can be up to four times the output data period.

For a synchronized step input (using the

SYNC or FSYNC functions) the settling time is three times the output data period. When changing channels on the part, the change from one channel to the other is synchronized so the output settling time is also three times the output data period. Thus, in switching between channels, the output data register is not updated until the settling time of the filter has elapsed.

Post-Filtering

The on-chip modulator provides samples at a 19.2␣ kHz output rate with f

CLK IN

at 2.4576␣ MHz. The on-chip digital filter decimates these samples to provide data at an output rate that corresponds to the programmed output rate of the filter. Since the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth will satisfy most application requirements. However, there may be some applications that require a higher data rate for a given bandwidth and noise performance. Applications that need this higher data rate will require some post-filtering following the part’s digital filter.

For example, if the required bandwidth is 7.86␣ Hz but the required update rate is 100␣ Hz, the data can be taken from the

AD7714 at the 100␣ Hz rate giving a –3 dB bandwidth of

26.2␣ Hz. Post-filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86␣ Hz bandwidth level, while maintaining an output rate of 100␣ Hz.

Post-filtering can also be used to reduce the output noise from the device for bandwidths below 1.26␣ Hz. At a gain of 128 and a bandwidth of 1.26␣ Hz, the output rms noise is 140␣ nV. This is essentially device noise or white noise and since the input is chopped, the noise has a primarily flat frequency response. By reducing the bandwidth below 1.26␣ Hz, the noise in the resultant passband can be reduced. A reduction in bandwidth by a factor of 2 results in a reduction of approximately 1.25 in the output rms noise. This additional filtering will result in a longer settling time.

–22– REV. C

ANALOG FILTERING

The digital filter does not provide any rejection at integer multiples of the input sampling frequency, as outlined earlier. However, due to the AD7714’s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. This means that the analog filtering requirements in front of the AD7714 are considerably reduced versus a conventional converter with no on-chip filtering. In addition, because the part’s common-mode rejection performance of 100␣ dB extends out to several kHz, common-mode noise in this frequency range will be substantially reduced.

Depending on the application, however, it may be necessary to provide attenuation prior to the AD7714 in order to eliminate unwanted frequencies from these bands which the digital filter will pass. It may also be necessary in some applications to provide analog filtering in front of the AD7714 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator.

If passive components are placed in front of the AD7714, in unbuffered mode, care must be taken to ensure that the source impedance is low enough so as not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing filtering which can be provided in front of the AD7714 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances will simply result in a small dc offset error (a 10␣ k

source resistance will cause an offset error of less than 10␣

µ

V). Therefore, if the system requires any significant source impedances to provide passive analog filtering in front of the AD7714, it is recommended that the part be operated in buffered mode.

CALIBRATION

The AD7714 provides a number of calibration options which can be programmed via the MD2, MD1 and MD0 bits of the

Mode Register. The different calibration options are outlined in the Mode Register and Calibration Sequences sections. A calibration cycle may be initiated at any time by writing to these bits of the Mode Register. Calibration on the AD7714 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range.

The AD7714 gives the user access to the on-chip calibration registers allowing the microprocessor to read the device’s calibration coefficients and also to write its own calibration coefficients to the part from prestored values in E

2

PROM. This gives the microprocessor much greater control over the AD7714’s calibration procedure. It also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in

E

2

PROM. The values in these calibration registers are 24-bit wide. In addition, the span and offset for the part can be adjusted by the user.

There is a significant variation in the value of these coefficients across the different output update rates, gains and unipolar/ bipolar operation. Internally in the AD7714, these coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration register contains a

AD7714

value which, when normalized, is subtracted from all conversion results. The full-scale calibration register contains a value which, when normalized, is multiplied by all conversion results.

The offset calibration coefficient is subtracted from the result prior to the multiplication by the full-scale coefficient. This means that the full-scale coefficient is effectively a span or gain coefficient.

The AD7714 offers self-calibration, system calibration and background calibration facilities. For full calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are “zero-scale” and “full-scale” points. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. As a result, the accuracy of the calibration can only be as good as the noise level which the part provides in normal mode. The result of the “zero-scale” calibration conversion is stored in the Zero

Scale Calibration Register for the appropriate channel. The result of the “full-scale” calibration conversion is stored in the

Full-Scale Calibration Register for the appropriate channel. With these readings, the microcontroller can calculate the offset and the gain slope for the input to output transfer function of the converter. Internally, the part works with 33 bits of resolution to determine its conversion result of either 16 bits or 24 bits.

Self-Calibration

A self-calibration is initiated on the AD7714 by writing the appropriate values (0, 0, 1) to the MD2, MD1 and MD0 bits of the Mode Register. In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (i.e., AIN(+) = AIN(–) = Internal

Bias Voltage). The PGA is set for the selected gain (as per G2,

G1, G0 bits in the Mode Register) for this zero-scale calibration conversion. The full-scale calibration conversion is performed at the selected gain on an internally-generated voltage of V

REF

/

Selected Gain.

The duration time of the calibration is 6

×

1/Output Rate. This is made up of 3

×

1/Output Rate for the zero-scale calibration and 3

×

1/Output Rate for the full-scale calibration. At this time the MD2, MD1 and MD0 bits in the Mode Register return to

0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The

DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to

DRDY going low is 9

×

1/

Output Rate. This is made up of 3

×

1/Output Rate for the zeroscale calibration, 3

×

1/Output Rate for the full-scale calibration and 3

×

1/Output Rate for a conversion on the analog input. If

DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before

DRDY goes high to indicate that calibration is in progress. Therefore,

DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register.

For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as above but since the part is configured for bipolar operation, the output code for zero differential input is 800000 Hex in 24-bit mode.

2

REV. C

–23–

AD7714

The part also offers ZS Self-Calibration and FS Self-Calibration options. In these cases, the part performs just a zero-scale or full-scale calibration respectively and not a full calibration of the part. A full-scale calibration should not be carried out unless the part contains valid zero-scale coefficients. These calibrations are initiated on the AD7714 by writing the appropriate values

(1, 1, 0 for ZS Self-Calibration and 1, 1, 1 for FS Self Calibration) to the MD2, MD1 and MD0 bits of the Mode Register.

The zero-scale or full-scale calibration is exactly the same as that described for the full self-calibration. In these cases, the duration of the calibration is 3

×

1/Output Rate. At this time the

MD2, MD1 and MD0 bits in the Mode Register return to

0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The

DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The time from the calibration command being issued to

DRDY going low is 6

×

1/Output

Rate. This is made up of 3

×

1/Output Rate for the zero-scale or full-scale calibration and 3

×

1/Output Rate for a conversion on the analog input. If

DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before

DRDY

goes high to indicate that calibration is in progress. Therefore,

DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode

Register.

The fact that the self-calibration can be performed as a two step calibration offers another feature. After the sequence of a full self calibration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the part’s zero point or gain. Calibrating one of the parameters, either offset or gain, will not affect the other parameter.

System Calibration

System calibration allows the AD7714 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as selfcalibration but uses voltage values presented by the system to the AIN inputs for the zero- and full-scale points. Full System calibration requires a two-step process, a ZS System Calibration followed by a FS System Calibration.

For a full system calibration, the zero-scale point must be presented to the converter first. It must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. Once the system zero scale has been set up at the analog input, a ZS System Calibration is then initiated by writing the appropriate values (0, 1, 0) to the MD2, MD1 and

MD0 bits of the Mode Register. The zero-scale system calibration is performed at the selected gain. The duration of the calibration is 3

×

1/Output Rate. At this time, the MD2, MD1 and

MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The

DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register.

The time from the calibration command being issued to

DRDY

going low is 4

×

1/Output Rate. This is made up of 3

×

1/Output

Rate for the zero-scale system calibration and 1/Output Rate for a conversion on the analog input. This conversion on the analog input is on the same voltage as the zero-scale system calibration and, therefore, the resultant word in the data register from this conversion should be a zero-scale reading. If

DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle

(MCLK␣ IN/128) before

DRDY goes high to indicate that calibration is in progress. Therefore,

DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register.

After the zero-scale point is calibrated, the full-scale point is applied to AIN and the second step of the calibration process is initiated by again writing the appropriate values (0, 1, 1) to

MD2, MD1 and MD0. Again the full-scale voltage must be set up before the calibration is initiated, and it must remain stable throughout the calibration step. The full-scale system calibration is performed at the selected gain. The duration of the calibration is 3

×

1/Output Rate. At this time, the MD2, MD1 and

MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The

DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register.

The time from the calibration command being issued to

DRDY

going low is 4

×

1/Output Rate. This is made up of 3

×

1/Output Rate for the full-scale system calibration and 1/Output Rate for a conversion on the analog input. This conversion on the analog input is on the same voltage as the full-scale system calibration and, therefore, the resultant word in the data register from this conversion should be a full-scale reading. If

DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle

(MCLK␣ IN/128) before

DRDY goes high to indicate that calibration is in progress. Therefore,

DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register.

In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale (zero differential voltage) and positive full scale.

The fact that the system calibration is a two step calibration offers another feature. After the sequence of a full system calibration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the system zero reference point or the system gain. Calibrating one of the parameters, either system offset or system gain, will not affect the other parameter. A full-scale calibration should not be carried out unless the part contains valid zero-scale coefficients.

System calibration can also be used to remove any errors from source impedances on the analog input when the part is used in unbuffered mode. A simple R, C antialiasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error.

–24– REV. C

System-Offset Calibration

System-offset calibration is a variation of both the system calibration and self-calibration. In this case, the zero-scale point is determined in exactly the same way as a ZS System Calibration.

The system zero-scale point is presented to the AIN inputs of the converter. This must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. Once the system zero scale has been set up, a

System-Offset Calibration is then initiated by writing the appropriate values (1, 0, 0) to the MD2, MD1 and MD0 bits of the

Mode Register. The zero-scale system calibration is performed at the selected gain.

The full-scale calibration is performed in exactly the same way as an FS Self Calibration. The full-scale calibration conversion is performed at the selected gain on an internally generated voltage of V

REF

/Selected Gain. This is a one step calibration sequence and the time for calibration is 6

×

1/Output Rate. At this time, the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0. This gives the earliest indication that the calibration sequence is complete. The

DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to

DRDY going low is 9

×

1/

Output Rate. This is made up of 3

×

1/Output Rate for the zeroscale system calibration, 3

×

1/Output Rate for the full-scale self-calibration and 3

×

1/Output Rate for a conversion on the analog input. This conversion on the analog input is on the same voltage as the zero-scale system calibration and, therefore, the resultant word in the data register from this conversion should be a zero-scale reading. If

DRDY is low before (or goes low during) the calibration command write to the Mode Register, it may take up to one modulator cycle (MCLK␣ IN/128) before

DRDY goes high to indicate that calibration is in progress. Therefore,

DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the Mode Register.

In the unipolar mode, the system-offset calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale.

Background Calibration

The AD7714 also offers a background calibration mode where the part interleaves its calibration procedure with its normal conversion sequence. In the background calibration mode, the part provides continuous zero-scale self-calibrations; it does not provide any full-scale calibrations. The zero-scale point used in determining the calibration coefficients in this mode is exactly the same as for a ZS Self-Calibration. The background calibration mode is invoked by writing 1, 0, 1 to the MD2, MD1,

MD0 bits of the Mode Register. When invoked, the background calibration mode performs a zero-scale self calibration after every output update and this reduces the output data rate of the AD7714 by a factor of six. Its advantage is that the part is continually performing offset calibrations and automatically updating its zero-scale calibration coefficients. As a result, the effects of temperature drift, supply sensitivity and time drift on zero-scale errors are automatically removed. When the background calibration mode is turned on, the part will remain in this mode until bits MD2, MD1 and MD0 of the Mode Register are changed.

AD7714

Because the background calibration does not perform full-scale calibrations, a self-calibration should be performed before placing the part in background calibration mode. Removal of the offset drift in this mode leaves gain drift as the only source of error not removed from the part. The typical gain drift of the

AD7714 with temperature is 0.2␣ ppm/

°

C. The

SYNC input or

FSYNC bit should not be exercised when the part is in background calibration mode.

Span and Offset Limits

Whenever a system calibration mode is used, there are limits on the amount of offset and span which can be accommodated.

The overriding requirement in determining the amount of offset and gain which can be accommodated by the part is the requirement that the positive full-scale calibration limit is

1.05

×

V

REF

/GAIN. This allows the input range to go 5% above the nominal range. The built-in headroom in the AD7714’s analog modulator ensures that the part will still operate correctly with a positive full-scale voltage which is 5% beyond the nominal.

The range of input span in both the unipolar and bipolar modes has a minimum value of 0.8

×

V

REF

/GAIN and a maximum value of 2.1

×

V

REF

/GAIN. However, the span (which is the difference between the bottom of the AD7714’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. Once again, the offset has to take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative (with respect to AIN(–)) offsets. In both unipolar and bipolar modes, the range of positive offsets which can be handled by the part depends on the selected span. Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user has to ensure that the offset range plus the span range does exceed 1.05

×

V

REF

/GAIN. This is best illustrated by looking at a few examples.

If the part is used in unipolar mode with a required span of

0.8

×

V

REF

/GAIN, the offset range the system calibration can handle is from –1.05

×

V

REF

/GAIN to +0.25

×

V

REF

/GAIN. If the part is used in unipolar mode with a required span of V

REF

/

GAIN, the offset range the system calibration can handle is from –1.05

×

V

REF

/GAIN to +0.05

×

V

REF

/GAIN. Similarly, if the part is used in unipolar mode and required to remove an offset of 0.2

×

V

REF

/GAIN, the span range the system calibration can handle is 0.85

×

V

REF

/GAIN.

If the part is used in bipolar mode with a required span of

±

0.4

×

V

REF

/GAIN, then the offset range which the system calibration can handle is from –0.65

×

V

REF

/GAIN to +0.65

×

V

REF

/GAIN. If the part is used in bipolar mode with a required span of

±

V

REF

/GAIN, the offset range the system calibration can handle is from –0.05

×

V

REF

/GAIN to +0.05

×

V

REF

/GAIN.

Similarly, if the part is used in bipolar mode and required to remove an offset of

±

0.2

×

V

REF

/GAIN, the span range the system calibration can handle is

±

0.85

×

V

REF

/GAIN.

2

REV. C

–25–

AD7714

Power-Up and Calibration

On power-up, the AD7714 performs an internal reset which sets the contents of the internal registers to a known state. There are default values loaded to all registers after a power-on or reset. The default values contain nominal calibration coefficients for the calibration registers. However, to ensure correct calibration for the device a calibration routine should be performed after power-up.

The power dissipation and temperature drift of the AD7714 are low and no warm-up time is required before the initial calibration is performed. However, if an external reference is being used, this reference must have stabilized before calibration is initiated. Similarly, if the clock source for the part is generated from a crystal or resonator across the MCLK pins, the start-up time for the oscillator circuit should elapse before a calibration is initiated on the part (see below).

USING THE AD7714

Clocking and Oscillator Circuit

The AD7714 requires a master clock input, which may be an external CMOS compatible clock signal applied to the MCLK␣ IN pin with the MCLK␣ OUT pin left unconnected. Alternatively, a crystal or ceramic resonator of the correct frequency can be connected between MCLK␣ IN and MCLK␣ OUT in which case the clock circuit will function as an oscillator, providing the clock source for the part. The input sampling frequency, the modulator sampling frequency, the –3␣ dB frequency, output update rate and calibration time are all directly related to the master clock frequency, f

CLK␣ IN

. Reducing the master clock frequency by a factor of 2 will halve the above frequencies and update rate and double the calibration time. The current drawn from the DV

DD

power supply is also directly related to f

CLK␣ IN

.

Reducing f

CLK␣ IN

by a factor of 2 will halve the DV

DD

current but will not affect the current drawn from the AV

DD

power supply.

Using the part with a crystal or ceramic resonator between the

MCLK IN and MCLK OUT pins generally causes more current to be drawn from DV

DD

than when the part is clocked from a driven clock signal at the MCLK IN pin. This is because the on-chip oscillator circuit is active in the case of the crystal or ceramic resonator. Therefore, the lowest possible current on the AD7714 is achieved with an externally applied clock at the

MCLK IN pin with MCLK OUT unconnected and unloaded.

The amount of additional current taken by the oscillator depends on a number of factors—first, the larger the value of capacitor placed on the MCLK␣ IN and MCLK␣ OUT pins, then the larger the DV

DD

current consumption on the AD7714. Care should be taken not to exceed the capacitor values recommended by the crystal and ceramic resonator manufacturers to avoid consuming unnecessary DV

DD

current. Typical values recommended by crystal or ceramic resonator manufacturers are in the range of 30␣ pF to 50␣ pF and if the capacitor values on MCLK

IN and MCLK OUT are kept in this range they will not result in any excessive DV

DD

current. Another factor that influences the DV

DD

current is the effective series resistance (ESR) of the crystal which appears between the MCLK IN and MCLK OUT pins of the AD7714. As a general rule, the lower the ESR value then the lower the current taken by the oscillator circuit.

When operating with a clock frequency of 2.4576␣ MHz, there is no appreciable difference in the DV

DD

current between an externally applied clock and a crystal resonator when operating with a DV

DD

of +3␣ V. With DV

2.4576␣ MHz, the typical DV

DD

DD

= +5␣ V and f

CLK IN

=

current increases by 50␣

µ

A for a crystal/resonator supplied clock versus an externally applied clock. The ESR values for crystals and resonators at this frequency tend to be low and as a result there tends to be little difference between different crystal and resonator types.

When operating with a clock frequency of 1␣ MHz, the ESR value for different crystal types varies significantly. As a result, the DV

DD

current drain varies across crystal types. When using a crystal with an ESR of 700␣

or when using a ceramic resonator, the increase in the typical DV

DD applied clock is 50␣

µ

A with DV

DD

DV

DD

current over an externally-

= +3␣ V and 175␣

µ

A with

= +5␣ V. When using a crystal with an ESR of 3␣ k

, the increase in the typical DV

DD

current over an externally applied clock is again 50␣

µ

A with DV

DD

= +3␣ V but 300␣

µ

A with

DV

DD

= +5␣ V.

The on-chip oscillator circuit also has a start-up time associated with it before it is oscillating at its correct frequency and correct voltage levels. The typical start up time for the circuit is 10␣ ms with a DV

DD

of +5␣ V and 15␣ ms with a DV

DD

of +3␣ V. At 3␣ V supplies, depending on the loading capacitances on the MCLK pins, a 1␣ M

feedback resistor may be required across the crystal or resonator in order to keep the start up times around the

15␣ ms duration.

The AD7714’s master clock appears on the MCLK OUT pin of the device. The maximum recommended load on this pin is one

CMOS load. When using a crystal or ceramic resonator to generate the AD7714’s clock, it may be desirable to then use this clock as the clock source for the system. In this case, it is recommended that the MCLK OUT signal is buffered with a CMOS buffer before being applied to the rest of the circuit.

System Synchronization

The

SYNC input (or FSYNC bit) allows the user to reset the modulator and digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, i.e., the rising edge of

SYNC or when a 1 is written to FSYNC.

The

SYNC input can also be used to allow two other functions.

If multiple AD7714s are operated from a common master clock, they can be synchronized to update their output registers simultaneously. A falling edge on the

SYNC input (or a 1 written to the FSYNC bit of the Mode Register) resets the digital filter and analog modulator and places the AD7714 into a consistent, known state. While the

SYNC input is low (or FSYNC high), the AD7714 will be maintained in this state. On the rising edge of

SYNC (or when a 0 is written to the FSYNC bit), the modulator and filter are taken out of this reset state and on the next clock edge the part starts to gather input samples again. In a system using multiple AD7714s, a common signal to their

SYNC inputs will synchronize their operation. This would normally be done after each AD7714 has performed its own calibration or has had calibration coefficients loaded to it. The output updates will then be synchronized with the maximum possible difference between the output updates of the individual

AD7714s being one MCLK IN cycle.

–26– REV. C

The

SYNC input can also be used as a start convert command allowing the AD7714 to be operated in a conventional converter fashion. In this mode, the rising edge of

SYNC starts conversion and the falling edge of

DRDY indicates when conversion is complete. The disadvantage of this scheme is that the settling time of the filter has to be taken into account for every data register update. This means that the rate at which the data register is updated at a three times slower rate in this mode.

Since the

SYNC input (or FSYNC bit) resets the digital filter, the full settling-time of 3

×

1/Output Rate has to elapse before there is a new word loaded to the output register on the part. If the

DRDY signal is low when SYNC returns high (or FSYNC goes to a 0), the

DRDY signal will not be reset high by the

SYNC (or FSYNC) command. This is because the AD7714 recognizes that there is a word in the data register which has not been read. The

DRDY line will stay low until an update of the data register takes place at which time it will go high for

500

× t

CLK IN before returning low again. A read from the data register resets the

DRDY signal high and it will not return low until the settling time of the filter has elapsed (from the

SYNC

or FSYNC command) and there is a valid new word in the data register. If the

DRDY line is high when the SYNC (or FSYNC) command is issued, the

DRDY line will not return low until the settling time of the filter has elapsed.

Reset Input

The

RESET input on the AD7714 resets all the logic, the digital filter and the analog modulator while all on-chip registers are reset to their default state.

DRDY is driven high and the

AD7714 ignores all communications to any of its registers while the

RESET input is low. When the RESET input returns high, the AD7714 starts to process data and

DRDY will return low in

3

×

1/Output Rate indicating a valid new word in the data register. However, the AD7714 operates with its default setup conditions after a

RESET and it is generally necessary to set up all registers and carry out a calibration after a

RESET command.

The AD7714’s on-chip oscillator circuit continues to function even when the

RESET input is low. The master clock signal continues to be available on the MCLK OUT pin. Therefore, in applications where the system clock is provided by the AD7714’s clock, the AD7714 produces an uninterrupted master clock during

RESET commands.

Standby Mode

The

STANDBY input on the AD7714 allows the user to place the part in a power-down mode when it is not required to provide conversion results The AD7714 retains the contents of all its on-chip registers (including the data register) while in standby mode. When in standby mode, the digital interface is reset and

DRDY is reset to a Logic 1. Data cannot be accessed from the part while in standby mode. When released from standby mode, the part starts to process data and a new word is available in the data register in 3

×

1/Output rate from when the

STANDBY

input goes high.

Placing the part in standby mode reduces the total current to

5␣

µ

A typical when the part is operated from an external master clock, provided this master clock is stopped. If the external clock continues to run in standby mode, the standby current increases to 150␣

µ

A typical with 5 V supplies and 75

µ

A typical with 3.3 V supplies. If a crystal or ceramic resonator is used as

REV. C

–27–

AD7714

the clock source, the total current in standby mode is 400␣

µ

A typical with 5 V supplies and 90

µ

A with 3.3 V supplies. This is because the on-chip oscillator circuit continues to run when the part is in its standby mode. This is important in applications where the system clock is provided by the AD7714’s clock, so that the AD7714 produces an uninterrupted master clock even when it is in its standby mode.

Accuracy

Sigma-Delta ADCs, like VFCs and other integrating ADCs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. The AD7714 achieves excellent linearity by the use of high quality, on-chip capacitors, which have a very low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in its input stage. To ensure excellent performance over time and temperature, the AD7714 uses digital calibration techniques that minimize offset and gain error.

Drift Considerations

The AD7714 uses chopper stabilization techniques to minimize input offset drift. Charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. The dc input leakage current is essentially independent of the selected gain.

Gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. It is not affected by leakage currents.

Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter or by operating the part in the background calibration mode. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes.

POWER SUPPLIES

No specific power sequence is required for the AD7714; either the AV

DD

or the DV

DD

supply can come up first. While the latch-up performance of the AD7714 is good, it is important that power is applied to the AD7714 before signals at REF␣ IN,

AIN or the logic input pins in order to avoid latch-up. If this is not possible, then the current which flows in any of these pins should be limited. If separate supplies are used for the AD7714 and the system digital circuitry, then the AD7714 should be powered up first. If it is not possible to guarantee this, then current limiting resistors should be placed in series with the logic inputs to again limit the current.

Supply Current

The current consumption on the AD7714 is specified for supplies in the range +3␣ V to +3.6␣ V and in the range +4.75␣ V to

+5.25␣ V. The part operates over a +2.85␣ V to +5.25␣ V supply range and the I

DD

for the part varies as the supply voltage varies over this range. Figure 5 shows the variation of the typical

I

DD

with V

DD

voltage for both a 1 MHz external clock and a

2.4576 MHz external clock at +25

°

C. The AD7714 is operated in unbuffered mode and the internal boost bit on the part is turned off. The relationship shows that the I

DD

is minimized by operating the part with lower V

DD

voltages. I

DD

on the AD7714 is also minimized by using an external master clock or by optimizing external components when using the on-chip oscillator circuit. The Y grade part is specified from 2.7 V to 3.3 V and

4.75 V to 5.25 V.

2

AD7714

1.0

0.9

0.8

0.7

0.6

MCLK IN = 2.4576MHz

0.5

0.4

0.3

MCLK IN = 1MHz

0.2

0.1

0

2.85

3.15

3.45

3.75

4.05

4.35

4.65

4.95

5.25

SUPPLY VOLTAGE (AV

DD

& DV

DD

) – Volts

Figure 5. I

DD

vs. Supply Voltage

Grounding and Layout

Since the analog inputs and reference input are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent Common-Mode Rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies to the AD7714 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided those noise sources do not saturate the analog modulator. As a result, the AD7714 is more immune to noise interference that a conventional high resolution converter. However, because the resolution of the AD7714 is so high and the noise levels from the AD7714 so low, care must be taken with regard to grounding and layout.

The printed circuit board which houses the AD7714 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7714 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the

AD7714. If the AD7714 is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7714.

Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7714 to avoid noise coupling. The power supply lines to the AD7714 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side.

Good decoupling is important when using high resolution

ADCs. All analog supplies should be decoupled with 10␣

µ

F tantalum in parallel with 0.1␣

µ

F capacitors to AGND. To achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with

0.1␣

µ

F disc ceramic capacitors to DGND. In systems where a common supply voltage is used to drive both the AV

DD

and

DV

DD

of the AD7714, it is recommended that the system’s

AV

DD

supply is used. This supply should have the recommended analog supply decoupling capacitors between the AV

DD

pin of the AD7714 and AGND and the recommended digital supply decoupling capacitor between the DV

DD

pin of the AD7714 and

DGND.

Evaluating the AD7714 Performance

The recommended layout for the AD7714 is outlined in the evaluation board for the AD7714. The evaluation board package includes a fully assembled and tested evaluation board, documentation, software for controlling the board over the printer port of a PC and software for analyzing the AD7714’s performance on the PC. For the AD7714-5, the evaluation board order number is EVAL-AD7714-5EB and for the AD7714-3, the order number is EVAL-AD7714-3EB.

Noise levels in the signals applied to the AD7714 may also affect performance of the part. The AD7714 allows two techniques for evaluating the true performance of the part, independent of the analog input signal. These schemes should be used after a calibration has been performed on the part.

The first of these is to select the AIN6/AIN6 input channel arrangement. In this case, the differential inputs to the AD7714 are internally shorted together to provide a zero differential voltage for the analog modulator. External to the device, the

AIN6 input should be connected to a voltage that is within the allowable common-mode range of the part.

The second scheme is to evaluate the part with a voltage near the input full scale voltage for a gain of 1. To do this, the reference voltage for the part should be applied to the analog input.

This will give a fixed full-scale reading from the device. If the zero-scale calibration coefficient is now read from the device, increased by a number equivalent to about 200 decimal and this value reloaded to the zero-scale calibration register, the input range will be offset such that a voltage equal to reference voltage no longer corresponds to a full-scale reading. This allows the user to evaluate the noise performance of the part with a near full-scale voltage.

–28– REV. C

DIGITAL INTERFACE

The AD7714’s programmable functions are controlled using a set of on-chip registers as previously outlined. Data is written to these registers via the part’s serial interface, and read access to the on-chip registers is also provided by this interface. All communications to the part must start with a write operation to the

Communications Register. After power-on or

RESET, the device expects a write to its Communications Register. The data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write operation to the Communications Register followed by a write to the selected register. A read operation from any register on the part (including the output data register) starts with a write operation to the Communications Register followed by a read operation from the selected register.

The AD7714’s serial interface consists of five signals,

CS,

SCLK, DIN, DOUT and

DRDY. The DIN line is used for transferring data into the on-chip registers while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal.

The

DRDY line is used as a status signal to indicate when data is ready to be read from the AD7714’s data register.

DRDY

goes low when a new data word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated.

CS is used to select the device. It can be used to decode the AD7714 in systems where a number of parts are connected to the serial bus.

AD7714

The AD7714 serial interface can operate in three-wire mode by tying the

CS input low. In this case, the SCLK, DIN and

DOUT lines are used to communicate with the AD7714 and the status of

DRDY can be obtained by interrogating the MSB of the Communications Register.

Figures 6 and 7 show timing diagrams for interfacing to the

AD7714 with

CS used to decode the part. Figure 6 is for a read operation from the AD7714’s output shift register, while Figure

7 shows a write operation to the input shift register. Both diagrams are for the POL input at a logic high; for operation with the POL input at a logic low simply invert the SCLK waveform shown in the diagrams. It is possible to read the same data twice from the output register even though the

DRDY line returns high after the first read operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place.

The serial interface can be reset by exercising the

RESET input on the part. It can also be reset by writing a series of 1s on the

DIN input. If a logic 1 is written to the AD7714 DIN line for at least 32 serial clock cycles the serial interface is reset. This ensures in three-wire systems that if the interface gets lost, either via a software error or by some glitch in the system, it can be reset back into a known state. This state returns the interface to where the AD7714 is expecting a write operation to the Communications Register. This operation does not in itself reset the contents of any registers but since the interface was lost, the information that was written to any of the registers is unknown and it is advisable to set up all registers again.

2

DRDY

CS

SCLK

DOUT t

3 t

10 t

4 t

6 t

5 t

7

MSB

Figure 6. Read Cycle Timing Diagram (POL = 1)

LSB t

9 t

8

REV. C

CS

SCLK

DIN t

11 t

12 t

13

MSB t

14 t

15

Figure 7. Write Cycle Timing Diagram (POL = 1)

LSB t

16

–29–

AD7714

CONFIGURING THE AD7714

The AD7714 contains eight on-chip registers that can be accessed via the serial interface. Communication with any of these registers is initiated by writing to the Communications

Register first. Figure 8 outlines a flow diagram of the sequence which is used to configure all registers after a power-up or reset.

The flowchart also shows two different read options—the first where the

DRDY pin is polled to determine when an update of the data register has taken place, the second where the

DRDY

bit of the Communications Register is interrogated to see if a data register update has taken place. Also included in the flowing diagram is a series of words which should be written to the registers for a particular set of operating conditions. These conditions are test channel (AIN6/AIN6), gain of 1, burnout current off, no filter sync, bipolar mode, 24-bit word length, boost off and maximum filter word (4000 decimal).

START

POWER-ON/RESET FOR AD7714

CONFIGURE & INITIALIZE µC/µP SERIAL PORT

WRITE TO COMMUNICATIONS REGISTER SETTING UP

CHANNEL & SETTING UP NEXT OPERATION TO BE A

WRITE TO THE FILTER HIGH REGISTER (27 HEX)

WRITE TO FILTER HIGH REGISTER SETTING

UP REQUIRED VALUES (4F HEX)

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A WRITE TO THE FILTER LOW REGISTER (37 HEX)

WRITE TO FILTER LOW REGISTER SETTING

UP REQUIRED VALUES (A0 HEX)

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A WRITE TO THE MODE REGISTER (17 HEX)

WRITE TO MODE REGISTER SETTING UP REQUIRED

VALUES & INITIATING A CALIBRATION (20 HEX)

POLL

DRDY

PIN

POLL

DRDY

BIT OF COMMUNICATIONS REGISTER

NO

DRDY

LOW?

YES

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A READ FROM THE DATA REGISTER (5F HEX)

READ FROM DATA REGISTER

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO BE A

READ FROM THE COMMUNICATIONS REGISTER (0F HEX)

READ FROM COMMUNICATIONS REGISTER

NO

DRDY

LOW?

YES

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A READ FROM THE DATA REGISTER (5F HEX)

READ FROM DATA REGISTER

Figure 8. Flowchart for Setting Up and Reading from the AD7714

–30– REV. C

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7714’s flexible serial interface allows for easy interface to most microcomputers and microprocessors. The flowchart of

Figure 8 outlines the sequence which should be followed when interfacing a microcontroller or microprocessor to the AD7714.

Figures 9, 10 and 11 show some typical interface circuits.

The serial interface on the AD7714 has the capability of operating from just three wires and is compatible with SPI interface protocols. The three-wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of opto-isolators required in the system.

The rise and fall times of the digital inputs to the AD7714

(especially the SCLK input) should be no longer than 1␣

µ s.

Most of the registers on the AD7714 are 8-bit registers which facilitates easy interfacing to the 8-bit serial ports of microcontrollers. Some of the registers on the part are up to 24 bits, but data transfers to these 24-bit registers can consist of a full 24-bit transfer or three 8-bit transfers to the serial port of the microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these processors, such as the ADSP-2105, have the facility to program the amount of cycles in a serial transfer. This allows the user to tailor the number of bits in any transfer to match the register length of the required register in the AD7714.

Even though some of the registers on the AD7714 are only eight bits in length, communicating with two of these registers in successive write operations can be handled as a single 16-bit data transfer if required. For example, if the Mode Register is to be updated, the processor must first write to the Communications Register (saying that the next operation is a write to the

Mode Register) and then write eight bits to the Mode Register.

This can all be done in a single 16-bit transfer if required because once the eight serial clocks of the write operation to the

Communications Register have been completed the part immediately sets itself up for a write operation to the Mode Register.

AD7714 to 68HC11 Interface

Figure 9 shows an interface between the AD7714 and the

68HC11 microcontroller. The diagram shows the minimum

(three-wire) interface with

CS on the AD7714 hard-wired low.

In this scheme, the

DRDY bit of the Communications Register is monitored to determine when the Data Register is updated.

An alternative scheme, which increases the number of interface lines to four, is to monitor the

DRDY output line from the

AD7714. The monitoring of the

DRDY line can be done in two ways. First,

DRDY can be connected to one of the 68HC11’s port bits (such as PC0) which is configured as an input. This port bit is then polled to determine the status of

DRDY. The second scheme is to use an interrupt driven system in which case, the

DRDY output is connected to the IRQ input of the

68HC11. For interfaces which require control of the

CS input on the AD7714, one of the port bits of the 68HC11 (such as

PC1), which is configured as an output, can be used to drive the

CS input.

AD7714

The 68HC11 is configured in the master mode with its CPOL bit set to a logic zero and its CPHA bit set to a logic one. When the 68HC11 is configured like this, its SCLK line idles low between data transfers. Therefore, the POL input of the AD7714 should be hard-wired low. For systems where it is preferable that the SCLK idle high, the CPOL bit of the 68HC11 should be set to a logic 1 and the POL input of the AD7714 should be hard-wired to a logic high.

SS

SCK

68HC11

MISO

MOSI

DV

DD DV

DD

SYNC

RESET

SCLK

AD7714

DATA OUT

DATA IN

POL

CS

Figure 9. AD7714 to 68HC11 Interface

The AD7714 is not capable of full duplex operation. If the

AD7714 is configured for a write operation, no data appears on the DATA OUT lines even when the SCLK input is active.

Similarly, if the AD7714 is configured for a read operation, data presented to the part on the DATA IN line is ignored even when SCLK is active.

Coding for an interface between the 68HC11 and the AD7714 is given in Table XV. In this example, the

DRDY output line of the AD7714 is connected to the PC0 port bit of the 68HC11 and is polled to determine its status.

AD7714 to 8051 Interface

An interface circuit between the AD7714 and the 8XC51 microcontroller is shown in Figure 10. The diagram shows the minimum number of interface connections with

CS on the

AD7714 hard-wired low. In the case of the 8XC51 interface the minimum number of interconnects is just two. In this scheme, the

DRDY bit of the Communications Register is monitored to determine when the Data Register is updated. The alternative scheme, which increases the number of interface lines to three, is to monitor the

DRDY output line from the AD7714. The monitoring of the

DRDY line can be done in two ways. First,

DRDY can be connected to one of the 8XC51’s port bits (such as P1.0) which is configured as an input. This port bit is then polled to determine the status of

DRDY. The second scheme is to use an interrupt driven system in which case, the

DRDY

output is connected to the

INT1 input of the 8XC51. For

2

REV. C

–31–

AD7714

interfaces which require control of the

CS input on the AD7714, one of the port bits of the 8XC51 (such as P1.1), which is configured as an output, can be used to drive the

CS input.

8XC51

P3.0

P3.1

DV

DD

SYNC

RESET

POL

AD7714

DATA OUT

DATA IN

SCLK

outputs from the ADSP-2103/ADSP-2105 are active. The serial clock rate on the ADSP-2103/ADSP-2105 should be limited to

3␣ MHz to ensure correct operation with the AD7714.

DV

DD

RFS

TFS

ADSP-2103/2105

DR

DT

SCLK

SYNC

RESET

CS

AD7714

DATA OUT

DATA IN

SCLK

POL

CS

Figure 10. AD7714 to 8051 Interface

The 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a single data line. As a result, the

DATA OUT and DATA IN pins of the AD7714 should be connected together. The serial clock on the 8XC51 idles high between data transfers and, therefore, the POL input of the

AD7714 should be hard-wired to a logic high. The 8XC51 outputs the LSB first in a write operation while the AD7714 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register.

Similarly, the AD7714 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data that is read into the serial buffer needs to be rearranged before the correct data word from the AD7714 is available in the accumulator.

AD7714 to ADSP-2103/ADSP-2105 Interface

Figure 11 shows an interface between the AD7714 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface shown, the

DRDY bit of the Communications Register is again monitored to determine when the Data Register is updated. The alternative scheme is to use an interrupt driven system in which case, the

DRDY output is connected to the IRQ2 input of the

ADSP-2103/ADSP-2105. The

RFS and TFS pins of the

ADSP-2103/ADSP-2105 are configured as active low outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The POL pin of the AD7714 is hard-wired low. Because the SCLK from the ADSP-2103/

ADSP-2105 is a continuous clock, the

CS of the AD7714 must be used to gate off the clock once the transfer is complete. The

CS for the AD7714 is active when either the RFS or TFS

Figure 11. AD7714 to ADSP-2103/ADSP-2105 Interface

CODE FOR SETTING UP THE AD7714

Table XV gives a set of read and write routines in C code for interfacing the 68HC11 microcontroller to the AD7714. The sample program sets up the various registers on the AD7714 and reads 1000 samples from the part into the 68HC11. The setup conditions on the part are exactly the same as those outlined for the flowchart of Figure 8. In the example code given here the

DRDY output is polled to determine if a new valid word is available in the output register.

The sequence of the events in this program are as follows:

1. Write to the Communications Register, setting the channel.

2. Write to the Filter High Register, setting the 4 MSBs of the filter word and setting the part for 24-bit read, bipolar mode with boost off.

3. Write to the Filter Low Register, setting the 8 LSBs of the filter word.

4. Write to the Mode Register, setting the part for a gain of 1, burnout current off, no filter synchronization and initiating a self-calibration.

5. Poll the

DRDY Output.

6. Read the data from the Data Register.

7. Loop around doing steps 5 and 6 until the specified number of samples have been taken.

–32– REV. C

AD7714

Table XV. C Code for Interfacing AD7714 to 68HC11

/* This program has read and write routines for the 68HC11 to interface to the AD7714 and the sample program sets the various registers and then reads 1000 samples from the part. */

#include <math.h>

#include <io6811.h>

#define NUM_SAMPLES 1000 /* change the number of data samples */

#define MAX_REG_LENGTH 3 /* this says that the max length of a register is 3 bytes */

Writetoreg (int);

Read (int,char); char *datapointer = store; char store[NUM_SAMPLES*MAX_REG_LENGTH + 30]; void main()

{

/* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */ char a;

DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */

PORTC | = 0x04; /* make the /CS line high */

Writetoreg(0x27); /* set the channel AIN6/AIN6 and set the next operation as write to the filter high register */

Writetoreg(0x4f); /* set Bipolar mode, 24 bits, boost off, all 4 MSBs of filterword to 1 */

Writetoreg(0x37); /* set the next operation as a write to the filter low register */

Writetoreg(0xA0); /* max filter word allowed for low part of the filterword */

Writetoreg(0x17); /* set the operation as a write to the mode register */

Writetoreg(0x20); /* set gain to 1, burnout current off, no filter sync, and do a self calibration */ while(PORTC & 0x10); /* wait for /DRDY to go low */ for(a=0;a<NUM_SAMPLES;a++);

{

Writetoreg(0x5f); /*set the next operation for 24 bit read from the data register */

Read(NUM_SAMPES,3);

}

}

Writetoreg(int byteword);

{ int q;

SPCR = 0x3f;

SPCR = 0X7f; /* this sets the WiredOR mode(DWOM=1), Master mode(MSTR=1), SCK idles high(CPOL=1), /SS can be low always (CPHA=1), lowest clock speed(slowest speed which is master clock /32 */

DDRD = 0x18; /* SCK, MOSI outputs */ q = SPSR; q = SPDR; /* the read of the staus register and of the data register is needed to clear the interrupt which tells the user that the data transfer is complete */

PORTC &= 0xfb; /* /CS is low */

SPDR = byteword; /* put the byte into data register */ while(!(SPSR & 0x80)); /* wait for /DRDY to go low */

PORTC |= 0x4; /* /CS high */

}

Read(int amount, int reglength)

{ int q;

SPCR = 0x3f;

SPCR = 0x7f; /* clear the interupt */

DDRD = 0x10; /* MOSI output, MISO input, SCK output */ while(PORTC & 0x10); /* wait for /DRDY to go low */

PORTC & 0xfb ; /* /CS is low */ for(b=0;b<reglength;b++)

{

SPDR = 0; while(!(SPSR & 0x80)); /* wait until port ready before reading */

*datapointer++=SPDR; /* read SPDR into store array via datapointer */

}

PORTC|=4; /* /CS is high */

}

REV. C

–33–

2

AD7714

APPLICATIONS

The on-chip PGA allows the AD7714 to handle an analog input voltage range as low as 10 mV full-scale with V

REF

= +1.25␣ V.

The differential inputs of the part allow this analog input range to have an absolute value anywhere between AGND and AV

DD when the part is operated in unbuffered mode. It allows the user to connect the transducer directly to the input of the AD7714.

The programmable gain front end on the AD7714 allows the part to handle unipolar analog input ranges from 0 mV to

+20␣ mV to 0 V to +2.5␣ V and bipolar inputs of

±

20 mV to

±

2.5 V. Because the part operates from a single supply these bipolar ranges are with respect to a biased-up differential input.

Pressure Measurement

One typical application of the AD7714 is pressure measurement. Figure 12 shows the AD7714 used with a pressure transducer, the BP01 from Sensym. The pressure transducer is

OUT–

arranged in a bridge network and gives a differential output voltage between its OUT(+) and OUT(–) terminals. With rated full-scale pressure (in this case 300 mmHg) on the transducer, the differential output voltage is 3 mV/Volt of the input voltage

(i.e., the voltage between its IN(+) and IN(–) terminals).

Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The excitation voltage for the bridge is also used to generate the reference voltage for the

AD7714. Therefore, variations in the excitation voltage do not introduce errors in the system. Choosing resistor values of

24␣ k

and 15 k

as per the diagram give a 1.92 V reference voltage for the AD7714 when the excitation voltage is 5 V.

Using the part with a programmed gain of 128 results in the full scale input span of the AD7714 being 15 mV which corresponds with the output span from the transducer.

EXCITATION VOLTAGE = +5V

IN+

IN–

OUT+

24k

V

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

+5V

AV

DD

DV

DD

AV

DD

1

m

A

AD7714

AGND

1

m

A

BUFFER

PGA

CHARGE BALANCING A/D

CONVERTER

AUTO-ZEROED

SD

MODULATOR

DIGITAL

FILTER

A = 1–128

CLOCK

GENERATION

SERIAL INTERFACE

REGISTER BANK

REF IN (+)

STANDBY

SYNC

MCLK IN

MCLK OUT

RESET

DRDY

POL

15k

V

REF IN (–)

AGND

DGND

BUFFER

DOUT

DIN

CS SCLK

Figure 12. Pressure Measurement Using the AD7714

–34– REV. C

AD7714

Temperature Measurement

Another application area for the AD7714 is in temperature measurement. Figure 13 outlines a connection from a thermocouple to the AD7714. In this application, the AD7714 is operated in its buffered mode to allow large decoupling capacitors on the front end to eliminate any noise pickup which there may have been in the thermocouple leads. When the AD7714 is operated in buffered mode, it has a reduced common-mode range. In order to place the differential voltage from the thermocouple on a suitable common-mode voltage, the AIN2 input of the AD7714 is biased up at the reference voltage, +2.5␣ V.

THERMOCOUPLE

JUNCTION

+5V

+V

IN

AD780

V

OUT

GND

R

R

C

AIN1

AIN2

C

AIN3

AIN4

AIN5

AIN6

+5V

AV

DD

AV

DD

1

m

A

DV

DD

AD7714

AGND

1

m

A

BUFFER

PGA

CHARGE BALANCING A/D

CONVERTER

AUTO-ZEROED

SD

MODULATOR

DIGITAL

FILTER

A = 1–128

CLOCK

GENERATION

SERIAL INTERFACE

REGISTER BANK

REF IN (+)

STANDBY

SYNC

MCLK IN

MCLK OUT

REF IN (–)

AGND

DGND BUFFER

DOUT

DIN

CS

SCLK

DV

DD

Figure 13. Thermocouple Measurement Using the AD7714

RESET

DRDY

POL

2

REV. C

–35–

AD7714

RTD Measurement

Figure 14 shows another temperature measurement application for the AD7714. In this case, the transducer is an RTD (Resistive Temperature Device), a PT100. The arrangement is a 4lead RTD configuration. There are voltage drops across the lead resistances R

L1

and R

L4

but these simply shift the commonmode voltage. There is no voltage drop across lead resistances

R

L2

and R

L3

as the input current to the AD7714 is very low

.

The lead resistances present a small source impedance so it would not generally be necessary to turn on the buffer on the AD7714.

If the buffer is required, the common-mode voltage should be set accordingly by inserting a small resistance between the bottom end of the RTD and AGND of the AD7714. In the application shown an external 400␣

µ

A current source provides the excitation current for the PT100 and it also generates the reference voltage for the AD7714 via the 6.25 k

resistor. Variations in the excitation current do not affect the circuit as both the input voltage and the reference voltage vary ratiometrically with the excitation current. However, the 6.25␣ k

resistor must have a low temperature coefficient to avoid errors in the reference voltage over temperature.

RTD

R

L4

+5V

AV

DD

DV

DD

400

m

A

REF IN (+)

6.25k

V

REF IN (–)

R

L1

R

L2

AIN1

AIN2

R

L3

AV

DD

1

m

A

AGND

1

m

A

AD7714

BUFFER

PGA

CHARGE BALANCING A/D

CONVERTER

AUTO-ZEROED

SD

MODULATOR

DIGITAL

FILTER

A = 1–128

CLOCK

GENERATION

SERIAL INTERFACE

REGISTER BANK

AGND

DGND

BUFFER

DOUT DIN

CS

SCLK

Figure 14. RTD Measurement Using the AD7714

STANDBY

SYNC

MCLK IN

MCLK OUT

RESET

DRDY

POL

–36– REV. C

AD7714

Data Acquisition

The AD7714 with its three differential channels (or five pseudodifferential channels) is suited to low bandwidth, high resolution data acquisition systems. In addition, the three-wire digital interface allows this data acquisition front end to be isolated with just three optoisolators. The entire system can be operated from a single +3␣ V or +5 V supply provided that the input signals to the AD7714’s analog inputs are all of positive polarity.

The low power operation of the AD7714 ensures that very little power has to be brought across the isolation barrier. Figure 15 shows the AD7714 in an isolated data acquisition system.

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

+5V

+V

IN

AD780

V

OUT

GND

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

+5V

AV

DD

DV

DD

AV

DD

1

m

A

AD7714

AGND

1

m

A

BUFFER

PGA

CHARGE BALANCING A/D

CONVERTER

AUTO-ZEROED

SD

MODULATOR

DIGITAL

FILTER

A = 1–128

CLOCK

GENERATION

SERIAL INTERFACE

REGISTER BANK

REF IN (+)

STANDBY

SYNC

MCLK IN

MCLK OUT

RESET

DRDY

POL

REF IN (–)

AGND

DGND

BUFFER

DV

DD

DOUT DIN

CS

SCLK

MICROCONTROLLER OPTO-ISOLATORS

Figure 15. Data Acquisition System Using the AD7714

2

REV. C

–37–

AD7714

Smart Transmitters

Another area where the low power, single supply, three-wire interface capabilities is of benefit is in smart transmitters. Here, the entire smart transmitter must operate from the 4␣ mA to

20␣ mA loop. Tolerances in the loop mean that the amount of current available to power the transmitter is as low as 3.5␣ mA.

The AD7714 consumes only 500␣

µ

A, leaving 3␣ mA available for the rest of the transmitter. Figure 16 shows a block diagram of a smart transmitter which includes the AD7714. Not shown in

Figure 16 is the isolated power source required to power the front end.

SENSORS

RTD mV ohm

TC

AMBIENT

TEMP.

SENSOR

DV

DD

AV

DD

ISOLATED SUPPLY

AD7714

REF IN

MCLK

IN

VOLTAGE

REFERENCE

MCLK

OUT

DGND

AGND

ISOLATED GROUND

ISOLATION

BARRIER

MAIN TRANSMITTER ASSEMBLY

3V

VOLTAGE

REGULATOR

V

CC

VOLTAGE

REFERENCE

MICROCONTROLLER UNIT

*PID

*RANGE SETTING

*CALIBRATION

*LINEARIZATION

*OUTPUT CONTROL

*SERIAL COMMUNICATION

*HART PROTOCOL

COM

3V

D/A

CONVERTER

HART

MODEM

BELL 202

INPUT/OUTPUT

STAGE

SIGNAL

CONDITIONER

WAVEFORM

SHAPER

BANDPASS

FILTER

LOOP

RTN

4–20mA

COM

Figure 16. Smart Transmitter Using the AD7714

–38– REV. C

AD7714

PAGE INDEX

Topic Page

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . 1

AD7714-5 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 2

AD7714-3 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 7

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8

PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . 9

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

AD7714-5 OUTPUT NOISE . . . . . . . . . . . . . . . . . . . . . . . 11

AD7714-3 OUTPUT NOISE . . . . . . . . . . . . . . . . . . . . . . . 12

BUFFERED MODE NOISE . . . . . . . . . . . . . . . . . . . . . . . 13

ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 14

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Calibration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CALIBRATION OPERATIONS . . . . . . . . . . . . . . . . . . . . 18

CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 19

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Input Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Burnout Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REFERENCE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DIGITAL FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Post-Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

ANALOG FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

System-Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . 25

Background Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . . 26

USING THE AD7714 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 26

System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Evaluating the AD7714 Performance . . . . . . . . . . . . . . . . 28

DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CONFIGURING THE AD7714 . . . . . . . . . . . . . . . . . . . . . 30

MICROCOMPUTER/MICROPROCESSOR

INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AD7714 to 68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 31

AD7714 to 8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 31

AD7714 to ADSP-2103/ADSP-2105 Interface . . . . . . . . 32

REV. C

–39–

Topic Page

CODE FOR SETTING UP AD7714 . . . . . . . . . . . . . . . . . 32

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 35

RTD Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 40

TABLE INDEX

Table Title Page

Table Ia.

AD7714-5 Output Noise/Resolution vs. Gain

and First Notch for f

CLK IN

= 2.4576 MHz . . . 11

Table Ib.

AD7714-5 Output Noise/Resolution vs. Gain and First Notch for f

CLK IN

= 1 MHz . . . . . . . . 11

Table IIa.

AD7714-3 Output Noise/Resolution vs. Gain and First Notch for f

CLK IN

= 2.4576 MHz . . . . 12

Table IIb.

AD7714-3 Output Noise/Resolution vs. Gain and First Notch for f

CLK IN

= 1 MHz . . . . . . . . 12

Table III.

AD7714-5 Buffered Mode Output Noise/

Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table IV.

AD7714-3 Buffered Mode Output Noise/

Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table V.

Communications Register . . . . . . . . . . . . . . . . 14

Table VI.

Register Selection . . . . . . . . . . . . . . . . . . . . . . 14

Table VII.

Channel Selection . . . . . . . . . . . . . . . . . . . . . . 15

Table VIII. Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table IX.

Filter High Register . . . . . . . . . . . . . . . . . . . . . 17

Table X.

Filter Low Register . . . . . . . . . . . . . . . . . . . . . 17

Table XI.

Calibration Operations . . . . . . . . . . . . . . . . . . 18

Table XII.

External R, C for No 16-Bit Gain Error . . . . . 20

Table XIII. External R, C for No 20-Bit Gain Error . . . . . 20

Table XIV. Input Sampling Frequency vs. Gain . . . . . . . . 21

Table XV.

C Code for AD7714 to 68HC11 Interface . . . 33

2

AD7714

24

1

PIN 1

OUTLINE DIMENSIONS

Dimensions are shown in inches and (mm).

24-Lead Plastic DIP

(N-24)

1.228 (31.19)

1.226 (31.14)

13

12

0.260 ± 0.001

(6.61 ± 0.03)

0.32 (8.128)

0.30 (7.62)

0.130 (3.30)

0.128 (7.62)

24-Lead Thin Shrink Small Outline Package TSSOP

(RU-24)

24 13

1

0.311 (7.90)

0.303 (7.70)

12

0.02 (0.5)

0.019 (0.41)

0.11 (2.79)

0.016 (2.28)

0.07 (1.78)

0.05 (1.27)

SEATING

PLANE

15

8

0

0.011 (0.28)

0.009 (0.23)

NOTES:

1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH

2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN PLATED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

0.006 (0.15)

0.002 (0.05)

PIN 1

SEATING

PLANE

0.0256 (0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

0.0433

(1.10)

MAX

0.0079 (0.20)

8

8

0

8

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

24

1

24-Lead Wide Body SOIC

(R-24)

0.608 (15.45)

0.596 (15.13)

13

12

0.299 (7.6)

0.291 (7.39)

0.414 (10.52)

0.398 (10.10)

PIN 1

0.096 (204)

0.089 (2.26)

0.03 (0.76)

0.02 (0.51)

0.01 (0.254)

0.006 (0.15)

0.05 (1.27)

BSC

0.019 (0.49)

0.014 (0.35)

SEATING

PLANE

0.013 (0.32)

8

8

0

8

0.009 (0.23)

NOTES:

1. LEAD NO. 1 IDENTIFIED BY DOT.

2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

0.0500 (1.27)

0.0157 (0.40)

28

1

28-Lead Shrink Small Outline Package SSOP

(RS-28)

0.407 (10.34)

0.397 (10.08)

15

14

0.212 (5.38)

0.205 (5.207)

0.311 (7.9)

0.301 (7.64)

PIN 1 0.07 (1.79)

0.066 (1.67)

0.008 (0.203)

0.002 (0.050)

0.0256 (0.65)

BSC

SEATING

PLANE

0.009 (0.229)

8

8

0

8

0.005 (0.127)

0.03 (0.762)

0.022 (0.558)

NOTES:

1. LEAD NO. 1 IDENTIFIED BY DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

–40– REV. C

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