14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP AD7942 Data Sheet

14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP AD7942 Data Sheet
14-Bit, 250 kSPS PulSAR,
Pseudo Differential ADC in MSOP/LFCSP
AD7942
Data Sheet
FEATURES
APPLICATION DIAGRAM
0.5V TO 5V
14-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR)
SINAD: 85 dB at 20 kHz
THD: −100 dB at 20 kHz
Pseudo differential analog input range
0 V to VREF with VREF up to VDD
No pipeline delay
Single-supply 2.3 V to 5.5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Proprietary serial interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible1
Daisy-chaining for multiple ADCs and busy indicator
Power dissipation
1.25 mW at 2.5 V/100 kSPS, 3.6 mW at 5 V/100 kSPS
1.25 μW at 2.5 V/100 SPS
Standby current: 1 nA
10-lead package: MSOP and 3 mm × 3 mm LFCSP
Pin-for-pin compatible with the 16-bit AD7685
0V TO VREF
IN+
IN–
2.5V TO 5V
REF VDD VIO
SDI
AD7942
SCK
SDO
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
CNV
04657-001
GND
1.8V TO VDD
Figure 1.
GENERAL DESCRIPTION
The AD7942 is a 14-bit, charge redistribution, successive approximation PulSAR® ADC that operates from a single power supply,
VDD, between 2.3 V to 5.5 V. It contains a low power, high
speed, 14-bit sampling ADC with no missing codes, an internal
conversion clock, and a versatile serial interface port. The part
also contains a low noise, wide bandwidth, short aperture delay
track-and-hold circuit. On the CNV rising edge, it samples an
analog input, IN+, between 0 V to VREF with respect to a ground
sense, IN−. The reference voltage, VREF, is applied externally and
is set up to be the supply voltage. Its power scales linearly with
the throughput.
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process controls
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using a separate
supply (VIO).
The AD7942 is housed in a 10-lead MSOP or a 10-lead LFCSP
package yet fits in the same size footprint as the 8-lead MSOP
or SOT-23. Operation for the AD7942 is specified from −40°C
to +85°C.
1
Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP/SOT-23, 14-/16-/18-Bit ADCs
Type
14-Bit
16-Bit
100 kSPS
AD7940
AD7680
AD7683
AD7684
18-Bit
1
250 kSPS
AD79421
AD76851
AD76871
AD7694
AD76911
400 kSPS to 500 kSPS
AD79461
AD76861
AD76881
AD76931
AD76901
≥1000 kSPS
ADC Driver
AD79801
AD79831
ADA4941-x
ADA4841-x
AD79821
AD79841
ADA4941-x
ADA4841-x
Pin-for-pin compatible to the AD7942.
Rev. C
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AD7942
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .................................................................................... 12
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 13
Application Diagram ........................................................................ 1
Circuit Information.................................................................... 13
General Description ......................................................................... 1
Converter Operation.................................................................. 13
Revision History ............................................................................... 2
Typical Connection Diagram ................................................... 14
Specifications..................................................................................... 3
Digital Interface .......................................................................... 16
Timing Specifications .................................................................. 5
Application Hints ........................................................................... 23
Absolute Maximum Ratings............................................................ 7
Layout .......................................................................................... 23
ESD Caution .................................................................................. 7
Evaluating the Performance of AD7942.................................. 23
Pin Configuration and Function Descriptions ............................. 8
Outline Dimensions ....................................................................... 24
Typical Performance Characteristics ............................................. 9
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/14—Rev. B to Rev. C
Changed QFN (LFCSP) Notation to LFCSP .............. Throughout
Added Patent Footnote .................................................................... 1
Changes to Evaluating the Performance of the AD7942 ........... 23
Changes to Ordering Guide .......................................................... 24
6/08—Rev. A to Rev. B
Changes to Features Section and General Description Section . 1
Moved Figure 2 and Figure 3 .......................................................... 6
Changes to Table 6 ............................................................................ 8
Moved Terminology Section ......................................................... 12
Changes to Figure 41 ...................................................................... 22
Changes to Ordering Guide .......................................................... 24
12/07—Rev. 0 to Rev. A
Changes to Table 1.............................................................................1
Changes to General Description Section .......................................1
Changes to Table 6.............................................................................7
Changes to Table 7.............................................................................8
Changes to Circuit Information Section ..................................... 13
Changes to Table 9.......................................................................... 15
Changes to Figure 39...................................................................... 21
Changes to Figure 41...................................................................... 22
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
3/05—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
AD7942
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current
Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
Offset Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise and Distortion Ratio (SINAD)
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
Conditions
Min
14
IN+ − IN−
IN+
IN−
fIN = 250 kHz
TA = 25°C, acquisition phase
0
−0.1
−0.1
Typ
Max
Unit
Bits
VREF
VDD + 0.1
+0.1
V
V
V
dB
nA
65
1
See the Analog Input section
14
−0.7
−1
VREF = VDD = 5 V
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
VDD = 5 V ± 5%
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
Full-scale step
0
0
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz
fIN = 20 kHz
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 5 V, −60 dB input
fIN = 20 kHz, VREF = 2.5 V
84.5
83
±0.3
±0.4
0.33
±0.7
±1
±0.45
±0.75
±2.5
±0.1
+0.7
+1
±6
±3
±4.5
250
200
1.8
kSPS
kSPS
μs
dB3
dB
dB
dB
dB
dB
dB
85
84
−100
−100
85
25
84
0.5
Bits
LSB1
LSB
LSB
LSB
ppm/°C
mV
mV
ppm/°C
LSB
250 kSPS, VREF = 5 V
50
V
μA
VDD = 5 V
2
2.5
MHz
ns
–0.3
0.7 × VIO
−1
−1
Rev. C | Page 3 of 24
VDD + 0.3
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
μA
μA
AD7942
Data Sheet
Parameter
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Conditions
Min
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current4, 5
Power Dissipation
ISINK = +500 μA
ISOURCE = −500 μA
Serial 14 bits straight binary
Conversion results available
immediately after
completed conversion
0.4
VIO − 0.3
TEMPERATURE RANGE6
Specified Performance
Specified performance
Specified performance
2.3
2.3
1.8
VDD and VIO = 5 V, at 25°C
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 200 kSPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 250 kSPS throughput
TMIN to TMAX
1
Typ
1
1.25
1.25
2.5
3.6
−40
Max
5.5
VDD + 0.3
VDD + 0.3
50
Unit
V
V
2
4
5
12.5
V
V
V
nA
μW
mW
mW
mW
mW
+85
°C
LSB means least significant bit. With a 5 V input range, 1 LSB = 305.2 μV.
See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
All specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
With all digital inputs forced to VIO or GND as required.
5
During acquisition phase.
6
Contact Analog Devices, Inc., sales for an extended temperature range.
2
3
Rev. C | Page 4 of 24
Data Sheet
AD7942
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V1, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 3.
Parameter
Conversion Time: CNV Rising Edge to Available Data
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO ≥ 4.5 V
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data-Valid Delay
VIO ≥ 4.5 V
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
CNV or SDI Low to SDO D13 MSB Valid (CS Mode)
VIO ≥ 4.5 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO ≥ 4.5 V
VIO ≥ 2.3 V
1
See Figure 2 and Figure 3 for load conditions.
Rev. C | Page 5 of 24
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
1.8
4
10
15
Typ
Max
2.2
17
18
19
20
7
7
5
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
ns
ns
ns
ns
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
26
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
5
3
4
AD7942
Data Sheet
VDD = 2.3 V to 4.5 V1, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO ≥ 3 V
VIO ≥ 2.7 V
VIO ≥ 2.3 V
CNV or SDI Low to SDO D13 MSB Valid (CS Mode)
VIO ≥ 2.7 V
VIO ≥ 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Timing Diagrams
IOL
1.4V
TO SDO
04657-002
CL
50pF
500µA
IOH
Figure 2. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
2V OR VIO – 0.5V1
2V OR VIO – 0.5V1
0.8V OR 0.5V2
0.8V OR 0.5V2
NOTES
1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Reference Levels for Timing
Rev. C | Page 6 of 24
04657-003
tDELAY
Typ
Max
3.2
29
35
40
12
12
5
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
24
30
35
ns
ns
ns
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
See Figure 2 and Figure 3 for load conditions.
500µA
Min
0.7
1.8
5
10
25
30
0
5
8
5
4
36
Data Sheet
AD7942
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs
IN+1, IN−1
REF
Supply Voltages
VDD and VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
10-Lead MSOP
10-Lead LFCSP_WD
θJC Thermal Impedance
10-Lead MSOP
10-Lead LFCSP_WD
Lead Temperature
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
200°C/W
48.7°C/W
44°C/W
2.96°C/W
215°C
220°C
See the Analog Input section.
Rev. C | Page 7 of 24
AD7942
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10 VIO
9
SDI
8
SCK
IN– 4
7
SDO
GND 5
6
CNV
IN+ 3
AD7942
NOTES
1. PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
04657-004
REF 1
VDD 2
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type1
AI
2
3
VDD
IN+
P
AI
4
5
6
IN−
GND
CNV
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
1
Description
Reference Input Voltage. The VREF range is from 0.5 V to VDD. REF is referred to the GND pin. Decouple REF
as closely as possible to a 10 μF capacitor.
Power Supply.
Analog Input. IN+ is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V
to VREF.
Analog Input Ground Sense. Connect IN− to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input pin has multiple functions. On its leading edge, CNV initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, CNV enables the SDO pin
when low. In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. C | Page 8 of 24
Data Sheet
AD7942
TYPICAL PERFORMANCE CHARACTERISTICS
1.00
1.00
POSITIVE INL = +0.22LSB
NEGATIVE INL = –0.34LSB
0.50
0.50
0.25
0.25
–0.25
0
–0.25
–0.50
–0.75
–0.75
04657-005
–0.50
0
4096
8192
CODE
12,288
04657-008
0
–1.00
POSITIVE DNL = +0.24LSB
NEGATIVE DNL = –0.12LSB
0.75
DNL (LSB)
INL (LSB)
0.75
–1.00
16,384
0
Figure 5. Integral Nonlinearity vs. Code
4096
8192
CODE
12,288
16,384
Figure 8. Differential Nonlinearity vs. Code
150,000
150,000
VDD = VREF = 2.5V
129,941
VDD = VREF = 5V
131,072
100,000
COUNTS
COUNTS
100,000
50,000
0
1FFE
915
216
1FFF
2000
2001
CODE IN HEX
0
2002
0
0
2003
0
0
0
1FFF
2000
2001
CODE IN HEX
2002
0
2003
0
0
16,384 POINT FFT
VDD = VREF = 5V
fS = 250kSPS
fIN = 20.43kHz
SNR = 85.1dB
THD = –105dB
SFDR = –105.9dB
–60
–80
–100
–120
–140
0
25
50
75
FREQUENCY (kHz)
100
–60
–80
–100
–120
–140
–160
04657-007
–160
–40
04657-010
–40
16,384 POINT FFT
VDD = VREF = 2.5V
fS = 250kSPS
fIN = 20.43kHz
SNR = 84.2dB
THD = –101.7dB
SFDR = –104.3dB
–20
AMPLITUDE (dB of Full Scale)
–20
AMPLITUDE (dB of Full Scale)
0
1FFE
Figure 9. Histogram of a DC Input at the Code Center
Figure 6. Histogram of a DC Input at the Code Center
–180
0
1FFD
04657-009
0
1FFD
04657-006
0
50,000
–180
125
0
25
50
75
FREQUENCY (kHz)
Figure 10. FFT Plot
Figure 7. FFT Plot
Rev. C | Page 9 of 24
100
125
AD7942
Data Sheet
15.0
86
–80
SNR
–85
82
2.0
2.5
5.0
13.0
5.5
VREF = 5V, –1dB
–100
–105
13.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
–95
–110
04657-014
ENOB
83
THD (dB)
14.0
ENOB (Bits)
SINAD
84
–90
04657-011
SNR, SINAD (dB)
VREF = 2.5V, –1dB
14.5
85
–115
0
40
Figure 11. SNR, SINAD, and ENOB vs. Reference Voltage
80
120
FREQUENCY (kHz)
160
200
Figure 14. THD vs. Frequency
–90
90
VREF = 5V, –10dB
–100
VREF = 5V, –1dB
VREF = 2.5V
THD (dB)
SINAD (dB)
85
80
VREF = 2.5V, –1dB
VREF = 5V
–110
0
50
100
FREQUENCY (kHz)
150
–120
–55
200
04657-015
70
04657-012
75
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 15. THD vs. Temperature
Figure 12. SINAD vs. Frequency
95
1000
fS = 100kSPS
85
VREF = 2.5V
80
75
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 13. SNR vs. Temperature
750
VDD
500
250
04657-016
OPERATING CURRENTS (μA)
VREF = 5V
04657-013
SNR (dB)
90
VIO
0
2.3
2.7
3.1
3.5
3.9
4.3
SUPPLY (V)
4.7
Figure 16. Operating Currents vs. Supply
Rev. C | Page 10 of 24
5.1
5.5
Data Sheet
AD7942
1000
6
500
VDD + VIO
250
0
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
4
3
2
1
–1
–2
–4
–5
–6
–55
125
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
25
VDD = 2.5V, 85°C
20
VDD = 5V
600
VDD = 2.5V
500
400
300
VDD = 2.5V, 25°C
10
VDD = 5V, 85°C
VDD = 5V, 25°C
5
200
100
0
–55
15
VIO
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
VDD = 3.3V, 85°C
04657-020
tDSDO DELAY (ns)
700
04657-018
OPERATING CURRENTS (µA)
800
–35
Figure 19. Offset Error and Gain Error vs. Temperature
fS = 100kSPS
900
GAIN ERROR
–3
Figure 17. Power-Down Currents vs. Temperature
1000
OFFSET ERROR
0
04657-019
OFFSET AND GAIN ERROR (LSB)
750
04657-017
POWER-DOWN CURRENTS (nA)
5
VDD = 3.3V, 25°C
0
125
Figure 18. Operating Currents vs. Temperature
0
20
40
60
80
SDO CAPACITIVE LOAD (pF)
100
120
Figure 20. tDSDO Delay vs. SDO Capacitance Load and Supply
Rev. C | Page 11 of 24
AD7942
Data Sheet
TERMINOLOGY
Linearity Error or Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (152.6 μV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the
ideal level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels, between the rms amplitude of the
input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula and is
expressed in bits as follows:
ENOB = (SINADdB − 1.76)/6.02
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
Rev. C | Page 12 of 24
Data Sheet
AD7942
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
REF
8192C
4096C
LSB
4C
2C
C
SW+
C
BUSY
COMP
GND
8192C
4096C
4C
2C
C
MSB
CONTROL
LOGIC
OUTPUT CODE
C
LSB
SW–
04657-021
CNV
IN–
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7942 is a fast, low power, single-supply, precise 14-bit
ADC using successive approximation architecture.
The AD7942 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
1.25 μW with a 2.5 V power supply, which is ideal for batterypowered applications.
The AD7942 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7942 is specified from 2.3 V to 5.5 V and can be interfaced to a 1.8 V, 2.5 V, 3.3 V, or 5 V digital logic. It is housed in
a 10-lead MSOP or a tiny 10-lead LFCSP that is space saving,
yet allows flexible configurations. It is pin-for-pin-compatible
with the 16-bit ADC AD7685.
CONVERTER OPERATION
The AD7942 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase starts, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs (IN+ and IN−) captured at the end of the
acquisition phase, is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4 ... VREF/16,384). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7942 has an on-board conversion clock, the
serial clock is not required for the conversion process.
Rev. C | Page 13 of 24
AD7942
Data Sheet
(NOTE 1)
5V
REF
10µF
(NOTE 2)
100nF
1.8V TO VDD
100nF
REF
33Ω
VDD
IN+
0V TO VREF
AD7942
2.7nF
(NOTE 3)
IN–
(NOTE 4)
GND
VIO
SDI
SCK
3- OR 4-WIRE INTERFACE (NOTE 5)
SDO
CNV
04657-022
NOTE 1: SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
NOTE 2: CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 22. Typical Application Diagram
Transfer Functions
TYPICAL CONNECTION DIAGRAM
The ideal transfer characteristic for the AD7942 is shown in
Figure 23 and Table 7.
Figure 22 shows an example of the recommended connection
diagram for the AD7942 when multiple supplies are available.
ADC CODE (STRAIGHT BINARY)
Analog Input
Figure 24 shows an equivalent circuit of the input structure of
the AD7942.
111...111
111...110
111...101
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to become forwardbiased and to start conducting current. However, these diodes
can handle a forward-biased current of 130 mA maximum. For
instance, these conditions could eventually occur when the
input buffer (U1) supplies are different from VDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.
000...010
000...000
–FS
–FS + 1 LSB
+FS – 1 LSB
+FS – 1.5 LSB
–FS + 0.5 LSB
ANALOG INPUT
04657-023
000...001
VDD
Figure 23. ADC Ideal Transfer Function
1
2
CPIN
Digital Output Code
Hexadecimal
0x3FFF1
0x2001
0x2000
0x1FFF
0x0001
0x00002
RIN
CIN
D2
04657-024
Description
FSR – 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
Analog Input
VREF = 5 V
4.999695 V
2.500305 V
2.5 V
2.499695 V
305.2 μV
0V
D1
IN+
OR IN–
Table 7. Output Codes and Ideal Input Voltages
GND
Figure 24. Equivalent Analog Input Circuit
This is also the code for an overranged analog input (VIN+ – VIN− > VREF – VGND).
This is also the code for an underranged analog input (VIN+ – VIN− < VGND).
This analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this differential
input, small signals common to both inputs are rejected, as
shown in Figure 25, which represents the typical CMRR over
frequency. For instance, by using IN− to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated.
Rev. C | Page 14 of 24
Data Sheet
AD7942
80
Driver Amplifier Choice
VDD = 5V
Although the AD7942 is easy to drive, the driver amplifier
needs to meet the following requirements:
CMRR (dB)
70

The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7942. Note that the AD7942
produces much less noise than most other 14-bit ADCs
and therefore can be driven by a noisier op amp while
preserving the same or better system performance. The
noise coming from the driver is filtered by the AD7942
analog input circuit, 1-pole, low-pass filter made by RIN
and CIN or by the external filter, if one is used.

For ac applications, the driver needs to have a THD
performance suitable to that of the AD7942. Figure 14
gives the THD vs. frequency that the driver should exceed.

For multichannel multiplexed applications, the driver
amplifier and the AD7942 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
14-bit level (0.006%). In the amplifier data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 14-bit level
and should be verified prior to driver selection.
60
40
04657-025
50
1
10
100
FREQUENCY (kHz)
1000
10000
Figure 25. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
input, IN+, can be modeled as a parallel combination of the
Capacitor CPIN and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 3 kΩ and is a lumped component made up of some serial
resistors and the on resistance of the switches. CIN is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, when the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter
that reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7942 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic
distortion (THD). The dc performances are less sensitive to the
input impedance. The maximum source impedance depends on
the amount of THD that can be tolerated. The THD degrades as
a function of the source impedance and the maximum input
frequency, as shown in Figure 26.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841
AD8021
AD8022
OP184
AD8605, AD8615
AD8519
AD8031
Typical Application
Very low noise, small, and low power
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single supply, low power
Small, low power, and low frequency
High frequency and low power
–70
Voltage Reference Input
–75
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
–80
RS = 1kΩ
–90
RS = 500Ω
–95
–100
–105
RS = 50Ω
RS = 15Ω
–110
–115
When REF is driven by a very low impedance source (for example,
a reference buffer using the AD8031 or the AD8605), a 10 μF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
RS = 250Ω
RS = 100Ω
0
04657-026
THD (dB)
–85
25
50
FREQUENCY (kHz)
75
100
Figure 26. THD vs. Analog Input Frequency and Source Resistance
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance, using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values
≥ 2.2 μF can be used with a minimal impact on performance,
especially on DNL.
Rev. C | Page 15 of 24
AD7942
Data Sheet
The AD7942 is specified over a wide operating range from
2.3 V to 5.5 V. It has, unlike other low voltage converters, a
noise low enough to design a low supply (2.5 V) 14-bit resolution system with respectable performance. It uses two power
supply pins: a core supply, VDD, and a digital input/output
interface supply, VIO. VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD can be tied together. The AD7942 is independent of power supply sequencing between VIO and VDD.
Additionally, it is insensitive to power supply variations over
a wide frequency range, as shown in Figure 27.

A reference voltage with enough current output capability,
such as the ADR43x, or

A reference buffer, such as the AD8031, that can also filter
the system power supply (see Figure 29).
5V
5V
10Ω
5V
10kΩ
1µF
AD8031
1µF
10µF
(NOTE 1)
REF
VDD
VIO
AD7942
90
VDD = 5V
85
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 29. Example of Application Circuit
PSRR (dB)
80
DIGITAL INTERFACE
75
Although the AD7942 has a reduced number of pins, it offers
flexibility in its serial interface modes.
70
65
04657-027
60
55
10
100
1000
FREQUENCY (kHz)
10000
Figure 27. PSRR vs. Frequency
The AD7942 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 28. This makes the part
ideal for low sampling rates (even rates of a few hertz) and low
battery-powered applications.
0
VDD = 2.5V
10
0.1
10
100
1000
10000
SAMPLING RATE (SPS)
100000
The busy indicator feature is enabled as follows:
1000000
Figure 28. Operating Current vs. Sampling Rate
Supplying the ADC from the Reference
For simplified applications, the AD7942, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 29. The reference line can be driven by either

When in chain mode, the AD7942 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on
a single data line similar to a shift register.
In either mode, the AD7942 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior
to readback.
VIO
04657-028
OPERATING CURRENT (µA)
VDD = 5V
When in CS mode, the AD7942 is compatible with SPI, QSPI,
digital hosts, and DSPs (for example, Blackfin® ADSP-BF53x or
ADSP-219x). A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections, which is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
conversions, to be independent of the readback timing (SDI).
This is useful in low jitter sampling or simultaneous sampling
applications.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
1000
0.001
04657-029
Power Supply

In the CS mode, if CNV or SDI is low when the ADC
conversion ends (see Figure 33 and Figure 37).

In the chain mode, if SCK is high during the CNV rising
edge (see Figure 41).
The system power supply directly,
Rev. C | Page 16 of 24
Data Sheet
AD7942
minimum conversion time and held high until the maximum
conversion time to avoid generating the busy signal indicator.
When the conversion is complete the AD7942 enters the acquisition phase and powers down. When CNV goes low, the MSB
is output onto SDO. The remaining data bits are then clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
14th SCK falling edge or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CS Mode 3-Wire Without Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 30 and the corresponding timing
diagram is shown in Figure 31.
With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues to completion irrespective of the state of CNV. For instance, it is useful to bring
CNV low to select other SPI devices, such as analog
multiplexers. However, CNV must be returned high before the
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7942
DATA IN
SDO
04657-030
SCK
CLK
Figure 30. CS Mode 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
12
tHSDO
14
tSCKH
tDSDO
tEN
SDO
13
D13
D12
D11
tDIS
D1
D0
Figure 31. CS Mode 3-Wire Without Busy Indicator, Serial Interface Timing (SDI High)
Rev. C | Page 17 of 24
04657-031
SCK
AD7942
Data Sheet
CS Mode 3-Wire with Busy Indicator
low until the maximum conversion time to guarantee the
generation of the busy signal indicator. When the conversion
is complete, SDO goes from high impedance to low impedance.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7942 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After
the optional 15th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input. The connection diagram is shown in Figure 32 and the
corresponding timing diagram is shown in Figure 33.
With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance.
SDO is maintained in high impedance until the completion of
the conversion irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other
SPI devices, such as analog multiplexers. However, CNV must
be returned low before the minimum conversion time and held
CONVERT
VIO
CNV
VIO
AD7942
DATA IN
SDO
SCK
IRQ
04657-032
SDI
DIGITAL HOST
47kΩ
CLK
Figure 32. CS Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
tHSDO
13
14
15
tSCKH
tDSDO
SDO
tDIS
D13
D12
D1
D0
Figure 33. CS Mode 3-Wire with Busy Indicator, Serial Interface Timing (SDI High)
Rev. C | Page 18 of 24
04657-033
SCK
Data Sheet
AD7942
CS Mode 4-Wire Without Busy Indicator
enters the acquisition phase and powers down. Each ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK driving edges. The data is valid on
both SCK edges. Although the nondriving edge can be used to
capture the data, a digital host also using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when SDI goes high,
whichever is earlier, SDO returns to high impedance and
another AD7942 can be read.
This mode is most often used when multiple AD7942s are
connected to an SPI-compatible digital host. A connection
diagram using two AD7942s is shown in Figure 34 and the
corresponding timing diagram is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers.
However, SDI must be returned high before the minimum
conversion time elapses and held high until the maximum
conversion time is completed to avoid generating the busy
signal indicator. When the conversion is complete, the AD7942
If multiple AD7942s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CS2
CS1
CONVERT
CNV
SDI
AD7942
DIGITAL HOST
CNV
SDO
SDI
SCK
AD7942
SDO
SCK
04657-034
DATA IN
CLK
Figure 34. CS Mode 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI (CS1)
tHSDICNV
SDI (CS2)
tSCK
tSCKL
SCK
1
2
3
12
tHSDO
14
15
16
26
27
28
tSCKH
tDSDO
tEN
D13
D12
D11
tDIS
D1
D0
D13
D12
D1
D0
04657-035
SDO
13
Figure 35. CS Mode 4-Wire Without Busy Indicator, Serial Interface Timing
Rev. C | Page 19 of 24
AD7942
Data Sheet
CS Mode 4-Wire with Busy Indicator
but SDI must be returned low before the minimum conversion
time elapses and held low until the maximum conversion time
is completed to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low. With a pull-up on the SDO line this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7942 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK driving edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host also using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 15th SCK falling edge
or SDI going high, whichever is earlier, the SDO returns to high
impedance.
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input and to keep CNV (which is used to sample the analog
input) independent of the signal used to select the data reading.
This requirement is particularly important in applications where
low jitter on CNV is desired. The connection diagram is shown
in Figure 36 and the corresponding timing diagram is given in
Figure 37.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
CS1
CONVERT
VIO
CNV
AD7942
DATA IN
SDO
SCK
IRQ
04657-036
SDI
DIGITAL HOST
47Ω
CLK
Figure 36. CS Mode 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
2
3
tHSDO
13
14
15
tSCKH
tDSDO
tDIS
tEN
SDO
D13
D12
D1
Figure 37. CS Mode 4-Wire with Busy Indicator, Serial Interface Timing
Rev. C | Page 20 of 24
D0
04657-037
SCK
Data Sheet
AD7942
Chain Mode Without Busy Indicator
and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first and 14 × N clocks are
required to readback the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture
the data, a digital host also using the SCK falling edge allows
a faster reading rate and consequently more AD7942s in the
chain, provided the digital host has an acceptable hold time.
The maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host setup time
and 3 V interface, up to eight AD7942s running at a conversion
rate of 220 kSPS can be daisy-chained on a 3-wire port.
This mode can be used to daisy-chain multiple AD7942s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register. A connection diagram example using
two AD7942s is shown in Figure 38 and the corresponding
timing diagram is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, selects the
chain mode, and disables the busy indicator. In this mode, CNV
is held high during the conversion phase and the subsequent
data readback. When the conversion is complete, the MSB is
output onto SDO and the AD7942 enters the acquisition phase
CONVERT
CNV
AD7942
A
SDO
DIGITAL HOST
AD7942
SDI
SCK
DATA IN
SDO
B
SCK
04657-038
SDI
CNV
CLK
Figure 38. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
tHSCKCNV
2
3
12
13
tSSDISCK
14
15
16
DA13
DA12
26
27
28
DA1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDIB
DA13
DA12
DA11
DA1
DA0
DB13
DB12
DB11
DB1
DB0
tHSDO
tDSDO
SDOB
Figure 39. Chain Mode Without Busy Indicator, Serial Interface Timing
Rev. C | Page 21 of 24
04657-039
ACQUISITION
tCONV
AD7942
Data Sheet
Chain Mode with Busy Indicator
can be used as a busy indicator to trigger the data readback
controlled by the digital host. The AD7942 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 14 × N + 1
clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host also
using the SCK falling edge allows a faster reading rate and
consequently more AD7942s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 5 ns digital
host setup time and a 3 V interface, up to eight AD7942s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
This mode can also be used to daisy-chain multiple AD7942s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data
readback is analogous to clocking a shift register. A connection
diagram example using three AD7942s is shown in Figure 40
and the corresponding timing diagram is given in Figure 41.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, SDO in the near end ADC
(ADC C in Figure 40) is driven high. This transition on SDO
CONVERT
CNV
CNV
AD7942
AD7942
AD7942
A
SDI
SDO
B
SDO
SDI
SCK
SCK
C
DIGITAL HOST
DATA IN
SDO
IRQ
SCK
04657-040
SDI
CNV
CLK
Figure 40. Chain Mode with Busy Indicator Connection Diagram
tCYC
ACQUISITION
tCONV
tACQ
ACQUISITION
CONVERSION
tSSCKCNV
SCK
tHSCKCNV
tSCKH
1
tEN
2
tSSDISCK
SDOA = SDIB
3
4
tSCK
13
14
tHSDISCK
DA13 DA12 DA11
15
16
17
27
28
29
31
35
DA1
tDSDOSDI
DB13 DB12 DB11
DB1
DB0 DA13 DA12
DA1
DA0
DC13 DC12 DC11
DC1
DC0 DB13 DB12
DB1
DB0 DA13 DA12
tDSDOSDI
tDSDOSDI
SDOC
43
42
DA0
tHSDO
tDSDO
SDOB = SDIC
41
tDSDOSDI
tSCKL
Figure 41. Chain Mode with Busy Indicator, Serial Interface Timing
Rev. C | Page 22 of 24
DA1
DA0
04657-041
CNV = SDIA
Data Sheet
AD7942
APPLICATION HINTS
LAYOUT
Design the PCB that houses the AD7942 so that the analog and
digital sections are separated and confined to certain areas of
the board. The pinout of the AD7942, with all its analog signals
on the left side and all its digital signals on the right side, eases
this task.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the case of being
split, the ground plane should be joined underneath the AD7942.
04657-042
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7942 is used as a shield. Fast switching signals, such as
CNV or clocks, should never run near analog signal paths.
Avoid crossover of digital and analog signals.
Figure 42. Layout Example (Top Layer)
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is accomplished by placing the reference
decoupling ceramic capacitor close to, and ideally right up
against, the REF and GND pins. Connect these pins with wide,
low impedance traces.
04657-043
Finally, decouple the power supply of the AD7942, VDD and
VIO, with ceramic capacitors, typically 100 nF, placed close to
the AD7942. Connect the capacitors using short and large
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines. An example of layout
following these rules is shown in Figure 42 and Figure 43.
EVALUATING THE PERFORMANCE OF AD7942
Other recommended layouts for the AD7942 are outlined in
the evaluation board for the AD7942 (EVAL-AD7942SDZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-SDP-CB1Z.
Rev. C | Page 23 of 24
Figure 43. Layout Example (Bottom Layer)
AD7942
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
3.10
3.00
2.90
1
5
5.15
4.90
4.65
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.05
0.33
0.17
SEATING
PLANE
0.80
0.60
0.40
8°
0°
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 44. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
0.30
0.23
0.18
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
*EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
5
TOP VIEW
0.80 MAX
0.55 NOM
0.80
0.75
0.70
SEATING
PLANE
1
2.48
2.38
2.23
0.05 MAX
0.02 NOM
0.20 REF
PIN 1
INDICATOR
(R 0.20)
*PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES.
031208-B
3.00
BSC SQ
Figure 45. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very, Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3
AD7942BRMZ
AD7942BRMZ-RL7
AD7942BCPZRL
AD7942BCPZRL7
EVAL-AD7942SDZ
EVAL-SDP-CB1Z
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
Evaluation Board
Controller Board
1
Ordering Quantity
Tube, 50
Reel, 1,000
Reel, 5,000
Reel, 1,500
Package Option
RM-10
RM-10
CP-10-9
CP-10-9
Z = RoHS Compliant Part.
The EVAL-AD7942SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3
The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
2
©2005–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04657-0-6/14(C)
Rev. C | Page 24 of 24
Branding
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