14-Bit, 8-Channel, 250 kSPS PulSAR ADC AD7949 Data Sheet

14-Bit, 8-Channel, 250 kSPS PulSAR ADC AD7949 Data Sheet

Data Sheet

FEATURES

14-bit resolution with no missing codes

8-channel multiplexer with choice of inputs

Unipolar single-ended

Differential (GND sense)

Pseudobipolar

Throughput: 250 kSPS

INL/DNL: ±0.5/±0.25 LSB typical

SINAD: 85 dB @ 20 kHz

THD: −100 dB @ 20 kHz

Analog input range: 0 V to V

REF

with V

REF

up to VDD

Multiple reference types

Internal selectable 2.5 V or 4.096 V

External buffered (up to 4.096 V)

External (up to VDD)

Internal temperature sensor (TEMP)

Channel sequencer, selectable 1-pole filter, busy indicator

No pipeline delay, SAR architecture

Single-supply 2.3 V to 5.5 V operation with

1.8 V to 5.5 V logic interface

Serial interface compatible with SPI, MICROWIRE,

QSPI, and DSP

Power dissipation

2.9 mW @ 2.5 V/200 kSPS

10.8 mW @ 5 V/250 kSPS

Standby current: 50 nA

20-lead 4 mm × 4 mm LFCSP package

APPLICATIONS

Multichannel system monitoring

Battery-powered equipment

Medical instruments: ECG/EKG

Mobile communications: GPS

Power line monitoring

Data acquisition

Seismic data acquisition systems

Instrumentation

Process control

14-Bit, 8-Channel,

250 kSPS PulSAR ADC

AD7949

FUNCTIONAL BLOCK DIAGRAM

0.5V TO VDD – 0.5V

0.1µF

0.5V TO VDD

10µF

2.3V TO 5.5V

REFIN REF VDD

BAND GAP

REF

TEMP

SENSOR

AD7949

VIO

1.8V

TO

VDD

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

MUX

14-BIT SAR

ADC

ONE-POLE

LPF

SEQUENCER

SPI SERIAL

INTERFACE

CNV

SCK

SDO

DIN

GND

Figure 1.

Table 1. Multichannel 14-/16-Bit PulSAR® ADCs

Type Channels

14-Bit 8

250 kSPS

AD7949

500 kSPS ADC

ADA4841-1

16-Bit 4

16-Bit 8

AD7682 ADA4841-1

AD7689 AD7699

GENERAL DESCRIPTION

The AD7949 is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply, VDD.

The AD7949 contains all components for use in a multichannel, low power data acquisition system, including a true 14-bit SAR

ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as singleended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

The AD7949 uses a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput.

The AD7949 is housed in a tiny 20-lead LFCSP with operation specified from −40°C to +85°C.

Rev. E

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Technical Support www.analog.com

AD7949

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Timing Specifications .................................................................. 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 14

Overview ...................................................................................... 14

Converter Operation .................................................................. 14

Transfer Functions...................................................................... 15

Typical Connection Diagrams .................................................. 16

Analog Inputs .............................................................................. 17

Driver Amplifier Choice ............................................................ 19

Data Sheet

Voltage Reference Output/Input .............................................. 19

Power Supply ............................................................................... 21

Supplying the ADC from the Reference .................................. 21

Digital Interface .............................................................................. 22

Reading/Writing During Conversion, Fast Hosts .................. 22

Reading/Writing After Conversion, Any Speed Hosts .......... 22

Reading/Writing Spanning Conversion, Any Speed Host .... 23

Configuration Register, CFG .................................................... 23

General Timing Without a Busy Indicator ............................. 25

General Timing with a Busy Indicator .................................... 26

Channel Sequencer .................................................................... 27

Read/Write Spanning Conversion Without a Busy

Indicator ...................................................................................... 28

Read/Write Spanning Conversion with a Busy Indicator ..... 30

Application Hints ........................................................................... 31

Layout .......................................................................................... 31

Evaluating AD7949 Performance ............................................. 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

Rev. E | Page 2 of 32

Data Sheet

REVISION HISTORY

5/15—Rev. D to Rev. E

Changed ADA4841-x to ADA4841-1, ADR43x to ADR430/

ADR431/ADR433/ADR434/ADR435, and AD44x to ADR440/

ADR441/ADR443/ADR444/ADR445 ........................ Throughout

Updated Outline Dimensions ........................................................ 32

Changes to Ordering Guide ........................................................... 32

3/12—Rev. C to Rev. D

Changes to Figure 26 ...................................................................... 16

Changes to Internal Reference/Temperature Sensor Section .... 19

Changes to External Reference and Internal Buffer Section ..... 20

Changes to Bits[5:3] Function, Table 9 ......................................... 24

Updated Outline Dimensions ........................................................ 32

8/11—Rev. B to Rev. C

Changes to Internal Reference Section ........................................ 18

Changes to External Reference and Internal Buffer Section and

External Reference Section ............................................................ 19

Changes to Bits[5:3] Function, Table 9 ......................................... 22

5/09—Rev. A to Rev. B

Changes to Features Section, Applications Section, and

Figure 1 ............................................................................................... 1

Changes to Specifications Section ................................................... 3

Changes to Timing Specifications Section ..................................... 5

Changes to Table 5 ............................................................................ 7

Changes to Figure 4 and Table 6 ..................................................... 8

Changes to Figure 20 ...................................................................... 11

Changes to Converter Operation Section .................................... 13

Changes to Table 7 .......................................................................... 14

Changes to Figure 25 and Figure 26 ............................................. 15

Changes to Bipolar Single Supply Section, Input Structure

Section, and Selectable Low-Pass Filter Section ......................... 16

AD7949

Changes to Input Configurations Section, Sequencer Section, and Source Resistance Section ...................................................... 17

Changes to Internal Reference/Temperature Sensor Section .... 18

Added Figure 30; Renumbered Sequentially ............................... 18

Changes to External Reference and Internal Buffer Section,

External Reference Section, and Reference Decoupling

Section .............................................................................................. 19

Added Figure 31 and Figure 32 ..................................................... 19

Changes to Power Supply Section ................................................. 20

Changed Reading/Writing During Conversion, Fast Hosts

Section to Reading/Writing After Conversion,

Any Speed Hosts ............................................................................. 21

Changes to Configuration Register, CFG Section and

Table 9 ............................................................................................... 22

Added General Timing Without a Busy Indicator Section and

Figure 36 ........................................................................................... 23

Added General Timing with a Busy Indicator Section and

Figure 37 ........................................................................................... 24

Added Channel Sequencer Section, Examples Section, and

Figure 38 ........................................................................................... 25

Changes to Read/Write Spanning Conversion Without a Busy

Indicator Section and Figure 40 .................................................... 26

Changes to Read/Write Spanning Conversion with a Busy

Indicator Section and Figure 42 .................................................... 27

Changes to Evaluating AD7949 Performance Section ............... 28

Added Exposed Pad Notation to Outline Dimensions .............. 29

Changes to Ordering Guide ........................................................... 29

5/08—Rev. 0 to Rev. A

Changes to Ordering Guide ........................................................... 26

5/08—Revision 0: Initial Version

Rev. E | Page 3 of 32

AD7949

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V

REF

= VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 2.

Parameter

RESOLUTION

ANALOG INPUT

Voltage Range

Absolute Input Voltage

Analog Input CMRR

Leakage Current at 25°C

Input Impedance 1

THROUGHPUT

Conversion Rate

Full Bandwidth

2

¼ Bandwidth 2

Transient Response

Test Conditions/Comments

Unipolar mode

Bipolar mode

Positive input, unipolar and bipolar modes

Negative or COM input, unipolar mode

Negative or COM input, bipolar mode f

IN

= 250 kHz

Acquisition phase

VDD = 4.5 V to 5.5 V

VDD = 2.3 V to 4.5 V

VDD = 4.5 V to 5.5 V

VDD = 2.3 V to 4.5 V

Full-scale step, full bandwidth

Full-scale step, ¼ bandwidth

ACCURACY

No Missing Codes

Integral Linearity Error

Differential Linearity Error

Transition Noise

Gain Error 4

Gain Error Match

REF = VDD = 5 V

Gain Error Temperature Drift

Offset Error 4

Offset Error Match

Offset Error Temperature Drift

Power Supply Sensitivity

AC ACCURACY 5

Dynamic Range

Signal-to-Noise

SINAD f

VDD = 5 V ± 5%

IN f

IN

= 20 kHz, V

REF

= 5 V

= 20 kHz, V

REF

= 4.096 V internal REF f

IN

= 20 kHz, V

REF

= 2.5 V internal REF f

IN

= 20 kHz, V

REF

= 5 V f

IN

= 20 kHz, V

REF

= 5 V, −60 dB input f

IN

= 20 kHz, V

REF

= 4.096 V internal REF

Total Harmonic Distortion f

IN

= 20 kHz, V

REF

= 2.5 V internal REF f

IN

= 20 kHz

Spurious-Free Dynamic Range f

IN

= 20 kHz

Channel-to-Channel Crosstalk f

IN

= 100 kHz on adjacent channel(s)

SAMPLING DYNAMICS

−3 dB Input Bandwidth

Aperture Delay

Full bandwidth

¼ bandwidth

VDD = 5 V

84

84.5

−1

14

−1

−1

−5

−1

0

0

0

0

Min

14

Typ

0

−V

REF

/2

−0.1

−0.1

V

REF

/2 − 0.1 V

REF

/2

68

1

±0.5

±0.25

0.1

±0.5

±0.2

±1

±0.5

±0.2

±1

±0.2

85.6

85.5

85

84

85

33.5

85

84

−100

108

−125

1.7

0.425

2.5

Data Sheet

+1

+1

+1

+5

+1

200

62.5

50

1.8

14.5

250

Max

+V

REF

+V

REF

/2

V

REF

+ 0.1

+0.1

V

REF

/2 + 0.1

V

V

Unit

Bits dB nA kSPS kSPS kSPS kSPS

μs

μs

Bits

LSB 3

LSB

LSB

LSB

LSB ppm/°C

LSB

LSB ppm/°C

LSB dB dB dB dB dB dB dB dB

dB 6

dB dB

MHz

MHz ns

Rev. E | Page 4 of 32

Data Sheet AD7949

Parameter

INTERNAL REFERENCE

REF Output Voltage

REFIN Output Voltage 7

REF Output Current

Temperature Drift

Line Regulation

Long-Term Drift

Turn-On Settling Time

EXTERNAL REFERENCE

Voltage Range

Current Drain

TEMPERATURE SENSOR

Output Voltage

8

Temperature Sensitivity

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format 9

Pipeline Delay 10

V

OL

V

OH

POWER SUPPLIES

VDD

VIO

Standby Current 11, 12

Power Dissipation

Test Conditions/Comments

2.5 V, @ 25°C

4.096 V, @ 25°C

2.5 V, @ 25°C

4.096 V, @ 25°C

VDD = 5 V ± 5%

1000 hours

CREF = 10 µF

REF input

REFIN input (buffered)

250 kSPS, REF = 5 V

@ 25°C

I

SINK

= +500 µA

I

SOURCE

= −500 µA

Specified performance

Specified performance

Operating range

VDD and VIO = 5 V, @ 25°C

VDD = 2.5 V, 100 SPS throughput

VDD = 2.5 V, 100 kSPS throughput

VDD = 2.5 V, 200 kSPS throughput

VDD = 5 V, 250 kSPS throughput

VDD = 5 V, 250 kSPS throughput with internal reference

2.3

1.8

−1

−1

VIO − 0.3

2.3

Min

2.490

4.086

0.5

0.5

−0.3

0.7 × VIO

Energy per Conversion 50 nJ

TEMPERATURE RANGE 13

Specified Performance T

MIN

to T

MAX

−40 +85 °C

1

See the Analog Inputs section.

2 The bandwidth is set in the configuration register.

3 LSB means least significant bit. With the 5 V input range, one LSB = 305 µV.

4

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

5 With VDD = 5 V, unless otherwise noted.

6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

7 This is the output from the internal band gap.

8 The output voltage is internal and present on a dedicated multiplexer input.

9 Unipolar mode: serial 14-bit straight binary.

10

Bipolar mode: serial 14-bit twos complement.

11

12

Conversion results available immediately after completed conversion.

With all digital inputs forced to VIO or GND as required.

13

During acquisition phase.

Contact an Analog Devices, Inc., sales representative for the extended temperature range.

Rev. E | Page 5 of 32

50

1.5

1.45

2.9

10.8

13.5

Typ

2.500

4.096

1.2

2.3

±300

±10

±15

50

5

50

283

1

Max

2.510

4.106

VDD + 0.3 V

VDD − 0.5 V

µA mV mV/°C

+0.3 × VIO V

VIO + 0.3 V

Unit

V

V

V

V

µA ppm/°C ppm/V ppm ms

0.4

5.5

+1

+1

VDD + 0.3 V

VDD + 0.3 V nA

µW

2.0

4.0

12.5

15.5 mW mW mW mW

V

V

V

µA

µA

AD7949

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 3.

Parameter 1

Conversion Time: CNV Rising Edge to Data Available

Acquisition Time

Time Between Conversions

Data Write/Read During Conversion

CNV Pulse Width

SCK Period

SCK Low Time

SCK High Time

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV Low to SDO D15 MSB Valid

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV High or Last SCK Falling Edge to SDO High Impedance

CNV Low to SCK Rising Edge

DIN Valid Setup Time from SCK Rising Edge

DIN Valid Hold Time from SCK Rising Edge

1

See Figure 2 and Figure 3 for load conditions.

Symbol

t

CONV t

ACQ t

CYC t

DATA t

CNVH t

SCK t

SCKL t

SCKH t

HSDO t

EN t

DSDO t

DIS t

CLSCK t

SDIN t

HDIN

10

5

5

Min

1.8

4.0

10 t

DSDO

+ 2

11

11

4

Typ

32

18

22

25

18

23

28

Max

2.2

1.0

Data Sheet

ns ns ns ns ns ns ns ns ns ns

Unit

µs

µs

µs

µs ns ns ns ns ns

Rev. E | Page 6 of 32

Data Sheet

VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 4.

Parameter 1

Conversion Time: CNV Rising Edge to Data Available

Acquisition Time

Time Between Conversions

Data Write/Read During Conversion

CNV Pulse Width

SCK Period

SCK Low Time

SCK High Time

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV Low to SDO D15 MSB Valid

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV High or Last SCK Falling Edge to SDO High Impedance

CNV Low to SCK Rising Edge

DIN Valid Setup Time from SCK Rising Edge

DIN Valid Hold Time from SCK Rising Edge

1

See Figure 2 and Figure 3 for load conditions.

t

DIS t

CLSCK t

SDIN t

HDIN

Symbol

t

CONV t

ACQ t

CYC t

DATA t

CNVH t

SCK t

SCKL t

SCKH t

HSDO t

DSDO t

EN

10

5

5

Min

1.8

5

10 t

DSDO

+ 2

12

12

5

Typ

I

OL

500µA

27

35

45

50

24

30

38

48

21

Max

3.2

1.2

AD7949

ns ns ns ns ns ns ns ns ns ns ns ns

Unit

µs

µs

µs

µs ns ns ns ns ns

TO SDO

C

L

50pF

1.4V

500µA I

OH

Figure 2. Load Circuit for Digital Interface Timing

70% VIO

30% VIO t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2 t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2

1

2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2

0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

Rev. E | Page 7 of 32

AD7949

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Analog Inputs

INx, 1 COM 1

REF, REFIN

Supply Voltages

VDD, VIO to GND

VIO to VDD

DIN, CNV, SCK to GND

SDO to GND

Storage Temperature Range

Junction Temperature

θ

JA

Thermal Impedance (LFCSP)

θ

JC

Thermal Impedance (LFCSP)

1

See the Analog Inputs section.

Rating

GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA

GND − 0.3 V to VDD + 0.3 V

−0.3 V to +7 V

−0.3 V to VDD + 0.3 V

−0.3 V to VIO + 0.3 V

−0.3 V to VIO + 0.3 V

−65°C to +150°C

150°C

47.6°C/W

4.4°C/W

Data Sheet

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Rev. E | Page 8 of 32

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD 1

REF

REFIN

GND

GND

4

5

2

3

AD7949

TOP VIEW

(Not to Scale)

15 VIO

14

13

SDO

SCK

12

11

DIN

CNV

AD7949

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic

1, 20

2

3

4, 5

6 to 9

10

11

12

13

14

15

VDD

REF

REFIN

GND

IN4 to IN7

COM

CNV

DIN

SCK

SDO

VIO

Type 1

P

AI/O

AI/O

P

AI

AI

DI

DI

DI

DO

P

Description

Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with

10 μF and 100 nF capacitors.

When using the internal reference for 2.5 V output, the minimum should be 3.0 V.

When using the internal reference for 4.096 V output, the minimum should be 4.5 V.

Reference Input/Output. See the Voltage Reference Output/Input section.

When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or 4.096 V.

When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power references.

For improved drift performance, connect a precision reference to REF (0.5 V to VDD).

For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as

close to REF as possible. See the Reference Decoupling section.

Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section.

When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor.

When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as described above.

Power Supply Ground.

Channel 4 through Channel 7 Analog Inputs.

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of

0 V or V

REF

/2 V.

Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled.

Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion.

Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5

V, 3 V, or 5 V).

Channel 0 through Channel 3 Analog Inputs. 16 to 19 IN0 to IN3 AI

21

(EPAD)

Exposed Pad

(EPAD)

NC The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane.

1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.

Rev. E | Page 9 of 32

AD7949

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V to 5.5 V, V

REF

= 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted.

1.0

1.0

0.5

0.5

0

–0.5

–1.0

0 4,096 8,192

CODES

12,288 16,384

Figure 5. Integral Nonlinearity vs. Code, V

REF

= VDD = 5 V

300k

261,120

V

REF

= VDD = 5V

250k

200k

150k

100k

–100

–120

–140

–160

0

50k

0

0

0

1FFC

0 0 1 0 0

1FFD 1FFE 1FFF 2000 2001

CODE IN HEX

0 0

2002 2003

Figure 6. Histogram of a DC Input at Code Center

–20

–40

–60 f f

V

REF

= VDD = 5V

S

= 250kSPS

IN

= 19.9kHz

SNR = 85.3dB

SINAD = 85.2dB

THD = –100dB

SFDR = 103dB

SECOND HARMONIC = –110dB

THIRD HARMONIC = –103dB

–80

125 25 50 75

FREQUENCY (kHz)

100

Figure 7. 20 kHz FFT, V

REF

= VDD = 5 V

Data Sheet

0

–0.5

–1.0

0 4,096 8,192

CODES

12,288 16,384

Figure 8. Differential Nonlinearity vs. Code, V

REF

= VDD = 5 V

300k

259,473

V

REF

= VDD = 2.5V

250k

200k

150k

100k

50k

0 0 0

955 693

0 0 0

0

1FFC 1FFD 1FFE 1FFF 2000 2001 2002 2003 2004

CODE IN HEX

Figure 9. Histogram of a DC Input at Code Center

0

–20

–40

–60

–80 f f

V

REF

= VDD = 2.5V

s

= 200kSPS

IN

= 19.9kHz

SNR = 84.2dB

SINAD = 82.4dB

THD = –84dB

SFDR = 85dB

SECOND HARMONIC = –100dB

THIRD HARMONIC = –85dB

–100

–120

–140

–160

–180

0 25 50

FREQUENCY (kHz)

75

Figure 10. 20 kHz FFT, V

REF

= VDD = 2.5 V

100

Rev. E | Page 10 of 32

Data Sheet

90

85

80

75

70

65

60

0

88

86

SNR

SINAD

ENOB

VDD = V

REF

VDD = V

REF

VDD = V

REF

VDD = V

REF

= 5V, –0.5dB

= 5V, –10dB

= 2.5V, –0.5dB

= 2.5V, –10dB

50 100

FREQUENCY (kHz)

150

Figure 11. SNR vs. Frequency

84

200

15.5

82

80

15.0

14.5

14.0

13.5

78

1.0

1.5

2.0

2.5

3.0

3.5

4.0

REFERENCE VOLTAGE (V)

4.5

5.0

5.5

13.0

Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage

90 f

IN

= 20kHz

VDD = V

REF

= 5V

85

VDD = V

REF

= 2.5V

80

75

70

65

60

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

Figure 13. SNR vs. Temperature

85 105

125

AD7949

90

85

80

75

70

65

VDD = V

REF

VDD = V

REF

VDD = V

REF

VDD = V

REF

= 5V, –0.5dB

= 5V, –10dB

= 2.5V, –0.5dB

= 2.5V, –10dB

130

125

120

115

110

105

100

95

90

85

80

75

70

1.0

60

0 50 100

FREQUENCY (kHz)

150

Figure 14. SINAD vs. Frequency

200

SFDR

THD

1.5

2.0

2.5

3.0

3.5

4.0

REFERENCE VOLTAGE (V)

4.5

5.0

Figure 15. SFDR and THD vs. Reference Voltage

–85

–90

–95

–100

–105

–110

–115

5.5

–120

–60

–65

–70

–75

–80

–90 f

IN

= 20kHz

–95

VDD = V

REF

= 5V

VDD = V

REF

= 2.5V

–100

–105

–110

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

Figure 16. THD vs. Temperature

85 105

125

Rev. E | Page 11 of 32

AD7949

–60

–70

–80

–90

–100

–110

VDD = V

VDD = V

VDD = V

VDD = V

REF

= 5V, –0.5dB

REF

= 2.5V, –0.5dB

REF

= 2.5V, –10dB

REF

= 5V, –10dB

–120

0

2

50 100

FREQUENCY (kHz)

Figure 17. THD vs. Frequency

150

86

85

84

83

90

89

88

87

82

81

80

79

78

–10 f

IN

= 20kHz

VDD = V

REF

= 5V

VDD = V

REF

= 2.5V

–8 –6 –4

INPUT LEVEL (dB)

Figure 18. SNR vs. Input Level

–2

200

0

1

0

–1

UNIPOLAR ZERO

UNIPOLAR GAIN

BIPOLAR ZERO

BIPOLAR GAIN

–2

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

Figure 19. Offset and Gain Errors vs. Temperature

125

Data Sheet

2750

2500

2250

2000

1750

1500

1250

1000

2.5V INTERNAL REF

4.096V INTERNAL REF

INTERNAL BUFFER, TEMP ON

INTERNAL BUFFER, TEMP OFF

EXTERNAL REF, TEMP ON

EXTERNAL REF, TEMP OFF

VIO f

S

= 200kSPS

30

5.5

20

60

50

40

80

70

100

90

750

2.5

3.0

3.5

4.0

VDD SUPPLY (V)

4.5

5.0

Figure 20. Operating Currents vs. Supply

3000

2750 f

S

= 200kSPS

2500

2250

VDD = 5V, INTERNAL 4.096V REF

2000

VDD = 5V, EXTERNAL REF

1750

1500

VDD = 2.5, EXTERNAL REF

1250

VIO 60

40

100

80

180

160

140

120

1000

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

Figure 21. Operating Currents vs. Temperature

125

20

25

VDD = 2.5V, 85°C

20

15

VDD = 2.5V, 25°C

10

VDD = 5V, 85°C

5

VDD = 5V, 25°C

VDD = 3.3V, 85°C

VDD = 3.3V, 25°C

0

0 20 40 60 80

SDO CAPACITIVE LOAD (pF)

100 120

Figure 22. t

DSDO

Delay vs. SDO Capacitance Load and Supply

Rev. E | Page 12 of 32

Data Sheet

TERMINOLOGY

Least Significant Bit (LSB)

The LSB is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is

LSB

(V) =

V

2

REF

N

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line (see Figure 24).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 … 10 to 111 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together.

The value for dynamic range is expressed in decibels.

AD7949

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the formula

ENOB = (SINAD dB

− 1.76)/6.02 and is expressed in bits.

Channel-to-Channel Crosstalk

Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a dc to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel and is expressed in decibels.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V

REF

) measured at T

MIN

, T (25°C), and T

MAX

. It is expressed in ppm/°C as

TCV

REF

( ppm/

°

C )

=

V

V

REF

REF

(

Max

(

25

°

C

)

×

) –

V

REF

(

T

MAX

(

Min

)

T

MIN

)

×

10

6 where:

V

REF

(Max) = maximum V

REF

at T

MIN

, T (25°C), or T

MAX

.

V

REF

(Min) = minimum V

REF

at T

MIN

, T (25°C), or T

MAX

.

V

REF

(25°C) = V

REF

at 25°C.

T

MAX

= +85°C.

T

MIN

= –40°C.

Rev. E | Page 13 of 32

AD7949

THEORY OF OPERATION

INx+

Data Sheet

REF

GND

8,192C

MSB

4,096C

8,192C 4,096C

MSB

4C 2C

4C 2C

C

C

C

C

LSB SW+

SWITCHES CONTROL

COMP

CONTROL

LOGIC

BUSY

OUTPUT CODE

LSB SW–

CNV

INx– OR

COM

These components are configured through an SPI-compatible,

14-bit register. Conversion results, also SPI compatible, can be read after or during conversions with the option for reading back the configuration associated with the conversion.

The AD7949 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency.

The AD7949 is specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. The part is housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space savings and allows flexible configurations. It is pin-for-pin compatible with the 16-bit AD7682 , AD7689 , and AD7699 .

Figure 23. ADC Simplified Schematic

OVERVIEW

The AD7949 is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). The AD7949 is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. For example, when operating with an external reference at 1 kSPS, it consumes 15 µW typically, ideal for battery-powered applications.

The AD7949 contains all of the components for use in a multichannel, low power data acquisition system, including

• 14-bit SAR ADC with no missing codes

• 8-channel, low crosstalk multiplexer

• Internal low drift reference and buffer

• Temperature sensor

• Selectable one-pole filter

• Channel sequencer

CONVERTER OPERATION

The AD7949 is a successive approximation ADC based on a

charge redistribution DAC. Figure 23 shows the simplified

schematic of the ADC. The capacitive DAC consists of two identical arrays of 14 binary-weighted capacitors, which are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the comparator input are connected to GND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− (or COM) inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps

(V

REF

/2, V

REF

/4, ... V

REF

/8,192). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator.

Because the AD7949 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.

Rev. E | Page 14 of 32

Data Sheet

TRANSFER FUNCTIONS

With the inputs configured for unipolar range (single-ended,

COM with ground sense, or paired differentially with INx− as ground sense), the data output is straight binary.

With the inputs configured for bipolar range (COM = V

REF

/2 or paired differentially with INx− = V

REF

/2), the data outputs are twos complement.

The ideal transfer characteristic for the AD7949 is shown in

Figure 24 and for both unipolar and bipolar ranges with the

internal 4.096 V reference.

TWOS

COMPLEMENT

STRAIGHT

BINARY

011...111

011...110

011...101

111...111

111...110

111...101

AD7949

100...010

100...001

100...000

000...010

000...001

000...000

–FSR

–FSR + 1LSB

–FSR + 0.5LSB

+FSR – 1LSB

+FSR – 1.5LSB

ANALOG INPUT

Figure 24. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Description

Unipolar Analog Input

1

V

REF

= 4.096 V

FSR − 1 LSB 4.095750 V

Digital Output Code

(Straight Binary Hex)

0x3FFF

3

Midscale + 1 LSB 2.048250 V 0x2001

Midscale 2.048000 V

Midscale − 1 LSB 2.047750 V

−FSR + 1 LSB 250 μV

0x2000

0x1FFF

0x0001

0x0000 4

1 With COM or INx− = 0 V or all INx referenced to GND.

2 With COM or INx− = V

REF

/2.

3

This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above V

REF

− GND).

4

This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND).

Bipolar Analog Input

2

V

REF

= 4.096 V

250 μV

0 V

−250 μV

−2.047750 V

−2.048 V

Digital Output Code

(Twos Complement Hex)

0x1FFF

3

0x0001

0x0000

0x3FFF

0x2001

0x2000 4

Rev. E | Page 15 of 32

AD7949

TYPICAL CONNECTION DIAGRAMS

5V 1.8V TO VDD

100nF

100nF

10µF

2

100nF

V+

0V TO V

REF

ADA4841-x

3

V–

V+

IN0

REF REFIN VDD VIO

IN[7:1]

AD7949

DIN

SCK

SDO

CNV

MOSI

SCK

MISO

SS

0V TO V

REF

ADA4841-x

3

V–

0V OR

V

REF

/2

COM

GND

NOTES

1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR

REFERENCE SELECTION.

2. C

REF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.

Figure 25. Typical Application Diagram with Multiple Supplies

+5V

1.8V TO VDD

10µF

2

V+

ADA4841-x

3

V–

100nF

REF

IN0

100nF

REFIN VDD

100nF

VIO

V+

ADA4841-x

3

V–

IN[7:1]

AD7949

DIN

SCK

SDO

CNV

V

REF

p-p

V

REF

/2

COM

GND

NOTES

1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR

REFERENCE SELECTION.

2. C

REF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.

Figure 26. Typical Application Diagram Using Bipolar Input

MOSI

SCK

MISO

SS

Data Sheet

Rev. E | Page 16 of 32

Data Sheet

Unipolar or Bipolar

Figure 25 shows an example of the recommended connection

diagram for the AD7949 when multiple supplies are available.

Bipolar Single Supply

Figure 26 shows an example of a system with a bipolar input

using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input configuration, the INx inputs are unipolar and are always referenced to GND (no negative voltages even in bipolar range).

For this circuit, a rail-to-rail input/output amplifier can be used; however, the offset voltage vs. input common-mode range should be noted and taken into consideration (1 LSB = 250 μV with

V

REF

= 4.096 V). Note that the conversion results are in twos complement format when using the bipolar input configuration.

Refer to the AN-581 Application Note, Biasing and Decoupling

Op Amps in Single Supply Applications, at www.analog.com

for additional details about using single-supply amplifiers.

ANALOG INPUTS

Input Structure

Figure 27 shows an equivalent circuit of the input structure of

the AD7949 . The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current.

These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions may eventually occur when the input buffer supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part.

VDD

INx+

OR INx–

OR COM

D1

R

IN

C

IN

C

PIN

D2

GND

Figure 27. Equivalent Analog Input Circuit

This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−.

(COM or INx− = GND ± 0.1 V or V

REF

± 0.1 V). By using these differential inputs, signals common to both inputs are rejected,

as shown in Figure 28.

AD7949

60

55

50

70

65

45

40

35

30

1

10

100

FREQUENCY (kHz)

1k

Figure 28. Analog Input CMRR vs. Frequency

10k

During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, C

PIN

, and the network formed by the series connection of R

IN

and C

IN

.

C

PIN

is primarily the pin capacitance. R

IN

is typically 2.4 kΩ and is a lumped component composed of serial resistors and the on resistance of the switches. C

IN

is typically 27 pF and is mainly the ADC sampling capacitor.

Selectable Low-Pass Filter

During the conversion phase, where the switches are opened, the input impedance is limited to C

PIN

. While the AD7949 is acquiring, R

IN

and C

IN

make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low-pass filter can be programmed for the full bandwidth or ¼ of the bandwidth with CFG[6], as

shown in Table 9. This setting changes R

IN

to 19 kΩ. Note that the converter throughput must also be reduced by ¼ when using the filter. If the maximum throughput is used with the bandwidth

(BW) set to ¼, the converter acquisition time, t

ACQ

, is violated, resulting in increased THD.

Rev. E | Page 17 of 32

AD7949

Input Configurations

Figure 29 shows the different methods for configuring the analog

inputs with the configuration register, CFG[12:10]. Refer to the

Configuration Register, CFG, section for more details.

The analog inputs can be configured as

• Figure 29A, single-ended referenced to system ground;

CFG[12:10] = 111

2

.

In this configuration, all inputs (IN[7:0]) have a range of

GND to V

REF

.

• Figure 29B, bipolar differential with a common reference

point; COM = V

REF

/2; CFG[12:10] = 010

2

.

Unipolar differential with COM connected to a ground sense; CFG[12:10] = 110

2

.

In these configurations, all inputs IN[7:0] have a range of

GND to V

REF

.

• Figure 29C, bipolar differential pairs with the negative

input channel referenced to V

REF

/2; CFG[12:10] = 00X

2

.

Unipolar differential pairs with the negative input channel referenced to a ground sense; CFG[12:10] = 10X

2

.

In these configurations, the positive input channels have the range of GND to V

REF

. The negative input channels are senses referred to V

REF

/2 for bipolar pairs, or GND for unipolar pairs. The positive channel is configured with

CFG[9:7]. If CFG[9:7] is even, then IN0, IN2, IN4, and IN6 are used. If CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 are used (channels with parentheses). For example, for

IN0/IN1 pairs with the positive channel on IN0, CFG[9:7]

= 000

2

. For IN4/IN5 pairs with the positive channel on

IN5, CFG[9:7] = 101

2

.

Note that for the sequencer, detailed in the Channel

Sequencer section, the positive channels are always IN0,

IN2, IN4, and IN6.

• Figure 29D, inputs configured in any of the preceding

combinations (showing that the AD7949 can be configured dynamically).

Data Sheet

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

A—8 CHANNELS,

SINGLE ENDED

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

COM–

IN4

IN5

IN6

IN7

COM

GND

IN0

IN1

IN2

IN3

B—8 CHANNELS,

COMMON REFERNCE

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+ (–)

CH2– (+)

CH3+ (–)

CH3– (+)

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+

CH3+

CH4+

CH5+

COM–

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

C—4 CHANNELS,

DIFFERENTIAL

D—COMBINATION

Figure 29. Multiplexed Analog Input Configurations

Sequencer

The AD7949 includes a channel sequencer useful for scanning

channels in a repeated fashion. Refer to the Channel Sequencer

section for further details of the sequencer operation.

Source Resistance

When the source impedance of the driving circuit is low, the

AD7949 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.

Rev. E | Page 18 of 32

Data Sheet

DRIVER AMPLIFIER CHOICE

Although the AD7949 is easy to drive, the driver amplifier must meet the following requirements:

 The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7949 . Note that the AD7949 has a noise much lower than most of the other 14-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise from the amplifier is filtered by the AD7949 analog input circuit low-pass filter made by R

IN

and C

IN

or by an external filter, if one is used.

 For ac applications, the driver should have a THD performance commensurate with the AD7949

. Figure 17 shows

THD vs. frequency for the AD7949 .

 For multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7949 analog input circuit must settle a full-scale step onto the capacitor array at a 14-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 14-bit level and should be verified prior to driver selection.

Table 8. Recommended Driver Amplifiers

ADA4841-1

AD8655

Very low noise, small, and low power

5 V single supply, low noise

AD8021

AD8022

Very low noise and high frequency

Low noise and high frequency

OP184 Low power, low noise, and low frequency

AD8605 , AD8615 5 V single supply, low power

AD7949

VOLTAGE REFERENCE OUTPUT/INPUT

The AD7949 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.

The internal reference of the AD7949 provides excellent performance and can be used in almost all applications. There are six possible choices of voltage reference schemes briefly

described in Table 9, with more details in each of the following

sections.

Internal Reference/Temperature Sensor

The precision internal reference, suitable for most applications, can be set for either a 2.5 V or a 4.096 V output, as detailed in

Table 9. With the internal reference enabled, the band gap

voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8605. Note that the voltage of REFIN changes depending on the 2.5 V or 4.096 V internal reference.

Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7949 and is thus useful for performing a system calibration. For applications requiring the use of the temperature sensor, the internal reference must be active (internal buffer can be disabled in this case). Note that, when using the temperature sensor, the output is straight binary referenced from the

AD7949 GND pin.

The internal reference is temperature-compensated to within

10 mV. The reference is trimmed to provide a typical drift of

±10 ppm/°C.

Connect the AD7949

as shown in Figure 30 for either a 2.5 V or

4.096 V internal reference.

10µF

REF

100nF

REFIN

AD7949

TEMP

GND

Figure 30. 2.5 V or 4.096 V Internal Reference Connection

Rev. E | Page 19 of 32

AD7949

External Reference and Internal Buffer

For improved drift performance, an external reference can be

used with the internal buffer, as shown in Figure 31. The

external source is connected to REFIN, the input to the on-chip unity gain buffer, and the output is produced on the REF pin.

An external reference can be used with the internal buffer with

or without the temperature sensor enabled. Refer to Table 9 for

register details. With the buffer enabled, the gain is unity and is limited to an input/output of VDD = −0.2 V; however, the maximum voltage allowable must be ≤(VDD − 0.5 V).

The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications.

In addition, a low power reference can be used because the internal buffer provides the necessary performance to drive the

SAR architecture of the AD7949 .

REF SOURCE

≤ (VDD – 0.5V)

10µF 100nF

REF REFIN

AD7949

TEMP

GND

Figure 31. External Reference Using Internal Buffer

External Reference

In any of the six voltage reference schemes, an external reference

can be connected directly on the REF pin as shown in Figure 32

because the output impedance of REF is >5 kΩ. To reduce power consumption, the reference and buffer should be powered down.

When using only the external reference (and optional reference

buffer as shown in Figure 35), the internal buffer is disabled.

Refer to Table 9 for register details. For improved drift perfor-

mance, an external reference such as the ADR430 / ADR431 /

ADR433 / ADR434 / ADR435 or ADR440 / ADR441 / ADR443 /

ADR444 / ADR445 is recommended.

10µF

REF

REF SOURCE

0.5V < REF < (VDD + 0.3V)

NO CONNECTION

REQUIRED

REFIN

AD7949

TEMP

GND

Figure 32. External Reference

Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows:

SNR

LOSS

20 log

4 .

096

5

Rev. E | Page 20 of 32

Data Sheet

Reference Decoupling

Whether using an internal or external reference, the AD7949 voltage reference output/input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance. A 10 μF

(X5R, 1206 size) ceramic chip capacitor is appropriate when using the internal reference, the ADR430 / ADR431 / ADR433 /

ADR434 / ADR435 or ADR440 / ADR441 / ADR443 / ADR444 /

ADR445 external reference, or a low impedance buffer such as the AD8031 or the AD8605 .

The placement of the reference decoupling capacitor is also important to the performance of the AD7949 , as explained in the

Layout section. Mount the decoupling capacitor on the same side

as the ADC at the REF pin with a thick PCB trace. The GND should also be connected to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias.

If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with minimal impact on performance, especially on DNL.

Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.

For applications that use multiple AD7949 devices or other

PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing

SAR conversion crosstalk.

The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±10 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.

Data Sheet

POWER SUPPLY

The AD7949 uses two power supply pins: an analog and digital core supply (VDD) and a digital input/output interface supply

(VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7949 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide

frequency range, as shown in Figure 33.

75

40

35

50

45

60

55

70

65

30

1 10 100

FREQUENCY (kHz)

1k

Figure 33. PSRR vs. Frequency

10k

The AD7949 powers down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low batterypowered applications.

10,000

1000 VDD = 5V, INTERNAL REF

100

VDD = 5V, EXTERNAL REF

VDD = 2.5V, EXTERNAL REF 10

1

VIO

0.1

0.010

0.001

10 100 1k 10k

SAMPLING RATE (SPS)

100k

Figure 34. Operating Currents vs. Sampling Rate

1M

AD7949

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7949 , with its low operating current, can be supplied directly using an external reference

circuit like the one shown in Figure 35. The reference line can

be driven by:

 The system power supply directly

 A reference voltage with enough current output capability, such as the ADR430 / ADR431 / ADR433 / ADR434 / ADR435 or ADR440 / ADR441 / ADR443 / ADR444 / ADR445

 A reference buffer, such as the

AD8605 , which can also

filter the system power supply, as shown in Figure 35

5V

5V

5V 10kΩ

1µF

AD8605

10µF

1

10Ω

1µF

0.1µF 0.1µF

REF VDD

AD7949

VIO

1

OPTIONAL REFERENCE BUFFER AND FILTER.

Figure 35. Example of an Application Circuit

Rev. E | Page 21 of 32

AD7949

DIGITAL INTERFACE

The AD7949 uses a simple 4-wire interface and is compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x , SHARC®, ADSP-219x , and

ADSP-218x .

The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications.

A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other

components, which are detailed in the Configuration Register,

CFG, section.

When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion), as detailed in the following sections. The CFG word is updated on the first 14 SCK rising edges, and conversion results are output on the first 13 (or 14 if busy mode is selected) SCK falling edges. If the CFG readback is enabled, an additional

14 SCK falling edges are required to output the CFG word associated with the conversion results with the CFG MSB following the LSB of the conversion result.

A discontinuous SCK is recommended because the part is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data.

Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, DIN, SDO) during the conversion.

However, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading/ writing time, t

DATA

, because the AD7949 provides error correction circuitry that can correct for an incorrect bit during this time. From t

DATA

to t

CONV

, there is no error correction and conversion results may be corrupted. The user should configure the

AD7949 and initiate the busy indicator (if desired) prior to t

DATA

. It is also possible to corrupt the sample by having SCK or

DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately

20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation.

Data Sheet

READING/WRITING DURING CONVERSION, FAST

HOSTS

When reading/writing during conversion (n), conversion results are for the previous (n − 1) conversion, and writing the

CFG register is for the next (n + 1) acquisition and conversion.

After the CNV is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion.

Reading/writing should only occur up to t

DATA

and, because this time is limited, the host must use a fast SCK.

The SCK frequency required is calculated by

f

SCK

Number

_

SCK t

DATA

_

Edges

The time between t

DATA

and t

CONV

is a safe time when digital activity should not occur, or sensitive bit decisions may be corrupted.

READING/WRITING AFTER CONVERSION, ANY

SPEED HOSTS

When reading/writing after conversion, or during acquisition

(n), conversion results are for the previous (n − 1) conversion, and writing is for the (n + 1) acquisition.

For the maximum throughput, the only time restriction is that the reading/writing take place during the t

ACQ

(minimum) time.

For slow throughputs, the time restriction is dictated by the throughput required by the user, and the host is free to run at any speed. Thus for slow hosts, data access must take place during the acquisition phase.

Rev. E | Page 22 of 32

Data Sheet

READING/WRITING SPANNING CONVERSION, ANY

SPEED HOST

When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n).

Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion.

Similar to reading/writing during conversion, reading/writing should only occur up to t

DATA

. For the maximum throughput, the only time restriction is that reading/writing take place during the t

ACQ

+ t

DATA

time.

For slow throughputs, the time restriction is dictated by the user’s required throughput, and the host is free to run at any speed. Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion.

AD7949

Note that data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method.

CONFIGURATION REGISTER, CFG

The AD7949 uses a 14-bit configuration register (CFG[13:0]),

as detailed in Table 9, to configure the inputs, the channel to be

converted, the one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on

DIN with 14 SCK rising edges. The CFG update is edge dependent, allowing for asynchronous or synchronous hosts.

Rev. E | Page 23 of 32

AD7949

The register can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion, t

CONV

(maximum). There is always a one deep delay when writing the CFG register. Note that, at power-up, the

CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions. Thus

CFG[13:0] = 0x3FFF. This sets the AD7949 for the following:

13

CFG

12

INCC

11

INCC

10

INCC

9

INx

8

INx

7

INx

Data Sheet

• IN[7:0] unipolar referenced to GND, sequenced in order

• Full bandwidth for a one-pole filter

• Internal reference/temperature sensor disabled, buffer enabled

• Enables the internal sequencer

• No readback of the CFG register

Table 9 summarizes the configuration register bit details. See

the Theory of Operation section for more details.

6

BW

5

REF

4

REF

3

REF

2

SEQ

1

SEQ

0

RB

Table 9. Configuration Register Description

Bit(s) Name Description

[13] CFG Configuration update.

0 = keep current configuration settings.

1 = overwrite contents of register.

[0]

[5:3]

[2:1]

[9:7]

[6]

[12:10] INCC Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer

to the

Input Configurations

section.

0

0

1

1

Bit 12

0

1

1

1

0

1

Bit 11

0

1

Bit 10

X 1

0

1

X 1

0

1

Function

Bipolar differential pairs; INx− referenced to V

REF

/2 ± 0.1 V.

Bipolar; INx referenced to COM = V

REF

/2 ± 0.1 V.

Temperature sensor.

Unipolar differential pairs; INx− referenced to GND ± 0.1 V.

Unipolar, INx referenced to COM = GND ± 0.1 V.

Unipolar, INx referenced to GND.

INx

BW

0

0

Input channel selection in binary fashion.

Bit 9 Bit 8 Bit 7

0

0

0

1

1

1

1

Channel

IN0

IN1

IN7

REF

SEQ

Select bandwidth for low-pass filter. Refer to the

Selectable Low-Pass Filter

section.

0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼.

1 = full BW.

Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.

Refer to the Voltage Reference Output/Input section.

0

0

0

1

1

Bit 5

0

0

1

1

1

1

Bit 4

0

1

0

1

0

1

Bit 3

0

Function

Internal reference, REF = 2.5 V output, temperature enabled.

Internal reference, REF = 4.096 V output, temperature enabled.

External reference, temperature enabled.

External reference, internal buffer, temperature enabled.

External reference, temperature disabled.

External reference, internal buffer, temperature disabled.

Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the

Channel Sequencer

section.

RB

0

1

Bit 2

0

1

1

0

Bit 1

0

1

Function

Disable sequencer.

Update configuration during sequence.

Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.

Scan IN0 to IN[7:0] (set in CFG[9:7]).

Read back the CFG register.

0 = read back current configuration at end of data.

1 = do not read back contents of configuration.

1 X = don’t care.

Rev. E | Page 24 of 32

Data Sheet AD7949

GENERAL TIMING WITHOUT A BUSY INDICATOR

Figure 36 details the timing for all three modes: read/write

during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion

(EOC). At EOC, if CNV is high, the busy indicator is disabled.

When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1.

The SCK can idle high or low depending on the clock polarity

(CPOL) and clock phase (CPHA) settings if SPI is used. A simple

solution is to use CPOL = CPHA = 0 as shown in Figure 36 with

SCK idling low.

As detailed previously in the Digital Interface section, the data

access should occur up to safe data reading/writing time, t

DATA

.

If the full CFG word was not written to prior to EOC, it is discarded and the current configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For

detailed timing, refer to Figure 39 and Figure 40, which depict

reading/writing spanning conversion with all timing details, including setup, hold, and SCK.

PHASE

POWER

UP

SOC t

CYC

EOC t

CONV

CONVERSION

(n – 2) UNDEFINED

ACQUISITION

(n – 1) UNDEFINED t

DATA

CONVERSION

(n – 1) UNDEFINED

EOC

ACQUISITION

(n)

From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the 2 nd

EOC; thus two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. Note that the first valid data occurs in Phase (n + 1) when the CFG register is written during

Phase (n − 1).

CONVERSION

(n)

EOC

ACQUISITION

(n + 1)

CONVERSION

(n + 1)

EOC

ACQUISITION

(n + 2)

NOTE 1

CNV

DIN

RDC

SDO

SCK

MSB

XXX

1

XXX

DATA (n – 3)

XXX

14

CFG (n)

DATA (n – 2)

XXX

1

14

NOTE 2

MSB

XXX

CFG (n + 1)

1

DATA (n – 1)

XXX

14

MSB

(n)

CFG (n + 2)

1

DATA (n)

14

NOTE 1

CNV

DIN

RAC

SDO

SCK

CFG (n)

DATA (n – 2)

XXX

1

14

NOTE 1

NOTE 2

CFG (n + 1)

1

DATA (n – 1)

XXX

14 1

CFG (n + 2)

DATA (n)

14 1

CFG (n + 3)

DATA (n + 1)

CNV

DIN

RSC

SDO

SCK

CFG (n) CFG (n)

1

DATA (n – 2)

XXX n n + 1

DATA (n – 2)

XXX

14

NOTE 2

CFG (n + 1) CFG (n + 1)

1

DATA (n – 1)

XXX n n + 1

DATA (n – 1)

XXX

14

1

CFG (n + 2)

DATA (n) n n + 1

CFG (n + 2)

DATA (n)

14

1

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 28 SCK FALLING EDGES IS

REQUIRED TO RETURN SDO TO HIGH-Z.

3. WITH THE SEQUENCER ENABLED, THE NEXT ACQUISITION PHASE WILL BE FOR IN0 AFTER THE LAST CHANNEL SET IN CFG[9:7] IS CONVERTED.

Figure 36. General Interface Timing for the AD7949 Without a Busy Indicator

CFG (n + 3)

DATA (n + 1) n

Rev. E | Page 25 of 32

AD7949

GENERAL TIMING WITH A BUSY INDICATOR

Figure 37 details the timing for all three modes: read/write

during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion

(EOC). As detailed previously, the data access should occur up to safe data reading/writing time, t

DATA

. If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains.

At the EOC, if CNV is low, the busy indicator is enabled. In addition, to generate the busy indicator properly, the host must assert a minimum of 15 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active.

Unlike the case detailed in the General Timing Without a Busy

Indicator section, if the conversion result is not read out fully

prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the busy

PHASE

POWER

UP t

CONV

CONVERSION

(n – 2) UNDEFINED t

CYC

EOC

START OF CONVERSION

(SOC) t

DATA

ACQUISITION

(n – 1) UNDEFINED

CONVERSION

(n – 1) UNDEFINED

EOC

ACQUISITION

(n)

CONVERSION

(n)

CONVERSION

(n + 1)

Data Sheet

generation requires either a high impedance or a remaining bit high-to-low transition. Because most SPI hosts are usually limited to 8-bit or 16-bit bursts, this should not be an issue.

Additional clocks are not a concern because SDO remains high impedance after the 15 th

falling edge.

The SCK can idle high or low depending on the CPOL and

CPHA settings if SPI is used. A simple solution is to use CPOL

= CPHA = 1 (not shown) with SCK idling high.

From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the 2 nd

EOC; thus, two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. Note that the first valid data occurs in Phase (n + 1) when the CFG register is written during

Phase (n − 1).

EOC

ACQUISITION

(n + 1)

EOC

ACQUISITION

(n + 2)

CNV

DIN

RDC

SDO

SCK

XXX

1

DATA (n – 3)

XXX

15

NOTE 1

CFG (n)

1

DATA (n – 2)

XXX

15

NOTE 2

CFG (n + 1)

1

DATA (n – 1)

XXX

15

CFG (n + 2)

1

DATA (n)

15

CNV

RAC

DIN

SDO

SCK

NOTE 1

CFG (n)

DATA (n – 2)

XXX

1 15

NOTE 2

CFG (n + 1)

1

DATA (n – 1)

XXX

15

CFG (n + 2)

DATA (n)

1

15

CNV

NOTE 1

RSC

DIN

SDO

CFG (n)

DATA (n – 2)

XXX

DATA (n – 2)

XXX

CFG (n + 1)

DATA (n – 1)

XXX

DATA (n – 1)

XXX

CFG (n + 2)

DATA (n)

SCK

1 n n + 1 15 1 n n + 1 15 1

NOTE 2

NOTES

1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.

2. A TOTAL OF 15 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,

A TOTAL OF 29 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

Figure 37. General Interface Timing for the AD7949 With a Busy Indicator

n n + 1

DATA (n)

15

1

CFG (n + 3)

DATA (n + 1)

1

CFG (n + 3)

DATA (n + 1)

Rev. E | Page 26 of 32

Data Sheet AD7949

CHANNEL SEQUENCER

The AD7949 includes a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced.

Busy Indicator section for more details. The sequencer can also

be used with the busy indicator and details for these timings can

be found in the General Timing with a Busy Indicator section

and the Read/Write Spanning Conversion with a Busy Indicator

section.

The sequencer starts with IN0 and finishes with IN[7:0] set in

CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that in sequencer mode, the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, IN6), and with the negative input on the odd channels (IN1, IN3, IN5, IN7). For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6.

For sequencer operation, the CFG register should be set during the (n − 1) phase after power-up. On phase (n), the sequencer setting takes place and acquires IN0. The first valid conversion result is available at phase (n + 1). After the last channel set in

CFG[9:7] is converted, the internal temperature sensor data is output (if enabled), followed by acquisition of IN0.

Examples

CFG[2:1] are used to enable the sequencer. After the CFG register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again.

With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in the following order:

IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2, …

Note that while operating in a sequence, some bits of the CFG register can be changed. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after the CFG register is updated.

For paired channels with the internal temperature sensor enabled, the sequencer scans in the following order:

IN0, IN2, IN4, IN6, TEMP, IN0, …

Figure 38 details the timing for all three modes without a busy

indicator. Refer to the General Timing Without a Busy Indicator

section and the Read/Write Spanning Conversion Without a

PHASE

POWER

UP

SOC t

CYC

EOC t

CONV

CONVERSION

(n – 2) UNDEFINED

ACQUISITION

(n – 1) UNDEFINED t

DATA

CONVERSION

(n – 1) UNDEFINED

EOC

ACQUISITION

(n), IN0

Note that IN1, IN3, IN5, and IN7 are referenced to a GND sense or V

REF

/2, as detailed in the Input Configurations section.

CONVERSION

(n), IN0

EOC

ACQUISITION

(n + 1), IN1

CONVERSION

(n + 1), IN1

EOC

ACQUISITION

(n + 2), IN2

NOTE 1

CNV

DIN

RDC

SDO

SCK

MSB

XXX

XXX

1

DATA (n – 3)

XXX

14

CFG (n)

1

DATA (n – 2)

XXX

14

NOTE 2

MSB

XXX

1

DATA (n – 1)

XXX

14

MSB

IN0

1

DATA IN0

NOTE 1

CNV

DIN

RAC

SDO

SCK

CFG (n)

DATA (n – 2)

XXX

1 14

NOTE 1

NOTE 2

1

DATA (n – 1)

XXX

14 1

DATA IN0

14

CNV

DIN

RSC

SDO

CFG (n)

DATA (n – 2)

XXX

CFG (n)

DATA (n – 2)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA IN0

SCK

1 n n + 1 14

1 n n + 1 14

NOTE 2

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

2. A TOTAL OF 14 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,

A TOTAL OF 28 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

1

Figure 38. General Channel Sequencer Timing Without a Busy Indicator

n n + 1

DATA IN0

14

14

1

DATA IN1

1

DATA IN1 n

Rev. E | Page 27 of 32

AD7949

READ/WRITE SPANNING CONVERSION WITHOUT

A BUSY INDICATOR

This mode is used when the AD7949 is connected to any host using an SPI, serial port, or FPGA. The connection diagram is

shown in Figure 39, and the corresponding timing is given in

Figure 40. For the SPI, the host should use CPHA = CPOL = 0.

Reading/writing spanning conversion is shown, which covers

all three modes detailed in the Digital Interface section. For this

mode, the host must generate the data transfer based on the conversion time. For an interrupt driven transfer that uses a

busy indicator, refer to the Read/Write Spanning Conversion with a Busy Indicator section.

A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned high before the safe data transfer time, t

DATA

, and then held high beyond the conversion time, t

CONV

, to avoid generation of the busy signal indicator.

AD7949

CNV

SDO

DIN

SCK

Data Sheet

After the conversion is complete, the AD7949 enters the acquisition phase and power-down. When the host brings CNV low after t

CONV

(maximum), the MSB is enabled on SDO. The host also must enable the MSB of the CFG register at this time

(if necessary) to begin the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG, and the first 13 SCK falling edges clock out the conversion results starting with

MSB − 1. The restriction for both configuring and reading is that they both must occur before the t

DATA

time of the next conversion elapses. All 14 bits of CFG[13:0] must be written, or they are ignored. In addition, if the 14-bit conversion result is not read back before t

DATA

elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 14 th (or 28 th ) SCK falling edge, or when CNV goes high (whichever occurs first), SDO returns to high impedance.

If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 28 SCK falling edges is required to return SDO to high impedance if this is enabled.

DIGITAL HOST

SS

MISO

MOSI

SCK

FOR SPI USE CPHA = 0, CPOL = 0.

Figure 39. Connection Diagram for the AD7949 Without a Busy Indicator

Rev. E | Page 28 of 32

Data Sheet AD7949 t

CYC t

DATA

> t

CONV t

CONV t

CONV t

DATA

CNV

EOC

RETURN CNV HIGH

FOR NO BUSY t

CNVH

EOC

RETURN CNV HIGH

FOR NO BUSY t

ACQ

ACQUISITION

(n - 1)

SCK

DIN

SDO t

CONVERSION (n – 1) t

SCK

SCKH t

SCKL

12 13

14/

28 t

EN

CFG

LSB

X

END CFG (n)

X

LSB

(QUIET

TIME)

UPDATE (n)

CFG/SDO t

CLSCK t

EN

1

ACQUISITION (n)

2

CFG

MSB t

SDIN

CFG

MSB – 1 t

HDIN

BEGIN CFG (n + 1) t

HSDO t

DSDO

MSB t

EN

CONVERSION (n) t

DIS

END DATA (n – 2) t

DIS

BEGIN DATA (n – 1) t

DIS

NOTES

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF

13 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

27 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 14TH OR 28TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPEDANCE.

Figure 40. Serial Interface Timing for the AD7949 Without a Busy Indicator

12 13

SEE NOTE

14/

28

CFG

LSB

X

END CFG (n + 1)

X

LSB

SEE NOTE

END DATA (n – 1) t

DIS

(QUIET

TIME)

UPDATE (n + 1)

CFG/SDO

Rev. E | Page 29 of 32

AD7949

READ/WRITE SPANNING CONVERSION WITH A

BUSY INDICATOR

This mode is used when the AD7949 is connected to any host using an SPI, serial port, or FPGA with an interrupt input. The

connection diagram is shown in Figure 41, and the corresponding timing is given in Figure 42. For the SPI, the host should use

CPHA = CPOL = 1. Reading/writing spanning conversion is

shown, which covers all three modes detailed in the Digital

Interface section.

A rising edge on CNV initiates a conversion, ignores data present on DIN and forces SDO to high impedance. After the conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned low before the safe data transfer time, t

DATA

, and then held low beyond the conversion time, t

CONV

, to generate the busy signal indicator.

When the conversion is complete, SDO transitions from high impedance to low (data ready), and with a pull-up to VIO, SDO can be used to interrupt the host to begin data transfer.

After the conversion is complete, the AD7949 enters the acquisition phase and power-down. The host must enable the

MSB of the CFG register at this time (if necessary) to begin the

VIO

AD7949

SDO t

DATA

CNV

DIN

SCK

Data Sheet

CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 14 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the t

DATA

time elapses for the next conversion. All 14 bits of

CFG[13:0] must be written or they are ignored. Also, if the 14-bit conversion result is not read back before t

DATA

elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 15 th (or 29 st ) SCK falling edge, SDO returns to high impedance. Note that if the optional SCK falling edge is not used, the busy feature cannot

be detected, as described in the General Timing with a Busy

Indicator section.

If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 29 SCK falling edges is required to return SDO to high impedance if this is enabled.

DIGITAL HOST

MISO

IRQ

SS

MOSI

SCK

FOR SPI USE CPHA = 1, CPOL = 1.

Figure 41. Connection Diagram for the AD7949 with a Busy Indicator

t

CYC t

ACQ t

CNVH t

DATA t

CONV

CNV

CONVERSION

(n – 1) t

SCKH

CONVERSION (n – 1) t

SCK

(QUIET

TIME)

UPDATE (n)

CFG/SDO

ACQUISITION (n)

SCK

DIN

SDO t

SCKL

13

X

14

END CFG (n)

X

LSB

+ 1

END DATA (n – 2)

15/

29

X

LSB t

DIS

1 2

CFG

MSB t

HDIN t

SDIN

CFG

MSB –1

BEIGN CFG (n + 1) t

HSDO t

DSDO

MSB

MSB

– 1

BEGIN DATA (n – 1) t

EN

NOTES:

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF

14 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

28 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 15TH OR 29TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPEDANCE.

OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.

t

EN t

DIS

LSB

+ 1

END DATA (n – 1)

LSB

NOTE 1

Figure 42. Serial Interface Timing for the AD7949 with a Busy Indicator

CONVERSION (n)

13

X

NOTE 1

14

15/

29

X

END CFG (n + 1)

X t

DIS

(QUIET

TIME)

ACQUISITION

(n + 1)

UPDATE (n + 1)

CFG/SDO t

EN

Rev. E | Page 30 of 32

Data Sheet

APPLICATION HINTS

LAYOUT

The printed circuit board (PCB) that houses the AD7949 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the

AD7949 , with all its analog signals on the left side and all its digital signals on the right side, eases this task.

Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7949 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Avoid crossover of digital and analog signals.

At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7949 .

The AD7949 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic

AD7949

inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and

GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies VDD and VIO of the AD7949 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7949 , and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines.

EVALUATING

AD7949

PERFORMANCE

Other recommended layouts for the AD7949 are outlined in the documentation of the evaluation board for the AD7949 ( EVAL-

AD7949EDZ ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the converter and evaluation development data capture board, EVAL-CED1Z .

Rev. E | Page 31 of 32

AD7949

OUTLINE DIMENSIONS

Data Sheet

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

TOP VIEW

0.50

BSC

15

16

0.30

0.25

0.20

EXPOSED

PAD

20

1

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

11

10

BOTTOM VIEW

6

5

0.50

0.40

0.30

0.25 MIN

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 43. 20-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

1

Notes Temperature Range

AD7949BCPZ

AD7949BCPZRL7

–40°C to +85°C

–40°C to +85°C

EVAL-AD7949EDZ

Package Description

20-Lead LFCSP_WQ

20-Lead LFCSP_WQ

Package Option

CP-20-10

CP-20-10

Ordering Quantity

Tray, 490

Reel, 1,500

EVAL-CED1Z

2

1

Z = RoHS Compliant Part.

2 This controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED.

©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D07351-0-5/15(E)

Rev. E | Page 32 of 32

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