AD7949-EP Data Sheet

AD7949-EP Data Sheet

Enhanced Product

FEATURES

14-bit resolution with no missing codes

8-channel multiplexer with choice of inputs

Unipolar single-ended

Differential (GND sense)

Pseudobipolar

Throughput: 250 kSPS

INL/DNL: ±0.5/±0.25 LSB typical

SINAD: 85 dB @ 20 kHz

THD: −100 dB @ 20 kHz

Analog input range: 0 V to V

REF

with V

REF

up to VDD

Multiple reference types

Internal selectable 2.5 V or 4.096 V

External buffered (up to 4.096 V)

External (up to VDD)

Internal temperature sensor (TEMP)

Channel sequencer, selectable 1-pole filter, busy indicator

No pipeline delay, SAR architecture

Single-supply 2.3 V to 5.5 V operation with

1.8 V to 5.5 V logic interface

Serial interface compatible with SPI, MICROWIRE,

QSPI, and DSP

Power dissipation

2.9 mW @ 2.5 V/200 kSPS

10.8 mW @ 5 V/250 kSPS

Standby current: 50 nA

20-lead 4 mm × 4 mm LFCSP package

Supports defense and aerospace applications (AQEC standard)

Military temperature range (−55°C to +125°C)

Controlled manufacturing baseline

Enhanced product change notification

Qualification data available on request

APPLICATIONS

Multichannel system monitoring

Battery-powered equipment

Medical instruments: ECG/EKG

Mobile communications: GPS

Power line monitoring

Data acquisition

Seismic data acquisition systems

Instrumentation

Process control

14-Bit, 8-Channel,

250 kSPS PulSAR ADC

AD7949-EP

FUNCTIONAL BLOCK DIAGRAM

0.5V TO VDD – 0.5V

0.1µF

0.5V TO VDD

10µF

2.3V TO 5.5V

REFIN REF VDD

BAND GAP

REF

TEMP

SENSOR

AD7949-EP

VIO

1.8V

TO

VDD

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

MUX

14-BIT SAR

ADC

ONE-POLE

LPF

SEQUENCER

SPI SERIAL

INTERFACE

CNV

SCK

SDO

DIN

GND

Figure 1.

Table 1. Multichannel 14-/16-Bit PulSAR® ADCs

Type Channels

14-Bit 8

250 kSPS

AD7949

500 kSPS ADC

ADA4841-1

16-Bit 4

16-Bit 8

AD7682 ADA4841-1

AD7689 AD7699

GENERAL DESCRIPTION

The AD7949-EP is an 8-channel, 14-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply, VDD.

The AD7949-EP contains all components for use in a multichannel, low power data acquisition system, including a true 14-bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or

4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

The AD7949-EP uses a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput.

The AD7949-EP is housed in a tiny 20-lead LFCSP with operation specified from −55°C to +125°C. Full details about this enhanced product are available in the AD7949 data sheet, which should be consulted in conjunction with this data sheet.

Rev. A

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AD7949-EP

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

REVISION HISTORY

5/15—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................ 1

Updated Outline Dimensions ....................................................... 12

Changes to Ordering Guide .......................................................... 12

4/11—Revision 0: Initial Version

Enhanced Product

Absolute Maximum Ratings ............................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Typical Performance Characteristics ..............................................9

Outline Dimensions ....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. A | Page 2 of 12

Enhanced Product

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V

REF

= VDD, all specifications −55 °C to +125 °C, unless otherwise noted.

AD7949-EP

Table 2.

Parameter Test Conditions/Comments

RESOLUTION

ANALOG INPUT

Voltage Range Unipolar mode

Absolute Input Voltage

Analog Input CMRR

Leakage Current at 25°C

Input Impedance

1

Positive input, unipolar and bipolar modes

Negative or COM input, unipolar mode

Negative or COM input, bipolar mode f

IN

= 250 kHz

Acquisition phase

THROUGHPUT

Conversion Rate

Full Bandwidth

2

¼ Bandwidth

2

VDD = 4.5 V to 5.5 V

VDD = 2.3 V to 4.5 V

VDD = 4.5 V to 5.5 V

Transient Response

VDD = 2.3 V to 4.5 V

Full-scale step, full bandwidth

Full-scale step, ¼ bandwidth

ACCURACY

No Missing Codes

Integral Linearity Error

Differential Linearity Error

Transition Noise REF = VDD = 5 V

Gain Error 4

Gain Error Match

Gain Error Temperature Drift

Offset Error

4

Offset Error Match

Offset Error Temperature Drift

Power Supply Sensitivity

AC ACCURACY

5

Dynamic Range

VDD = 5 V

 5%

Signal-to-Noise f

IN

= 20 kHz, V

REF

= 5 V f f

IN

IN

= 20 kHz, V

= 20 kHz, V

REF

REF

= 4.096 V internal REF

= 2.5 V internal REF

SINAD f

IN

= 20 kHz, V

REF

= 5 V f

IN

= 20 kHz, V

REF

= 5 V, −60 dB input f

IN

= 20 kHz, V

REF

= 4.096 V internal REF f

IN

= 20 kHz, V

REF

= 2.5 V internal REF

Total Harmonic Distortion f

IN

= 20 kHz

Spurious-Free Dynamic Range f

IN

= 20 kHz

Channel-to-Channel Crosstalk f

IN

= 100 kHz on adjacent channel(s)

SAMPLING DYNAMICS

−3 dB Input Bandwidth

Aperture Delay

Full bandwidth

¼ bandwidth

VDD = 5 V

Min Typ Max

14

Unit

Bits

0 +V

REF

V

−V

REF

/2 +V

REF

/2

−0.1 V

REF

+ 0.1 V

−0.1 +0.1

V

REF

/2 − 0.1 V

REF

/2 V

REF

/2 + 0.1

68

1 dB nA

0

0

0

250

200

62.5 kSPS kSPS kSPS

0 50

1.8

14.5 kSPS

μs

μs

14 Bits

−1

−1

±0.5

±0.25

0.1

+1

+1

LSB

3

LSB

LSB

−1

−1

84.5

84

±0.2

±1

±0.2

±1

85.6

85.5

85

84

85

33.5

85

84

−100

108

−125

1.7

0.425

2.5

+1

+1

LSB ppm/°C

LSB ppm/°C dB dB dB dB dB dB

6 dB dB dB dB dB

MHz

MHz ns

Rev. A | Page 3 of 12

AD7949-EP Enhanced Product

Parameter

INTERNAL REFERENCE

REF Output Voltage

Test Conditions/Comments

2.5 V, @ 25°C

Min

2.490

Typ

2.500

Max

2.510

Unit

V

4.096 4.086

REFIN Output Voltage

7

2.5

4.096

REF Output Current ±300 μA

Temperature Drift

Line Regulation

Long-Term Drift

Turn-On Settling Time

EXTERNAL REFERENCE

VDD = 5 V ± 5%

1000 hours

CREF = 10 μF

±10

±15

50

5 ppm/°C ppm/V ppm ms

Voltage Range

Current Drain

TEMPERATURE SENSOR

Temperature Sensitivity

REF input

REFIN input (buffered)

250 kSPS, REF = 5 V

Output Voltage 8 @

DIGITAL INPUTS

Logic Levels

V

IL

DIGITAL OUTPUTS

Data Format

Pipeline Delay

10

V

OL

V

OH

V

IH

I

IL

I

IH

9

POWER SUPPLIES

I

SINK

= +500 μA

I

SOURCE

= −500 μA

0.5

0.5

0.7 × VIO

VIO − 0.3

50

VDD + 0.3 V

VDD − 0.5 V

μA

283

1

VIO + 0.3

0.4 mV mV/°C

V

V

V

VIO

Standby Current 11, 12

Power Dissipation

Energy per Conversion

TEMPERATURE RANGE

13

Specified performance

Operating range

VDD and VIO = 5 V, @ 25°C

VDD = 2.5 V, 100 SPS throughput

VDD = 2.5 V, 100 kSPS throughput

VDD = 2.5 V, 200 kSPS throughput

VDD = 5 V, 250 kSPS throughput

VDD = 5 V, 250 kSPS throughput with internal reference

2.3

1.8

50

1.5

1.45

2.9

10.8

50

VDD + 0.3 V

VDD + 0.3 V nA

2.0

4.0

12.5

μW mW mW mW nJ

Specified Performance T

MIN

to T

MAX

°C

1 See the AD7949 data sheet.

2 The bandwidth is set in the configuration register.

3

LSB means least significant bit. With the 5 V input range, one LSB = 305 μV.

4

See the AD7949 data sheet. These specifications include full temperature range variation but not the error contribution from the external reference.

5 With VDD = 5 V, unless otherwise noted.

6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

7

This is the output from the internal band gap.

8

The output voltage is internal and present on a dedicated multiplexer input.

9 Unipolar mode: serial 14-bit straight binary.

Bipolar mode: serial 14-bit twos complement.

10

Conversion results available immediately after completed conversion.

11

With all digital inputs forced to VIO or GND as required.

12 During acquisition phase.

13

Contact an Analog Devices, Inc., sales representative for the extended temperature range.

Rev. A | Page 4 of 12

Enhanced Product

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications −55 °C to +125 °C, unless otherwise noted.

Table 3.

Parameter 1

Conversion Time: CNV Rising Edge to Data Available

Acquisition Time

Time Between Conversions

Data Write/Read During Conversion

CNV Pulse Width

SCK Period

SCK Low Time

SCK High Time

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV Low to SDO D15 MSB Valid

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV High or Last SCK Falling Edge to SDO High Impedance

CNV Low to SCK Rising Edge

DIN Valid Setup Time from SCK Rising Edge

DIN Valid Hold Time from SCK Rising Edge

1

See Figure 2 and Figure 3 for load conditions.

Symbol

t

CONV t

ACQ t

CYC t

DATA t

CNVH t

SCK t

SCKL t

SCKH t

HSDO t

EN t

DSDO t

DIS t

CLSCK t

SDIN t

HDIN

10

5

5

Min

1.8

4.0

10 t

DSDO

+ 2

11

11

4

Typ

32

18

22

25

18

23

28

Max

2.2

1.0

AD7949-EP

ns ns ns ns ns ns ns ns ns ns

Unit

µs

µs

µs

µs ns ns ns ns ns

Rev. A | Page 5 of 12

AD7949-EP

VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications −55 °C to +125 °C, unless otherwise noted.

Table 4.

Parameter 1

Conversion Time: CNV Rising Edge to Data Available

Acquisition Time

Time Between Conversions

Data Write/Read During Conversion

CNV Pulse Width

SCK Period

SCK Low Time

SCK High Time

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV Low to SDO D15 MSB Valid

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV High or Last SCK Falling Edge to SDO High Impedance

CNV Low to SCK Rising Edge

DIN Valid Setup Time from SCK Rising Edge

DIN Valid Hold Time from SCK Rising Edge

1

See Figure 2 and Figure 3 for load conditions.

t

DIS t

CLSCK t

SDIN t

HDIN

Symbol

t

CONV t

ACQ t

CYC t

DATA t

CNVH t

SCK t

SCKL t

SCKH t

HSDO t

DSDO t

EN

10

5

5

Min

1.8

5

10 t

DSDO

+ 2

12

12

5

Typ

Enhanced Product

27

35

45

50

24

30

38

48

21

Max

3.2

1.2 ns ns ns ns ns ns ns ns ns ns ns ns

Unit

µs

µs

µs

µs ns ns ns ns ns

I

OL

500µA

TO SDO

C

L

50pF

1.4V

500µA I

OH

Figure 2. Load Circuit for Digital Interface Timing

70% VIO

30% VIO t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2 t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2

1

2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2

0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

Rev. A | Page 6 of 12

Enhanced Product

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

INx,

1

COM

1

GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA

REF, REFIN

Supply Voltages

VDD, VIO to GND

VIO to VDD

DIN, CNV, SCK to GND

SDO to GND

Storage Temperature Range

Junction Temperature

θ

JA

Thermal Impedance (LFCSP)

θ

JC

Thermal Impedance (LFCSP)

1

See the AD7949 data sheet.

GND − 0.3 V to VDD + 0.3 V

−0.3 V to +7 V

−0.3 V to VDD + 0.3 V

−0.3 V to VIO + 0.3 V

−0.3 V to VIO + 0.3 V

−65°C to +150°C

150°C

47.6°C/W

4.4°C/W

AD7949-EP

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Rev. A | Page 7 of 12

AD7949-EP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD

REF

REFIN

GND

GND

1

2

3

4

5

AD7949-EP

TOP VIEW

(Not to Scale)

15

14

VIO

SDO

SCK 13

12

11

DIN

CNV

Enhanced Product

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type

1

Description

1, 20 VDD

2 REF

P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with

10 μF and 100 nF capacitors.

When using the internal reference for 2.5 V output, the minimum should be 3.0 V.

When using the internal reference for 4.096 V output, the minimum should be 4.5 V.

AI/O Reference Input/Output. See the AD7949 data sheet.

When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or

4.096 V.

When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power references.

For improved drift performance, connect a precision reference to REF (0.5 V to VDD).

For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the AD7949 data sheet.

3 REFIN

4, 5 GND

6 to 9 IN4 to IN7

10 COM

11 CNV

12 DIN

13 SCK

14 SDO

15 VIO

16 to 19 IN0 to IN3

21

(EPAD)

Exposed Pad

(EPAD)

AI/O

P

Internal Reference Output/Reference Buffer Input. See the AD7949 data sheet.

When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor.

When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as described above.

Power Supply Ground.

AI Channel 4 through Channel 7 Analog Inputs.

AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or V

REF

/2 V.

DI

Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled.

DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.

DI

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion.

DO Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,

2.5 V, 3 V, or 5 V).

AI Channel 0 through Channel 3 Analog Inputs.

NC The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane.

1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 8 of 12

Enhanced Product

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V to 5.5 V, V

REF

= 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted.

1.0

1.0

0.5

0.5

0

–0.5

–1.0

0 4,096 8,192

CODES

12,288 16,384

Figure 5. Integral Nonlinearity vs. Code, V

REF

= VDD = 5 V

300k

261,120

V

REF

= VDD = 5V

250k

200k

150k

100k

–100

–120

–140

–160

0

50k

0

0

0

1FFC

0 0 1 0 0

1FFD 1FFE 1FFF 2000 2001

CODE IN HEX

0 0

2002 2003

Figure 6. Histogram of a DC Input at Code Center

–20

–40

–60 f f

V

REF

= VDD = 5V

S

= 250kSPS

IN

= 19.9kHz

SNR = 85.3dB

SINAD = 85.2dB

THD = –100dB

SFDR = 103dB

SECOND HARMONIC = –110dB

THIRD HARMONIC = –103dB

–80

125 25 50 75

FREQUENCY (kHz)

100

Figure 7. 20 kHz FFT, V

REF

= VDD = 5 V

AD7949-EP

0

–0.5

–1.0

0 4,096 8,192

CODES

12,288 16,384

Figure 8. Differential Nonlinearity vs. Code, V

REF

= VDD = 5 V

300k

259,473

V

REF

= V

DD

= 2.5V

250k

200k

150k

100k

50k

0 0 0

955 693

0 0 0

0

1FFC 1FFD 1FFE 1FFF 2000 2001 2002 2003 2004

CODE IN HEX

Figure 9. Histogram of a DC Input at Code Center

0

–20

–40

–60

–80 f f

V

REF

= VDD = 2.5V

s

= 200kSPS

IN

= 19.9kHz

SNR = 84.2dB

SINAD = 82.4dB

THD = –84dB

SFDR = 85dB

SECOND HARMONIC = –100dB

THIRD HARMONIC = –85dB

–100

–120

–140

–160

–180

0 25 50

FREQUENCY (kHz)

75

Figure 10. 20 kHz FFT, V

REF

= VDD = 2.5 V

100

Rev. A | Page 9 of 12

AD7949-EP

90

85

80

75

70

65

60

0

88

86

SNR

SINAD

ENOB

VDD = V

REF

VDD = V

REF

VDD = V

REF

VDD = V

REF

= 5V, –0.5dB

= 5V, –10dB

= 2.5V, –0.5dB

= 2.5V, –10dB

50 100

FREQUENCY (kHz)

150

Figure 11. SNR vs. Frequency

84

200

15.5

82

80

15.0

14.5

14.0

13.5

78

1.0

1.5

2.0

2.5

3.0

3.5

4.0

REFERENCE VOLTAGE (V)

4.5

5.0

5.5

13.0

Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage

90 f

IN

= 20kHz

VDD = V

REF

= 5V

85

VDD = V

REF

= 2.5V

80

75

70

65

60

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

Figure 13. SNR vs. Temperature

85 105

125

Enhanced Product

90

85

80

75

70

65

VDD = V

REF

VDD = V

REF

VDD = V

REF

VDD = V

REF

= 5V, –0.5dB

= 5V, –10dB

= 2.5V, –0.5dB

= 2.5V, –10dB

130

125

120

115

110

105

100

95

90

85

80

75

70

1.0

60

0 50 100

FREQUENCY (kHz)

150

Figure 14. SINAD vs. Frequency

200

SFDR

THD

1.5

2.0

2.5

3.0

3.5

4.0

REFERENCE VOLTAGE (V)

4.5

5.0

Figure 15. SFDR and THD vs. Reference Voltage

–85

–90

–95

–100

–105

–110

–115

5.5

–120

–60

–65

–70

–75

–80

–90 f

IN

= 20kHz

–95

VDD = V

REF

= 5V

VDD = V

REF

= 2.5V

–100

–105

–110

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

Figure 16. THD vs. Temperature

85 105

125

Rev. A | Page 10 of 12

Enhanced Product

–60

–70

–80

–90

–100

–110

VDD = V

REF

VDD = V

REF

= 5V, –0.5dB

= 2.5V, –0.5dB

VDD = V

REF

VDD = V

REF

= 2.5V, –10dB

= 5V, –10dB

–120

0

2

50 100

FREQUENCY (kHz)

150

Figure 17. THD vs. Frequency

86

85

84

83

82

90

89

88

87

81

80

79

78

–10 f

IN

= 20kHz

VDD = V

REF

= 5V

VDD = V

REF

= 2.5V

–8 –6 –4

INPUT LEVEL (dB)

Figure 18. SNR vs. Input Level

–2

200

0

1

0

–1

UNIPOLAR ZERO

UNIPOLAR GAIN

BIPOLAR ZERO

BIPOLAR GAIN

–2

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

Figure 19. Offset and Gain Errors vs. Temperature

125

AD7949-EP

2750

2500

2250

2000

1750

1500

1250

1000

2.5V INTERNAL REF

4.096V INTERNAL REF

INTERNAL BUFFER, TEMP ON

INTERNAL BUFFER, TEMP OFF

EXTERNAL REF, TEMP ON

EXTERNAL REF, TEMP OFF

VIO

750

2.5

3.0

3.5

4.0

VDD SUPPLY (V)

4.5

5.0

Figure 20. Operating Currents vs. Supply

3000 f

S

= 200kSPS

2750

2500

2250

2000

VDD = 5V, INTERNAL 4.096V REF

VDD = 5V, EXTERNAL REF

1750 f

S

= 200kSPS

40

30

5.5

20

80

70

60

50

100

90

1500

1250

VDD = 2.5, EXTERNAL REF

VIO 60

40

120

100

80

180

160

140

1000

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

Figure 21. Operating Currents vs. Temperature

125

20

Rev. A | Page 11 of 12

AD7949-EP

OUTLINE DIMENSIONS

Enhanced Product

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

TOP VIEW

0.50

BSC

15

16

0.30

0.25

0.20

EXPOSED

PAD

20

1

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

11

10

BOTTOM VIEW

6

5

0.50

0.40

0.30

0.25 MIN

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 22. 20-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model 1

AD7949SCPZ-EP-RL7

1 Z = RoHS Compliant Part.

Temperature

Range

–55°C to +125°C

Package Description

20-Lead LFCSP_WQ, 7” Tape and Reel

Package

Option

CP-20-10

Ordering

Quantity

1,500

©2011–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D09822-0-5/15(A)

Rev. A | Page 12 of 12

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