16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP AD7985 Data Sheet

16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP AD7985 Data Sheet

16-Bit, 2.5 MSPS, PulSAR

15.5 mW ADC in LFCSP

Data Sheet

AD7985

FEATURES

16-bit resolution with no missing codes

Throughput: 2.5 MSPS (TURBO high), 2.0 MSPS (TURBO low)

Low power dissipation

15.5 mW at 2.5 MSPS, with external reference

28 mW at 2.5 MSPS, with internal reference

INL: ±0.7 LSB typical, ±1.5 LSB maximum

SNR

88.5 dB, with on-chip reference

90 dB, with external reference

4.096 V internal reference: typical drift of ±10 ppm/°C

Pseudo differential analog input voltage range

0 V to V

REF

with V

REF

up to 5.0 V

Allows use of any input range

No pipeline delay

Logic interface: 1.8 V/2.5 V/2.7 V

Proprietary serial interface SPI-/QSPI™-/MICROWIRE™-/DSPcompatible

1

Ability to daisy-chain multiple ADCs with busy indicator

20-lead, 4 mm × 4 mm LFCSP

0V

TO

V

REF

APPLICATION DIAGRAM

5V 2.5V

IN+

BVDD

AVDD,

DVDD

VIO

TURBO

IN–

AD7985

GND REF

SDI

SCK

SDO

CNV

10µF

NOTES

1. GND REFERS TO REFGND, AGND, AND DGND.

Figure 1.

1.8V

TO

2.7V

VIO

3- OR 4-WIRE

INTERFACE:

SPI, CS,

DAISY CHAIN

(TURBO = LOW)

APPLICATIONS

Battery-powered equipment

Communications

ATE

Data acquisition systems

Medical instruments

GENERAL DESCRIPTION

The AD7985

1

is a 16-bit, 2.5 MSPS successive approximation analog-to-digital converter (SAR ADC). It contains a low power, high speed, 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and a versatile serial interface port. On the rising edge of CNV, the

AD7985 samples an analog input, IN+, between 0 V and REF with respect to a ground sense, IN−. The AD7985 features a very high sampling rate turbo mode (TURBO is high) and a reduced power normal mode (TURBO is low) for low power applications where the power is scaled with the throughput.

In normal mode (TURBO is low), the SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V supplies using the separate VIO supply.

The AD7985 is available in a 20-lead LFCSP with operation specified from −40°C to +85°C.

1

Protected by U. S. Patent 6,703,961.

Table 1. MSOP, LFCSP, 14-/16-/18-Bit PulSAR® ADCs

1

Type

14-Bit

16-Bit

100 kSPS

AD7940

AD7680

AD7683

250 kSPS

AD7942

2

AD7685

AD7687

2

2

AD7684

18-Bit

AD7694

AD7691

2

1 See www.analog.com

for the latest selection of PulSAR ADCs and ADC drivers.

2 Pin for pin compatible with all other devices marked with this endnote.

3

The AD7985 and AD7986 are pin for pin compatible.

400 kSPS to 500 kSPS

AD7946

2

AD7686

2

AD7688

2

AD7693

2

AD7690

2

≥1000 kSPS

AD7980

2

AD7983

2

AD7985

3

AD7982

2

AD7984

2

AD7986 3

ADC Driver

ADA4941-1

ADA4841-1

AD8021

ADA4941-1

ADA4841-1

AD8021

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

AD7985

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications ....................................................................................... 1

 

Application Diagram ........................................................................ 1

 

General Description ......................................................................... 1

 

Revision History ............................................................................... 2

 

Specifications ..................................................................................... 3

 

Timing Specifications .................................................................. 5

 

Absolute Maximum Ratings ............................................................ 6

 

ESD Caution .................................................................................. 6

 

Pin Configuration and Function Descriptions ............................. 7

 

Typical Performance Characteristics ............................................. 9

 

Terminology .................................................................................... 12

 

Theory of Operation ...................................................................... 13

 

Circuit Information .................................................................... 13

 

Converter Operation .................................................................. 13

 

Conversion Modes of Operation .............................................. 13

 

Typical Connection Diagram ................................................... 14

 

REVISION HISTORY

3/16—Rev. B to Rev. C

Changes to Table 1 ............................................................................ 1

Change to Endnote 3, Table 1 ......................................................... 3

Change to Signal-to-Noise-and-Distortion Ratio Parameter,

Table 2 ................................................................................................ 3

Deleted Endnote 4, Table 2 .............................................................. 3

Changes to Figure 4 .......................................................................... 7

Changes to Figure 23 ...................................................................... 14

Changes to Driver Amplifier Choice Section ............................. 15

Change to Reference Decoupling Section ................................... 16

Changes to Reading During Conversion, Fast Host (Turbo or

Normal Mode) Section and Split-Reading, Any Speed Host

(Turbo or Normal Mode) Section ................................................ 18

Changes to Figure 31 ...................................................................... 21

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 27

Data Sheet

Analog Inputs ............................................................................. 15

 

Driver Amplifier Choice ........................................................... 15

 

Voltage Reference Input ............................................................ 16

 

Power Supply ............................................................................... 16

 

Digital Interface .............................................................................. 17

 

Data Reading Options ............................................................... 18

 

CS Mode, 3-Wire Without Busy Indicator ............................. 19

 

CS Mode, 3-Wire with Busy Indicator .................................... 20

 

CS Mode, 4-Wire Without Busy Indicator ............................. 21

 

CS Mode, 4-Wire with Busy Indicator .................................... 22

 

Chain Mode Without Busy Indicator ...................................... 23

 

Chain Mode with Busy Indicator ............................................. 24

 

Applications Information .............................................................. 25

 

Layout .......................................................................................... 25

 

Evaluating the AD7985 Performance ...................................... 25

 

Outline Dimensions ....................................................................... 27

 

Ordering Guide .......................................................................... 27

 

7/14—Rev. A to Rev. B

Added Patent Endnote ...................................................................... 1

Changes to Figure 21 ...................................................................... 13

Changes to Data Reading Options Section ................................. 18

Updated Outline Dimensions ....................................................... 27

8/10—Rev. 0 to Rev. A

Change to Table 4, Conversion Time: CNV Rising Edge to Data Available ................................................................................ 5

9/09—Revision 0: Initial Version

Rev. C | Page 2 of 28

Data Sheet

SPECIFICATIONS

AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, V

REF

= 4.096 V, T

A

= −40°C to +85°C, unless otherwise noted.

AD7985

Table 2.

Parameter

RESOLUTION

ANALOG INPUT

Voltage Range

Absolute Input Voltage

Leakage Current at 25°C

Input Impedance

ACCURACY

No Missing Codes

Differential Nonlinearity Error, DNL

Integral Nonlinearity Error, INL

Transition Noise

Gain Error, T

MIN

to T

MAX

2

Gain Error Temperature Drift

Zero Error, T

MIN

to T

MAX

2

Zero Temperature Drift

Power Supply Sensitivity

THROUGHPUT

Conversion Rate

Transient Response

AC ACCURACY

Dynamic Range

Signal-to-Noise Ratio, SNR

Spurious-Free Dynamic Range, SFDR

Total Harmonic Distortion, THD

Test Conditions/Comments

(IN+) − (IN−)

IN+

IN−

Acquisition phase

AVDD = 2.5 V ± 5%

Full-scale step

V

REF

= 4.096 V, internal reference

V

REF

= 5.0 V, external reference f

IN

= 20 kHz, V

REF

= 4.096 V, internal reference f

IN

= 20 kHz, V reference

REF

= 5.0 V, external f

IN

= 20 kHz f

IN

= 20 kHz, V reference

REF

= 4.096 V, internal f

IN

= 20 kHz, V

REF

= 4.096 V

−0.99

0

87.5

89.0

87.0

Min

16

Typ Max

0

−0.1

−0.1

16

−0.99

−1.50

−15

250

+0.1

See the Analog Inputs section

V

REF

V

REF

+ 0.1

±0.50

±0.7

0.8

±2

+0.99

+1.50

+15

±0.8

±0.08

0.55

90

89

90

88.5

+0.99

2.5

100

89.0 90.0

103

−100 dB

3 dB 3 dB 3

Signal-to-Noise-and-Distortion Ratio,

SINAD

SAMPLING DYNAMICS

−3 dB Input Bandwidth

90

19 dB 3

MHz

Aperture Delay 0.7 ns

1

2

3

LSB means least significant bit. With the 4.096 V input range, one LSB is 62.5 µV.

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. ppm/°C mV ppm/°C dB 3

MSPS ns dB

3 dB 3 dB 3

Unit

Bits

V

V

V nA

Bits

LSB 1

LSB 1

LSB 1

LSB

1

Rev. C | Page 3 of 28

AD7985

Table 3.

Parameter

INTERNAL REFERENCE

Output Voltage

Temperature Drift

Line Regulation

Turn-On Settling Time

REFIN Output Voltage

REFIN Output Resistance

EXTERNAL REFERENCE

Voltage Range

Current Drain

REFERENCE BUFFER

REFIN Input Voltage Range

REFIN Input Current

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format

Pipeline Delay

Test Conditions/Comments

PDREF is low

T

A

= 25°C

−40°C to +85°C

AVDD = 2.5 V ± 5%

C

REF

= 10 μF, C

REFIN

= 0.1 μF

REFIN at 25°C

PDREF is high, REFIN is low

V

OL

V

OH

I

SINK

= +500 µA

I

SOURCE

= −500 µA

POWER SUPPLIES

AVDD, DVDD

BVDD

VIO

Standby Current 1, 2

Power Dissipation

With Internal Reference

Specified performance

AVDD = DVDD = VIO = 2.5 V

2.5 MSPS throughput

2.0 MSPS throughput

With External Reference 2.5 MSPS throughput

2.0 MSPS throughput

TEMPERATURE RANGE 3

Specified Performance T

MIN

to T

MAX

1

2

3

With all digital inputs forced to VIO or GND as required.

During acquisition phase.

Contact an Analog Devices, Inc., sales representative for the extended temperature range.

Data Sheet

2.375

4.75

1.8

−40

2.4

Min

4.081

Typ

4.096

±10

±50

40

1.2

6

500

1.2

160

−0.3

0.9 × VIO

−1

−1

0.1 × VIO

VIO + 0.3

+1

+1

Serial 16 bits, straight binary

Conversion results available immediately after completed conversion

VIO − 0.3

0.4

5.1

Max

4.111

1.0

28

25

2.5

5.0

2.5

15.5

12

33

30

2.625

5.25

2.7

17

13

+85

V

µA

V

µA

Unit

V ppm/°C ppm/V ms

V kΩ

V

V

µA

µA

V

V

V

V

V

µA mW mW mW mW

°C

Rev. C | Page 4 of 28

Data Sheet

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, V

REF

= 4.096 V, T

A

= −40°C to +85°C, unless otherwise noted.

1

Table 4.

Parameter

Conversion Time: CNV Rising Edge to Data Available

Acquisition Time

Time Between Conversions

CNV Pulse Width

Data Read During Conversion

Quiet Time During Acquisition from Last SCK

Falling Edge to CNV Rising Edge

SCK Period

SCK Low Time

SCK High Time

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

CNV or SDI Low to SDO D15 MSB Valid

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance

SDI Valid Setup Time from CNV Rising Edge

SDI Valid Hold Time from CNV Rising Edge

SCK Valid Setup Time from CNV Rising Edge

SCK Valid Hold Time from CNV Rising Edge

SDI Valid Setup Time from SCK Falling Edge

SDI Valid Hold Time from SCK Falling Edge

SDI High to SDO High

1

See Figure 2 and Figure 3 for load conditions.

Symbol Test Conditions/Comments

t

CONV

Turbo mode/normal mode t

ACQ t

CYC t

CNVH t

DATA t

QUIET t

SCK t

SCK t

SCKL t

SCKH t

HSDO t

DSDO t

EN t

DIS t

SSDICNV t

HSDICNV t

HSDICNV t

SSCKCNV t

HSCKCNV t

SSDISCK t

HSDISCK t

DSDOSDI

Turbo mode/normal mode

CS mode

Turbo mode/normal mode

CS mode

Chain mode

CS mode

CS mode

4

0

Chain mode

Chain mode

Chain mode

Chain mode

Chain mode

Chain mode with busy indicator

2

3

0

5

5

Min

9

11

3.5

3.5

2

80

400/500

10

20

Typ Max Unit

320/420 ns

15

4

5

8

AD7985

ns ns ns

190/290 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

500µA I

OL

TO SDO

C

L

20pF

1.4V

500µA I

OH

Figure 2. Load Circuit for Digital Interface Timing

10% VIO

90% VIO t

DELAY

V

V

IH

1

IL

1 t

DELAY

V

V

IH

1

IL

1

1

MINIMUM V

IH

AND MAXIMUM V

IL

USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

Figure 3. Voltage Levels for Timing

Rev. C | Page 5 of 28

AD7985

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+, IN− to GND

1

Supply Voltage

REF, BVDD to GND, REFGND

AVDD, DVDD, VIO to GND

AVDD, DVDD to VIO

Digital Inputs to GND

Digital Outputs to GND

Storage Temperature Range

Junction Temperature

θ

JA

Thermal Impedance

20-Lead LFCSP

Lead Temperatures

Vapor Phase (60 sec)

Infrared (15 sec) 220°C

1

See the Analog Inputs section for an explanation of IN+ and IN−.

−0.3 V to V

REF

+ 0.3 V or ±130 mA

−0.3 V to +6.0 V

−0.3 V to +2.7 V

−6 V to +3 V

−0.3 V to VIO + 0.3 V

−0.3 V to VIO + 0.3 V

−65°C to +150°C

150°C

30.4°C/W

215°C

Data Sheet

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Rev. C | Page 6 of 28

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REF

REF

REFGND

REFGND

IN–

1

2

3

4

5

AD7985

TOP VIEW

(Not to Scale)

15 TURBO

14

13

SDI

CNV

12 SCK

11 DVDD

AD7985

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.

FOR INCREASED RELIABILITY OF THE SOLDER JOINTS,

IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO

THE SYSTEM GROUND PLANE.

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic

Type

1

Description

1, 2

3, 4

5

6

7

8

9

10

11

12

13

14

REF

REFGND

IN−

IN+

PDREF

VIO

SDO

DGND

DVDD

SCK

CNV

SDI

AI

AI

AI

AI

DI

P

DO

P

P

DI

DI

DI

Reference Output/Input Voltage.

When PDREF is low, the internal reference and buffer are enabled, producing 4.096 V on this pin.

When PDREF is high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 V.

Decoupling is required with or without the internal reference and buffer. This pin is referred to the

REFGND pins and must be decoupled closely to the REFGND pins with a 10 µF capacitor.

Reference Input Analog Ground.

Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote ground sense.

Analog Input. This pin is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to V

REF

.

Internal Reference Power-Down Input. When this pin is low, the internal reference is enabled. When this pin is high, the internal reference is powered down and an external reference must be used.

Input/Output Interface Digital Power. Nominally at the same supply voltage as the host interface

(1.8 V, 2.5 V, or 2.7 V).

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

Digital Power Ground.

Digital Power. Nominally at 2.5 V.

Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.

Convert Input. This input has multiple functions. On the leading edge, it initiates the conversions and selects the interface mode of the device: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data must be read when CNV is high.

Serial Data Input. This input has multiple functions. It selects the interface mode of the ADC as follows.

15

16

17, 18

TURBO

AVDD

AGND

DI

P

P

Chain mode is selected if SDI is low during the CNV rising edge. In chain mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In CS mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled.

Conversion Mode Selection. When TURBO is high, the maximum throughput (2.5 MSPS) is achieved, and the ADC does not power down between conversions. When TURBO is low, the maximum throughput is lower (2.0 MSPS), and the ADC powers down between conversions.

Input Analog Power. Nominally at 2.5 V.

Analog Power Ground.

Rev. C | Page 7 of 28

AD7985 Data Sheet

Pin No. Mnemonic

19 BVDD

20 REFIN

Type 1 Description

P Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum

SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the

REFIN pin to ground. The external reference buffer must be connected to the BVDD pin.

AI/O Internal Reference Output/Reference Buffer Input.

When PDREF is low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 µF typical).

When PDREF is high, use an external reference to provide 1.2 V (typical) to this pin.

When PDREF is high and REFIN is low, the on-chip reference buffer and the band gap reference are powered down. An external reference must be connected to REF and BVDD.

21 Exposed Pad EP The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane.

1 AI = analog input, AI/O = bidirectional analog, DI = digital input, DO = digital output, and P = power.

Rev. C | Page 8 of 28

Data Sheet AD7985

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, V

REF

= 5.0 V, external reference (PDREF is high, REFIN is low), unless otherwise noted.

1.25

1.00

POSITIVE INL = +0.38LSB

NEGATIVE INL = –0.46LSB

POSITIVE DNL = +0.19LSB

NEGATIVE DNL = –0.20LSB

1.00

0.75

0.75

0.50

0.50

0.25

0.25

0 0

–0.25

–0.25

–0.50

–0.75

–1.00

–0.50

–0.75

–1.25

0 65,536

–1.00

0 65,536 16,384 32,768

CODE

49,152

Figure 5. Integral Nonlinearity vs. Code

16,384 32,768

CODE

49,152

Figure 8. Differential Nonlinearity vs. Code

60,000

57,138

60,000

48,730

53,522

50,000

50,000

38,843

40,000

40,000

30,000

26,249

30,000

20,000

10,000

0

6150

2537

0

122

33 0

7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004

CODE IN HEX

Figure 6. Histogram of DC Input at Code Center (External Reference)

60,000

49,585

50,000

40,000

30,000

33,064

31,957

20,000

10,000

8455

7024

0 11

565

403

8 0

0

7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005

CODE IN HEX

Figure 7. Histogram of DC Input at Code Center (Internal Reference)

20,000

15,645

11,888

10,000

0

0 2

479

800

6 0

7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004

CODE IN HEX

Figure 9. Histogram of DC Input at Code Transition (External Reference)

50,000

45,000

40,000

35,000

30,000

25,000

20,000

15,000

10,000

20,474

46,649

43,622

15,598

5000

0

0

90

2947

1662

30

0

7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005

CODE IN HEX

Figure 10. Histogram of DC Input at Code Transition (Internal Reference)

Rev. C | Page 9 of 28

AD7985

0

–80

–100

–120

–140

–20

–40

–60

–160

–180

0 f f

S

= 2.5MSPS

IN

= 20kHz

SNR = 89.87dB

THD = –102.76dB

SINAD = 89.66dB

250 500 750

FREQUENCY (kHz)

1000

Figure 11. FFT Plot (External Reference)

1250

100 16

95

90

15

ENOB

SNR

14

SINAD

13 85

75

70

65

1

90

85

80

80 12

2.50

2.75

3.00

3.25

3.50

3.75

4.00

4.25

4.50

4.75

5.00

REFERENCE VOLTAGE (V)

Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage

95

10 100

FREQUENCY (kHz)

Figure 13. SINAD vs. Frequency

1000

Data Sheet

–80

–100

–120

–140

–160

–180

0

0

–20

–40

–60

–90 f f

S

= 2.5MSPS

IN

= 20kHz

SNR = 88.45dB

THD = –103.42dB

SINAD = 88.32dB

250 500 750

FREQUENCY (kHz)

1000

Figure 14. FFT Plot (Internal Reference)

1250

100

–95 95

SFDR

–100 90

–100

–105

–90

–95

–110

1

–105 85

THD

–110 80

2.50

2.75

3.00

3.25

3.50

3.75

4.00

4.25

4.50

4.75

5.00

REFERENCE VOLTAGE (V)

Figure 15. THD and SFDR vs. Reference Voltage

–85

10 100

FREQUENCY (kHz)

Figure 16. THD vs. Frequency

1000

Rev. C | Page 10 of 28

Data Sheet

95

94

93

92

91

90

89

88

87

86

85

–10 –9 –8 –7 –6 –5 –4

INPUT LEVEL (dBFS)

–3

Figure 17. SNR vs. Input Level

–2 –1 0

1.4

1.2

1.0

0.8

2.0

1.8

1.6

0.6

0.4

I

AVDD

I

DVDD

I

VIO

I

BVDD

I

REF

0.2

0

2.375

2.425

2.475

2.525

AVDD AND DVDD VOLTAGE (V)

2.575

Figure 18. Operating Current vs. Supply Voltage

2.625

AD7985

10

8

6

1.4

1.2

1.0

0.8

2.0

1.8

1.6

0.6

0.4

0.2

0

–55

I

BVDD

I

REF

I

AVDD

–35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

Figure 19. Operating Current vs. Temperature

14

125

12

4

I

AVDD

+ I

DVDD

+ I

VIO

2

0

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

Figure 20. Power-Down Current vs. Temperature

125

Rev. C | Page 11 of 28

AD7985

TERMINOLOGY

Aperture Delay

Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together.

The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is expressed in bits and is related to SINAD as follows:

ENOB

= (

SINAD dB

− 1.76)/6.02

Effective Resolution

Effective resolution is expressed in bits and is calculated as follows:

Effective Resolution

= log

2

(2

N

/

RMS Input Noise

)

Gain Error

The last transition (from 111 … 10 to 111 … 11) must occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels.

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line (see Figure 22).

Data Sheet

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is expressed in bits and is calculated as follows:

Noise-Free Code Resolution

= log

2

(2

N

/

Peak-to-Peak Noise

)

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

Signal-to-Noise-and-Distortion Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.

Transient Response

Transient response is the time required for the ADC to accurately acquire the input after a full-scale step function is applied.

Zero Error

Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB.

Rev. C | Page 12 of 28

Data Sheet

THEORY OF OPERATION

IN+

AD7985

REF

GND

MSB

32,768C 16,384C

32,768C 16,384C

MSB

4C 2C

4C 2C

C

C

C

C

LSB SW+

SWITCHES CONTROL

COMP

CONTROL

LOGIC

BUSY

OUTPUT CODE

LSB SW+

CNV

IN–

CIRCUIT INFORMATION

The AD7985 is a fast, low power, single-supply, precise, 16-bit

ADC using a successive approximation architecture. The AD7985 features different modes to optimize performance according to the application. In turbo mode, the AD7985 is capable of converting

2,500,000 samples per second (2.5 MSPS).

The AD7985 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications.

The AD7985 can be interfaced to any 1.8 V to 2.7 V digital logic family. It is available in a space-saving 20-lead LFCSP that allows flexible configurations. It is pin for pin compatible with the

18-bit AD7986.

CONVERTER OPERATION

The AD7985 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors that are connected to the two comparator inputs.

During the acquisition phase, the terminals of the array tied to the input of the comparator are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is completed and the CNV input goes high, a conversion phase is initiated.

Figure 21. ADC Simplified Schematic

When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the analog inputs and connected to the REFGND input. Therefore, the differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and

REF, the comparator input varies by binary weighted voltage steps (V

REF

/2, V

REF

/4, … V

REF

/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the device returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator.

Because the AD7985 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.

CONVERSION MODES OF OPERATION

The AD7985 features two conversion modes of operation: turbo and normal. Turbo conversion mode (TURBO is high) allows the fastest conversion rate of up to 2.5 MSPS and does not power down between conversions. The first conversion in turbo mode must be ignored because it contains meaningless data.

For applications that require lower power and slightly slower sampling rates, the normal mode (TURBO is low) allows a maximum conversion rate of 2.0 MSPS and powers down between conversions. The first conversion in normal mode contains meaningful data.

Rev. C | Page 13 of 28

AD7985

Transfer Functions

The ideal transfer function for the AD7985

is shown in Figure 22 and Table 7.

Data Sheet

Table 7. Output Codes and Ideal Input Voltages

Description

FSR – 1 LSB

Midscale + 1 LSB

Analog Input,

V

REF

= 4.096 V

4.095938 V

2.048063 V

Digital Output

Code (Hex)

0xFFFF

1

0x8001

111 ... 111

111 ... 110

111 ... 101

000 ... 010

000 ... 001

000 ... 000

–FSR

–FSR + 1 LSB

–FSR + 0.5 LSB

+FSR – 1 LSB

+FSR – 1.5 LSB

ANALOG INPUT

Figure 22. ADC Ideal Transfer Function

Midscale – 1 LSB 2.047938 V 0x7FFF

–FSR + 1 LSB 62.5 μV 0x0001

V 0x0000

2

1

This is also the code for an overranged analog input (V

IN+

− V

IN−

above

V

REF

− REFGND).

2 This is also the code for an underranged analog input (V

IN+

− V

IN−

below REFGND).

TYPICAL CONNECTION DIAGRAM

Figure 23 shows an example of the recommended connection

diagram for the AD7985 when multiple supplies are available.

5V 2.5V

1.8V

TO

2.7V

0V TO V

REF

V+

V–

10 Ω

1.5nF

IN+

IN–

BVDD

REF

AVDD,

DVDD

AD7985

GND

VIO

TURBO

SDI

SCK

SDO

CNV

10µF

NOTES

1. GND REFERS TO REFGND, AGND, AND DGND.

Figure 23. Typical Application Diagram with Multiple Supplies

VIO

3- OR 4-WIRE

INTERFACE:

SPI, CS,

DAISY CHAIN

(TURBO = LOW)

Rev. C | Page 14 of 28

Data Sheet

ANALOG INPUTS

Figure 24 shows an equivalent circuit of the input structure of

the AD7985 .

The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Take care to ensure the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of

130 mA maximum. However, if the supplies of the input buffer

(for example, the V+ and V− supplies of the buffer amplifier in

Figure 23) are different from those of REF, the analog input

signal may eventually exceed the supply rails by more than

0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can protect the device.

REF

D1

R

IN

C

IN

IN+ OR IN–

C

PIN

D2

REFGND

Figure 24. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected.

During the acquisition phase, the impedance of the analog inputs (IN+ and IN−) can be modeled as a parallel combination of Capacitor C

PIN

and the network formed by the series connection of Resistor R

IN

and Capacitor C

IN

. C

PIN

is primarily the pin capacitance. R

IN

is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches.

C

IN

is typically 30 pF and is mainly the ADC sampling capacitor.

During the sampling phase, where the switches are closed, the input impedance is limited to C

PIN

. R

IN

and C

IN

make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits noise.

When the source impedance of the driving circuit is low, the AD7985 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.

AD7985

DRIVER AMPLIFIER CHOICE

Although the AD7985 is easy to drive, the driver amplifier must meet the following requirements:

The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7985 . The noise from the driver is filtered by the AD7985 analog input circuit one-pole, lowpass filter, made by R

IN

and C

IN

, or by the external filter, if one is used. Because the typical noise of the AD7985 is

50 µV rms, the SNR degradation due to the amplifier is

SNR

LOSS

=

20 log

50

50

2

+

π

2

f

3dB

(

Ne

N

)

2

 where:

f

–3dB

is the input bandwidth, in megahertz, of the AD7985

(19 MHz) or the cutoff frequency of the input filter, if one is used.

N

is the noise gain of the amplifier (for example, 1 in buffer configuration).

e

N

is the equivalent input noise voltage of the operational amplifier in nV/√Hz.

For ac applications, the driver must have a THD performance commensurate with that of the AD7985 .

For multichannel multiplexed applications, the driver amplifier and the AD7985 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level

(0.0015%, 15 ppm). In the data sheet of the driver amplifier, settling at 0.1% to 0.01% is more commonly specified. This value may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection.

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

AD8021

AD8022

ADA4899-1

AD8014

Very low noise and high frequency

Low noise and high frequency

Ultralow noise and high frequency

Low power and high frequency

Rev. C | Page 15 of 28

AD7985

VOLTAGE REFERENCE INPUT

The AD7985 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.

The internal reference of the AD7985 provides excellent performance and can be used in almost all applications.

Internal Reference, REF = 4.096 V (PDREF Low)

To use the internal reference, the PDREF input must be low.

This enables the on-chip band gap reference and buffer, resulting in a 4.096 V reference on the REF pin (1.2 V on REFIN).

The internal reference is temperature compensated to

4.096 V ± 15 mV. The reference is trimmed to provide a typical drift of 10 ppm/°C.

The output resistance of REFIN is 6 kΩ when the internal reference is enabled. It is necessary to decouple this pin with a ceramic capacitor of at least 100 nF. The output resistance of

REFIN and the decoupling capacitor form an RC filter, which helps to reduce noise.

Because the output impedance of REFIN is typically 6 kΩ, relative humidity (among other industrial contaminants) can directly affect the drift characteristics of the reference. A guard ring typically reduces the effects of drift under such circumstances.

However, the fine pitch of the AD7985 makes this difficult to implement. One solution, in these industrial and other types of applications, is to use a conformal coating, such as Dow Corning®

1-2577 or HumiSeal® 1B73.

External 1.2 V Reference and Internal Buffer (PDREF High)

To use an external reference along with the internal buffer, PDREF must be high. This powers down the internal reference and allows the 1.2 V reference to be applied to REFIN, producing 4.096 V

(typically) on the REF pin.

External Reference (PDREF High, REFIN Low)

To apply an external reference voltage directly to the REF pin,

PDREF must be tied high and REFIN must be tied low. BVDD must also be driven to the same potential as REF. For example, if REF = 2.5 V, BVDD must be tied to 2.5 V.

The advantages of directly using an external voltage reference are as follows:

SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a larger reference voltage (5 V) instead of a typical 4.096 V reference when the internal reference is used. This is calculated by

SNR

20 log

4 .

096

5 .

0

Power savings when the internal reference is powered down (PDREF high).

Rev. C | Page 16 of 28

Data Sheet

Reference Decoupling

The AD7985 voltage reference input, REF, has a dynamic input impedance that requires careful decoupling between the REF

and REFGND pins. The Layout section describes how this can

be done.

When using an external reference, a very low impedance source

(for example, a reference buffer using the AD8031 or the AD8605 ) and a 10 μF (X5R, 0805 size) ceramic chip capacitor are appropriate for optimum performance.

If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For example, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR434 reference.

If desired, a reference decoupling capacitor with a value as small as 2.2 μF can be used with minimal impact on performance, especially DNL.

In any case, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and REFGND pins.

POWER SUPPLY

The AD7985 has four power supply pins: an analog supply

(AVDD), a buffer supply (BVDD), a digital supply (DVDD), and a digital input/output interface supply (VIO). VIO allows direct interface with any logic from 1.8 V to 2.7 V. To reduce the number of supplies needed, VIO, DVDD, and AVDD can be tied together. The power supplies do not need to be started in a particular sequence. In addition, the AD7985 is very insensitive to power supply variations over a wide frequency range.

In normal mode, the AD7985 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. This makes the device ideal for low sampling rates (even a few SPS) and batterypowered applications.

10

1

0.1

I

BVDD

I

AVDD

I

DVDD

I

VIO

I

VREF

0.01

0.1

1

SAMPLING RATE (MSPS)

Figure 25. Operating Current vs. Sampling Rate in Normal Mode

Data Sheet

DIGITAL INTERFACE

Although the AD7985 has a reduced number of pins, it offers flexibility in the serial interface modes.

In CS mode, the AD7985 is compatible with SPI, MICROWIRE,

QSPI, and digital hosts. In CS mode, the AD7985 can use either a

3-wire or a 4-wire interface. A 3-wire interface that uses the CNV,

SCK, and SDO signals minimizes wiring connections, which is useful, for example, in isolated applications. A 4-wire interface that uses the SDI, CNV, SCK, and SDO signals allows CNV, which initiates conversions, to be independent of the readback timing

(SDI). This is useful in low jitter sampling or simultaneous sampling applications.

In chain mode, the AD7985 provides a daisy-chain feature that uses the SDI input for cascading multiple ADCs on a single data line similar to a shift register. Chain mode is available only in normal mode (TURBO is low).

The mode in which the device operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if

SDI is high, and chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, chain mode is always selected.

In normal mode operation, the AD7985 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback.

AD7985

The busy indicator feature is enabled in CS mode if CNV or

SDI is low when the ADC conversion ends (see Figure 29 and

Figure 33). TURBO must be kept low for both digital interfaces.

When CNV is low, readback can occur during conversion or acquisition, or it can be split across acquisition and conversion, as described in the following sections.

A discontinuous SCK is recommended because the device is selected with CNV low, and SCK activity begins to clock out data.

Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, SDI, and SDO) during the conversion.

However, due to the possibility of performance degradation, digital activity must occur only prior to the safe data reading time, t

DATA

, because the AD7985 provides error correction circuitry that can correct for an incorrect bit decision during this time.

From t

DATA

to t

CONV

, there is no error correction, and conversion results may be corrupted.

Similarly, t

QUIET

, the time from the last falling edge of SCK to the rising edge of CNV, must remain free of digital activity.

The user must configure the AD7985 and initiate the busy indicator (if desired in normal mode) prior to t

DATA

.

It is also possible to corrupt the sample by having SCK near the sampling instant. Therefore, it is recommended that the digital pins be kept quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation.

Rev. C | Page 17 of 28

AD7985

DATA READING OPTIONS

There are three different data reading options for the AD7985 .

There is the option to read during conversion, to split the read

across acquisition and conversion (see Figure 26 and Figure 27),

and, in normal mode, to read during acquisition. The desired

SCK frequency largely determines which reading option to use.

Reading During Conversion, Fast Host (Turbo or

Normal Mode)

When reading during conversion (n), conversion results are for the previous (n − 1) conversion. Reading must occur only up to t

DATA

and, because this time is limited, the host must use a fast SCK.

The required SCK frequency is calculated by

f

SCK

Number t

DATA

_

SCK t

CNVH

_

Edges t

EN

To determine the minimum SCK frequency, follow these examples to read data from conversion (n − 1).

For turbo mode (2.5 MSPS),

Number_SCK_Edges

= 16;

t

DATA

= 190 ns;

t

CNVH

= 10 ns;

t

EN

= 5 ns

f

SCK

= 16/(190 ns – 10 ns – 5 ns) = 91.5 MHz

For normal mode (2.0 MSPS),

Number_SCK_Edges

= 16;

t

DATA

= 290 ns;

t

CNVH

= 10 ns;

t

EN

= 5 ns

f

SCK

= 16/(290 ns − 10 ns − 5 ns) = 58.2 MHz

The time between t

DATA

and t

CONV

is an input/output quiet time during which digital activity must not occur, or sensitive bit decisions may be corrupted.

Split-Reading, Any Speed Host (Turbo or Normal Mode)

To allow for a slower SCK, there is the option of a split read, where data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous

(n − 1) conversion.

Similar to reading during conversion, split-reading must occur only up to t

DATA

. For the maximum throughput, the only time restriction is that split-reading take place during the t

ACQ

(minimum) +

(t

DATA

− t

QUIET

) time. The time between the falling edge of SCK and CNV rising is an acquisition quiet time, t

QUIET

.

Data Sheet

To determine how to split the read for a particular SCK frequency, follow these examples to read data from conversion (n − 1).

For turbo mode (2.5 MSPS),

f

SCK

= 75 MHz;

t

DATA

= 190 ns;

t

CNVH

= 10 ns;

t

EN

= 5 ns

Number_SCK_Edges

= 75 MHz × (190 ns − 10 ns − 5 ns) = 13.1

Thirteen bits are read during conversion (n), and three bits are read during acquisition (n).

For normal mode (2.0 MSPS),

f

SCK

= 50 MHz;

t

DATA

= 290 ns;

t

CNVH

= 10 ns;

t

EN

= 5 ns

Number_SCK_Edges

= 50 MHz × (290 ns – 10 ns – 5 ns) = 13.75

Thirteen bits are read during conversion (n), and three bits are read during acquisition (n).

For slow throughputs, the time restriction is dictated by the throughput required by the user; the host is free to run at any speed. Similar to reading during acquisition, data access for slow hosts must take place during the acquisition phase with additional time into the conversion.

Note that data access spanning conversion requires the CNV pin to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method.

Reading During Acquisition, Any Speed Host (Turbo or

Normal Mode)

When reading during acquisition (n), conversion results are for the previous (n − 1) conversion. Maximum throughput is achievable in normal mode (2.0 MSPS); however, in turbo mode, 2.5 MSPS throughput is not achievable.

For the maximum throughput, the only time restriction is that reading take place during the t

ACQ

(minimum) time. For slow throughputs, the time restriction is dictated by the throughput required by the user; the host is free to run at any speed. Thus, for slow hosts, data access must take place during the acquisition phase.

Rev. C | Page 18 of 28

Data Sheet

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7985 is connected to an SPI-compatible digital host. The connection diagram is

shown in Figure 26, and the corresponding timing is given in

Figure 27.

With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance.

When a conversion is initiated, it continues until completion, irrespective of the state of CNV.

AD7985

This can be useful, for example, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator.

When the conversion is complete, the AD7985 enters the acquisition phase and powers down. When CNV goes low, the

MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 16 th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance.

CONVERT

DIGITAL HOST

VIO

CNV

SDI

AD7985

SDO DATA IN t

DATA

> t

CONV t

CONV

SCK

CLK

Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)

t

CYC t

CNVH t

CONV t

DATA

SDI = 1

CNV

ACQUISITION

(n – 1)

SCK

SDO t

ACQ

CONVERSION (n – 1)

(I/O QUIET

TIME)

ACQUISITION (n)

(I/O QUIET

TIME)

CONVERSION (n) t

DIS t

QUIET

14 15 16

1

2 14 15 16 t

SCK t

EN t

EN t

HSDO t

DSDO

2 1 0 15 14 13 2 1

END DATA (n – 2) t

DIS

BEGIN DATA (n – 1) t

DIS

END DATA (n – 1)

Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)

0

(I/O QUIET

TIME)

ACQUISITION

(n + 1) t

DIS

Rev. C | Page 19 of 28

AD7985

CS MODE, 3-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7985 is connected to an SPI-compatible digital host that has an interrupt input. It is available only in normal conversion mode (TURBO is low).

The connection diagram is shown in Figure 28, and the corresponding timing is given in Figure 29.

With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion, irrespective of the state of CNV. Prior to the minimum conversion time, CNV can select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator.

Data Sheet

When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7985 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time.

After the optional 17 th

SCK falling edge, SDO returns to high impedance.

If multiple AD7985 devices are selected at the same time, the

SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation.

VIO

SDI

CNV

AD7985

SDO

CONVERT

VIO

47kΩ

DIGITAL HOST

DATA IN

IRQ

SCK TURBO

CLK

Figure 28. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)

TURBO = 0

SDI = 1 t

CYC

CNV t

CNVH

ACQUISITION

SCK

SDO t

CONV

CONVERSION

1 t

HSDO

2

D15 t

ACQ

ACQUISITION

3 t

DSDO

D14 t

SCKL

15 t

SCKH t

SCK

16

D1

17

D0

(I/O QUIET

TIME) t

DIS t

QUIET

Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)

Rev. C | Page 20 of 28

Data Sheet

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7985 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD7985

devices is shown in Figure 30, and the corresponding timing is given in Figure 31.

With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low,

SDO is driven low.) Prior to the minimum conversion time,

SDI can select other SPI devices, such as analog multi-plexers, but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator.

AD7985

When the conversion is complete, the AD7985 enters the acquisition phase and powers down. Each ADC result can be read by bringing the SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 16 th

SCK falling edge, SDO returns to high impedance and another

AD7985 can be read.

CS2

CS1

CONVERT

CNV

SDI

AD7985

SDO

CNV

SDI

AD7985

SDO

DIGITAL HOST

SCK

SCK

DATA IN

CLK

Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

t

CYC

CNV

AQUISITION t

CONV

CONVERSION t

ACQ

AQUISITION t

SSDICNV

SDI (CS1) t

HSDICNV t

QUIET

SDI (CS2)

SCK

SDO t

EN

1 t

HSDO

2

D15 D14 t

SCKL

3 14 t

DSDO t

SCKH

D13 t

SCK

15

D1

16 17 18

D0 D15 D14

Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing

30 31 32

D1 D0 t

DIS

Rev. C | Page 21 of 28

AD7985

CS MODE, 4-WIRE WITH BUSY INDICATOR

This mode is usually used when a single AD7985 is connected to an SPI-compatible digital host with an interrupt input and when it is desired to keep CNV, which samples the analog input, independent of the signal that selects the data reading. This independence is particularly important in applications where low jitter on CNV is desired. This mode is available only in normal conversion mode (TURBO is low). The connection diagram is

shown in Figure 32, and the corresponding timing is given in

Figure 33.

With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.)

Data Sheet

Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator.

When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7985 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an accept-able hold time. After the optional 17 th

SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance.

SDI

CNV

AD7985

SCK

SDO

TURBO

CS1

CONVERT

VIO

47kΩ

DIGITAL HOST

DATA IN

IRQ

CLK

Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram

TURBO = 0 t

CYC

CNV

ACQUISITION t

CONV

CONVERSION t

ACQ

ACQUISITION

(I/O QUIET

TIME) t

SSDICNV

SDI t

HSDICNV

SCK

SDO t

SCK t

EN

1 t

HSDO t

DSDO

2

D15

3 t

SCKL

15 t

SCKH

16

D14 D1

Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing

17

D0 t

DIS t

QUIET

Rev. C | Page 22 of 28

Data Sheet

CHAIN MODE WITHOUT BUSY INDICATOR

This mode can daisy-chain multiple AD7985 devices on a 3-wire serial interface. It is available only in normal conversion mode

(TURBO is low). This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register.

A connection diagram example using two AD7985 devices is

shown in Figure 34, and the corresponding timing is given in

Figure 35.

When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback.

CONVERT

CNV

SDI

AD7985

A

SCK

SDO

TURBO

CNV

SDI

AD7985

B

SCK

SDO

TURBO

DIGITAL HOST

DATA IN

CLK

Figure 34. Chain Mode Without Busy Indicator Connection Diagram

TURBO = 0

SDI

A

= 0

CNV t

CYC

ACQUISITION

SCK t

HSCKCNV

SDO

A

= SDI

B

SDO

B t

CONV

CONVERSION t

QUIET t

EN t

ACQ

ACQUISITION t

SCK t

SCKL

14 1 2 t

SSDISCK

3 15 16 t

SCKH

17 18 t

HSDISCK t

HSDO t

DSDO

D

A

15

D

B

15

D

A

14 D

A

13

D

B

14 D

B

13

D

A

1

D

B

1

D

A

0

D

B

0 D

A

15 D

A

14

Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing

30 31 32

D

A

1 D

A

0

AD7985

When the conversion is complete, the MSB is output onto SDO, and the AD7985 enters the acquisition phase and powers down.

The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the

SCK falling edge. Each ADC in the chain outputs the data MSB first, and 16 × N clocks are required to read back the N ADCs.

The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7985 devices in the chain, provided that the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time.

Rev. C | Page 23 of 28

AD7985

CHAIN MODE WITH BUSY INDICATOR

This mode can daisy-chain multiple AD7985 devices on a 3-wire serial interface while providing a busy indicator. It is available only in normal conversion mode (TURBO is low). This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7985

devices is shown in Figure 36, and the corresponding timing is given in Figure 37.

When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback.

CNV

SDI

AD7985

A

SCK

SDO

TURBO

CNV

SDI

AD7985

B

SCK

SDO

TURBO

CNV

SDI

AD7985

C

SCK

SDO

TURBO

CLK

Figure 36. Chain Mode with Busy Indicator Connection Diagram

TURBO = 0 t

CYC

CNV = SDI

A

SCK t

HSCKCNV

SDO

A

= SDI

B

SDO

B

= SDI

C t

CONV

ACQUISITION

CONVERSION t

SSCKCNV t

EN t

DSDOSDI t

DSDOSDI t

ACQ

ACQUISITION t

SCK t

SCKH

4 1 t

SSDISCK

2 3 t

HSDISCK t t

HSDO

DSDO

D

A

15 D

A

14 D

A

13

D

B

15 D

B

14 D

B

13

15 16

D

A

1 t

17

SCKL

D

A

0

18 19

D

B

1 D

B

0 D

A

15 D

A

14

31

SDO

C

32 33

D

A

1 D

A

0

34 35

D

C

15 D

C

14 D

C

13 D

C

1 D

C

0 D

B

15 D

B

14 D

B

1 D

B

0 D

A

15 D

A

14

Figure 37. Chain Mode with Busy Indicator Serial Interface Timing

CONVERT

DIGITAL HOST

DATA IN

IRQ

47 48 t

DSDOSDI

49 t

DSDOSDI t

DSDOSDI

D

A

1 D

A

0

Data Sheet

When all ADCs in the chain have completed their conversions, the

SDO pin of the ADC closest to the digital host (see the AD7985

ADC labeled C in Figure 36) is driven high. This transition on

SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7985 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs the data MSB first, and 16 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7985 devices in the chain, provided that the digital host has an acceptable hold time.

Rev. C | Page 24 of 28

Data Sheet

APPLICATIONS INFORMATION

LAYOUT

Design the printed circuit board (PCB) that houses the AD7985 so the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7985 , with the analog signals on the left side and the digital signals on the right side, eases this task.

Avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD7985 is used as a shield. Fast switching signals, such as CNV or clocks, must not run near analog signal paths. Crossover of digital and analog signals must be avoided.

At least one ground plane must be used. It can be common or split between the digital and analog sections. In the latter case, the planes must be joined underneath the AD7985 devices.

The AD7985 voltage reference inputs (REF) have a dynamic input impedance and must be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right against, the REF and

REFGND pins and connecting them with wide, low impedance traces.

AD7985

Finally, the power supplies, VDD and VIO of the AD7985 , must be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7985 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines.

EVALUATING THE

AD7985

PERFORMANCE

Other recommended layouts for the AD7985 are outlined in the documentation for the AD7985 evaluation board ( EVAL-

AD7985FMCZ ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-

SDP-CH1Z board.

Rev. C | Page 25 of 28

AD7985

BVDD AVDD

REF

REF REF

GND GND GND

1

2

3

4

5

PADDLE

GND GND

GND GND

6

VIO

Figure 38. Example Layout of the AD7985 (Top Layer)

5V

EXTERNAL

REFERENCE

(ADR435 OR ADR445)

REF

REF REF

C

REF

C

BVDD

BVDD AVDD C

AVDD

GND

GND GND

GND GND

C

DVDD

DVDD

GND GND GND

VIO

C

VIO

VIO

Figure 39. Example Layout of the AD7985 (Bottom Layer)

Rev. C | Page 26 of 28

DVDD

Data Sheet

Data Sheet

OUTLINE DIMENSIONS

AD7985

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

TOP VIEW

0.50

BSC

15

16

0.30

0.25

0.20

EXPOSED

PAD

20

1

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

11

10

BOTTOM VIEW

6

5

0.50

0.40

0.30

0.25 MIN

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model 1, 2, 3

AD7985BCPZ

AD7985BCPZ-RL7

Temperature

Range

−40°C to +85°C

−40°C to +85°C

Package Description

20-Lead Lead Frame Chip Scale Package [LFCSP], Tray

20-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel

Package

Option

Ordering

Quantity

CP-20-10 490

CP-20-10 1,500

EVAL-AD7985FMCZ Evaluation Board

EVAL-SDP-CH1Z Controller Board

1

2

3

Z = RoHS Compliant Part.

The EVAL-AD7985FMCZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CH1Z for evaluation/demonstration purposes.

The EVAL-SDP-CH1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the FMC designator.

Rev. C | Page 27 of 28

AD7985

NOTES

Data Sheet

©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D07947-0-3/16(C)

Rev. C | Page 28 of 28

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