EVAL-AD7625/AD7626EDZ

EVAL-AD7625/AD7626EDZ
®










4
SNRgain(dB) 10 log(OversampleRatio)
A
B
C
8
+2.5V
+2.5V
+5V
+7V
+12VA
GND
GND
-12VA
-5VA
VIO
VDD2
VDD1
1
1
1
VCCREF
VDRV-
AVDD
GND
GND
C16
10UF
VIO
VIO
BLU
GND
C10
10UF
VDD2
BLU
DVDD
GND
C14
10UF
7
C13
10UF
4VREF+
BLU
GND
C12
10UF
VDRVBLU
VDD1
BLU
1
1
-5VA
1
-5VA
-5VA
WHT
1
GND
TP16
BLK
GND
+5VA
RED
6
+5VA
1
+5VA
+12VA
RED
+12VA
1
+12VA
VDIG
-12VA
-12VA
WHT
-12VA
VDIG
1
VDIG
RED
VDIG
1
R3
P19
P20
P21
P22
P7
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
P23
P24
P25
+5V
120K
EN
SENSE
5
IN
OUT
6
IN2
OUT2
ADJ
GND1 PAD
2 PAD
ADP1708ARDZ-R7
U9
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8
ADJ
GND1 PAD
2 PAD
LDO ADJUSTED TO 2.5V
130K
R2
1
7
3
4
8
ADP1708ARDZ-R7
U8
LDO ADJUSTED TO 1.2V
60.4K
R7
FPGA SUPPLIES
5
130K
R6
ADP1708ARDZ-R7
U7
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8
ADJ
GND1 PAD
2 PAD
GND
GND
GND
1
A
2
COM
3
B
0
0
R13
R10
0
1 R8 2
VIO_FPGA
REGULATES FPGA VIO SUPPLIES TO 2.5V
60.4K
GND
C17
C18
C11
10UF
R4
R1
60.4K
1
2
1
2
4.7UF
4.7UF
4.7UF
4.7UF
VPLLA2
4
3PIN_SOLDER_JUMPER
JP3
VPLLA2
VFPGA
VPLLA1
VPLLA1
0
R70
0
R69
3
EN_2.5V
AN A LOG
DEV CES
+5VA
10K
R12
10K
R11
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OF ANALOG DEVICES.
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
VIO_FPGA
EN_7V_N
+12VA
VIO_FPGA
EN_5V_N
+12VA
REV
2
DESCRIPTION
GND
A3
ADP3334ARZ
7
FB
3
5
IN
OUT
4
6
IN1 OUT1
SD_N GND
2
1
A2
ADP3334ARZ
7
FB
3
5
IN
OUT
4
6
IN1 OUT1
SD_N GND
2
1
130K
R21
GND
2
<PTD_ENGINEER>
PTD ENGINEER
<DESIGN_VIEW>
DESIGN VIEW
<DRAWING_TITLE_HEADER>
AD7626/5/7 EVAL BD Z
<PRODUCT_1>
ADP1708ARDZ-R7
U11
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8
ADJ
GND1 PAD
2 PAD
R18
300K
R16
210K
D
SIZE
+7V
+5V
-
SCALE
1
1
REV
OF 6
B
APPROVED
SHEET 1
DATE
DRAWING NO.
02-020616
SCHEMATIC
GND
+2.5V
0
R32
0
R30
REVISIONS
ANALOG SUPPLIES
2.2UF
+7V
C27
R15
POWER SUPPLIES
C9
P5
P10
1
2
C20
C21
C4
VDRV+
BLU
C28
60.4K
1000PF
R17
3
C23
1
4.7UF
C5
4
C42
5
4.7UF
64.9K
1000PF
R19
VDRV+
6
C19
60.4K
+12VA
P1
4.7UF
2.2UF
R33
2.2UF
7
10K
2.2UF
D
8
C25
C43
4.7UF
A
B
C
D
A
B
8
VCCREF
0
R22
10UF
C36
1 2
7
+5V
GND
0.1UF
C2
C
A1
8
TP1
7
NC2
6
VOUT
5
TRIM
1
GND
V+ VO
V3
2
ADR280ARTZ
A4
ADR435BRZ
1
TP
2
VIN
3
NC1
4
GND
0.1UF
7
C37
C3
D
8
2.2UF
0.1UF
0
R23
6
6
TBD0805
P27
1
VREF
YEL
1K
R26
GND
GND
C38
10UF
TBD0805
1 R27 2
3
2
A5
6
C40
0.1UF
VCCREF
5
GND
4 AD8031BRZ
V-
7
V+
1K
R28
TBD0805
C39
1 2
NOBUF
BUF
REF
BLU
1
REFIN
BLU
REFIN
REF
1
4
REFIN
1
2
3
P13
REF
EXTERNAL REFERENCE
4
REF/2_7626
GND
C41
10UF
3
3
R73
5
1
2
3
P6
1
2
3
2
A6
4
V-
7
V+
JP4
C99
0.1UF
AN A LOG
DEV CES
GND
AD8031BRZ
6
VDRV+
1
A
2
COM
3
B
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OF ANALOG DEVICES.
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
1M
R24
C35
2
2
<PTD_ENGINEER>
PTD ENGINEER
<DESIGN_VIEW>
DESIGN VIEW
REVISIONS
D
SIZE
-
SCALE
1
1
REV
OF 6
B
APPROVED
SHEET 2
DATE
DRAWING NO.
02-020616
SCHEMATIC
DESCRIPTION
<DRAWING_TITLE_HEADER>
AD7626/5/7 EVAL BD Z
<PRODUCT_1>
VCM
REV
A
B
C
D
A
B
C
1 AIN+
8
GND
2 3 4 5
J2
GND
VCM
6
VCM
BUF+
1
VCM
BLU
R29
GND
1 R40 2
R43
0
1 R42 2
TBD0805
1 R41 2
TBD0805
GND
590
C47
0.1UF
GND
C46
0.1UF
590
R39
0
R38
TBD0805
R37
TBD0805
GND
R36
TBD0805
7
GND
INPAS-
C48
TBD0805
GND
49.9
1 R46 2
GND
C49
TBD0805
49.9
1 R47 2
1
0.1UF
C98
0.1UF
C55
OPAS+
VCM
OPAS-
0.1UF
C54
GND
VDRV0.1UF
C57
GND
U14
7
2 +VS 8
6
DISABLE*
VOUT
1
3 FEEDBACK
-VS
PAD 5
4
PAD
ADA4899-1YRDZ
VDRV+
6
2
0
R5
GND
P3
GND
6
0
R9
ADA4899-1YRDZ
6
1
U13
0.1UF
T1-1T-KK81+
T1
4
3
VDRV-
7
2 +VS 8
DISABLE*
VOUT
3 FEEDBACK
-VS
PAD 5
4
PAD
VDRV+
C52
P8
BUF+
P9
OPAS-
OPAS+
1
A
2
COM
3
B
4
C
JP2
1
A
2
COM
3
B
4
C
JP1
DIFF+
R20
DIFF_IN+
TBD0805
TBD0805
R62
R14
DIFF_INTBD0805
DIFF-
4
5
C8
TBD0805
GND
C7
TBD0805
R35
499
R48
499
JP5
499
R51
VDRV-
GND
1 VDRV+
A
2
COM
3
B
GND
+VS
-VS
2
+IN
3
-IN
12
PD_N
VDRV+
499
R50
ADC BUFFERS
5
C15
4
1
0.1UF
PAD
GND
GND
TP7
BLK
VCM
0.1UF
1
TP8
BLK
ADA4938-1ACPZ-R7
U5
VOCM
1
FB-OUT
11
-OUT
10
+OUT
4
FB+OUT
0.1UF
C24
7
** NO GND OR POWER UNDER THE NODES MARKED IN RED. **
DIFF_IN+
DIFF_IN-
INPAS-
JP9
1 AIN-
2 3 4 5
J1
JP6
1
A
2
COM
3
B
4
C
D
R44
R45
C50
1 2
C51
1 2
R34
R31
TBD0805
TBD0805
TBD0805
TBD0805
C22
5
6
7
8
16
15
14
13
9
PAD
TBD0805
R49
TBD0805
R57
0
R53
0
R52
DIFF-
DIFF+
3
3
1
SIGBLU
SIG+
BLU
AN A LOG
DEV CES
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OF ANALOG DEVICES.
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
33
R55
33
R54
1
2
<PTD_ENGINEER>
PTD ENGINEER
<DESIGN_VIEW>
DESIGN VIEW
REVISIONS
IN+
D
SIZE
-
SCALE
1
1
REV
OF 6
B
APPROVED
SHEET 3
DATE
DRAWING NO.
02-020616
SCHEMATIC
GND
IN-
DESCRIPTION
<DRAWING_TITLE_HEADER>
AD7626/5/7 EVAL BD Z
<PRODUCT_1>
C1
TBD0805
REV
2
C53
C56
1
A
2
COM
3
B
4
C
8
TBD0805
TBD0805
10K
10K
R156
R157
56PF
56PF
1
2
1
2
1
2
A
B
C
D
A
B
8
7
REFIN
EN0
EN1
VDD1
VDD2
6
6
GND
C66
CNV+
CNV-
5
C34
GND
C71
5
GND
1
2
3
4
5
6
7
8
GND
GND
DNI
TP3
1 5015
DNI
.1UF
C58
TP2
1 5015
VIO
100
R82
VDD1
VDD2
CAP
REFIN
EN0
EN1
VDD2
CNV-
PAD
REF
.1UF
1UF
32
31
30
29
28
10UF
C26
GND
GND
IN+
INREF/2
VDD1
VDD1
VDD2
CLK+
100
R83
24
23
22
21
20
19
18
17
10UF
U3
1UF
C73
C29
4
GND
4
AD7626 SITE
.1UF
C44
.1UF
27
26
25
REF
GND
REF
REF
CAP2
GND
CAP2
CAP2
CNV+
DD+
VIO
IO_GND
DCODCO+
CLK-
9
10
11
12
13
14
15
16
C
7
IN-
IN+
.1UF
GND
REF/2_7626
C74
C75
D
8
GND
.1UF
.1UF
C32
10UF
C30
.1UF
C97
R59
1
DATA+
DATA-
DCO+
DCO-
SCLK+
SCLK-
TBD0603
E2
2
3
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OF ANALOG DEVICES.
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
AN A LOG
DEV CES
VDD2
VDD1
TP1
1 0319-0-15-15-18-27-04-0
3
2
2
<PTD_ENGINEER>
PTD ENGINEER
<DESIGN_VIEW>
DESIGN VIEW
REVISIONS
D
-
SCALE
02-020616
SIZE
1
1
REV
OF 6
B
APPROVED
SHEET 4
DATE
DRAWING NO.
SCHEMATIC
DESCRIPTION
<DRAWING_TITLE_HEADER>
AD7626/5/7 EVAL BD Z
<PRODUCT_1>
REV
A
B
C
D
A
B
C
D
8
8
7
7
6
6
4
GND
P4
ERNI533402
-12VA
-5VA
+5VA
RESET
BD<12>
AD<3>
AD<1>
VDIG
BRD_N
AD<7>
AD<5>
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
5
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
P4
ERNI533402
-5VA
+5VA
BD<11>
BD<13>
BD<8>
BD<9>
BD<10>
BD<2>
BD<3>
BD<4>
VDIG
BD<5>
BD<6>
BD<7>
CONTROL
BD<0>
BD<1>
4
GND
P4
ERNI533402
+12VA
-5VA
+5VA
BBUSY
BD<14>
BD<15>
AD<4>
AD<2>
AD<0>
AD<6>
VDIG
BWR_N
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
96-PIN EDGE CONNECTOR
5
3
3
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OF ANALOG DEVICES.
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
AN A LOG
DEV CES
2
<PTD_ENGINEER>
PTD ENGINEER
<DESIGN_VIEW>
DESIGN VIEW
REVISIONS
D
SIZE
-
SCALE
1
1
OF 6
REV
B
APPROVED
SHEET 5
DATE
DRAWING NO.
02-020616
SCHEMATIC
DESCRIPTION
<DRAWING_TITLE_HEADER>
AD7626/5/7 EVAL BD Z
<PRODUCT_1>
REV
2
A
B
C
D
A
B
C
PS_DATA
GND
C
A
PS_DCLK
VIO_FPGA
GND
R76
8
VIO_FPGA
GND
N_CSO
C6
PS_DATA
GND
R63
Y1
GND
OUT 3
GND
2
100MHZ
MCLK
SYNC_OUT
GND
R86
MSEL2
GND
R89
0
R88
VIO_FPGA
EPCS4SI8N
PS_DATA
7
GND
GNDA1
M5
K8
L7
L8
M6
M7
M8
N3
N5
N6
N8
P3
P6
P8
4
3
2
10K
R90
SYNC_OUT
EP3C5F256C7N
L3
L4
K5
R1
L1
L2
N1
N2
P1
P2
U1
ASDO
N_CSO
CONTROL
BRD_N
VIO_FPGA
C64
.1UF
GND
6
DIFFIO_B2P_DQ5B
PLL1_CLKOUTP
DIFFIO_B6P_DQ5B
DIFFIO_B7P_DQ5B
DIFFIO_B8P_DQ5B
DIFFIO_B11P
DQS1B_CQ1B_DPCLK2
DIFFIO_B2N
PLL1_CLKOUTN
DIFFIO_B6N
DIFFIO_B7N
DIFFIO_B8N_DQS5B_CQ5B
DIFFIO_B11N
GND
C62
.1UF
VFPGA
VIO_FPGA
BANK3
SCLKSCLK+
4
DQ5T
DQS5T_CQ5T
VREFB8N0
DIFFIO_T7N_DQS3T_CQ3T
DIFFIO_T7P_DQ5T
DIFFIO_T8N
DIFFIO_T8P
DIFFIO_T9N_DQ5T
DIFFIO_T9P_DATA4_DQ5T
DIFFIO_T10N_DATA2_DQ5T
DIFFIO_T10P_DATA3
DIFFIO_T11N
DIFFIO_T11P
C67
.1UF
DCO-
DCO+
C69
.1UF
GND
EP3C5F256C7N
R3
R4
R5
R6
R7
R8
T2
T3
T4
T5
T6
T7
T8
U1
VFPGA
7
6
5
3
5
6
EP3C5F256C7N
D8
C8
C6
A6
B6
F6
F7
A7
B7
E8
F8
A8
B8
U1
BWR_N
VIO_FPGA
15
8
14
12
2
1
7
4
GND
C72
.1UF
5
DATADATA+
C77
.1UF
100
R65
C95
.1UF
T9
R9
L9
K9
N9
M9
T10
R10
T11
R11
R14
N11
M10
C96
.1UF
EP3C5F256C7N
U1
VIO_FPGA
GND
PLL2_CLKOUTN
PLL2_CLKOUTP
DQS4T_CQ5T
DIFFIO_T12N
DIFFIO_T12P
DIFFIO_T13N_DQ5T
DIFFIO_T13P_DM5T0_BWS5T0
DIFFIO_T14N_DQ5T
DIFFIO_T14P_DQ5T
DIFFIO_T15N
DIFFIO_T15P
DIFFIO_T16N
DIFFIO_T16P_DQS2T_CQ3T
4
DIFFIO_B12N
DIFFIO_B12P
DIFFIO_B13N
DIFFIO_B13P
DIFFIO_B14N_DQ5B
DIFFIO_B14P
DIFFIO_B15N_DQS4B_CQ5B
DIFFIO_B15P_DQ5B
DIFFIO_B16N
DIFFIO_B16P_DQ5B
IO_5
RDN2
RUP2
A14
B14
E9
A9
B9
C9
D9
A10
B10
F11
A15
F10
F9
FPGA -- CYCLONE III
DATA5_DQ5T
BANK8
DATA6_DQ5T
DIFFIO_T1N
DIFFIO_T1P
DIFFIO_T2N
DIFFIO_T2P_DQS1T_CQ1T_DPCLK7
DIFFIO_T3N
DIFFIO_T3P
DIFFIO_T4N_DM5T1_BWS5T1
DIFFIO_T4P
DIFFIO_T5N
DIFFIO_T5P_DQ5T
DIFFIO_T6N_DATA7_DQ5T
PS_DCLK
E7
E6
C3
D3
A3
B3
D5
D6
A4
B4
A2
B5
A5
EP3C5F256C7N
H1
J4
C1
C2
D1
D2
F1
F2
G1
G2
F3
F4
U1
0
1
DIFFIO_B5N
DQ5B_1
DIFFIO_B9P_DQ5B
DQ5B_2
DIFFIO_B5P_DQS3B_CQ3B
DIFFIO_B9N_DM5B0_BWS5B0
DIFFIO_B1P
DIFFIO_B4P_DQ5B
DIFFIO_B4N_DQ5B
DIFFIO_B10P_DQ5B
DIFFIO_B1N_DM5B1_BWS5B1
VREFB3N0
DIFFIO_B10N_DQ5B
VREFB2N0
RDN1_DQ1L
RUP1_DQ1L
DQS3L_CQ3L
DIFFIO_L8N_DQ1L
DIFFIO_L8P_DQS1L_CQ1L_DPCLK1
DIFFIO_L9N_DQ1L
DIFFIO_L9P_DQ1L
DIFFIO_L10N_DM1L_BWS1L
DIFFIO_L10P_DQ1L
N4
VCCD_PLL1
VFPGA
DCLK
TDO
DIFFIO_L1N_DATA1_ASDO
DIFFIO_L1P
DIFFIO_L2N
DIFFIO_L2P_FLASH_NCE_NCSO
DIFFIO_L3N
DIFFIO_L3P
DIFFIO_L4N
DIFFIO_L4P_DQS0L_CQ1L_DPCLK0
VREFB1N0
NSTATUS
BANK1
MSEL1
BANK2
MCLK
1 YEL
MCLK
L5
VCCA1
IO_0
IO_1
IO_2
IO_3
DATA0
DQS2L_CQ3L
CLK1_DIFFCLK_0N
CLK0_DIFFCLK_0P
TCK
TDI
NCONFIG
NCE
TMS
M2
CLK2_DIFFCLK_1P
M1
CLK3_DIFFCLK_1N
J6
IO_4
J1
DIFFIO_L5N_DQ1L
J2
DIFFIO_L5P_DQ1L
L6
DIFFIO_L6N
K6
DIFFIO_L6P
K1
DIFFIO_L7N_DQ1L
K2
DIFFIO_L7P
49.9
4 V+
1 EN
D4
E5
F5
G5
H2
B1
GND
R85
0
GND
E1
E2
H3
H4
H5
J3
J5
DCLK
ASDI
GND
4
2
U4
R60
0
GND
MSEL0
ASDO
DATA
3 7
VCC
VIO_FPGA
5
PS_DCLK
8
nCS
VIO_FPGA
6
R61
ASDO
GND
R78
10K
VPLLA1
PS_CONFIG_N
MCLK
GND
C6 1
PS_STATUS_N
GND
2 3 4 5
J3
1
10K
10K
R75
GND
VIO_FPGA
A
CR 1
10PF
C
3M2510-5002UB
C3 1
CR2
10PF
C
A
D
C5 9
CR3
C
CR4
A
1
C81
N_CSO
.1UF
C83
R77
10K
.1UF
C85
PS_DCLK
GND
PS_CDONE_N
VIO_FPGA
PS_CONFIG_N
PS_STATUS_N
PS_DATA
N_CSO
ASDO
GND
.1UF
C87
R64
1
2
3
4
5
6
7
8
9
10
.1UF
C89
VIO_FPGA
.1UF
C91
VCCIO1
VIO_FPGA
.1UF
C84
P2
VCCIO2
10PF
5
.1UF
C92
VCCIO3
3
R93
10K
M15
M16
J11
K11
K12
L12
M12
N13
J13
L13
P15
N14
L14
E15
E16
H13
H12
G12
F13
G11
H14
B16
F14
13
11
10
9
0
EP3C5F256C7N
E10
E11
C11
A11
B11
A12
B12
A13
B13
D11
D12
C14
D14
U1
BBUSY
RESET
VFPGA
AD<7..0>
BD<15..0>
REV
LED1
2
60.4
R95
R94
3
AN A LOG
DEV CES
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OF ANALOG DEVICES.
EP3C5F256C7N
J14
J12
J16
J15
K16
K15
L16
L15
N16
N15
P16
R16
U1
2
<PTD_ENGINEER>
PTD ENGINEER
<DESIGN_VIEW>
DESIGN VIEW
<DRAWING_TITLE_HEADER>
AD7626/5/7 EVAL BD Z
<PRODUCT_1>
DIFFIO_R6N_DQ1R
DIFFIO_R6P
DIFFIO_R7N_DEV_OE
DIFFIO_R7P_DEV_CLRN
DIFFIO_R8N_DQ1R
DIFFIO_R8P_DQS1R_CQ1R_DPCLK4
DIFFIO_R9N
DIFFIO_R9P
DIFFIO_R10N_DQ1R
DIFFIO_R10P_DQ1R
DIFFIO_R11N_DQS3R_CQ3R
DIFFIO_R11P_DQ1R
BANK5
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
CLK6_DIFFCLK_3P
CLK7_DIFFCLK_3N
IO_6
IO_7
IO_8
IO_9
IO_10
IO_11
DQ1R_1
DQ1R_2
RDN3
RUP3
VREFB5N0
GND
A
C
GND
R96
10K
R99
10K
R98
10K
10K
10K
R100
1
DATE
D
SIZE
-
SCALE
DRAWING NO.
02-020616
GND
GND
1
SHEET 6
REV
OF 6
B
APPROVED
VIO_FPGA
TP24
TP25
TP26
1 BLK 1 BLK 1 BLK
SCHEMATIC
CNVCNV+
EN0
EN1
CR5
BRD
1 YEL
BBUSY
1 YEL
BWR
1 YEL
A
C
CR6
CONTROL
RESET
BRD_N
BBUSY
BWR_N
1 R25 2
REVISIONS
DESCRIPTION
ADCOK
U1
F12
D13
60.4
VCCA2
VCCD_PLL2
DIFFIO_R1N_DQS2R_CQ3R C16
CLK4_DIFFCLK_2P
DIFFIO_R1P C15
CLK5_DIFFCLK_2N
BANK6
EN_7V_N
DIFFIO_R2N D16
MSEL0
DIFFIO_R2P D15
MSEL1
DIFFIO_R3N_NCEO F16
MSEL2
DIFFIO_R3P_CLKUSR F15
IO_12
G16
DIFFIO_R4N_INIT_DONE
IO_13
DIFFIO_R4P_CRC_ERROR G15
CONF_DONE
EN_2.5V
DIFFIO_R5N H16
DQS0R_CQ1R_DPCLK5
H15
EN_5V_N
DIFFIO_R5P
VREFB6N0
GNDA2
E12
EP3C5F256C7N
GND
EP3C5F256C7N
P9
P11
T12
R12
L10
K10
T13
R13
T15
T14
L11
P14
N12
M11
U1
PS_CDONE_N
MSEL0
MSEL1
MSEL2
VPLLA2
RDN4
RUP4
VREFB7N0
DIFFIO_T17N_DQ5T
DIFFIO_T17P_DQ5T
DIFFIO_T18N_DQ5T
DIFFIO_T18P_DQ5T
DIFFIO_T19N
DIFFIO_T19P_DQ5T
DIFFIO_T20N
DIFFIO_T20P_DQS0T_CQ1T_DPCLK6
DIFFIO_T21N
DIFFIO_T21P_DQ5T
BANK7
DQS2B_CQ3B
VREFB4N0
DIFFIO_B17N_DQ5B
DIFFIO_B17P_DQ5B
DIFFIO_B18N
DIFFIO_B18P
DIFFIO_B19N_DQ5B
DIFFIO_B19P
DIFFIO_B20N_DQS0B_CQ1B_DPCLK3
DIFFIO_B20P_DQ5B
DIFFIO_B21N
DIFFIO_B21P
DIFFIO_B22N
DIFFIO_B22P
BANK4
VIO_FPGA
.1UF
6
.1UF
C79
VCCIO4
C93
10PF
1000P F
.1UF
C80
VCCIO5
C94
7
VCCINT
100
0.1U F
C60
.1UF
VCCIO6
.1UF
C90
.1UF
C76
0.1UF
8
.1UF
C78
.1UF
C82
VCCIO7
.1UF
C86
.1UF
C68
G6
G7
G8
G9
G1 0
H6
H1 1
K7
E3
G3
K3
M3
P4
P7
T1
P1 0
P1 3
T16
K14
M14
E14
G14
A16
C1 0
C13
A1
C4
C7
C63
.1UF
C88
.1UF
C70
VCCIO8
B2
B15
C5
C12
D7
D10
E4
E13
G4
G13
H7
H8
H9
H10
J7
J8
J9
J10
K4
K13
M4
M13
N7
N10
P5
P12
R2
R15
. 1UF
C65
C33
C45
.1UF
1000PF
A
B
C
D
FNYQUIST 
SampleFrequency
2 ( N 1)
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