Silicon Laboratories | SI5366 | Si5366

Si5366
P R E L I M I N A R Y D A TA S H E E T
P RECISION C L O C K M ULTIPLIER / J I T T E R A TTENUATOR
Description
„
The Si5366 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5366 accepts four clock inputs ranging
from 8 kHz to 707 MHz and generates five frequencymultiplied clock outputs ranging from 8 kHz to
1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of
popular SONET, Ethernet, and Fibre Channel rates.
The Si5366 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the
application level. Operating from a single 1.8 or 2.5 V
supply, the Si5366 is ideal for providing clock
multiplication and jitter attenuation in high performance
timing applications.
„
Applications
„
SONET/SDH OC-48/STM-16 and OC-192/STM-64
line cards
„ GbE/10GbE, 1/2/4/8/10GFC line cards
„ ITU G.709 line cards
„ Optical modules
„
Test and measurement
Synchronous Ethernet
Features
„
„
„
„
„
„
„
„
„
„
„
„
„
Selectable output frequencies ranging from 8 kHz to
1050 MHz
Ultra-low jitter clock outputs w/jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Four clock inputs w/manual or automatically
controlled hitless switching
Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
SONET frame sync switching and regeneration
Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
LOL, LOS, FOS alarm outputs
Pin-controlled output phase adjust
Pin-programmable settings
On-chip voltage regulator for 1.8 ±5% or
2.5 V ±10% operation
Small size: 14 x 14 mm 100-pin TQFP
Pb-free, RoHS compliant
Xtal or Refclock
CKIN1
CKIN2
DSPLL
CKIN3
®
÷ NF1
CKOUT1
÷ NF2
CKOUT2
÷ NF3
CKOUT3
N1_HS
CKIN4
Input Clock Configuration
Divider Select
Manual/Auto Switch
Clock Select
÷ NF4
CKOUT4
÷ NF5
CKOUT5 (FS_OUT)
Resonator/Rate Select
LOL/LOS/FOS Alarms
Control
Output Clock2
Frequency Select
Bandwidth Select
Input Clock3
VDD (1.8 or 2.5 V)
Skew Control
Input Clock4
GND
FSYNC Align
Preliminary Rev. 0.3 2/08
Copyright © 2008 by Silicon Laboratories
Si5366
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5366
Table 1. Performance Specifications
(VDD = 1.8 ±5% or 2.5 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Supply Current
Symbol
TA
VDD
Test Condition
IDD
fOUT = 622.08 MHz
All CKOUTs enabled
LVPECL format output
Only CKOUT1 enabled
fOUT = 19.44 MHz
All CKOUTs enabled
CMOS format output
Only CKOUT1 enabled
Tristate/Sleep Mode
Input frequency and clock multiplication ratio pin-selectable
from table of values using
FRQSEL and FRQTBL settings. Consult Silicon Laboratories configuration software
DSPLLsim or Any-Rate Precision Clock Family Reference
Manual at www.silabs.com/timing (click on Documentation) for
table selections.
Input Clock Frequency
CKF
(CKIN1, CKIN2, CKIN3,
CKIN4)
Input Clock Frequency
CKF
(CKIN3, CKIN4 used as
FSYNC inputs)
CKOF
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4,
CKOUT5 used as fifth
high-speed output)
CKOUT5 used as frame
CKOF
sync output (FS_OUT)
3-Level Input Pins
Input Mid Current
IIMM
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing CKNDPP
Common Mode Voltage
CKNVCM
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
CKNTRF
CKNDC
See Note 2.
1.8 V ±5%
2.5 V ±10%
20–80%
Whichever is smaller
Min
–40
2.25
1.71
—
Typ
25
2.5
1.8
394
Max
85
2.75
1.89
435
Unit
ºC
V
V
mA
—
—
253
278
284
321
mA
mA
—
—
0.008
229
165
—
261
TBD
707.35
mA
mA
MHz
0.008
—
—
MHz
0.008
—
1049.76
MHz
0.008
—
—
MHz
–2
—
2
µA
0.25
0.9
1.0
—
—
—
—
—
—
1.9
1.4
1.7
11
60
—
VPP
V
V
ns
%
ns
—
—
—
VDD – 1.25
1.9
0.93
V
V
V
230
350
ps
40
2
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT)
Common Mode
VOCM
LVPECL
VDD – 1.42
100 Ω load
Differential Output Swing
VOD
1.1
line-to-line
Single Ended Output
VSE
0.5
Swing
Rise/Fall Time
CKOTRF
20–80%
—
Notes:
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing (click on
Documentation).
2. This is the amount of leakage that the 3 level input can tolerate from an external driver. See the Family Reference
Manual. In most designs, an external resistor voltage divider is recommended.
2
Preliminary Rev. 0.3
Si5366
Table 1. Performance Specifications (Continued)
(VDD = 1.8 ±5% or 2.5 V ±10%, TA = –40 to 85 ºC)
Parameter
Duty Cycle
PLL Performance
Jitter Generation
Symbol
CKODC
Test Condition
Min
45
Typ
—
Max
55
Unit
%
JGEN
fIN = fOUT = 622.08 MHz,
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
—
0.3
TBD
ps rms
Jitter Transfer
Phase Noise
JPK
CKOPN
—
—
—
0.3
0.05
TBD
TBD
0.1
TBD
ps rms
dB
dBc/Hz
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc
—
40
—
ºC/W
Subharmonic Noise
Spurious Noise
SPSUBH
SPSPUR
Package
Thermal Resistance
Junction to Ambient
θJA
fIN = fOUT = 622.08 MHz
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
Phase Noise @ 100 kHz Offset
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
Still Air
Notes:
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing (click on
Documentation).
2. This is the amount of leakage that the 3 level input can tolerate from an external driver. See the Family Reference
Manual. In most designs, an external resistor voltage divider is recommended.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 3.6
V
LVCMOS Input Voltage
VDIG
–0.3 to (VDD + 0.3)
V
Operating Junction Temperature
TJCT
–55 to 150
ºC
Storage Temperature Range
TSTG
–55 to 150
ºC
2
kV
ESD MM Tolerance; All pins except CKIN+/CKIN–
200
V
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
700
V
ESD MM Tolerance; CKIN+/CKIN–
150
V
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except CKIN+/CKIN–
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.3
3
Si5366
Phase Noise (dBc/Hz)
622 MHz In, 622 MHz Out BW=877 kHz
-50
-70
-90
-110
-130
-150
-170
1000
10000
100000
1000000
10000000 100000000
Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
4
Jitter Bandwidth
RMS Jitter (fs)
OC-48, 12 kHz to 20 MHz
374
OC-192, 20 kHz to 80 MHz
388
OC-192, 4 MHz to 80 MHz
181
OC-192, 50 kHz to 80 MHz
377
Broadband, 800 Hz to 80 MHz
420
Preliminary Rev. 0.3
Si5366
C10
System
Power
Supply
Ferrite
Bead
Crystal
Option 2:
Ext.
Refclk–
Ext.
Refclk+
C1–9
VDD = 3.3 V
0.1 µF
0.1 µF
CKIN1+
XA
XB
XA
XB
130 Ω
GND
0.1 µF
VDD
130 Ω
Option 1:
1 µF
CKIN1–
82 Ω
82 Ω
CKOUT1+
0.1 µF
+
100 Ω
CKOUT1–
Input
Clock
Sources1
0.1 µF
–
VDD = 3.3 V
130 Ω
130 Ω
CKIN4+
CKIN4–
82 Ω
CKOUT4+
CKOUT4–
VDD
15 kΩ
CKOUT5/FS_OUT+
RATE2
VDD
15 kΩ
VDD
15 kΩ
Frequency Table Select
Bandwidth Select
0.1 µF
–
+
0.1 µF
–
15 kΩ
VDD
15 kΩ
CKSEL[1:0]3
Si5366
FOS_CTL2
15 kΩ
VDD
15 kΩ
Frequency Select
0.1 µF
AUTOSEL2
Input Clock Select
Frequency Offset Control
CKOUT5/FS_OUT–
CK_CONF
VDD
15 kΩ
Manual/Automatic Clock
Selection (L)
15 kΩ
+
100 Ω
15 kΩ
Input Clock Configuration
Control
Clock
Outputs
100 Ω
82 Ω
Crystal/Ref Clk Rate
0.1 µF
FRQTBL2
FRQSEL[3:0]2
15 kΩ
BWSEL[1:0]2
15 kΩ
Skew Increment
INC
Skew Decrement
VDD
15 kΩ
Signal Format Select
VDD
15 kΩ
CKOUT3 and CKOUT4
Divider Control
15 kΩ
Clock Output 2 Disable/
Bypass Mode Control
Clock Outputs 3 and 4
Disable
FS_OUT Disable
SFOUT[1:0]2
15 kΩ
VDD
15 kΩ
DIV34_[1:0]2
DBL2_BY2
15 kΩ
VDD
15 kΩ
DEC
DBL34
DBL_FS2
15 kΩ
FSYNC Inputs to Clock
Selection Enable
FS_SW
FSYNC Realignment
Control
FS_ALIGN
Reset
RST
ALRMOUT
Alarm Output Indicator
CKnB
CKINn Invalid Indicator
(n = 1 to 3)
LOL
PLL Loss of Lock
Indicator
Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. Assumes manual input clock selection.
Figure 2. Si5366 Typical Application Circuit
Preliminary Rev. 0.3
5
Si5366
1. Functional Description
The Si5366 is a jitter-attenuating precision clock
multiplier for high-speed communication systems,
including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5366 accepts four clock inputs ranging
from 8 kHz to 707 MHz and generates five frequencymultiplied clock outputs ranging from 8 kHz to
1050 MHz. By default the four clock inputs are at the
same frequency and the five clock outputs are at the
same frequency. Two of the output clocks can be
divided down further to generate an integer sub-multiple
frequency. Optionally, the fifth clock output can be
configured as
a 8 kHz SONET/SDH frame
synchronization output that is phase aligned with one of
the high-speed output clocks. The input clock frequency
and clock multiplication ratio are selectable from a table
of popular SONET, Ethernet, and Fibre Channel rates.
In addition to providing clock multiplication in SONET
and datacom applications, the Si5366 supports SONETto-datacom frequency translations. Silicon Laboratories
offers a PC-based software utility, DSPLLsim, that can
be used to look up valid Si5366 frequency translations.
This
utility
can
be
downloaded
from
http://www.silabs.com/timing (click on Documentation).
The Si5366 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
Si5366 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 60 Hz to
8.4 kHz. The DSPLLsim software utility can be used to
calculate valid loop bandwidth settings for a given input
clock frequency/clock multiplication ratio.
The Si5366 supports hitless switching between input
clocks in compliance with GR-253-CORE and GR-1244CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (<200 ps typ). Manual and automatic revertive
and non-revertive input clock switching options are
available via the AUTOSEL input pin. The Si5366
monitors the four input clocks for loss-of-signal and
provides a LOS alarm when it detects missing pulses on
any of the four input clocks. The device monitors the
lock status of the PLL. The lock detect algorithm works
by continuously monitoring the phase of the input clock
in relation to the phase of the feedback clock. If a
potential phase cycle slip is detected, the LOL output is
set high. The Si5366 monitors the frequency of CKIN1,
CKIN3, and CKIN4 with respect to a reference
frequency applied to CKIN2, and generates a frequency
offset alarm (FOS) if the threshold is exceeded. This
FOS feature is available for SONET applications in
which both the monitored frequency on CKIN1, CKIN3,
and CKIN4 and the reference frequency are integer
multiples of 19.44 MHz. Both Stratum 3/3E and SONET
6
Minimum Clock (SMC) FOS thresholds are supported.
The Si5366 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL is locked to an input frequency
that existed a fixed amount of time before the error
event occurred, eliminating the effects of phase and
frequency transients that may occur immediately
preceding digital hold.
The Si5366 has five differential clock outputs. The
signal format of the clock outputs is selectable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. For system-level debugging, a bypass mode is
available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8 or 2.5 V supply.
1.1. External Reference
An external, 38.88 MHz clock or a low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high-quality crystal. Specific recommendations
may be found in the Family Reference Manual. An
external 38.88 MHz clock from a high quality OCXO or
TCXO can also be used as a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold, will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5366. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
Preliminary Rev. 0.3
Si5366
VDD
CKOUT3+
CKOUT3–
VDD
SFOUT1
VDD
CKOUT1–
CKOUT1+
VDD
DBL34
FS_OUT–
VDD
FS_OUT+
VDD
NC
VDD
CKOUT2+
CKOUT2–
SFOUT0
VDD
VDD
CKOUT4–
VDD
CKOUT4+
VDD
2. Pin Descriptions: Si5366
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
1
NC
NC
2
74
NC
RST
3
73
NC
FRQTBL
4
72
NC
VDD
5
71
FRQSEL3
VDD
6
70
FRQSEL2
GND
7
69
FRQSEL1
GND
8
68
FRQSEL0
C1B
9
67
DIV34_1
C2B
10
66
DIV34_0
C3B
11
65
GND
ALRMOUT
12
64
GND
CS0_C3A
13
63
VDD
GND
14
62
VDD
VDD
15
61
BWSEL1
XA
60
BWSEL0
XB
16
17
59
C2A
GND
18
58
C1A
GND
19
57
CS1_C4A
FS_SW
20
56
FOS_CTL
FS_ALIGN
21
55
INC
AUTOSEL
22
54
DEC
NC
23
53
NC
NC
24
52
NC
NC
25
Si5366
GND PAD
CK_CONF
DBL_FS
LOL
NC
NC
CKIN1–
GND
CKIN1+
GND
GND
RATE1
CKIN3–
CKIN3+
GND
DBL2_BY
GND
CKIN2–
GND
CKIN2+
RATE0
GND
CKIN4–
CKIN4+
GND
VDD
GND
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Table 3. Si5366 Pin Descriptions
Pin #
Pin Name
1, 2, 23, 24,
25, 47, 48,
52, 53, 72,
73, 74, 75,
90
NC
3
RST
I/O
Signal Level
Description
No Connect.
These pins must be left unconnected for normal operation.
I
LVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are disabled during reset. After rising edge of RST signal, the device
will perform an internal self-calibration when a valid input signal
is present.
This pin has a weak pull-up.
Preliminary Rev. 0.3
7
Si5366
Table 3. Si5366 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
4
FRQTBL
I
3-Level
Frequency Table Select.
This pin selects SONET/SDH, datacom, or SONET/SDH to
datacom frequency translation table.
L = SONET/SDH.
M = Datacom.
H = SONET/SDH to Datacom.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
5, 6, 15, 27,
62, 63, 76,
79, 81, 84,
86, 89, 91,
94, 96, 99,
100
VDD
VDD
Supply
VDD.
The device operates from a 1.8 or 2.5 V supply. Bypass capacitors should be associated with the following VDD pins:
Pins
Bypass Cap
5, 6
0.1 µF
15
0.1 µF
27
0.1 µF
62, 63
0.1 µF
76, 79
1.0 µF
81, 84
0.1 µF
86, 89
0.1 µF
91, 94
0.1 µF
96, 99, 100
0.1 µF
7, 8, 14, 18,
19, 26, 28,
31, 33, 36,
38, 41, 43,
46, 64, 65
GND
GND
Supply
Ground.
This pin must be connected to system ground. Minimize the
ground path impedance for optimal performance.
9
C1B
O
LVCMOS
CKIN1 Invalid Indicator.
This pin is an active high alarm output associated with CKIN1.
Once triggered, the alarm will remain high until CKIN1 is validated.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
C2B
O
LVCMOS
CKIN2 Invalid Indicator.
This pin is an active high alarm output associated with CKIN2.
Once triggered, the alarm will remain high until CKIN2 is validated.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
11
C3B
O
LVCMOS
CKIN3 Invalid Indicator.
This pin is an active high alarm output associated with CKIN3.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
8
Description
Preliminary Rev. 0.3
Si5366
Table 3. Si5366 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
12
ALRMOUT
O
LVCMOS
Alarm Output Indicator.
This pin is an active high alarm output associated with CKIN4
or the frame sync alignment alarm.
0 = ALRMOUT not active.
1 = ALRMOUT active.
13
57
CS0_C3A
CS1_C4A
I/O
LVCMO
Input Clock Select/CKINn Active Clock Indicator.
Input: If manual clock selection mode is chosen
(AUTOSEL = L), the CS[1:0] pins function as the manual input clock selector control.
CS[1:0]
Active Input Clock
00
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
These inputs are internally deglitched to prevent inadvertent clock switching during changes in the CSn input
state. If configured as input, these pins must not float.
Output: If automatic clock detection is chosen (AUTOSEL = M
or H), these pins function as the CKINn active clock
indicator output.
0 = CKINn is not the active input clock.
1 = CKINn is currently the active input clock to the
PLL.
16
17
XA
XB
I
ANALOG
External Crystal or Reference Clock.
An external crystal or an external clock should be connected to
these pins. Frequency of crystal or external clock is set by the
RATE pins. The quality of the selected crystal or external clock
affects the quality of the part's output; refer to the Family Reference Manual for external reference selection and interfacing.
20
FS_SW
I
LVCMOS
FSYNC Inputs to Clock Selection Enable.
If CK_CONF = 1, this pin enables the use of the CKIN3 and
CKIN4 loss-of-signal indicators as inputs to the clock selection
state machine.
0 = Do not use CKIN3 and CKIN4 LOS indicators as inputs to
the clock selection state machine.
1 = Use CKIN3 and CKIN4 LOS indicators as inputs to the
clock selection state machine.
This pin has a weak pull-down.
21
FS_ALIGN
I
LVCMOS
FSYNC Alignment Control.
If CK_CONF = 1, a logic high on this pin causes the FS_OUT
phase to be realigned to the rising edge of the currently active
input sync (CKIN3 or CKIN4).
0 = No realignment.
1 = Realignment.
This pin has a weak pull-down.
Preliminary Rev. 0.3
9
Si5366
Table 3. Si5366 Pin Descriptions (Continued)
10
Pin #
Pin Name
I/O
Signal Level
Description
22
AUTOSEL
I
3-Level
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selection to be used.
L = Manual.
M = Automatic non-revertive.
H = Automatic revertive.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
29
30
CKIN4+
CKIN4–
I
MULTI
Clock Input 4.
Differential clock input. This input can also be driven with a single-ended signal. CKIN4 serves as the frame sync input associated with the CKIN2 clock when CK_CONF = 1.
32
42
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three-level inputs that select the type and rate of external crystal or reference clock to be applied to the XA/XB port. Refer to
the Family Reference Manual for settings. These pins have
both a weak pull-up and a weak pull-down and default to M.
Some designs may require an external resistor voltage divider
when driven by an active device.
34
35
CKIN2+
CKIN2–
I
MULTI
Clock Input 2.
Differential input clock. This input can also be driven with a single-ended signal.
37
DBL2_BY
I
3-Level
CKOUT2 Disable/PLL Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and PLL
bypass mode.
L = CKOUT2 Enabled.
M = CKOUT2 Disabled.
H = BYPASS Mode with CKOUT2 enabled.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
39
40
CKIN3+
CKIN3–
I
MULTI
Clock Input 3.
Differential clock input. This input can also be driven with a single-ended signal. CKIN3 serves as the frame sync input associated with the CKIN1 clock when CK_CONF = 1.
44
45
CKIN1+
CKIN1–
I
MULTI
Clock Input 1.
Differential clock input. This input can also be driven with a single-ended signal.
49
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked.
1 = PLL unlocked.
Preliminary Rev. 0.3
Si5366
Table 3. Si5366 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
50
DBL_FS
I
3-Level
FS_OUT Disable.
This pin performs the following functions:
L = Normal operation. Output path is active and signal format is
determined by SFOUT inputs.
M = CMOS signal format. Overrides SFOUT signal format to
allow FS_OUT to operate in CMOS format while the clock outputs operate in a differential output format.
H = Powerdown. Entire FS_OUT divider and output buffer path
is powered down.
This pin has both weak pull-ups and weak pull-downs and
defaults to M.Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
51
CK_CONF
I
LVCMOS
Input Clock Configuration Control.
This pin controls the input clock configuration.
0 = CKIN1, 2, 3, 4 inputs, no FS_OUT alignment.
1 = CKIN1, 3 and CKIN2, 4 clock/FSYNC pairs.
This pin has a weak pull-down.
54
DEC
I
LVCMOS
Coarse Skew Decrement.
A pulse on this pin decreases the input to output device skew
by 1/fOSC (approximately 200 ps). Detailed operations and timing characteristics for this pin may be found in the Any-Rate
Precision Clock Family Reference Manual. There is no limit on
the range of skew adjustment by this method. If both INC and
DEC are tied high, phase buildout is disabled and the device
maintains a fixed-phase relationship between the selected
input clock and the output clock during an input clock switch.
Detailed operations and timing characteristics for this pin may
be found in the Any-Rate Precision Clock Family Reference
Manual.
This pin has a weak pull-down.
55
INC
I
LVCMOS
Coarse Skew Increment.
A pulse on this pin increases the input to output skew by 1/fOSC
(approximately 200 ps). Detailed operations and timing characteristics for this pin may be found in the Any-Rate Precision
Clock Family Reference Manual. There is no limit on the range
of skew adjustment by this method. If both INC and DEC are
tied high, phase buildout is disabled and the device maintains a
fixed-phase relationship between the selected input clock and
the output clock during an input clock switch. Detailed operations and timing characteristics for this pin may be found in the
Any-Rate Precision Clock Family Reference Manual.
Note: INC does not increase skew if NI_HS = 4.
This pin has a weak pull-down.
Preliminary Rev. 0.3
11
Si5366
Table 3. Si5366 Pin Descriptions (Continued)
12
Pin #
Pin Name
I/O
Signal Level
Description
56
FOS_CTL
I
3-Level
58
C1A
O
LVCMOS
CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator.
0 = CKIN1 is not the active input clock.
1 = CKIN1 is currently the active input clock to the PLL.
59
C2A
O
LVCMOS
CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator.
0 = CKIN2 is not the active input clock.
1 = CKIN2 is currently the active input clock to the PLL.
60
61
BWSEL0
BWSEL1
I
3-Level
Bandwidth Select.
These pins are three level inputs that select the DSPLL closed
loop bandwidth. Detailed operations and timing characteristics
for these pins may be found in the Any-Rate Precision Clock
Family Reference Manual.
These pins have both weak pull-ups and weak pull-downs and
default to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
66
67
DIV34_0
DIV34_1
I
3-Level
CKOUT3 and CKOUT4 Divider Control.
These pins control the division of CKOUT3 and CKOUT4 relative to the CKOUT2 output frequency. Detailed operations and
timing characteristics for these pins may be found in the AnyRate Precision Clock Family Reference Manual.
These pins have both weak pull-ups and weak pull-downs and
default to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
68
69
70
71
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
I
3-Level
Multiplier Select.
These pins are three level inputs that select the input clock and
clock multiplication setting according to the Any-Rate Precision
Clock Family Reference Manual, depending on the FRQTBL
setting.
These pins have both weak pull-ups and weak pull-downs and
default to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
Frequency Offset Control.
This pin enables or disables use of the CKIN2 FOS reference
as an input to the clock selection state machine.
L = FOS Disabled.
M = Stratum 3/3E FOS Threshold.
H = SONET Minimum Clock FOS Threshold.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
Preliminary Rev. 0.3
Si5366
Table 3. Si5366 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
77
78
CKOUT3+
CKOUT3–
O
MULTI
Clock Output 3.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL settings. Output is differential for LVPECL, LVDS,
and CML compatible modes. For CMOS format, both output
pins drive identical single-ended clock outputs.
80
95
SFOUT1
SFOUT0
I
3-Level
Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for all of the clock outputs
except FS_OUT. See DBL_FS pin descripition.
SFOUT[1:0]
Signal Format
HH
Reserved
HM
LVDS
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—Low Swing
LH
CMOS
LM
Disabled
LL
Reserved
These pins have both weak pull-ups and weak pull-downs and
default to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tristate.
82
83
CKOUT1–
CKOUT1+
O
MULTI
Clock Output 1.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL. Output signal format is selected by SFOUT pins.
Output is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical single-ended clock outputs.
85
DBL34
I
LVCMOS
Output 3 and 4 Disable.
Active high input. When active, entire CKOUT3 and CKOUT4
divider and output buffer path is powered down. CKOUT3 and
CKOUT4 outputs will be in tristate mode during powerdown.
This pin has a weak pull-up.
87
88
FS_OUT–
FS_OUT+
O
MULTI
Frame Sync Output.
Differential 8 kHz frame sync output or fifth high-speed clock
output with a frequency specified by FRQSEL and FRQTBL.
Output signal format is selected by SFOUT pins. Detailed operations and timing characteristics for this pin may be found in
the Any-Rate Precision Clock Family Reference Manual. Output is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical single-ended clock outputs.
Preliminary Rev. 0.3
13
Si5366
Table 3. Si5366 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
92
93
CKOUT2+
CKOUT2–
O
MULTI
Clock Output 2.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL. Output signal format is selected by SFOUT pins.
Output is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical single-ended clock outputs.
97
98
CKOUT4–
CKOUT4+
O
MULTI
Clock Output 4.
Differential output clock with a frequency specified by FRQSEL
and FRQTBL settings. Output signal format is selected by
SFOUT pins. Output is differential for LVPECL, LVDS, and
CML compatible modes. For CMOS format, both output pins
drive identical single-ended clock outputs.
GND PAD
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
14
Preliminary Rev. 0.3
Si5366
3. Ordering Guide
Ordering Part Number
Package
ROHS6, Pb-Free
Temperature Range
Si5366-C-GQ
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Preliminary Rev. 0.3
15
Si5366
4. Package Outline: 100-Pin TQFP
Figure 3 illustrates the package details for the Si5366. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 3. 100-Pin Thin Quad Flat Package (TQFP)
Table 4. 100-Pin Package Diagram Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
A
—
—
1.20
E
16.00 BSC
A1
0.05
—
0.15
E1
14.00 BSC
A2
0.95
1.00
1.05
E2
3.85
4.00
4.15
b
0.17
0.22
0.27
L
0.45
0.60
0.75
c
0.09
—
0.20
aaa
—
—
0.20
D
16.00 BSC
bbb
—
—
0.20
D1
14.00 BSC
ccc
—
—
0.08
ddd
—
—
0.08
θ
0º
3.5º
7º
D2
e
3.85
4.00
0.50 BSC
4.15
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant AED-HD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
16
Max
Preliminary Rev. 0.3
Si5366
5. Recommended PCB Layout
Figure 4. PCB Land Pattern Diagram
Preliminary Rev. 0.3
17
Si5366
Table 5. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
0.50 BSC.
E
15.40 REF.
D
15.40 REF.
E2
3.90
4.10
D2
3.90
4.10
GE
13.90
—
GD
13.90
—
X
—
0.30
Y
1.50 REF.
ZE
—
16.90
ZD
—
16.90
R1
R2
0.15 REF
—
1.00
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
18
Preliminary Rev. 0.3
Si5366
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
„
„
„
„
„
„
Updated Table 1, “Performance Specifications,” on
page 2.
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Updated “2. Pin Descriptions: Si5366”.
Updated "3. Ordering Guide" on page 15.
Added “5. Recommended PCB Layout”.
Revision 0.2 to Revision 0.3
Changed 1.8 V operating range to ±5%.
„ Clarified "2. Pin Descriptions: Si5366" on page 7.
„ Updated "4. Package Outline: 100-Pin TQFP" on
page 16.
„
Preliminary Rev. 0.3
19
Si5366
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: Clockinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
20
Preliminary Rev. 0.3
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