TPS65530

TPS65530
TPS65530
www.ti.com....................................................................................................................................................... SLVS744C – OCTOBER 2007 – REVISED MAY 2008
FULLY INTEGRATED 8-CHANNEL DC/DC CONVERTER FOR DIGITAL STILL CAMERAS
FEATURES
APPLICATIONS
• 8-Channel DC/DC Converter and Low Dropout
(LDO)
• Integrated Power MOSFET Switch Except CH8
– Boost (CH5/7)
– Buck (CH1/3)
– Buck-Boost (CH2/4)
– Invert (CH6)
• Low-Power Suspend Mode (Sleep Mode)
• Power ON/OFF Sequence (CH1/2/3 and CH5/6)
• LED-Back Light Brightness Control (CH7)
• Fixed Switching Frequency (CH1–4: 1.5 MHz,
CH5–8: 750 kHz)
• Fixed Max Duty Cycle Internally
• Soft Start
• Undervoltage Lockout (UVLO)
• Protection
– Thermal Shutdown (TSD)
– Overvoltage Protection (OVP)
– Overcurrent Protection (OCP) Except CH8
• Supply Voltage Range: 1.5 V to 5.5 V
• Operating Temperature Range: –25°C to 85°C
• 6 × 6 mm, 0.4-mm Pitch, 48-Pin QFN Package
•
•
1
2
Digital Still Cameras (DSCs)
Portable Electronics Equipment
DESCRIPTION/
ORDERING INFORMATION
The TPS65530 is a fully integrated 8-channel
switching dc/dc converter, and seven channels have
integrated power FET.
CH2/4 are configured for H bridge for buck-boost
topology and single inductor supports. These
channels achieve higher efficiency in spite of
input/output voltage conditions.
CH7 has a brightness control and drives white LED
by constant current. Also, CH7 supports overvoltage
protection (OVP) for open load.
CH1/2/3 have a power ON/OFF sequence suitable for
a digital still camera (DSC) system. CH5/6 have a
power ON/OFF sequence, depending on the CCD.
Power ON/OFF for CCD block (CH5/6) is selectable
by the input voltage level at the SEQ56 pin. CH4 and
CH7 have individual ON/OFF sequences.
The TPS65530 high switching frequency is achieved
by an integrated power MOSFET switch. It reduces
external parts dynamically. Shutdown current
consumption is less than 1 µA as a typical value.
ORDERING INFORMATION
TA
–25°C to 85°C
(1)
(2)
PACKAGE
QFN
(1) (2)
ORDERABLE PART NUMBER
Reel of 250
TPS65530RSLT
Reel of 2500
TPS65530RSLR
TOP-SIDE MARKING
TPS65530
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS65530
SLVS744C – OCTOBER 2007 – REVISED MAY 2008....................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CHANNEL CONFIGURATION
CHANNEL
OPERATION
MODE
RECTIFY
MODE
CONTROL
METHOD
OUTPUT
VOLTAGE
(V)
APPLICATION
MAXIMUM
SUPPLY
CURRENT
(mA)
CH1
Buck SW
Synchronous
Voltage
0.9 to 2.5
Engine core
600
Average current
2.5 to 3.6
Engine I/O
(DSP I/F)
600
CH2
Buck-boost SW
Synchronous
CH3
Buck SW
Synchronous
Voltage
0.9 to 2.5
External memory
300
CH4
Buck-boost SW
Synchronous
Average current
2.2 to 3.6
AFE
300
CH5
Boost SW
Nonsynchronous
Peak current
Up to 18
CCD+
50
CH6
Invert SW
Nonsynchronous
Voltage
–10 to –5
CCD–
100
CH7
Boost SW
Nonsynchronous
Voltage
3 to 20
Backlight LED
25
–
15
CH8
Boost SW
Synchronous
Voltage
3.3 to 5.5
Motor controller
and IC drive supply
REF
Low dropout
voltage
–
–
2.8
Internal supply for
logic
2
VCC4
SEQ56
EN56
S/S56
FB6
SW6
VCC6
FB5
VCC5
SWOUT
SW5
PGND5/7
48
47
46
45
44
43
42
41
40
39
38
37
QFN PACKAGE
(TOP VIEW)
SW4S
1
36
SW7
PGND4
2
35
FBV
SW4I
3
34
CIN
VOUT4
4
33
FBC
FB4
5
32
B-ADJ
ENAFE
6
31
FBG7/8
PowerPAD™
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24
PGND3
SW3
25
23
12
VCC3
VCC2
22
SW8LD
FB3
26
21
11
FB1
REF
20
LL8
PGND1
27
19
10
SW1
AGND
18
SW8HD
VCC1
28
17
9
FB2
S/S
16
PS
VOUT2
29
15
8
SW2I
EN7
14
FB8
PGND2
30
13
7
SW2S
XSLEEP
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65530
TPS65530
www.ti.com....................................................................................................................................................... SLVS744C – OCTOBER 2007 – REVISED MAY 2008
TERMINAL FUNCTIONS
TERMINAL
NO.
(1)
NAME
I/O (1)
DESCRIPTION
1
SW4S
O
Buck-side terminal of coil for CH4
2
PGND4
G
GND for CH4 low-side FET
3
SW4I
I
Boost-side terminal of coil for CH4
4
VOUT4
O
Output of CH4
5
FB4
I
Output voltage feedback for CH4. The external resistors should be connected as close as possible
to the terminal.
6
ENAFE
I
Enable for CH4 (L: Disable, H: Enable)
7
XSLEEP
I
Control for sleep mode/normal operation (L: Sleep mode, H: Normal operation)
8
EN7
I
Enable for CH7 (L: Disable, H: Enable)
9
S/S
I/O
Soft-start time adjustment. The time is programmable by an external capacitor (see the Soft Start
description).
10
AGND
G
Analog ground
11
REF
O
Output of LDO. From 2.2 µF to 4.7 µF, capacitor should be connected to AGND.
12
VCC2
P
Power supply at CH2 buck-side FET from battery
13
SW2S
O
Buck-side terminal of coil for CH2
14
PGND2
G
GND for CH2 low-side FET
15
SW2I
I
Boost-side terminal of coil for CH2
16
VOUT2
O
Output of CH2
17
FB2
O
Output voltage feedback for CH2. The external resistors should be connected as close as possible
to the terminal.
18
VCC1
P
Power supply at CH1 high-side FET from battery
19
SW1
O
Output of CH1. The terminal should be connected to the external inductor.
20
PGND1
G
GND for CH1 low-side FET
21
FB1
I
Output voltage feedback for CH1. The external resistors should be connected as close as possible
to the terminal.
22
FB3
I
Output voltage feedback for CH3. The external resistors should be connected as close as possible
to the terminal.
23
VCC3
P
Power supply at CH3 high-side FET from battery
24
SW3
O
Output of CH3. The terminal should be connected to the external inductor.
25
PGND3
G
GND for CH3 low-side FET
26
SW8LD
O
Output for CH8 external low-side FET drive. The terminal is connected to the gate of the low-side
external FET.
27
LL8
O
Switching output for CH8 at wake mode. The terminal is switched when the output voltage of CH8 is
less than 2.5 V.
28
SW8HD
O
Output for CH8 external high-side FET drive. The terminal is connected to the gate of the high-side
external FET.
29
PS
I
Power input for IC inside. The terminal should be connected to CH8 output voltage.
30
FB8
I
Output voltage feedback for CH8. The external resistors should be connected as close as possible
to the terminal.
31
FBG7/8
I
GND for CH7/8 feedback resistors
32
B-ADJ
I
Brightness adjustment for W-LED
33
FBC
I
Output current feedback for CH7
34
CIN
I
Input current at CH7 load switch
35
FBV
I
Output voltage feedback for CH7. The external resistors should be connected as close as possible
to the terminal.
36
SW7
O
Output of CH7. The terminal should be connected to the external inductor.
37
PGND5/7
G
Power GND for CH5/7. The terminal should be connected by power ground layer at PCB via a
through hole.
38
SW5
O
Low-side terminal of coil for CH5
I = input, O = output, I/O = input/output, P = power supply, G = GND
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O (1)
DESCRIPTION
NO.
NAME
39
SWOUT
O
High-side terminal of coil for CH5
40
VCC5
P
Power supply at CH5 high-side FET from battery
41
FB5
I
Output voltage feedback for CH5. The external resistors should be connected as close as possible
to the terminal.
42
VCC6
P
Power supply at CH6 load switch from battery
43
SW6
O
Output of CH6. The terminal should be connected to the external inductor.
44
FB6
I
Output voltage feedback for CH6. The external resistors should be connected as close as possible
to the terminal.
45
S/S56
I/O
Soft-start time adjustment for CH5/6. The time is programmable by external capacitor (see the Soft
Start description).
46
EN56
I
Enable for CH5/6 (L: Disable, H: Enable)
47
SEQ56
I
Sequence select for CH5/6 (see the Power ON/OFF Sequence description)
48
VCC4
P
Power supply at CH4 high-side FET from battery
Back
side
PowerPAD™
G
Must be soldered to achieve appropriate power dissipation. Should be connected to PGND to use a
Φ0.3-mm through hole.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
Input voltage
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, SWOUT, FB2, FB4,
FB5, FB8, FBC, FBV. PS, XSLEEP, ENAFE, SEQ56,
EN56, EN7, SW4S, SW4I, VOUT4, SW2S, SW2I, VOUT2,
SW1, SW3, SW8LD, SW8HD, FBG78
(based on PGND or AGND)
–0.3 to 6
BADJ, SS, FB1, FB3, FB6, SS56
–0.3 to 3
LL8
–0.3 to 7
REF
–0.3 to 3.6
SW5
–0.3 to 22
SW7, CIN
–0.3 to 27
SW6 (based on VCC6)
–20
PGND1, PGND2, PGND3, PGND4, PGND57, AGND
CIN
Switching current
–0.3 to 0.3
0.05
SW2S, SW2I
3.3
SW4S, SW4I
1.65
SW1
1.9
SW3
1
SW5
1.6
SW6
–1.35
SW7
1.2
LL8
SW8LD, SW8HD
V
A
1
0.6
°C
TJ
Maximum junction temperature range
–30 to 150
Tstg
Storage temperature range
–40 to 150
°C
(1)
4
ESD rating, Human-Body Model (HBM)
JEDEC JESD22A-A114
2
kV
ESD rating, Charged-Device Model (CDM)
JEDEC JESD22A-C101
500
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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Product Folder Link(s): TPS65530
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www.ti.com....................................................................................................................................................... SLVS744C – OCTOBER 2007 – REVISED MAY 2008
DISSIPATION RATINGS
(1)
PACKAGE
RθJA (1)
POWER RATINGS
TA < 25°C
POWER RATINGS RATE
TA > 25°C
48-pin QFN
27°C/W
2.9 W
0.029°C/W
The thermal resistance, RθJA, is based on a soldered PowerPAD package on a 2S2P JEDEC board (3-in × 3-in, four layers) using
thermal vias (0.3-mm diameter × 12 vias)
RECOMMENDED OPERATING CONDITIONS
Supply voltage
High-level input voltage
Low-level input voltage
MIN
MAX
VCC1, VCC2, VCC4, VCC5
1.5
5.5
VCC3, VCC6
2.5
5.5
XSLEEP, ENAFE, EN56, EN7
1.4
SEQ56
1.4
XSLEEP, ENAFE, EN56, EN7, SEQ56
REF
UNIT
V
V
0.4
V
–25
85
°C
TYP (1)
MAX
1
10
VCC2 = 3.6 V, VPS = 5 V, XSLEEP = AGND,
ENAFE = VCC2
40
70
ICC_PWM
VCC2 = 3.6 V , VPS = 5 V, XSLEEP = VCC2,
ENAFE = VCC2, EN56 = VCC2, EN7 = VCC2
20
30
ICC_Iq2
VCC2 = VPS = 3.6 V, XSLEEP = AGND
1
10
ICC_sleep2
VCC2 = 3.6 V, VPS = 5 V, XSLEEP = AGND,
ENAFE = VCC2
12
30
VCC2 = 3.6 V , VPS = 5 V, XSLEEP = VCC2,
ENAFE = VCC2, EN56 = VCC2, EN7 = VCC2
0.3
1
Operating temperature
ELECTRICAL CHARACTERISTICS
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
For All Circuits
ICC_Iq
VCC2 = VPS = 3.6 V, XSLEEP = AGND
ICC_sleep
Consumption current at PS (pin 29)
Consumption current at VCC2 (pin 12)
ICC_PWM2
TSD
Thermal shutdown temperature
V(UV_ON)
UVLO detect level
(2)
V(UV_OFF) UVLO hysteresis
VCC2 from 5.5 V to 0 V
OSC
Internal OSC frequency
VCC2 = 3.6 V
OSC_SUB
CH5–8 switching frequency
OSC = 1.5 MHz, VPS = 5 V
REF output voltage
XSLEEP = VCC2
SS source current
S/S = AGND
Pulldown resistance at XSLEEP,
ENAFE, EN56, EN7, SEQ56
XSLEEP = ENAFE = EN56 = EN7 = SEQ56 = 3 V
Iss
mA
µA
mA
°C
150
VCC2 from 0 V to 5.5 V, XSLEEP = VCC2
µA
1.25
1.4
1.55
50
100
150
mV
1.35
1.5
1.65
MHz
750
V
KHz
2.72
2.8
3.03
V
6
10
14
µA
200
kΩ
CH1
VCC1
Supply voltage
1.5
5.5
V
VOUT1
Output voltage (2)
0.9
2.5
V
IOUT1
Output current (2)
VCC1 > 2.4 V, VOUT1 = 1.2 V,
Feedback resistance: R1 = 330 kΩ,
R2 = 330 kΩ
600
mA
VFB1
FB1 reference voltage
No load
0.6
0.61
V
0.9
1.9
A
0.75
0.83
V
0.59
Overcurrent protection threshold
Overvoltage protection threshold
(sensing at FB1 pin)
(1)
(2)
0.67
TA = 25°C
Specified by design
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ELECTRICAL CHARACTERISTICS (continued)
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
TYP (1)
MAX
UNIT
VPS = 5 V
320
500
mΩ
VPS = 5 V
200
250
mΩ
PARAMETER
TEST CONDITIONS
(3)
Low-side Nch FET ON resistance (3)
High-side Nch FET ON resistance
MIN
Trigger voltage to start CH3
0.48
V
Trigger voltage to power off LDO
0.25
V
CH2
VCC2
VOUT2
Supply voltage
Output voltage
(2)
IOUT2
Output current (2)
VCC2 > 2.4 V, VOUT2 = 3.3 V,
Feedback resistance: R1 = 180 kΩ,
R2 = 820 kΩ
VFB2
FB2 reference voltage
No load
1.5
5.5
V
2.5
3.6
V
600
mA
0.595
Overcurrent protection threshold
Overvoltage protection threshold
(sensing at FB2 pin)
0.67
0.605
0.615
V
2.6
3.3
A
0.75
0.83
V
High-side FET
ON resistance
VPS = 5 V
100
210
Low-side FET
ON resistance
VPS = 5 V
450
600
High-side FET
ON resistance
VPS = 5 V
130
240
Low-side FET
ON resistance
VPS = 5 V
80
140
Trigger voltage to power off CH3
VOUT2 = 0.5 V
0.5
VOUT2 leakage current
VOUT2 = 0.5 V
Nch FET ON resistance for discharge
XSLEEP = AGND, ENAFE = AGND
Buck
side (3)
Boost
side (4)
mΩ
mΩ
1
V
1
µA
2
kΩ
CH3
VCC3
VOUT3
Supply voltage
Output voltage
(5)
IOUT3
Output current (5)
VCC3 > 2.5 V, VOUT3 = 1.8 V,
Feedback resistance: R1 = 220 kΩ,
R2 = 470 kΩ
VFB3
FB3 reference voltage
No load
2.5
5.5
V
0.9
2.5
V
300
mA
0.6
0.61
V
0.6
1
A
0.75
0.83
V
0.59
Overcurrent protection threshold
Overvoltage protection threshold
(sensing at FB3 pin)
0.67
High-side Nch FET ON resistance (4)
VPS = 5 V
370
750
mΩ
Low-side Nch FET ON resistance (4)
VPS = 5 V
300
600
mΩ
Nch FET ON resistance for discharge
XSLEEP = AGND, ENAFE = AGND
1
2
kΩ
Trigger voltage to start CH2
Trigger voltage to power off CH1
0.48
V
0.2
V
CH4
VCC4
Supply voltage
1.5
5.5
V
VOUT4
Output voltage (5)
2.2
3.6
V
100
300
mA
0.605
0.615
IOUT4
Output current (5)
VCC4 > 2.4 V, VOUT4 = 3.3 V,
Feedback resistance: R1 = 82 kΩ,
R2 = 330 kΩ
VFB4
FB4 reference voltage
No load
(3)
(4)
(5)
6
0.595
V
The value of FET ON resistance includes the resistance of bonding wire.
The value of FET ON resistance includes the resistance of bonding wire.
Specified by design
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ELECTRICAL CHARACTERISTICS (continued)
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Overcurrent protection threshold
Overvoltage protection threshold
(sensing at FB4 pin)
Buck
side (4)
Boost
side (4)
0.67
TYP (1)
MAX
UNIT
1.4
1.65
A
0.75
0.83
V
High-side FET
ON resistance
VPS = 5 V
130
310
Low-side FET
ON resistance
VPS = 5 V
600
730
High-side FET
ON resistance
VPS = 5 V
170
270
Low-side FET
ON resistance
VPS = 5 V
130
250
mΩ
mΩ
VOUT4 leakage current
VOUT4 = 0.5 V
Nch FET ON resistance for discharge
XSLEEP = AGND, ENAFE = AGND
1
1
µA
2
kΩ
CH5
VCC5
Supply voltage
VOUT5
Output voltage (5)
VFB5
FB5 reference voltage
No load
IOUT5
Output current (6)
VCC5 > 2.4 V, VOUT5 = 15 V,
Feedback resistance: R1 = 40 kΩ,
R2 = 560 kΩ
1.5
5.5
V
VCC5
18
V
1.02
V
0.98
Overcurrent protection threshold
Overvoltage protection threshold
(sensing at FB5 pin)
1.09
1
50
mA
1.3
1.6
A
1.25
1.38
V
Nch FET ON resistance (7)
VPS = 5 V
610
900
mΩ
Load switch ON resistance
(between VCC5 and SW5)
1.5 V < VCC5 < 5.5 V
100
470
mΩ
Load switch ramp-up time
(between VCC5 and SW5) (6)
1.5 V < VCC5 < 5.5 V,
SWOUT capacitance = 4.7 µF
200
Load switch leakage current
(between VCC5 and SW5)
1
Max duty cycle
Trigger voltage to start up CH6
µS
96
SEQ56 = AGND
µA
98
%
0.8
V
CH6
VCC6
VOUT6
Supply voltage
Output voltage
(6)
IOUT6
Output current (6)
VCC6 > 2.8 V, VOUT6 = –7.5 V,
Feedback resistance: R1 = 136 kΩ,
R2 = 820 kΩ
VFB6
FB6 reference voltage
No load
Overcurrent protection threshold
VCC6 > 2.8 V
Overvoltage protection threshold
(sensing at FB6 pin)
Pch FET ON resistance (7)
VS/S56
S/S56 pin voltage
IS/S56
S/S56 pin source current
5.5
V
–10
–5
V
100
mA
–0.02
–0.3
VCC6 = 3.6 V
Max duty cycle
Trigger voltage to power off CH6
2.5
SEQ56 = AGND
S/S56 = AGND
0
0.02
V
1.1
1.35
A
–0.2
–0.1
V
mΩ
640
1100
84
91
98
%
0.5
0.53
0.56
V
1.22
1.25
1.28
V
170
200
230
µA
5.5
V
CH7
VCC7
(6)
(7)
Supply voltage (6)
1.5
Specified by design
The value of FET ON resistance includes the resistance of bonding wire.
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ELECTRICAL CHARACTERISTICS (continued)
0°C ≤ TJ ≤ 125°C, 1.8 V ≤ VCC2 ≤ 5 V (unless otherwise noted)
PARAMETER
VOUT7
Output voltage
TEST CONDITIONS
(8)
MIN
VCC7 < VOUT7
TYP (1)
3
MAX
UNIT
20
V
IOUT7_L
Lower output current (6)
VCC7 > 2.4 V, VOUT7 = 15 V,
Feedback resistance: R1 = 47 kΩ,
R2 = 680 kΩ, Rsense = 10 Ω,
B_ADJ pin voltage = 0 V
IOUT7_H
Higher output current
(6)
VCC7 > 2.4 V, VOUT7 = 15 V,
Feedback resistance: R1 = 47 kΩ,
R2 = 680 kΩ, Rsense = 10 Ω,
B_ADJ pin voltage = 1 V
23.7
25
26.3
mA
VFBV
FBV reference voltage
No load
0.97
1
1.03
V
1.15
1.25
1.35
V
Overvoltage protection threshold
(sensing at FBV pin)
3.7
5
6.3
mA
Overcurrent protection threshold
0.8
1.2
Nch FET ON resistance (7)
700
1200
91
99
%
2
4
Ω
1
µA
Max duty cycle
86
Load switch ON resistance
Load switch leakage current
(between C-IN and FBC)
RB-ADJ
B-ADJ pin input impedance
1
A
mΩ
mΩ
CH8
Supply voltage (9)
VPS
Output voltage (9)
VFB8
FB8 reference voltage
Fixed ON time at PFM mode
TA = 25°C,
Start up (XSLEEP from AGND to VCC2)
1.8
5.5
XSLEEP = VCC2
1.5
5.5
3.3
5.5
XSLEEP = H, ENAFE = AGND, No load
CH8 operation mode: PFM mode, No load
1.27
1.25
1.35
250
76
85
92
Source impedance
VPS = 5 V, ISW = 100 mA
5
7.5
Sink impedance
VPS = 5 V, ISW = –100 mA
1
1.5
SW8HD
driver
Source impedance
VPS = 5 V, ISW = 100 mA
10
15
Sink impedance
VPS = 5 V, ISW = –100 mA
5
7.5
1.56
1.8
1.3
FBG7/8 FET ON resistance
VPS = 5 V, XSLEEP = VCC2
FBG7/8 leakage current
XSLEEP = AGND, ENAFE = AGND
V
V
ns
SW8LD
driver
Overvoltage protection threshold
(sensing at FB8 pin)
8
1.25
1.2
VCC2 = 3.6 V
Max duty cycle
(8)
(9)
1.23
V
0.6
%
Ω
Ω
V
kΩ
1
µA
Due to constant current control for CH7, the operating condition is that Input voltage is less than LED supply voltage (output voltage).
Specified by design
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BLOCK DIAGRAM
EN56
SEQ56
46
47
48
VCC4
1
SW4S
2
PGND4
3
SW4I
4
VOUT4
5
FB4
6
ENAFE
7
XSLEEP
CP/BST
S/S56 45
FB6 44
SW6 43
CH6
INV
SEQUENCE
CONTROL
(CH5/6)
CH4
Buck
Boost
CP/BST
42
CH1-6, 8
FB5 41
OCP+ UV
X 64
VCC6
VCC5
40
CP
SWOUT 39
TSD
POR
S/S,
REF
CH5
Boost
SW5 38
U-SD
1.5 MHz
To
CH7
LDO
8
EN7
9
S/S
10
AGND
11
REF
12
VCC2
13
SW2S
14
GND2
OSC
INT
Power
1/2
PGND5/7 37
CP/BST
SW7 36
FBV
35
CIN
34
FBC
CH2
Buck
Boost
CH7
Boost
CP/BST
B- ADJ 32
CH1
Buck
31
FB8 30
17 FB2
18
VCC1
19
SW1
20
PGND1
21
FB1
22
FB3
23
VCC3
24
SW3
25
PGND3
CP/BST
From EN7
FBG7/8
16 VOUT2
SEQUENCE
CONTROL
CH1/2/3
W/
Discharge
33
15 SW2I
PFM
PS 29
SW8HD 28
CH8
Boost
CP/BST
LL8 27
Start
Up
SW8LD 26
EEPROM
CH3
Buck
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APPLICATION INFORMATION
10
A.
When output voltage is higher than input voltage at 2AA battery models, VCC1 and VCC3 should be connected to the
CH8 output. When the 2AA battery is connected, VCC6 should be connected to the CH8 output.
B.
The external FET for CH8 is dependent on the load. When the motor is connected to CH8, the external FET is large.
C.
It is acceptable to connect directly to PS without resistor.
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FUNCTIONAL DESCRIPTION
Logic True Table
The enable/disable of each channel is controlled by logic input signals level at XSLEEP (pin 7 for all channels),
ENAFE (pin 6 for CH4), EN56 (pin 46 for CH5/6) and EN7 (pin 8 for CH7). Table 1 is the summary of the
enable/disable mode.
Table 1. Control Pin vs Enable/Disable
NO. OF
STATE
CH8 (1)
LDO
OFF
OFF
OFF
OFF
PWM
ON
OFF
ON
PWM
ON
ON
ON
OFF
PWM
ON
ON
ON
ON
PWM
ON
ON
OFF
OFF
OFF
PWM
ON
ON
ON
OFF
OFF
ON
PWM
ON
ON
ON
ON
ON
OFF
PWM
ON
ON
ON
ON
ON
ON
ON
PWM
ON
OFF
OFF
OFF
OFF
OFF
OFF
PFM
OFF
XSLEEP
ENAFE
EN56
EN7
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
L
L
–
–
OFF
OFF
OFF
OFF
OFF
OFF
2
H
L
L
L
ON
ON
ON
OFF
OFF
OFF
3
H
L
L
H
ON
ON
ON
OFF
OFF
4
H
L
H
L
ON
ON
ON
OFF
5
H
L
H
H
ON
ON
ON
OFF
6
H
H
L
L
ON
ON
ON
7
H
H
L
H
ON
ON
8
H
H
H
L
ON
ON
9
H
H
H
H
ON
10 (2)
L
H
–
–
OFF
(1)
(2)
PWM = pulse width modulation, PFM = pulse frequency modulation
State 10 (CH8: PFM mode) must go through State 2.
Power ON/OFF Sequence
This device has the power ON/OFF sequence of CH1/2/3/8/REF and CH5/6 for DSC application. The
CH1/2/3/8/REF sequence is shown in Figure 1. The CH5/6 sequence is shown in Figure 2. CH4 and CH7 have
individual sequences but CH4–6 has the subordinate relationship with CH1–3 because the slope of soft start is
the same and puts high priority of CH1–3 to avoid the functional conflict (see the Soft Start description). Due to
this, CH4–6 should not be ON before CH1–3 is ON. When XSLEEP is forced low, all channels turn OFF with the
power OFF sequence.
Figure 1. CH1/CH2/CH3/CH8/REF Power ON/OFF Sequence
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Figure 2. CH5/6 Power ON/OFF Sequence
Soft Start
This function reduces the rush current from the battery at start-up. This device has two slopes, defined by S/S
(pin 9) and S/S56 (pin 45). The slopes of CH1–4 are defined by S/S; the slopes of CH5/6 depend on SEQ56 (pin
47) signal level. When SEQ56 is low, the slope of CH5 is defined by S/S; the slope of CH6 is defined by S/S56.
When SEQ56 is high, the slopes of CH5/6 are defined by S/S56. The soft-start time is calculated by Equation 1
and Equation 2.
TS/S = CS/S × 60
(1)
TS/S56 = CS/S56 × 6.25
(2)
Where:
CS/S = Capacitance at S/S [µF]
TS/S = Soft-start duration defined by S/S [ms]
CS/S56 = Capacitance at S/S56 [µF]
TS/S56 = Soft-start duration defined by S/S56 [ms]
The recommended capacitances are CS/S = 0.1 [µF] or TS/S = 6.0 [ms], CS/S56 = 1.0 [µF] or TS/S56 = 6.25 [ms].
Undervoltage Lockout (UVLO)
This device monitors the battery voltage level at VCC2 (pin 12). When XSLEEP is high and VCC2 (pin 12) is less
than the threshold (defined in Electrical Characteristics as UVLO detect level), the operation shuts down
immediately without the power OFF sequence. UVLO has a hysteresis as shown in Figure 3. This factor is
defined in Electrical Characteristics as UVLO hysteresis.
Figure 3. UVLO Hysteresis
Protection
The TPS65530 has three protection conditions: overcurrent protection (OCP), overvoltage protection (OVP), and
thermal shutdown (TSD) (see Table 2).
12
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Table 2. Protection Conditions
PROTECTION
TSD
CH7
CH8
REF (LDO)
Change
mode
All CH shutdown (latch-off)
(without power OFF sequence)
All CH shutdown
All CH shutdown (latch-off)
Forced OFF at MOSFET (latch-off) (without power (without power OFF
OFF sequence)
sequence)
Detect
condition
Current over the threshold, VOUT
less than 80% to compare the
target, and
count 64 cycle × 1.5 MHz
Current over the
threshold
VOUT less than 70% to
compare the target
VOUT less than 80% to
compare the target
Comeback
condition
XSLEEP: Change level from Low
to High
ENAFE: Change level from Low
to High (for CH4)
EN56: Change level from Low to
High (for CH5/6)
or
VCC2: Apply more than UVLO
threshold (1.4 V) after removing
VCC2
Current less than the
threshold (automatic
restoration)
or
VCC2: Apply more than
UVLO threshold (1.4 V)
after removing VCC2
XSLEEP: Change level
from Low to High
ENAFE: Change level
from Low to High
or
VCC2: Apply more than
UVLO threshold (1.4 V)
after removing VCC2
XSLEEP: Change level from
Low to High
ENAFE: Change level from
Low to High
or
VCC2: Apply more than UVLO
threshold (1.4 V) after
removing VCC2
Change
mode
Forced OFF at applicable CH
MOSFET
Forced OFF at
MOSFET, load switch
turns ON
Forced OFF at MOSFET
Detect
condition
Voltage over the threshold at
feedback
Voltage over the
threshold at feedback
Voltage over the
threshold at feedback
Comeback
condition
Voltage less than the threshold at EN7: Change level from
feedback (auto-recovery)
Low to High
Change
mode
All CH shutdown (without power OFF sequence)
Detect
condition
The junction temperature is more than the threshold.
Comeback
condition
XSLEEP: Change level from Low to High, ENAFE: Change level from Low to High (for CH4), EN56: Change level from
Low to High (for CH5/6), or VCC2: More than 1.4 V
OCP
OVP
CH1–CH6
No OVP function
Voltage less than the
threshold at feedback
(auto-recovery)
CHANNEL DESCRIPTIONS
CH1/3 Description
Both CH1 and CH3 are the same topology. CH1/3 are the voltage-mode-controlled synchronous buck converters
for engine core (CH1) or external memory (CH3). Both high-side and low-side switches are integrated into the
device and consist of NMOS-FET only. The gate of the high-side switch is driven by bootstrap circuit. The
capacitance of the bootstrap is included in the device. These channels are able to operate up to 100% duty
cycle.
This device has a discharge path to use the switch (Q_Discharge1/3) for the CH1/3 output capacitor via the
inductor. The switch is activated after the power OFF sequence has started. Typical resistance at the discharge
circuit is 1 kΩ. When the device detects the threshold at FB1/3 after the power OFF sequence has started, the
MOSFET turns OFF and the output is fixed with high impedance.
It is acceptable to connect the battery to VCC1/VCC3 (pins 18/23) directly when the battery voltage is more than
2.5 V. When the battery voltage is less than 2.5 V, the CH8 output should be connected to VCC1/VCC3.
The output voltage is programmed from 0.9 V to 2.5 V (both CH1 and CH3) to use the feedback loop sensed by
the external resistances. The output voltage is calculated by Equation 3. The block diagram is shown in Figure 4.
VOUT = (1 + R2/R1) × 0.6 [V]
(3)
Where:
VOUT = Output voltage [V]
R1, R2 = Feedback resistance (see Figure 4)
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Figure 4. CH1/3 Block Diagram
CH1/3 Recommended Parts
Table 3. Recommended Parts for Inductor (CH1/3)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
TOKO
DE2812C-1098AS-4R7M
4.7
130
2.8 × 3.0 × 1.2
Table 4. Recommended Parts for Capacitor (Input, CH1/3)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM21BB30J226ME38
22.0
20
2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 5. Recommended Parts for Capacitor (Output, CH1/3)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
TDK
C2012X5R0J106M
10.0
20
2.0 × 1.25 × 1.25 (EIA code: 0805)
CH2/4 Description
Both CH2 and CH4 are the same topology. CH2/4 are the average current-mode-controlled synchronous
back-boost converters for engine I/O (CH2) or AFE (CH4). This converter is an adapted H-bridge circuit to use
four switches. These switches are integrated into the device and consist of NMOS-FET only. The gate of the
high-side switch is controlled by the bootstrap circuit. The capacitance of the bootstrap is included in the device.
The device automatically switches from buck operation to boost operation or from boost operation to buck
operation as required by the configuration. It always uses one active switch, one rectifying switch, one switch
permanently on, and one switch permanently off. Therefore, it operates as a buck converter when the input
voltage is higher than the output voltage, and as a boost converter when the input voltage is lower than the
output voltage. There is no mode of operation in which all four switches are permanently switching.
14
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This device has a discharge switch (Q_Discharge2/4) for the CH2/4 output capacitor. The typical ON resistance
at the discharge switch is 1 kΩ. The discharge switch is activated when XSLEEP turns low. For CH4 only, the
switch is also activated when ENAFE turns low. After output voltage reaches approximately 0.5 V, the discharge
switch turns OFF and VOUT2/VOUT4 is changed into high impedance. The output voltage is programmable from 2.5
V to 3.6 V (for CH2) or from 2.2 V to 3.6 V (for CH4) to use the feedback loop sensed by the external
resistances. The output voltage is calculated by Equation 4. The block diagram is shown in Figure 5.
VOUT = (1 + R2/R1) × 0.6 [V]
(4)
Where:
VOUT = Output voltage [V]
R1, R2 = Feedback resistance (see Figure 5)
Figure 5. CH2/4 Block Diagram
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CH2/4 Recommended Parts
Table 6. Recommended Parts for Inductor (CH2)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
TOKO
DE2812C-1098AS-2R7M
2.7
72
2.8 × 3.0 × 1.2
Table 7. Recommended Parts for Inductor (CH4)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
TOKO
DE2812C-1098AS-4R7M
4.7
130
2.8 × 3.0 × 1.2
Table 8. Recommended Parts for Capacitor (Input, CH2/4)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM21BB30J226ME38
22.0
20
2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 9. Recommended Parts for Capacitor (Output, CH2/4)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Taiyo Yuden
JMK212BJ476MG-T
47.0
20
2.0 × 1.25 × 1.25 (EIA code: 0805)
CH5 Description
CH5 is the peak current-mode-controlled nonsynchronous boost converter for CCD+. The switch between
inductor and power GND is integrated into the device and consists of NMOS-FET. Also, this device has a load
switch between the battery and inductor and consists of NMOS-FET. The gate of the switch is controlled by a
charge-pump circuit. The output voltage is programmable up to 18 V to use the feedback loop sensed by the
external resistances. The output voltage is calculated by Equation 5. The block diagram is shown in Figure 6.
VOUT5 = (1 + R2/R1) × 1.0 [V]
(5)
Where:
VOUT5 = Output voltage of CH5 [V]
R1, R2 = Feedback resistance (see Figure 6)
16
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Figure 6. CH5 Block Diagram
CH5 Recommended Parts
Table 10. Recommended Parts for Inductor (CH5)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
TOKO
DE2812C-1098AS-120M
12.0
340
2.8 × 3.0 × 1.2
Table 11. Recommended Parts for Capacitor (Output, CH5)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM31CB31E106KA75
10.0
10
3.2 × 1.6 × 1.6 (EIA code: 1206)
Table 12. Recommended Parts for Capacitor (SWOUT, CH5)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
TDK
C2012X5R1A335M
3.3
20
2.0 × 1.25 × 1.25 (EIA code: 0805)
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Table 13. Recommended Parts for Diode (CH5)
VENDOR
TYPE NO.
VR (V)
IF (mA)
VF (V)/IF (A)
CAPACITANCE (pF)
SIZE (mm)
Sanyo
SB0503EJ
30
500
0.55/0.5
16.5
1.6 × 0.8 × 0.6
CH6 Description
CH6 is the voltage-mode-controlled nonsynchronous inverting converter for CCD–. The switch between the input
voltage and inductor is integrated into the device and consists of PMOS-FET. It is acceptable to connect the
battery to VCC6 (pin 42) directly when the battery voltage is more than 2.5 V. When the battery voltage is less
than 2.5 V, the CH8 output should be connected to VCC6. The output voltage is programmable from –10 V to
–5 V to use the feedback loop sensed by the external resistances. The output voltage is calculated by
Equation 6. The block diagram is shown in Figure 7.
VOUT6 = 1.25 – (1 + R2/R1) × 1.25 [V]
(6)
Where:
VOUT6 = Output voltage of CH6 [V]
R1, R2 = Feedback resistance (see Figure 7)
Figure 7. CH6 Block Diagram
CH6 Recommended Parts
Table 14. Recommended Parts for Inductor (CH6)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
TOKO
DE2815C-1071AS-120M
12.0
240
2.8 × 3.0 × 1.2
Table 15. Recommended Parts for Capacitor (Input, CH6)
18
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM21BB31A106KE18
10.0
10
2.0 × 1.25 × 1.25 (EIA code: 0805)
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Table 16. Recommended Parts for Capacitor (Output, CH6)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM31CB31E106KA75
10.0
10
3.2 × 1.6 × 1.6 (EIA code: 1206)
Table 17. Recommended Parts for Diode (CH6)
VENDOR
TYPE NO.
VR (V)
IF (mA)
VF (V)/IF (A)
CAPACITANCE (pF)
SIZE (mm)
Sanyo
SB0503EJ
30
500
0.55/0.5
16.5
1.6 × 0.8 × 0.6
CH7 Description
CH7 is the voltage-mode-controlled nonsynchronous boost converter for the backlight LED. The switch between
the inductor and power GND is integrated into the device and consists of NMOS-FET. Also, this device has a
load switch to control the output current and consists of NMOS-FET. The output current is constant and is
calculated by Equation 7. It is controlled by the B_ADJ (pin 32) input voltage as shown in Figure 8. The B_ADJ
input voltage is required as an analog input. When it is required to input PWM signal for B_ADJ, the RC filter is
needed.
ILED =
0.2
0.05
• VBADJ +
RSENSE
RSENSE
(7)
Where:
ILED = Output current of CH7 [A]
RSENSE = Sense resistor between FBC and PGND5/7 [Ω]
VBADJ = B_ADJ input voltage (0 < VBADJ < 1) [V]
Figure 8. Output Current vs B_ADJ Input Voltage (RSENSE = 10 Ω)
The principle of the operation is to adjust the duty cycle of the MOSFET. When the B_ADJ input voltage is
changed, the level of “A” point shown in Figure 9 is changed to get the desired duty cycle compared to the sense
current.
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Figure 9. LED Brightness Control Block Diagram
At first, CH7 operates as pulse frequency modulation (PFM) mode at start-up. After reaching the target output
voltage, CH7 operation is changed from PFM mode to pulse width modulation (PWM) mode automatically. The
output voltage is programmable up to 20 V to use the feedback loop sensed by the external resistances. The
maximum output voltage is calculated by Equation 8. The block diagram is shown in Figure 10.
VOUT7
MAX
= 1 + (R2/R1) × 1.25 [V]
(8)
Where:
VOUT7
MAX
= Maximum output voltage of CH7 [V]
R1, R2 = Feedback resistance (see Figure 10)
20
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Figure 10. CH7 Block Diagram
CH7 Recommended Parts
Table 18. Recommended Parts for Inductor (CH7)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
TOKO
DE2815C-1071AS-120M
12.0
240
2.8 × 3.0 × 1.2
Table 19. Recommended Parts for Capacitor (Input, CH7)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM21BB31A106KE18
10.0
10
2.0 × 1.25 × 1.25 (EIA code: 0805)
Table 20. Recommended Parts for Diode (CH7)
VENDOR
TYPE NO.
VR (V)
IF (mA)
VF (V)/IF (A)
CAPACITANCE (µF)
SIZE (mm)
Sanyo
SB0503EJ
30
500
0.55/0.5
16.5
1.6 × 0.8 × 0.6
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Table 21. Recommended Parts for Capacitor (Output, CH7)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM31CB31E106KA75
10.0
10
3.2 × 1.6 × 1.6 (EIA code: 1206)
CH8 Description
CH8 uses an external FET. It is based on voltage-mode-controlled synchronous boost converter topology used
for motor control and an IC inside driver. CH8 output should connect to PS (pin 29) because PS is the path to
supply the power for the driver of each channel. This channel has two operation modes – PWM and PFM. The
operation depends on the XSLEEP (pin 7) and ENAFE (pin 6) signal level.
When XSLEEP turns high, CH8 operates as PWM mode. The ENAFE signal level does not matter. For start-up
(less than 2.5 V at CH8 output), CH8 operates as WAKE mode to use the internal MOSFET switch connected to
LL8 (pin 27). The duty cycle of WAKE mode is fixed. After PS voltage reaches 2.5 V, CH8 operation is changed
from WAKE mode to PFM mode automatically. PFM mode is driven by the external MOSFET switch. When PS
voltage reaches 90% of the target voltage, the operation mode is changed from PFM mode to PWM mode
automatically. To operate CH8 in PFM mode only, XSLEEP must be high at first. After that, XSLEEP goes low
and ENAFE is high for PFM mode. PFM operation is recommended for the IC drive only from an efficiency point
of view.
CH8 has reversed current protection to monitor the different voltage between LL8 and PS. The protection
monitors the difference between both PFM mode and PWM mode. When LL8 voltage is larger than PS voltage,
the function is activated. When the function is activated, SW8HD (pin 28) level is changed from high to low;
SW8LD (pin 26) level stays low. This means that LL8 voltage converges the battery voltage naturally.
The recovery condition is dependent on the operation mode. When CH8 operates as PFM mode, the condition is
that FB8 (pin 30) voltage is less than 1.25 V. When CH8 operates as PWM mode, the condition is that LL8
voltage is smaller than PS voltage at the rising edge of the internal clock.
The output voltage is programmable from 3.3 V to 5.5 V to use the feedback loop sensed by the external
resistances. The output voltage is calculated by Equation 9. The block diagram is shown in Figure 11.
VOUT8 = (1 + R1/R2) × 1.25 [V]
(9)
Where:
VOUT8 = Output voltage of CH8 [V]
R1, R2 = Feedback resistance (see Figure 11)
22
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Product Folder Link(s): TPS65530
TPS65530
www.ti.com....................................................................................................................................................... SLVS744C – OCTOBER 2007 – REVISED MAY 2008
Figure 11. CH8 Block Diagram
CH8 Recommended Parts
For Motor Control and IC Inside Driver
Table 22. Recommended Parts for Inductor (CH8)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
TOKO
DE4518-1124-4R3M
4.3
54
4.5 × 4.7 × 1.8
Table 23. Recommended Parts for Capacitor (Input, CH8)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
TDK
C3216X5R0J226M
22.0 × 2 pcs
20
3.2 × 1.6 × 0.85 (EIA code: 1206)
Table 24. Recommended Parts for Capacitor (Output, CH8)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
Murata
GRM31MB31A106KE18
10.0 × 2 pcs
10
3.2 × 1.6 × 1.15 (EIA code: 1206)
Table 25. Recommended Parts for FET (CH8)
VENDOR
TYPE NO.
ID (DC)
(N-ch) (A)
ID (DC)
(P-ch) (A)
Rds(on)
(N-ch) (Ω)
Rds(on)
(P-ch) (Ω)
QG (N-ch) (nQ)
QG (P-ch) (nQ)
VEC2607
4.5
–4.0
0.032/4 V
0.037/–4.5 V
7.6
11.0
VEC2611
3.0
–2.6
0.053/4 V
0.080/–4.5 V
8.8
6.5
Sanyo
For IC Inside Driver Only
Table 26. Recommended Parts for Inductor (CH8)
VENDOR
TYPE NO.
INDUCTANCE (µH)
DCR (mΩ)
SIZE (mm)
Taiyo Yuden
LB2518T330
33
700
1.8 × 2.5 × 1.8
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Product Folder Link(s): TPS65530
23
TPS65530
SLVS744C – OCTOBER 2007 – REVISED MAY 2008....................................................................................................................................................... www.ti.com
Table 27. Recommended Parts for Capacitor (Input, CH8)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
TDK
C3216X5R0J226M
22
20
3.2 × 1.6 × 0.85 (EIA code: 1206)
Table 28. Recommended Parts for Capacitor (Output, CH8)
VENDOR
TYPE NO.
CAPACITANCE (µF)
TOLERANCE (%)
SIZE (mm)
TDK
C1608X5R0J475M
4.7
20
1.6 × 0.8 × 0.8 (EIA code: 0603)
Table 29. Recommended Parts for FET (CH8)
VENDOR
TYPE NO.
ID (DC)
(N-ch) (A)
ID (DC)
(P-ch) (A)
Rds(on)
(N-ch) (Ω)
Rds(on)
(P-ch) (Ω)
QG (N-ch)
(nQ)
QG (P-ch)
(nQ)
ON
Semiconductor
NTZD3155C
0.54
–0.43
0.4/4.5 V
0.5/–4.5 V
1.5
1.7
Sanyo
SCH2615
1.2
–0.9
0.28/4 V
0.47/–4.5 V
1.15
1.43
Layout Consideration
To avoid ground shift problems due to the high currents in the switches, separate AGND (pin 10) from PGND1
(pin 20), PGND2 (pin 14), PGND3 (pin 25), PGND4 (pin 2), and PGND5/7 (pin 37). The reference GND for all
control signals, such as XSLEEP, is AGND. The power switches inside the IC are connected to PGND1, PGND2,
PGND3, PGND4, and PGND5/7. Both grounds must be connected on the printed circuit board (PCB) (ideally at
only one point).
24
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS65530RSLR
ACTIVE
VQFN
RSL
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS65530RSLRG4
ACTIVE
VQFN
RSL
48
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS65530RSLT
ACTIVE
VQFN
RSL
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS65530RSLTG4
ACTIVE
VQFN
RSL
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65530RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
TPS65530RSLT
VQFN
RSL
48
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65530RSLR
VQFN
RSL
48
2500
367.0
367.0
38.0
TPS65530RSLT
VQFN
RSL
48
250
210.0
185.0
35.0
Pack Materials-Page 2
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