High Quality III-V Semiconductors/Si Heterostructures for Photonic Integration and Photovoltaic Applications

High Quality III-V Semiconductors/Si Heterostructures for Photonic Integration and Photovoltaic Applications

High Quality III-V Semiconductors/Si Heterostructures for

Photonic Integration and Photovoltaic Applications

Himanshu Kataria

Doctoral Thesis in Microelectronics and Applied Physics

Stockholm, Sweden 2014

Laboratory of Semiconductor Materials

Department of Materials and Nano Physics

School of Information and Communication Technology

KTH Royal Institute of Technology

High Quality III-V Semiconductors/Si Heterostructures for Photonic Integration and

Photovoltaic Applications

A dissertation submitted to the Royal Institute of Technology, Stockholm, Sweden, in partial fulfilment of the requirements for the degree of Doctor of Philosophy (Teknologie Doktor).

TRITA-ICT/MAP AVH Report 2014:13

ISSN 1653-7610

ISRN KTH/ICT-MAP/AVH-2014:13-SE

ISBN 978-91-7595-289-5

© Himanshu Kataria, 2014

Printed by US-AB, Stockholm, 2014

Cover picture: Schematic of the monolithically integrated III-V laser on silicon based on epitaxial lateral overgrowth technique, defects originating from the defective InP seed layer are blocked by the SiO

2

mask.

The curve (inset) shows the room temperature emission from one of the optically pumped microdisk resonators fabricated in this thesis work.

To my parents

Abstract

High Quality III-V Semiconductors/Si Heterostructures for

Photonic Integration and Photovoltaic Applications

Himanshu Kataria

TRITA-ICT/MAP AVH Report 2014:13; ISSN 1653-7610; ISRN KTH/ICT-MAP/AVH-2014:13-SE

ISBN 978-91-7595-289-5

Abstract

This thesis deals with one of the promising strategies to monolithically integrate

III-V semiconductors with silicon via epitaxial lateral overgrowth (ELOG) technology and is supported by extensive experimental results. The aimed applications are light sources on silicon for electronics-photonics integration and cost effective high efficiency multijunction solar cells.

The work focusses on the growth of III-V semiconductors consisting of indium phosphide (InP) and its related alloys on silicon primarily because of the bandgaps that these offer for the aimed applications. For this purpose, we make use of the epitaxial growth technique called hydride vapour phase epitaxy and exploit its near equilibrium operation capability to achieve primarily ELOG of high quality InP as the starting material on patterned InP(seed)/silicon wafer. The InP/InGaAsP layers are grown by metal organic vapour phase epitaxy.

Different pattern designs are investigated to achieve high quality InP over a large area of silicon by ELOG to realise lasers. First, nano patterns designed to take advantage of aspect ratio trapping of defects are investigated. Despite substantial defect filtering insufficient growth area is achieved. To achieve a larger area, coalescence from multiple nano openings is used. Shallowly etched InP/InGaAsP based microdisk resonators fabricated on indium phosphide on silicon achieved by this method have shown whispering gallery modes. However, no lasing action is observed partly due to the formation of new defects at the points of coalescence and partly due to leakage losses due to shallow etching. To overcome these limitations, a new design mimicking the futuristic monolithic evanescently coupled laser design supporting an efficient mode coupling and athermal operation is adopted to yield large areas of ELOG InP/Si having good carrier transport and optical properties. Microdisk resonators fabricated from the uniformly obtained InP/InGaAsP structures on the ELOG InP layers have shown very strong spontaneous luminescence close to lasing action. This is observed for the first time in

InP/InGaAsP laser structures grown on ELOG InP on silicon.

A newly modified ELOG approach called Corrugated ELOG is also developed.

Transmission electron microscopy analyses show the formation of abrupt interface between InP and silicon. Electrical measurements have supported the linear Ohmic behaviour of the above junction. This proof of concept can be applied to even other III-V compound solar cells on silicon. This allows only thin layers of expensive III-V semiconductors and cheap silicon as separate subcells for fabricating next generation multijunction solar cells with enhanced efficiencies at low cost. A feasible device structure of such a solar cell is presented. The generic nature of this technique also makes it suitable for integration of III-V light sources with silicon and one such design is proposed.

ii Acknowledgement

Acknowledgement

I joined the laboratory of semiconductor materials, “HMA” at Kungliga Tekniska

Högskola in June 2010, after I was awarded the Erasmus Mundus scholarship to pursue my Ph.D. studies. I would like to thank Prof. Sebastian Lourdudoss “Doss” and the

European Union for accepting my application and giving me the opportunity to pursue my dream. All these years Prof. Doss has always been there to listen to my never ending questions about research, I thank him for his forbearance and encouragement. I thank Prof.

Doss for being a true guide not only as a researcher but also as a father figure to me in

Sweden. I thank him for patiently listening to my worries from every aspect of my life.

Second, I would like to thank Prof. Srinivasan Anand, my second supervisor and a very good friend for numerous insightful discussions we had about science of photons and science of life. I will miss our daily discussions in “Pendeltåg” about everything.

I would like to express my special thanks to my seniors Dr. Carl Junesand and Dr.

Wondwosen Metaferia for introducing me to the field of heteroepitaxy of semiconductors in a pedagogical manner. Whether, it was about HVPE or a characterisation technique my questions were always answered, I thank them for their patience with me.

I would like to thank Dr. Yanting Sun for giving me the opportunity to work with him on the multijunction solar cell project, I have learnt a lot from him.

I would like to thank all the professors those who instructed me as course teachers during my stay at KTH, Mattias Hammar, Richard Schatz, Anders Larsson, Mikael

Ösling, Henry Radamson and many others. I also thank all the technical staff at the

Electrum laboratory for keeping the equipment up and running and making it possible for me to perform my research.

I thank all of my friends I have made at KTH during my Ph.D, I will never forget the support I received from all of you.

This work is a joint effort of many of my colleagues working at HMA and our collaborators abroad. I would like to thank Dr. Zhechao Wang, Dr Alexandre Bazin,

Chong Zhang, Bin Tian, Nick Julian, Phil Mages, Prof. John E. Bowers, Assoc. Prof.

Fabrice Raineri, Prof. Dr. Ir. Dries Van Thourhout and their colleagues for their fruitful collaboration.

A special thanks to our department administrator Ms. Madeleine Printzsköld, for helping with all kind of administrative work and making the whole process very simple.

I am a person who believes in destiny and I believe my life brought me to Sweden not only to do a Ph.D but also to introduce me to love of my life “Hanna”. She has been a

Acknowledgement constant source of encouragement and I thank her for being so understanding and patient. I thank Sweden for giving me the two most meaningful things in my life.

I thank my parents and sisters back home in India for keeping their faith in me; I believe it is their prayers and blessing that made me complete this Ph.D successfully.

I understand that many things could have been done differently and in a better way. Nevertheless, I sincerely hope that despite all the shortcomings of this thesis, it may be helpful for others.

Finally, I would like to finish with an excerpt from the preface by Prof. John H.

Davies to his book “The Physics of Low-Dimensional Semiconductors”.

“An author never finishes a book, he just abandons it”.

Himanshu Kataria

Stockholm, September 2014.

iv List of papers

List of papers

Publications included in the thesis

A. H. Kataria, C. Junesand, Z. Wang, W. Metaferia, Y. T. Sun, Sebastian

Lourdudoss, G. Patriarche, A. Bazin, F. Raineri, P. Mages, N. Julian and J. E.

Bowers, “Towards a monolithically integrated III-V laser on silicon: optimization of multi quantum well grown on InP on Si”, Semicond. Sci.

Technol. 28 (2013) 094008-094015. (Invited)

B. H. Kataria, W. Metaferia, C. Junesand, C. Zhang, N. Julian, J. E. Bowers, S.

Lourdudoss, “Simple epitaxial lateral overgrowth process as a strategy for photonic integration on silicon”, IEEE J. Select. Topics in Quant. Elect.

10.1109/JSTQE.2013.2294453.

C. H. Kataria, W. Metaferia, M. Nagarajan, C. Junesand, Y. Sun, and S.

Lourdudoss, “Carrier-transport, optical and structural properties of large area

ELOG InP on Si using conventional optical lithography,” in 2013 International

Conference on Indium Phosphide and Related Materials (IPRM), Japan, 2013, pp. 1–2

D. H. Kataria, W. Metaferia, C. Junesand, C. Zhang, J. E. Bowers, and S.

Lourdudoss, “High quality large area ELOG InP on silicon for photonic integration using conventional optical lithography,” in 2014 SPIE, Photonics

West, USA, 2014, vol. 8989, pp. 898904–898904–9. (Invited)

E. C. Junesand, H. Kataria, W Metaferia, N. Julian, Z. Wang, Y. T. Sun, J. E.

Bowers, G Pozina, L. Hultman, S. Lourdudoss, “Study of planar defect filtering in InP grown on Si by epitaxial lateral overgrowth”, Opt. Mater. Express 3(11)

(2013)1960-1973.

F. Y-T. Sun, H. Kataria, W. Metaferia, “Realization of atomically abrupt InP/Si heterojunction and dislocation reduction via corrugated epitaxial lateral overgrowth”, CrystEngComm(2014), DOI: 10.1039/C4CE00844H

G. W. Metaferia, H. Kataria, Y-T. Sun and S. Lourdudoss, “Optimization of InP growth directly on Si by corrugated epitaxial lateral overgrowth”, Submitted to

Journal of Physics D:Applied Physics.

List of papers

Other relevant publications not included in the thesis

Journal Publications

1. W. Metaferia, A. Dev, H. Kataria, C. Junesand, Y-T. Sun, S. Anand, J.

Tommila, G. Pozina, L. Hultman, M. Guina, T. Niemi and S. Lourdudoss,

“High quality InP nanopyramidal frusta on Si”, CrystEngComm(2014),

DOI:10.1039/C3CE42231C.

2. W. Metaferia, J. Tommila, C. Junesand, H. Kataria, C. Hu, M. Guina, T.

Niemi, and S. Lourdudoss, “Selective area heteroepitaxy through nanoimprint lithography for large area InP on Si”, Phys. Stat. solidi C 9, No. 7 (2012)1610-

1613.

Conference Contributions

1. H. Kataria, W. Metaferia, C. Junesand, Y. T. Sun and S. Lourdudoss,

“Monolithic Integration of InP Based Structures on Silicon for Optical

Interconnects” ECS and SMEQ Joint International Meeting (October 5-10,

2014) (Electronic Materials and Processing). Accepted for publication in ECS transaction. (Invited)

2. O. Parillaud, G-M de Naurois, B. Simozrag, V. Trinité, G. Maisons, M.Garcia,

B. Gérard, and M. Carras, W. Metaferia, C. Junesand, H. Kataria, Y. Sun, and

S. Lourdudoss, “Multi-regrowth steps for the realization of buried single ridge and micro-stripes quantum cascade lasers”, in: 2013 International Conference

on Indium Phosphide and Related Materials (IPRM), (2013)1–2.

3. W. Metaferia, J. Tommila, H. Kataria, C. Junesand, Y. Sun, M. Guina, T.

Niemi, and S. Lourdudoss, “Selective area heteroepitaxy of InP nanopyramidal frusta on Si for nanophotonics,” in 2012 International Conference on Indium

Phosphide and Related Materials (IPRM), 2012, USA, pp. 81–84.

4. W. Metaferia, J. Tommila , C. Junesand, H. Kataria, C. Hu, M. Guina, T.

Niemi and S. Lourdudoss, “Large area and selective area heteroepitaxial growth of indium phosphide on silicon through nanoimprint lithography”, in

2011 16th Semiconducting and Insulating Materials Conference, 2011,

Stockholm,. Pp. 1610-1613.

5. H. Kataria, W. Metafaria, C. Junesand, Y. Sun, S. Lourdudoss, "High quality large area ELOG InP on silicon using conventional optical lithography", Optics

and Photonics day, Swedish Optical Society, Stockholm, Sweden

6. S. Lourdudoss, C. Junesand, W. Metaferia, H. Kataria and Y. Sun,

“Integration of III-V Device Structures on Silicon for Optical Interconnects”,

PIERS, Stockholm, Sweden, 2013.

vi List of papers

7. S. Lourdudoss, C. Junesand, W. Metaferia, H. Kataria and Y. Sun, “Direct

Growth of Multi-quantum Wells on Micro and Nanostructures of Indium

Phosphide on Silicon for Silicon Photonics”, PIERS, Stockholm, Sweden,

2013.

Other Publications

1. H. Kataria and S. Lourdudoss, “Monolithic Solution to Heterogeneous III-V sources on Silicon”, Feature article for Compound Semiconductor Magazine (in press) 2014. (Invited)

2. H. Kataria and S. Lourdudoss, “Integrated Light Sources on Silicon, SPIE

Newsroom, (in press) 2014. (Invited)

Acronyms

AFM Atomic Force Microscopy

APD a-Si Amorphous

CL Cathodoluminescence

CMOS Complementary Metal Oxide Semiconductor

EBL

EDS

Electron Beam Lithography

Energy Dispersive X-ray Spectroscopy

ELOG

FIB

FDTD

IC

Epitaxial Lateral Overgrowth

Focussed Ion Beam

Finite Difference Time Domain

Integrated Circuit

ICP Inductively Plasma

I-V Current-Voltage

LP-HVPE Low Pressure Hydride Vapour Phase Epitaxy

MD Microdisk

MECSL

MOVPE

MQW

Monolithic Evanescently Coupled Silicon Laser

Metal Organic Vapour Phase Epitaxy

Multi Quantum Well

NA Numerical

Nd:YAG Neodymium Doped Yttrium Aluminium Garnet

NELOG Nano-ELOG

PC-CL

PECVD

Panchromatic-Cathodoluminescence

Plasma Enhanced Chemical Vapour Deposition

PL Photoluminescence

QD Quantum

RF Radio

RIE Reactive Etching rms Root Square

RT Room

SAG

SCH

SEM

Selective Area Growth

Separate Confinement Heterostructure

Scanning Electron Microscopy

SMU

WGM

Source Measure Unit

TEM

UID Unintentionally

Whispering Gallery Mode

Acronyms

viii Table of Contents

Table of Contents

Abstract

............................................................................................................................................ i 

Acknowledgement

........................................................................................................................ ii 

List of papers

................................................................................................................................ iv 

Acronyms

..................................................................................................................................... vii 

Table of Contents

........................................................................................................................ viii 

1

  Introduction ............................................................................................................................. 1 

1.1

  Heterogeneous bonding of InP on Si ....................................................................................... 2 

1.2

  Heteroepitaxial solutions for InP on Si ................................................................................... 3 

1.3

  Goals and Achievements of this thesis .................................................................................... 4 

1.4

  Thesis Outline .................................................................................................................................. 5 

2

  Theoretical Background ....................................................................................................... 8 

2.1

  Crystallographic defects ............................................................................................................... 8 

2.1.1  Defects in InP grown on Si................................................................................................ 11 

2.1.2  Defect reduction in InP on Si by using ELOG ........................................................... 12 

2.1.3  Blocking the threading defects by using “Epitaxial Necking” .............................. 13 

2.2

  Application of III-Vs on Si in silicon photonics and multijunction photovoltaic ... 14 

2.2.1  ELOG for III-V lasers on silicon photonics ................................................................ 14 

2.2.2  CELOG for III-Vs and Si multijunction photovoltaic.............................................. 15 

2.2.3  CELOG for Silicon Photonics .......................................................................................... 16 

3

  Experimental Techniques.................................................................................................. 19 

3.1

  Chemical Mechanical Polishing (CMP) ............................................................................... 19 

3.1.1  CMP of InP seed layer ........................................................................................................ 19 

3.1.2  CMP of SiO

2

.......................................................................................................................... 21 

3.2

  Lithography .................................................................................................................................... 21 

3.2.1  Electron Beam Lithography .............................................................................................. 22 

3.2.2  Optical Lithography ............................................................................................................. 23 

3.3

  Etching ............................................................................................................................................. 24 

3.3.1  Reactive Ion Etching of SiO

2

............................................................................................ 24 

3.3.2  Inductively Coupled Plasma Etching of InP/InGaAsP ............................................ 26 

3.3.3  Focussed Ion Beam Etching of InP/InGaAsP ............................................................. 27 

3.4

  Hydride Vapour Phase Epitaxy (HVPE) .............................................................................. 28 

3.5

  Scanning Electron Microscopy ................................................................................................ 29 

3.6

  Cathodoluminescence ................................................................................................................. 29 

3.7

  Photoluminescence ...................................................................................................................... 30 

3.8

  Transmission Electron Microscopy ........................................................................................ 31 

3.9

  Current-Voltage Measurements ............................................................................................... 32 

4

  Results and Discussion ....................................................................................................... 34 

4.1

  NELOG of InP on Silicon (Paper A) ..................................................................................... 34 

4.1.1  Optimisation of InGaAsP MQW growth (Paper A) .................................................. 38 

4.1.2  Microdisk resonators on NELOG InP on Si (Paper A) ............................................ 39 

4.1.3  Characterisation and Modal analysis of MDs on Sample D .................................. 40 

4.2

  Isolated large area ELOG InP on Si (Paper B, Paper C and Paper D) ....................... 41 

4.2.1  Optimisation of InGaAsP MQWs on isolated large areas of ELOG InP on Si 43 

(Paper B)

................................................................................................................................................ 43 

4.2.2  Microdisk resonators on isolated large areas of ELOG InP on Si ........................ 44 

4.2.3  Characterisation ..................................................................................................................... 45 

4.2.4  Electrical and Optical properties of unintentionally doped ELOG InP on Si .. 46 

4.2.5  Formation and Blocking the stacking faults in ELOG (Paper E) .................... 48 

Table of Contents

4.3

  Corrugated ELOG InP on Si for Photonics and Multi Junction Solar Cells (Paper F and Paper G)

............................................................................................................................................. 48 

4.3.1  Growth and characterisation results from CELOG experiments .......................... 51 

5

  Summary and conclusions ................................................................................................ 55 

6

  Future Outlook .................................................................................................................... 58 

7

  Summary of appended papers ......................................................................................... 59 

1

Introduction

1

Introduction

This thesis aims to provide an integrated versatile platform of III-Vs with silicon to address futuristic optoelectronics and photovoltaic applications. Silicon is undoubtedly the most versatile semiconducting material that has contributed considerably to revolutionise the modern society. From outshining the first transistors made out of germanium [1] to monopolising the present day complementary metal oxide semiconductor (CMOS) industry, silicon has come a long way. Data generation and processing by transistors based on silicon has grown from 4-bit (0.7 MHz) processors to 64-bit (3.9 GHz) processors [2]. Parallel to this, developments in the field of optical fibers have also come a long way since its first demonstration in 1966 [3]. Both of these pioneering inventions led to Nobel Prizes in physics to Jack St. Clair Kilby in year 2000 for making the first integrated circuit (1958) [4] and to

Charles Kuen Kao in 2009 for his pioneering work on optical fibers [5]. While advances in electronics industry are attributed to the technological advances in material processing and lithographic techniques, success of optical fibers should be attributed to the invention of semiconductor lasers based on GaAs junction in 1962 [6]. As silicon cannot generate the light needed for optical communication, it was only after the invention of the semiconductor laser that compact light sources were available for transmission of light signals through optical fibers over long distances. Even over half a century has passed since the introduction of silicon for integrated circuits, silicon still remains as the material of choice for electronics but

III-V semiconductors have become the materials of choice for light sources. These materials for lasers have come a long way from bulk GaAs layers to InGaAsP quantum wells grown on

InP substrates. These developments also resulted in other needful devices for optical communication: thus first InGaAs based photodetector was proposed [7]. A new field called photonics emerged, which deals with the generation, manipulation and detection of photons.

Integration of lasers and photodetectors spurred the development of a complete optical communication system. In this system an electrical signal is used to drive a laser to generate an equivalent optical signal (transmitter) that is transmitted over a long distance (~ 100 km) over an optical fiber cable and received by a photodetector (receiver) that converts it back into an electrical signal. All of these components, like silicon based electronics, glass based optical fiber and InP based lasers and detectors, have matured and are sold commercially today.

However, the ultrafast data generation and its ultrafast communication over long distances is still restricted by the copper based electrical interconnects that exists in an electronic circuit.

This “interconnect bottleneck” can be overcome by using optical interconnects instead of electrical ones. In this system, data communication inside an electronic chip can be carried out by “optical wires” made of silicon, which even though cannot produce light can guide it very efficiently. But this requires calculated positioning of ultra-small lasers on an electronic chip to feed in data (in form of photons) to the “optical wires” made of silicon. We call these

“optical wires” as optical waveguides.

Technological advances in silicon based electronics and III-V based photonics have opened the door of an innovative integrated platform of these two. Such an integrated platform is eagerly anticipated by industries for over a decade which would help in the realisation of futuristic optoelectronic integrated circuits. This in turn would facilitate

Introduction resolving the issues like interconnect bottleneck and high power consuming components.

Benefits of this integrated platform can be extended to energy efficient multi junction solar cells as well. An increasing trend towards achieving a more sustainable society has pushed the research in both industry and academia to provide this integrated platform. Different approaches to achieve this integration spans from direct epitaxial growth of III-Vs on Si to bonding of III-Vs on Si [8] [9] [10] [11]. Lasers [12], photodetector [13], modulators and almost complete optical systems have been demonstrated using bonding techniques [14].

However, despite the feasibility provided by attractive bonding techniques to integrate III-Vs with Si, any such solution struggles to find its implementation in industry due to different reasons like increased costs, lower yields, higher thermal budget and unequal substrate sizes of III-Vs and silicon. In contrast to bonding approaches a truly monolithic integration solution achieved via epitaxial methods is the most sustainable one.

1.1

Heterogeneous bonding of InP on Si

Different approaches available for bonding of III-Vs on Si can primarily be distinguished between molecular and adhesive. As the name suggests both of these techniques are used to bond either full wafers [15] or individual dies of III-Vs on pre-processed silicon on insulator (SOI) wafers [16]. Fabrication of light emitting devices on these III-V wafers or dies on SOI are done afterwards. Some groups have shown bonding of already fabricated devices on SOI as well [17].

In molecular bonding the phenomenon of van der Waal attractions is exploited between two even surfaces i.e. attraction between atomic and molecular electric dipoles with opposite charge. But as it is clear from its description, smooth surfaces with clean interfaces are indispensable and any contamination on the wafer surfaces is undesirable. In this approach first the wafer surfaces are polished using chemical mechanical polishing, in the second step they are cleaned and in the third step the surfaces to be bonded are activated. When these activated surfaces are brought in close contact with each other the molecular bonding process begins from the center of the two surfaces and subsequently the bonding wave spreads across the wafer [18]. After this the two bonded wafers are annealed at high temperature to strengthen the molecular bond between them.

In the adhesive bonding approach, surface of the primary wafer (wafer on which another wafer is bonded) is first coated with an adhesive polymer at room temperature also known as surface wetting. In the second step, the wafer to be bonded is placed on the top and an adhesive bond is created across the interface. And in the third and the final step of annealing at a high temperature, cross-linking between the molecules of the polymer takes place to strengthen the bonding interface. While looking at these two bonding approaches, it is evident that the molecular bonding puts more stringent demands on bonding process than the adhesive bonding. However, introduction of adhesive polymers to CMOS fab is still considered an issue to be resolved. Both the techniques have their advantages and disadvantages, and have proven their merits via numerous device demonstrations.

2

3

Introduction

1.2

Heteroepitaxial solutions for InP on Si

Heteroepitaxial solutions have been proposed long before bonding solutions. In the initial experiments on the direct growth of InP on Si [19] [20] highly defective material was obtained. Later, improved material quality was achieved by doing surface cleaning [21], lowtemperature growth [22], and growth with alternate annealing steps [23]. Nevertheless, these heteroepitaxial layers were not found suitable for device fabrication. Direct epitaxial techniques focus on the elimination of defects caused due to lattice and thermal expansion mismatch between InP and Si either by growing very thick layers or by growing very thin strained layers with miniscule lattice mismatch to reach the desired material [24]. An alternative approach called Epitaxial Lateral Overgrowth (ELOG), also the primary focus of this thesis work, tries to avoid the propagation of these defects into the III-V epitaxial layer.

To do so, growth through a selective area is performed to reduce the defects beneath a thin film of a dielectric material. The technique relies on the reduced probability for a defect to travel through these selected openings. However, such experiments in past have not been able to remove all the defects completely [25] [26] due to the defect propagation in the openings.

However, excellent findings by Fitzgerald et al. have shown that blocking of these defects can be done even in the openings defined in a thick film of the dielectric material [27]. ELOG technique has matured a lot from obtaining defective layers [28] to completely defect free layers of InP on Si [29]. This thesis proposes to use this method as a platform for electronicsphotonics integration. Fig. 1 shows a schematic depicting an integrated platform of Si based

CMOS with InP based photonics defined on ELOG technique. InGaN based lasers have been demonstrated using ELOG technique [30], however a device based on InP material system is yet to be demonstrated. In this thesis work, for the first time optically pumped microdisk resonators are fabricated on ELOG InP that has shown promising optical resonances.

Figure1. Schematic of an integrated platform of III-Vs based photonic with Si based CMOS designed on ELOG technology (not to scale): the layer “Box” is the buried oxide.

Apart from its application for silicon photonics there is an increased interest in realisation of III-V based multi junction solar cells on cheap substrates like Si. To achieve this

Introduction a direct heterointerface without an intermediate layer between III-Vs and silicon is required.

As it is evident many epitaxial methods have failed to deliver direct heterointerface between high quality III-Vs and Si, whereas bonding approaches are too expensive to commercially realise such a platform. Nevertheless, metamorphic growth of GaAsP solar cell structures on

GaP on Si has shown promising results [31]. To achieve such layer structures we modified the conventional ELOG process into a corrugated ELOG (CELOG) process, which enables the formation of direct heterointerface between III-Vs and Si with reduced defect densities than before. The CELOG process is closely related to the earlier proposed conformal growth of InP on Si [32]. In the conformal growth, selective area growth (SAG) is conducted from the sidewalls of the seed layer mesa, whereas in the proposed CELOG process growth is conducted from the top of the seed layer mesa and the growth is directed downwards to the silicon surface. In both the techniques III-V film growth extends laterally while making an abrupt interface with Si with reduced defect densities.

1.3

Goals and Achievements of this thesis

The primary goal of thesis work is to obtain high quality InP on Si for photonic integration and photovoltaic applications. To this end, we intend to optimise and exploit the

ELOG technique to make the ELOG InP layer defect-free as much as possible through technological improvements and theoretical understanding. Different experimental parameters were optimised to improve the overall fabrication and growth processes to obtain superior material quality. Different pattern designs were optimised with their fabrication spanning from electron beam lithography to optical lithography to achieve large areas of dislocation free ELOG InP on Si. Growth and fabrication of InP/InGaAsP based resonators were also done.

In addition, efforts were made to obtain a direct heterointerface between InP and Si via

CELOG. Studies on the electrical quality of the interface between InP and Si were also conducted. The CELOG is a generic technique and can be used for other kind of III-Vs

(GaAs, GaInP, GaAsP) as well. This will be useful to obtain epitaxially grown III-V based multi-junction solar cells on Si.

The major achievements of this thesis work can be listed as follows

 Growth of large enough areas of uncoalesced high quality ELOG InP on Si for photonic integration.

 Growth of highly uniform multi quantum wells (MQWs) with clean interfaces on

ELOG InP on Si.

 First time demonstration of strong emission from microdisk resonators fabricated on

MQWs grown on ELOG InP on Si.

 First time carrier transport studies on the coalesced ELOG InP on Si.

 Demonstration of abrupt heterointerface between InP and Si with reduced defect densities using CELOG.

4

5

Introduction

1.4

Thesis Outline

This thesis is organised as follows:

After this introductory chapter, Chapter 2 gives a theoretical background of the concepts that are necessary to obtain good quality material of InP on Si via ELOG and

CELOG. Propagation and blocking of defects in these processes are dealt with. It is explained how the ELOG method can be exploited for silicon photonics. Method to show how CELOG is useful for the formation of high efficiency and cost effective III-V based multi-junction solar cells on silicon is also presented.

Chapter 3 provides brief introduction to various experimental techniques used in this thesis by exemplifying certain process optimisation.

Chapter 4 discusses the results achieved tracking the efforts to obtain high quality layers of InP on silicon in a versatile manner to address a variety of applications.

 First section deals with ELOG optimisation through multiple nano-sized openings to obtain large enough areas for the growth of InGaAsP laser structures on them.

Characterisation results from microdisk resonators fabricated on them have shown the presence of whispering gallery modes. However, certain findings revealed the formation of defects due to coalescence of parallel growth fronts that can lead to malfunctioning of the devices.

 Second section presents ELOG optimisation through isolated micron-sized openings to achieve almost defect free isolated large areas of ELOG InP, this also helped in ruling out the defects caused due to coalescence. This is followed by the successful growth of highly uniform multi quantum wells across these layers. Promising results obtained from the device characterisation (optical pumping) of microdisk resonators fabricated on these layers are presented next.

 In the third and final section the new method of CELOG is explained. After the growth optimisation experiments an abrupt interface between InP and Si covering a large area with reduced defects is shown. The high quality of the InP and Si interface is supported by measurement of tunnelling current across the junction.

Chapter 5 presents the summary of this thesis work and chapter 6 gives the future outlook.

Summary of the appended papers are given in chapter 7

References

[1] "The Nobel Prize in Physics 1956".

Nobelprize.org.

Nobel Media AB 2014. Web. 31 Aug 2014. http://www.nobelprize.org/nobel_prizes/physics/laureates/1956>. (2014-09-01)

[2] http://www.intel.com/content/www/us/en/history/museum-story-of-intel-4004.html (2014-09-01)

[3] M Börner, “Electro-Optical Transmission System Utilizing Lasers”, US Patent 3845293 (A), 1966.

Introduction

[4] "The Nobel Prize in Physics 2000". Nobelprize.org. Nobel Media AB 2014. Web. 1 Sep 2014.

<http://www.nobelprize.org/nobel_prizes/physics/laureates/2000> (2014-09-01).

[5] "The Nobel Prize in Physics 2009". Nobelprize.org. Nobel Media AB 2014. Web. 1 Sep 2014.

<http://www.nobelprize.org/nobel_prizes/physics/laureates/2009/kao-facts.html> (2014-09-01).

[6] R. N. Hall, G. E. Fenner, J. D. Kingsley, T. J. Soltys, and R. O. Carlson, ” Coherent Light Emission From

GaAs Junctions”, Physical Review Letters, Volume 9, Number 9, 1962.

[7] T. P. Pearsall and M. Papuchon,” The Ga0.47In0.53As homojunction photodiode—A new avalanche photodetector in the near infrared between 1.0 and 1.6 m”, Applied Physics Letters 33, 640, 1978.

[8] T. E. Crumbaker, H. Y. Lee, M. J. Hafich and G. Y. Robinson,” Growth of InP on Si substrates by molecular beam epitaxy”, Appl. Phys. Lett. 54, 140, 1989.

[9] Masahiro Akiyama, Yoshihiro Kawarada,Takashi Ueda, Seiji Nishi, Katsuzo Kaminishi, ” Growth of high quality GaAs layers on Si substrates by MOCVD”, Journal of Crystal Growth, Volume 77, Issues 1–3, 1986.

[10] Y. Okuno, K. Uomi, M. Aoki, and T. Tsuchiya, “Direct Wafer Bonding of III–V Compound

Semiconductors for Free-Material and Free-Orientation Integration”, IEEE Journal Of Quantum Electronics,

VOL. 33, NO. 6, 1997.

[11] G. Roelkens 1 ; D. Van Thourhout 1 ; R. Baets, “Ultra-thin benzocyclobutene bonding of III–V dies onto

SOI substrate”, Electronics Letters, Volume 41, Issue 9, 2005.

[12] H. Park, A. W. Fang, S. Kodama, and J. E. Bowers,” Hybrid silicon evanescent laser fabricated with a silicon waveguide and III-V offset quantum wells”, Optics Express, Vol. 13, Issue 23, 2005.

[13] G. Roelkens, J. Brouckaert, D. Taillaert, P. Dumon, W. Bogaerts, D. V. Thourhout, R. Baets, R. Nötzel, and

M. Smit,” Integration of InP/InGaAsP photodetectors onto silicon-on-insulator waveguide circuits,” Optics

Express, Vol. 13, Issue 25, 2005

[14] N. Dupuis et al.,” 30Gbps Optical Link Utilizing Heterogeneously Integrated III-V/Si Photonics and CMOS

Circuits”, Optical Fiber Communication Conference San Francisco, California United States March 9-13, 2014.

[15] D. Pasquariello and K. Hjort,” Plasma-Assisted InP-to-Si Low Temperature Wafer Bonding”, IEEE Journal

On Selected Topics In Quantum Electronics, Vol. 8, No. 1, 2002.

[16] G. Roelkens et al, “III-V/Si photonics by die-to-wafer bonding”, materials today, Vol 10, Issues 7–8, 2007.

[17] H. Yang et al., “Tranfer-printed stacked nanomembranes on silicon”, Nature Photonics 6, 615–620, 2012.

[18] Q.-Y. Tong, U. Gösele,” SemiConductor Wafer Bonding: Science and Technology”, ISBN: 978-0-471-

57481-1, 1998.

[19] M. K. Lee, D. S. Wuu, and H. H. Tung, “Heteroepitaxial growth of InP directly on Si by low pressure metalorganic chemical vapor deposition,” Appl. Phys. Lett., vol. 50, 1987.

[20] M. Razeghi, M. Defour, R. Blondeau, F. Omnes, P. Maure, andO.Acher, “First CW operation of a Ga0.25

In0.75 As0.5 P0.5 InP laser on a silicon substrate,” Appl. Phys. Lett., vol. 53, 1988.

[21] Y. Ababou, R. A. Masut, A. Yelon1 andS. Poulin,” Low temperature heteroepitaxy of InP on Si(111) substrates treated with buffered HF solution”, Appl. Phys.Lett. 66, 1995

[22] C. A. Tran, R. A. Masut, P. Cova, J. L. Brebner and R. Leonelli,” Growth and characterization of InP on silicon by MOCVD”, J. Cryst. Growth 121, 1992.

[23] Y. Ababou et al.,” Structural and optical characterization of InP grown on Si(111) by metalorganic vapor phase epitaxy using thermal cycle growth”, J. Appl. Phys. 80, 1996.

6

7

[24] K. Samonji,” Reduction of threading dislocation density in InP-on-Si heteroepitaxy with strained short

‐ period superlattices”, Appl. Phys. Lett. 69, 1996.

[25] Y. S. Chang, S. Naritsuka, T. Nishinaga, “Optimization of growth condition for wide dislocation-free

GaAs on Si substrate by microchannel epitaxy”, Journal of Crystal Growth 192, 18-22, 1998.

[26] F. Olsson, M. Xie, S. Lourdudoss, I. Prieto, and P. A. Postigo, “Epitaxial lateral overgrowth of InP on Si from nano-openings - Theoretical and experimental indication for defect filtering throughout the grown layer”, J.

Appl. Phys. 104, 093112, 2008.

[27] E. A. Fitzgerald and Naresh Chand, “Epitaxial Necking in GaAs Grown on Pre-patterned Si Substrates”,

Journal of Electronic Materials, Vol. 20, No. 10, 1991.

[28] P. Vohl, C. O. Bozler, R. W. McClelland. A. Chu and A. J. Strauss, “Lateral Growth Of Single-Crystal Inp

Over Dielectric Films By Orientation-Dependent Vpe”, Journal ot Crystal Growth 56, 4l U 422, 1982.

[29] G. Wang et al,” Growth of high quality InP layers in STI trenches on miscut Si (0 0 1) substrates”, J.

Crystal Growth 315, 2011.

[30] S. Nakamura,” InGaN/GaN/AlGaN-based laser diodes with modulation-doped strained-layer superlattices grown on an epitaxially laterally overgrown GaN substrate”, Appl. Phys. Lett. 72, 1998.

[31] J. R. Lang, J. Faucher, S. Tomasulo, K. N. Yaung and M. L. Lee,”Comparison of GaAsP solar cells on GaP and GaP/Si,” Appl. Phys. Lett. 103, 2013.

[32] O. Parillaud, E. G. Lafon, B. Gérard, P. Etienne and D. Pribat,” High quality InP on Si by conformal growth”, Appl. Phys. Lett. 68, 1996.

Theoretical Background

8

2

Theoretical Background

The importance and the need of an integrated platform consisting of III-Vs and Si, to achieve an enhanced material system combining the optical and electrical properties of both was briefly introduced in chapter 1. However, the big difference in lattice and thermal properties between the two makes this integration difficult. In this chapter certain fundamental material issues pertaining to this integration, like generation of defects, their propagation and how they can be prevented will be discussed. The focus will be on the defects in InP, as the relevance of InP in such an integration is very important due to favourable wavelengths for communication possible with InP and its related alloys. Next the ELOG and the newly developed CELOG technique that are used in this thesis to integrate III-Vs with silicon will be discussed. The advantages of these techniques are also indicated.

2.1

Crystallographic defects

Crystallographic defects, as the name suggests are defects in crystals. In any crystal any variance in the regular arrangements of the atoms is a defect. Formation of defects is primarily caused due to thermodynamical reasons: these are formed because a defective crystal has a lower energy than a perfect crystal. The discussion on the defects will be confined to face centered cubic (FCC) system as the two material systems (InP and Si) used in this thesis work have the FCC Bravais lattice. However, references from simple cubic system are also used to explain certain defect geometries in a simpler manner. Silicon has the diamond structure whereas InP has the zinc-blende structure, in which unlike in the diamond structure of silicon the nearest neighbour is a different atom.

To understand the plastic deformation of a crystal under stressed conditions, the concept of slip plane and Burgers vector is necessary. Slip plane is the plane on which the movement of defects takes place. Burgers vector represents the magnitude and direction of the movement of the defect line (line demarcating the perfect and the imperfect parts of the crystal).

Crystallographic defects can primarily be divided into three types, 0-D or (point defects), 1-D (linear defects) and 2-D (planar defects). Zero dimensional or 0-D defects are caused by absence or presence of an atom at a place other than its specific lattice position.

Vacancies, interstitials (self or impurity) and substitution (impurity) are the 0-D defects that can occur in a crystal. Fig. 1 shows the 0-D defects in a crystal.

9

Theoretical Background

Fig. 1. Schematic showing different kinds of 0-D defects in a crystal

1-D defects on the other hand are formed when a group or chain of atoms is displaced from their regular position. A dislocation is the example of a 1-D defect; dislocations are further classified into edge and screw dislocations according to their movement in the crystal, mixture or hybrid of these two results in other forms of dislocations like misfit and its concomitant 2-threading dislocations and 60° dislocation. When the angle between the

Burgers vector and the line vector of the dislocation is 90 degrees it is called an edge dislocation.

The upper image of Fig. 2 shows the slip plane and the edge dislocation (represented by ┬) in a cubic system. The slip plane is the plane on which the movement of dislocation takes place. In the lower images one can see the breaking and formation of bonds resulting in the displacement of the edge dislocation (to the right) which ultimately amounts to shifting of the bottom half cell along the slip plane. It is clear that during the movement of an edge dislocation only one bond is broken at a time. In the case of a screw dislocation the angle between the Burgers vector and the line vector of the dislocation is zero degrees.

Theoretical Background

10

Fig. 2. Schematics showing the movement of an edge dislocation in a cubic crystal, the upper image shows the slip plane and the lower images show the movement of the dislocation

2-D defects are formed when there is a change in the regular sequence or order of the atoms in a crystal. Stacking faults, twin boundaries, and anti-phase domains (APDs) are the examples of planar defects in the single crystalline materials. An additional kind of planar defect called grain boundary exists in polycrystalline materials. In our study stacking faults and anti-phase boundaries are common and hence are described here. A stacking fault in a normal FCC lattice where the normal stacking sequence is ABCABC…ABC is caused by insertion of an extra plane for example ABCABCA C B…ABC. Fig. 3 shows the formation of stacking fault in an FCC crystal.

11

Theoretical Background

Fig. 3. Normal stacking sequence in FCC crystals (left), and formation of a stacking fault

(right).

Another kind of defect that comes into existence during the growth of polar materials over non-polar substrates is called Anti-phase domains (APDs). As the name suggests APDs are formed when two atoms different in phase with each other makes a bond. It is clear this kind of defect can only exist in materials with different atoms. Probability of finding this defect is higher if monoatomic steps are existing on the substrate. To overcome APDs, substrates with diatomic (or even number of atomic steps) are used. With the use of a wafer with diatomic steps, the formation of APDs can be avoided. Fig. 4 shows the formation of

APDs while growing a diatomic (binary) material (InP, GaAs, GaP etc.) on a monoatomic material (Si) and their self-annihilation after certain critical thickness. It is for this reason that in our experiments of heteroepitaxy InP on Si we always use silicon substrates provided with multiples of diatomic steps.

Fig. 4. Formation and annihilation of APDs on monoatomic surfaces.

2.1.1 Defects in InP grown on Si

InP has a lattice constant of 5.869 Å and Si has a lattice constant of 5.431 Å at 300 K

[1] that results in a lattice mismatch of around 8%. Also there is ~50% difference in the coefficient of thermal expansion of InP (4.7 ppm/°C) and Si (2.6 ppm/°C) [2]. These two

Theoretical Background factors make epitaxial growth of one on the other quite challenging as it is susceptible to the formation of different types of defects described above. A transmission electron microscope

(TEM) image of such an epitaxially generated interface between InP and Si is shown in Fig.

5. Numerous efforts in the past have failed to grow a superior quality layer of InP on Si. In the following sections, methods to reduce these defects using ELOG technique are explained.

12

Fig. 5. TEM image showing the defects propagating at the interface between InP seed layer grown on Si

2.1.2 Defect reduction in InP on Si by using ELOG

Direct growth of InP on Si results in a layer with high defect density of order 10

9

/cm

2

.

To reduce this high number of defects ELOG initiated via SAG on a patterned substrate is used. With this technique a vast number of defects that are generated at the interface between

InP and Si are blocked by a dielectric mask, which prevents them from penetrating into the laterally grown InP layer on the mask. Fig. 6 shows schematics of the principle of ELOG via

SAG. However due to 1-D and 2-D geometries, certain defects like threading dislocations and stacking faults can climb up in the epitaxial layer. Nevertheless, researchers have studied the propagation of such defects and phenomenon like epitaxial necking or aspect ratio trapping

(ART) to block these defects has been proposed in past [3]. By orienting the line opening at a certain angle and keeping the mask thickness to twice the size of the opening for SAG, all threading dislocations can be blocked [3] [4]. Another kind of defect present in the heteroepitaxy of diatomic (binary) materials (III-Vs) on silicon results in the formation of

APDs. Any substrate no matter how flat, may still have atomic steps on it and in cases where the steps are monoatomic, which is the case with silicon, there is a high probability that group

III-III (In-In) or V-V (P-P) metallic bonds may form (see Fig. 4). To overcome this, the substrate surface should be provided with diatomic steps or multiples of diatomic steps. As explained earlier this geometry will help reduce the formation of APDs. Growth of III-Vs over Si (001) 6° off-oriented towards <111> have shown complete annihilation of APDs [5].

However, there has been growth optimization on direct metamorphic growth of GaP on exact

13

Theoretical Background

Si (001) leading to annihilation of APDs after a critical thickness of 50 nm [6]. Another recent work by researchers at IMEC has shown complete absence of APDs in InP grown on {111} surfaces defined on Si (100) wafers [7]. This work also demonstrated that all of the misfit strain in InP grown on silicon is accommodated by the formation of stacking faults instead

[7], because of lower stacking fault energy of InP [8].

Fig. 6. Schematics showing defect propagation through wide openings during SAG and defect penetration in the ELOG layer

2.1.3 Blocking the threading defects by using “Epitaxial Necking”

Different kinds of dislocations like edge, screw and mixed may form by lattice mismatch between two materials. All of these dislocations are blocked beneath the dielectric mask used for ELOG, except the threading dislocations. As explained earlier, a threading dislocation may arise from the two edges of a misfit dislocation. These two threads must reach the surface of the epitaxial layer to terminate so as to reach the lowest possible energy state. A study done by Fitzgerald at el. [9] gave an excellent explanation about the propagation of threading dislocations in a system where a GaAs film was grown selectively from openings defined on silicon. The findings of their study explained that misfit dislocation in this system lies along [110] whereas its related threading segment makes an angle of 45° from (001) plane in <100> direction. This convention dictates that, since the angle between the threading segment and the crystal surface (001) is 45°, any thickness beyond the width of the epitaxial layer will be dislocation free. Thus by depositing a dielectric mask with a thickness equal to the size of the opening for SAG would stop all the threading dislocations within the opening. Nevertheless there are shortcomings in this process as well. In cases where two threading dislocations interact with each other in the opening it may result in diversion of the dislocation in other <110> directions. Even though, most of the threading dislocations will be blocked beneath the dielectric mask, there is a very small probability for such an event to occur during SAG. To counter the unexpected, the mask thickness can be doubled. This thesis work and researchers at IMEC have shown trapping of defects in such high aspect ratio openings. Fig. 7 presents schematics showing the propagation of a threading

Theoretical Background dislocation during ELOG process and its blocking by the mask sidewall known as aspect ratio trapping.

14

Fig. 7. Schematic showing the “epitaxial necking” of threading defects during the SAG process, resulting in completely dislocation free ELOG layer.

Even though selective area growth has solutions to block a majority of defects, blocking of stacking faults still remains to be completely resolved. In this thesis work we provide a model to block stacking faults by ELOG technique.

2.2

Application of III-Vs on Si in silicon photonics and multijunction photovoltaic

A monolithically integrated platform of III-Vs and silicon can open the doors for next generation photonics and photovoltaic. This thesis deals with these two primary applications of III-Vs on Si. Two different methods of SAG are used to deliver the desired integrated platform of III-Vs and Si. Already existing ELOG technique is modified to provide monolithic integration of III-V light sources on silicon. New growth technique CELOG is exemplified to address the realisation of next-generation solar cells based on III-V and Si mulitjunctions.

2.2.1 ELOG for III-V lasers on silicon photonics

Even though silicon has relatively mediocre electronic properties as a semiconductor when compared to other materials like InP, GaAs and their related materials, its abundance has established it as the material of choice for electronics. Silicon in combination with SiO

2 can be used as an efficient carrier of light produced by a laser. This has given birth to the field of silicon photonics, where silicon wires or waveguides carry the optical signals. Arrayed waveguide gratings based wavelength division multiplex [10], on-chip optical interconnects

[11] and numerous other applications based on passive silicon photonics have been proposed.

However, all such platforms rely on an active light source to provide optical signals to these silicon circuits. This puts an indispensable demand to provide ultra-small light sources for these networks of silicon waveguides.

Advances in passive silicon photonics lack a truly monolithic platform with light sources on silicon. Light sources for these complex passive photonic circuits have been

15

Theoretical Background provided by bonding techniques [12] [13], however the current demand is for sustainable monolithic solution. This thesis work gives a general approach that can provide strategically placed ultra-small light sources on a silicon photonic chip. In order to achieve this, the ELOG technique can be modified by transforming the dielectric mask that is used for defect filtering into a silicon waveguide buried in SiO

2

cladding. Evanescent coupling of the optical mode from the active region to silicon waveguide using bonding techniques have been demonstrated

[14]. Yang et al. have also shown evanescent coupling of the InGaAs/GaAs quantum dot lasers with hydrogenated amorphous silicon waveguides on silicon [15]. A simulation work done by Wang et al. demonstrated that the dielectric mask used in ELOG can be adapted into similar amorphous silicon waveguides buried in the dielectric mask, in which case the optical mode generated in the ELOG layer will be evanescently coupled to the amorphous silicon waveguide [16]. Fig. 8 shows a schematic depicting transformation of the dielectric mask used in the ELOG process into a silicon waveguide buried in SiO

2

mask.

Fig. 8. Regular ELOG mask converted into an a-Si waveguide buried in SiO

2

cladding layer and subsequent MQW growth for realization of monolithically integrated evanescently coupled laser.

2.2.2 CELOG for III-Vs and Si multijunction photovoltaic

Another important aspect that is addressed by this thesis work is the formation of direct heterointerface between III-Vs and Si with reduced defect densities. Formation of such an interface can simplify the growth of high efficiency III-V based multijunction solar cells on cheap silicon substrates. Connolly et al. give a very thorough introduction to the designing of III-V multijunction solar cells on silicon [17]. By growing thin layers of selectively chosen

III-Vs on Si a wider range of the sun’s spectrum can be covered, resulting in increased efficiency. However, such integrated platforms are not exploited completely as heteroepitaxy of materials with large mismatch results in defective layers. For example, a tandem solar cell with GaInP as the top cell, GaAs as the middle cell and Ge as the bottom cell can show 36% efficiency under concentrated sunlight. Similarly, a Si based solar cell under concentrated conditions can have up to 28% efficiency. A mixture of these two solar cells can reduce the need of expensive Ge substrate and inherit a higher efficiency than both. However, there is a

Theoretical Background trade-off between efficiency and cost-effectiveness. Thus an ideal multijunction solar cell platform should be advantageous if based on the naturally abundant silicon. Investigations done by Fitzgerald’s group at MIT have shown a theoretically ideal tandem solar cell with two cells, the lower one made with silicon at 1.1eV and the upper one made with GaAsP at

1.75 eV reaching an efficiency of 36.5%, highest for a two tandem solar cell [18]. An example of such a tandem solar cell is shown in Fig. 9 that will cover a very large range of the solar spectrum. In this design, the top cell consists of GaInP, with the middle cell of GaAs or

InGaAs and the third cell is made up of Si. Two tunnel junctions between each interface will facilitate efficient carrier transport. It will be a two terminal device and hence growth of layers to achieve current matching can be demanding. The device design shown in Fig. 9 is an artistic view and exact design of the layer structures for the final devices is still under investigation.

16

Fig. 9. Schematic of the proposed III-Vs and Si based multijunction solar cell designed on

CELOG platform, (Complete CELOG process is described in chapter 4)

2.2.3 CELOG for Silicon Photonics

CELOG provides the possibility of bringing III-Vs in close proximity of silicon. Apart from finding its application in III-Vs and silicon multijunction solar cell, CELOG platform can also be adapted to realise a monolithically integrated evanescently coupled III-V laser on silicon. In this scheme, the III-V seed layer mesas can be made on silicon on insulator (SOI) wafers, a common substrate type in electronics industry (see Fig. 10). After defining the silicon waveguide, the whole structure can be covered in a conformal manner with openings only at the top of the III-V seed layer mesa to facilitate SAG. As explained earlier, CELOG from this opening can make a close contact with the buried silicon waveguide. On top of the

CELOG layer, suitable multi quantum wells can be grown and these layers can be further processed into laser cavities. This is suggested as a future effort to this thesis work. This design is an extrapolation of the CELOG process for integrated photonics. Other processes like growth of active region, CMP of ELOG layer to increase the proximity between the active region and the silicon waveguide will need further optimisation.

17

Theoretical Background

Fig. 10. Schematic of the proposed monolithic III-V laser on Si platform based on CELOG technique.

References

[1] http://www.ioffe.ru/SVA/NSM/Semicond/ (2014-09-03).

[2] http://www.cleanroom.byu.edu/CTE_materials.phtml (2014-09-03).

[3] T. A. Langdo, C. W. Leitz, M. T. Currie, E. A. Fitzgerald, A. Lochtefeld, and D. A. Antoniadis, “High quality Ge on Si by epitaxial necking,” Appl. Phys. Lett., vol. 76, no. 25, pp. 3700–3702, 2000.

[4] G. Wang et al,” Growth of high quality InP layers in STI trenches on miscut Si (0 0 1) substrates”, J. Crystal

Growth, 315, 2011.

[5] G. Wang et al., “Selective Area Growth of InP in Shallow-Trench-Isolated

Structures on Off-Axis Si(001) Substrates”, Journal of The Electrochemical Society, 157, (11), H1023-H1028,

2010.

[6] K. Volz, A. Beyer, W. Witte, J. Ohlmann, I. Németh, B. Kunert, W. Stolz,” GaP-nucleation on exact Si

(0 0 1) substrates for III/V device integration”, Journal of Crystal Growth, Vol. 315, 2011.

[7] M. Paladugu, C. Merckling, R. Loo, O. Richard, H. Bender, J. Dekoster, W. Vandervorst, M. Caymax, and

M. Heyns,” Site Selective Integration of III–V Materials on Si for Nanoscale Logic and Photonic Devices”,

Crystal Growth & Design, 12 (10), 2012.

[8] Gottschalk, H., Patzer, G. & Alexander, H. compounds. Phys. Status Solidi A, 45, 1978.

[9] E. A. Fitzgerald and Naresh Chand, “Epitaxial Necking in GaAs Grown on Pre-patterned Si Substrates”,

Journal of Electronic Materials, Vol. 20, No. 10, 1991.

[10] P. Cheben, J. H. Schmid, A. Delâge, A. Densmore, S. Janz, B. Lamontagne, J. Lapointe, E. Post, P.

Waldron, and D.-X. Xu,” A high-resolution silicon-on-insulator arrayed waveguide grating microspectrometer with sub-micrometer aperture waveguides, Optics Express, Vol. 15, Issue 5, 2007.

[11] M. J. R. Heck, H.-W. Chen, A. W. Fang, B. R. Koch, D. Liang, H. Park, M. N. Sysak, J. E. Bowers,”

Hybrid Silicon Photonics for Optical Interconnects”, Journal of Selected Topics in Quantum

Electronics,

Volume:17 Issue:2, 2011.

[12] A. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers,” Electrically pumped hybrid

AlGaInAs-silicon evanescent laser”, Optics Express, Vol. 14, Issue 20, 2006.

[13] G. Roelkens, J. Brouckaert, D. Taillaert, P. Dumon, W. Bogaerts, D. V. Thourhout, R. Baets, R. Nötzel, and

M. Smit,” Integration of InP/InGaAsP photodetectors onto silicon-on-insulator waveguide circuits,” Optics

Theoretical Background

Express, Vol. 13, Issue 25, 2005.

[14] H. Park, A. W. Fang, S. Kodama, and J. E. Bowers,” Hybrid silicon evanescent laser fabricated with a silicon waveguide and III-V offset quantum wells”, Optics Express, Vol. 13, Issue 23, 2005.

[15] J. Yang and P. Bhattacharya, “Integration of epitaxially-grown InGaAs/GaAs quantum dot lasers with hydrogenated amorphous silicon waveguides on silicon,” Optics Express, vol. 16, no. 7, p. 5136, 2008.

[16] Z. Wang, C. Junesand, W. Metaferia, C. Hu, L. Wosinski, and S. Lourdudoss, “III–Vs on Si for photonic applications—A monolithic approach,” Mater. Sci. Eng. B, vol. 177, no. 1, pp. 1551–1557, 2011.

[17] J. P. Connolly, D. Mencaraglia, C. Renard and D. Bouchier,” Designing III–V multijunction solar cells on silicon”, Prog. Photovolt: Res. Appl., 22: 810–820,2014.

[18] http://sauvignon.mit.edu/fitz/ (2014-09-03).

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Experimental Techniques

3

Experimental Techniques

The primary goal of this thesis work was to obtain good quality InP material on silicon in order to establish a platform to monolithically integrate III-Vs with Si for integrated photonics and photovoltaic applications. This chapter describes briefly several experimental techniques, process optimisation and the involved characterisation techniques necessary to reach the goal.

As mentioned earlier, we primarily adopted ELOG and CELOG methods to obtain good quality InP on silicon. The experimental techniques that were developed for this purpose and those implemented for fabricating devices involved (i) chemical mechanical polishing of the seed layer and/or the dielectric mask, (ii) e-beam lithography and optical lithography and (iii) dry etching techniques such as reactive ion etching, inductively coupled plasma etching and focused ion beam etching. The growth was conducted in a Hydride Vapour Phase Epitaxy reactor. The techniques that were used to characterize the ELOG/CELOG layers and the devices made on them include Scanning Electron Microscopy (SEM), Cathodoluminescence

(CL), Photoluminescence (PL), Transmission Electron Microscopy (TEM) and currentvoltage (I-V) characterisation. All these were used to fabricate and study the surface morphology, optical and electrical properties to tailor the material quality or to study fabricated device structures. This chapter gives a brief description on each of the above mentioned techniques/processes.

3.1

Chemical Mechanical Polishing (CMP)

Chemical mechanical polishing is a planarisation process that is used to smoothen the surface morphology of semiconductors, dielectrics and metals used in integrated circuits. As the name implies CMP makes use of a chemically active slurry to react with the material while mechanical pressure is applied to physically remove the material. CMP is a standard process in the present day CMOS industry. In this thesis work CMP was used to planarise the non-uniform InP seed layer surface before patterns were defined. In some cases the SiO

2

mask layer was also subjected to CMP. Next sections give the detailed CMP process and its utility in the ELOG of InP on Si.

3.1.1 CMP of InP seed layer

All of our heteroepitaxial experiments started with a 4° off <110> Si (001) wafer precoated with InP seed layer grown using metal organic vapour phase epitaxy (MOVPE). As mentioned earlier, due to very high difference in lattice constants and thermal expansion coefficients, direct growth of InP on Si results not only in a defective layer but also a very rough/uneven surface morphology. Fig. 1a shows an atomic force microscope (AFM) image of the InP seed layer on Si, which had a root mean square (rms) roughness of around 20 nm

(scan area). Thickness of the InP seed layer was approximately 2 μm, with a high degree of crystallographic defects like stacking faults and dislocations. As explained earlier these defects can be blocked by ELOG, but uniform patterning of these samples was required.

However, bad surface morphology and topography of the seed layers made it impossible to generate uniform patterns across the wafer. This non-uniformity of the seed layer resulted in

Experimental Techniques non-uniform ELOG layer and irregular coalescence. To avoid these non-uniformities caused due to an uneven seed layer, CMP was used for polishing the seed layer. Due to its prevalent use in the CMOS industry, it was adopted during this thesis work as well. Two types of polishing schemes are employed i) polishing of the dielectric layer (SiO

2

) deposited to facilitate SAG and ii) polishing of the InP seed layer. The first choice was avoided during this work. Although the non-uniform SiO

2

surface was smoothened after CMP, the underlying InP seed layer still remained non-uniform [1]. Thus, in thesis work CMP of InP seed layer was optimised.

20

Fig. 1a. AFM scans of InP seed layer on Si, b) after 15 minute HVPE overgrowth

Prior to polishing of the InP seed layer, a relatively thick layer (4-5 μm) was overgrown on the InP seed layer in hydride vapour phase epitaxy (HVPE) reactor for 15 minutes. This thick layer was added in the process to facilitate thickness control during polishing. This overgrowth of InP over InP seed layer resulted in a layer with deteriorated surface morphology and topography. From the AFM scans (Fig. 1b) performed on this overgrown layer, it was found that in addition to the already existing surface roughness there was an increase in the surface topography of the InP seed layer as well. To counter this a twostep process was devised. In the first step, commercially available Al

2

O

3

based slurry was used to flatten the surface while in the second step, a freshly prepared citric acid (C

6

H

8

O

7

) plus sodium hypochlorite (NaClO) based solution was used to remove the surface roughness

[2]. Adopting these procedures, resulted in a 2 μm thick InP seed layer on Si with a rms roughness of less than 1 nm. Fig. 2a and 2b show the AFM scans after each polishing step.

The polished seed layer after step 2 shows a flat and smooth surface morphology. As it is visible in Fig. 2a,coarse polishing using Al

2

O

3

based polishing slurry introduced certain amount of scratches on the surface. However, these scratches were buffed away by polishing with citric acid and sodium hypochlorite based slurry, resulting in a very smooth surface morphology (see Fig. 2b).

21

Experimental Techniques

Fig. 2a. AFM scans of InP seed layer on Si after 1 min of coarse polishing and b) after 60 minutes of fine polishing

3.1.2 CMP of SiO

2

Monolithic integration of III-V sources with Si requires a platform through which the optical mode from the III-V light source is coupled to the underlying Si. This coupling is essential as the data transfer in optical interconnects will take place through the Si waveguide.

To achieve this platform, few factors like efficient coupling between the two and efficient mode confinement in Si waveguide are very important as demonstrated by Yang et al. [3]. To facilitate such a platform, experiments were performed to optimise the fabrication of this kind of structures. In these experiments, first a layer of SiO

2

(1 μm thick) was deposited on planar

Si wafer using plasma enhanced chemical vapour deposition (PECVD). Then a layer of (a-Si) amorphous silicon (1 μm thick) was deposited using PECVD that was subsequently patterned into 1.5 μm waveguide structures. Similar structure has been shown to have excellent mode confinement [4]. Subsequently, a thick layer of SiO

2

(5 μm) was deposited using PECVD to make a buried Si waveguide in SiO

2

structure. However, the last step of SiO

2

resulted in big bumps of SiO

2

as the deposition was close to conformal. CMP of SiO

2

was optimised to planarise the surface. Such a structure would be required to fabricate a monolithic evanescently coupled silicon laser (MECSL) [5]. Fig. 3 shows the cross-sectional SEM image of the planarised structure. Features in the SiO

2

mask next to the waveguide structure were caused due to the fracturing of the SiO

2

/Si structure during the cleaving process. This process can be replicated on the InP seed layer in order to fabricate the MECSL structure.

Fig. 3. SEM image of the cross-section showing a buried amorphous silicon waveguide in

SiO

2

cladding layer (mask). The inset is the magnified view of an a-silicon waveguide.

3.2

Lithography

Lithography is probably the most simple but most important technique that is widely used in the microelectronics and photonics industry. To conduct SAG, the substrate needs to be covered with a dielectric material and pattered using lithography. In this thesis work, lithographic processes using standard optical lithography and electron beam lithography

(EBL) were heavily used for pattern definition. These processes were optimised to achieve desired feature size with clearly defined uniform patterns.

Experimental Techniques

3.2.1 Electron Beam Lithography

EBL is a versatile technique that can be used to generate patterns of varying details in a flexible manner. It uses the electron beam to directly write on a particular resist a preprogrammed pattern and hence it avoids any mask as in some optical lithography systems. It can be used to generate ultra-small features (<100 nm). In our initial experiments, to achieve

ELOG through nano size openings, EBL was used for pattern definition. EBL system used in this thesis work is manufactured by Raith®™ GmbH. Fig. 4 shows a schematic of the commercially available EBL system. The EBL system has an integrated scanning electron microscope (SEM) for imaging and also contains a beam blanker along with a separate unit for pattern generation. Commercially available software, Raith 150, was used for the creation of the design files in .gds format. This software also provided the offline control to do the proximity corrections. Like any other lithography systems patterns were defined in a thin film of a polymer based photoresist. But unlike other optical lithography system where a photoresist film is exposed by photons, here the thin film is exposed to high energy electrons.

These electrons are provided by the inbuilt SEM to provide high precision at low acceleration voltages. The EBL tool is also equipped with a field emission electron source for pattern writing.

22

Fig. 4. Graphical representation of an EBL system [6]

EBL technique was used for pattern generation for nano-ELOG (NELOG) templates

(Paper A). To define openings in the SiO

2

hard mask, ZEP520A positive photoresist was used. InP on Si samples were first cleaned with acetone and isopropanol to remove any organic contamination. Photoresist was spun at a speed of 4000 rpm for 60 seconds resulting in a thin film with a thickness of 400 nm. Use of positive photoresist meant that the areas exposed to the electron beam could be washed away by the developer. After the spinning of the photoresist, a resist prebake step (180° C for 10 minutes) was used to evaporate any residual solvents. After that, another crucial step of exposure dose (i.e. the amount of electrical charge received by per unit area, given by μC/cm

2

) was optimised. Any divergence from the critical dose can result in either under exposure of the photoresist leading to non-

23

Experimental Techniques uniform pattern generation or an over dose that can result into features bigger than desired.

After optimising the exposure dose to attain the desired feature size, the samples were developed in p-xylene. The same process was repeated on different samples to generate template for NELOG. Once the pattern was realised on the photoresist film, it was transferred to the underlying SiO

2

mask using the reactive ion etching process explained in section 3.3.1.

Fig. 5 shows the SEM image of one such template used for NELOG experiments. Same procedure was also used to fabricate devices on NELOG InP on Si templates.

Fig. 5. SEM image of a template fabricated using EBL for NELOG of InP on Si

3.2.2 Optical Lithography

EBL is versatile in creating extremely small features but it is extremely time consuming. Hence for patterns of larger feature size on a large wafer, conventional optical lithography was used (Papers B, C and D). Unlike EBL, in this technique, a photolithography mask is used through which light from a broadband UV source passes through to replicate the pattern of the mask on a wafer coated with a photo sensitive resist . In this work (Papers B, C and D), a positive photoresist (SPR 700-1.2®) sensitive to UV wavelengths was used. Prior to the spinning of the photoresist, samples were cleaned using the same procedure as mentioned before to remove the organic contaminants. Photoresist was spun at a speed of 3000 rpm for 30 seconds to result in a thickness of around 1.2 μm after which the samples were pre baked at 100°C for 100 seconds and were exposed under the broadband UV source for 5 seconds. After the exposure the samples were developed in the commercially available developer solution CD-26 for 30 seconds that dissolves the photoresist from the exposed areas. Once the uniform pattern was defined on the samples, it was transferred to the SiO

2

mask by RIE (see 3.3.1).

Experimental Techniques

3.3

Etching

Etching was one of the heavily used experimental techniques in this thesis work.

Etching can primarily be divided into dry etching (anisotropic) and wet etching (isotropic). In this thesis work different kinds of dry etching techniques were optimised depending on the material type and pattern design.

3.3.1 Reactive Ion Etching of SiO

2

As already explained, ELOG of InP was facilitated by openings defined in a thin layer of SiO

2

mask. Only defining an opening was not sufficient, it was also critical that the sidewalls of these openings were smooth and vertical. This is desired to avoid irregular, nonvertical and rough sidewalls of the SiO

2

mask which can introduce additional defects in the overgrown material during the ELOG process. In addition, if the original surface on which

SiO

2

is deposited is not smooth, additional defects can be introduced during ELOG which demands surface polishing of the seed layer [1]. To obtain smooth and vertical sidewalls while maintaining a high mask thickness to opening aspect ratio (>2) was a challenging task.

Various methods of dry etching SiO

2

are present in the literature [7] [8], but due to our process sensitivity and to avoid the damage caused to the dielectric surface during the removal of the etch mask, photoresist was the obvious choice. Even though RIE of SiO

2

is a standard industry process, limited selectivity of photoresist during SiO

2

etching makes it harder especially when it is necessary to achieve deep trenches with smooth sidewalls [9] as in our case.

In this thesis work Plasmalab80Plus (Oxford RIE System®) was used for etching of

SiO

2

. The gas species are introduced from the top of the RIE chamber through a

“showerhead”. Both ion density and energy are controlled by a single radio frequency (RF) source. To avoid the re-deposition of the electrode material, a graphite plate is used as the substrate holder.

Initial experiments employed CHF

3

based chemistries that resulted in sidewalls with an inclination angle of around 10 degree in deeply etched trenches. Fig. 6 shows an image of the deep etched structures in SiO

2

using this recipe; as we can see in the inset, the sidewall of these trenches was not smooth. The time taken to etch a deep trench of 2μm in SiO

2

through an opening of 1 μm was 120 minutes. Another challenge during the SiO

2

deep etching was the generation and re-deposition of the polymer species on the sidewalls and the surface, which in turn reduced the etch rate.

24

25

Experimental Techniques

Fig. 6. SEM image of deep etched structures in SiO

2

mask deposited on Si using CHF

3

only

To overcome the generation of polymer and to reduce the etching time, additional argon (Ar) gas was used to take advantage of its sputtering (physical etching) behaviour. This certainly reduced the etching time to 90 minutes. However, vertical and smooth sidewall was still not obtained. Fig. 7 shows a cross-sectional image of the etching experiments done on

SiO

2

film on Si with the addition of Ar.

Fig. 7. Cross-sectional SEM image of deep etched structures in SiO

2

using Ar gas in RIE

Since addition of Ar did not improve the verticality of the etched features, as it is unreactive to the polymers formed during the etching process and is unable to remove them chemically, oxygen was introduced instead of argon. With the use of oxygen, the redeposition of polymer was minimised since the polymer reacted with the oxygen plasma and was vented out of the etching chamber. Addition of oxygen in the etching process undoubtedly reduced the selectivity of the polymer based photoresist film as well.

Nevertheless, by optimising the flow of the oxygen gas and baking of the resist, very smooth and almost vertical sidewalls were obtained. Fig. 8 shows a cross-sectional SEM of highly uniform deeply etched structures in SiO

2

deposited on Si.

Experimental Techniques

26

Fig. 8. Cross-sectional SEM image of deep etched structures in SiO

2

using O2 in RIE

3.3.2 Inductively Coupled Plasma Etching of InP/InGaAsP

After the ELOG of InP on Si and subsequent growth of multi quantum wells (MQWs) on it, the MQW structures were used for the definition of resonators. Major portion of this thesis work focussed on fabrication of microdisk (MD) resonators due to their small area and low power operation [10]. Oxford Instrument ICP380 Etch System® was used for dry etching of InP/InGaAsP materials system. The system contained independent Inductively Coupled

Plasma (ICP) and Radio Frequency (RF) generators to control density and energy of ions individually. A low process pressure up to 4 mTorr can be reached with both chemical and ion-induced etching. Different gases can be used in this system.

Choice of proper etch masks and etching gases is very important in this particular case. Due to operation at high ICP power, metal masks were easily etched away during the process due to very low selectivity. SiN x

was another choice of material. However, due to already available standard process of SiO

2

etching from previous experiments on dry etching of InP/InGaAsP based structures, SiO

2

mask was found to be most suitable. In the past, etching recipes using different gases like Cl

2

, Ar, CH

4

and H

2

have shown smooth and highly anisotropic etching of submicron InP nanopillar arrays [11]. Fig. 9 shows an example of the etched microdisk using the parameters given in [11]. However, in the SEM image we can see that the sidewalls of the MD were damaged due to sputtering of high energy ions from the sample surface to the sidewalls and formation of polymer is also visible on the sample surface.

27

Experimental Techniques

Fig. 9. SEM image of a fabricated MD on InP/InGaAsP MWQs on reference sample

During this thesis work, ICP etching was optimised for fabrication of MD resonators on ELOG InP on Si using a combination of Cl

2

, CH

4

and H

2

gases only. In this recipe physical etching component of Ar was removed. Removal of Ar gas from the etching chemistry and optimisation of other etching parameters like forward and reflected power resulted in a smooth and vertical sidewalls. Fig. 10 shows a SEM image of the MD resonators fabricated using these optimised parameters. Even though the sidewalls were almost vertical and smooth, atomic force microscopy analysis of the etched sidewalls revealed a high degree of roughness (~8 nm). It is likely etching of nanopillar arrays [11] is different from isolated structures such as MD resonators. This roughness is found to be disastrous for the MD resonators as it increased the scattering losses in the resonating cavity, that did not allow the efficient laser operation.

Fig. 10. SEM image of a MD fabricated using optimised ICP etching of InP/InGaAsP MQWs on reference sample

3.3.3 Focussed Ion Beam Etching of InP/InGaAsP

To overcome the roughness caused during the etching of InP/InGaAsP MD resonators using ICP, an alternative fabrication process was devised. This time, FIB fabrication process was optimised to achieve circular MDs with ultra-smooth sidewalls. Quanta 3D FEG tool was used for FIB processing manufactured by FEI company®. In this tool, gallium ion beam is used for milling of the InP/InGaAsP MD resonator structures. Different values of currents and voltages are available to tune the process to either reduce the etching time or to reduce the damage to the sample caused due to FIB. In the past FIB has been used for etching of

InP/InGaAsP based structures [12]. In this thesis work, a two-step approach is employed: in the first step, a high current (30 nA) with an acceleration voltage of 30 kV was used to define the big features and in the second step a lower value of current (1 nA) was used to polish the sidewalls of the MDs. This polishing step not only removed the irregularities in the features but also removed the damage caused to the material due to the FIB exposure. Fig. 11 shows

Experimental Techniques the SEM image of InP/InGaAsP MDs fabricated on NELOG InP on Si with 1 st

and 2 nd

FIB steps. MDs fabricated using this process have shown higher optical gain in our experiments.

28

Fig. 11. SEM image after 1 st

& 2 nd

FIB etching step of MD resonators on NELOG InP on Si

3.4

Hydride Vapour Phase Epitaxy (HVPE)

HVPE was the principal technique used for ELOG of InP on Si experiments. HVPE is a near equilibrium technique in which the growth is primarily driven by the mass input rate of the reactants. The dependence of growth rate on mass input rate results in really thick layers in very short time. The main reason for equilibrium nature of HVPE is attributed to the volatility of III-Chlorides species at operating temperatures [13]. This volatile nature of III-

Chloride species also makes it impossible for them to get adsorbed at dielectric surface thereby making this technique suitable for selective area growth. However, shift in HVPE’s equilibrium is caused by kinetic factors like phosphine or arsine decomposition [13]. Thus under different growth temperature regimes like low growth temperature (kinetically controlled regime) the growth rates on different crystallographic planes differ from each other and at high growth temperature (thermodynamically controlled regime) these do not differ

[14]. Hydride based vapour phase epitaxy is a technique where hydrides like phosphine and arsine are used, in contrast to halide based VPE where tri chloride of phosphorus or arsenic are used. In HVPE, a controlled flow of HCl over molten indium results in in-situ generation of InCl species (III-Chloride) and phosphine or arsine is supplied as a precursor for group V species (P or As). Chemical reactions taking place inside the HVPE reactor during the growth of InP are as follows:

In(l) + HCl(g) = InCl + ½H

2

(g)

InCl (g) + PH

3

(g)= InP (c) + HCl(g)+ H

2

(g)

It is assumed that at low pressures phosphine reacts with InCl without decomposition into P2 and P4.

HVPE is versatile in SAG compared to metal organic vapour phase epitaxy (MOVPE).

In the latter, the deposition of In radicals from trimethyl indium (TMI) on dielectric mask is irreversible but in HVPE, desorption of InCl from the mask due to its volatility guarantees its complete selectivity. Fig. 12 shows the image of the low pressure HVPE reactor at KTH used

29

Experimental Techniques during this thesis work. It has five temperature zones, inlet for HCl(g), PH3(g), H2S(g) (ntype sulphur doping), Zinc (p-type doping) and Ferrocene (iron doping for semi-insulating layers). Zinc and iron sources are provided through their respective metal organics.

Fig. 12. HVPE reactor at KTH

3.5

Scanning Electron Microscopy

Scanning electron microscopy (SEM) is a very useful imaging tool to study the uniformity of fabricated and grown structures. When it is provided with Energy dispersive Xray Spectroscopy (EDS), it can also be used for studying the chemical composition of the sample under investigation. This thesis made heavy use of SEM to study the quality of ELOG layers and devices fabricated on them thereafter. SEM is a technique where a high-energy electron beam is focussed on a specimen through a rectangular pattern to capture images.

After this, primary beam of electrons interacts with the specimen different kind of signals like secondary electrons, back scattered electrons, x-rays, luminescence and transmitted electrons are generated. A specific detector that can read the respective signal is then used to study the signal and generate an image. Secondary electron detectors are used for normal imaging in

SEM, back scattered electron detector are used to generate diffraction patterns formed by backscattered electrons to determine the crystal structure of the specimen, x-ray detectors are used for energy dispersive x-ray spectroscopy (EDS) to analyse chemical composition of the specimen and photodetector is used to read out the luminescence from the specimen to study the defects in the material. During this thesis work ULTRA FE-SEM manufactured by Carl

Zeiss NTS GmbH equipped with detectors for EDS was used.

3.6

Cathodoluminescence

As mentioned earlier luminescence from a sample can be read by the inbuilt photodetector in the SEM. This readout of the photon emission from the sample when exposed to the electron beam is called cathodoluminescence. This focused high energy electron beam excites the carriers to high energy states and their subsequent recombination results in photon emission. Thus on a specimen exposed to the high energy electron beam, radiative recombination centers yield bright contrast whereas non-radiative recombination centers result in dark contrast. In this thesis work, the CL measurements were done at the

Experimental Techniques

30 microscopy facility at Linköping University. This SEM setup has an inbuilt detector to read out wavelengths of our interest (covering ~ 920 nm for InP). The measurements were done using a mirror with a tiny slit, through which the electron beam is focused on the specimen.

Reflected light from the specimen is collected and read by the photodetector, which then creates an image with contrast (bright or dark) to show radiative and non-radiative sites respectively. CL measurements on ELOG InP showed bright contrast whereas any defects in the ELOG InP layers are shown by dark spots. The depth of the characterised material depends on the penetration depth of the electron, which is given as as [15].

d

Z

E

1

2

n

Where

d = penetration depth (Å)

A = Mass number

Z = Atomic number

ρ = Density

E = Energy of electrons (eV) and n is a variable dependent on Z as given by [15]:

1.2

n

Z

Thus by increasing the acceleration voltage of the setup the penetration depth can be increased to study the defects existing deep in the ELOG InP layer. For InP A is given by its molar mass and Z is given by calculation of effective atomic number of InP which is calculated to be 145.792 g/mol and ~45 respectively. Effective atomic number is calculated using the power law given by,

Z eff

m

f Z i i m

where the sum of electron fraction of all the elements is given by Σfi = 1 and m is equal to

2.94 given by Mayneord [16]

3.7

Photoluminescence

Photoluminescence is another technique that collects the emission made by the radiative recombination in a material to study the optical gain in a material. Any direct bandgap material that is exposed to photons of higher energy than the band gap, excitation of carriers from the valance band to conduction band takes place. These excited carriers however cannot stay in this state forever and falls back to the valence band by remitting the absorbed energy as photons (also known as spontaneous emission) after sometime known as carrier lifetime.

This emitted photon is of the same wavelength/energy as the bandgap of the material. It is this emitted photon that is collected by the measurement setup and read by the photodetector to give the gain spectrum of the material. This spectrum is called the PL-spectrum of the material reflecting its optical gain. During this thesis after every ELOG experiment optical properties of the material was studied using PL measurements. Depending upon the

31

Experimental Techniques investigation i.e. to study the optical gain of the material or to optically pump the fabricated laser structures three different PL setups were used in this thesis.

The first μ-PL setup was used to study the optical properties of the ELOG InP. The setup is equipped with an Ar laser (514 nm) for optical excitation that has a spot size of ~2-3

μm. The setup includes an objective with a numerical aperture (NA) of 0.45, a charged coupled device camera and a monochromator with an InGaAs detector cooled by liquid nitrogen. The optical excitation is done in continuous wave mode with an approximate excitation power of 100 μW. The setup is also equipped with an additional cryostat stage in case optical study of the material is to be carried out at low temperature. The same objective was used both for optical pumping and collection of the emission from the samples.

The second μ-PL setup was used for optical pumping of MD resonators fabricated on

MQWs grown on ELOG InP grown on Si through nano sized openings. In this setup an external laser diode emitting at a wavelength of 1.18 μm was used to for optical pumping of

MD resonators. The laser diode used can emit at two wavelengths of 800 nm and 1180 nm, however 1180 nm wavelength was chosen for optical pumping as the value is above the band gap energy of InP. The output power of the laser diode was approximately 20 mW measured before the objective. The measurements were done at room temperature with the laser diode operating in continuous mode.

The third μ-PL setup used a high power pulsed laser for optical pumping of MD resonators fabricate on isolated areas of ELOG InP on Si. Measurements were made at room temperature using a Nd:YAG (Neodymium doped yttrium aluminium garnet) nanosecond (ns) pulsed laser emitting at 1064 nm with a repetition rate of 321 Hz. The pulse width was 7 ns whose intensity was mitigated by a 50x objective with 0.6 NA. The spot size of the optical pump was adjustable and an InGaAs detector cooled by liquid nitrogen was used to read the optical emission from the MDs. To improve the signal to noise ratio the system used a lock-in amplifier to lock the signal below threshold. The same objective that was used for optical pumping also collects the emission from the MD resonators.

3.8

Transmission Electron Microscopy

Transmission electron microscopy was used to study the defect propagation, filtering and generation. Unlike other electron microscopy methods, in this technique the specimen needs to be really thin, so the electrons can transmit through the sample, that gives the name

Transmission electron microscopy. It is these transmitted electrons that are used to generate an image. These electrons in the thin slice of the specimen get diffracted like in a X-ray diffraction experiment and results in a diffraction pattern or a magnified image. The TEM used in this work is manufactured by JEOL consisting of a high-energy electron source, condenser lenses, objective, lenses to switch between the diffraction pattern and image and a sample holder. In this work, diffraction patterns were used to study the crystalline properties of the ELOG material and the interface between InP with other materials (Si, SiO

2

). Different crystallographic defects like anti phase domains, stacking faults and dislocation can be revealed in the magnified TEM image. Images taken from TEM were also used to study the defect blocking mechanism in the ELOG technique and how new defects were generated at

Experimental Techniques the point of coalescence. Fig. 13 shows a TEM image of the interface created between ELOG

InP with the SiO

2

mask used for SAG.

32

Fig. 13. TEM image showing the interface between ELOG InP and SiO

2

mask surface

3.9

Current-Voltage Measurements

Current-voltage (I-V) measurements were used to measure the tunnelling of the electrical charges across the abrupt junction of InP and Si formed using CELOG technique.

The measurement was performed on a standard 4-probe measurement setup, but only two of its probes were used to inject carriers from one to other through CELOG InP on Si. The tool can make semi-automatic measurements over an 8-inch wafer with temperature control over the thermal chuck ranging from -65° C to +200° C. The measurements were made at room temperature under dark conditions in manual mode, as dark I-V measurements are known to be more sensitive to series resistance, shunt resistance etc. The instrument was equipped with wafer mapping software, 2-medium power current voltage source measure units (SMU), 2high resolution SMU, 2-channel CV and 2-channel IV. Undoped and sulphur doped CELOG

InP on Si layers were used to study the Ohmic behaviour of the direct interface between

CELOG InP and Si. Electrical contacts were defined using standard lithography and metallisation process. Approximately 200 nm AuGe alloy was used as a contact material for both undoped and sulphur doped InP and around 600 nm Al was used for contacting backside of the Si substrate. The metal contacts were annealed using rapid thermal annealing at a temperature of 400° C for 1 min under nitrogen environment. Annealing step was required to achieve an Ohmic contact between metal and semiconductor. A voltage sweep of -1V to +1V was used to study the electrical conduction across the CELOG InP and Si junction. Since both

InP and Si were n-doped, when the sweep was reversed the I-V behaviour did not change drastically. From the I-V measurements an Ohmic behaviour was observed across the junction, which supported the absence of an intermediate amorphous layer.

33

Experimental Techniques

References

[1] C. Junesand, C. Hu, Z. Wang, W. Metaferia, P. Dagur, G. Pozina, L. Hultman and S. Lourdudoss, ”Effect of the surface morphology of seed and mask layers on InP grown on Si by epitaxial lateral overgrowth”, J.

Electron. Mater. 41 9, 2012.

[2] Y. Morisawa, I. Kikuma, N. Takayama, M. Takeuchi, “Mirror polishing of InP wafer surfaces with NaOClcitric acid”, Applied Surface Science, Volume 92, 2 February 1996.

[3] J. Yang and P. Bhattacharya, “Integration of epitaxially-grown InGaAs/GaAs quantum dot lasers with hydrogenated amorphous silicon waveguides on silicon,” Opt Exp., vol. 16, no. 7, p. 5136, 2008.

[4] A. W. Fang, E. Lively,Y-H. Kuo, D. Liang and J. E. Bowers, “A distributed feedback silicon evanescent laser”, Opt. Express 16, 4413–4419 (2008).

[5] Z. Wang, C. Junesand, W. Metaferia, C. Hu, L. Wosinski, and S. Lourdudoss, “III–Vs on Si for photonic applications—A monolithic approach,” Mater. Sci. Eng. B, vol. 177, no. 1, pp. 1551–1557, 2011.

[6] N. Shahid, “Technology and properties of InP-based photonic crystal structures and devices,” Doctoral

Thesis, KTH Royal Institute of Technology, ISBN: 978-91-7501-442-5, 2012.

[7] B. E. E. Kastenmeier, P. J. Matsuo, J. J. Beulens and G. S. Oehrlein,“Chemical dry etching of silicon nitride and silicon dioxide using CF4/O2/N2gas mixtures”, J. Vac. Sci. Technol. A 14, 2802, 1996.

[8] L. M. Ephrath, “Selective Etching of Silicon Dioxide Using Reactive Ion Etching with  CF4-H2”, J.

Electrochem. Soc., volume 126, issue 8, 1419-1421, 1979.

[9] H. K. Lee, K. S. Chung and J. S. Yu, “Selective Etching of Thick Si3N4, SiO

2

and Si by Using CF4/O2 and

C2F6 Gases with or without O2 or Ar Addition”, J. Korean Phys.Soc. 54,1816, 2009.

[10] J. Van Campenhout, P. Rojo-Romeo, P. Regreny, C. Seassal, D. Van Thourhout, S. Verstuyft, L. Di

Cioccio, J.-M. Fedeli, C. Lagahe and R. Baets, “Electrically pumped InP-based microdisk lasers integrated with a nanophotonic silicon-on-insulator waveguide circuit”, Opt. Express 15, 6744–6749, 2007.

[11] M. Y. Li, S. Naureen, N. Shahid, S. Anand, “Fabrication of Submicrometer InP Pillars by Colloidal

Lithography and Dry Etching”, Journal of The Electrochemical Society 157 (9), H896-H899, 2010.

[12] L. A. M. Barea, F. Vallini, A. R. Vaz, J. R. Mialichi, and N. C. Frateschi, ” Low-roughness active microdisk resonators fabricated by focused ion beam”, Journal of Vacuum Science & Technology B 27, 2979, 2009.

13] G. B. Stringfellow, “Fundamental aspects of vapor growth and epitaxy,” J. Cryst. Growth, vol 115, pp. 1–11,

1991.

[14] D. W. Shaw, “Mechanisms in vapor phase epitaxy,” in Crystal Growth, C. H. L. Goodman, Ed. New York:

Plenum, vol. 1, ch. 1, 1974.

[15] C. Feldman, “Range of 1

‐10 kev Electrons in Solids”, Physical Review, vol. 117, no. 2, pp. 455–459, 1960.

[16] W. Mayneord, “The significance of the Ro¨ntgen,” Acta—Unio Internationalis Contra Cancrum 2, 271–282

1937.

Results and Discussion

34

4

Results and Discussion

Epitaxial growth of III-Vs on alien substrates has seen its revival and is maturing over the years. Growth processes for one of the methods, ELOG, concentrated in this work, have been optimised using coalesced and uncoalesced layers to achieve large enough areas for potential device fabrication. Different phenomenon like ART and nano ELOG (NELOG) have been proposed to attain defect free material. In this work not only experimental verifications of these hypotheses are shown but also by incorporating the phenomenon of ART large enough areas of uncoalesced ELOG InP on Si with low defect throughout the layer, even above the opening has been achieved by making use of conventional optical lithography. In addition to this parallel efforts are made to create an atomically abrupt interface between InP and Si using

Corrugated ELOG (CELOG).

4.1

NELOG of InP on Silicon (Paper A)

ELOG is a technique where the propagating defects arising from the interface of InP and Si are primarily blocked by the dielectric mask. However, in the past when the ELOG technique was used, openings for ELOG were tens of micrometre wide [1]. Such wide openings did facilitate large area of low defect ELOG material on both sides of the opening, but due to the wide openings a huge amount of defects were able to propagate to the ELOG surface just above the opening [2]. These findings led researchers to opt for nano sized openings, which reduced the probability of defect propagation [3] based on the phenomenon of ART or necking effect proposed by Langdo et al. [4]. In this technique the mask thickness to opening width aspect ratio greater than 2 is maintained to block the movement of threading dislocations.

Following these principles in this thesis work experiments were designed for NELOG

(i.e., ELOG with nano sized openings). Experiments were initiated with four samples (A, B,

C, D) of InP seed layer on Si. The InP surface of each of these samples was subjected to chemical mechanical polishing (CMP) procedure explained earlier in chapter 3. On sample A, single and closely spaced double line openings were defined in 700 nm thick layer of SiO

2 using e-beam lithography and reactive ion etching process. The length of the openings was 50

μm with a width of approximately 300 nm, and the spacing between double openings was kept around 1 μm to achieve coalescence. Details of the mask design are shown in Fig. 1.

Openings were defined 30° off [110] to achieve higher lateral growth rate, as higher order planes are exposed [5].

35

Results and Discussion

Fig. 1. Schematic of the mask designed defined on sample A The opening width is 300 nm for both type of openings (single and double)

Growth of InP was conducted in LP-HVPE for 2 minutes with a V/III ratio of 8 at a temperature of 610° C. The ELOG InP layer was sulphur doped with a nominal concentration of 1x10

18

cm

-3

. Fig. 2 shows the SEM and AFM images of the sample A after 2 minutes of growth. A ratio of lateral to vertical growth rate (growth aspect ratio) of 3 is achieved. A smooth surface morphology is observed for the ELOG InP on Si indicated by a root mean square (rms) roughness of approximately 1 nm measured using AFM. Optical properties of these uncoalesced and coalesced ELOG InP/Si layers were studied using photoluminescence

(PL) and panchromatic cathodoluminescence (PC-CL) measurements.

Fig. 2. SEM image of the coalesced NELOG InP on Si from closely spaced (1 μm) nano sized double openings (300 nm) and its corresponding AFM scan.

Results and Discussion

The PL measurements showed an improvement in intensity for ELOG InP on Si compared to that from the InP seed layer on Si under similar excitation conditions. PL intensity from ELOG InP on Si was of the same order of magnitude to that of the InP reference grown along with it. This indeed supported the effective defect filtering mechanism in high aspect ratio openings defined for SAG. The corresponding CL analysis (Paper A) is supportive of the improved material quality as well. It was clearly observed that there were no defects in the uncoalesced layers while new defects could form due to the coalescence of two growth fronts. To further qualify the ELOG InP material quality, InGaAsP based multi quantum wells (MQWs) were grown on it (ELOG InP) using MOVPE, but tremendous loading effect was observed during MQW growth resulting in a drastic change of targeted well/barrier thicknesses and an extremely poor surface morphology.

NELOG experiments resulted in almost defect free isolated areas of ELOG InP on Si.

However, reduced region for selective area growth did introduce the need to incorporate multiple nano sized openings closely spaced with each other to achieve large areas of NELOG

InP on Si. These large areas of NELOG InP on Si would help to eliminate or minimize the loading effect during InGaAsP MQWs growth. Hence 10 nano sized (300 nm) closely spaced

(1 μm) wide openings were defined in 700 nm thick SiO

2

mask using the similar fabrication process as described above. Additionally, an InP seed window next to the multiple line openings was also exposed. This open area of InP seed would help minimising the loading effect (explained in section 4.2) during MQWs growth. We implemented this pattern design on Sample B which is depicted in Fig. 3.

36

Fig. 3. Schematic of the mask design defined on sample B

This time the ELOG InP was conducted with an increased V/III ratio from 8 to 10 and the growth time from 2 minutes to 2 minutes and 20 seconds, but the nominal sulphur doping and growth temperature were the same as before, i.e., 1x10

18

cm

-3

and 610° C, respectively.

Increasing the V/III ratio and the growth time resulted in a completely coalesced NELOG InP on Si layers with smooth surface morphology, as visible in the AFM scans shown in Fig. 4.

37

Results and Discussion

Fig. 4. AFM scan of coalesced NELOG InP on Si, sample B

However, when optical properties of these layers were studied using PL, a sharp contrast in quality was observed between NELOG InP/Si and planar InP reference grown along with it. One potential reason for the sharp decline in the PL intensity of NELOG InP on

Si is the intermixing of NELOG layer with the overgrowth from the adjacent open area of defective InP seed layer. To avoid such an intermixing, a new mask pattern was designed with additional SiO

2

barriers next to the area with multiple openings (Fig. 5). The length of the

SiO

2

barriers (50 μm) was kept smaller than the length of the openings (250 μm) to study the effect of intermixing of layers. Both samples C and D were prepared using this design (Fig.

5).

Fig. 5. Schematic of the mask designed defined on samples C and D

NELOG of sulphur doped InP was conducted for 2 minutes and 20 seconds at a growth temperature of 610 °C with a V/III ratio of 10. This resulted in a completely coalesced

NELOG of InP layer with smooth surface morphology. PL analysis of these NELOG layers at different points (1, 2 and 3) as shown in Fig. 6 revealed different PL intensities (Paper A).

Highest PL intensity was observed from the NELOG InP grown between the SiO

2

barriers

Results and Discussion

(point 1) with a decrease in the PL intensity as we move away from the barriers to point 2 where there was probable intermixing of NELOG InP with the overgrown InP seed layer. The lowest PL intensity was observed at point 3, where the direct overgrowth on InP seed layer had taken place. These results were also supported by the quality of the subsequent MQWs growth on these completely coalesced layers of NELOG InP on Si, as will be explained in the next section.

38

Fig. 6. SEM image of the NELOG InP on Si from mask design on sample C and D

4.1.1 Optimisation of InGaAsP MQW growth (Paper A)

Loading effect during the SAG on the patterned samples is the phenomenon leading to enhanced growth rate in the open areas caused by unadsorbed excess growth species on the dielectric surface. If these excess growth species are volatile, these will continue to diffuse towards the area where they can nucleate and hence higher growth rate with respect to the unpatterned samples. If not optimised this uncontrolled diffusion of growth species towards open area could result in undesired material thicknesses. In some cases, especially in the case of selective area growth of MQWs, it can result in bad surface morphology and rough interface between the quantum wells and the barriers.

Growth of MQWs on NELOG InP on Si on sample A is a good example of enhanced loading effect as a result of a largely reduced area for SAG (Paper A). On sample B the exposed InP seed window next to the openings helped in reduction of loading effect during the MQW growth. However, the intermixing of the NELOG InP layer with the overgrown InP seed layer did introduce unwarranted defects in the NELOG InP. Similar experiments on sample C resulted in a superior material quality between the SiO

2

barriers, which was again

39

Results and Discussion supported by the PL measurements of MQWs on this template. Five InP/InGaAsP based

MQWs emitting at a wavelength of 1542 nm were deposited using MOVPE with a 200 nm

InP cap layer. Following these conclusions, a new InGaAsP based MQW structure with separate confinement heterostructure (SCH) was designed. SCH layers were introduced in the design for better optical mode confinement in the MQW region. Table 1 gives the detailed layer structure of the new design with SCH layers. This new design was used during the

MOVPE growth of MQWs on sample D. PL measurements on these MQWs gave similar results like sample C, with diminution in PL intensity as we move away from point 1 to points

2 and 3 (see Fig. 6) PL peak intensities of MQWs grown on NELOG InP layer between the

SiO

2

barrier were reaching up to 85 % to those of MQWs on planar reference sample.

Layer Number

ELOG InP on Si

Material n-InP

Thickness Doping (cm

-3

) Details

2x10

18

2, 10 In

0.78

GaAs

0.48

P 120 SCH

3,5,7, 9

4, 6, 8

In

0.48

GaAs

0.83

P 7

In

0.76

GaAs

0.83

Table1. Layer structure for MQWs grown on sample D using MOVPE

4.1.2 Microdisk resonators on NELOG InP on Si (Paper A)

Stimulated by the superior material quality of the MQWs grown on NELOG InP/Si, these templates were used for the fabrication of microdisk resonators. A microdisk (MD) laser is one of the most promising device to achieve low threshold current with high output power

[6]. MD lasers of diameter 7.5 μm have been fabricated on an SOI platform in the past by using bonding techniques. Following this, devices were fabricated with a diameter of 7.5 μm on sample D using e-beam lithography and InP/InGaAsP etching process described earlier in chapter 3. MD cavities with an etch depth of around 800 nm were fabricated.

Room temperature PL measurements of these MDs did show whispering gallery modes (WGM), however no lasing action could be observed (Paper A). A potential reason for this was found to be the leakage of the mode through the underlying NELOG InP layer, that remained due to shallow etching of MDs. Finite Difference Time Domain (FDTD) simulations of such MD structures have shown considerable leakage that did not allow the onset of lasing action. Efforts were made to create InGaAsP MD on InP pedestal using selective wet etching of InP, but unfortunately the InGaAsP MDs were lifted off during the wet etching process. Scattering losses observed due to the damage caused by dry etching of

InP/InGaAsP were also recognised as a reason for non lasing action of the MDs.

Following this a new method for device fabrication was developed, using focussed ion beam (FIB) for etching InP/InGaAsP MDs. Fig. 7 shows the fabricated MDs on sample C using the FIB process defined in chapter 3. FIB etching could control the etch depth of the

MDs to avoid the leakage of the optical mode. As seen in the inset of Fig. 7 with an additional

FIB polishing step at a lower current, MDs with ultra-smooth sidewalls were obtained.

Experiments on optical pumping of these devices under pulsed conditions are continuing.

Results and Discussion

40

Fig. 7. SEM image of the FIB etched MDs on NELOG InP on Si with MQWs (sample C).

Inset is showing the smooth sidewalls of an etched MD.

4.1.3 Characterisation and Modal analysis of MDs on Sample D

The fabricated MDs on sample D were optically pumped using the PL setup

(mentioned earlier in chapter 3) at room temperature using a continuous wave laser emitting at 1.1 μm. As mentioned earlier the PL measurements did show WGM modes, however no lasing was seen. Speculative conclusion was made about tremendous scattering losses caused by rough sidewall to be the primary reason for non-lasing action. However, the modal analysis (Finite element method based simulations) revealed that the main reason for nonlasing instead was the leakage of the optical mode to the underlying ELOG layer via shallow etched MD. Fig. 8 shows the results of the simulations, leakage of the optical mode is visible in the shallow etched MD (0.8 μm), whereas in a deeply etched MD (1 μm) mode leakage is minimised. From the simulations it was confirmed that the modal gain of the active region was of same order to that of leakage losses (Paper A).

41

Results and Discussion

Fig. 8. Optical mode profile in shallow etched (0.8 μm) and deep etched (1 µm) MDs

4.2

Isolated large area ELOG InP on Si (Paper B, Paper C and Paper D)

TEM and CL Characterisation of coalesced NELOG InP on Si layers revealed that new defects were formed at the point of coalescence of two growth fronts. To overcome the need of multiple line openings to achieve large ELOG area, experiments with modified patterns were devised. Unlike in the previous experiments, this time optical lithography was used as described in chapter 3 for pattern definition. The use of optical lithography restricted the resolvable feature to 1 μm (opening size) and also introduced the imperative demand of etching a comparatively thick dielectric mask (2 μm) to enable ART for defect trapping.

Earlier simulations from our group [7] had shown that for an integrated platform based on

ELOG InP on Si maximum heat dissipation could be obtained through 1μm wide openings.

Effective heat dissipation from the III-Vs to Si is a major concern in other bonding based heterogeneous techniques [8] [9]. Another demand raised by the use of 1 μm wide openings was to use a thick SiO

2

mask (2 μm) to take advantage of ART. But fortunately, the design of an evanescently coupled platform also requires a thick layer of SiO

2

for efficient mode confinement in a buried Si waveguide. Such a buried Si waveguide in SiO

2

had been used in the past by Yang et al. for evanescent coupling of optical mode from QD lasers [10].

To study the strategy for a monolithically integrated III-V on Si platform based on

ELOG technique, experiments were devised with the use of thick PECVD SiO

2

mask (2 μm) to mimic the buried waveguide structure (Fig. 9).

Three samples were prepared to study (i) the absence of ART with 1 μm wide opening in a thin (<1 µm) SiO

2

mask, (ii) the revelation of ART from the coalesced nano sized openings with thick SiO

2

mask and (iii) the revelation of ART with 1 μm wide openings with

2 µm thick SiO

2

mask. All the samples were polished using the InP seed layer CMP process described earlier in chapter 3. In this thesis the fabrication, growth and characterisation experiments performed on the last sample, which was fabricated using optical lithography with thick SiO

2

mask (2 μm). Details of other two samples are given in Paper B.

Results and Discussion

Fig. 9. Schematic of the proposed monolithic III-Vs on Si platform based on ELOG [7]

For these experiments a new photolithography mask was designed with six fields.

Each field had an area of 1.25 x 1.25 cm

2

with a constant opening size of 1 μm. They differed only in the separation (1 μm, 2 μm, 3 μm, 4μm, 5 μm and 20 μm) between the parallel openings. Varying separations were used in the experiment to study the effect of coalescence from such wide openings with SiO

2

mask thicknesses supporting ART. Field with 20 μm separation between openings was used to generate isolated large areas of ELOG InP on Si

(Paper B), whereas the other 5 fields were used to optimise the coalescence of parallel growth fronts (Paper C). Fig. 10 shows the schematic of the mask design. Standard lithography and RIE techniques were used to define patterns on the deposited SiO

2

mask to facilitate SAG. Like previous experiments line openings were defined 30° off [110] to facilitate higher lateral growth rates.

42

Fig. 10. Schematic of the mask design used to generate large areas of ELOG InP on Si

43

Results and Discussion

The sample with a separation of 20 μm was used for sulphur doped (nominal concentration of 2x10

18

cm

-3

) ELOG InP by HVPE. The growth was conducted at 605° C with a V/III ratio of 10, and the growth time was optimised to be 17 minutes (Paper D) to avoid coalescence. PL measurements of this ELOG InP on Si layer have shown comparable intensities to that of planar InP reference grown along with it. These results supported the promising material quality obtained through SAG via such wide openings. Fig. 11 shows the

TEM image demonstrating the phenomenon of ART and it was first time that blocking of threading defects was reported even in such wide openings (Paper B).

Fig. 11. TEM image showing the blocking of a threading dislocation by ART

4.2.1 Optimisation of InGaAsP MQWs on isolated large areas of ELOG InP on Si

(Paper B)

Motivated by the promising results obtained from PL and TEM analysis done on isolated large areas of ELOG InP of Si, these templates were used for growth of InGaAsP based MQW using MOVPE. Layer structure of the MQWs is given in Table 2. Similar to previous MQW growth on NELOG InP on Si, SCH layers were present in this design as well for better mode confinement. The layer structure of InGaAsP based MQWs was designed to emit at a wavelength of 1.55 μm. Prior to the MOVPE growth, SiO

2

mask was stripped off using 7% buffered HF (hydrofluoric acid) to minimize the loading effect as explained earlier in section 4.1.1. The PL measurements on these MQWs revealed comparable intensities with respect to those of quantum wells grown on planar InP reference grown along with it. A cross sectional TEM analysis of these structures has shown quantum structures with highly uniform material layers with clean abrupt interfaces.

Results and Discussion

44

Layer Number

ELOG InP on Si

2, 18

3,5,7, 9,11,13,15,17

4, 6, 8,10, 12, 14, 16

In

In

0.73

GaAs

0.51

In

Material

0.71

0.73

n-InP

GaAs

GaAs

0.51

0.84

Thickness Doping (cm

-3

) Details

9 μm 1x10

18

P 105

P 6.5

UID

UID

SCH

P 8.2 UID Barrier

QWs

Table 2. Details of the MQW structure grown on isolated large areas of ELOG InP on Si

4.2.2 Microdisk resonators on isolated large areas of ELOG InP on Si

Encouraged by the good quality of the ELOG material and of the subsequently grown uniform MQWs, we undertook MD device fabrication. Learning from previous experiments on the fabrication of MDs on NELOG InP on Si, efforts were made in refining the process of mask less FIB etching of InP/InGaAsP based structures. A two-step FIB process was developed as described in chapter 3, which began with the fabrication of a big ring like structure with high FIB current followed by a slow polishing process to smoothen the sidewalls of the etched MDs. Many MDs with different diameters varying from 6 μm - 15μm were fabricated using this process, which also enabled us to use the sample many times with different FIB parameters. Fig. 12 shows SEM image of one typical MD fabricated using this process. As we have seen earlier from the SEM images the first step of FIB etching introduced considerable roughing of the sidewall; however, the subsequent polishing process smoothened the sidewall. In our previous etching experiments such smooth sidewalls were never obtained. Since gallium ion beam was used, some gallium deposition is visible on the top of the MDs.

Fig. 12. SEM image of the FIB etched MD on isolated area of ELOG InP on Si. The inset shows the high resolution TEM of the InGaAsP MQWs grown on ELOG InP on Si.

45

Results and Discussion

4.2.3 Characterisation

These MD resonators were optically pumped using room temperature micro-PL setup.

The measurements were performed at our collaborators lab in Photonics group at University of Ghent, Belgium. A short-pulsed (7 ns) laser emitting at 1064 nm (1.17 eV) was used for the optical pumping of the MD devices. Choice of a wavelength corresponding to the bandgap lower than that of InP (E g

= 1.35 eV) for optical pumping eliminated the photon absorption by the top InP layer. Fig. 13 shows the PL spectrum measured from the fabricated microdisks.

From the PL curve we can certainly observe the WGMs of the MD resonator; the sharp peak close to 1550 nm signifies the fundamental mode of the resonating cavity. The resonances in shorter wavelength side are attributed to the filling of higher energy states in the QW. These resonances can be the excitations of carriers to the next QW states. Due to step like density of states function for QW, a sharp dip is observed at 1450 nm as well. Such carrier screening effect had been explained earlier in the PL spectra of InP/InGaAsP MQW photovoltaic structures [11]. Similarly a long tail was observed in the PL spectra of the MQWs on ELOG

InP/Si as well (Paper B). The observation of strong emission in these MDs appears to be near-lasing emission, which however remains to be confirmed by more experiments and simulations. We experienced difficulty in collecting from the sidewalls of the MDs the emitted photons that are widely scattered. This can be improved by using optical fiber or even better by employing the buried Si waveguide structure in SiO

2

mask, as explained earlier.

Fig. 13. PL spectrum measured at room temperature from MDs fabricated on ELOG InP on Si

Results and Discussion

4.2.4 Electrical and Optical properties of unintentionally doped ELOG InP on Si

(Paper C)

As mentioned earlier a new photolithography mask with smaller separation between openings was designed to study the coalescence of ELOG over a large area (1.25 x 1.25 cm

2

).

After numerous experiments, coalescence of ELOG InP on Si was optimised using the separation of 3 μm between two parallel openings. This procedure was used to study the electrical properties of a coalesced large area of ELOG InP on Si. Same pattern fabrication process was used as explained in earlier sections, however, a two-step growth process was used in this experiment. In first growth step, a semi-insulating (SI) InP doped with iron was grown to completely fill the openings and even allowed to coalesce. This SI InP doped with iron was indispensable as it should separate the underlying n-doped InP seed layer of conductive nature from the subsequently grown unintentionally doped (UID) ELOG InP on which Hall measurements were planned for the investigation of its transport properties. The

SI InP growth was done at 600° C in HVPE for 15 minutes with a V/III ratio of 10. Nominal resistivity of the SI InP doped with iron is on the order of 2x10

8

Ω.cm. In the second growth step UID ELOG InP was grown which resulted in a layer thickness of ~5 μm. The UID growth was done at 610° C for 20 minutes with a V/III ratio of 10. This resulted in a completely coalesced ELOG InP on Si although some voids were inevitably observed at few sites. Fig. 14 shows a schematic of the overall growth process. The presence of voids in the

ELOG InP layer was due to the reluctance of the certain inevitable facets to merge with the adjacent fronts at certain sites. Overall the surface could be considered as continuous. Two other samples were also used in the same experiment as references. One planar InP reference doped with iron and another iron doped InP with similar pattern design as on Silicon sample.

Details of the three samples are given in paper C.

Hall measurements were performed in a system with four probes, and tin (Sn) doped

In metal was used to make contacts on all the three samples. Since the residual dopant in our

HVPE reactor is always of n-type, InSn alloy was used as a contact material. Metal contacts were annealed at 350° C for 1 minute using rapid thermal annealing in nitrogen environment.

A magnetic field of 5 kG (kilo Gauss) (0.5 Tesla) was used during the Hall measurements.

46

47

Results and Discussion

Fig. 14. Schematic of the ELOG process to measure the Hall mobility of ELOG of InP on Si

All three samples were measured under similar conditions. Table 3 shows the measured carrier concentrations (n) and Hall mobility. The trend in decreasing mobility from planar InP reference > ELOG InP on InP > ELOG InP on Si was explained by the formation of certain growth facets and enhanced dopant incorporation in certain regions especially at the points of coalescence. These factors contributed in formation of some voids in ELOG InP on

Si causing least uniformity that resulted in a relatively higher carrier concentration.

Sample

ELOG InP/ELOG InP:Fe/n-InP seed/Si substrate

ELOG InP/ELOG InP:Fe/InP:Fe substrate

Hall mobility

(cm

2

/Vs)

815

1950

Carrier (n)

Concentration

(cm

-3

)

1.8x10

17

1.8x10

15

UID InP/InP:Fe substrate 2850 1.9x10

14

Table3. Hall mobility and carrier concentration of UID ELOG InP on Si in comparison to reference samples.

Results and Discussion

PL measurements from all three samples showed comparable PL intensities. Some residual strain (tensile) was observed in ELOG InP on Si with a 4 nm shift in the peak PL intensity. It was believed that the GaAs buffer layer that was used for growth of InP seed layer on Si was completely relaxed. However, X-Ray Diffraction (XRD) measurements from

ELOG InP on Si layer have revealed a relatively broader GaAs XRD peak (not completely relaxed) between sharp InP and Si peaks. In addition to this interaction of ELOG InP with

SiO

2

mask is knows to introduce tensile strain in the ELOG layer due to difference in thermal expansion coefficients [12].

4.2.5 Formation and Blocking the stacking faults in ELOG (Paper E)

Aspect ratio trapping or epitaxial necking [17] has demonstrated the blocking of line defects, however filtering or formation of planar defects like stacking faults during ELOG remains a challenge. These were addressed by theoretical modelling. It was found that stacking faults due to their 2-D geometry might appear to be blocked by the mask sidewall at one point but can still be exposed elsewhere in the elongated ELOG region and climb up. To counter the propagation of stacking faults, a model has been worked out taking into account different orientation angles of the openings defined in a mask of different thicknesses. This model predicts a critical thickness of the dielectric mask that is needed to stop the propagation of a stacking fault in the ELOG layer. The model was made for openings defined 30° off

[110] direction, as this is the direction known to provide maximum lateral growth rate. From the model it was found that the bounding partials of dislocations dictate the propagation or non-propagation of the stacking fault. Calculations based on this model showed that, in the present case the critical mask thickness required to stop propagation of all stacking faults is

>3.9 times the size of the opening, assuming the bounding partials extend along <101> and

<011> directions. These theoretical findings were not checked exhaustively by experiments during this thesis work, however recent work by Julian et al. has shown ELOG of InP on Si in such high aspect ratio openings showing stacking faults terminating at the mask sidewalls without reaching the ELOG layer [13]

Formation of stacking faults during the ELOG had also been a concern, due to random deposition errors, steric hindrances, high-growth rates as proposed earlier [14] [15]. However, the ELOG experiments on InP substrates did not show formation of stacking faults either in coalesced or uncoalesced ELOG InP layers. This rules out the formation of stacking faults as something specific to ELOG and is rather attributed to their presence in the highly defective seed layer. Their existence in the ELOG layer is caused due to their propagation from the low aspect ratio openings. Nevertheless, stacking faults can randomly form in the ELOG layers to accommodate the strain in the overgrown layers.

4.3

Corrugated ELOG InP on Si for Photonics and Multi Junction Solar Cells (Paper

F and Paper G)

It is widely known that direct growth of lattice mismatched materials results in deteriorated material quality. Mismatch in lattice constants, difference in thermal expansion

48

49

Results and Discussion coefficients results in a layer full of defects. These defects can be 0-dimensional (Point defects) or 1-dimensional (line defects like dislocations) or 2-dimensional (planar defects like stacking faults, twin boundaries). These limitations have long disrupted the direct growth of two highly mismatched materials. One such example is InP and Si, as explained earlier numerous efforts to integrate these two materials have failed in past. Researchers have proposed many alternatives, one such solution called ELOG was focus of this thesis.

ELOG has demonstrated its promising application in achieving an integrated platform to provide for III-V light sources on Si. Nevertheless one shortcoming of ELOG technique is its inability to form direct contact with Si substrate because of the presence of an intermediate mask layer This acts as a limiting factor in cases where direct interface between III-Vs and Si is required. One such application is multijunction solar cells based on III-V and Si. From the beginning of this thesis work parallel efforts were made to realise a direct heterojunction between InP and Si. A new method of ELOG was devised where growth was instead conducted from the top of partially exposed mesa structure of InP seed layer on Si, thus the name corrugated ELOG.

This technique heavily exploits the near equilibrium nature of HVPE, where growth species are unable to chemisorb anywhere except InP seed layer. Fig. 15 shows a schematic of the CELOG process (fabrication and growth). CELOG is a technique where ART is not used for defect filtering instead, the property of defect propagation in upward growth directions is used for defect filtering. In other words, as the growth began from the top of the InP seed mesa defects from the InP seed layer propagated in upward direction and subsequently the downward grown lateral region contained almost no defects as the defects are not able to bend downwards. CELOG technique resembles to conformal growth technique in certain growth regions. In CELOG, growth is conducted from the top of the InP seed mesa while in conformal growth, the growth takes place from the sidewalls of the InP seed mesas [16]. As we know a threading dislocations is the dislocation propagating to the top of the epilayer with an angle of 45° from (001) in <100> directions [17]. In our experiments these defects reach the top of the epilayer surface and terminate. This provided completely defect free areas of

InP in the wing section of the CELOG. After the defect filtering another main aspect of

CELOG InP was to make a direct heterojunction with Si. Direct growth of epitaxial InP on Si resulted in misfit dislocations caused due to the 8.1% lattice mismatch between them.

However, native oxide free bonding of InP substrates with Si have shown completely dislocation free InP [18] [19]. CELOG is a technique where once the laterally grown InP extends over the mesa of InP seed layer, growth starts happenings in 3 directions upward, lateral and downward (Fig. 15). The growth in downward direction makes an interface with the silicon surface once brought in contact at InP growth temperature. The interaction between two materials is not completely understood, however it is believed that some sort of molecular bonding is taking place during the creation of abrupt heterointerface of epitaxial

InP and Si. Studies are underway to understand the absence of misfit dislocations in InP and

Si heterostructure, as the misfit strain caused due to lattice mismatch must be accommodated in the epitaxial layer.

Results and Discussion

50

Fig. 15. Schematics of the complete CELOG process

In the TEM analysis of CELOG InP on Si, no dislocations were observed, however stacking faults were clearly seen in the cross-section, which was attributed to the damaged Si surface (Paper F). However, (Paper E) rules out the formation of stacking faults due to damaged surfaces. One main reason for the absence of dislocations could be the low stacking fault energy of InP [20] [21], thus more prone to form i.e. the misfit strain is compensated by the formation of stacking faults or twins [22].

Details of the “bonding” event during epitaxy is not yet fully understood. Studies on strain induced during the CELOG process will help in understanding the formation of stacking faults.

Such a platform can be the pathway for a monolithically integrated platform of InP and Si. The generic nature of this technique can be useful for integration of other mismatched systems as well. In this work CELOG of InP on Si is demonstrated as a proof of concept, the idea was proposed as a cheap alternative to fabricate multijunction solar cell based on III-Vs on Si using both as subcells (Paper F). In ideal case GaInP/GaAsP would be the materials of choice for CELOG on Si, to accommodate a wider wavelength absorption range from solar spectrum in an efficient manner. Additionally this process has great potential for other

51

Results and Discussion photonics applications, one such application is the integration of InP based lasers on Si (see chapter 2, section 2.2.3).

4.3.1 Growth and characterisation results from CELOG experiments

CELOG experiments began with optimisation of lateral growth of InP from the top of a partially exposed InP mesa covered with SiO

2

mask everywhere else. Initial growth experiments were conducted on InP substrates. Two type of mesa structures were used in the experiments, line and ring structures. Line openings were defined 30° off [110] to facilitate higher lateral growth rate and ring openings were defined for site controlled growth and to study the effect of single point of coalescence in CELOG. In the first fabrication step, InP mesa structures (20 μm) were defined using standard lithography and dry etching process for

InP using SiO

2

mask; after the InP etching, SiO

2

mask was stripped off. In the second fabrication step, 200 nm SiO

2

mask was deposited in a conformal manner over the whole substrate. In the third and final fabrication step line and ring openings (1 μm) were defined on top of InP mesas. After this, growth was conducted in HVPE. The growth started from the openings and then continued in both vertical and lateral directions. Once the lateral growth exceeded over the InP mesa growth in downward direction began. When continued, this growth makes a contact with underlying material and thereafter continues laterally making heterointerface with the whole substrate.

To study the growth directions, this experiment was performed with alternating layers of sulphur doped and UID InP. Fig. 16 shows a SEM image of the cross-section of stain etched alternating layers of CELOG InP on InP (Paper G). The void close to the sidewall of the InP mesa was due to the deposition of a thicker layer of oxide close to the base of the InP mesa.

Based on these observations, experiments on Si were devised with a slightly different mask design from that used in the previous experiment. Same InP on Si seed layer substrate that were used for ELOG experiments earlier were also used for CELOG experiments. The fabrication process on Si was slightly modified from the CELOG experiments on InP substrates. In this experiment only InP seed layer mesas were covered with SiO

2

mask and the

Si surface was not covered. Openings were defined on top of these mesas of InP seed layer.

Fig. 15 gives a clear explanation of the fabrication process on Si samples. Details of growth optimisation experiments are given in paper G.

Results and Discussion

52

Fig. 16. SEM image of the alternate doping profile to study the CELOG mechanism

Following the growth optimisation, experiments were made to study the diffusion of phosphine in Si and doping of sulphur in InP to form a tunnelling junction between III-V and

Si. High doping levels are required for this purpose. Both phosphine and sulphur will act as ndopants for Si and InP, respectively. The experiments were made using the same fabrication process explained in earlier section. Sulphur doped CELOG of InP was conducted in HVPE at a growth temperature of 610° for 10 minutes with a V/III ratio of 5. It was found that lateral growth is lowered with the doping (paper G). A vertical growth of 12 μm and a lateral growth rate of 21 μm were observed for this sample.

After the successful CELOG of InP, experiments were made to study the electrical properties of the heterointerface created between InP and Si. Before electrical contacts can be made between CELOG InP and Si it was necessary to completely isolate the conductive InP seed layer from the CELOG InP on Si. To achieve this dry etching of InP was used. Fig. 17 shows the isolated regions of CELOG InP making an interface with Si and the InP seed mesa.

Since the InP mesa was covered with SiO

2

that has a quite high selectivity during InP dry etching, the height of InP seed mesa was higher than that of CELOG InP on Si after dry etching. An alternative to dry etching of InP could be the use of CMP of InP. After making sure that the two areas were isolated from each other, electrical contacts were deposited on

InP and Si using metal evaporation. Circular contacts were defined only on the top of the isolated CELOG InP using standard optical lithography, metal evaporation and lift-off process.

53

Results and Discussion

Fig. 17. TEM image of the isolated section of CELOG InP making a heterointerface with Si

Alternating stack of Au-AuGe (~ 200 nm) was used as a contact for n-type CELOG

InP and Al (~600 nm) was used as a contact for Silicon substrate. Aluminium was deposited on the backside of the Si wafer. Standard two probe I-V measurements were made on these samples, and a linear response was observed for a sweep voltage of -1V to +1V. This linear response supported the Ohmic behaviour of the tunnel junction formed between CELOG InP and Si. Interfacial resistance of this heterojunction was estimated to be 0.025 Ω cm

2

. It was clear that high doping of InP (2x10

18 cm

-3

) facilitated the formation of the tunnel junction between CELOG InP and Si. Cross sectional TEM analysis of the abrupt heterointerface created by CELOG InP and Si has shown interaction of the InP lattice with the lattice of Si without creation of any misfit dislocations. However stacking faults were created at the abrupt interface between InP and Si. These experiments show that with proper growth parameters an abrupt interface of highly mismatched systems can be achieved using the proposed CELOG technique.

References

[1] P. Vohl, C. O. Bozler, R. W. McClelland. A. Chu and A. J. Strauss, “Lateral Growth Of Single-Crystal Inp

Over Dielectric Films By Orientation-Dependent Vpe”, Journal of Crystal Growth 56, 4l U 422, 1982.

[2] Y.S. Chang, S. Naritsuka, T. Nishinaga, “Optimization of growth condition for wide dislocation-free

GaAs on Si substrate by microchannel epitaxy”, Journal of Crystal Growth 192, 18-22, 1998.

[3] F. Olsson, M. Xie, S. Lourdudoss, I. Prieto, and P. A. Postigo, “Epitaxial lateral overgrowth of InP on Si from nano-openings - Theoretical and experimental indication for defect filtering throughout the grown layer”, J.

Appl. Phys. 104, 093112, 2008.

[4] T. A. Langdo, C. W. Leitz, M. T. Currie, E. A. Fitzgerald, A. Lochtefeld, and D. A. Antoniadis, “High quality Ge on Si by epitaxial necking,” Appl. Phys. Lett., vol. 76, no. 25, pp. 3700–3702, 2000.

[5] T. Nishinaga, T. Nakano, and S. Zhang,”Epitaxial Lateral Overgrowth of GaAs by LPE”, Japanese Journal

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J. Fedeli, C. Lagahe, and R. Baets, “Electrically pumped InP-based microdisk lasers integrated witha nanophotonic silicon-on-insulator waveguide circuit,” Optics Express, vol. 15, no. 11, pp. 6744–6749, 2007.

Results and Discussion

[7] Z. Wang, C. Junesand, W. Metaferia, C. Hu, L. Wosinski, and S. Lourdudoss, “III–Vs on Si for photonic applications—A monolithic approach,” Mater. Sci. Eng. B, vol. 177, no. 1, pp. 1551–1557, 2011.

[8] P. Rojo-Romeo, J. Van Campenhout, P. Regreny, A. Kazmierczak, C. Seassal, X. Letartre, G. Hollinger, D.

Van Thourhout, R. Baets, M. Fedeli, and L. Di Cioccio, “Heterogeneous integration of electrically driven microdisk based laser sources for optical interconnects and photonic ICs,” Opt Express, vol. 14, no. 9, pp. 3864–

3871, May 2006.

[9] J. Van Campenhout, P. Rojo Romeo, D. Van Thourhout, C. Seassal, P. Regreny, L. Di Cioccio, J. M. Fedeli, and R. Baets, “Thermal characterisation of electrically injected thin-film InGaAsP microdisk lasers on Si,” IEEE

Journal Of Lightwave Technology, VOL. 25, NO. 6, JUNE, 2007.

[10] J. Yang and P. Bhattacharya, “Integration of epitaxially-grown InGaAs/GaAs quantum dot lasers with hydrogenated amorphous silicon waveguides on silicon,” Opt Express., vol. 16, no. 7, p. 5136, 2008.

[11] O. Y. Raisky, W. B. Wang, and R. R. Alfano,” Carrier screening effects in photoluminescence spectra of

InGaAsPÕInP multiple quantum well photovoltaic structures”, Applied Physics Letters Volume 79, Number 3,

16 July, 2001.

[12] Y. T. Sun, K. Baskar, and S. Lourdudoss, “Thermal strain in indium phosphide on silicon obtained by epitaxial lateral overgrowth,” J. Appl. Phys., vol. 94, no. 4, pp. 2746–48, 2003.

[13] Nick H. Julian, , Phil A. Mages, Chong Zhang, John E. Bowers, “Improvements in epitaxial lateral overgrowth of InP by MOVPE, Journal of Crystal Growth Volume 402, 2014.

[14] F. Ernst and P. Pirouz, “Formation of planar defects in the epitaxial growth of GaP on Si substrate by metal organic chemical-vapor deposition,” J. Appl. Phys. 64(9), 4526–4530, 1988.

[15] R. Loo, G. Wang, T. Orzali, N. Waldron, C. Merckling, M. R. Leys, O. Richard, H. Bender, P. Eyben, W.

Vandervorst, and M. Caymax, “Selective area growth of InP on On-Axis Si(001) substrates with low antiphase boundary formation,” J. Electrochem. Soc. 159(3), H260–H265, 2012.

[16] O. Parillaud, E. Gil Lafon, B. Gérard, P. Etienne and D. Pribat, “High quality InP on Si by conformal growth”, Appl. Phys. Lett. 68, 2654, 1996.

[17] E. A. Fitzgerald and Naresh Chand, “Epitaxial Necking in GaAs Grown on Pre-patterned Si Substrates”,

Journal of Electronic Materials, Vol. 20, No. 10, 1991.

[18] A. Talneau, C. Roblin, A. Itawi, O. Mauguin, L. Largeau, G. Beaudouin, I. Sagnes, G. Patriarche, C. Pang, and H. Benisty, “Atomic-plane-thick reconstruction across the interface during heteroepitaxial bonding of InPclad quantum wells on silicon”, Applied Physics Letters 102, 212101, 2013.

[19] C. Pang, H. Benisty, M. Besbes, X. Pommarede, and A. Talneau, “Oxide-free InP-on-Silicon-on-Insulator

Nanopatterned Waveguides: Propagation Losses Assessment Through End-Fire and Internal Probe

Measurements”, IEEE Journal Of Lightwave Technology, VOL. 32, NO. 6, MARCH 15, 2014.

[20] A. Krost, F. Heinrichsdorff, D. Bimberg, and H. Cerva, "InP on Si(111): accommodation of lattice mismatch and structural properties," Appl. Phys. Lett. 64, 769-771, 1994.

[21] M. Dynna, A. Marty, ” The energetics of the relaxation of misfit strain in thin epitaxial films by means of twinning”, Acta Materialia Volume 46, Issue 4, 1998.

[22] Gottschalk, H., Patzer, G. & Alexander, H. “Stacking-fault energy and ionicity of cubic-III-V compounds”, Phys. Status Solidi A 45, 207–217, 1978.

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55

Summary and conclusions

5

Summary and conclusions

This chapter summarises the major results obtained during this thesis work, which focussed to achieve high quality III-V/Si semiconductors heterostructures for photonic integration and photovoltaic applications by combining ELOG of the starting InP layer by

HVPE and subsequent growth of active layers on it by MOVPE.

1. InP is the starting material that is grown on Si via ELOG. The major challenge is to hinder the defect propagation in the ELOG InP layer. ELOG starting from SAG in nano-sized openings helps in reducing the probability of defect propagation; however some threading defects are still able to climb up via these openings. ART or epitaxial necking where a high mask thickness to opening ratio (>2) is used to block threading dislocation not only beneath the mask but also within the opening. Nevertheless, it is found that new defects may form on the top of the dielectric mask surface either due to surface irregularities caused by the rough and defective seed layer beneath or through coalescence of parallel growth fronts. To eliminate the defects caused due to roughness of the dielectric mask, the non-uniform InP seed layer is planarised by a two-step chemical mechanical polishing process. This smooth InP seed layer helped in achieving an almost defect free smooth ELOG layer, revealed through cathodoluminescence (CL) studies.

However, due to very small area of ELOG InP obtained, the subsequent growth of multi quantum well (MQWs) incurred heavy loading effect during metal organic vapour phase epitaxy (MOVPE). After several iterations a new mask pattern design with closely spaced multiple nano-sized openings resulted in a smooth layer of coalesced ELOG InP on Si of area large enough (15 x 250 μm2) for subsequent growth of MQW layers. Although the loading effect was not completely eliminated, the grown MQW on these samples showed similar optical quality as MQWs on planar

InP reference grown along with it. These templates are used to fabricate microdisk

(MD) resonators on them using precise e-beam alignment and optimised InP dry etching. Photoluminescence (PL) measurement from these MDs showed strong luminescence and presence of WGM is observed. Unfortunately lasing action is not be observed which is attributed to high leakage losses caused due to shallow etching of

MDs. Additional characterisation of these MDs using transmission electron microscopy (TEM) has revealed inhomogeneity and non-uniformity in MQWs grown on ELOG InP. This is primarily attributed to two factors i) persisting loading effect (in smaller extent than before) during MOVPE growth ii) surface irregularities and formation of new defects in ELOG InP due to coalescence.

2. To avoid the defect formation through coalescence and loading effect due to reduced area growth a new mask was designed to cover a comparatively large area with isolated openings for growth. This new design made use of optical lithography instead of e-beam lithography. The most significant advantage of this new mask design is its compatibility with the strategy of the proposed monolithic evanescently coupled III-V

Summary and conclusions laser on silicon. Mask thickness and opening size used in the new design mimics the ideal conditions required for efficient mode confinement and athermal operation of a monolithic III-V laser on Si. ELOG experiments from this new design resulted in large areas of high quality InP on Si. Optical characterisation on these ELOG layers is supportive of the high material quality and TEM studies revealed blocking of threading defects even in such wide openings. It is for the first time that ART of threading defects has been demonstrated in micrometer size openings. Subsequent growth of MQW in MOVPE resulted in material with high optical quality. PL measurements from them have shown comparable (~85%) intensities with MQWs on planar InP reference grown along with it. TEM analysis of these MQW has revealed high uniformity and clean interfaces between the quantum wells. Encouraged by this,

MD resonators were fabricated on them. PL measurements (optical pumping under pulsed conditions) on these resonators are supportive of possible lasing action.

However, collection of light from these resonators is still a concern, which can be eliminated either with the use of an optical fiber or even better with the proposed integrated platform of silicon waveguide buried in SiO

2

cladding. These results are yet to be confirmed with simulations that calculate the free spectral range between the optical modes. A complete electrically driven evanescently coupled monolithic platform of III-Vs on Si is yet to be demonstrated. Nevertheless, the promising optical quality of ELOG InP and MQWs and strong resonances from the MD resonators are very encouraging.

3. Even though the dielectric mask blocks threading defects, there is a possibility that certain planar defects can climb up in ELOG through the openings for SAG or just form during the ELOG remains. It is found with extensive TEM analysis that planar defects like stacking faults that might appear to be blocked at one point can still be exposed at another point in the openings. A theoretical model is proposed, which suggests that under certain conditions by coordinating the orientation of the openings and the thickness of the mask even stacking faults can be blocked. It is also found that new stacking faults can form in the ELOG layer due to strain induced by the dielectric mask. Annealing of the ELOG layer at a temperature higher than the growth temperature can help in removing the induced strain in the ELOG layer. Both of these hypotheses remain to be confirmed by experiments.

4. For the first time coalesced layer of unintentionally doped ELOG InP on Si covering a large area of (1.25 x1.25 cm

2

) is used to study the carrier transport in ELOG InP.

Good carrier mobility with respect to the carrier concentration (n) is observed in the

ELOG InP on Si. Reduction in Hall mobility compared to planar unintentionally doped InP reference is attributed to enhanced dopant incorporation at the coalescence points. Since uncoalesced and isolated areas of ELOG InP are of importance for an integrated platform on silicon, their electrical properties can be studied by Hall bar measurement.

56

57

Summary and conclusions

5. ELOG by HVPE is modified in a newly developed technique called corrugated ELOG

(CELOG). In contrast to conventional ELOG technique where growth is conducted in an opening, in CELOG growth is conducted from the top of a seed layer mesa structure on silicon. Using this technique the formation of direct interface between InP and Si with reduced defect density has been demonstrated. The complete mechanism of how this interface is formed is still under investigation. Absence of dislocations is visible in the TEM analysis of CELOG InP on Si, however, stacking faults are prominent. Absence of misfit dislocation caused by misfit strain between InP and Si is attributed to low stacking fault energy of InP, where misfit strain between two is accommodated by the formation of stacking faults instead. Formation of direct interface between InP and silicon with reduced defect densities open ups the potential for fabricating III-V based multijunction solar cells on silicon. Nevertheless, the nature of the technique is generic and it can be modified to support a monolithically integrated III-V laser on Si.

Future Outlook

58

6

Future Outlook

With the revival of interest in integrating III-Vs on Si using epitaxial methods, advances in ELOG techniques can contribute significantly to this. To meet the future demands and challenges of communication and energy sectors a monolithically integrated platform of III-

Vs and Si is quite essential. Few suggestions are given to contribute to the continuing efforts on integrating III-Vs on Si as a future outlook.

1. For a monolithically integrated, evanescently coupled and electrically driven III-V based laser on Si, isolated regions of ELOG InP should be grown at strategically placed locations on a silicon wafer with buried silicon waveguide in SiO

2

structure.

Focus should be placed on optimisation of the overall ELOG process with additional annealing steps afterwards to remove strain-induced defects from ELOG material.

This work should be extended to silicon on insulator (SOI) wafers, with planarisation of the waveguide structure continuing with selective growth of InP seed layer in openings adjacent to the waveguide structure. Optimised ELOG of InP should be conducted through these openings. Already available technique for SAG of InGaAsP based multi quantum wells (MQWs) should be extended for use on ELOG material for growth of high optical quality active region.

2. Carrier transport in ELOG InP on Si should be studied thoroughly using Hall bar measurements to understand the electrical properties of ELOG InP. Background doping of silicon from the reactor wall and from the underlying silicon substrate should be studied by separate experiments on planar InP reference and ELOG InP on

Si. Semi-insulating layers of ELOG InP on silicon can be used for fabrication of III-Vs based ultra-fast electronic devices on cheap silicon substrates.

3. Further optimisation of CELOG growth process with controlled doping concentrations can be instrumental for futuristic III-Vs on Si multijunction solar cell where both III-V and silicon can be used as subcells. Designing of the subcell structure should account the restrictions of HVPE, as growth and doping of ternary compounds can be challenging in HVPE. A III-V subcell based on GaAs should be fabricated first, as planar GaAs substrate covers a very wide range of solar spectrum with experimental efficiency shown up to 28%. This efficiency can further be improved by techniques like light trapping by nano structuring of the layer. Compared to traditional GaAs based solar cells that are made on GaAs substrate; this subcell will use a relatively thin layer of GaAs. In addition to this, improvements in silicon subcell structure can be made by efficient phosphine diffusion and activation to realise an efficient pn-junction in silicon. Nano structuring of the silicon surface can further enhance the absorption in the silicon subcell that will be planarised by the subsequent CELOG growth in HVPE.

In this two subcell based solar cell it will be comparatively easier to achieve current matching with high short-circuit current than solar cell with three or four junction tandem cell.

59

Summary of appended papers

7 Summary of appended papers

Towards a monolithically integrated III–V laser on silicon: optimization of multi-quantum well growth on InP on Si

This paper presents the designing of the SiO

2

mask deposited for epitaxial lateral overgrowth ELOG to optimise the loading effect during multi quantum well (MQW) growth, which is a prerequisite for monolithically integrating III-V light sources on silicon. Growth of high quality InP layers on silicon through single and multiple nano-size openings is optimised by making use of the ELOG technique. These templates act as virtual InP substrates for the growth of

InP/InGaAsP MQWs. Studies on optical properties of ELOG InP and

InGaAs/InP MQWs have shown defect free ELOG InP with uniform well/barrier thickness across the grown layer. Microdisk (MD) resonators are fabricated on these templates using electron beam lithography and inductively coupled plasma etching of InP/InGaAsP layers. Room temperature optical pumping of MDs has shown clear signs of whispering gallery modes. Absence of lasing action is attributed to excessive leakage losses due to shallow etching of MDs. This is supported by a finite difference method based mode solver.

Contribution: Part of experiment planning, device fabrication, part of characterisation, data analysis and interpretation, manuscript writing

Simple Epitaxial Lateral Overgrowth Process as a Strategy for Photonic

Integration on Silicon

This paper outlines one of the promising strategies to integrate III-Vs with silicon to provide monolithic light sources for silicon photonics. Transformation of the conventional dielectric mask used in ELOG to SiO

2

/Si/SiO

2

waveguide structure for efficient mode confinement and enhanced thermal conductivity is shown. Optical characterisation and transmission electron microscopy of these layers have shown high optical quality with uniform interfaces. The study is important for futuristic needs of silicon photonics embedded with optical interconnects.

Contribution: Experiment planning, mask design and process development, part of epitaxial growth, part of characterisation, data analysis and interpretation, manuscript writing

Summary of appended papers

60

Carrier-transport, Optical and Structural Properties of Large Area ELOG InP on Si Using Conventional Optical Lithography

First time studies of electrical properties of ELOG InP on Si are presented. Hall measurements are used to study the carrier transport in ELOG layers on silicon grown using hydride vapour phase epitaxy (HVPE). Aspect ratio trapping or epitaxial necking of defects is used to eliminate defect propagation in the ELOG layer. However, increased carrier concentration caused due to enhanced dopant incorporation at coalescence points reduces the mobility of ELOG InP on Si.

Photoluminescence and X-ray diffraction techniques are also used to study the optical and structural properties of ELOG layers respectively.

Contribution: Experiment planning, mask design and process development, part of characterisation, data analysis and interpretation, manuscript writing

High quality large area ELOG InP on silicon for photonic integration using conventional optical lithography

To achieve large areas of high quality ELOG InP on Si without having the need of coalescence is presented. Unlike previous experiments on nano-sized opening to cover a large area pattern definition is done using optical lithography. This method fulfils the stringent requirements to achieve a monolithically integrated

III-V based light source on silicon. Optimisation of different processes serving as building blocks to achieve this platform is presented.

Contribution: Experiment planning, mask design and process development, part of epitaxial growth, part of characterisation, data analysis and interpretation, manuscript writing

Study of planar defect filtering in InP grown on Si by epitaxial lateral overgrowth

Propagation and formation of stacking faults in epitaxial lateral overgrowth is studied. It is found that propagation and formation of stacking faults is attributed to the poor quality of InP seed layer as the ELOG experiments on InP substrates have not shown any sign of defect propagation and formation. A model is devised that explains the propagation of stacking faults from the InP seed layer to the ELOG InP layer. This model also outlines the conditions with which even stacking faults can be blocked during the ELOG process.

61

Summary of appended papers

Contribution: Part of experiment planning, part of mask design and process development, part of epitaxial growth, part of characterisation, part of data analysis and interpretation, manuscript discussion

Realization of atomically abrupt InP/Si heterojunction via corrugated epitaxial lateral overgrowth

A new method called corrugated ELOG (CELOG) for achieving an atomically abrupt interface with low defect density between InP and silicon is developed.

As the name implies in contrast to conventional ELOG techniques in CELOG process growth is conducted from the top of an elevated mesa structure.

Transmission electron microscope is supportive of the atomically abrupt interface with reduced defect density. Electrical characterisation done by means of current-voltage measurements is supportive of the absence of an intermediate amorphous layer.

Contribution: Part of experiment planning, mask design and process development, part of characterisation, part of data analysis and interpretation, manuscript discussion

Growth of InP Directly on Si by Corrugated Epitaxial Lateral Overgrowth

This paper presents the details of the corrugated epitaxial lateral overgrowth

(CELOG) of InP on Si optimisation experiments in hydride vapour phase epitaxy. Effect of varying growth conditions like doping and V/III ratio is studied. Formation of high index boundary planes {331} and {211} during the

CELOG process is explained by dopant incorporation and gas phase supersaturation.

Contribution: Part of experiment planning, mask design and process development, part of characterisation, part of data analysis and interpretation, manuscript discussion

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