Indoor navigation with pseudolites (fake GPS sat.) Vlad Badea

Indoor navigation with pseudolites (fake GPS sat.) Vlad Badea
Examensarbete
LITH-ITN-ED-EX--05/001--SE
Indoor navigation with
pseudolites (fake GPS sat.)
Vlad Badea
Rikard Eriksson
2005-01-27
Department of Science and Technology
Linköpings Universitet
SE-601 74 Norrköping, Sweden
Institutionen för teknik och naturvetenskap
Linköpings Universitet
601 74 Norrköping
LITH-ITN-ED-EX--05/001--SE
Indoor navigation with
pseudolites (fake GPS sat.)
Examensarbete utfört i Elektronikdesign
vid Linköpings Tekniska Högskola, Campus
Norrköping
Vlad Badea
Rikard Eriksson
Handledare Karl Thysell
Examinator Ole Pedersen
Norrköping 2005-01-27
Datum
Date
Avdelning, Institution
Division, Department
Institutionen för teknik och naturvetenskap
2005-01-27
Department of Science and Technology
Språk
Language
Rapporttyp
Report category
Svenska/Swedish
x Engelska/English
Examensarbete
B-uppsats
C-uppsats
x D-uppsats
ISBN
_____________________________________________________
ISRN LITH-ITN-ED-EX--05/001--SE
_________________________________________________________________
Serietitel och serienummer
ISSN
Title of series, numbering
___________________________________
_ ________________
_ ________________
URL för elektronisk version
http://www.ep.liu.se/exjobb/itn/2005/ed/001/
Titel
Title
Indoor navigation with pseudolites (fake GPS sat.)
Författare
Author
Vlad Badea, Rikard Eriksson
Sammanfattning
Abstract
This
thesis was conducted by Rikard Eriksson and Vlad Badea for their Master of Science degree in
Electronics Design at the University of Linköping, Sweden. HTC Sweden AB initialized this thesis and
the thesis contains a pre study of pseudolite based indoor navigation systems, a design of a simple
pseudolite and finally some recommendations of applications.
The pre study starts off with an introduction of the GPS system. This since pseudolite based systems and
GPS have many similarities. Different pseudolites based techniques were then investigated and the pre
study is wrapped up with a very short briefing on the Hammerhead chip.
Some of the pseudolite based techniques were worth some more looking into and a pseudolite was
therefore designed and simulated. There was unfortunate not enough time to actually build the
pseudolite and verify it.
Some recommendations to HTC Sweden were given in the last chapter of this thesis. The authors of this
thesis recommend some interesting techniques and how the future work could proceed.
Nyckelord
Keyword
GPS, indoor navigation, pseudolites.
Upphovsrätt
Detta dokument hålls tillgängligt på Internet – eller dess framtida ersättare –
under en längre tid från publiceringsdatum under förutsättning att inga extraordinära omständigheter uppstår.
Tillgång till dokumentet innebär tillstånd för var och en att läsa, ladda ner,
skriva ut enstaka kopior för enskilt bruk och att använda det oförändrat för
ickekommersiell forskning och för undervisning. Överföring av upphovsrätten
vid en senare tidpunkt kan inte upphäva detta tillstånd. All annan användning av
dokumentet kräver upphovsmannens medgivande. För att garantera äktheten,
säkerheten och tillgängligheten finns det lösningar av teknisk och administrativ
art.
Upphovsmannens ideella rätt innefattar rätt att bli nämnd som upphovsman i
den omfattning som god sed kräver vid användning av dokumentet på ovan
beskrivna sätt samt skydd mot att dokumentet ändras eller presenteras i sådan
form eller i sådant sammanhang som är kränkande för upphovsmannens litterära
eller konstnärliga anseende eller egenart.
För ytterligare information om Linköping University Electronic Press se
förlagets hemsida http://www.ep.liu.se/
Copyright
The publishers will keep this document online on the Internet - or its possible
replacement - for a considerable time from the date of publication barring
exceptional circumstances.
The online availability of the document implies a permanent permission for
anyone to read, to download, to print out single copies for your own use and to
use it unchanged for any non-commercial research and educational purpose.
Subsequent transfers of copyright cannot revoke this permission. All other uses
of the document are conditional on the consent of the copyright owner. The
publisher has taken technical and administrative measures to assure authenticity,
security and accessibility.
According to intellectual property law the author has the right to be
mentioned when his/her work is accessed as described above and to be protected
against infringement.
For additional information about the Linköping University Electronic Press
and its procedures for publication and for assurance of document integrity,
please refer to its WWW home page: http://www.ep.liu.se/
© Vlad Badea, Rikard Eriksson
Abstract
This thesis was conducted by Rikard Eriksson and Vlad Badea for their
Master of Science degree in Electronics Design at the University of
Linköping, Sweden. HTC Sweden AB initialized this thesis and the thesis
contains a pre study of pseudolite based indoor navigation systems, a
design of a simple pseudolite and finally some recommendations of
applications.
The pre study starts off with an introduction of the GPS system. This
since pseudolite based systems and GPS have many similarities. Different
pseudolites based techniques were then investigated and the pre study is
wrapped up with a very short briefing on the Hammerhead chip.
Some of the pseudolite based techniques were worth some more looking
into and a pseudolite was therefore designed and simulated. There was
unfortunate not enough time to actually build the pseudolite and verify it.
Some recommendations to HTC Sweden were given in the last chapter
of this thesis. The authors of this thesis recommend some interesting
techniques and how the future work could proceed.
Acknowledgement
This research would not have been possible without the help from a
number of people. The authors want to express their gratitude towards
the people who aided them in their research. Fore most their advisor and
examiner Ole Pedersen for guidence and support through the whole
project. Associate Professor Qin-Zhong Ye for guidence during the
VHDL programming of the C/A- code generator. Adriana Serban
Craciunescu for her help with the design of the PLL- circuit. Associate
Professor Shaofang Gong for help with the mixer. Thanks also to Ph.D.
Candidate Haeyoung Jun of the Seoul National University for giving
guidelines on where to find information about C/A- code generation
procedure.
Contents
1
Introduction .........................................................................................................................................1
1.1
Motivation ...................................................................................................................................1
1.2
Background .................................................................................................................................1
1.3
Outline of this report.................................................................................................................1
2
The literature study .............................................................................................................................2
2.1
The Global Positioning System (GPS)....................................................................................2
2.1.1 GPS signal...............................................................................................................................3
2.1.1.1 L1, L2 and L3 Carrier waves.......................................................................................3
2.1.1.2 Pseudo- Random codes ...............................................................................................3
2.1.1.3 P(Y) and C/A codes Basics ........................................................................................4
2.1.1.4 P(Y) code generator .....................................................................................................4
2.1.1.5 C/A code generator .....................................................................................................8
2.1.2 Distance measuring .............................................................................................................10
2.1.2.1 Pseudorange measurements......................................................................................10
2.1.3 Trilateration ..........................................................................................................................11
2.1.3.1 2D Trilateration ..........................................................................................................11
2.1.3.2 3D Trilateration ..........................................................................................................12
2.1.4 GPS Clocks...........................................................................................................................12
2.1.4.1 GPS Satellite clocks....................................................................................................12
2.1.4.2 GPS Receiver clocks ..................................................................................................13
2.1.5 Geometric Dilution of Precision (GDOP)......................................................................13
2.1.6 Code phase ...........................................................................................................................13
2.1.7 Differential Code-phase GPS (DGPS).............................................................................14
2.1.8 Carrier- phase Differential GPS (CDGPS)......................................................................15
2.1.8.1 Carrier Phase Ambiguity............................................................................................16
2.1.8.2 Carrier Phase Ambiguity Resolution .......................................................................17
2.1.9 Atmospheric errors..............................................................................................................18
2.1.9.1 Ionosphere...................................................................................................................18
2.1.9.2 Troposphere................................................................................................................18
2.1.10
Multipath ..........................................................................................................................18
2.2
GPS Pseudolites (PL) ..............................................................................................................19
2.2.1 Pseudolite signals.................................................................................................................19
2.2.2 Binary phase shift keying (BPSK) .....................................................................................19
2.2.3 Pseudolite antennas .............................................................................................................20
2.2.4 The pseudolite pole .............................................................................................................20
2.2.5 Differential Pseudolite System...........................................................................................21
2.2.6 Difference between Pseudolite CDGPS and Global CDGPS......................................21
2.2.7 Indoor Pseudolite Navigation Systems ............................................................................22
2.2.7.1 Asynchronous System overview...............................................................................22
2.2.7.2 Synchronous System overview .................................................................................23
2.2.7.3 Pseudolite based inverted navigation systems........................................................24
2.2.8 Time Division Multiple Access (TDMA) and signal pulsing ........................................26
2.2.9 Code Division Multiple Access (CDMA) and Frequency hopping .............................26
2.2.10
Pseudolite error sources.................................................................................................27
2.2.10.1
Multipath .................................................................................................................27
2.2.10.2
Solution for the multipath problem ....................................................................27
2.2.10.3
The Near/far problem ..........................................................................................27
2.2.10.4
Solution for the Near/far problem .....................................................................28
2.2.10.5
Power tuning...........................................................................................................28
2.2.10.6
Out of band transmissions ...................................................................................28
2.2.11
The time tag problem .....................................................................................................28
2.2.12
Differences between PL CDGPS and Global CDGPS ............................................29
2.2.13
Carrier phase ambiguity Resolutions............................................................................29
2.2.14
A simple Pseudolite Architecture .................................................................................29
2.2.14.1
The PLL circuit ......................................................................................................30
2.2.14.2
The C/A code generator.......................................................................................34
2.2.14.3
The mixer, antenna and filter ...............................................................................34
2.2.15
Pulsed Pseudolite Architecture .....................................................................................34
2.3
GPS Transceivers.....................................................................................................................35
2.3.1 The Transceiver Architecture ............................................................................................35
2.3.2 Self Calibrating Pseudolite Array (SCPA) ........................................................................36
2.3.2.1 Bidirectional Ranging.................................................................................................37
2.3.2.2 Bidirectional Ranging equations...............................................................................38
2.3.2.3 Self-Calibrating............................................................................................................39
2.3.2.4 Self Calibrating methods ...........................................................................................39
2.3.2.5 System calibration problems .....................................................................................40
2.3.2.6 Other error factors .....................................................................................................41
2.4
GPS Synchrolites......................................................................................................................42
2.4.1 Synchrolite Reflection Delay..............................................................................................42
2.4.2 Navigation with the aid of one synchrolite......................................................................43
2.4.3 Simple Synchrolite architecture .........................................................................................43
2.5
Locata positioning system.......................................................................................................45
2.5.1 LocataLite .............................................................................................................................45
2.5.2 Locata ....................................................................................................................................45
2.5.3 LocataNet .............................................................................................................................45
2.5.4 Navigation Algorithm used for navigation in LocataNet ..............................................45
2.5.5 The TimeLoc technique .....................................................................................................47
2.6
Hammerhead ............................................................................................................................51
3
Our Prototype....................................................................................................................................52
3.1
Design ........................................................................................................................................52
3.1.1 The first PLL Design ..........................................................................................................52
3.1.1.1 uPB1507GV Prescaler fromNEC............................................................................52
3.1.1.2 MC145151-2 Frequency Synthesizer from Motorola............................................53
3.1.1.3 M3500-1324 micro wave VCO from Micronetics.................................................54
3.1.1.4 Loop filter....................................................................................................................55
3.1.2 The second PLL design ......................................................................................................56
3.1.2.1 ADF4360-4 Integrated Synthesizer from Analog Devices ..................................56
3.1.2.2 Passive loop filter........................................................................................................58
3.1.2.3 The programmable data input ..................................................................................58
3.1.3 The C/A code generator ....................................................................................................63
3.1.4 Mixer......................................................................................................................................66
3.1.5 Printed Circuit board (PCB) design ..................................................................................67
3.1.5.1 Components ................................................................................................................67
3.1.5.2 Circuit board design ...................................................................................................68
3.2
Simulation and synthesizing ...................................................................................................71
3.2.1 Simulations of the first PLL circuit...................................................................................71
3.2.2 Simulation of the second PLL circuit ...............................................................................72
3.2.3 Synthesizing of the C/A code generator..........................................................................72
3.3
Results and Further work with the prototype......................................................................72
4
Recommendations for HTC Sweden AB ......................................................................................73
4.1
Interesting techniques and costs ............................................................................................73
4.1.1 Self Calibrating Pseudolite Array.......................................................................................73
4.1.1.1 Advantage ....................................................................................................................73
4.1.1.2 Disadvantage ...............................................................................................................73
4.1.1.3 User- friendly...............................................................................................................73
4.1.1.4 Estimated costs ...........................................................................................................74
4.1.2 Locata Navigation System..................................................................................................74
4.1.2.1 Advantage ....................................................................................................................74
4.1.2.2 Disadvantage ...............................................................................................................74
4.1.2.3 User-friendly................................................................................................................74
4.1.2.4 Estimated costs ...........................................................................................................75
4.1.3 Asynchronous Pseudolite Navigation System.................................................................75
4.1.3.1 Advantage ....................................................................................................................75
4.1.3.2 Disadvantage ...............................................................................................................75
4.1.3.3 User- friendly...............................................................................................................75
4.1.3.4 Estimated costs ...........................................................................................................75
4.2
Further work .............................................................................................................................76
4.2.1 Continuing the project ........................................................................................................76
4.2.2 Continuing the project reinforced with M.Sc candidates ..............................................76
4.2.3 Continuing the project reinforced with consultancy ......................................................76
4.2.4 Outsourcing..........................................................................................................................76
4.2.5 Joint Venture ........................................................................................................................76
4.3
Comments .................................................................................................................................77
4.3.1 Usage of the Hammerhead ................................................................................................77
4.3.2 Using transceivers and SCPA ............................................................................................77
4.3.3 Considering other frequencies ...........................................................................................77
Glossary .......................................................................................................................................................78
Bibliography ................................................................................................................................................80
Appendix A .................................................................................................................................................82
Appendix B .................................................................................................................................................84
Appendix C .................................................................................................................................................85
Appendix D.................................................................................................................................................86
Appendix E .................................................................................................................................................89
Appendix F..................................................................................................................................................90
Appendix G.................................................................................................................................................91
Appendix H.................................................................................................................................................95
Appendix I.................................................................................................................................................103
Appendix J.................................................................................................................................................108
List of Figures
Figure 1: GPS Code generator........................................................................................................................................................... 4
Figure 2: P-code formulation.............................................................................................................................................................. 5
Figure 3: X1A and X2A register polynomials and the initial values................................................................................................. 5
Figure 4: X1A Shift register............................................................................................................................................................. 6
Figure 5: X1B Shift register.............................................................................................................................................................. 6
Figure 6: The X2A and X2B registers and their initial values........................................................................................................... 7
Figure 7: X2A Shift register............................................................................................................................................................. 7
Figure 8: X2B Shift register.............................................................................................................................................................. 8
Figure 9: C/A code generation polynomials ....................................................................................................................................... 8
Figure 10: G1 shift register ............................................................................................................................................................... 9
Figure 11: G2 shift register ............................................................................................................................................................... 9
Figure 12: Pseudorange model one.................................................................................................................................................... 10
Figure 13: Pseudorange model two (WGS 84 model) ....................................................................................................................... 11
Figure 14: 2D Trilateration by knowing the three distances R1 , R2 and R3 . ................................................................................ 12
Figure 15: Single- and double differencing illustration ....................................................................................................................... 14
Figure 16: Single and double differencing equations........................................................................................................................... 15
Figure 17: Carrier phase measurements............................................................................................................................................ 16
Figure 18: INC200 Pseudolite from IntegriNautics......................................................................................................................... 19
Figure 19: BPSK modulation.......................................................................................................................................................... 19
Figure 20: Helix antenna VS commercial patch antennas................................................................................................................ 20
Figure 21: The Pseudolite pole......................................................................................................................................................... 21
Figure 22: Asynchronous pseudolite system....................................................................................................................................... 22
Figure 23: Synchronous pseudolite system ......................................................................................................................................... 23
Figure 24: Inverted pseudolite systems .............................................................................................................................................. 24
Figure 25: TDMA pulsing............................................................................................................................................................. 26
Figure 26: Frequency hop functional block diagram.......................................................................................................................... 26
Figure 27: Near/far problem illustration......................................................................................................................................... 27
Figure 28: A simple pseudolite block diagram overview..................................................................................................................... 29
Figure 29: The PLL block architecture ........................................................................................................................................... 30
Figure 30: Lead- and Lag signal generation in the phase detector...................................................................................................... 31
Figure 31: A simple phase detector architecture built by two Flip-flops and an AND gate................................................................. 32
Figure 32: Charge pump illustration................................................................................................................................................ 32
Figure 33: A simple loop filter......................................................................................................................................................... 33
Figure 34: Divider consisting of three Flip-flops................................................................................................................................ 33
Figure 35: Pulsed pseudolite block diagram...................................................................................................................................... 34
Figure 36: Transceiver Architecture ................................................................................................................................................. 35
Figure 37: SCPA system overview................................................................................................................................................... 36
Figure 38: Bidirectional ranging using self differencing....................................................................................................................... 37
Figure 39: Bidirectional ranging equations ....................................................................................................................................... 38
Figure 40: Example of synchrolite outdoor navigation system ............................................................................................................ 42
Figure 41: Navigation with the aid of one Synchrolite....................................................................................................................... 43
Figure 42: Synchrolite functional block diagram ............................................................................................................................... 43
Figure 43: The LocataNet navigation algorithm .............................................................................................................................. 45
Figure 44: The clock bias and ambiguity errors ................................................................................................................................ 46
Figure 45: LocataNet establishment step one. .................................................................................................................................. 47
Figure 46: LocataNet establishment step two. .................................................................................................................................. 47
Figure 47: LocataNet establishment step three. ................................................................................................................................ 48
Figure 48: LocataNet establishment step four. ................................................................................................................................. 48
Figure 49: LocataNet established .................................................................................................................................................... 49
Figure 50: LocataNet establishment indoors .................................................................................................................................... 49
Figure 51: Example of indoor navigation using Locata and LocataNet ............................................................................................ 50
Figure 52: Augment to the global GPS system................................................................................................................................. 50
Figure 53: PMB2520 in a 48 pin Very thin Quad Flat Pack Non leaded standard chip package (VQPN-48) ............................. 51
Figure 54: The prototype functional block diagram ........................................................................................................................... 52
Figure 55: First PLL design overview.............................................................................................................................................. 53
Figure 56: MC145151DW Motorola PLL synthesizer in a SOG Package.................................................................................... 53
Figure 57: Filter calculations........................................................................................................................................................... 55
Figure 58: Functional block diagram of the ADF4360-4 circuit...................................................................................................... 56
Figure 59: The output frequency calculation...................................................................................................................................... 57
Figure 60: Passive loop filter and coupling to VTUNE ...................................................................................................................... 58
Figure 62: The Control latch........................................................................................................................................................... 59
Figure 63: The N counter latch ....................................................................................................................................................... 61
Figure 64: The R counter latch........................................................................................................................................................ 62
Figure 65: The first C/A- code generator ........................................................................................................................................ 63
Figure 66: The second C/A- code generator ..................................................................................................................................... 64
Figure 67: The third C/A code generator ........................................................................................................................................ 65
Figure 68: The fourth C/A code generator....................................................................................................................................... 65
Figure 69: Xilinx ISA simulation of the fourth code generator ......................................................................................................... 66
Figure 70: Mixer overview............................................................................................................................................................... 66
Figure 71: The RF2638 package and functional block diagram....................................................................................................... 67
Figure 72: Component schematic part .............................................................................................................................................. 67
Figure 73: Footprint for the TCXO................................................................................................................................................ 68
Figure 74: Schematic design of the pseudolite with the first PLL circuit ............................................................................................. 69
Figure 75: Schematic design of the pseudolite with the second PLL circuit.......................................................................................... 69
Figure 76: The layout of the pseudolite PCB with the first PLL....................................................................................................... 70
Figure 77: The layout of the pseudolite PCB with the second PLL .................................................................................................. 70
Figure 78: Simulink Model of the first PLL circuit ......................................................................................................................... 71
List of Tables
Table 1: The possible factors R........................................................................................................................................................ 54
Table 2: Table of possible values P/P+1......................................................................................................................................... 57
Table 3: The latches VS The control bits......................................................................................................................................... 59
Table 4: Possible values of charge pump current ( I CP ) .................................................................................................................... 60
Table 5: Output power level of the VCO ......................................................................................................................................... 60
Table 6: Core power levels of the ADF3460-4 inbuilt VCO .......................................................................................................... 61
1
1.1
Introduction
Motivation
This Master of Science thesis was written by the students Rikard Eriksson and Vlad Badea for
their Master of Science Degree in Electronics Design. The thesis was conducted at HTC Sweden
AB in order to give HTC some recommendations for further development of an indoor
pseudolite navigation system. If the study of the different systems suggests that it would be
possible to use them or some of them for HTC agenda, then a prototype might be considered.
That is if time permits since the project only lasts for five months. The project specification is
found in appendix A.
1.2
Background
The authors of this thesis had finished their fourth and final year on the Master of Science
program Electronics Design, at Linköping University Sweden. This thesis concludes their degrees
upon completion. The authors had good prior knowledge in RF-technique and sophisticated
electronic design but had no prior experience of GPS systems. It was therefore necessary to
collect information in this field before the project was initialized.
1.3
Outline of this report
Chapter 2 is the literature study and begins with basic theory about the global positioning system
(GPS). This theory was necessary since indoor and outdoor navigation systems have many
similarities. The pseudolite and its applications are then introduced. Synchrolites, transceivers and
LocataLites come next and those are pseudolite enhancement. The enhancements are similar to
pseudolites but more advanced and their applications are of course also introduced. Chapter 2
ends with a short briefing of the Hammerhead chip.
The facts in the pre study suggested that it was possible to build a simple pseudolite prototype
and chapter 3 describes how this prototype was designed and simulated. The resulting prototype
and the future work with it is also found in chapter 3. Chapter 4 concludes this master thesis and
contains recommendations for HTC Sweden AB.
A Glossary can be found in the end of this thesis. This glossary should give the reader some help
in understanding difficult terms.
1
2
The literature study
This literature study was conducted in order to collect enough information for the authors to
consider a prototype design and be able to give HTC Sweden AB some recommendations about
the use of pseudolite based indoor navigation techniques.
Since pseudolites are miniature GPS signal generators it is convenient to understand the GPS
system. An introduction of GPS is therefore conducted in order to give the reader a good basic
knowledge of GPS. The GPS system has over the years been improved into the more accurate
DGPS and CDGPS. Since their improvements also have affected the pseudolite based
techniques, those techniques are introduced as well.
The pseudolite based indoor navigation techniques, discovered during the literature study, differs
a bit from each other depending on what sort of transmitting device is used. Those devices are
pseudolites, synchrolites, LocataLites and transceivers.
This chapter ends with a short briefing on the Hammerhead chip, which is not a pseudolite based
transmitter but is a GPS receiver so sensitive that it can be considered for indoor navigation
systems.
2.1
The Global Positioning System (GPS)
[4] The GPS (Code-phase GPS) system was initialized by the United States Department of
Defence in 1978 when the first satellite was launched. Today the system consists of 24 orbiting
satellites which are replaced over time. These satellites orbit in 12 hours and are placed at an
altitude of approximately 20 000 km. The satellites are placed in six different orbital planes which
means that at least four or more satellites are visible in the sky at the same time, anywhere on
earth.
[1], [2] The satellites altitude is relatively far away relatively to any receiver on earth. This is a
good thing since the signals time delays are used for estimation of distance. The GPS satellite is
basically a radio wave transmitter which transmits signals at the speed of light to receivers on
earth. The receivers have a built in almanac in their software in order to keep track of the
satellites current positions. Since the altitude, speed and orbit may differ a little bit, very precise
radar measurements are conducted from control stations by the United States Department of
Defence.
The satellites are continuously monitored from the different monitoring stations on earth. The
monitoring stations measure the signals from the satellites and compute exact orbital data and
clock corrections for each satellite every few minutes. The orbital data is called ephemeris. The
computed data is then transmitted to the satellites at least once a day. The satellites then forward
the received data to the receivers as part of the GPS navigation satellites broadcasting.
The exact position is sent back to the satellite itself and the satellite then includes this new
corrected position information in its broadcasted timing signals. The receiver can now eliminate
the satellites incorrectly position and derive a more accurate position. Other errors are multipath
and the delays of the GPS signal through the ionosphere and atmosphere.
2
2.1.1
GPS signal
[2] The GPS uses low power radio signals. Radio waves are electromagnetic energy and travel
with the speed of light. The speed of light is [3] 299792458 meter per second. The GPS signal
consists of carrier frequencies and pseudorandom codes. The GPS signals have the L-band
standard carrier frequencies L1, L2 and L3.
2.1.1.1
L1, L2 and L3 Carrier waves
Right now there are 3 carrier frequencies in use. The frequencies are L1 at 1575.42 MHz, L2 at
1227.60 MHz and the new frequency L3 at 1176.45MHz. [6] Receivers that track only the L1
frequency are called single frequency receivers. Receivers which can track both the L1 and L2
frequency are called dual frequency receivers. The L2 frequency is not entirely available to the
general public but there are techniques to extract the code and carrier from the L2 signal.
2.1.1.2
Pseudo- Random codes
[1],[4] The pseudo- random code is a very complex digital code that looks almost like random
electrical noise and therefore it is called pseudo- random. This ensures that the receiver doesn’t
accidentally pick up the wrong satellite signal. The pseudo- random code is used like an ID-card
for each GPS satellite.
There are two kinds of pseudo- random codes. The first is called Coarse/Acquisition (C/A) code
and the other is called P code. C/A codes are chosen from the so called “Gold codes”. The Gold
codes are a set of codes that have their auto-correlation and cross-correlation properties well
defined.
The P code is used by the military and can some times be encrypted. The P code is modulated at
a rate of 10 MHz on both the L1 carrier frequency and the L2 carrier frequency.
[6] The C/A code stands for Coarse/Acquisition code and is a repeating pseudorandom code.
The C/A codes are chosen from a family of 1023 “Gold codes” based on maximal-length linear
feedback shift register codes. Every C/A- code is 1023 chips long. The chip is an individual bit of
the sequence of 2 k − 1 where k is the number of bits in the shift register. 32 of these codes have
been allocated for the GPS satellites and 4 are allocated for use by pseudolites. There are as many
as 511 codes that can be used. The remaining 512 codes can’t be used because the codes aren’t
balanced. The unbalanced codes are harder to modulate and are vulnerable to narrow- band
interference. The C/A code is modulated at a rate of 1 MHz on the L1 carrier frequency.
[6] When transmitted the C/A codes repeat exactly at 1000 time per second which means that the
code is transmitted at a speed of 1.023 * 10 6 chips per second. When the signal is sent, the
message is added bit by bit with the batch of 20 epochs of the C/A code. This signal is then
modulated by the use of binary phase shift keying onto the carrier frequency.
3
2.1.1.3
P(Y) and C/A codes Basics
[4],[5 ],[6] When satellites send their signals on the L1 and L2 carrier bands, the signal is
modulated by so called PRN ranging codes. PRN stands for Pseudo- Random Noise. The PRN is
a very complicated digital code that appears to be random electrical noise but in fact it is not. The
complexity of the PRN is needed to make sure that the receiver does not sync with the wrong
signal. Every satellite has its own pseudo random- noise and therefore it is important that the
user can’t sync up with the wrong satellite. Because of the high complexity of the pseudo random
noise it is highly unlikely that the receiver will sync with the wrong signal. Another good side of
pseudo- random noise is its immunity to jamming. The jamming can either come from another
satellite because the same carrier frequency is used or from a hostile force.
Clk 1.023 MHz
÷ 10
Clk 10.23 MHz
Frequency
divider
G2 Generator
G2(t)
satellite i
G1 Generator
X1 epoch
X2 Generator
X1 Generator
X1(t)
G1(t)
X1 epoch
Delay
di Tg
X2(t)
Delay
i Tp
1.023 Mchip/s rate
1023 chip period =
1ms period
C/A code
Gi(t)= G1(t) XOR G2(t + di Tg)
satellite i
P code
Pi(t)= X1(t) XOR X2(t + i Tp)
10.23 Mchips/s rate
15 345 000 chip period
1.5 s period
10.23 Mchips/s rate
15 345 037 chip period
37 chips longer than
X1(t)
Figure 1: GPS Code generator
2.1.1.4
P(Y) code generator
As mentioned earlier, the P(Y) code is a so called PRN and it modulates both the L1 and L2
carrier frequencies. The P code can be denied to normal users when the control segment activates
an anti-spoofing mode in the satellites. When the anti-spoofing system is activated, the P-code
becomes encrypted and is called Y- code. Therefore when the authors of this thesis refer to the
P- or Y-code they refer to them as the P(Y) -code.
The P(Y) -code is 7 days long and is transmitted with a chipping rate of 10.23* 106 chips per
second. In this case a chip is the same as a bit, but it is not called a bit because the code doesn’t
carry any data. The signal is constructed by a modulo-2 sum of two sub- sequences, the X1 and
the X2i sequences. The X1 sequence is 15 345 000 chips long and the X2i sequence is 15 345 037
chips long.
4
The “i” in the X2i stands for the i’th satellite or pseudolite (1- 37). The X2i sequence is
constructed by delaying the X2 sequence by 1 to 37 chips yielding the ability to generate 37
mutually exclusive P- codes. 32 of those codes are reserved for the satellites and the rest are
reserved for other purposes like pseudolites. The P-code is created by the following formula.
Pi(t) = modulo- 2 sum of X1 and X2(i- iT)
Where
T = an P(Y)- code chip period and it is equal to (1.023 *107)-1 seconds
i = an integer between 1 and 37 depending on the sender
Figure 2: P-code formulation
X1 is generated by the modulo- 2 sum between the outputs of two 12- stage registers named
X1A and X1B. The X1A register is short cycled to 4092 and the X1B register is short cycled to
4093.
When X1A’s short cycles are counted up to 3750 the X1 epoch is generated. An X1 epoch occurs
every 1.5 seconds. This occurs after 15 345 000 chips are generated. The X1A and the X1B
registers have the following polynomials and initial values.
X1A: 1 + Χ 6 + Χ8 + Χ11 + Χ12
X1B: 1 + Χ1 + Χ 2 + Χ 5 + Χ8 + Χ 9 + Χ10 + Χ11 + Χ12
The initial value ends with Least Significant Bit (LSB).
X1A: 001001001000
X1B: 010101010100
Figure 3: X1A and X2A register polynomials and the initial values
The creation of these polynomials and the involving registers and modulo-2 operations are
illustrated in the figures below.
5
Stage number
1
0
0
2
0
2
1
4
1
3
0
3
6
0
5
0
4
6
5
8
0
7
1
8
7
10
1
9
0
Output
12
11
10
9
12
0
11
0
Tap numbers
Initial value
LSB
Shift direction
Figure 4: X1A Shift register
Stage number
1
0
0
2
0
1
4
0
3
1
2
3
6
0
5
1
4
5
8
0
7
1
6
8
7
10
0
9
1
9
12
0
11
1
10
11
Output
12
Tap numbers
Initial value
LSB
Shift direction
Figure 5: X1B Shift register
The period of the X1 is defined as 15 345 000 chips (3750 X1A cycles). That is not an integer
number of the X1B cycles. Therefore the X1B shift register is kept in its final state (chip 4093) of
the 3749th cycle. When the 3750th cycle of the X1A (343 additional chips) is completed a new
X1 epoch is established and the X1A and X1B registers are reinitialized so a new X1 cycle is
started.
The X2i sequences are generated by generating the X2 sequence and then delaying it by a number
between 1 and 37 of chips. By doing so, 37 different sequences are generated. Every X2i sequence
is then modulo- 2 added to the X1 sequence to produce a unique P(t) sequence as showed earlier.
The X2A and X2B sequences are also short- cycled to 4092 and 4093 respectively.
6
The precession rate is the same as for the X1 registers. As for the X1 registers, the X2A epochs
are counted to include 3750 cycles. The X2B register is held at 3749 cycle until the 3750th cycle
of the X2A register is completed. The X2A and X2B polynomials and the initial values are shown
in the figure below
X2A: 1 + Χ1 + Χ 3 + Χ 4 + Χ 5 + Χ 7 + Χ8 + Χ 9 + Χ10 + Χ11 + Χ12
X2B: 1 + Χ 2 + Χ3 + Χ 4 + Χ8 + Χ9 + Χ12
The initial values end with LSB.
X2A: 100100100101
X2B: 010101010100
Figure 6: The X2A and X2B registers and their initial values
The creation of these polynomials and the involving registers and modulo-2 operations is
illustrated in the figures below.
Stage number
1
1
0
2
0
1
4
0
3
1
2
3
6
1
5
0
4
5
8
0
7
0
6
8
7
Initial value
LSB
Shift direction
Figure 7: X2A Shift register
7
10
0
9
1
9
12
1
11
0
10
11
Output
12
Tap numbers
Stage number
Output
1
0
0
LSB
2
0
1
4
0
3
1
2
3
6
0
5
1
4
6
5
8
0
7
1
9
1
8
7
10
0
9
12
0
11
1
10
11
Tap numbers
12
Initial value
Shift direction
Figure 8: X2B Shift register
The X2A and B epochs with respect to the X1A and B epochs so that the X2 period is longer
then the X1 period with 37 chips. The X1A, X1B, X2A and X2B are reinitialized at the beginning
of the week so the first chip of the week can be produced. All the shift registers are timed with
respect to the X1A register. X1B, X2A and X2B are held in their last state of their cycles until the
last X1A cycle in the last period of the GPS week interval is completed. When that occurs all four
shift registers are reinitialized so the first chip of the next week can be provided.
2.1.1.5
C/A code generator
The C/A is also a ranging code but it is only modulated on the L1 carrier frequency. The C/A
code is usually used to acquire the P(Y) code. The C/A code is a Gold code (Gi) with a length of
1023 chips. Because the chipping rate of the C/A code is 1.023 MHz the period of the sequence
is 1 millisecond. The Gi epoch is synchronized with the X1 epoch from the P(Y) code.
The Gi(t) sequence is generated by the modulo- 2 sum of two 1023- chip linear sub- sequences
G1 and G2i. The same way as for the P(Y) code, the G2i sequence is formed by delaying the G2
sequence. The delay is by an integer number of chips between 5 and 950. In this way the system
generates 36 different C/A codes (code 34 and 37 are identical). The C/A codes 33 through 37
are reserved for ground transmitters, the rest are used for the satellite system. The G1 and G2
sequences are generated by 10 stage shift registers with the following polynomials:
G1: 1 + Χ 3 + Χ10
G2: 1 + Χ 2 + Χ 3 + Χ 6 + Χ8 + Χ 9 + Χ10
G1 and G2 have the initialization vector: 1111111111.
Figure 9: C/A code generation polynomials
8
Stage number
1
1
2
1
0
4
1
3
1
2
1
6
1
5
1
3
4
8
1
7
1
6
5
10
1
9
1
8
7
Output
10
9
Tap numbers
Initial value
LSB
Shift direction
Figure 10: G1 shift register
Stage number
1
1
0
2
1
1
4
1
3
1
2
3
6
1
5
1
4
5
8
1
7
1
6
8
7
10
1
9
1
9
Output
10
Tap numbers
Initial value
LSB
Shift direction
Figure 11: G2 shift register
The G1 and G2 shift registers are initialized at the P(Y) code X1 epoch. This is done to make
sure that the first chip of the C/A code begins at the same time as the first chip of the P(Y) code.
The delay of the G2 sequence to form the G2i sequence is done by the modulo- 2 addition of the
output from two stages of the G2 shift register.
9
2.1.2
Distance measuring
Since distance is velocity multiplied with time, time variations in signals can give us the distance
since we know radio signals travels with the speed of light. The main problem with the distance
measuring is that the satellites are not stationary but moving all the time. The main idea is very
simple, we know the speed of light and we can measure the time it takes for the signal to reach
the receiver. This gives us the possibility to calculate the distance from the satellite to the
receiver. The tricky part is to find out exactly how long time it takes for the signal to travel from
the satellite to the receiver since many errors are associated with this kind of measurement.
2.1.2.1
Pseudorange measurements
[4],[6] The satellite broadcasts a GPS signal (pseudorandom code) while the receiver generates a
copy at the same time. Since the satellite signal has to travel a long distance, there will be a delay
between the satellites broadcasting and the receiver’s local copy. The receiver can then overlap
the signals and measure the time delay between them. This time delay is the time it took for the
satellites signal to reach the receiver. Now we can calculate the distance between the receivers
and the satellite. This kind of measurement does not calculate with errors and pseudorange alone
will give us a position which is inaccurate with 10-15meters due to errors.
[23] The pseudo range measurement can be illustrated by the following equation. The error
sources in this equation will be introduce later in this thesis.
Figure 12: Pseudorange model one
10
When using World Geodetic System 1984 (WGS 84 model) the Pseudorange measurement can
be illustrated in x-y-z coordinates.
Figure 13: Pseudorange model two (WGS 84 model)
2.1.3
Trilateration
[1],[2] Each satellite’s distance is measured by the receiver and since we know the exact location
of the satellites it is possible to calculate the receivers exact position. Trilateration is sometimes
called triangulation which can be misleading since the triangle symmetry has nothing to do with
this concept.
2.1.3.1
2D Trilateration
The receiver has the ability to calculate the distance to any satellite visible in the sky or ground
base pseudolites. The receiver knows the distance but does not know from which direction the
signal comes from. In 2D navigation we can illustrate those distances as circles with the satellite
in the middle and the satellites distance to the receiver as radiuses R j in x-y direction. If the
receiver picks up three signals and calculates the distance in the x-y plane, then our position will
be somewhere where these distances match. We draw a circle with the distance R j for every
received signal and can determine our position in 2D. Our positioning will be the point of
intersection of the circles as illustrated in figure 14.
11
Figure 14: 2D Trilateration by knowing the three distances R1 , R2 and R3 .
2.1.3.2
3D Trilateration
The distance from a satellite can be illustrated as a sphere with a radius equal to the distance. The
intersection of three spheres gives us a volume with two points of intersection between these
radiuses. When looking at these points one point will be in space while the other will be on earth.
If you place a receiver on the surface of earth, then you expect the receiver to give you a location
on earth and not in space. One point can therefore be disregarded by the receiver. This concept
uses earth as a fourth sphere. If we receive distances from four or more satellites then we will
only end up with one intersection between the spheres. If the spheres do not intersect in only
one point, then we know that we have encountered an error.
2.1.4
GPS Clocks
In the previous parts we assumed that the satellites and the receiver’s clocks are synchronic. This
since a small difference in their clocks will yield very big distance errors. The clocks in the
receivers are not of the same type and will differ a lot and yield great accuracy errors if the clock
drift is not dealt with.
2.1.4.1
GPS Satellite clocks
The satellites are equipped with very precise clocks. The high accuracy is needed since one
nanosecond of inaccuracy yields about 30cm of error in the measurement of the distance
between the satellite and the receiver. Hence that the speed of light is c=299792458 meters per
second and we know that distance is how long something move at a given velocity. A clock drift
of one nanosecond multiplied with the speed of light gives us an error of 0.299792458 meter
which is about 30 centimetres.
[1] Atomic clocks use oscillations of a particular atom (Cesium) in order to form timing. This
kind of clock is very stable and accurate. It is considered to be the most accurate clock developed
by man. [6] Despite their accuracy, these clocks still have a small clock drift of about one
nanosecond every third hour. This clock drift is monitored by ground stations with even more
accurate clocks built of combinations of more than 10 atomic clocks. The clock drift is then
broadcasted to nearby receivers, which can subtract these relatively small clock errors from their
distance calculations.
12
2.1.4.2
GPS Receiver clocks
[6] Since the distance measurements are based on time delays between the satellite’s broadcasted
signal and the receiver’s local copy, inaccuracy in reciver clocks will also give measurement errors.
If the receiver clock has an error of one millisecond it would approximately give a 300000 meter
error in the distance measurement. (The speed of light is approximately 300,000km per second.)
Atomic clocks are very expensive (cost about US$50000) and the receivers would become to
expensive if they where equipped with those clocks. [1] Therefore receiver clocks have to correct
their clocks every second with an extra satellite range measurement correlation. How these
correlations are measured will be explained shortly.
[2] When the receiver measures the distance to four satellites it draws four spheres that should
intersect in one point. Three spheres will intersect even if your numbers are wrong but four
spheres will not intersect. Since the receiver uses its own built in clock when measuring all
distance to the satellites, the errors in distance measurements will be proportional incorrect. The
receiver can therefore make some adjustments so all four spheres will intersect in one point.
Based on this the receiver now resets its own clock to be in synch with the satellites more
accurate atomic clock. Since this operation is preformed every second, the receiver clock will be
almost as accurate as the atomic clock in the satellite.
2.1.5
Geometric Dilution of Precision (GDOP)
[8] This is a valued factor that is determined by how good the geometry of the above satellite
constellation is. Bad geometry gives less measurement and therefore yields a high value of
GDOP. The GDOP parameters in 3D are latitude, longitude, height and clock offset. What is
necessary to know about GDOP is that a good geometry is important. A good spread of the
satellites gives a lower GDOP and the other way around. This concept is basically the same for
the pseudolite based techniques described later in this thesis
2.1.6
Code phase
[1],[9] Since distance between a satellite and a receiver is measured by calculating how long it
takes for the satellites signal to reach the receiver. The exact position of the satellite’s are known
and it’s signal travels with the speed of light. So the question is how do we measure the time for
the satellites signal to reach the receiver. The satellites signal contains a pseudorandom code
which is unique. All receivers have copies of all satellite codes and can distinguish which satellite
they are receiving from and since they have built in calendars they also know the satellites
positions. The satellite and the receiver start generating the same code at the same time. Their
clocks must be synchronous and this is made possible by correlations broadcasted from the
satellite itself. The receiver compares the incoming code from the satellite with its own generated
copy. The delay in the code is then multiplied with the speed of light and the receiver then knows
the distance to the satellite. This method is called code phase and gives a precision in range of
approximately 0.5 meters in vacuum. Code phase patterns are almost unlimited because the code
patterns are long and we don’t have an initial unknown integer.
13
2.1.7
Differential Code-phase GPS (DGPS)
[2],[6],[9] As mention earlier, GPS system with only satellites and receivers isn’t very precise. It is
accurate up to approximately 10 to 15 meters. In order to make this system more accurate, exact
positioned reference stations are used. These stations are located at exact known positions and
when they receive signals from the satellites they can triangulate their positions. Their exact
location is then compared with the triangulated location. By doing so the reference station knows
how much the positioning of the GPS system is off. The reference station broadcasts corrections
to all receivers in the area and the receivers can then subtract these errors from its own measured
position and then end up with a more accurate position. The differential mode will remove most
of the errors except multipath. Multipath is a local phenomena that differs from different
locations of the receivers. Multipath is described later in this thesis.
Single differencing
Corrections
Reciever
Reference station
Double differencing
Corrections
Receiver
Reference station
Figure 15: Single- and double differencing illustration
The distance between the reference station and the receiver is often called a base line. Since the
reference station sends corrections and the distance to the receiver will yield a small time delay. A
rule of thumb is that you will get an additional error of 1cm for every kilometre of base line.
14
Single differencing is when we have one satellite, one reference station and one receiver
Double differencing is when one receiver, two satellites and one reference station is used. The
mathematical pseudo range expressions for single and double differencing are shown in the figure
below. These equations are further explained in [23].
Figure 16: Single and double differencing equations
2.1.8
Carrier- phase Differential GPS (CDGPS)
The normal GPS receiver measures the C/A code chip and cycle of the L1 carrier frequency. The
code chip is approximately 293 meters long and the L1 carrier frequency is about 19 cm long.
Carrier- phase has a theoretical precision of about 1 mm and the Code- phase has a theoretical
precision of about 0.5 meters.
By looking at the numbers, Carrier- phase is much more superior then Code-phase and normally
should be used all the time. But that is not the case because the Carrier- phase has the problem of
ambiguity.
Carrier- phase is only used in differential GPS, which means that a reference station must be at a
known location. But line of sight from the reference station is not needed within 30 km from the
reference station if special carrier tracking receivers are used [10].
When tracking carrier- phase signals there is no timing information in the signals. The carrier
signals do not carry any information that could be used to distinguish the cycles from each other.
The whole idea of the carrier-phase is that the receiver counts the number of cycles between the
sender and receiver. As mentioned earlier the carrier frequency is not unique and therefore hard
to count.
When using Carrier- phase, the system uses Code phase to get close to the position and then uses
Carrier- phase to get near within centimetre accuracy. By doing so it is easier to count the cycles
of the carrier frequency because there are only a few wavelengths to consider. [1]
[6] The receiver can measure the amount of complete cycles and the fractional phase of the signal
but the exact number of cycles in the pseudorange cannot be exactly counted. That is called
integer cycle ambiguity.
15
The counting of the cycles is done by looking at how many times the carrier phase passes zero.
When it passes zero and goes on the positive side, the receiver increments its counter, when it
passes towards the negative side, it decreases the counter. The relative carrier phase is the
instantaneous value of the counter and the fractional phase. This is called ADR (Accumulated
Delta Range) or integrated Doppler. The integer ambiguity is the difference between the relative
carrier phase and the pseudo range at any given time.
[55] The maths behind carrier phase measurements is illustrated below. The carrier phase
ambiguity must be resolved before these measurements can be done. Carrier phase ambiguity is
explained later in this thesis. The error sources must also be known. Remember from the
pseudorange calculations that dρ S , dt S , dTr and c are orbital error term, the satellite clock error,
receiver clock error and the speed of light constant c.
Figure 17: Carrier phase measurements
We must also know the errors due to receiver noise and multipath. These errors can sometimes
be hard to resolve completely since they vary a lot while the receiver moves.
2.1.8.1
Carrier Phase Ambiguity
[6],[7] When the satellites are sending the signals, the carrier frequency repeats itself many times
before the receiver gets the signal. The problem is that the frequency cycles are not different
from each other. Therefore it is impossible to know when the sender started sending. The only
thing that the receiver can find out is the fractional phase.
When the satellites move away from the receiver the delay starts to grow until one cycle is passed.
The receiver knows that because it has been following the signal from the sender continuously.
As the satellites move away from the receiver more and more the signal gets delayed and more
cycles are known. This way the receiver finds out a part of the unknown integers. As long as the
receiver keeps continuous track of the satellites, all the distances that the receiver measure every
second contain the same initial unknown integer. The whole idea is that as long as the satellites
are tracked, the receiver has to deal only with one initial unknown integer. With carrier-phase it is
very important to keep track of all cycles.
16
A cycle slip is when the receiver miscalculates the amount of cycles, either by missing a cycle or
by adding an extra cycle. Cycle slip can occur when background noise interfere with the signal.
Not all receivers are able to use carrier- phase.
2.1.8.2
Carrier Phase Ambiguity Resolution
There are four different methods presented in this thesis, to compute the integers (ambiguity).
These methods are brute force search, filtering, geometrical and RTK. All the methods must start
with an estimation of the position or a trajectory. The estimation is usually made with codephase measurements. The search and filtering methods needs an estimation of the error in the
initial position estimation.
Brute Force Search methods use the estimations to create a so called search space of all possible
integer combinations. When positions are estimated with aid of the integer combinations, large
least-squares residuals will be generated. A predefined threshold can be used to decide if the
residuals are incorrect or not. The residuals are discarded if they are incorrect. As time passes by
and the satellites pass by more and more of the residuals are discarded and the only remaining
integers are the correct ones.
The idea of this method is to use several measurements from each satellite’s code phase pseudo
ranges to form an accurate measurement. The noise level will decrease with 1 / m where m is
the number of independent measurements. The noise level must be reduced to less than the
length of a carrier. By doing so, the carrier phase integers can be determined.
Usually the filtering methods perform poorly, especially when used alone.
By combining several sets of simultaneous code- and carrier phase measurements both the
position or trajectory correction and integer ambiguities can be computed. The measurements
must be taken separated in time so that the satellites line of sight vectors are sufficiently different.
By taking measurements to close to each other in time not enough new information is gathered
and the position and integer ambiguities cannot be solved. The solution given by Geometrical
methods gives DOP’s for the position and integers.
To solve the ambiguity problem much faster, up to ten times faster, measurements on both
frequencies (L1; L2) can be carried out. The technique is called wide- laning. But the drawback is
that dual receivers must be used, dual receivers are more expensive.
[8],[11] Real time refers to immediate GPS data collection and the following processing and
determination of the position, usually done by the receiver. Real time does not use a computer
outside the receiver but uses its own circuits. The process is made in real time.
Real Time Kinematics is a DGPS process where carrier phase corrections are transmitted in real
time from a reference receiver at a known location. RTK is often used for carrier phase integer
ambiguity resolution. RTK uses Doppler Effect in order to determine how much out of phase
the carrier wave is. [11] RTK measurements on a moving remote receiver allow centimetre level
relative positioning.
17
2.1.9
Atmospheric errors
[6] The speed of the transmission from the satellite varies a bit with different media. The
atmosphere consists of two layers, the Ionosphere and the Troposphere. Differential GPS
corrections can cancel 1 meter of range error caused by the troposphere and ten meter of range
error caused by the ionosphere. This gives a good idea of the property of these error sources.
2.1.9.1
Ionosphere
[6] The ionosphere contains particles that slow down the code and speed up the carrier. When
using code phase GPS with no reference station, this will yield range errors δ ion greater than ten
meters. The magnitude of the effect of the ionosphere is greater on the day than during the night.
The magnitude also differs in cycles over the year as well. In other words it is a tricky error to
calculate with. Some receivers have mathematical models in order to deal with this problem but
can only reduce the errors by 50 percent.
The frequency is an important factor when dealing with ionosphere caused errors. The higher the
frequency is, the less delay in the code. The L1 frequency (1575.42MHz) and the L2 frequency
(1227.60MHz) codes will be delayed differently. The L2 code will be more delayed than the L1
code. A dual receiver can calculate this delay and then use a known formula for frequency
dependence of the ionospheres delay. A dual receiver can practically remove the errors caused by
the ionosphere.
2.1.9.2
Troposphere
[6] The troposphere is the lower level and consists of water vapour. The water vapour slows
down both carrier and code. These errors cannot be resolved by dual receivers since the delays
don’t depend on frequency as it did for the ionosphere. Instead water vapour, temperature and
pressure are measured. With these measurements and a mathematical formula it is possible to
calculate the delays caused in the troposphere. The distance error δ trop caused by the troposphere
is approximately one meter.
2.1.10
Multipath
[4],[6],[12] Multipath is a big concern when working with GPS systems in suburban environments
or indoor. The problem is if there are obstacles in abundance the signal gets reflected from the
obstacle to the receiver. By doing so the signal gets delayed and eider corrupts the original signal
by interference or because of the longer time of flight it gives the wrong distance between the
satellite and the receiver. If the range of the signal that bounces of the reflectors has a range that
is over ten meters longer then the range of the direct path signal then the multipath effect can be
reduced by the use of signal processing techniques.
There are three possible multipath propagation mechanisms that can interfere with the signal.
The first one is diffraction. Diffraction occurs at the edge of an object that is larger then the
wavelength of the signal and impenetrable. What happens is that when the signal encounters such
an edge the wave propagates in different directions with the edge as a source meaning that signals
can be received by a receiver even when there is no line of sight between the transmitter and the
receiver. Another propagation mechanism is reflection. Reflection occurs when the signal
bounces of a surface, that is larger then the wavelength of the signal. When reflection occurs the
reflected signal is phase shifted 180 degrees and therefore it can cancel the direct signal from the
transmitter to the receiver. When the signal encounters an object that is smaller then the wave of
the signal, the signal scatters. When scattering occurs, the main signal is scattered into several
signals that are much weaker than the original signal.
18
2.2
GPS Pseudolites (PL)
The pseudolite is a signal generator that generates a GPS like signal. The signal sent by the
pseudolites consists of the L1 carrier at 1575.42 MHz, Clear/Acquisition code, and sometimes 50
bps Data message. One of the drawbacks of the pseudolite is that it uses a low-price TCXO
(Temperature Compensated Crystal Oscillator). The INC200 Pseudolite from IntegriNautics is a
complete pseudolite but it is no longer in production. The authors of this thesis weren’t able to
find and buy any pseudolite.
A complete Pseudolite Generator
From IntegriNautics
Figure 18: INC200 Pseudolite from IntegriNautics
The normal, standard pseudolite transmits its signals on the civilian L1 carrier frequency of
1575.42 MHz. On this carrier frequency, the pseudolite modulates the Clear/Acquisition- code or
also called C/A- code. In the signal the pseudolite can also send 50bps data message. The GPS
satellites use very accurate atomic clocks, but the pseudolites use low-price TCXO (Temperature
Compensated Crystal Oscillator). A standard GPS receiver is able to receive the signal from the
pseudolite, but because the signal from the pseudolite is a bit different, the firmware must be
modified.
2.2.1
Pseudolite signals
The pseudolite signal is a lot like the GPS signal. The first pseudolites could not transmit the 50
bits of data as the satellites do but the more recent pseudolites have the ability to transmit signals
with data. The pseudolite signal is very much a like the satellites signal but the pseudolite only use
C/A code transmissions.
2.2.2
Binary phase shift keying (BPSK)
[4] When using radio frequency techniques in order to transmit data in the air, a carrier wave is
needed. The data bits must somehow be attached to this carrier wave. This is called modulation
and there are many different techniques in this area. Pseudolites uses Binary Phase Shift Keying
in order to modulate the data on to the carrier wave. [12] The transmitted signal s(t) consists of
two kinds of signals depending on whether the data is 0 or 1. A is the signal’s amplitude and its
time. f c is the carrier frequency.
⎧ A cos( 2πf c t ) ⎫ ⎧ A cos( 2πf c t ) ⎫ 1
s (t ) = ⎨
⎬=⎨
⎬=
⎩ A cos( 2πf c t + π )⎭ ⎩− A cos( 2πf c t )⎭ 0
Figure 19: BPSK modulation
19
As the figure 19 illustrates, the phase is altered with 180 degrees when the data switches from 1
to 0 and the other way around.
2.2.3
Pseudolite antennas
[13] The two most common transmitting antennas when broadcasting from pseudolites are the
Helix antenna and the micro strip patch antenna. The helix antenna has a good hemisphere
transmitting pattern. This pattern is optimal for pseudolite receivers since the power is greatest in
the transmitting direction and lowest in the orthogonal directions.
Figure 20: Helix antenna VS commercial patch antennas
Signals transmitted from commercial patch antennas, is subject to multipath problems since the
signals bounce on walls and ceilings. Theses signals are delayed and the receiver calculates the
wrong distance to the transmitter.
2.2.4
The pseudolite pole
One thing that has to be taken in concern is the problem of temperature variation. The problem
is that when the system is initialized for the first time the hardware is as cold as the environment
it is placed in. After the system is started the hardware starts to heat up and the frequency will
change with the temperature change. This fact makes the TCXO to be an unstable clock and it
will yield errors in range measurements.
By recalibrating the system within short intervals this problem might be resolved. If the whole
hardware is placed inside a container that is temperature regulated to about twice the working
environment of the system, for example 50° Celsius when the environment temperature is about
20° Celsius, this problem is eliminated. The temperature regulation is achieved by the use of fans
and heat radiators. By doing so an extra amount of energy will be needed and therefore extra
batteries are needed. By temperature regulating all electronics in the indoor navigation system, the
clock biases can be determined and assumed to be constant.
20
Figure 21: The Pseudolite pole
2.2.5
Differential Pseudolite System
The Differential Pseudolite System works the same way as the normal differential GPS system.
That means that the system uses an extra receiver to correct for various errors. The extra receiver
is called reference station and its position is known with high accuracy. The errors in the
measurements are usually due to the clock bias problem. Because the pseudolites use low cost
TCXO‘s instead of expensive atomic clocks there will always be some difference between the
measured distance and the real distance. Because of that exact position of the reference station is
known, the clock bias can easily be eliminated differential methods. The clock bias information is
sent to the receiver by the reference station. When the clock bias is known, the accurate position
of the receiver can be computed.
2.2.6
Difference between Pseudolite CDGPS and Global CDGPS
The biggest difference between Pseudolite CDGPS and Global CDGPS is the geometry of the
system.When working with the Global CDGPS the “on earth” distance between the user and the
reference station is small with regards to the distance between the receiver and the satellites.
Therefore the errors and delays due to the path of the signal through the earth’s atmosphere are
the same for the reference station and the receiver. Pseudolite CDGPS is restricted to a limited
area. Therefore the distance between the pseudolites, the reference station and the receiver can
be about the same length. But in this case there are no significant errors or delays due to the
atmosphere of the earth. The Global CDGPS uses the reference station to compute the
corrections needed for the accurate position of the user. The Pseudolite CDGPS uses the
reference station to compute the pseudolite clock biases.
21
2.2.7
Indoor Pseudolite Navigation Systems
The satellites used for outdoor navigation have internal atomic clocks that are very exact but at
the same time the clocks are very expensive. Therefore the pseudolites don’t use atomic clocks,
instead pseudolites use TCXO clocks. The problem with the TCXO clock is that it is not exact
which yields clock bias errors.
There are two different navigation systems that can be used to cope with the problem of clock
bias errors, the asynchronous and the synchronous systems. There are also inverted systems with
few pseudolites and many receivers.
2.2.7.1
Asynchronous System overview
As shown figure 21 below, the asynchronous system is constructed of pseudolites, a reference
station, and the GPS user. The reference station has the ability to send and receive.
Pseudolite 1
Pseudolite 2
GPS User
Wireless Link
Pseudolite 3
Pseudolite 4
Reference station
Figure 22: Asynchronous pseudolite system
The pseudolites in the asynchronous system use their own clocks. But as mentioned before the
clocks are not exact. Because the system uses pseudolites that use their own clocks, the system is
not synchronized, there by the name asynchronous system. But by using different clocks a
problem comes up, clock bias error. To be able to give the right coordinates we need to remove
these errors somehow. This is done by using a reference station. The positions of the reference
station and pseudolites are well known and we can calculate the pseudolite clock bias errors from
the pseudo range measurements at the reference station. The reference station calculates the
clock bias errors and sends them to the user through wireless data link as shown in the figure
above. After receiving this information from the reference station, the user compensates for the
clock bias errors and calculates its own position.
22
2.2.7.2
Synchronous System overview
The Synchronous pseudolite system consists of a reference station, GPS user, pseudolites, a data
link, and a master pseudolite. The master pseudolite has its own clock much like the pseudolites
in the asynchronous system but the other pseudolites are a bit different. They have digitally
controlled clocks that are used to generate the signal. The reference station sends clock
synchronization command to the “slave” pseudolites via the data link.
Pseudolite 1
Pseudolite 2
GPS User
Reference station
Pseudolite 3
Reference station
Pseudolite 4
Figure 23: Synchronous pseudolite system
By knowing the exact location of the master pseudolite, the reference station and the slave
pseudolites, one can measure the clock synchronization errors between the master pseudolite and
the slave pseudolites. With the measurement errors known, the reference station can generate
clock synchronization commands. Each slave pseudolite sets its own clock after the master’s
clock and the system becomes synchronized. After the synchronization is done, the GPS user can
calculate its position using only the pseudolite signals. This is called stand-alone navigation. In
this system the wireless data link between the reference station and the user is not needed.
23
2.2.7.3
Pseudolite based inverted navigation systems
[14] There are two different pseudolite based inverted navigation systems. Both use a signal
transmitter as reference but the difference is that Type 1 system uses a pseudolite as reference
and the Type 2 system uses a GPS satellite as reference. Both types have the same Dilution of
Precision (DOP) because the value is a function of the receiver and mobile pseudolite array.
The system consists of receivers, a mobile pseudolite and a reference pseudolite/satellite. The
receivers are connected together to form an array which is then connected to a central processing
unit. The central processing unit processes the data received from the array to generate the
navigation solution. The reference pseudolite/satellite is used to form the double-differenced
observables. At the same time the reference is used to remove the code and phase biases and also
to remove the receivers’ clock biases.
Type 1
Type 2
Receiver
Receiver
Mobile Pseudolite
Receiver
Receiver
Central
Processing Unit
Receiver
Ref Pseudolite
Figure 24: Inverted pseudolite systems
There are of course benefits and disadvantages with both types of systems. The advantage of the
Type 1 system is that orbital errors and atmospheric errors can be ignored due to the close
proximity of the system. Type 1 system also overcomes the limitations of the satellite GPS
system when used for indoor navigation. Another advantage of the Type 1 system is that the
hardware and software of the system can be configured on the ground and therefore the power,
computational load and size can easily be resolved. When the Type 2 system is used, the overall
system cost is reduced because one less pseudolite is used.
24
In this thesis the Type 1 will be discussed because the system will be used indoor and therefore
the GPS satellite system can not be used.
When using a pseudolite based navigation system for indoor navigation, there are a few issues
that have to be addressed. These include the geometric optimization, multipath, near- far
problem and errors due to the receiver array location.
By choosing the right geometry for the receiver array and the pseudolite transmitters the Position
Dilution of Precision can be minimized. When both the receiver array and the pseudolite
transmitter are situated in the same geometrical plane, the line of sight vectors from the
transmitter to the receivers have similar angular orientations and this will result in poor system
geometry. To achieve a better geometry and therefore better PDOP one of the receivers should
be elevated and positioned in the centre of the array. PDOP is GDOP disregarding the clock
offset.
The near/far problem explained earlier in this thesis must be taken in concern. When a receiver is
to close to a pseudolite, the signal from that pseudolite blocks the signal from other pseudolites
because the signal from the nearby pseudolite is much stronger. If the pseudolite is to far away
from the receiver, the signal will be too weak to be received. The ideal distance between the
pseudolite and receiver, where the receiver is able to receive the signal from the pseudolite is
called the “dynamic range”. A solution to the near/far problem is to use Time Division Multiple
Access (TDMA). That is, the signal from the pseudolites is pulsed and only one pseudolite
transmits at a given time.
There is another problem that must be dealt with. Because the signal tends to bounce of floors,
walls and ceilings the length of the signal path from the transmitter to the receiver can vary even
if the position of the receiver and transmitter is static. Good hardware design and software based
multipath mitigation techniques must be developed and used.
Because of the distances between the transmitters and receivers in a pseudolite based inverted
position system is much smaller than in the satellite based GPS, the position of the receivers
must be as accurate as possible. If both the receivers and transmitters are stationary, in the worst
case scenario the influence of the location bias on the differenced range becomes doubled.
Therefore the exact position of the receivers and transmitters must be known, especially for
kinematic applications, to achieve good positioning.
25
2.2.8
Time Division Multiple Access (TDMA) and signal pulsing
TDMA is a method to better use the radio signal channel spectrum. The problem when having
many signals in one channel is that they can cause interference with each other. TDMA uses
pulsing schemes to get around this problem. Each signal is transmitted in pulses at an exact
moment. Only one transmitter transmits at a given time and then allows another signal to get
through. In this way many signal can be broadcasting in almost the same time. In reality only one
transmitter is using the channel at a given moment in short burst. Figure 24 below illustrates
TDMA pulsing were signals A and B is broadcasted without interfering each other. [7] A pulsing
scheme with duty cycles of 10% is a common solution for the near/far problem.
Figure 25: TDMA pulsing
2.2.9
Code Division Multiple Access (CDMA) and Frequency hopping
CDMA is another method to better use the radio signal channel spectrum. [12] CDMA uses
Spread Spectrum and by making signals hop between different frequencies it is possible to send
many signals at the same time without interference. The signals are also hard to listening into
since the signals hop between frequency channels in a pseudorandom fashion. When using
pseudorandom hoping technique, it’s necessary to use a pseudorandom code generator. Such a
generator can be implemented using VHDL code into a FPGA package. A rough function
diagram of the concept with frequency hopping is illustrated in figure 25.
Demodulator
Modulator
S(t)
Filter
Transmitter
Filter
Receiver
Binary
data
Frequency
Synthesizer
Channel
table
Frequency
Synthesizer
Pseudorandom bit
source
Figure 26: Frequency hop functional block diagram
26
Channel
table
Binary
data
[13] CDMA communication system should only be used if all of the signal powers are about the
same level. In an indoor system the signals power varies much since the user moves very near or
to far away from the transmitting pseudolite. This is called the near/fare problem which must be
resolved if CDMA is to be used.
2.2.10
Pseudolite error sources
When using pseudolite based indoor navigation systems there are several error sources that one
must try to resolve. The two most significant error sources are multipath and the near/far
problem.
2.2.10.1
Multipath
As mention earlier, multipath is a big problem in GPS navigation systems. When pseudolites are
used for indoor navigation the problem becomes even bigger because the amount of potential
reflectors is much higher then with outdoor GPS. There are two kinds of errors due to multipath.
First because the signal bounces of the ceiling and/or the walls the range travelled by the signal is
longer. The other kind is when signal interference between the direct signal and the signal that is
reflected corrupts the original signal. The range error because of multipath is in the order of
centimetres with carrier- phase measurement and that is not a very big problem. But if codephase measuring is used the range error can be up to ten meters.
2.2.10.2 Solution for the multipath problem
Conventional radio frequency antennas are usually patch antennas. If conventional patch
antennas were to be used in indoor navigation, multipath problems would deteriorate the
position calculations so bad that indoor navigation would almost be impossible to achieve. The
solution is to use some kind of patterned antenna. For example when using a helix antenna, the
gain pattern of the antenna could be focused towards the floor of the room. By doing so the risk
of a signal bouncing on the walls and ceiling is reduced.
2.2.10.3 The Near/far problem
The near/far problem is when the receiver is eider to close or to far away from the pseudolite. If
the receiver is to close to the pseudolite, the signals from the other pseudolites get jammed by the
signal from the nearby pseudolite. On the other hand if the receiver is to far from the pseudolite,
the signal is jammed or to week to be received by the receiver. The near/far problem appears
only when pseudolites are used.
Figure 27: Near/far problem illustration
27
While in the “near bubble” the receiver tracks only one signal, in the middle bubble all signals are
tracked, and when the receiver is in the far bubble the signal from the pseudolite cannot be
tracked by the receiver.
2.2.10.4 Solution for the Near/far problem
[7],[15] There are several ways to resolve the near/far problem for example tuning the power
level of the signal, out of band transmissions, frequency hopping or pulsing.
[15] Solution by pulse the signal from the pseudolite so that the signal doesn’t interfere with the
other signals is referred to as pulsing. When the signal from the pseudolite is pulsed it is pulsed
with a duty cycle of about 5 to 10 % of the C/A code period. This means that the pseudolite
sends for 50 o 100 µs and stops for 900 to 950 µs. During the time when the pseudolite is quiet,
other pseudolites can transmit. (TDMA)
There are to ways to do the pulsing either synchronized or unsynchronized. When an
unsynchronized solution is used, the risk is that the pulses overlap which leads to signal
interference and therefore a higher measurement noise. The synchronized system uses an
external clock to provide a unified time reference for the system. Every pseudolite has a
predetermined time slot in which it can broadcast its signal. When one of the pseudolites is
sending all the other pseudolites are silent. The synchronized pulse system uses a true time
division multiple access (TDMA) scheme. By doing so the risk of interference between the
signals is abruptly reduced. If the time slots are kept short, larger number of pseudolite can be
used. The disadvantage of this system is that it needs some extra hardware which yields a higher
cost.
2.2.10.5 Power tuning
By adjusting the pseudolites power levels in a pseudolite array one can create a space between the
pseudolites, where the signal is at nominal power so the user can receive signals from all the
pseudolites in the array. But outside the “space” the receiver loses contact with the pseudolites.
2.2.10.6 Out of band transmissions
This method can only be used in outdoor navigation when pseudolites are used to aid the GPS
system. The idea is that the pseudolite sends its signal on another frequency then the L1
frequency. The disadvantage of this signal is that the receivers have to be able to receive on two
different frequencies which yield a higher price for the receivers. Another disadvantage is that the
timing of the second signal can drift with time and temperature relative to the signals send on the
L1 frequency.
2.2.11
The time tag problem
The problem when using an array based on pseudolites is that the pseudolites are using TCXO’s.
In the outdoor satellite based GPS system precise atomic clocks are used so the satellites are
synchronized to each other. But because pseudolites are not synchronized to each other the
receivers cannot synchronize their sampling time so that they can receive data at different times.
The solution to the time tag problem is the use of the 50 bits per second data message that is
content free of a master pseudolite to synchronize the receiver and the reference station. By
doing so the time tag error is reduced to 0.3 mm because the sampling time is synchronized
within one micro second.
28
2.2.12
Differences between PL CDGPS and Global CDGPS
The architecture for the carrier phase pseudolite system is almost the same as for the global
carrier phase differential GPS system. One major difference however is that the pseudolites are
relatively close to the receivers compared to satellites in the sky. This makes the pseudolites
sensitive for near/far problem.
2.2.13
Carrier phase ambiguity Resolutions
[7] There are three different methods to compute the integers. The methods are brute force
search, filtering and geometrical. All the methods must start with an estimate of the position or a
trajectory. The estimation is usually made with code- phase measurements. The search and
filtering methods need an estimation of the error in the initial position estimation. These
methods are the same for GPS and for pseudolite systems. Theses methods are described on
page 17 in this thesis
2.2.14
A simple Pseudolite Architecture
As mention earlier in this thesis a pseudolite is a radio transmitter designed to generate and
transmit GPS like signals. A pseudolite must generate a carrier wave and modulate information
onto it. The carrier wave must be at specific frequency in order to make it possible for the
receiver to collect data at this given frequency. The pseudolite must also amplify this signal so it
can be detected when reaching the receiver.
The simplest pseudolite imaginable with these functions is presented in [7] and is described in
this chapter in order to give the reader insights in the pseudolite design. A block diagram of this
simple pseudolite is illustrated in the figure below. It consists of a TCXO, a PLL, a C/A
generator, a mixer, a L1 filter and a transmitting antenna.
Antenna
Mixer
PLL Block
TCXO
C/A
generator
L1 filter
Figure 28: A simple pseudolite block diagram overview
29
The PLL (Phase Locked Loop) generates the L1 frequency (1575.42 MHz). The PLL consist of a
phase detector, a microwave VCO, a loop filter and divider. The C/A code is created in the C/A
generator and the C/A code and the L1 frequency are then brought together in the modulo-2
operation by the mixer. The Signal is then filtered in the L1 filter in order to remove noise from
the signal. The antenna can now broadcast the L1 frequency GPS carrier wave signal.
2.2.14.1
The PLL circuit
[12] The PLL circuit consists of a phase detector, a microwave VCO, a loop filter and divider.
The PLL circuit creates a predetermine frequency and then lock on to it. The PLL architecture is
illustrated in the figure below. The reference clock in this PLL is a TCXO.
Reference frequency
FREF
Phase
detector
Vo
Phase detector
output
Loop
filter
N * FIN
Microwave
VCO
N * FIN
= FIN
N
Divider (N)
TCXO
Figure 29: The PLL block architecture
The phase detector measures phase difference between the reference frequency ( FREF ) and
output signal from the divider ( FIN ). The output of the phase detector is stored as a voltage
potential (Vo) over a capacitor in the loop filter. The phase detector can either increase or
decrease this potential in the capacitor.
30
The phase detector compares the phase difference between the input signals ( FREF ) and ( FIN ).
These signals are square waves and the phase detector generates two new signals that are send to
the charge pump. These signals are called Lead- and Lag signal and together they form the phase
detectors pulsed signal. This pulsed signal is then send into the charge pump. The LEAD- and
LAG signal generation is illustrated below.
Figure 30: Lead- and Lag signal generation in the phase detector
One possible design of a phase detector is illustrated in the figure below. It consists of two flipflops and a AND gate. This kind of circuit gives LEAD pulses when ( FIN ) is high and LAG
pulses when ( FREF ) is high. If ( FREF ) and ( FIN ) are high at the same time (in phase) then the
output from the AND gate will be high, resulting a reset on the flip-flops. No signal goes to the
charge pump while the Reset is high. Reset is high since the signals are in phase and no further
correction of the potential input to the VCO is necessary.
31
Figure 31: A simple phase detector architecture built by two Flip-flops and an AND gate
The charge pump can be constructed of MOS transistors and an example is showed in the figure
below. Lead signal will increase the potential Vo while Lag signals will decrease the potential. The
figure shows how the potential Vo increases whit the incoming Lead signal. MOS transistors are
used and LAG signals are the input signals. If LEAD signals were input signals the Vo diagram
would be the same but decreasing instead of increasing. R and C illustrate a simple loop filter
function.
FREF
Lead
G
S
FIN
A simple LP-filter
D
Charge pump
G
Lag
D
S
R
+
Vo
Lead
R
C
Vo
Figure 32: Charge pump illustration
32
[16] The loop filter stores the Vo potential over a capacitor. In reality this could be realized by a
simple passive loop filter. Such a filter is illustrated in the figure below.
R1
R2
C
Figure 33: A simple loop filter
The charge pump will drain the filter if LAG signals are input in the charge pump. This will
decrease Vo. If LEAD signals are input to the charge pump then the filter will be loaded and Vo
will increase. The loop filters output is then fed into the VCO.
A VCO generates oscillations in proportions to the input voltage. The input voltage is a constant
dc voltage level Vo. If Vo is increased by the charge pump then the VCO gives a higher
oscillation frequency and the other way around. If Vo is kept constant then the oscillation is
constant. As mention earlier this is the potential (Vo) stored over the capacitor in the charge
pump circuit. The generated dc voltage level from the charge pump generates a new frequency
which has N times greater frequency than FREF and FIN . This new frequency is the PLL output
square wave with N* FIN frequency.
The signal output from the VCO (N* FIN ) is of much greater frequency (N times greater) than
the reference TCXO ( FREF ). In order to make it possible to compare the phase difference
between these signals in the phase detector, they must have the same frequency. The divider
divides N* FIN by N and the resulting FIN signal can the compared with FREF in the phase
detector. A simple divider can be built out of flip-flops.
Figure 34: Divider consisting of three Flip-flops.
33
The divider above has N=8 and therefore consist of three flip-flops. When designing this sort of
divider one can use the formula N = 2 ( NumberofFlip − flops ) . In this case N=8 which gives three flipflops since 8 = 2 ( 3) .
2.2.14.2 The C/A code generator
The C/A code generator could be programmed in a FPGA or CPLD capsule using shift registers
and XOR gates. There are a variety of components that can be programmed with VHDL code
and the design should reflect the C/A code generation that was explained earlier in this thesis.
The VHDL coding in chapter 3 was done with the aid of course literature [17] from a previous
course attended by the authors.
2.2.14.3 The mixer, antenna and filter
These components come in vast varieties from the cellular phone industries. The mixer must be
able to do BPSK modulation as described earlier in this thesis and the antenna should have
directed signal patterns. A good antenna for this task is the helix antenna.
2.2.15
Pulsed Pseudolite Architecture
As mentioned earlier in this thesis, one of the problems that have to be addressed when using
pseudolites for indoor navigation is the near/far problem. To resolve the near/far problem a so
called pulsed pseudolite can be used. A pulsed pseudolite is presented in the paper GPS
Pseudolites: Theory, Design, and Applications [7].
The simple
pseudolite
PIN
Switch
Amp
Amp
PIN
Switch
Microprocessor
Figure 35: Pulsed pseudolite block diagram
In this paper [7] the author modified a pair of simple pseudolites into pulsed pseudolites. The
pseudolites were modified so that high power pulses could be transmitted. The signal pulsing
(TDMA) is described earlier in this thesis. The duty cycle of the pulses was between 10 to 12.5
percent. To make the pseudolites compatible with a new series of receivers, data modulation was
added to the signal.
The pulse pattern chosen in [7] was RTCM-104 and it was implemented inside a Motorola
68HC11 microprocessor. The microprocessor synchronizes with the beginning of each C/A
code epoch. For the switches used to generate the pulse, the specified isolation in the off state is
crucial. The specified power handling capability of the switches is important if the pseudolites are
intended to cover a wide area. At least one switch must be placed between the final power
amplifier and the pseudolite antenna. If there is no switch between the final power amplifier and
the antenna, the near radius will be determined by the amplifier’s own internally generated noise.
34
2.3
GPS Transceivers
A pseudolite is a pure transmitting device and can not receive any data. But if the design is
further developed into a device that can both transmit and receive signals, we end up with a
device called a transceiver. There are not many transceivers that have been constructed by
companies. The transceivers are usually costume made and therefore there are many possible
architectures. Most of the parts used to construct the transceivers are standard low price of the
shelf components. The transceiver is a pseudolite that can send and receive signals on the L1
frequency from other pseudolites or transceivers.
2.3.1
The Transceiver Architecture
The transceiver architecture illustrated in the figure below is the one used by Edward A.
LeMaster in his Self Calibrating Pseudolite Array project [15].
Amplifier
Splitter
Wireless
Ethernet
Receiver
Pseudolite
Pulse
Generator
Figure 36: Transceiver Architecture
The transceiver he constructed is self- differencing which means that the receiver monitors its
own transmitter output at RF instead of synchronization via an oscillator. The transceiver has
two front ends and it can track pseudolite signals through a dedicated line to a front end or by
the use of the normal airwave. The tracking of the signal by the use of the airwaves works well at
low signal power and can reduce outside interference to the direct signal. When signal is at high
power, the leakage at the RF connectors eliminates the benefit of interference reduction. Edward
LeMaster used the airway-propagated signal for self-differencing. The transceiver equipment
includes a pseudolite, receiver, RF antenna, amplifiers, attenuators used to modify the signal
strength, a wireless communication system that is used to collect data and for remote command
and control and a power bus. The pulse generator is used if external pulse synchronization of the
pseudolite output is desired.
When LeMaster constructed the transceivers he used an IntegriNautics IN200C signal generator,
a 12-chanel Mitel Orion receiver modified to use two separate front ends, a ½ wave dipole
antennas, MiniCircuits ZLJ-3G amplifier and Alan Industries 60SV33-1773 attenuators. The base
station used in the experiment was used to collect raw data from the transceivers and process it.
The processing tasks include raw data storage, array self-calibration, bidirectional ranging and
trilateration. The computer used is running Windows NT and is a Dell Latitude with 133MHz
processor.
35
2.3.2
Self Calibrating Pseudolite Array (SCPA)
The SCPA is an array of transceivers that has the ability to self calibrate. The idea of the SCPA is
that a number of transceivers are deployed on unknown positions on a surface and then the
transceivers communicate with each other and build an array. This array will give centimetre level
position to any number of rovers operating within the line of sight of the transceiver array. This
technology is very useful to use in places were normal GPS system coverage is unavailable for
example in indoor navigation. A system overview is illustrated below.
Figure 37: SCPA system overview
The SCPA system consists of three or more stationary transceiver units, a transceiver unit
mounted on the moving unit, a wireless Ethernet and a computer. The distance between the
transceivers is calculated and stored in the computer via the wireless Ethernet.
The primarily problem the system has to deal with is the accurate determination of the
transceiver position. If there should be centimetre level accuracy then the position of the
transceivers must be known with centimetre level accuracy. The SCPA is able to simultaneously
determine both the position of the transceivers that compose the array and the position of the
rovers navigating using the array of transceivers.
36
The navigation is done through the use of a technique called bidirectional ranging. All data that is
collected from the transceivers is processed at a central computer. The self calibration involves a
transceiver mounted on a rover that moves around in the transceiver array. Carrier- phase
measurement data between the transceivers is collected and processed. The result yields the
centimetre level position of the transceivers and the trajectory of the rover. New algorithms and
methods have been developed by Edward A. LeMaster [7] to achieve the centimetre level
accuracy. New methods and algorithms were needed because the geometry of the array can’t be
completely described by the use of methods and algorithms used in normal GPS pseudolite
arrays.
The new algorithms are nonlinear and stochastic and give successful array calibration under most
possible array geometries and under poor initial estimations of the system geometry.
2.3.2.1
Bidirectional Ranging
[15] As discussed earlier in this thesis, a transceiver consists of a pseudolite and a receiver. This
architecture allows a new type of ranging measurement technique called bidirectional ranging.
This method is based on the fact that a transceiver can use self differencing. By self differencing
it is possible for the transceiver to measure its own line bias and receiver bias. When self
differencing is used in bidirectional ranging it is possible to calculate the distance between two
transceivers without any additional measurements. This ranging technique can use both codeand carrier-phase measurements and can therefore give centimetre level accuracy. In order to use
carrier phase measurements one must first determine the integer ambiguity by other means. The
concept of bidirectional ranging using self differencing is illustrated in the figure below.
( Satelite )
bRe
ciever = bias
b2( 2) , R
Range = R
Pseudolite 1
Receiver 2
b1(1) , R ≈ 0
b2( 2) , R ≈ 0
Receiver 1
Pseudolite 2
b1( 2) , R
Figure 38: Bidirectional ranging using self differencing
37
The pseudolite and the receiver are collocated in the transceiver and the range between them is
almost equal to zero. When calculating the bidirectional ranging, the range between the
collocated devices is set to zero.
A line bias is something that will yield errors and it is necessary to calculate them and it is also
necessary to calculate the clock bias for the receivers. Biases may be defined as systematic errors
that will yield constant errors in measurements. [18] These constant errors are measurable and
can be determined as constant in mathematical equation systems. Such biases involved in this
chapter are line and clock biases. Line biases is how much the signal is delayed when it is
transferred and the clock bias is how much the current clock is of compared to another clock.
[15] The line bias must be known before the bidirectional ranging and must be determine by
other means. For carrier phase the line biases can be added to the integer ambiguities and be
determined during the calibrating process. Calibrating processes are explained later in this thesis.
The complexity of bidirectional ranging requires a data link in order for the system to share data.
This system could be wired or wireless. A wireless system is convenient since the cables can be an
obstruction for the mobile unit but a wireless system can however be expensive, may interfere
with other system and has a limited bandwidth.
2.3.2.2
Bidirectional Ranging equations
[15] The bidirectional ranging is mathematically described with the following equations.
Φ nm = Measurement
τ ( n ) = Timestamp
τ m = Clockbias
bm( n ) = LineBias
R = Range
(n = Transmitter , m = Re ceiver )
∇b ∆
Φ1(1) = τ (1) + τ 1 − b1(1)
Φ1( 2) = τ ( 2 ) + τ 1 − b1( 2 ) − R
∆Φ1 = Φ1(1) − Φ1( 2) = τ (1) + τ 1 − b1(1) − (τ ( 2) + τ 1 − b1( 2) − R)
Φ (21) = τ (1) + τ 2 − b2(1) − R
Φ (22) = τ ( 2 ) + τ 2 − b2( 2 )
∆Φ 2 = Φ (21) − Φ (22) = τ (1) + τ 2 − b2(1) − R − (τ ( 2) + τ 2 − b2( 2) )
∇ b ∆Φ = ∆Φ1 − ∆Φ 2 = τ (1) − b1(1) − τ ( 2 ) + b1( 2 ) + R − (τ (1) − b2(1) − R − τ ( 2 ) + b2( 2 ) )
∇ b ∆Φ = 2 R − (b1(1) − b1( 2) − b2(1) − b2( 2) )
( ∇ b ∆ = Double differencing measurements)
Figure 39: Bidirectional ranging equations
38
The result of the bidirectional ranging method is the range R and the line biases. In order to
know the distance R we need to determine the line biases and this is done in the calibration
process explained later in this thesis. The clock bias of the receiver clock is cancelled and does
not have to be determined at all.
2.3.2.3
Self-Calibrating
The self- calibration of the transceiver array is done in four steps. First of all the array must be
deployed. After the array is deployed the self- calibration is initiated. The next part is the coderange measurement part. In this part a rough estimation of the array configuration is done,
including the start position of the mobile unit. During this first step the initial integer estimations
are set for the carrier- range measurement. Bidirectional ranging is used between the stationary
transceivers to estimate the initial integers. The next step is to use the mobile unit to collect
carrier- range measurements. The trajectory of the mobile transceiver is between and around the
stationary transceivers. Range measurements are taken periodically. The measurements are then
used to estimate the position of the mobile unit. In the last part the collected data is used to
generate a new estimation of the stationary transceivers location and the actual track of the
mobile transceiver. In this part the corresponding carrier- phase integer and line biases are
estimated. More information is found in PhD LeMaster thesis [15]. The calibration can be
summarized in four steps:
1. Array deployment. The transceivers are set in place in a geometric fashion.
2. Code-phase coarse calibration. The system uses code phase measurements and the array
and the mobile unit is given an imprecise start position. Bidirectional measurements
between the stationary transceivers and the mobile unit gives the initial integer.(Solves the
integer ambiguity)
3. The mobile unit starts a trajectory around or between the transceivers in the array and
collects carrier range measurements. The mobile unit’s position along the trajectory is
estimated by using the carrier phase measurements.
4. The resulting positioning calibrating is now at centimetre level accuracy based on carrier
phase measurements
The system is calibrated and ready. It can now be used with or without a reference station
depending on which ranging technique is chosen. Bidirectional ranging can be used without the
use of a reference station but regular CDGPS with single and double differencing measurements
still needs the reference station in order to get error corrections (assumed it is an asynchronous
system).
2.3.2.4
Self Calibrating methods
There are two methods that can be used for array self calibration. Linear Iterative Least Squares
and Quadratic Iterative Least Squares. When using those methods one can use eider the standard
method or multiple- seeding. Multiple- seeding is a technique used by Ph.D. LeMaster in his
research on self- calibrating arrays to improve the basic algorithm effectiveness. The QILS
multiple- seeding algorithm success rate is 99.8%. More information on multiple- seeding is
found in Ph.D. LeMaster thesis [15].
The evaluation of the algorithms is done using Monte-Carlo simulations because of the large
number of parameters and the nonlinear nature of SCPA. The primary reason for array selfcalibration error is the configuration of the array. The Quadratic Iterative Least Squares method
gives the highest success probability throughout the range of possible array configurations; even
high bias values are present. But for industrial application where there is room for small errors,
the Linear Iterative Least Squares method can be used.
39
Beginning with the nominal estimate of the array configuration and trajectory, the linearization of
the nonlinear equations that describe the dependence of the measurement upon the system states
is done about that estimate so a local gradient can be determined. A new estimation of the array
configuration results from a displacement vector which is generated from the difference between
the measured and the expected ranges. The measurement equations are again linearized near
about this new point. The whole process is done all over again until convergence can be
achieved.
2.3.2.5 System calibration problems
[15]When working with self calibrating arrays, and the arrays must be calibrated, there are a few
problems that have to be resolved. Some of the problems can be eliminated by calibration of the
system. Those are the integer ambiguity, locations of the transmitters and line biases. Other
problems can be a bit more difficult to eliminate. Multipath is one of those problems.
Because the SCPA uses carrier- phase measurements in the same way as the GPS the carrierphase cycle ambiguity can be resolved in the same matter. Only one of the methods will be
discussed here, the motion- based method. The other methods have already been explained
earlier in this thesis. This method is used to resolve the integer ambiguity problem in SCPA.
This technique uses either the motion of a transmitter or a receiver to resolve the problem.
Basically, the system collects range measurement as one of the devices is stationary and the other
is in motion. When enough measurement data has been collected, then one set of integers is
consistent with the measured range changes between the stationary and the mobile devices during
the motion of the mobile device.
When navigating with the aid of the GPS the exact positions of the transmitters is known and
when the position is changed, the new position is broadcasted to the receivers via the data
message incorporated inside the navigation signal. But for the SCPA the position of the
transmitters must be determined somehow.
Because the SCPA uses transceivers instead of separated transmitters and receivers range
measurements exist between each pair of devices. This means that meter- level accuracy can be
achieved if code- level calibration is used. The carrier- phase cycle ambiguities present in single or
double- differenced solutions can be detected if a carrier- phase study is done. When the integer
values are known, the ranges between the transceivers can be known.
The problem of line biases is due to the time loss when signals travel through the system
hardware. When the system is in use, usually the line biases are constant, but might change due to
changes in temperature. The line biases can be resolved by placing the receiver and transmitter at
known positions and by observing the difference between the calculated a measured carrier
phases.
40
2.3.2.6
Other error factors
There are other factors that have to be taken in concern besides the ones mentioned earlier.
Problems like approximation error, multipath and cycle slip errors have been discussed earlier in
this thesis. The number of sampling points that are taken while the system self- calibrates is
another source of possible errors that can lead to unsuccessful calibration of the transceiver array.
The adequate number of samples is one every 0.2 units traveled [15] for most situations. The
coordinate frame used is another error source. There are several potential choices for coordinate
frames that can be chosen. Ph.D. LeMaster suggests in his Ph.D. thesis [15] that the optional
coordinate frame is a floating frame that is attached to the centre of the transceiver array.
41
2.4
GPS Synchrolites
[7],[15]A Synchrolite is a pseudolite that does not generate and broadcast its own individual
signal. Instead it acts like an electronic mirror and bounces GPS signals from satellites to the
receiver. The synchrolite must be placed at an exact known location. The synchrolite remodulates
the GPS signal with an individual PRN identification code and then retransmits the signal with a
known phase delay from the original signal. The bounced signals from the synchrolite are then
easily identified by the receiver.
The user must subtract the direct signal from the reflected signal in order to measure the pseudo
range. The synchrolite uses code and carrier phase measurements as described earlier in this
thesis. Observe that only three synchrolites are needed for 3D positioning since the satellite also
transmit signals direct to the user receiver.
Figure 40: Example of synchrolite outdoor navigation system
A synchrolite has the ability to reflect the signal from several satellites. In this case the receiver is
able to calculate a precise differential position from the synchrolite. If this scheme is used then
continuous differential reference data can be provided without the major GPS error sources.
2.4.1
Synchrolite Reflection Delay
[4] Since the synchrolite has circuits it must have some delay in it. It takes a little time for the
received signal to be rebroadcast to the user. This time delay ( t j ) must be known in order to
make range measurements. Many of the characteristics that cause delays in an electric circuit can
be predicted or measured. These delays will vary very little with age of the circuit and temperature
but is for simplicity sake assumed constant. When assuming these variation sources as small, it is
important to protect the circuits from heat and aging affects.
It is a good thing to design synchrolites with equal delays, even if the synchrolite reflects multiple
signals should be designed so that the signal delay is the same for all the signals. Since these
delays are subtracted when calculating range they can be of various sizes but must be measurable.
If time delay ( t j ) can’t be designed exact equal for all the synchrolites in the system, then its
necessary to determine the delays by other means. For example a nearby monitor situated at
known distance from the synchrolite can be used to compute the delay inside the synchrolite in
real time, and the synchrolite can null out the delay.
42
2.4.2
Navigation with the aid of one synchrolite
A complete CDGPS system can be set up using only one synchrolite. If a receiver is able to
receive the signals from four or more satellites at the same time as it receives the signals from the
same satellites but bounced of a synchrolite positioned at known location a CDGPS navigation
can be achieved. If very accurate CDGPS navigation is needed the value of the delay inside of the
synchrolite must be computed by the navigation algorithm. If the carrier- phase ambiguities are
known, the synchrolite navigation system can be used with carrier- phase pseudo range to
navigate with centimetre level precision.
Figure 41: Navigation with the aid of one Synchrolite
2.4.3
Simple Synchrolite architecture
[7] The block diagram below is synchrolite architecture suggested in [7].
Antenna
T/R Switch
Microwave
Local
Oscillator
Tracking
Loop
Controller
Receive
C/A Code
Generator
Tracking
Loop
Controller
Tracking
Loop
Controller
Figure 42: Synchrolite functional block diagram
43
Because a synchrolite has both a transmitter and a receiver and the difference in signal power
between the received signals and the transmitted is at worst 160 dB, the risk of near- far
interference is very high. The solution is to transmit in pulses and to receive between the pulses.
Because receivers are usually harder to design, standard receivers are used. The software of the
receiver must be changed so that it can slave a second correlator to the first and commands it to
generate a new C/A code. The carrier from the master channel is combined by the hardware with
the C/A code from the slave channel and then modulates the resulting signal onto a signal at
1571.328 MHz. The result is a synchrolite signal with a new C/A code but the timing of the
incoming signal is the same.
44
2.5
Locata positioning system
2.5.1
LocataLite
[19] A LocataLite is a time synchronous pseudolite transceiver. The LocataLite transmits GPS
like signals and can use carrier phase measurements with centimetre level accuracy. The
frequency it sends on is the standard L1 frequency. The LocataLite also generates a C/A code
pseudorange. The receiver of the LocataLite has the same hardware as the Locata
2.5.2
Locata
The unit that a position is calculated for is called a Locata. A Locata can be a moving unit with a
position we want to keep track of. The Locata has the ability to track the GPS signals and signals
from the LocataLites. The Locata is capable of 3D positioning with precision under the
centimetre when signals from 4 or more LocataLites are tracked. The hardware of the Locata is
based on an existing GPS chipset.
2.5.3
LocataNet
[19] A LocataNet consists of an array of LocataLites and a Locata. When synchronizing a
pseudolite system it is possible to achieve stand alone systems without the usage of a reference
station. Since the clocks in the LocataLites are synchronized, no exact positioned reference
station is needed in order to eliminate the pseudolite and receivers clock biases. Each LocataLite
can synchronize their clocks to a master LocataLite or another LocataLite. The synchronization
technique is called TimeLoc and it is explained later in this thesis. Once the LocataLites are
synchronized it is possible to measure the Locata’s position with sub centimetre accuracy. The
main advantage of the LocataNet is that the LocataLite array is synchronized so there are no
clock bias errors.
2.5.4
Navigation Algorithm used for navigation in LocataNet
[20] The system uses carrier-phase point positioning to compute its position. To acquire a
position in 3 dimensions, information from at least four different LocataLites is needed.
When the standard outdoor GPS system is used the basic carrier phase observation equation
between receiver r and satellite s (in meters) is written as follows
ϕ rs = ρ rs + τ trop + cδTr − cδT s − τ ion − ⎛⎜ c f ⎞⎟ * N rs + ε
L1 ⎠
⎝
where
τ ion ; τ trop
f L1 is the frequency of the L1 carrier-phase observable
c is the speed of light in vacuum (300 000 000 m/s)
ρ rs is the range between the receiver and the satellite
δTr is the receiver clock error
δT s is the satellite clock error
N rs is the integer ambiguity
are the atmospheric corrections due to ionosphere and troposphere
ε represents the remaining errors for example multipath
Figure 43: The LocataNet navigation algorithm
45
These equations’ parameters aren’t known with enough accuracy so that the receiver can perform
CPP, and determine its own position with centimetre level accuracy.
To go around this problem, another GPS receiver can be used and double-differencing is
performed to eliminate the clock biases, orbital errors and spatially correlated errors. This extra
receiver is called base station.
The LocataNet carrier- phase observation equation between LocataLite l and receiver r in meters
is as followed:
ϕ rl = ρ rl + τ trop + cδTrl − ⎛⎜ c f ⎞⎟ * N rl + ε
L1 ⎠
⎝
The terms are exactly the same as the ones for the first equation. The clock error is not needed in
this equation because the LocataNet is synchronised. There is no τ ion because the LocataNet is
ground based. τ trop is negligible because of the short distance between the LocataLites and the
Locata.
The ambiguity term and the clock error are determined through a static initialisation at a known
point. The clock bias and ambiguity error in meters can be written as:
⎞* Nl +ε
Brl = δdTrl − ⎛⎜ c
⎟
r
⎝ f L1 ⎠
and
ρ rl =
(X
r
−Xl
) + (Y
2
r
−Yl
) + (Z
2
r
− Zl
)
2
where
δdTrl is the change in the receiver clock error from the static initialisation epoch
Figure 44: The clock bias and ambiguity errors
δdTrl together with the Locata X; Y and Z coordinates will give four unknowns, which can be
solved with four Locata carrier- phase measurements and least square estimation. After the
carrier- phase bias is estimated through static initialisation the Locata is free to navigate when
moving.
46
2.5.5
The TimeLoc technique
[20] The Locata positioning system uses a technique called TimeLoc in order to synchronize the
clocks of all LocataLites in the LocataNet. To achieve time synchronization between LocataLites
the system goes through the following steps.
1. Locata A uses four or more satellites in order to determine its exact location in 3D. Then
LocataLite A uses its Locata signal and begins transmitting C/A code and carrier signal.
A
Figure 45: LocataNet establishment step one.
2. LocataLite B receives tracks and measures the signal from LocataLite A. LocataLite B
also determine its own location by using four or more satellites. LocataLite B uses a
different PRN code, and generates its own C/A code and carrier signal on the PRN code.
LocataLite B adjusts its TCXO using Direct Digital Synthesis to reduce the difference
between its own C/A code and carrier signal and the C/A code and carrier signal from
LocataLite A. The C/A codes and carrier signals are continuously monitored to ensure
synchronization between LocataLite A and LocataLite B. The advantage of this technique
is that it can use low-price TCXO’s instead of expensive atomic clocks to achieve
synchronization. Two or more LocataLites can use this technique to achieve clock
synchronization.
A
B
Figure 46: LocataNet establishment step two.
47
3. LocataLite C receives signals from LocataLite B and LocataLite A. It also determines its
own position by using four or more satellites. Since LocataLite A and LocataLite B
knows their own positions and can both receive and transmit signal to each other and can
therefore determine the range between them. LocataLite B calculates the difference
between its own carrier signal and C/A code and the C/A code and carrier signal
received from LocataLite A. In this way it can calculate the difference between the signals
due to clock bias and range between the LocataLites. The propagation errors are ignored.
C
A
B
Figure 47: LocataNet establishment step three.
4. LocataLite A, LocataLite B and LocataLite C know their own positions and all ranges
between them can now be calculated. LocataLite D determines its own position by using
four or more satellites and then begins to send its own Locata signal.
D
C
A
B
Figure 48: LocataNet establishment step four.
48
All LocataLite positions are now known and all ranges between them are calculated. The GPS
constellation is no longer needed and we now have a stand alone system. A Locata can now
move in the system and receive Locata signals and then triangulate its own position.
D
C
B
A
Figure 49: LocataNet established
Since Locata signals can be broadcast with high power it is possible to penetrate walls. Therefore
it is possible to determine position of indoor LocataLites by using triangulation and TimeLoc.
D
C
E
B
A
Figure 50: LocataNet establishment indoors
49
This concept can also be used when navigateing indoor with a Locata. It is possible to add more
LocataLites to the system and then improve the system.
Receiver
Figure 51: Example of indoor navigation using Locata and LocataNet
The Locata technology can also be used to augment the positioning using the global GPS system.
By using the global GPS in the same way as described in step one to four and then use this
LocataNet, a greater accuracy can be acheived.
Receiver
Figure 52: Augment to the global GPS system
50
2.6
Hammerhead
The Hammerhead is a GPS receiver in a single chip developed by Infineon and Global Locate.
[21] This chip is also called PMB2520 and has a very low sensitivity of -161dBm. This low
sensitivity allows the Hammerhead receiver to track Global GPS signals indoors even if these
signals are up to one thousand times weaker than the signals outdoors.
This chip is housed in a 7mm*7mm VQFN-48 package and will cost 6.50 Euro in quantities of
ten thousand chips. Infineon and Global Locate expect to have available samples no sooner than
the first quarter of 2005. The Hammerhead chip in a VQFN-48 package is shown in the figure
below.
Figure 53: PMB2520 in a 48 pin Very thin Quad Flat Pack Non leaded standard chip package
(VQPN-48)
Since this chip is able to track GPS satellites from indoors, it would be possible to build a system
very similar to an outdoors GPS system but indoors. Since GPS satellites broadcasts a very weak
signal that bends with the atmosphere intuition says that roof or wall of a building should bend
this signal even further. A CDGPS system would try to calculate and remove these errors but it
should be a harder task to do than with receivers located outside. Although the hammerhead chip
is worth more investigation.
51
3
Our Prototype
The purpose with the prototype was to determine whether it was possible to make a simple
pseudolite. The pseudolite shown in the figure below was to be built. This simple pseudolite does
not produce any data bits, it only generates C/A code and BPSK modulates it onto the L1
frequency.
Mixer
BPSK modulated
C/A code with
carrier frequency
L1=1575.42MHz
PLL
Block
C/A
generator
TCXO
Figure 54: The prototype functional block diagram
3.1
Design
3.1.1
The first PLL Design
In order to create and lock on to the L1 frequency a PLL was necessary and since no appropriate
PLL components seem to be available for this task, a new one was designed from scratch. This
PLL had a reference clock with a clock frequency of 10MHz and should deliver 1575.42MHz as
output frequency. This was proven to be a difficult task and merely 1575MHz was the real output
from this PLL circuit.
The most challenging task with this kind of design was that there was a 10MHz reference clock
and the output should be 1575MHz. If an ordinary PLL design,as described earlier in thesis, was
to be used then a divider with N=157.5 must be used. This fact inflicts a problem since that sort
of design is unknown to the author of this thesis.
In order to solve this problem and get a lower frequency in the PLL circuit, a custom made
design was used by using the following components:
•
•
•
•
uPB1507GV Prescaler fromNEC.
MC145151-2 Frequency Synthesizer from Motorola.
M3500-1324 micro wave VCO from Micronetics.
A custom made Loop Filter of passive components.
3.1.1.1
uPB1507GV Prescaler fromNEC
The uPB1507GV Prescaler from NEC simply divide the PLL output frequency of 1575MHz
with N=256 which gives the frequency ( FIN ) of 6.15MHz.
52
3.1.1.2
MC145151-2 Frequency Synthesizer from Motorola
The MC145151-2 Frequency Synthesizer from Motorola was used since it can divide both the
reference frequency and the input frequency on the input to the phase detector. Because a
reference clock ( FREF ) of 10MHz was used and that FIN and FREF must be of the same
frequency in order to detect valid phase difference in the phase detector. Since the FIN has a
frequency of 6.15MHz more division of frequencies must be made.
This is why the MC145151-2 Frequency Synthesizer was chosen. It has the ability to further
divide the FIN and the FREF frequencies. In order to get the same frequency as input to the phase
detector, FIN was divided by M=315 and FREF with R=512. Now these signals both had the
frequency of 19531.25Hz which is the PLL’s internal frequency. The MC145151-2 Frequency
Synthesizer also includes a charge pump which generates positive or negative voltage signals as
output.
19531.25Hz
÷ R = 512
R1
PFD with built in
Charge Pump.
VCO
PDOUT
÷ M = 315
R2
19531.25Hz
TCXO
10MHz
C
GND
N=256
FVCO = 1575MHz
Figure 55: First PLL design overview
The authors of this thesis were unable to get this circuit in a suitable DIP package. SOG Package
had to due instead. This SOG Package is illustrated in the figure below. And full data sheet of
this circuit can be found in the appendix C.
Figure 56: MC145151DW Motorola PLL synthesizer in a SOG Package
53
Because the input frequency FIN input is 6152343.75Hz and that the reference frequency FREF is
10MHz. These two signals must have the same frequency when phase detect measurements is
conducted in the phase detector. The MC1451512 component has an attractive feature to solve
this problem. It can divide the signals FIN and FREF on the input stage of the circuit. FIN is
divided by a factor N and FREF by a factor R. Possible values of R is illustrated in the table
below.
Table 1: The possible factors R
Pins 7-5 ( R A 2 − R A0 ) sets the number R which the FREF frequency is divided with. R=512 will
yield the chosen frequency of 19531.25Hz. This frequency is the internal PLL frequency. Pins 7-5
should be set to 011.
Choosing the factor M is a more “free of choice task” since binary values between 1023 and 1 is
possible. Since we want the input frequency FIN of 6152343.75Hz to be the same as the chosen
frequency of 19531.25Hz.
Pins 20-11 ( N 9 − N 0 ) sets the number M which will divide the FIN frequency. M=315 is
obtained by setting pins 20-11 with 0100111011 and will yield the frequency 19531.25Hz.
(M): 2 8 + 2 5 + 2 4 + 2 3 + 21 + 2 0 = 256 + 32 + 16 + 8 + 4 + 1 = 315
FIN and FREF have now the same frequency. This internal frequency is much smaller than the
big 1575MHz signal and will yield fewer errors in the circuit.
3.1.1.3
M3500-1324 micro wave VCO from Micronetics
The M3500-1324 micro wave VCO from Micronetics is fed with a low DC voltage from the
charge pump of the MC145151-2 and should then generate a relatively high frequency of
1575MHz. The M3500-1324 micro wave VCO generates frequencies between 1350MHz and
2400MHz and has a tuning voltage between 1V and 12V (Max 15V).
54
3.1.1.4
Loop filter
A passive low pass filter was designed using the design considerations, page 28 in the MC1451512 datasheet in appendix C. The filter design is shown in the figure below.
Parameters:
• FREF =19531.25Hz
• FVCO = 1575Mz
• N=256
• M=315
• K VCO =80MHz/Volt
• VDD Phase detector 9V
• Damping factor ζ =1
• K VCO is replaced with M* K VCO
(due to the use of frequency synthesizer).
VDD
• KΦ =
4π
2π
• wn =
FREF Natural frequency
10
Loop filter
Calculations:
wn =
K Φ KVCO M
(1)
NC ( R1 + R2 )
ξ = 0.5wn R2 C +
N
(2)
( K Φ MKVCO )
(2) Gives R2 C = 1.629604775 *10 −4 which yields (1) R1C = 0.4679745124
By choosing values of C we get values of R1 and R2 :
C
1pF
1nF
1uF
1mF
R1
468G Ω
468M Ω
468k Ω
468 Ω
R2
163M Ω
163k Ω
163 Ω
0.163 Ω
Figure 57: Filter calculations
55
Comment:
To big resistance
Should be about right
To small resistance
3.1.2
The second PLL design
A second PLL circuit was designed since the first circuit could not deliver the exact L1 frequency
of 1575.42MHz, merely 1575MHz. The second PLL design went better than the first one and the
authors of this thesis managed to achieve the exact L1 frequency of 1575.42MHz. This PLL
circuit consists of only two components.
•
•
ADF4360-4 Integrated Synthesizer with inbuilt VCO
External passive loop filter
3.1.2.1
ADF4360-4 Integrated Synthesizer from Analog Devices
An alternative PLL circuit is presented in this chapter. The ADF4360-4 device is an integrated
synthesizer from Analog Devices with an inbuilt VCO. Analog Devices has a simulation program
for their product which is a good instrument when designing the loop filter. ADF4360-4 can
produce an output frequency between 1450MHz and 1750MHz with reference frequencies
typical between 10MHz and 250MHz. The functional block diagram of the ADF4360-4
component is shown in the figure below.
Figure 58: Functional block diagram of the ADF4360-4 circuit
The REFIN input is coupled to the 10MHz TCXO and this 10MHz frequency is divided with a
selectable 14Bit counter with range from 16384 to 0. The divided signal from this register is then
fed to the phase comparator.
56
The other input to the phase input is fed from the grey block in the left lower corner. This block
is a complicated frequency divider with the dividing factor N=(BP+A) where A is 5 bit counter,
B a 13 bit counter and P/P+1 is a Prescaler with selectable values with the bits P2 and P1.
P2
0
0
1
1
P1
0
1
0
1
P/P+1
8/9
16/17
32/33
Also 32/33
Table 2: Table of possible values P/P+1
The phase comparator simply measures difference in phase and the two inputs must have the
same frequency. The difference in phase is then converted to a current by the charge pump. This
current is ± I cp depending on the phase difference between the inputs are positive or negative.
The charge pump current is fed to a loop filter which must be designed outside the ADF4360-4
circuit. This filter was designed using the ADIsimPLL version2.5 software provided by analog
Devices homepage [24].
The output from the passive low pass filter is then fed to the VTUNE input on the ADF4360-4
circuit. This input is pure dc voltage and it generates oscillation in the VCO. This oscillation is
then fed through the circuit’s output stage to the RFOUT A and RFOUT B outputs. The output
frequency is obtained by setting values to counters A, B, R and the Prescaler P. The following
equation gives the output frequency of the ADF4360-4 synthesizer.
RFOUT = ( A + BP)
Where:
FREF
R
A=3
B=4923
P=16
(P/P+1=16/17)
R=500
FREF = 10 MHz
=> RFOUT =
(3 + 4923 *16)10MHz
= 157.542 *10MHz = 1575.42MHz = L1
500
Figure 59: The output frequency calculation
The L1 frequency is achieved using the settings above and by using a well deigned LP filter. The
figure below is taken out from the ADIsimPLL software and it illustrates the passive low pass
filter and the coupling to VTUNE . The reference frequency is set to 10MHz and should act as the
TCXO.
57
3.1.2.2
Passive loop filter
A loop filter is needed in the feedback loop from the charge pump output to the voltage tuning
input on the inbuilt VCO. ADIsimPLL is a good tool when designing this filter. The resulting
low pass filter is calculated using the ADIsimPLL program.
Loop filter
C1=3.9nF
R1=8.20k Ω
C2=18nF
Figure 60: Passive loop filter and coupling to VTUNE
The output from this filter is pure DC voltage stored in the filters capacitors. This dc voltage is
fed back into the circuit’s VTUNE input as illustrated above.
3.1.2.3
The programmable data input
In the functional block diagram of the ADF4360-4 component, there are three inputs (CLK,
DATA and LE) LE stands for LOAD/ENABLE and when LE pin goes high the data stored in
the shift registers is loaded into one of the four latches. The data is loaded in serial with most
significant bit first on the DATA input pin. In order to set parameters in the ADF4360-4
component, three 24bit latches must be implemented on the data input.
In the ADF4360-4 datasheet (See appendix C) one can read about timing characteristics for the
CLK input (clock) used when shifting in the binary latches. The minimum time duration for low
flank is t5 =25ns and for high flank is t 4 =25ns. This yields that the minimum clock cycle
duration is t 5 + t 4 = 50ns and by knowing this fact we can easily calculate the maximum
frequency for this clock input. This is illustrated below.
Tmin = t 4 + t 5 = 50ns
f max =
1
Tmin
=
f max > f TCXO
Figure 61: Maximum clock rate for the CLK input calculations
58
1
= 20 MHz
50ns
The counters and the prescaler are loaded with control latches. These latches consist of a binary
data stream of 24bit each. These latches also set current, power, gain and voltage levels out from
and inside the PLL synthesizer.
These latches are clocked in with the most significant bit (MSB) first and the least significant bit
(LSB) last. The latches are loaded in serial and the TCXO is used as clock. The two LSB bits
(DB1-DB0) in the latches are control bits. Note that the test mode latch is for factory testing
only and should not be programmed by the user. The table below shows how to set the control
bits when choosing latch.
Control latch
N counter latch
R counter latch
Test mode latch (For factory testing)
0
1
0
1
0
0
1
1
Table 3: The latches VS The control bits
The Control latch is 24Bit long and consists of the bits DB23-DB0. DB23 is the most significant
(MSB) bit and DB0 is the least significant bit (LSB). The control latch and the chosen values are
illustrated in the table below.
Figure 62: The Control latch
DB23-DB22 (P2,P1) are the bits set for determine the value of the prescaler and this setting
should be 01 which gives us P/P+1 = 16/17.
DB21-DB20 (PD2,PD1) are the power down setting. This setting is recommended in the
datasheet to be in normal mode. Therefore these bits should be set to x0. X means don’t care bit
and it can be set to any value since the device don’t care of its value.
59
DB19-DB17 are the setting for the charge pump current ( I CP ) and the following values are
available.
CP16
CP15
CP14
I CP
0
0
0
0.31mA
0
0
1
0.62mA
0
1
0
0.93mA
0
1
1
1.25mA
1
0
0
1.56mA
1
0
1
1.87mA
1
1
0
2.18mA
1
1
1
2.50mA
Table 4: Possible values of charge pump current ( I CP )
DB16- DB14 are not used and these bits are set to 000.
DB13-DB12 controlis the output level of the VCO and the following values are available. The
chosen value must match with the input requirements of the mixer. The mixer has a maximum
input level of +30dBm and the DB13-DB12 bits can therefore be set to 11 without any problem
for the mixer.
DB13
(PL2)
0
0
1
1
DB12
(PL1)
0
1
0
1
Output power level
Current Power into 50 Ω
3.5mA -13dBm
5.0mA -10dBm
7.5mA -7dBm
11.0mA -4dBm
Table 5: Output power level of the VCO
DB11 is the Mute-Till-Lock-Detect bit. When set high this function ensures that the RF outputs
of the ADF4360-4 are not switched on until the PLL is locked. This is a very desirable feature
and the DB11 bit should therefore be set to 1.
DB10 is set 1 in order to enable the DB19-DB17 bits and disable the DB16- DB14 bits.
DB9 determines the charge pump output behavior. 0 gives three state and 1 gives normal
behaviour. Normal behavior is recommended in the ADF3460-4 datasheet and this bit should be
set to 1.
DB8 is the phase detector polarity. When using inbuilt VCO with an external passive loop filter,
it is recommended in the ADF3460-4 datasheet to have a positive phase detector polarity. This
bit was set to 1 to insure positive polarity.
DB7-DB5 set the behavior of the Muxout control function. When set to 001 the device will set a
active high on the Muxout pin when the PLL is locked. This feature is desirable when testing the
device with the loop filter and these bits are set to 001.
DB4 is the Counter reset. When this bit is set high, the counters A, B and R are held in reset.
When the Counter reset bit is low the counters are in normal mode. This bit was set to 0.
60
DB3-DB2 set the core power in the VCO and the following values are available. The ADF3460-4
datasheet however recommend 15mA so these bits were set to 10.
DB3
0
0
1
1
DB2
0
1
0
1
Core power level of the VCO
5mA
10mA
15mA
20mA
Table 6: Core power levels of the ADF3460-4 inbuilt VCO
The N counter latch is aslo 24Bit long and consists of the bits DB23-DB0. DB23 is the most
significant (MSB) bit and DB0 is the least significant bit (LSB). The N counter latch and the
chosen values are illustrated in the table below.
Figure 63: The N counter latch
DB23 and DB22 are used if one wants to divide the output signal with 2. This is not the case for
the chosen design and these bits were set to 00 in order to disable this feature.
DB21 has the same function as the DB10 bit in the control latch. The bit always reflect the latest
values and by setting both DB10 in the control latch and DB21 in the N counter latch as 1, it
does not matter which latch that was loaded most recently.
DB20-DB8 are the settings for counter B. This counter should be 4923 which means that DB20DB8 must be set to 1001100111011, since 212 + 2 9 + 28 + 25 + 2 4 + 23 + 21 + 2 0 = 492310 .
DB7 is a reserved bit and is set as don’t care bit (x).
DB6-DB2 are settings for the A counter which should be 3. Binary three is easily recognized to
be 11, which give us that DB6-DB2 should be set 00011.
61
In the same way as the other two latches the R counter latch is also 24Bit long and consists of the
bits DB23-DB0. DB23 is the most significant (MSB) bit and DB0 is the least significant bit
(LSB). The R counter latch and the chosen values are illustrated in the table below
Figure 64: The R counter latch
DB23-DB22 are reserved bits and should be regarded as don’t care bits.
DB21-DB20 is the Band select clock divider function. This is a divider used if the phase detector
frequency should exceed 1MHz. The phase detector input frequency is derived by dividing the
reference frequency ( REFIN ) with the R counter.
REFIN
10Mhz
< 1MHZ =>
= 20kHZ < 1MHz . No further division is needed!
R
500
When DB21-DB20 are set to 00 divisions with one is carried out.
DB19 is a test bit used by the constructer. This bit should be set 0 for normal mode.
DB18 is a function that sets the lock detection precision. Should be set as 1 for best accuracy of
the lock detect function.
DB17-DB16 The PFD includes a programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Set these pins 00 for antibacklash equal to 3ns
DB15-DB2 set counter R. This counter should be 500 and DB20-DB8 should be set to
0000111110100, since 28 + 2 7 + 2 6 + 2 5 + 2 4 + 2 2 = 50010 .
62
3.1.3
The C/A code generator
As mentioned before in this thesis, there are several ways to resolve the C/A- code generation in
the pseudolite. One of the ways was to program the C/A- code generator in VHDL. Two sets of
programs were used when the VHDL program code was written. The first program was ActiveHDL from ALDEC and after successfully simulating the C/A- code generator, the programs
Xilinx ISE and ModelSim II were used to simulate and synthesise the VHDL code. After
successfully synthesizing the program a program file was generated and loaded onto the XSA-200
development board. Because in the future the prototype C/A code generator will be used in a
system that uses several pseudolites the user has to be able to choose which C/A-code will be
generated. Therefore prior to the initialisation, the user can choose the C/A- code by putting the
right 6-bit sequence on the delay input.
The first C/A code generator was constructed by using to special design right shift registers. The
registers output was not 1 bit but 1023 bits. That was done by embedding 1023 bits long register
inside the right shift register. When a bit was generated by the right shift register, the bit was
saved into the right position inside the 1023 bits register. After 1023 bits were generated, the
1023 bits long sequence was put onto the output of the whole right shift register. After the 1023
bit sequence was generated the system could reuse the sequence continuously without the need
to generate it again. The right shift registers are implemented as state machines. One of the right
shift registers has a “delay” input that is used to choose how many bits the sequence will be
delayed so that different C/A- codes can be generated. When both right shift registers generated
their 1023 bit sequences, the sequences were sent into an XOR gate and the output of the XOR
gate was the C/A- code. 1023 bits buses were used to connect the right shift registers with the
XOR gate. The output of the XOR gate was also a 1023 bits bus. This C/A- code generator was
poorly optimised and it would have needed a high amount of hardware to implement a very
simple system. Therefore this generator was never used.
Figure 65: The first C/A- code generator
63
The second C/A- code generator was based on the above-described generator but the big
difference is that the output of the right shift registers is only 1 bit instead of 1023-bit sequence.
The right shift registers are also implemented as state machines. After all the needed bits are
generated and saved into a register inside the right shift register the system sets a variable to 1023
and starts to read the bit that has the same address as the variable value. After reading one bit
from the register the value counts down 1 and reads the next bit inside the register. When the
variable counts all the way down to 1 and the last bit is read from the register the variable is reset
to 1023 and the process starts again. The output of the right shift register is the value read from
the register. The 1023 bits sequence is generated by the right shift registers only once during the
initialisation of the C/A- code generator. The system uses an XOR gate to modulo-2 add the
output bits from the right shift registers to generate the C/A- code. The system generates
continuously the C/A- code. After the last bit of the C/A-code is generated, the system starts
again by generating the first bit of the C/A- code. This code generator was never used because it
was not optimised enough.
Figure 66: The second C/A- code generator
The third C/A-code generator uses a control unit that controls the whole C/A- code generation
process. The system consists of two right shift registers, an XOR unit and the control unit. The
generator generates one bit at the time and after a 1023 bit sequence is generated, the control unit
resets the right shift registers and the generation of the 1023 bit sequence starts again. This
generator is very complicated and therefore it takes several clock cycles to generate one bit. A lot
of time is lost because the control unit has to give the start command for every other part of the
system and has to wait until it receives the done signal from every unit before it can go to the
next stage. Therefore even this generator was never used.
64
Figure 67: The third C/A code generator
The final C/A- code generator is very simple. It is constructed using two right shift registers and
an XOR gate.
Figure 68: The fourth C/A code generator
One of the right shift registers has a “delay” input. The delay input is used to choose which C/A
code will be generated. When the right shift registers are reset, the registers are loaded with the
bit sequence “1111111111”. The C/A – code is generated sequentially. It takes one clock cycle to
generate one bit.
65
As mentioned earlier in this thesis the C/A- code must be generated at a speed of 1 Mbps. If the
C/A- code generator clock frequency is 1 MHz then the right speed is achieved. The C/A- code
generator was simulated in Xilinx ISA and the result of the simulation can be seen in the
following picture:
Figure 69: Xilinx ISA simulation of the fourth code generator
To make sure that the right C/A- code has been generated; the first ten bits of the C/A- code
can be checked with the table of C/A- codes found in Appendix B. The left most bit in the
“Delay” sequence is the LSB. Therefore in the simulation the chosen value is 32 instead of 1. The
“Delay” value is one so that the C/A-code for the satellite nr 1 is generated. The whole 1023 bit
sequence can be viewed in Appendix E. That simulation is done in Active- HDL.
The fourth C/A code generator worked well and the other C/A code generators was disregarded
for the rest of the project.
3.1.4
Mixer
The C/A code and the L1 frequency should somehow build a transmission signal. For pseudolite
applications this is done by BPSK (See chapter about BPSK modulation) modulation. The binary
data stream and the frequency from the PLL are mixed together and the resulting signal can be
transmitted to the receiver.
BPSK
IF
Binary data stream
(1023Bit C/A-code)
L1 frequency from the
PLL (1575.42MHz)
RF OUT
LO
Figure 70: Mixer overview
66
RF Carrier signal with C/A
code modulated upon it.
The RF2638 BPSK modulator from RF Micro Devices was choused for this task. This BPSK
modulator is housed in small MSOP-8 package and has the following functional block diagram.
Figure 71: The RF2638 package and functional block diagram
The LO inputs are local oscillation inputs where LO- and LO+ are inverse of each other. Only
LO+ is used so LO- is coupled to ground via a capacitor. Such a capacitor prevents dc noise and
interference from the ground plane of the PCB to reach the LO- input. The IF inputs are also
inverses of each other and IF+ is coupled to ground in the same way as LO-, since only IF is
used. IF+ is fed with the 1023Bit data stream from the C/A code generator. Pin 3 is not used
and the voltage supply VCC is set to 3V. Pin 8 is the output RF BPSK modulated signal.
3.1.5
Printed Circuit board (PCB) design
After all the components of the pseudolite have been chosen and received from the
manufactures the printed circuit board had to be developed. The authors had to wait until all the
components were received so there would not be any risk that the layout of the board had to be
changed because the needed components were not available.
A component is missing from the design because at the time this thesis was writhen all the
requirements for that component were not known. The missing component is an FPGA or a
CPLD. The component is meant to house the C/A- code generator that has been programmed
in VHDL. Because the amount of needed hardware is not known at this moment, the authors
have not decided if the component should be an FPGA or a CPLD. The advantage of using a
CPLD instead of an FPGA is that the CPLD is non-volatile and thus no extra PROM is needed
to save the program. The disadvantage of CPLDs is that the amount of logical gates incorporated
inside is much lower then the amount of logical gates in FPGAs.
3.1.5.1
Components
Because an older version of Protel was used, most of the needed components were not available
in the component libraries and therefore the components had to be designed by the authors. The
fist task was to design the schematic part of the components. This part is used when a schematic
drawing of the circuit is done. During this design, the component body an pins were designed
and assigned. One of the components that have been designed is the TCXO. The component
schematic part can be seen in the picture below.
Figure 72: Component schematic part
67
The next step was the design of the component footprint. This part is used when the layout of
the printed circuit board is designed and it shows where the pins of the component will be
soldered onto the PCB. The footprint of the TCXO can be viewed in the picture below.
The difficult part of the design is to make sure that distances between and the dimensions of the
solder pads. To make sure that the right dimensions were used, the footprint and component
layout information from the component fact sheets were used. The fact sheets were procured by
the manufacturers.
Figure 73: Footprint for the TCXO
3.1.5.2
Circuit board design
Before the board level design begun a few problems had to be taken in consideration. First of all
the sizes of the printed circuit board had to be decided. The distance between components has to
be bigger than normal because this pseudolite is a prototype and it will be soldered by hand. By
having some distance between the components, the risk of damage to the nearby components
due to the soldering is minimized. In the same time, if needed, the copper lines can be rerouted
using wires. Second, because no FPGA was used, but the pseudolite needs one to function
properly so a 22 pin connector was added to the design so the right voltage and the XSA200
development board can be connected with the pseudolite. Of course not all the pins were used
but if needed the rest of the pins can be used.
The next step was to construct a schematic design of the pseudolite. After all the component pins
were connected the schematic was compiled to make sure there were no errors. The schematics
of the pseudolite can be viewed in the figure below.
68
Figure 74: Schematic design of the pseudolite with the first PLL circuit
Figure 75: Schematic design of the pseudolite with the second PLL circuit
69
After the compilation, a PCB project was created and the PCB was updated with the new
components. After placing the components onto the PCB the routing of the wires was done
automatically using the Auto Route All command. The system was allowed to rout on both sides
of the PCB but as few vias as possible were to be used. The following pictures shows the layout
of the pseudolite.
Figure 76: The layout of the pseudolite PCB with the first PLL
Figure 77: The layout of the pseudolite PCB with the second PLL
70
3.2
Simulation and synthesizing
The PLL designs must be simulated in order to check their behaviour. A model of the first PLL
circuit was built in Simulink. The second PLL circuit came with a program and was also
simulated. The C/A code generator chosen at the design stage was already simulated successfully
and should now be synthesized on a XSA200 development board.
3.2.1
Simulations of the first PLL circuit
In order to check the design of this PLL a model was built in Simulink (Matlab).
Figure 78: Simulink Model of the first PLL circuit
This model was a bit slow to simulate since the loop from the VCO into the phase detector has a
frequency that is 256*315=80640 times higher than the inner frequency of only 19531.25Hz
inside the phase detector. This means that things change very slowly in the simulation. The
simulation of this model needed a couple hours in order to get any useable readings.
The result from these simulations suggests that the circuit isn’t stable enough. The best result is
shown in appendix F and here one can se that the circuit is off with 293.09Hz. The
VCONTROL output should rise and form a straight line but here it varies 0.000025 Volt. The authors
of this thesis weren’t satisfied with these simulations and a new approach was needed.
71
3.2.2
Simulation of the second PLL circuit
This PLL was simulated in a program from Analog Devices called ADIsimPLL version 2.5. This
program can be downloaded from Analog Devices homepage (www.analog.com). The user can
specify what sort of PLL that is to be designed and what sort of reference source that should be
used. The program also comes with libraries of PLL synthesizers from Analog Devices. Since the
ADF4360-4 comes with an inbuilt VCO it is desirable to come up with a design that uses this
feature. The program also has libraries of ideal filters and standard component filters. The filter
chosen for this design was a simple passive low pass filter. The passive filter and the components
values can be found in the appendix D. In this appendix one can also se the coupling of the filter
and the simulation results of the circuit. As the simulation plot shows, the PLL locks on to the
L1 frequency (1572.42MHz). This simulation suggests that the circuit will work and that the exact
L1 frequency is achieved.
3.2.3
Synthesizing of the C/A code generator
After the successful construction of the C/A- code generator with the aid of Active- HDL the
program code had to be further processed with other programs in order to test the code on a
development board. The programs used were Xilinx ISE and ModelSimII. Even a development
board was purchased form XESS. The development board used is XSA200, which uses an FPGA
from the Xilinx Spartan FPGA family. When the program code was compiled with the new
programs there were no errors detected. So the next step was to connect all the units together
and run the whole system. When the whole system was synthesised, the program found two
errors. Both errors came from the XOR unit and the error was that the outputs were connected
to GND. After further investigation, an error in the program code was detected and adjusted.
After rerunning the synthetization no errors were found. The synthetization rapport can be
found as Appendix H. The next step is to implement the design. During the implementation of
the design, a map report was generated. In the map report one can check how much hardware is
used and how it has been mapped. The map report can be found in Appendix I. The final step is
the generation of the programming file. The programming file is then loaded onto the XSA200development board for testing. The programming file generation report is in Appendix I.
3.3
Results and Further work with the prototype
The design of the simple pseudolite was a success according to the obtained simulation results.
The second PLL design was chosen since it delivered the exact L1 frequency and since it was
more stable than the first PLL circuit. The C/A code generator was simulated successfully. A
table of costs of our prototype, with the second PLL design and a CPLD, can be viewed in
Appendix J.
The C/A code should be loaded into a non volatile FPGA component or a CPLD. The PLL
circuit, the TCXO and the mixer comes in standard components and the next step is to put the
components on the PCB and verify the circuits.
When the simple pseudolite is verified and is working well, it can be modified into a pulsed
pseudolite, a synchrolite, a transceiver or a LocataLite. All that is needed are some more design
evaluation of some additional circuits.
72
4
4.1
Recommendations for HTC Sweden AB
Interesting techniques and costs
Three techniques were chosen to be considered for HTC Sweden AB’s agenda. These techniques
are Self Calibrating Pseudolite Array (SCPA), Locata Navigation System (LNS) and the
Asynchronous Pseudolite System using Carrier Phase measurements. These techniques have
advantages and disadvantages because their different architectures. The costs for these techniques
vary a bit as well.
4.1.1
Self Calibrating Pseudolite Array
4.1.1.1
Advantage
One of the biggest advantages of this navigation technique is its ability to self calibrate. Because
the system can self calibrate one can use it in almost any terrain possible, the system can be used
as an indoor navigation system.
[15] The system has a better geometric observability because pseudorange and carrier- phase
measurements are added from other transmitters to the transceiver, system states as clock offsets
and device locations become more observable. If system biases such as carrier- phase integers are
known some geometric parameters can be solved directly rather then by iteration of a set of
nonlinear equations. Even the robustness of the system is improved because the greater number
of measurements. That yields that the system is less sensitive to signal dropouts.
Because the systems ability to synchronize the clocks directly eliminates the need for a separate
reference station
4.1.1.2
Disadvantage
The near/far problem is more severe because the signals from the collocated transmitter
(pseudolite) may interfere with the receiver so that the receiver would not be able to track and
receive the GPS signals from the nearby transceivers.
Because the system doesn’t use only transmitters but uses transceivers, the overall cost of the
system is higher. The extra hardware that is added to the system is first of all the extra receivers.
Even if the receivers are rather cheap, their addition makes the system more expensive. The
system also needs a communication link between the receivers so that they can share data. This
link could be either wired or wireless, however it raises the cost.
4.1.1.3
User- friendly
Because of its self calibrating ability the user friendly level of the system is very high. If the
system is used for indoor navigation, the user can place the transceivers more or less wherever
possible. For example if a system containing four transceivers, one mobile and three stationary, a
equilateral triangle like geometry should be used. The forth transceiver can both navigate inside
of the triangle or outside it. If the mobile unit is allowed to move outside the triangle a more
advanced sensor system should be used so that the mobile unit won’t collide with a nearby
obstacle.
If a higher accuracy is desired or a bigger area has to be covered, extra transceivers can be added
to the system.
73
4.1.1.4
Estimated costs
The authors of this thesis have developed a pseudolite that can be used for this task. Because
most of the components the authors used were free samples received from different component
distributors both from Sweden and USA the exact cost of the pseudolite can not be calculated.
Therefore only a ruff estimation of the overall cost can be calculated. The price of constructing
one pseudolite is between 10 000 to 15 000 Swedish crowns.
The authors have also contacted the company IntegriNautics in California. IntegriNautics is the
only manufacturer of such a device, known to the authors. The price of their pseudolites is
between 10 000 and 15 000 US dollars. The price is not the only problem however since they do
not manufacture pseudolites any more. The company will however begin manufacturing new
pseudolites in august 2005.
4.1.2
Locata Navigation System
4.1.2.1 Advantage
When using GPS like positioning system it is very important that the system is time synchronised.
As mentioned earlier in this thesis, a very small clock drift yields a position error of several tens
of meters due to the speed of light. The Locata Navigation System has the ability to achieve exact
clock synchronisation without any significant clock drift. Therefore a centimetre level accuracy
can be achieved.
There is no need for an exact measurement of the LocataLites position, because during the
initialisation of the LNS four LocataLites can be placed outdoor so that the GPS system can be
used to pinpoint their exact location. Afterwards, the system can compute the location of the
LocataLites placed indoor so their exact location is known. This is possible only because the
system uses the WGS-84 coordinate system which is the same coordinate system that the GPS
uses.
The system can be enhanced by adding additional LocataLites, and therefore bigger area coverage
can be achieved.
4.1.2.2
Disadvantage
More sophisticated hardware is needed because the LocataLite must be able to receive signals
both from the GPS satellites and from other LocataLites. Therefore the overall cost of the
system is increased. If of the shelf parts are used, for example GPS receivers, the firmware must
be changed.
Because helix antennas are not used problems like the near/far problem and signal multipath
must be taken in concern.
4.1.2.3
User-friendly
The system is very user-friendly, especially after it is initialised. One of the reasons is its ability to
self compute the position of the LocataLites using the standard GPS system and its ability to self
synchronise. If the system is used for indoor navigation, the user can have four LocataLites
outdoor in the close proximity of the indoor navigation area. Because the signal power from the
LocataLites is higher then the signal power of the GPS satellites, the signal is able to penetrate
through walls and therefore other LocataLites can be placed indoors so higher indoor navigation
accuracy can be achieved.
74
After initialisation of the system the user doesn’t have to recalibrate the system. The
synchronisation of the system clocks is done automatically once every second. The LocataLites
can autonomously survey and navigate themselves into a positioning system.
4.1.2.4
Estimated costs
The cost of such a system is more or less the same as for the Self Calibrating Pseudolite Array.
4.1.3
Asynchronous Pseudolite Navigation System
4.1.3.1
Advantage
The advantage of the asynchronous pseudolite navigation system, using carrier phase
measurement, is its simplicity. The system does not use any advanced self calibration algorithms
because the exact position of the pseudolites is already known. Another big advantage of this
system is that the hardware of the system is simple then it only uses pseudolites that send the
GPS like signal. Because most of the time the system is used, the receivers are not very close to
the transmitters, the near/far problem is reduced. Even the multipath problem can be reduced if
helix antennas are used to transmit the signal from the pseudolites.
4.1.3.2
Disadvantage
The biggest drawback of this navigation system is that the exact position of the pseudolite must
be known. Another drawback of the system is that a wireless data link has to be used so that the
reference station can send correction messages to the user.
4.1.3.3
User- friendly
The level of user friendliness is quite low because some work has to be done before the system
can be used. As mentioned earlier, the exact position of the pseudolites has to be known. This
problem can be resolved by making sure that when the pseudolite array is deployed, it can only
be deployed in only one way and the exact position of the pseudolites can be known.
The pseudolites can be placed on poles that have a predefined height. That way the height of the
pseudolites is known. If the poles are connected to each other with ribbons so that when pulled
apart they build a square then the distance between the poles is always the same. To be absolutely
sure that the right geometry is achieved a laser measuring device can be used to make sure that
the diagonal distance between the poles is right. At the same time the ribbons between the poles
can be used to seal off the working area.
If the reference station is mounted on one of the poles and that pole defines the origin of the
coordinate system then the exact location of every pseudolite inside the coordinate system will be
known.
4.1.3.4
Estimated costs
Because the system uses less hardware then the SCPA and LNS the overall cost is much lower.
If four pseudolites, two receivers, wireless link and one control station were to be used the
system cost should be less then 80 000 Swedish crowns.
75
4.2
Further work
4.2.1
Continuing the project
The authors of this thesis have spent five months investigating indoor navigation techniques
based on pseudolites and pseudolite based transmitters. A prototype of a pseudolite has been
initialized and the current data suggests that it is possible to further develop this prototype to
more advanced systems. Since this sort of technique is very complicated and since not many
people have been working with it, knowledge about this technique will cost very much if an
expert is consulted. Therefore it would seem to be in HTC Sweden AB’s best interest to keep this
gained knowledge by letting the authors of this thesis continue this project.
4.2.2
Continuing the project reinforced with M.Sc candidates
The University can supply HTC Sweden AB with competent reinforcements for a very little cost.
Master of Science (M.Sc) candidates from chosen areas could support the project. Since the
authors of this thesis are well familiar with this technique, they should plan, direct and led the
project as well as working in their own special fields of the project. Advanced Project
Management is one of the authors listed merits and this knowledge could be well used in such a
situation. Hardware and software development are other merits of the authors that will be
essential when selecting M.Sc Candidates that best would fulfil the project’s needs. The
recruitment process should also be made by the authors since they by now know what sort of
reinforcement skills that are required and since the authors has good connections at the
University of Linköping.
4.2.3
Continuing the project reinforced with consultancy
If experienced consultancy is considered to be an option, then the project would probably have a
greater success rate but also a much higher cost. Consultancies at this level costs much more than
it should and the reason is that there aren’t that many experts in this kind of technique and they
know it. If experts is brought in to the project then HTC Sweden AB would ensure that their
needs is fulfilled by letting the authors of this thesis act as middle hand and regulate the project
after HTC Sweden AB’s needs.
4.2.4
Outsourcing
If the project is completely outsourced to another company then the price would probably be
high. A high level of fulfilment comes with this high price but what do HTC Sweden AB really
get for their money? Without technical supervision and interaction from HTC Sweden AB’s part
it is possible that they will receive a product that fulfils their needs but is ridiculous complex and
thereby also overpriced. Even if the project is outsourced it is still of great value to interact and
help the outsourcing company to design the product during its whole life cycle.
4.2.5
Joint Venture
Why not gather strength and ambitions from other companies with similar needs but in other
markets. This will split the costs between many companies. If the authors of this thesis represent
HTC Sweden AB in this task, then they are able to contribute with their gained knowledge in this
area. A combined project would probably speed up the development time as well.
76
4.3
Comments
4.3.1
Usage of the Hammerhead
There are other ways to navigate indoor. The ones suggested by the authors have already been
tested and proved by others to work [7],[14],[15],[19]. Of course there are other ways to navigate
indoors with GPS like systems. For instance a system using several GPS receivers based on the
Hammerhead chip can be used to navigate with the aid of the GPS. The problem is that the
accuracy of the system is not centimetre level. Since the Hammerhead chip isn’t on the market
yet, its impossible to say how well it works. An indoor navigation system based on Hammerhead
chips can be augmented with a single indoor positioned pseudolite to achieve higher precision. In
this case the exact position of the pseudolite must be known. Several systems like this one have
been developed to augment the GPS when it is used for precision landing of aircrafts.
4.3.2
Using transceivers and SCPA
One idea is to have the whole processing unit on the machine. The processing unit is the
computer that calculates the position, trajectory and navigation commands of the mobile unit. By
doing so an extra wireless link between the mobile unit and the processing unit is no longer
needed and the risk of interference between the SCPA and other wireless systems is minimised.
The transceiver antenna should be placed some where as far as possible from engines, generators
or other parts of the machine that generate electromagnetic fields that could severely deteriorate
the functionality of the navigation system. A perfect location for the transceiver is as high as
possible and it should have all the other transceivers in its line of sight.
The other transceivers could be placed by the user before the system is initiated. The exact
position of the other transceivers is not important because of the systems ability to self- calibrate.
At least four stationary transceivers should be used to ensure good navigation precision. The
stationary transceivers can be placed in a square like geometry with 50 meters between each
other. By doing so an area of 250 square meters can be covered. If wider area coverage is needed
some design parameters can be changed to achieve that. After the work is done inside this area
the transceivers can easily be moved and a new working area can be set up. Like mentioned
earlier in this thesis the system is very user friendly.
4.3.3
Considering other frequencies
[25] When the authors began their work with the indoor navigation system they were asked to
evaluate if it is possible to navigate indoors with a GPS like system. Therefore the authors
designed the prototype pseudolite to work with the standard carrier frequency L1 at 1575.42
MHz. What the authors did not know at that time is that the frequency band of 1563 to 1587
MHz is reserved only for receiving from the GPS- satellites and therefore a transmitter that uses
this frequency band may not be used. In Sweden the authority that decides if a frequency may or
may not be used is the PTS. The authors have contacted PTS and received information about
this frequency band. The contact person at PTS pointed out that it is possible to apply for the use
of this frequency band, but PTS has never allowed other transmitters to transmit on this
frequency band. There is one way to resolve this problem. The frequency band of 5725 to 5875
MHz, 2400 to 2483.5 MHz or 24.0 to 24.25 GHz can be used. The system is more or less the
same only a few design parameters must be changed so the pseudolite sends on the new
frequency band. These frequency bands can be used if the highest transmitting power is 25 mW
according to the exception from the licence obligation in accordance with Section5, item 5[a]. If a
higher power is needed the frequency band 5795 to 5805 MHz can be used for up to 2 Watt
according to the exception from the licence obligation in accordance with Section5, item 5.
77
Glossary
[A]
Accuracy
The difference between measured position, time and velocity and the
known/expected value of these parameters yield a level of accuracy. Small
difference between measured and expected values gives high accuracy and the
other way around.
Ambiguity
The unknown number of cycles (number of wavelength) between the
satellite/pseudolite and the receiver is called ambiguity. Once this number(integer)
is known it is possible to use carrier phase measurements in order to determine an
accurate distance between the receiver and the satellite/pseudolite.
Ambiguity Resolution
In order to use carrier phase measurements it is necessary to resolve the integer
ambiguity. In order words, determine the whole number of wavelength between
the receiver and the satellite/pseudolite. Ambiguity resolutions are methods to find
this integer ambiguity.
.
Anti-spoofing mode
Anti-spoofing mode is the process when encrypting the P code modulation
sequence so it can’t be replicated or falsified by unauthorized users. When the P
code is encrypted it’s called P(Y) code.
Attenuation
A radio signal is reduced in strength due to free space loss, reflection, absorption
and dispersion.
Augmentation
Enhance accuracy with another unit.
[B]
Baseline
The distance between a reference station and a receiver is called Baseline.
Bias
Systematic errors that cause the measured value to differ from the expected or
theoretical value are called biases. Biases are constant and often measurable.
Block diagram
A graphical system overview that shows no details in the circuitry but gives a good
view of the systems ingoing parts. Square blocks with text are most commonly
used.
Bit
A bit symbolises the binary value of high or low. A bit can either be 1 or 0.
Byte
Eight bits build one data byte.
78
[C]
C/A Code
The Coarse/Acquisition code (or Clear/Acquisition code) is also called the civilian
code since it is mainly used for civilian GPS applications. The C/A code is a PRN
noise code and is modulated on the L1 (1575.42MHz) frequency.
[D]
dB
Decibel is logarithmic measurement of power or gain ratios.
DC
DC is short for Direct Current. DC voltage is a linear voltage that is applied in one
direction. The opposite to AC.
Deteriorate
Falls apart and get worse.
DOP
Dilution Of Precision is a value expressing a confidence factor based on the
geometry of the Satellite constellation. Different kinds of DOP are GDOP, PDOP,
HTDOP, HDOP, VDOP, TDOP where G is geometrical DOP and involve all
DOP parameters (Height, Latitude, Longitudes and Clock offset). PDOP is the 3D
parameters (latitude, height and longitude). TDOP is only clock offset. VDOP is
just heght. PDOP is GDOP disregarding the clock offset and HDOP is Latitude
and Longitude.
[G]
Gold code
The Gold is a series of codes built of Pseudorandom Noise.
[L]
LSB
Least Significant Bit. This is the lowest value/position.
[M]
Modulo-2 sum
A bitwise XOR addition generates a Modulo-2 sum.
MSB
Most Significant Bit. This bit has the highest value/position.
[P]
Pseudorandom
Pseudo means false and pseudorandom can be described as a pattern that seems
random but isn’t in reality. The complex pattern and long cycle makes the code
seem random.
[R]
Register
A Register is a temporary software storage element for binary bits.
[V]
VCO
Voltage Controlled Oscillation. The oscillation output from this function varies
with the applied input voltage. A constant K V determine how much the oscillation
increase/decrees when the input voltage increase/decrees.
79
Bibliography
[1]
Trimble (2004), All about GPS [www]
http://www.trimble.com/gps/index.html (091504)
[2]
HowStuffWorks, How GPS works [www]
http://electronics.howstuffworks.com/gps.htm (091304)
[3]
Nordling Carl, Österlund Jonny (1999), Physics handbook for science and
engineering, Page 12, Lund, Studentlitteratur Sixth edition, ISBN 91-44-00823-6.
[4]
Kaplan Elliott D. (1996), Understanding GPS Principles and Application, London,
ARTECH HOUSE INC, First edition, ISBN 0-89006-793-7.
[5]
ICD-GPS-200 (Unclassified documents) [www]
http://www.navcen.uscg.gov/pubs/gps/icd200/icd200cw1234.pdf (081204)
[6]
Bradford W. Parkinson James J. Spilker Jr. (1996), Global Positioning Systems:
Theory and Applications Volume I, Washington, American Institute of
Aeronautics and Astronautics, Third edition, ISBN 1-56347-106-X.
[7]
Cobb Stewart H (1997), GPS pseudolites: Theory, design and application [www]
http://www.tik.ee.ethz.ch/~beutel/projects/picopositioning/GPS_pseudolites_st
uthesis.pdf (081204)
[8]
GPS World, Glossary (2004) [www]
http://www.gpsworld.com/gpsworld/static/staticHtml.jsp?id=8000 (081204)
[9]
Bradford W. Parkinson James J. Spilker Jr. (1996), Global Positioning Systems:
Theory and Applications Volume II, Washington, American Institute of
Aeronautics and Astronautics, Third edition, ISBN 1-56347-107-8.
[10]
Department of Geography, University of Texas, Dana Peter H (1994), Global
Positioning System Overview [www]
http://www.colorado.edu/geography/gcraft/notes/gps/gps_f.html (081204)
[11]
Mobile positioning, Glossary zone (2004) [www]
www.mobilepositioning.com/glossary.asp (081204)
[12]
Stalling William (2002), Wireless Communication and Networks, Upper Saddle
River New Jersey, Prentice Hall, First edition, ISBN 0-13-040864-6.
[13]
Doohee Yun, Haeyoung Jun at Seoul National University GPS Lab, Indoor
navigation system using pseudolite [www]
http://gps.snu.ac.kr/research/pseudolite/indoor_eng.htm#%203.%20System%20
Concept (081204)
[14]
Liwen Dai, Jinling Wang, Toshiaki Tsujii, Chris Rizo, Pseudolite-based inverted
positioning and its applications (2003) [www]
http://www.gmat.unsw.edu.au/snap/publications/dai_etal2001d.pdf (081204)
80
[15]
LeMaster Edward A at Stanford University (2002), Self-Calibrating Pseudolite
Arrays: Theory an Experiment [www]
http://sun-valley.stanford.edu/papers/LeMaster:2002.pdf (081204)
[16]
David A. Johns Ken Martin (1997), Analog Integrated Circuit Design, Toronto,
John Wiley and Sons INC, First edition, ISBN 0-471-14448-7.
[17]
Brown Stephen, Vransic Zvonko (2000), Fundamentals of Digital Logic with
VHDL Design, Toronto, McGraw Hill, First Edition, ISBN 0-07-012591-0.
[18]
The Satellite Navigation and Positioning Group (SNAP), A glossary of GPS terms
(2004) [www]
www.gmat.unsw.edu.au/snap/gps/glossary_a-c.htm (081204
[19]
BARNES, J., RIZOS, C., WANG, J., SMALL, D., VOIGHT, G., & GAMBALE,
N (2003), LocataNet: The positioning technology of the future? [www]
http://www.gmat.unsw.edu.au/snap/publications/barnes_etal2003a.pdf (081204)
[20]
BARNES J, RIZOS C, WANG J, SMALL D, VOIGHT G, & GAMBALE N
(2003), Intelligent synchronized pseudolites for cm-level stand-alone positioning
[www]
http://www.gmat.unsw.edu.au/snap/publications/barnes_etal2003d.pdf (081204)
[21]
Infineon homepage, Hammerhead a single chip GPS solution (081204) [www]
http://www.infineon.com/cmc_upload/documents/011/4061/pmb2520pb_1.pdf (041122)
[22]
physorg.com [www]
www.physorg.com/printnews.php?newsid=1532 (041122)
[23]
Morley Thomas G. Augmentation of GPS with Pseudolite in a Marine
Environment [www]
http://www.geomatics.ucalgary.ca/Papers/Thesis/GL/97.20108.TMorley.pdf
(121304)
[24]
Analog Devices homepage [www]
http://www.analog.com/ (041124)
[25]
National Post and Telecom Agency’s Regulations on Exemptions from the Licence
Obligation for Certain Radio Transmitters; PTSFS 2004:8 [www]
http://www.pts.se/Archive/Documents/EN/2004_8_engelska.pdf
81
Appendix A
The Project specification
Title
Indoor navigation using Pseudolites
Students
Rikard Eriksson, riker075@student.liu.se , Linköping University, Campus Norrköping, Sweden.
Vlad Badea, vlaba533@student.liu.se , Linköping University, Campus Norrköping, Sweden.
Examiner
Ole Pedersen, olepe@itn.liu.se , Department of Science and Technology, Linköping University,
Sweden.
Supervisor
Karl Thysell, Karl.thysell@htc.se , Development department, HTC Sweden AB, BOX 69, 614 22
Söderköping.
Purpose and Goal
The purpose with this Master thesis is to investigate the application of pseudolites for indoor
navigation of a large machine, in big areas. If it’s considered possible to use Pseudolites for this
task and if there is enough time then a prototype will be built.
Classification
Depending on the obtained results there might be reasons for classify parts of this thesis. An
alternative is to give two presentations, where some parts are left out in the official version. If
this is not possible then the whole project should be classified according to Swedish laws.
Thesis level and academic points
This thesis is for the Master of Science degree in Electronics Design and should take about 20
working weeks to finalize. This degree is given upon completion of the project by Department of
Science and Technology Linköping University, Campus Norrköping, Sweden.
Fee for the students
The fee for this project is 1000 Swedish crowns per academic point and if HTC Sweden AB find
the results to be of use for their purpose, then additional 500 Swedish crowns per academic is
received by the students as a bonus. The fee will be divided equally between the students.
Outline of the project
-Pre study
-Design
-Simulation
-Verification
-Prototype (If time permits)
-Report
-Project presentation
82
Recourses
HTC Sweden AB will provide with all recourses needed for this project. The following things
must be at hand for the students.
-Computers connected to the internet and with a connected printer
-Desks and chairs
-All the tools and components needed for the construction of a prototype
The University’s CAD programs are available if they should be needed
The report
The report must be of the standards set by the Department of Science and Technology. (Magnus
Merkel, 1996, Technical reports and thesis)
Preliminary Time table
The project starts September the first 2004 and ends the 19th of January 2005. This makes a total
project time of twenty weeks. A presentation date is set later. The table below shows the
preliminary time table of this project.
End Appendix A
83
Appendix B
Table of GPS signals
Sender
PRN
number
C/A code
tao
selection
C/A code
Delay in
chips
P code
Delay in
chips
First 10
C/A chips
(oct)
First 12
P chips
(oct)
1
2 XOR 6
5
1
1440
4444
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
3 XOR 7
4 XOR 8
5 XOR 9
1 XOR 9
2 XOR 10
1 XOR 8
2 XOR 9
3 XOR 10
2 XOR 3
3 XOR 4
5 XOR 6
6 XOR 7
7 XOR 8
8 XOR 9
9 XOR 10
1 XOR 4
2 XOR 5
3 XOR 6
4 XOR 7
5 XOR 8
6 XOR 9
1 XOR 3
4 XOR 6
5 XOR 7
6 XOR 8
7 XOR 9
8 XOR 10
1 XOR 6
2 XOR 7
3 XOR 8
4 XOR 9
5 XOR 10
4 XOR 10
1 XOR 7
2 XOR 8
4 XOR 10
6
7
8
17
18
139
140
141
251
252
254
255
256
257
258
469
470
471
472
473
474
509
512
513
514
515
516
859
860
861
862
863
950
947
948
950
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
1620
1710
1744
1133
1455
1131
1454
1626
1504
1642
1750
1764
1772
1775
1776
1156
1467
1633
1715
1746
1763
1063
1706
1743
1761
1770
1774
1127
1453
1625
1712
1745
1713
1134
1456
1713
4000
4222
4333
4377
7355
4344
4340
4342
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
4343
End Appendix B
84
Appendix C
Datasheets
Datasheets for the components used for the prototype described in chapter 3 are listed below:
MC145151-2 PLL Frequency Synthesizer from Motorola [www]
http://www.datasheetcatalog.com/datasheets_pdf/M/C/1/4/MC145151-2.shtml (131204)
RF2638 BPSK modulator from RF Micro Devices [www]
http://www.rfmd.com/DataBooks/db97/2638.pdf (131204)
NEC µ PB1507GV Prescaler from NEC [www]
http://www.ee.nec.de/_pdf/P10767EJ2V0DS00.PDF (131204)
ADF4360-4 PLL Frequency Synthesizer from Analog Devices [www]
http://www.analog.com/en/prod/0%2C2877%2CADF4360%25252D4%2C00.html
M3500-1324 VCO from Micronetics [www]
http://www.micronetics.com/pdf/vco1324.pdf (131204)
End Appendix C
85
Appendix D
ADIsimPLL simulation
Simulation report
PLL Chip is ADF4360-4
VCO is ADF4360-4
Reference is custom (10MHz)
Frequency Domain Analysis of PLL
Analysis at PLL output frequency of 1.58GHz
Phase Noise Table
Freq
Total
100
-69.80
1.00k
-61.73
10.0k
-85.24
100k
-111.0
1.00M
-132.0
VCO
-71.39
-62.44
-86.27
-111.0
-132.0
Ref
------
Chip
-75.01
-72.39
-95.51
-135.4
-175.4
Reference Spurious
Noise and Jitter Calculations include the first 10 ref spurs
First three spurs: -300 dBc -300 dBc -300 dBc
Phase jitter using brick wall filter
from 10.0kHz to 100kHz
Phase Jitter 0.33 degrees rms
Carrier Recovery phase jitter
Carrier recovery bandwidth 6.40kHz damping factor 0.7071
Symbol Filter cutoff 32.0kHz Butterworth with 3 poles
Phase Jitter 1.09 degrees rms
Residual FM
from 300 Hz to 5.00kHz is 112 Hz
FM SNR
sinusoidal modulation with 10.0kHz peak deviation
Signal to Noise Ratio = 36.0 dB
ACP - Channel 1
Channel 1 is centred 25.0kHz from carrier with bandwidth 15.0kHz
Power in channel = -53.7dBc
---- End of Frequency Domain Results ---Transient Analysis of PLL
Power up transient to frequency of 1.58GHz
Simulation run for 2.54ms
Frequency Locking
Time to lock to 1.00kHz is 1.47ms
Time to lock to 10.0 Hz is 1.90ms
Phase Locking (VCO Output Phase)
Time to lock to 10.0 deg is 1.65ms
Time to lock to 1.00 deg is 1.80ms
Lock Detect Threshold
Time to lock detect exceeds 2.50 V is 250us
---- End of Time Domain Results ----
86
Filter
-92.49
-73.71
-94.60
-134.4
-174.4
Coupling of the circuit
The values of the counters and the Prescaler
87
The output from the PLL
End Appendix D
88
Appendix E
The ten first bits of the first 1023 bit C/A code
End Appendix E
89
Appendix F
Simulink simulation
K VCO =80Mhz/V
I CP =1mA
VTUNE =4 V
FVCO = 1575.00029309 MHz
End Appendix F
90
Appendix G
VHDL code
The code for the G1 right shift register
library ieee;
use ieee.std_logic_1164.all;
entity Linear_Right_Shift_Registe_G1 is
port( Clock, Reset:
in
OutputG1:
end Linear_Right_Shift_Registe_G1;
std_logic;
out std_logic);
Architecture Behavior of Linear_Right_Shift_Registe_G1 is
signal Q:
std_logic_vector(1 to 10);
signal TAP3: std_logic;
signal TAP10: std_logic;
signal counter: integer range 0 to 1023 := 1023;
signal Ut: std_logic;
begin
TAP3 <= Q(3);
TAP10 <= Q(10);
OutputG1 <= Ut;
process(Clock,Reset)
begin
if Reset = '0' then
Q <= "1111111111";
counter <= 1023;
elsif(Clock'EVENT and Clock = '1') then
if counter > 0 then
Ut <= Q(10);
Q(10) <= Q(9);
Q(9) <= Q(8);
Q(8) <= Q(7);
Q(7) <= Q(6);
Q(6) <= Q(5);
Q(5) <= Q(4);
Q(4) <= Q(3);
Q(3) <= Q(2);
Q(2) <= Q(1);
Q(1) <= TAP3 XOR TAP10;
counter <= counter -1;
else
counter <= 1023;
Q<="1111111111";
end if;
end if;
end process;
end Behavior;
91
The code for the G2 right shift register
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Linear_Right_Shift_Register_G2 is
port( Clock, Reset:
end Linear_Right_Shift_Register_G2;
in
OutputG2:
Delay_Select:
std_logic;
in
architecture behavior of Linear_Right_Shift_Register_G2 is
signal Q:
std_logic_vector(1 to 10);
signal TAP: std_logic_vector(1 to 10);
signal Phase_selected: std_logic;
signal DelayTap1: integer range 1 to 10;
signal DelayTap2: integer range 1 to 10;
signal counter: integer range 0 to 1023 := 1023;
begin
TAP <= Q;
OutputG2 <= Phase_selected;
process(Delay_Select)
begin
if Delay_Select = "100000" then--1
DelayTap1 <= 2;
DelayTap2 <= 6;
elsif Delay_Select = "010000" then--2
DelayTap1 <= 3;
DelayTap2 <= 7;
elsif Delay_Select = "110000" then--3
DelayTap1 <= 4;
DelayTap2 <= 8;
elsif Delay_Select = "001000" then--4
DelayTap1 <= 5;
DelayTap2 <= 9;
elsif Delay_Select = "101000" then--5
DelayTap1 <= 1;
DelayTap2 <= 9;
elsif Delay_Select = "011000" then--6
DelayTap1 <= 2;
DelayTap2 <= 10;
elsif Delay_Select = "111000" then--7
DelayTap1 <= 1;
DelayTap2 <= 8;
elsif Delay_Select = "000100" then--8
DelayTap1 <= 2;
DelayTap2 <= 9;
elsif Delay_Select = "100100" then
DelayTap1 <= 3;
DelayTap2 <= 10;
elsif Delay_Select = "010100" then
DelayTap1 <= 2;
DelayTap2 <= 3;
elsif Delay_Select = "110100" then
DelayTap1 <= 3;
DelayTap2 <= 4;
elsif Delay_Select = "001100" then
DelayTap1 <= 5;
DelayTap2 <= 6;
elsif Delay_Select = "101100" then
DelayTap1 <= 6;
DelayTap2 <= 7;
92
out std_logic;
std_logic_vector(0 to 5));
elsif Delay_Select = "011100" then
DelayTap1 <= 7;
DelayTap2 <= 8;
elsif Delay_Select = "111100" then
DelayTap1 <= 8;
DelayTap2 <= 9;
elsif Delay_Select = "000010" then
DelayTap1 <= 9;
DelayTap2 <= 10;
elsif Delay_Select = "100010" then
DelayTap1 <= 1;
DelayTap2 <= 4;
elsif Delay_Select = "010010" then
DelayTap1 <= 2;
DelayTap2 <= 5;
elsif Delay_Select = "110010" then
DelayTap1 <= 3;
DelayTap2 <= 6;
elsif Delay_Select = "001010" then
DelayTap1 <= 4;
DelayTap2 <= 7;
elsif Delay_Select = "101010" then
DelayTap1 <= 5;
DelayTap2 <= 8;
elsif Delay_Select = "011010" then
DelayTap1 <= 6;
DelayTap2 <= 9;
elsif Delay_Select = "111010" then
DelayTap1 <= 1;
DelayTap2 <= 3;
elsif Delay_Select = "000110" then
DelayTap1 <= 4;
DelayTap2 <= 6;
elsif Delay_Select = "100110" then
DelayTap1 <= 5;
DelayTap2 <= 7;
elsif Delay_Select = "010110" then
DelayTap1 <= 6;
DelayTap2 <= 8;
elsif Delay_Select = "110110" then
DelayTap1 <= 7;
DelayTap2 <= 9;
elsif Delay_Select = "001110" then
DelayTap1 <= 8;
DelayTap2 <= 10;
elsif Delay_Select = "101110" then
DelayTap1 <= 1;
DelayTap2 <= 6;
elsif Delay_Select = "011110" then
DelayTap1 <= 2;
DelayTap2 <= 7;
elsif Delay_Select = "111110" then
DelayTap1 <= 3;
DelayTap2 <= 8;
elsif Delay_Select = "000001" then
DelayTap1 <= 4;
DelayTap2 <= 9;
elsif Delay_Select = "100001" then
DelayTap1 <= 5;
DelayTap2 <= 10;
elsif Delay_Select = "010001" then
DelayTap1 <= 4;
93
DelayTap2 <= 10;
elsif Delay_Select = "110001" then
DelayTap1 <= 1;
DelayTap2 <= 7;
elsif Delay_Select = "001001" then
DelayTap1 <= 2;
DelayTap2 <= 8;
elsif Delay_Select = "101001" then
DelayTap1 <= 4;
DelayTap2 <= 10;
else
DelayTap1 <= 4;
DelayTap2 <= 10;
end if;
end process;
(DelayTap2);
process(Clock,Reset)
begin
if Reset = '0' then
Q <= "1111111111";
counter <= 1023;
elsif(Clock'EVENT and Clock = '1') then
if counter > 0 then
Phase_selected <= TAP(DelayTap1) xor TAP
Q(10) <= Q(9);
xor TAP(6) xor TAP(8) xor TAP(9) xor TAP(10);
Q(9) <= Q(8);
Q(8) <= Q(7);
Q(7) <= Q(6);
Q(6) <= Q(5);
Q(5) <= Q(4);
Q(4) <= Q(3);
Q(3) <= Q(2);
Q(2) <= Q(1);
Q(1) <= TAP(2) XOR TAP(3)
counter <= counter-1;
else
counter <= 1023;
Q<="1111111111";
end if;
end if;
end process;
end behavior;
End Appendix G
94
Appendix H
Synthetization rapport
Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.32 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.32 s | Elapsed : 0.00 / 1.00 s
--> Reading design: ca_code_gen.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
========================================================
=================
*
Synthesis Options Summary
*
========================================================
=================
---- Source Parameters
Input File Name
: ca_code_gen.prj
Input Format
: mixed
Ignore Synthesis Constraint File : NO
Verilog Include Directory
:
---- Target Parameters
Output File Name
Output Format
Target Device
: ca_code_gen
: NGC
: xc2s200-5-fg256
---- Source Options
Top Module Name
: ca_code_gen
Automatic FSM Extraction
: YES
FSM Encoding Algorithm
: Auto
FSM Style
: lut
RAM Extraction
: Yes
95
RAM Style
: Auto
ROM Extraction
: Yes
ROM Style
: Auto
Mux Extraction
: YES
Mux Style
: Auto
Decoder Extraction
: YES
Priority Encoder Extraction
: YES
Shift Register Extraction
: YES
Logical Shifter Extraction
: YES
XOR Collapsing
: YES
Resource Sharing
: YES
Multiplier Style
: lut
Automatic Register Balancing
: No
---- Target Options
Add IO Buffers
: YES
Global Maximum Fanout
: 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication
: YES
Equivalent register Removal
: YES
Slice Packing
: YES
Pack IO Registers into IOBs
: auto
---- General Options
Optimization Goal
: Speed
Optimization Effort
:1
Keep Hierarchy
: NO
Global Optimization
: AllClockNets
RTL Output
: Yes
Write Timing Constraints
: NO
Hierarchy Separator
:_
Bus Delimiter
: <>
Case Specifier
: maintain
Slice Utilization Ratio
: 100
Slice Utilization Ratio Delta
:5
---- Other Options
lso
: ca_code_gen.lso
Read Cores
: YES
cross_clock_analysis
: NO
verilog2001
: YES
Optimize Instantiated Primitives : NO
tristate2logic
: No
========================================================
=================
========================================================
=================
*
HDL Compilation
*
96
========================================================
=================
Compiling vhdl file C:/Logic_CA/LRSR_G1.vhd in Library work.
Architecture behavior of Entity linear_right_shift_registe_g1 is up to date.
Compiling vhdl file C:/Logic_CA/LRSR_G2.vhd in Library work.
Architecture behavior of Entity linear_right_shift_register_g2 is up to date.
Compiling vhdl file C:/Logic_CA/ca_code_gen.vhf in Library work.
Entity <ca_code_gen> (Architecture <behavioral>) compiled.
========================================================
=================
*
HDL Analysis
*
========================================================
=================
Analyzing Entity <ca_code_gen> (Architecture <behavioral>).
Entity <ca_code_gen> analyzed. Unit <ca_code_gen> generated.
Analyzing Entity <linear_right_shift_registe_g1> (Architecture <behavior>).
Entity <linear_right_shift_registe_g1> analyzed. Unit <linear_right_shift_registe_g1> generated.
Analyzing Entity <linear_right_shift_register_g2> (Architecture <behavior>).
Entity <linear_right_shift_register_g2> analyzed. Unit <linear_right_shift_register_g2>
generated.
========================================================
=================
*
HDL Synthesis
*
========================================================
=================
Synthesizing Unit <linear_right_shift_register_g2>.
Related source file is C:/Logic_CA/LRSR_G2.vhd.
Using one-hot encoding for signal <DelayTap1>.
Using one-hot encoding for signal <DelayTap2>.
Found 64x20-bit ROM for signal <$n0097>.
Found 1-bit xor2 for signal <$n0095> created at line 147.
Found 10-bit comparator greater for signal <$n0096> created at line 146.
Found 10-bit subtractor for signal <$n0098> created at line 158.
Found 10-bit comparator lessequal for signal <$n0099> created at line 146.
Found 1-bit xor6 for signal <$n0102> created at line 157.
Found 10-bit register for signal <counter>.
Found 1-bit register for signal <Phase_selected>.
Found 10-bit register for signal <Q>.
Summary:
inferred 1 ROM(s).
inferred 21 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 2 Comparator(s).
inferred 1 Xor(s).
Unit <linear_right_shift_register_g2> synthesized.
97
Synthesizing Unit <linear_right_shift_registe_g1>.
Related source file is C:/Logic_CA/LRSR_G1.vhd.
Found 10-bit comparator greater for signal <$n0023> created at line 25.
Found 10-bit subtractor for signal <$n0024> created at line 37.
Found 10-bit comparator lessequal for signal <$n0025> created at line 25.
Found 1-bit xor2 for signal <$n0026> created at line 36.
Found 10-bit register for signal <counter>.
Found 10-bit register for signal <Q>.
Found 1-bit register for signal <Ut>.
Summary:
inferred 21 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 2 Comparator(s).
Unit <linear_right_shift_registe_g1> synthesized.
Synthesizing Unit <ca_code_gen>.
Related source file is C:/Logic_CA/ca_code_gen.vhf.
Unit <ca_code_gen> synthesized.
========================================================
=================
*
Advanced HDL Synthesis
*
========================================================
=================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
========================================================
=================
HDL Synthesis Report
Macro Statistics
# ROMs
:1
64x20-bit ROM
:1
# Adders/Subtractors
:2
10-bit subtractor
:2
# Registers
: 24
10-bit register
:2
1-bit register
: 22
# Comparators
:4
10-bit comparator lessequal
:2
10-bit comparator greater
:2
# Xors
:3
1-bit xor6
:1
98
1-bit xor2
:2
========================================================
=================
========================================================
=================
*
Low Level Synthesis
*
========================================================
=================
WARNING:Xst:1988 - Unit <linear_right_shift_registe_g1>: instances <Mcompar__n0023>,
<Mcompar__n0025> of unit <LPM_COMPARE_1> and unit <LPM_COMPARE_2> are
dual, second instance is removed
WARNING:Xst:1988 - Unit <linear_right_shift_register_g2>: instances <Mcompar__n0096>,
<Mcompar__n0099> of unit <LPM_COMPARE_1> and unit <LPM_COMPARE_2> are
dual, second instance is removed
Optimizing unit <ca_code_gen> ...
Optimizing unit <linear_right_shift_registe_g1> ...
Optimizing unit <linear_right_shift_register_g2> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ca_code_gen, actual ratio is 3.
========================================================
=================
*
Final Report
*
========================================================
=================
Final Results
RTL Top Level Output File Name : ca_code_gen.ngr
Top Level Output File Name
: ca_code_gen
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
Macro Statistics :
# ROMs
#
64x20-bit ROM
# Registers
#
1-bit register
#
10-bit register
# Adders/Subtractors
#
10-bit subtractor
:9
:1
:1
: 24
: 22
:2
:2
:2
99
# Comparators
:4
#
10-bit comparator greater : 2
#
10-bit comparator lessequal : 2
# Xors
:1
# 1-bit xor6
:1
Cell Usage :
# BELS
: 207
#
GND
:1
# LUT1
:4
#
LUT1_L
: 18
#
LUT2_D
:2
# LUT3
:9
#
LUT3_L
:1
# LUT4
: 48
#
LUT4_D
:8
#
LUT4_L
: 45
# MUXCY
: 18
#
MUXF5
: 21
#
MUXF6
: 10
#
VCC
:1
#
XOR2
:1
#
XORCY
: 20
# FlipFlops/Latches
: 42
#
FDE
:2
# FDP
: 40
# Clock Buffers
:1
# BUFGP
:1
# IO Buffers
:8
# IBUF
:7
#
OBUF
:1
========================================================
=================
Device utilization summary:
--------------------------Selected Device : 2s200fg256-5
Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of bonded IOBs:
Number of GCLKs:
77 out of 2352 3%
42 out of 4704 0%
135 out of 4704 2%
8 out of 180 4%
1 out of 4 25%
========================================================
=================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
100
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Clock
| BUFGP
| 42 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum period: 8.314ns (Maximum Frequency: 120.279MHz)
Minimum input arrival time before clock: 12.692ns
Maximum output required time after clock: 9.802ns
Maximum combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'Clock'
Delay:
8.314ns (Levels of Logic = 2)
Source:
XLXI_1_counter_8 (FF)
Destination:
XLXI_1_Ut (FF)
Source Clock:
Clock rising
Destination Clock: Clock rising
Data Path: XLXI_1_counter_8 to XLXI_1_Ut
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDP:C->Q
3 1.292 1.480 XLXI_1_counter_8 (XLXI_1_counter_8)
LUT4_D:I0->O
10 0.653 2.200 XLXI_1__n002324 (CHOICE17)
LUT4:I1->O
1 0.653 1.150 XLXI_1__n00221 (XLXI_1__n0022)
FDE:CE
0.886
XLXI_1_Ut
---------------------------------------Total
8.314ns (3.484ns logic, 4.830ns route)
(41.9% logic, 58.1% route)
------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'Clock'
Offset:
12.692ns (Levels of Logic = 6)
Source:
Delay<4> (PAD)
Destination:
XLXI_2_Phase_selected (FF)
Destination Clock: Clock rising
101
Data Path: Delay<4> to XLXI_2_Phase_selected
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
40 0.924 4.200 Delay_4_IBUF (Delay_4_IBUF)
LUT4:I0->O
1 0.653 1.150 XLXI_2_Mrom__n0097_inst_mux_f6_0_SW0
(N3644)
LUT3:I1->O
1 0.653 1.150 XLXI_2_Mrom__n0097_inst_mux_f6_0
(XLXI_2_DelayTap2<2>)
LUT4:I0->O
1 0.653 1.150 XLXI_2__n007126 (CHOICE12)
LUT4_L:I3->LO
1 0.653 0.100 XLXI_2__n007135 (XLXI_2__n0113<0>)
LUT4_L:I3->LO
1 0.653 0.000 XLXI_2_Mxor__n0095_Result1 (XLXI_2__n0095)
FDE:D
0.753
XLXI_2_Phase_selected
---------------------------------------Total
12.692ns (4.942ns logic, 7.750ns route)
(38.9% logic, 61.1% route)
------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'Clock'
Offset:
9.802ns (Levels of Logic = 2)
Source:
XLXI_1_Ut (FF)
Destination:
CA_Bit (PAD)
Source Clock:
Clock rising
Data Path: XLXI_1_Ut to CA_Bit
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDE:C->Q
1 1.292 1.150 XLXI_1_Ut (XLXI_1_Ut)
XOR2:I0->O
1 0.653 1.150 XLXI_3 (CA_Bit_OBUF)
OBUF:I->O
5.557
CA_Bit_OBUF (CA_Bit)
---------------------------------------Total
9.802ns (7.502ns logic, 2.300ns route)
(76.5% logic, 23.5% route)
========================================================
=================
CPU : 8.70 / 11.35 s | Elapsed : 9.00 / 11.00 s
-->
Total memory usage is 60536 kilobytes
End Appendix H
102
Appendix I
The programming file generation report
Release 6.3i Map G.35
Xilinx Mapping Report File for Design 'ca_code_gen'
Design Information
-----------------Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200-fg256-5 -cm
area -pr b -k 4 -c 100 -tx off -o ca_code_gen_map.ncd ca_code_gen.ngd
ca_code_gen.pcf
Target Device : x2s200
Target Package : fg256
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.16.8.2 $
Mapped Date : Wed Dec 08 10:20:51 2004
Design Summary
-------------Number of errors:
0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops:
42 out of 4,704 1%
Number of 4 input LUTs:
132 out of 4,704 2%
Logic Distribution:
Number of occupied Slices:
75 out of 2,352 3%
Number of Slices containing only related logic: 75 out of 75 100%
Number of Slices containing unrelated logic:
0 out of 75 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:
135 out of 4,704 2%
Number used as logic:
132
Number used as a route-thru:
3
Number of bonded IOBs:
8 out of 176 4%
Number of GCLKs:
1 out of 4 25%
Number of GCLKIOBs:
1 out of
4 25%
Total equivalent gate count for design: 1,335
Additional JTAG gate count for IOBs: 432
Peak Memory Usage: 62 MB
NOTES:
Related logic is defined as being logic that shares connectivity e.g. two LUTs are "related" if they share common inputs.
When assembling slices, Map gives priority to combine logic that
is related. Doing so results in the best timing performance.
Unrelated logic shares no connectivity. Map will only begin
packing unrelated logic into a slice once 99% of the slices are
103
occupied through related logic packing.
Note that once logic distribution reaches the 99% level through
related logic packing, this does not mean the device is completely
utilized. Unrelated logic packing will then begin, continuing until
all usable LUTs and FFs are occupied. Depending on your timing
budget, increased levels of unrelated logic packing may adversely
affect the overall timing performance of your design.
Table of Contents
----------------Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts
Section 1 - Errors
-----------------Section 2 - Warnings
-------------------Section 3 - Informational
------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
Section 4 - Removed Logic Summary
--------------------------------2 block(s) optimized away
Section 5 - Removed Logic
------------------------Optimized Block(s):
TYPE
GND
VCC
BLOCK
XST_GND
XST_VCC
104
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
-------------------------+-----------------------------------------------------------------------------------------------------------------------+
| IOB Name
| Type | Direction | IO Standard | Drive | Slew | Reg (s) |
Resistor | IOB |
|
|
|
|
| Strength | Rate |
|
| Delay |
+-----------------------------------------------------------------------------------------------------------------------+
| Clock
| GCLKIOB | INPUT | LVTTL
|
| |
|
|
|
| CA_Bit
| IOB | OUTPUT | LVTTL
| 12
| SLOW |
|
|
|
| Delay<0>
| IOB | INPUT | LVTTL
|
| |
|
|
|
| Delay<1>
| IOB | INPUT | LVTTL
|
| |
|
|
|
| Delay<2>
| IOB | INPUT | LVTTL
|
| |
|
|
|
| Delay<3>
| IOB | INPUT | LVTTL
|
| |
|
|
|
| Delay<4>
| IOB | INPUT | LVTTL
|
| |
|
|
|
| Delay<5>
| IOB | INPUT | LVTTL
|
| |
|
|
|
| Reset
| IOB | INPUT | LVTTL
|
| |
|
|
|
+-----------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
---------------Section 8 - Guide Report
-----------------------Guide not run on this design.
Section 9 - Area Group Summary
-----------------------------No area groups were found in this design.
Section 10 - Modular Design Summary
----------------------------------Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
105
This design was not run using timing mode.
Section 12 - Configuration String Details
----------------------------------------Use the "-detail" map option to print out Configuration Strings
Section 13 - Additional Device Resource Counts
---------------------------------------------Number of JTAG Gates for IOBs = 9
Number of Equivalent Gates for Design = 1,335
Number of RPM Macros = 0
Number of Hard Macros = 0
PCI IOBs = 0
PCI LOGICs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DLLs = 0
GCLKIOBs = 1
GCLKs = 1
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 1
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 0
Unbonded IOBs = 0
Bonded IOBs = 8
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MULTANDs = 0
MUXF5s + MUXF6s = 31
4 input LUTs used as Route-Thrus = 3
4 input LUTs = 132
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 1
Slice Flip Flops = 42
Slices = 75
Number of LUT signals with 4 loads = 0
Number of LUT signals with 3 loads = 0
Number of LUT signals with 2 loads = 16
Number of LUT signals with 1 load = 106
NGM Average fanout of LUT = 1.98
NGM Maximum fanout of LUT = 20
106
NGM Average fanin for LUT = 3.4697
Number of LUT symbols = 132
Number of IPAD symbols = 8
Number of IBUF symbols = 7
End Appendix I
107
Appendix J
Table of costs for our prototype
TCXO
PLL
Passive components
Mixer
CPLD
PCB
Housing for the circuit
400
25
50
30
460
2500
1000
Total cost:
4465
Costs in Swedish Crowns
End Appendix J
108
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising