Audio Control | FOUR.1i | Specifications | Audio Control FOUR.1i Specifications

Audio Control FOUR.1i Specifications
 TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
FEATURES
1
• Four-Channel Audio DAC
– 102-dBA Signal-to-Noise Ratio
– 16/20/24/32-Bit Data
– Supports Rates From 8 kHz to 96 kHz
– 3D/Bass/Treble/EQ/De-Emphasis Effects
– Flexible Power Saving Modes and
Performance Are Available
• Four-Channel Audio ADC
– 92-dBA Signal-to-Noise Ratio
– Supports Rates From 8 kHz to 96 kHz
– Digital Signal Processing and Noise
Filtering Available During Record
• Twelve Audio Inputs
– Programmable in Single-Ended or Fully
Differential Configurations
– 3-State Capability for Floating Input
Configurations
• Fourteen Audio Output Drivers
– Stereo 8-Ω, 500-mW/Channel Speaker Drive
Capability
– Multiple Fully Differential or Single-Ended
Headphone Drivers
– Multiple Fully Differential or Single-Ended
Line Outputs
– Fully Differential Mono Outputs
• Low Power: 15-mW Stereo 48-kHz Playback
With 3.3-V Analog Supply
• Ultralow-Power Mode With Passive Analog
Bypass
• Programmable Input/Output Analog Gains
• Automatic Gain Control (AGC) for Record
• Programmable Microphone Bias Level
• Dual Programmable PLLs for Flexible Clock
Generation
• I2C Control Bus
• Dual Audio Serial Data Busses
– Support I2S, Left/Right-Justified, DSP, PCM,
and TDM Modes
– Enable Asynchronous Simultaneous
Operation of Busses and Data Converters
234
•
•
•
•
•
Digital Microphone Input Support
Concurrent Digital Microphone and Analog
Microphone Support Available
Extensive Modular Power Control
Power Supplies:
– Analog: 2.7 V–3.6 V
– Digital Core: 1.65 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
Package: 6-mm × 6-mm 87-BGA
APPLICATIONS
•
•
Digital Cameras
Smart Cellular Phones
DESCRIPTION
The TLV320AIC34 is a low-power four-channel audio
codec with four-channel headphone amplifier, as well
as multiple inputs and outputs programmable in
single-ended or fully differential configurations.
Extensive register-based power control is included,
enabling four-channel 48-kHz DAC playback as low
as 15 mW from a 3.3-V analog supply, making it ideal
for portable battery-powered audio and telephony
applications.
The record path of the TLV320AIC34 contains
integrated microphone bias, digitally controlled
four-channel microphone preamplifier, and automatic
gain control (AGC), with mix/mux capability among
the multiple analog inputs. Programmable filters are
available during record which can remove audible
noise that can occur during optical zooming in digital
cameras. The playback path includes mix/mux
capability from the four-channel DAC and selected
inputs, through programmable volume controls, to the
various outputs.
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The TLV320AIC34 contains eight high-power output drivers as well as six line-level output drivers. The
high-power output drivers are capable of driving a variety of load configurations, including up to eight channels of
single-ended 16-Ω headphones using ac-coupling capacitors, or four channels in a capless output configuration.
In addition, for codec A, pairs of drivers can be used to drive mono or stereo 8-Ω speakers directly in a BTL
configuration at 500 mW per channel.
The four-channel audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital
filtering in each path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz,
44.1-kHz, and 48-kHz rates. The four-channel audio ADC supports sampling rates from 8 kHz to 96 kHz and is
preceded by programmable gain amplifiers providing up to 59.5-dB analog gain for low-level microphone inputs.
The TLV320AIC34 provides an extremely high range of programmability for both attack (8–1,408 ms) and for
decay (0.05–22.4 seconds). This extended AGC range allows the AGC to be tuned for many types of
applications.
For battery saving applications where neither analog nor digital signal processing is required, the device can be
put in a special analog signal pass-through mode. This mode significantly reduces power consumption, as most
of the device is powered down during this pass through operation.
The serial control bus supports normal-speed and fast I2C protocols, whereas the dual serial audio data busses
are programmable for I2S, left/right-justified, DSP, PCM, or TDM mode. Two highly programmable PLLs are
included for flexible clock generation and support for all standard audio rates from a wide range of available
MCLK_x frequencies, varying from 512 kHz to 50 MHz, with special attention paid to the most popular cases of
12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.
The TLV320AIC34 operates from an analog supply of 2.7 V–3.6 V, a digital core supply of 1.65 V–1.95 V, and a
digital I/O supply of 1.1 V–3.6 V. The device is available in a 6-mm × 6-mm, 87-ball MicroStar Junior™ BGA
package.
2
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
AVDD_DAC
AVSS_DAC
DRVDD
DRVSS
AVSS_ADC
DVDD
DVSS
IOVDD
RESETB_A
GPIO1_A
GPIO2_A
ADDR_A
MICDET_A
MICBIAS_A
MCLK_A
DIN_A
DOUT_A
BCLK_A
WCLK_A
SCL
SDA
SIMPLIFIED BLOCK DIAGRAM
Voltage Supplies
Reset,
GPIO
Bias,
Detect
Audio Serial
Data Bus A
I C Serial
Control Bus
2
Block A Codec
HPLOUT_A
LINE2LP_A
LINE2LM_A
HPLCOM_A
MIC3L_A
LINE1LP_A
LINE1LM_A
LINE1RP_A
LINE1RM_A
PGA
0/+59.5dB
0.5dB steps
Mixing,
Muxing
MIC3R_A
Volume Ctl
and Effects
ADC
PGA
0/+59.5dB
0.5dB steps
Volume Ctl
and Effects
ADC
HPRCOM_A
DAC
Mixing,
Muxing,
Volume
Controls
DAC
HPROUT_A
MONO_LOP_A
MONO_LOM_A
LINE2RP_A
LINE2RM_A
LEFT_LOP_A
PLL
LEFT_LOM_A
RIGHT_LOP_A
RIGHT_LOM_A
Block B Codec
HPLOUT_B
HPLCOM_B
LINE2LP_B
LINE2LM_B
MIC3L_B
LINE1LP_B
LINE1LM_B
LINE1RP_B
LINE1RM_B
Mixing,
Muxing
MIC3R_B
PGA
0/+59.5dB
0.5dB steps
ADC
PGA
0/+59.5dB
0.5dB steps
ADC
Volume Ctl
and Effects
Volume Ctl
and Effects
HPRCOM_B
DAC
Mixing,
Muxing,
Volume
Controls
DAC
HPROUT_B
MONO_LOP_B
MONO_LOM_B
LINE2RP_B
LINE2RM_B
LEFT_LOP_B
PLL
LEFT_LOM_B
RIGHT_LOP_B
MCLK_B
DIN_B
DOUT_B
BCLK_B
WCLK_B
Reset, GPIO
RESETB_B
GPIO1_B
GPIO2_B
ADDR_B
Audio Serial
Data Bus A
MICDET_B
MICBIAS_B
RIGHT_LOM_B
Bias,
Detect
B0232-01
PACKAGING/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
OPERATING
TEMPERATURE
RANGE
TLV320AIC34
BGA-87
ZAS
–40°C to 85°C
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
TLV320AIC34IZAS
Trays, 490
TLV320AIC34IZASR
Tape and reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
TERMINAL ASSIGNMENTS
ZAS Package
(Top View)
A
B
C
D
E
F
G
H
J
K
L
1 2
3
4
5
6
7
8
9 10 11
P0061-01
Table 1. TERMINAL FUNCTIONS, ALPHABETIC
TERMINAL
NAME
BGA BALL
I/O
DESCRIPTION
ADDR_A
L7
I
I2C address control A
ADDR_B
L8
I
I2C address control B
AVDD_DAC
B3
–
Analog DAC voltage supply, 2.7 V–3.6 V
AVSS_ADC
D8
–
Analog ADC ground supply, 0 V
AVSS_DAC
D4, E4, F4,
G4
–
Analog DAC ground supply, 0 V
BCLK_A
K3
I/O
Audio serial data bus bit clock (input/output) A
BCLK_B
L2
I/O
Audio serial data bus bit clock (input/output) B
DIN_A
K5
I
Audio serial data bus data input (input) A
DIN_B
L4
I
Audio serial data bus data input (input) B
DOUT_A
K6
O
Audio serial data bus data output (output) A
DOUT_B
L5
O
Audio serial data bus data output (output) B
DRVDD
B4, A4
–
ADC analog and output driver voltage supply, 2.7 V–3.6 V
DRVDD
B9, A9
–
Analog ADC and output driver voltage supply, 2.7 V–3.6 V
DRVSS
D5, D6, D7
–
Analog output driver ground supply, 0 V
DVDD
K1
–
Digital core voltage supply, 1.65 V–1.95 V
DVSS
E8, F8, G8,
H4, H5, H6,
H8
–
Digital core / I/O ground supply, 0 V
GPIO1_A
J2
I/O
General-purpose input/output #1–A
GPIO1_B
J1
I/O
General-purpose input/output #1–B
GPIO2_A
H2
I/O
General-purpose input/output #2 (input/output) / digital microphone data input / PLL clock
input / audio serial data bus bit clock input/output–A
GPIO2_B
H1
I/O
General-purpose input/output #2 (input/output) / digital microphone data input / PLL clock
input / audio serial data bus bit clock input/output–B
HPLCOM_A
B7
O
High-power output driver (left minus or multifunctional) A, capable of driving 8-Ω load
HPLCOM_B
A7
O
High-power output driver (left minus or multifunctional) B
HPLOUT_A
B8
O
High-power output driver (left plus) A, capable of driving 8-Ω load
HPLOUT_B
A8
O
High-power output driver (left plus) B
HPRCOM_A
B6
O
High-power output driver (right minus or multifunctional) A, capable of driving 8-Ω load
4
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Table 1. TERMINAL FUNCTIONS, ALPHABETIC (continued)
TERMINAL
NAME
BGA BALL
I/O
DESCRIPTION
HPRCOM_B
A6
O
High-power output driver (right minus or multifunctional) B
HPROUT_A
B5
O
High-power output driver (right plus) A, capable of driving 8-Ω load
HPROUT_B
A5
O
High-power output driver (right plus) B
H7, K7
–
I/O voltage supply, 1.1 V–3.6 V
LEFT_LOM_A
D2
O
Left line output (minus) A
LEFT_LOM_B
D1
O
Left line output (minus) B
LEFT_LOP_A
C2
O
Left line output (plus) A
LEFT_LOP_B
C1
O
Left line output (plus) B
LINE1LM_A
L10
I
MIC1 or Line1 analog input (left minus or multifunction) A
LINE1LM_B
L11
I
MIC1 or Line1 analog input (left minus or multifunction) B
LINE1LP_A
K9
I
MIC1 or Line1 analog input (left plus or multifunction) A
LINE1LP_B
K8
I
MIC1 or Line1 analog input (left plus or multifunction) B
LINE1RM_A
J10
I
MIC1 or Line1 analog input (right minus or multifunction) A
LINE1RM_B
J11
I
MIC1 or Line1 analog input (right minus or multifunction) B
LINE1RP_A
K10
I
MIC1 or Line1 analog input (right plus or multifunction) A
LINE1RP_B
K11
I
MIC1 or Line1 analog input (right plus or multifunction) B
LINE2LM_A
G10
I
MIC2 or Line2 analog input (left minus or multifunction) A
LINE2LM_B
G11
I
MIC2 or Line2 analog input (left minus or multifunction) B
LINE2LP_A
H10
I
MIC2 or Line2 analog input (left plus or multifunction) A
LINE2LP_B
H11
I
MIC2 or Line2 analog input (left plus or multifunction) B
LINE2RM_A
E10
I
MIC2 or Line2 analog input (right minus or multifunction) A
LINE2RM_B
E11
I
MIC2 or Line2 analog input (right minus or multifunction) B
LINE2RP_A
F10
I
MIC2 or Line2 analog input (right plus or multifunction) A
LINE2RP_B
F11
I
MIC2 or Line2 analog input (right plus or multifunction) B
MCLK_A
K2
I
Master clock input A
MCLK_B
L1
I
Master clock input B
MIC3L_A
D10
I
MIC3 input (left or multifunction) A
MIC3L_B
D11
I
MIC3 input (left or multifunction) B
MIC3R_A
A10
I
Microphone or line input 3 right A
MIC3R_B
A11
I
Microphone or line input 3 right B
MICBIAS_A
B10
O
Microphone bias voltage output A
MICBIAS_B
B11
O
Microphone bias voltage output B
MICDET_A
C10
I
Microphone detect A
MICDET_B
C11
I
Microphone detect B
MONO_LOM_A
A2
O
Mono line output (minus) A
MONO_LOM_B
B1
O
Mono line output (minus) B
MONO_LOP_A
A3
O
Mono line output (plus) A
MONO_LOP_B
A1
O
Mono line output (plus) B
RESET_A
G2
I
Reset A
RESET_B
G1
I
Reset B
RIGHT_LOM_A
F2
O
Right line output (minus) A
RIGHT_LOM_B
F1
O
Right line output (minus) B
RIGHT_LOP_A
E2
O
Right line output (plus) A
RIGHT_LOP_B
E1
O
Right line output (plus) B
SCL
L9
I/O
I2C serial clock
SDA
L6
I/O
I2C serial data input/output
IOVDD
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Table 1. TERMINAL FUNCTIONS, ALPHABETIC (continued)
TERMINAL
NAME
BGA BALL
I/O
DESCRIPTION
WCLK_A
K4
I/O
Audio serial data bus word clock (input/output) A
WCLK_B
L3
I/O
Audio serial data bus word clock (input/output) B
Table 2. TERMINAL FUNCTIONS, NUMERIC
TERMINAL
BGA BALL
I/O
DESCRIPTION
A1
MONO_LOP_B
O
Mono line output (plus) B
A2
MONO_LOM_A
O
Mono line output (minus) A
A3
MONO_LOP_A
O
Mono line output (plus) A
A4
DRVDD
–
ADC analog and output driver voltage supply, 2.7 V–3.6 V
A5
HPROUT_B
O
High-power output driver (right plus) B
A6
HPRCOM_B
O
High-power output driver (right minus or multifunctional) B
A7
HPLCOM_B
O
High-power output driver (left minus or multifunctional) B
A8
HPLOUT_B
O
High-power output driver (left plus) B
A9
DRVDD
–
Analog ADC and output driver voltage supply, 2.7 V–3.6 V
A10
MIC3R_A
I
Microphone or line input 3 right A
A11
MIC3R_B
I
Microphone or line input 3 right B
B1
MONO_LOM_B
O
Mono line output (minus) B
B3
AVDD_DAC
–
Analog DAC voltage supply, 2.7 V–3.6 V
B4
DRVDD
–
ADC analog and output driver voltage supply, 2.7 V–3.6 V
B5
HPROUT_A
O
High-power output driver (right plus) A, capable of driving 8-Ω load
B6
HPRCOM_A
O
High-power output driver (right minus or multifunctional) A, capable of driving 8-Ω load
B7
HPLCOM_A
O
High-power output driver (left minus or multifunctional) A, capable of driving 8-Ω load
B8
HPLOUT_A
O
High-power output driver (left plus) A, capable of driving 8-Ω load
B9
DRVDD
–
Analog ADC and output driver voltage supply, 2.7 V–3.6 V
B10
MICBIAS_A
O
Microphone bias voltage output A
B11
MICBIAS_B
O
Microphone bias voltage output B
C1
LEFT_LOP_B
O
Left line output (plus) B
C2
LEFT_LOP_A
O
Left line output (plus) A
C10
MICDET_A
I
Microphone detect A
C11
MICDET_B
I
Microphone detect B
D1
LEFT_LOM_B
O
Left line output (minus) B
D2
LEFT_LOM_A
O
Left line output (minus) A
D4
AVSS_DAC
–
Analog DAC ground supply, 0 V
D5, D6, D7
6
NAME
DRVSS
–
Analog output driver ground supply, 0 V
D8
AVSS_ADC
–
Analog ADC ground supply, 0 V
D10
MIC3L_A
I
MIC3 input (left or multifunction) A
D11
MIC3L_B
I
MIC3 input (left or multifunction) B
E1
RIGHT_LOP_B
O
Right line output (plus) B
E2
RIGHT_LOP_A
O
Right line output (plus) A
E4
AVSS_DAC
–
Analog DAC ground supply, 0 V
E8
DVSS
–
Digital core / I/O ground supply, 0 V
E10
LINE2RM_A
I
MIC2 or Line2 analog input (right minus or multifunction) A
E11
LINE2RM_B
I
MIC2 or Line2 analog input (right minus or multifunction) B
F1
RIGHT_LOM_B
O
Right line output (minus) B
F2
RIGHT_LOM_A
O
Right line output (minus) A
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Table 2. TERMINAL FUNCTIONS, NUMERIC (continued)
TERMINAL
BGA BALL
NAME
I/O
DESCRIPTION
F4
AVSS_DAC
–
Analog DAC ground supply, 0 V
F8
DVSS
–
Digital core / I/O ground supply, 0 V
F10
LINE2RP_A
I
MIC2 or Line2 analog input (right plus or multifunction) A
F11
LINE2RP_B
I
MIC2 or Line2 analog input (right plus or multifunction) B
G1
RESET_B
I
Reset B
G2
RESET_A
I
Reset A
G4
AVSS_DAC
–
Analog DAC ground supply, 0 V
G8
DVSS
–
Digital core / I/O ground supply, 0 V
G10
LINE2LM_A
I
MIC2 or Line2 analog input (left minus or multifunction) A
G11
LINE2LM_B
I
MIC2 or Line2 analog input (left minus or multifunction) B
H1
GPIO2_B
I/O
General-purpose input/output #2 (input/output) / digital microphone data input / PLL clock
input / audio serial data bus bit clock input/output–B
H2
GPIO2_A
I/O
General-purpose input/output #2 (input/output) / digital microphone data input / PLL clock
input / audio serial data bus bit clock input/output–A
H4, H5, H6
DVSS
–
Digital core / I/O ground supply, 0 V
H7
IOVDD
–
I/O voltage supply, 1.1 V–3.6 V
H8
DVSS
–
Digital core / I/O ground supply, 0 V
H10
LINE2LP_A
I
MIC2 or Line2 analog input (left plus or multifunction) A
H11
LINE2LP_B
I
MIC2 or Line2 analog input (left plus or multifunction) B
J1
GPIO1_B
I/O
General-purpose input/output #1–B
J2
GPIO1_A
I/O
General-purpose input/output #1–A
J10
LINE1RM_A
J11
K1
I
MIC1 or Line1 analog input (right minus or multifunction) A
LINE1RM_B
I
MIC1 or Line1 analog input (right minus or multifunction) B
DVDD
–
Digital core voltage supply, 1.65 V–1.95 V
K2
MCLK_A
I
Master clock input A
K3
BCLK_A
I/O
Audio serial data bus bit clock (input/output) A
K4
WCLK_A
I/O
Audio serial data bus word clock (input/output) A
K5
DIN_A
I
Audio serial data bus data input (input) A
K6
DOUT_A
O
Audio serial data bus data output (output) A
K7
IOVDD
–
I/O voltage supply, 1.1 V–3.6 V
K8
LINE1LP_B
I
MIC1 or Line1 analog input (left plus or multifunction) B
K9
LINE1LP_A
I
MIC1 or Line1 analog input (left plus or multifunction) A
K10
LINE1RP_A
I
MIC1 or Line1 analog input (right plus or multifunction) A
K11
LINE1RP_B
I
MIC1 or Line1 analog input (right plus or multifunction) B
L1
MCLK_B
I
Master clock input B
L2
BCLK_B
I/O
Audio serial data bus bit clock (input/output) B
L3
WCLK_B
I/O
Audio serial data bus word clock (input/output) B
L4
DIN_B
I
Audio serial data bus data input (input) B
L5
DOUT_B
O
Audio serial data bus data output (output) B
L6
SDA
I/O
I2C serial data input/output
L7
ADDR_A
I
I2C address control A
L8
ADDR_B
I
I2C address control B
L9
SCL
L10
LINE1LM_A
I
MIC1 or Line1 analog input (left minus or multifunction) A
L11
LINE1LM_B
I
MIC1 or Line1 analog input (left minus or multifunction) B
I/O
I2C serial clock
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
VALUE
UNIT
DRVDD to AVSS_ADC, AVDD_DAC to AVSS_DAC
–0.3 to 3.9
V
DRVDD to DRVSS
–0.3 to 3.9
V
IOVDD to DVSS
–0.3 to 3.9
V
DVDD to DVSS
–0.3 to 2.5
V
AVDD_DAC to DRVDD
–0.1 to 0.1
V
–0.3 to IOVDD + 0.3
V
Digital input voltage to DVSS
Analog input voltage to AVSS_ADC, AVSS_DAC
–0.3 to AVDD_DAC + 0.3
V
TA
Operating temperature range
–40 to 85
°C
Tstg
Storage temperature range
–65 to 105
°C
TJ Max
Junction temperature
105
°C
Power dissipation
θJA
Thermal impedance
Lead temperature
(1)
(2)
(TJ Max – TA)/θJA
Maximum reflow temperature, 60 s
47
°C/W
260
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ESD complicance tested to EIA/JESD22-A114-B and passed.
DISSIPATION RATINGS (1)
(1)
PACKAGE TYPE
TA = 25°C
POWER RATING
DERATING
FACTOR
TA = 75°C
POWER RATING
TA = 85°C
POWER RATING
BGA
1.7 W
21.3 mW/°C
636 mW
423 mW
This data is based on using a JEDEC standard four-layer 3-in. × 3-in. (7.62-mm × 7.62-mm) PCB with 2-oz. (0.071-mm thick) trace and
copper pad that is soldered directly to the device.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
AVDD_DAC, DRVDD
(1)
Analog supply voltage
DVDD (1)
Digital core supply voltage
IOVDD (1)
Digital I/O supply voltage
AVDD_DAC
Analog full-scale 0-dB input voltage (DRVDD = 3.3 V)
MIN
NOM
2.7
3.3
3.6
V
1.65
1.8
1.95
V
1.1
1.8
3.6
0.707
8
V
VRMS
10
kΩ
Stereo headphone output load resistance (codec block A and codec
block B)
16
Ω
Operating free-air temperature
Ω
8
Digital output load capacitance
(1)
UNIT
Stereo line output load resistance (codec block A and codec block B)
Stereo speaker output load resistance (codec block A ONLY)
TA
MAX
10
–40
pF
85
°C
Analog voltage values are with respect to AVSS_ADC, AVSS_DAC, DRVSS; digital voltage values are with respect to DVSS.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS
At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC,
Codec Block A, B
Input signal level (0-dB)
SNR
Signal-to-noise ratio
Dynamic range
(1) (2)
(2)
THD
Total harmonic distortion
PSRR
Power supply rejection ratio
Single-ended input
fS = 48 ksps, 0-dB PGA gain, LINE1LP_x and LINE1LM_x
inputs ac-shorted to ground, A-weighted
0.707
80
VRMS
92
dB
fS = 48 ksps, 0-dB PGA gain, –60-dB full-scale input signal
applied at LINE1LP_x and LINE1LM_x inputs, A-weighted
93
dB
fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input
signal applied at LINE1LP_x and LINE1LM_x inputs
–87
217-Hz signal applied to DRVDD
49
1-kHz signal applied to DRVDD
46
–70
dB
dB
fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input
signal applied on LINE1LP_x and LINE1LM_x inputs
0.55
1-kHz, –2-dB full-scale signal, MIC3L_x to MIC3R_x
–86
1-kHz, –2-dB full-scale signal, MIC2LP_x and MIC2LM_x to
MIC2RP_x and MIC2RM_x
–98
1-kHz, –2-dB full-scale signal, MIC1LP_x and MIC1LM_x to
MIC1RP_x and MIC1RM_x
–80
ADC programmable-gain
amplifier maximum gain
1-kHz input frequency, RSOURCE < 50 Ω
59.5
dB
ADC programmable-gain
amplifier step size
1-kHz input frequency, RSOURCE < 50 Ω
0.5
dB
LINE1LP_x, LINE1LM_x, or LINE1RP_x, LINE1RM_x inputs
routed to single ADC;
input mix attenuation = 0 dB
20
LINE1LP_x, LINE1LM_x, or LINE1RP_x, LINE1RM_x inputs
routed to single ADC; input mix attenuation = 12 dB
80
LINE2LP_x, LINE2LM_x, or LINE2RP_x, LINE2RM_x inputs
routed to single ADC;
input mix attenuation = 0 dB
20
LINE2LP_x, LINE2LM_x, or LINE2RP_x, LINE2RM_x inputs
routed to single ADC; input mix attenuation = 12 dB
80
MIC3L_x or MIC3R_x inputs routed to single ADC,
input mix attenuation = 0 dB
20
MIC3L_x or MIC3R_x inputs routed to single ADC, input mix
attenuation = 12 dB
80
Gain error
Input channel separation
Input resistance
dB
dB
kΩ
Input level control minimum
attenuation setting
0
dB
Input level control maximum
attenuation setting
12
dB
Input signal level
Differential input
(1) (2)
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
1.414
VRMS
fS = 48 ksps, 0-dB PGA gain, inputs ac-shorted to ground,
differential mode, A-weighted
92
dB
fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input
signal, differential mode, A-weighted
–89
dB
MIC1/LINE1 to LINE_OUT
330
MIC2/LINE2 to LINE_OUT
330
ANALOG PASS-THROUGH MODE,
Codec Block A, B
rds(on)
(1)
(2)
Input-to-output switch resistance
Ω
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic-range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC DIGITAL DECIMATION FILTER, fS = 48 kHz,
Codec Block A, B
Filter gain from 0 to 0.39 fS
Filter gain at 0.4125 fS
Filter gain at 0.45 fS
Filter gain at 0.5 fS
Filter gain from 0.55 fS to 64 fS
Filter group delay
±0.1
dB
–0.25
dB
–3
dB
–17.5
dB
–75
dB
17/fS
s
MICROPHONE BIAS,
Codec Block A, B
Programmable setting = 2 V, load current = 4 mA
Bias voltage
Current sourcing
Programmable setting = 2.5 V, load current = 4 mA
2
2.3
2.4
Programmable setting = DRVDD (3.3 V), load current = 4 mA
3
Programmable setting = 2.5 V
4
2.7
V
mA
AUDIO DAC – DIFFERENTIAL LINE OUTPUT, Load = 10 kΩ,
Codec Block A, B
Full-scale output voltage
0-dB input full-scale signal, output volume control = 0 dB,
output common-mode setting = 1.35 V
Signal-to-noise ratio (3)
No input signal, output volume control = 0 dB, output
common-mode setting = 1.35 V, fS = 48 kHz, A-weighted
Dynamic range
THD
Total harmonic distortion
PSRR
Power-supply rejection ratio
SNR
1.414
90
VRMS
99
dB
–60 dB, 1-kHz input full-scale signal, output volume control =
0 dB, output common-mode setting = 1.35 V, fS = 48 kHz,
A-weighted
95
dB
0-dB, 1-kHz input full-scale signal, output volume control = 0
dB, output common-mode setting = 1.35 V, fS = 48 kHz
–88
217-Hz signal applied to AVDD_DAC
77
1-kHz signal applied to AVDD_DAC
73
DAC channel separation
0-dB full-scale input signal between left and right lineout
DAC gain error
0-dB, 1-kHz input full-scale signal, output volume control =
0 dB, output common-mode setting = 1.35 V, fS = 48 kHz
–75
dB
dB
123
dB
–0.49
dB
Vrms
AUDIO DAC – SINGLE-ENDED LINE OUTPUT, Load = 10 kΩ,
Codec Block A, B
Full-scale output voltage
0-dB input full-scale signal, output volume control = 0 dB,
output common-mode setting = 1.35 V
0.707
SNR
Signal-to-noise ratio
No input signal, output volume control = 0 dB, output
common-mode setting = 1.35 V, fS = 48 kHz, A-weighted
94
dB
THD
Total harmonic distortion
0-dB, 1-kHz input full-scale signal, output volume control =
0 dB, output common-mode setting = 1.35 V, fS = 48 kHz
79
dB
DAC gain error
0-dB, 1-kHz input full-scale signal, output volume control =
0 dB, output common-mode setting = 1.35 V, fS = 48 kHz
–0.5
dB
(3)
10
Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω
single-ended load.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO DAC – SINGLE-ENDED HEADPHONE OUTPUT, Load = 16 Ω,
Codec Block A, B
0-dB input full-scale signal, output volume control = 0 dB,
output common-mode setting = 1.35 V
0.707
No input signal, output volume control = 0 dB, output
common-mode setting = 1.35 V, fS = 48 kHz, A-weighted
93
dB
No input signal, output volume control = 0 dB, output
common-mode setting = 1.35 V, fS = 48 kHz, 50% DAC
current boost, A-weighted
94
dB
Dynamic range
–60 dB, 1-kHz input full-scale signal, output volume control =
0 dB, output common-mode setting = 1.35 V, fS = 48 kHz,
A-weighted
89
dB
THD
Total harmonic distortion
0-dB, 1-kHz input full-scale signal, output volume control =
0 dB, output common-mode setting = 1.35 V, fS = 48 kHz
PSRR
Power-supply rejection ratio
Full-scale output voltage
SNR
Signal-to-noise ratio
–74
Vrms
–65
dB
217-Hz signal applied to DRVDD, AVDD_DAC
41
1-kHz signal applied to DRVDD, AVDD_DAC
44
DAC channel separation
0-dB full-scale input signal between left and right headphone
out
84
dB
DAC gain error
0-dB, 1-kHz input full-scale signal, output volume control =
0 dB, output common-mode setting = 1.35 V, fS = 48 kHz
–0.8
dB
dB
AUDIO DAC – LINEOUT AND HEADPHONE OUT DRIVERS,
Codec Block A, B
First option
Output common mode
1.35
Second option
1.5
Third option
V
1.65
Fourth option
1.8
Output volume-control maximum
setting
9
dB
Output volume-control step size
1
dB
AUDIO DAC – DIFFERENTIAL SPEAKER OUTPUT, RLOAD = 8 Ω, 1 kHz Input Signal,
Codec Block A ONLY
Full-scale output voltage, codec
block A only
0-dB input full-scale signal, output common-mode setting =
1.35 V, output volume control = 0 dB
SNR
Signal-to-noise ratio, codec
block A only
A-weighted, fS = 48 kHz, output volume control = 0 dB, no
input signal, output common-mode setting = 1.35 V
THD
Total harmonic distortion, codec
block A only
DAC gain error, codec block A
only
1.414
VRMS
96
dB
fS = 48 kHz, 1-kHz input full-scale signal, output volume
control = 0 dB, output common-mode setting = 1.35 V
–67
dB
fS = 48 kHz, 1-kHz input full-scale signal, output volume
control = 0 dB, output common-mode setting = 1.35 V
–2
dB
DAC DIGITAL INTERPOLATION – FILTER fS = 48-ksps
Codec Block A, B
Pass band
0
Pass-band ripple
0.45 fS
±0.06
Hz
dB
Transition band
0.45 fS
0.55 fS
Hz
Stop band
0.55 fS
7.5 fS
Hz
Stop-band attenuation
65
Group delay
dB
21/fS
s
DIGITAL I/O
Codec Block A, B
VIL
Input low level
VIH
Input high level (4)
VOL
Output low level
VOH
Output high level
(4)
–0.3
IOVDD > 1.6 V
0.7 IOVDD
IOVDD < 1.6 V
1.1
0.3 IOVDD
V
V
0.1 IOVDD
0.8 IOVDD
V
V
When IOVDD < 1.6 V, minimum VIH is 1.1 V.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V
Currents Listed are for Codec Block A or Block B.
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IIN
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
IDRVDD + IAVDD_DAC
IDVDD
12
1.19
RESET_x pulse applied, no external clocks
0.75
Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal,
PLL off
2.06
Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal,
PLL off
4.06
Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no
signal, PLL off
4.27
Stereo DAC playback to lineout, analog mixer bypassed, fS =
48 ksps, I2S slave, no signal, PLL off
0.55
0.67
2.45
3.5
2.3
Stereo DAC playback to Lineout, fS = 48 ksps, I S slave, no
signal, PLL off
4.42
Stereo DAC playback to stereo single-ended headphones, fS
= 48 ksps, I2S slave, no signal, PLL off
7.78
2
Stereo linein to stereo lineout, no signal
Extra power when PLL enabled
All blocks powered down, headset detection enabled
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µA
mA
2.27
2.26
3.16
1.79
1.2
1
5.3
188
µA
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS (FOR A AND B INTERFACES)
All specifications at 25°C, DVDD = 1.8 V
WCLK_x
td(WS)
BCLK_x
td(DO-WS)
td(DO-BCLK)
DOUT_x
tS(DI)
th(DI)
DIN_x
T0145-04
PARAMETER
IOVDD = 1.1 V
MIN
MAX
IOVDD = 3.3 V
MIN
MAX
UNIT
td(WS)
ADWS/WCLK_x delay time
50
15
ns
td(DO-WS)
ADWS/WCLK_x to DOUT_x delay time
50
20
ns
td(DO-BCLK)
BCLK_x to DOUT_x delay time
15
ns
ts(DI)
DIN_x setup time
10
6
ns
th(DI)
DIN_x hold time
10
6
ns
tr
Rise time
30
10
ns
tf
Fall time
30
10
ns
50
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 1. I2S/LJF/RJF Timing in Master Mode
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
All specifications at 25°C, DVDD = 1.8 V
WCLK_x
td(WS)
td(WS)
BCLK_x
td(DO-BCLK)
DOUT_x
tS(DI)
th(DI)
DIN_x
T0146-03
PARAMETER
IOVDD = 1.1 V
MIN
MAX
IOVDD = 3.3 V
MIN
MAX
UNIT
td(WS)
ADWS/WCLK_x delay time
50
15
ns
td(DO-BCLK)
BCLK_x to DOUT_x delay time
50
15
ns
ts(DI)
DIN_x setup time
10
6
ns
th(DI)
DIN_x hold time
10
6
ns
tr
Rise time
30
10
ns
tf
Fall time
30
10
ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 2. DSP Timing in Master Mode
14
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
All specifications at 25°C, DVDD = 1.8 V
WCLK_x
tS(WS)
th(WS)
tH(BCLK)
BCLK_x
td(DO-WS)
tL(BCLK)
td(DO-BCLK)
DOUT_x
tS(DI)
th(DI)
DIN_x
T0145-05
PARAMETER
IOVDD = 1.1 V
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK_x high period
70
35
ns
tL(BCLK)
BCLK_x low period
70
35
ns
ts(WS)
ADWS/WCLK_x setup time
10
6
ns
th(WS)
ADWS/WCLK_x hold time
10
6
td(DO-WS)
ADWS/WCLK_x to DOUT_x delay time (for LJF mode only)
50
20
ns
td(DO-BCLK)
BCLK_x to DOUT_x delay time
50
20
ns
ts(DI)
DIN_x setup time
10
6
th(DI)
DIN_x hold time
10
6
tr
Rise time
8
4
ns
tf
Fall time
8
4
ns
ns
ns
ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 3. I2S/LJF/RJF Timing in Slave Mode
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
All specifications at 25°C, DVDD = 1.8 V
WCLK_x
tS(WS)
tS(WS)
th(WS)
th(WS)
tL(BCLK)
BCLK_x
td(DO-BCLK)
tH(BCLK)
DOUT_x
tS(DI)
th(DI)
DIN_x
T0146-04
PARAMETER
IOVDD = 1.1 V
MIN
IOVDD = 3.3 V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK_x high period
70
35
ns
tL(BCLK)
BCLK_x low period
70
35
ns
ts(WS)
ADWS/WCLK_x setup time
10
6
ns
th(WS)
ADWS/WCLK_x hold time
10
6
td(DO-BCLK)
BCLK_x to DOUT_x delay time
ts(DI)
DIN_x setup time
10
6
th(DI)
DIN_x hold time
10
6
tr
Rise time
8
4
ns
tf
Fall time
8
4
ns
50
ns
20
ns
ns
ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 4. DSP Timing in Slave Mode
16
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
HEADPHONE OUT POWER
SIGNAL-TO-NOISE RATIO
vs
ADC PGA SETTING
45
0
2.7 VDD_CM 1.35_LDAC
40
3.6 VDD_CM 1.8_LDAC
-20
SNR - Signal-To-Noise - dB
THD - Total Harmonic Distortion - dB
-10
3.3 VDD_CM1.65_LDAC
2.7 VDD_CM 1.35_RDAC
-30
-40
3.3 VDD_CM 1.65_RDAC
-50
-60
-70
35
30
25
20
15
10
-80
LINEIR Routed to RADC in Differential Mode,
48 KSPS, Normal Supply and Temperature,
Input Signal at -65 dB
5
3.6 VDD_CM 1.8_RDAC
0
-90
0
20
40
60
80
0
100
10
Headphone Out Power - mW
30
40
50
Figure 5.
ADC, PGA - Setting - dB
Figure 6.
MICBIAS_x VOLTAGE
vs
SUPPLY VOLTAGE
MICBIAS_x VOLTAGE
vs
FREE-AIR TEMPERATURE
60
70
4
4
AVDD = 3.3 V,
No Load
No Load
3.5
3.5
PGM = VDD
MICBIAS VOLTAGE - V
MICBIAS VOLTAGE - V
20
3
PGM = 2.5 V
2.5
PGM = VDD
3
PGM = 2.5 V
2.5
PGM = 2 V
PGM = 2 V
2
1.5
2.7
2
2.9
3.1
3.3
3.5
1.5
-60
-40
VDD - Supply Voltage - V
Figure 7.
-20
0
20
40
60
TA - Free- Air Temperature - °C
80
100
Figure 8.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
LEFT-DAC FFT
0
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
4096 Samples,
AVDD = DRVDD = 3.3 V,
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
-160
0
1
2
3
4
5
6
7
8
9 10 11 12
f - Frequency - kHz
13
14
15 16
17 18
19 20
Figure 9.
RIGHT-DAC FFT
0
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
AVDD = DRVDD = 3.3 V,
-20
Amplitude - dB
-40
-60
-80
-100
-120
-140
-160
0
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15 16
17 18
19
20
f - Frequency - kHz
Figure 10.
LEFT-ADC FFT
0
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
2048 Samples,
AVDD = DRVDD = 3.3 V,
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
-160
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14 15
16
17 18 19
20
f - Frequency - kHz
Figure 11.
18
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
RIGHT-ADC FFT
0
Load = 10 kW,
FS = 48 kHz, fs = 64 kHz,
2048 Samples,
AVDD = DRVDD = 3.3 V,
Amplitude - dB
-20
-40
-60
-80
-100
-120
-140
-160
0
1
2
3
4
5
6
7
8
9 10 11 12 13
f - Frequency - kHz
Figure 12.
14
15
16 17
18
19
20
TYPICAL SYSTEM CONFIGURATION
Downlink Path
Bluetooth
Module
Analog Baseband
Module
Differential
Input
PCM
Differential
Output
Applications/Multimedia
Processor
2
2
I S
I C
Uplink Path
Application Audio
2
I S
S
FM/
Line In
DAC
DAC
ADC
ADC
ADC
S
AIC34
Codec B
8W
8W
AIC34
Codec A
Headphone
MIC
Stereo
Amplifier
DAC
MIC
Differential
Output
Headset
B0272-01
Figure 13. Bluetooth Call Recording Plus Application Audio Block Diagram
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TYPICAL CHARACTERISTICS (continued)
IOVDD
Applications/Multimedia
Processor
Rp
Rp
2
ADDR_A
DIN_A
DOUT_A
BCLK_A
MCLK_A
WCLK_A
SCL
SDA
RESET_A
I C ADDRESS
SELECT
0.47 mF
LINE1LP_A
LINE1LM_A
FM/
Line In
AVDD
AVDD_ADC
AVDD_DAC
DRVDD
DRVDD
DRVDD
DRVDD
LINE1RP_A
LINE1RM_A
0.1 mF
1 mF
From
Codec
Block B
LINE2LP_A
LINE2LM_A
LEFT_LOP_B
LEFT_LOM_B
AIC34
Codec Block A
0.1 mF
0.1 mF
0.1 mF
1 mF
1 mF
10 mF 0.1 mF
1 mF
0.1 mF
1 mF
1 mF
A
IOVDD
IOVDD
DVDD
To
Codec
Block B
1 mF
0.1 mF
DVDD
MONO_LOP_A
MONO_LOM_A
MONO_LOP_A
MONO_LOM_A
0.1 mF
1 mF
DVSS
D
LEFT_LOP_A
LEFT_LOM_A
RIGHT_LOM_A
RIGHT_LOP_A
HPRCOM_A
HPLCOM_A
HPROUT_A
2 kW
HPLOUT_A
MICDET_A
Headset Mic With
Headset Speakers
MIC3R_A
MICBIAS_A
AVSS_ADC
AVSS_DAC
AVSS_DAC
DRVSS
DRVSS
DRVSS
A
VBAT
560 W
1 mF
560 W
PVDD
560 W
HEADSET MIC
HEADSET SPKR_R
A
0.47 mF
47 mF
HEADSET SPKR_L
560 W
47 mF
4700pF
HEADSET GND
A
4700pF
PVSS
A
TPA2012D2 Class-D
Spkr Amp
MONO
Speaker
S0316-01
Figure 14. Typical Connections for TLV320AIC34 in Bluetooth Application (Sheet 1 of 2)
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TYPICAL CHARACTERISTICS (continued)
Applications/Multimedia
Processor
Bluetooth
Module
(Mono)
2
ADDR_B
MCLK_B
WCLK_B
BCLK_B
DIN_B
DOUT_B
RESET_B
I C ADDRESS
SELECT
0.47 mF
MONO_LOP_B
MONO_LOM_B
LINE2RP_B
LINE2RM_B
Analog
Baseband/
Modem
AIC34
Codec Block B
From
Codec
Block A
MONO_LOP_A
MONO_LOM_A
LINE2LP_B
LINE2LM_B
MICBIAS_B
LEFT_LOP_B
2 kW
MICDET_B
Microphone
LEFT_LOM_B
LEFT_LOP_B
LEFT_LOM_B
To
Codec
Block A
0.47 mF
MIC3L_B
S0317-01
Figure 15. Typical Connections for TLV320AIC34 in Bluetooth Application (Sheet 2 of 2)
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OVERVIEW
The TLV320AIC34 is a highly flexible, low-power, four-channel audio codec with extensive feature integration,
intended for applications in smart phones, portable computing, communication, and entertainment applications.
Available in a 6-mm × 6-mm, 87-ball BGA, the device integrates a host of features to reduce cost, board space,
and power consumption in space-constrained, battery-powered, portable applications.
The TLV320AIC34 consists of the following blocks:
• Four-channel audio multibit delta-sigma DAC (8 kHz–96 kHz)
• Four-channel audio multibit delta-sigma ADC (8 kHz–96 kHz)
• Dedicated programmable-gain amplifier at each ADC input, with independently configurable hardware
automatic gain control on all channels
• Programmable digital audio effects processing for record (wind noise, microphone EQ, resonance noise
removal)
• Programmable digital audio effects processing for playback (3-D, bass, treble, midrange, EQ, de-emphasis)
• Twelve audio inputs configurable for up to eight fully differential inputs or up to twelve single-ended inputs
• Eight high-power audio output drivers (headphone, and speaker drive capability for codec block A)
• Six line output drivers with fully differential or single-ended outputs
• Dual fully programmable PLLs
• Dual audio serial data busses support I2S, left/right-justified, DSP, PCM, and TDM operation
• Support for simultaneous, fully asynchronous operation of data converters using both serial busses
• Headphone/headset jack detection with interrupt
Control communication with the TLV320AIC34 is accomplished using the I2C interface, which supports both
standard and fast communication modes.
HARDWARE RESET
The TLV320AIC34 requires a hardware reset after power up for proper operation. After all power supplies are at
their specified values, the RESET_A and RESET_B terminals must be driven low for at least 10 ns. If this reset
sequence is not performed, the device may not respond properly to register reads/writes. It is recommended that
the two RESET_x terminals be shorted and controlled together.
DIGITAL CONTROL SERIAL INTERFACE
The TLV320AIC34 is entirely controlled by registers, with a register map that is software compatible with the
low-power stereo audio codecs TLV320AIC31/32/33 and TLV320AIC3101/4/5/6. In order to maintain best
software compatibility with stereo codecs, the register configuration of the four-channel TLV320AIC34 is divided
into two separate I2C slave devices containing separate addresses, with each address used to access registers
controlling two channels of codec and associated inputs and outputs. The two partitions of the device are
denoted A and B, with analog and digital inputs, outputs, and internal blocks named accordingly, ending in _A or
_B. The two I2C addresses are also denoted A and B, with each used to control the correspondingly named
signals and internal blocks.
Within each I2C address, the register map consists of multiple pages of registers, with each page containing up
to 128 registers. The register at address zero on each page is used as a page control register, and writing to this
register determines the active page for the device. All subsequent read/write operations access the page that is
active at the time, unless a register write is performed to change the active page. Only two pages of registers
(zero and one) are implemented in this product, with the active page defaulting to page 0 on device reset.
For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for
addresses 1 to 127 access registers in page 0. If registers on page 1 must be accessed, the user must write the
8-bit value 0x01 to register 0, the page control register, to change the active page from page 0 to page 1. After
this write, it is recommended that the user also read back the page control register to ensure the change in page
control has occurred properly. Future read/write operations to addresses 1 to 127 now access registers in
page 1. When page-0 registers must be accessed again, the user writes the 8-bit value 0x00 to register 0, the
page control register, to change the active page back to page 0. After a recommended read of the page control
register, all further read/write operations to addresses 1 to 127 again access page-0 registers.
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I2C CONTROL MODE
The TLV320AIC34 supports the I2C control protocol using 7-bit addressing and capable of both standard and fast
modes. For I2C fast mode, note that the minimum timing for each of tHD-STA, tSU-STA, and tSU-STO is 0.9 µs, as seen
in Figure 16. The TLV320AIC34 uses two I2C addresses, with the A channels controlled through one device
address, and the B channels controlled using a different device address. These addresses can be modified
through use of the ADDR_A and ADDR_B terminals, as described in the following table.
A I2C address
ADDR_A = 1
ADDR_A = 0
001 1010
001 1000
B I2C address
ADDR_B = 1
ADDR_B = 0
001 1011
001 1001
SDA
tHD-STA ³ 0.9 ms
SCL
tSU-STA ³ 0.9 ms
tSU-STO ³ 0.9 ms
tHD-STA ³ 0.9 ms
S
Sr
P
S
T0114-02
2
Figure 16. I C Fast-Mode Timing Requirements
This capability to modify the I2C addresses allows two TLV320AIC34 codecs to be used on a single I2C control
bus, providing individual control of each codec. This provides up to eight channels of audio codec controlled from
a single host processor I2C peripheral.
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the TLV320AIC34 can only act as a slave
device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted
across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate
level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA
line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receiver
shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. The
master always drives the clock line. The TLV320AIC34 never drives SCL, because it cannot act as a master. On
the TLV320AIC34, SCL is an input only when configured as an I2C terminal.
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Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start a communication. They do this by
causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock
line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its
counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from
HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that indicates which slave device it wants to
communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master
sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to
the slave device. The TLV320AIC34 supporst only 7-bit slave addresses.
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW
to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (Remember that the master always
drives the clock line.)
A not-acknowledge is performed simply by leaving SDA HIGH during an acknowledge cycle. If a device is not
present on the bus and the master attempts to address it, it receives a not−acknowledge because no device is
present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
Both A and B partitions of the TLV320AIC34 respond to and acknowledge a general call, which consists of the
master issuing a command with a slave address byte of 00h. It is not recommended to access the device using a
general call, because it is unclear which sets of registers are meant to be addressed, and results may not be
correct.
SCL
DA(6)
SDA
DA(0)
7-Bit Device Address
(M)
Start
(M)
RA(7)
Write
(M)
RA(0)
8-Bit Register Address
(M)
Slave
Ack
(S)
D(7)
D(0)
8-Bit Register data
(M)
Slave
Ack
(S)
Slave
Ack
(S)
Stop
(M)
(M) – SDA Controlled by Master
(S) – SDA Controlled by Slave
T0147-01
2
Figure 17. I C Write
SCL
DA(6)
SDA
Start
(M)
DA(0)
7-Bit Device Address
(M)
RA(7)
Write
(M)
Slave
Ack
(S)
DA(6)
RA(0)
8-Bit Register Address
(M)
Slave
Ack
(S)
Repeat
Start
(M)
DA(0)
7-Bit Device Address
(M)
D(7)
Read
(M)
Slave
Ack
(S)
D(0)
8-Bit Register Data
(S)
Master
No Ack
(M)
Stop
(M)
(M) – SDA Controlled by Master
(S) – SDA Controlled by Slave
T0148-01
2
Figure 18. I C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental
register.
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Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of the SDA bus and transmits for
the next 8 clocks the data of the next incremental register. Note that incremental read/write operation does not
continue past a page boundary. The user should not attempt to read/write past the end of a page, because this
may result in undesirable operation.
I2C BUS DEBUG IN A GLITCHED SYSTEM
Occasionally, some systems may encounter noise or glitches on the I2C bus. In the unlikely event that this
affects bus performance, then it can be useful to use the I2C debug register. This feature terminates the I2C bus
error, allowing this I2C device and system to resume communications. The I2C bus error detector is enabled by
default. The TLV320AIC34 I2C error detector status can be read from page 0, register 107, bit D0. If desired, the
detector can be disabled by writing to page 0, register 107, bit D2.
DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between host processor(s) and the TLV320AIC34 via the two digital audio data serial
interfaces. The two data serial interfaces on this device are identical and very flexible, supporting left- or
right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to
communicate directly with multiple devices within a system.
A key characteristic of the TLV320AIC34 is its ability for separate data converters to operate at different sampling
rates simultaneously. This requires use of the two data busses at different rates at the same time, which is fully
supported by this device. In addition, the two data busses can operate at the same time with different data
transfer format configurations. This is useful, for example, in a cellular handset application, where the A-channel
data bus can communicate with a Bluetooth™ transceiver device using PCM format at an 8-ksps sampling rate,
transferring mono or stereo data with A-channel mono or stereo ADCs and DACs. At the same time, the B
channel data bus can be communicating with a multimedia applications processor in I2S format at a 44.1-ksps
sampling rate, transferring mono or stereo data with B-channel mono or stereo ADCs or DACs.
Each data serial interface also can use two sets of terminals for clock communication between external devices,
with the particular terminals used being controlled through register programming. This configuration is shown in
Figure 19 for the A interface, with the B interface having identical flexibility. The TLV320AIC34 provides
independent control over both the formats and clock mux configurations of the two interfaces, so the two busses
can be configured differently from each other.
GPIO1_x
GPIO2_x
WCLK_x
BCLK_x
DIN_x
DOUT_x
Audio Serial Data Bus
B0233-01
Figure 19. Internal Multiplex Capability on Each I2S Bus, Enabling Communication
With Multiple External Devices
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The data busses of the TLV320AIC34 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word
clock (WCLK_x or GPIO1_x) and bit clock (BCLK_x or GPIO2_x) can be independently configured in either
master or slave mode for flexible connectivity to a wide variety of processors.
The word clock (WCLK_x or GPIO1_x) is used to define the beginning of a frame, and may be programmed as
either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
ADC and DAC sampling frequencies.
The bit clock (BCLK_x or GPIO2_x) is used to clock in and out the digital audio data across the serial bus. When
in master mode, this signal can be programmed in two further modes, continuous transfer mode and 256-clock
mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are
generated, so in general, the number of bit clocks per frame is two times the data width. For example, if data
width is chosen as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is
used by a PLL in another device, it is recommended that the 16-bit or 32-bit data-width selections be used.
These cases result in a low-jitter bit clock signal being generated, having frequencies of 32 × fS or 64 × fS. In the
cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal
period, due to the device not having a clean 40 × fS or 48 × fS clock signal readily available. The average
frequency of the bit clock signal is still accurate in these cases (being 40 × fS or 48 × fS), but the resulting clock
signal has higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC34 further includes programmability to put the DOUT_x line in the high-impedance state during
all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit
clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in
multiple codecs able to use a single audio serial data bus.
The TLV320AIC34 also provides additional capability for ADCs and DACs within each partition (A or B) to run at
different data rates, which is described in more detail later in this datasheet. In this mode, both ADC and DAC
data are clocked using the same bit clock (BCLK_x) signal, but two word clock (WCLK_x) signals are used, one
for the ADC data and one for the DAC data. When configured for this mode of operation, the WCLK_x terminal is
used for the DAC word clock, while GPIO1_x can be used for the ADC word clock.
When the audio serial data busses are powered down while configured in master mode, the terminals associated
with the interfaces are put into a high-impedance state.
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RIGHT-JUSTIFIED MODE
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
1/fs
WCLK_x
BCLK_x
Right Channel
Left Channel
DIN_x/
DOUT_x
0
n
2
n–1 n–2
MSB
1
0
n
n–1 n–2
2
1
0
LSB
T0149-03
Figure 20. Right-Justified Serial Bus Mode Operation
LEFT-JUSTIFIED MODE
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
1/fs
WCLK_x
BCLK_x
Right Channel
Left Channel
DIN_x/
DOUT_x
0
n
n–1 n–2
MSB
2
1
0
n
n–1 n–2
2
1
0
n
n–1
LSB
T0150-03
Figure 21. Left-Justified Serial Data Bus Mode Operation
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I2S MODE
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
1/fs
WCLK_x
BCLK_x
1 Clock Before MSB
Right Channel
Left Channel
DIN_x/
DOUT_x
n
n–1 n–2
2
1
MSB
0
n
2
n–1 n–2
1
0
n
LSB
T0151-03
2
Figure 22. I S Serial Data Bus Mode Operation
DSP MODE
In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
1/fs
WCLK_x
BCLK_x
Right Channel
Left Channel
DIN_x/
DOUT_x
1
0
n
n–1 n–2
LSB MSB
2
1
0
n
n–1 n–2
2
1
LSB MSB
0
n
n–1 n–2
LSB MSB
T0152-02
Figure 23. DSP Serial Bus Mode Operation
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TDM DATA TRANSFER
Time-division multiplexed data transfer can be realized in any of the previously mentioned transfer modes if the
256-clock bit clock mode is selected, although it is recommended to be used in either left-justified mode or DSP
mode. By changing the programmable offset, the bit clock in each frame where the data begins can be changed,
and the serial data output driver (DOUT_x) can also be programmed into the high-impedance state during all bit
clocks except when valid data is being put onto the bus. This allows other codecs to be programmed with
different offsets and to drive their data onto the same DOUT_x line, just in a different slot. For incoming data, the
codec simply ignores data on the bus except where it is expected based on the programmed offset. See the
Using TDM Function to Interface Four AIC33 CODECs with a Single Host Processor application report
(SLAA301) and the Using TLV320AIC3x Digital Audio Data Serial Interface With Time-Division Multiplexing
Support application report (SLAA311).
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in
the frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frame
apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- and
right-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
Figure 24 for the two cases.
DSP Mode
WCLK_x
BCLK_x
DIN_x/
DOUT_x
N–1 N–2
••••
1
0
N–1 N–2
••••••
1
0
Offset
Left-Channel Data
Right-Channel Data
Left-Justified Mode
WCLK_x
BCLK_x
DIN_x/
DOUT_x
N–1 N–2
••••
1
Offset
N–1 N–2
0
••••
1
0
Offset
Right-Channel Data
Left-Channel Data
T0153-02
Figure 24. DSP Mode and Left-Justified Mode, Showing the
Effect of a Programmed Data Word Offset
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AUDIO DATA CONVERTERS
The TLV320AIC34 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. As described earlier, the A and B partitions
of the device can operate at entirely asynchronous sampling rates at the same time. The operation of a single
partition is described in detail as follows, although the description applies equally to both partitions.
The data converters are based on the concept of an fS(ref) rate that is used internal to the part, and it is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, fS(ref) is either
44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional
restrictions applying if the PLL is used. This concept is used to provide different sampling rates on the ADC and
DAC simultaneously, and also to enable high-quality playback of low-sampling-rate data without high-frequency
audible noise being generated.
The sampling rate of the DAC can be set to fS(ref)/NDAC or 2 × fS(ref)/NDAC, with NDAC being 1, 1.5, 2, 2.5, 3,
3.5, 4, 4.5, 5, 5.5, or 6.
While only one fS(ref) can be used at a time in one partition, the ADC and DAC sampling rates can differ from
each other by using different NADC and NDAC divider ratios for each. For example, with fS(ref) = 44.1 kHz, the
DAC sampling rate can be set to 44.1 kHz by using NDAC = 1, while the ADC sampling rate can be set to
8.018 kHz by using NADC = 5.5.
When the ADCs and DACs are operating at different sampling rates, an additional word clock is required, to
provide information regarding where data begins for the ADC versus the DAC. In this case, the standard bit clock
signal (which can be supplied through the BCLK_x terminal or through GPIO2_x) is used to transfer both ADC
and DAC data, the standard word clock signal is used to identify the start of the DAC data, and a separate ADC
word clock signal (denoted ADWK) is used. This clock can be supplied or generated from GPIO1_x at the same
time the DAC word clock is supplied or generated from WCLK_x.
AUDIO CLOCK GENERATION
The audio converters in the TLV320AIC34 need an internal audio master clock at a frequency of 256 × fS(ref),
which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC34 is shown in Figure 25.
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MCLK_x
BCLK_x
GPIO2_x
PLL_CLKIN
CLKDIV_CLKIN
CLKDIV_IN
Q = 2, 3,….., 16, 17
PLL_IN
(K ´ R) / P
2/Q
CLKDIV_OUT
K = J.D
J = 1, 2, 3, ...., 62, 63
D = 0000, 0001, ...., 9998, 9999
R = 1, 2, 3, 4, ...., 15, 16
P = 1, 2, ...., 7, 8
PLL_OUT
1/8
PLLDIV_OUT
CLKMUX_OUT
CODEC_CLKIN
CODEC_CLK = 256 ´ fS(ref)
CLKOUT_IN
M = 1, 2, 4, 8
N = 2, 3, ..., 16, 17
2 / (N ´ M)
CLKOUT
GPIO1_x
CODEC
DAC fS
ADC fS
WCLK = fS(ref) /NCODEC
CODEC fS = DAC fS = ADC fS
Set NCODEC = NADC = NDAC = 1, 1.5, 2, ...., 5.5, 6
DAC DRA => NDAC = 0.5
ADC DRA => NADC = 0.5
B0153-02
Figure 25. Audio Clock Generation Processing
The part can accept an MCLK_x input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK_x or
GPIO2_x inputs can also be used to generate the internal audio master clock.
This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is not
powered up. The user can supply a separate clock to GPIO2_x, route this through the PLL, with the resulting
output clock driven out GPIO1_x, for use by other devices in the system.
A primary concern is proper operation of the codec at various sample rates with the limited MCLK_x frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations easily.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK_x inputs, with particular
focus paid to the standard MCLK_x rates already widely used.
When the PLL is disabled,
fS(ref) = CLKDIV_IN / (128 × Q)
Where Q = 2, 3, …, 17
CLKDIV_IN can be MCLK_x, BCLK_x, or GPIO2_x, selected by page 0, register 102, bits D7–D6.
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NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK_x can be
as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz.
When the PLL is enabled,
fS(ref) = (PLLCLK_IN × K × R) / (2048 × P), where
P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK_x or BCLK_x, selected by page 0, register 102, bits D5–D4.
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified
performance:
10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R=1
Example:
MCLK = 12 MHz and fS(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and fS(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
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The following table lists several example cases of typical MCLK rates and how to program the PLL to achieve
fS(ref) = 44.1 kHz or 48 kHz.
fS(ref) = 44.1 kHz
MCLK (MHz)
P
R
J
D
ACHIEVED fS(ref)
% ERROR
2.8224
1
1
32
0
44100.00
0.0000
5.6448
1
1
16
0
44100.00
0.0000
12.0
1
1
7
5264
44100.00
0.0000
13.0
1
1
6
9474
44099.71
–0.0007
16.0
1
1
5
6448
44100.00
0.0000
19.2
1
1
4
7040
44100.00
0.0000
19.68
1
1
4
5893
44100.30
0.0007
48.0
4
1
7
5264
44100.00
0.0000
MCLK (MHz)
P
R
J
D
ACHIEVED fS(ref)
% ERROR
2.048
1
1
48
0
48000.00
0.0000
3.072
1
1
32
0
48000.00
0.0000
4.096
1
1
24
0
48000.00
0.0000
6.144
1
1
16
0
48000.00
0.0000
8.192
1
1
12
0
48000.00
0.0000
12.0
1
1
8
1920
48000.00
0.0000
13.0
1
1
7
5618
47999.71
–0.0006
16.0
1
1
6
1440
48000.00
0.0000
19.2
1
1
5
1200
48000.00
0.0000
19.68
1
1
4
9951
47999.79
–0.0004
48.0
4
1
8
1920
48000.00
0.0000
fS(ref) = 48 kHz
The TLV320AIC34 can also output a separate clock on the GPIO1_x pin. If the PLL is being used for the audio
data converter clock, the M and N settings can be used to provide a divided version of the PLL output. If the PLL
is not being used for the audio data converter clock, the PLL can still be enabled to provide a completely
independent clock output on GPIO1_x. The formula for the GPIO1 clock output when PLL is enabled and
CLKMUX_OUT is 0 is:
GPIO1_x = (PLLCLK_IN × 2 × K × R) / (M × N × P)
When CLKMUX_OUT is 1, regardless of whether PLL is enabled or disabled, the input to the clock output divider
can be selected as MCLK_x, BCLK_x, or GPIO2_x. Is this case, the formula for the GPIO1_x clock is:
GPIO1_x = (CLKDIV_IN × 2) / (M × N), where
M = 1, 2, 4, 8
N = 2, 3, …, 17
CLKDIV_IN can be BCLK_x, MCLK_x, or GPIO2_x, selected by page 0, register 102, bits D7–D6
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STEREO AUDIO ADC
The partition of the TLV320AIC34 includes a stereo audio ADC, which uses a delta-sigma modulator with
128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling
rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC
is in operation, the device requires that an audio master clock be provided and appropriate audio clock
generation be setup within the part.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support the case where only mono record capability is required. In addition, both channels can be fully powered
or entirely powered down.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear phase
output response with a group delay of 17/fS. The –3-dB bandwidth of the decimation filter extends to 0.45 fS and
scales with the sample rate (fS). The filter has minimum 75-dB attenuation over the stopband from 0.55 fS to 64
fS. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that
can be independently set to three different settings, can be disabled entirely, or can be programmed to a
completely customized transfer function, as described in the following section.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC34 integrates a second-order
analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient anti-aliasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by the PGA equals the desired value set by the register. The soft-stepping control can also be
disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to
the part after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When
the ADC power-down flag is no longer set, the audio master clock can be shut down.
STEREO AUDIO ADC HIGH-PASS FILTER
Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The
TLV320AIC34 has a programmable first-order, high-pass filter that can be used for this purpose. The digital filter
coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0, N1,
and D1. The transfer function of the digital high-pass filter is of the form:
*1
H(z) + N0 ) N1 z *1
32768 * D1 z
(1)
Programming the left channel is done by writing to page 1, registers 65–70, and the right channel is programmed
by writing to page 1, registers 71–76. After the coefficients have been loaded, these ADC high-pass filter
coefficients can be selected by writing to page 0, register 107, D7–D6, and the high-pass filter can be enabled by
writing to page 0, register 12, bits D7–D4.
DIGITAL AUDIO PROCESSING FOR RECORD PATH
In applications where record-only is selected in a particular partition, and the DAC in that partition is powered
down, the playback path signal processing blocks can be used in the ADC record path. These filtering blocks can
support high-pass, low-pass, band-pass, or notch filtering, or an entirely arbitrary transfer function. In this mode,
the record-only path has switches SW-D1 through SW-D4 closed and reroutes the ADC output data through the
digital signal processing blocks. Because the DAC digital signal processing blocks are being re-used, naturally
the addresses of these digital filter coefficients are the same as for the DAC digital processing and are located on
page 1, registers 1–52. This record-only mode is enabled by powering down both DACs by writing to page 0,
register 37, bits D7–D6 (D7 = D6 = 0). Next, enable the digital filter pathway for the ADC by writing a 1 to page 0,
register 107, bit D3. (Note, this pathway is only enabled if both DACs are powered down.) This record-only path
for one partition can be seen in Figure 26.
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BCLK_x
WCLK_x
DIN_x
DOUT_x
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AGC
DINR
DINL
DOUTL
DOUTR
Digital Audio Data Serial Interface
DAC
Powered
Down
Record Path
SW-D2
Left-Channel
Analog Inputs
+
PGA
0 dB–59.5 dB,
0.5-dB Steps
Effects
ADC
Volume
Control
DAC
L
SW-D1
DAC
Powered
Down
Record Path
AGC
SW-D4
Right-Channel
Analog Inputs
+
PGA
0 dB–59.5 dB,
0.5-dB Steps
Effects
ADC
SW-D3
Volume
Control
DAC
R
B0173-02
Figure 26. Record-Only Mode With Digital Processing Path Enabled
AUTOMATIC GAIN CONTROL (AGC)
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant
output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry
automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a
person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several
programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum
PGA gain applicable that allow the algorithm to be fine-tuned for any particular application. The algorithm uses
the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the
nominal amplitude of the output signal.
Note that completely independent AGC circuitry is included with each ADC channel with entirely independent
control over the algorithm from one channel to the next. This is attractive in cases where two microphones are
used in a system, but may have different placement in the end equipment and require different dynamic
performance for optimal system operation.
Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level.
The TLV320AIC34 allows programming of eight different target levels, which can be programmed from –5.5 dB
to –24 dB relative to a full-scale signal. Because the device reacts to the signal absolute average and not to peak
levels, it is recommended that the target level be set with enough margin to avoid clipping at the occurrence of
loud sounds.
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Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
can be varied from 7 ms to 1,408 ms. The extended left-channel attack time can be programmed by writing to
page 0, register 103, and the right channel is programmed by writing to page 0, register 105.
Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied
in the range from 0.05 s to 22.4 s. The extended left-channel decay time can be programmed by writing to page
0, register 104, and the right channel is programmed by writing to page 0, register 106.
The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the
clock setup that is used. Table 3 shows the relationship of the NADC ratio to the maximum time available for the
AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit any
practical AGC decay time that is needed by the system.
Table 3. AGC Decay Time Restriction
NADC RATIO
MAXIMUM DECAY TIME (seconds)
1
4
1.5
5.6
2
8
2.5
9.6
3
11.2
3.5
11.2
4
16
4.5
16
5
19.2
5.5
22.4
6
22.4
Noise gate threshold determines the level below which if the input speech average value falls, AGC considers it
as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise
threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold
setting. This ensures that noise does not get gained up in the absence of speech. Noise threshold level in the
AGC algorithm is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also
available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain
from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise
threshold flag is set, the status of gain applied by the AGC and the saturation flag should be ignored.
Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the
AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than
the programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.
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Input
Signal
Target
Level
Output
Signal
AGC
Gain
Decay Time
Attack
Time
Figure 27. Typical Operation of the AGC Algorithm During Speech Recording
Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time
constants are achieved using the fS(ref) value programmed in the control registers. However, if the fS(ref) is set in
the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different
fS(ref) in practice, then the time constants would not be correct. See The Built-In AGC Function in TSC2100/01
and TLV320AIC26/28/32/33 Devices application report (SLAA260).
STEREO AUDIO DAC
The TLV320AIC34 includes a stereo audio DAC in each partition supporting sampling rates from 8 kHz to
96 kHz. Each channel of the audio DACs consists of a digital audio processing block, a digital interpolation filter,
multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed
within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × fS(ref)
and changing the oversampling ratio as the input sample rate is changed. For an fS(ref) of 48 kHz, the digital
delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated
within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly,
for an fS(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.
The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is
enabled in the DAC.
Allowed Q values = 4, 8, 9, 12, 16
Q values where equivalent fS(ref) can be achieved by turning on PLL
Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16.0 and PLL enabled)
Q = 10, 14 (set P = 5, 7 and K = 8.0 and PLL enabled)
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DIGITAL AUDIO PROCESSING FOR PLAYBACK
The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment,
speaker equalization, and 3-D effects processing. The de-emphasis function is implemented by a programmable
digital filter block with fully programmable coefficients (see page 1, registers 21–26 for left channel, page 1,
registers 47–52 for right channel). If de-emphasis is not required in a particular application, this programmable
filter block can be used for some other purpose. The de-emphasis filter transfer function is given by:
*1
H(z) + N0 ) N1 z *1
32768 * D1 z
(2)
where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients that
should be loaded to implement standard de-emphasis filters are given in Table 4.
Table 4. De-Emphasis Coefficients for Common Audio Sampling Rates
SAMPLING FREQUENCY (kHz)
N0
N1
D1
32
16,950
–1,220
17,037
44.1
15,091
–2,877
20,555
48
14,677
–3,283
21,374
In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth-order digital IIR
filter with programmable coefficients (one set per channel). This filter is implemented as a cascade of two biquad
sections with frequency response given by:
N0 ) 2
ǒ32768
*2
N1 z *1 ) N2 z *2
D1 z *1 * D2 z *2
N3 ) 2
Ǔǒ32768
*2
N4 z *1 ) N5 z*2
D4 z *1 * D5 z*2
Ǔ
(3)
The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structure
of the filtering when configured for independent channel processing is shown in Figure 28, with LB1
corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly
corresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5. The RB1 and
RB2 filters refer to the first and second right-channel biquad filters, respectively.
LB1
LB2
RB1
RB2
B0154-01
Figure 28. Structure of the Digital Effects Processing for Independent Channel Processing
The coefficients for this filter implement a variety of sound effects, with bass boost or treble boost being the most
commonly used in portable audio applications. The default N and D coefficients in the part are given in Table 5
and implement a shelving filter with 0-dB gain from dc to approximately 150 Hz, at which point it rolls off to a
3-dB attenuation for higher-frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D
coefficients are represented by 16-bit, 2s-complement numbers with values ranging from –32,768 to 32,767.
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Table 5. Default Digital Effects Processing Filter Coefficients,
When in Independent Channel Processing Configuration
Coefficients
N0 = N3
D1 = D4
N1 = N4
D2 = D5
N2 = N5
27,619
32,131
–27,034
–31,506
26,461
The digital processing also includes capability to implement 3-D processing algorithms by providing means to
process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo
output playback. The architecture of this processing mode, and the programmable filters available for use in the
system, are shown in Figure 29. Note that the programmable attenuation block provides a method of adjusting
the level of 3-D effect introduced into the final stereo output. This, combined with the fully programmable biquad
filters in the system, enables the user to optimize fully the audio effects for a particular system and provide
extensive differentiation from other systems using the same device.
+ +
+
L
+
+
–
LB1
R
LB2
To Left Channel
Atten
+
–
+
To Right Channel
RB2
B0155-01
Figure 29. Architecture of the Digital Audio Processing When 3-D Effects are Enabled
It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.
While new coefficients are being written to the device over the control port, it is possible that a filter using
partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable
audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of
effects can be entirely avoided.
DIGITAL INTERPOLATION FILTER
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21/fS. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and still
audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation
filter is designed to maintain at least 65-dB rejection of images that land below 7.455 fS. To use the
programmable interpolation capability, fS(ref) should be programmed to a higher rate (restricted to be in the range
of 39 kHz to 53 kHz when the PLL is in use), and the actual fS is set using the NDAC divider. For example, if
fS = 8 kHz is required, then fS(ref) can be set to 48 kHz, and the DAC fS set to fS(ref)/6. This ensures that all images
of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.
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DELTA-SIGMA AUDIO DAC
The stereo audio DAC in each partition incorporates a third-order multibit delta-sigma modulator followed by an
analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and
noise shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed
by a continuous-time RC filter. The analog FIR operates at a rate of 128 × fS(ref) (6.144 MHz when fS(ref) = 48 kHz,
5.6448 MHz when fS(ref) = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive
clock jitter on the MCLK_x input. Therefore, care must be taken to keep jitter on this clock to a minimum.
AUDIO DAC DIGITAL VOLUME CONTROL
The audio DAC includes a digital volume control block which implements a programmable digital gain. The
volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for
each channel. The volume level of both channels can also be changed simultaneously by the master volume
control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by
one step per input sample, either up or down, until the desired volume is reached. The rate of soft stepping can
be slowed to one step per two input samples through a register bit.
Because of soft stepping, the host does not know when the DAC has been actually muted. This may be
important if the host wishes to mute the DAC before making a significant change, such as changing sample
rates. In order to help with this situation, the device provides a flag back to the host via a read-only register bit
that alerts the host when the part has completed the soft-stepping and the actual volume has reached the
desired volume level. The soft-stepping feature can be disabled through register programming. If soft stepping is
enabled, the MCLK_x signal should be kept applied to the device until the DAC power-down flag is set. When
this flag is set, the internal soft-stepping process and power-down sequence is complete, and the MCLK_x can
then be stopped if desired.
The TLV320AIC34 also includes functionality to detect when the user switches on or off the de-emphasis or
digital audio processing functions, to (1) soft-mute the DAC volume control, (2) change the operation of the digital
effects processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to
instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC. The
circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired volume
level. At power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.
INCREASING DAC DYNAMIC RANGE
The TLV320AIC34 allows trading off dynamic range with power consumption. The DAC dynamic range can be
increased by writing to page 0, register 109, bits D7–D6. The lowest DAC current setting is the default, and the
dynamic range is displayed in the datasheet table. Increasing the current can increase the DAC dynamic range
by up to 1.5 dB.
ANALOG OUTPUT COMMON-MODE ADJUSTMENT
The output common-mode voltage and output range of the analog output of each partition are determined by an
internal band-gap reference, in contrast to other codecs that may use a divided version of the supply. This
scheme is used to reduce the coupling of noise that may be on the supply (such as 217-Hz noise in a GSM cell
phone) into the audio signal path.
However, due to the possible wide variation in analog supply range (2.7 V–3.6 V), an output common-mode
voltage setting of 1.35 V, which would be used for a 2.7-V supply case, is overly conservative if the supply is
actually much higher, such as 3.3 V or 3.6 V. In order to optimize device operation, the TLV320AIC34 includes a
programmable output common-mode level, which can be set by register programming to a level most appropriate
to the actual supply range used by a particular customer. The output common-mode level can be selected from
four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to 1.8 V (most
appropriate for high supply ranges, near 3.6 V). Note that there is also some limitation on the range of DVDD
voltage as well in determining which setting is most appropriate.
40
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Table 6. Analog Output Common-Mode Recommended Settings
CM SETTING
RECOMMENDED AVDD, DRVDD
RECOMMENDED DVDD
1.35 V
2.7 V–3.6 V
1.65 V–1.95 V
1.5 V
3 V–3.6 V
1.65 V–1.95 V
1.65 V
3.3 V–3.6 V
1.8 V–1.95 V
1.8 V
3.6 V
1.95 V
AUDIO DAC POWER CONTROL
The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can
be powered up or down independently. This provides power savings when only a mono playback stream is
needed.
AUDIO ANALOG INPUTS
The TLV320AIC34 includes 20 analog audio input terminals, 10 for each partition. The 10 inputs in each partition
can be configured as up to four fully differential pairs plus one single-ended pair of audio inputs, or up to six (or
eight, if LINE2(L/R)M to line bypass are considered) single-ended audio inputs. These ten terminals connect
through series resistors and switches to the virtual ground terminals of two fully differential operational amplifiers
(one per ADC/PGA channel). By selecting to turn on only one set of switches per operational amplifier at a time,
the inputs can be effectively multiplexed to each ADC PGA channel.
By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved.
However, single-ended and fully differential audio inputs cannot be mixed into the same ADC PGA at the same
time. Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal operational
amplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented,
the user should take adequate precautions to avoid such a saturation case from occurring. In general, the mixed
signal should not exceed 2 Vp-p single-ended or 4 Vp-p fully differential.
In most mixing applications, there is also a general need to adjust the levels of the individual signals being
mixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal
generally should be amplified to a level comparable to that of the large signal before mixing. In order to
accommodate this need, the TLV320AIC34 includes input level control on each of the individual inputs before
they are mixed or multiplexed into the ADC PGAs, with gain programmable from 0 dB to –12 dB in 1.5-dB steps.
Note that this input level control is not intended to be a volume control, but instead used occasionally for level
setting. Soft-stepping of the input level control settings is implemented in this device, with the speed and
functionality following the settings used by the ADC PGA for soft-stepping.
The TLV320AIC34 supports the ability to mix up to three fully differential analog inputs into each ADC PGA
channel. Figure 30 shows the mixing configuration for the left channel of one partition, which can mix the signals
LINE1LP_x, LINE1LM_x, LINE2LP_x, LINE2LM_x, LINE1RP_x, and LINE1RM_x of the associated partition.
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
LINE1LP_x
LINE1LM_x
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
LINE2LP_x
LINE2LM_x
To Left ADC PGA
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
LINE1RP_x
LINE1RM_x
B0156-03
Figure 30. Left-Channel Fully Differential Analog Mixing Capability
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Three fully-differential analog inputs can similarly be mixed into each partition's right-ADC PGA as well,
consisting of LINE1RP_x, LINE1RM_x, LINE2RP_x, LINE2RM_x, LINE1LP_x, and LINE1LM_x. Note that it is
not necessary to mix all three fully differential signals if this is not desired—unnecessary inputs can simply be
muted using the input level control registers.
Inputs can also be selected as single-ended instead of fully differential, and mixing or multiplexing into the ADC
PGAs is also possible in this mode. It is not possible, however, for an input pair to be selected as fully differential
for connection to one ADC PGA and simultaneously selected as single-ended for connection to the other ADC
PGA channel in the same partition. However, it is possible for an input to be selected or mixed into both left- and
right-channel PGAs of the same partition, as long as it has the same configuration for both channels (either both
single-ended or both fully differential).
Figure 31 shows the single-ended mixing configuration for one partition's left-channel ADC PGA, which enables
mixing of the signals LINE1LP_x, LINE2LP_x, LINE1RP_x, MIC3L_x, and MIC3R_x. The right-channel ADC
PGA mix is similar, enabling mixing of the signals LINE1RP_x, LINE2RP_x, LINE1LP_x, MIC3L_x, and
MIC3R_x.
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
LINE1LP_x
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
LINE2LP_x
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
To Left ADC PGA
LINE1RP_x
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
MIC3L_x
Gain = 0, –1.5, –3, . . ., –12 dB, Mute
MIC3R_x
B0156-04
Figure 31. Left-Channel Single-Ended Analog Input Mixing Configuration
ANALOG INPUT BYPASS PATH FUNCTIONALITY
The TLV320AIC34 includes the additional ability to route some analog input signals past the integrated data
converters, for mixing with other analog signals and then direct connection to the output drivers. This capability is
useful in a cell phone, for example, when a separate FM radio device provides a stereo analog output signal that
must be routed to headphones. The TLV320AIC34 supports this in a low-power mode by providing a direct
analog path through the device to the output drivers, while all ADCs and DACs can be completely powered down
to save power.
For fully differential inputs, the TLV320AIC34 provides the ability to pass the signals LINE1LP_x, LINE1LM_x,
LINE1RP_x, and LINE1RM_x of each partition directly to the output stage of the same partition. If in single-ended
configuration, the device can pass the signal LINE1LP_x and LINE1RP_x to the output stage directly.
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ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
In addition to the input bypass path described previously, the TLV320AIC34 also includes the ability to route the
ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the
output drivers of the same partition. These bypass functions are described in more detail in the sections on
output mixing and output driver configurations.
INPUT IMPEDANCE AND VCM CONTROL
The TLV320AIC34 includes several programmable settings to control analog input terminals, particularly when
they are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a
high-impedance state, such that the input impedance seen looking into the device is extremely high. Note,
however, that the terminals on the device do include protection diode circuits connected to AVDD_ADC and
AVSS_ADC. Thus, if any voltage is driven onto a terminal approximately one diode drop (~0.6 V) above
AVDD_ADC or one diode drop below AVSS_ADC, these protection diodes begin conducting current, resulting in
an effective impedance that no longer appears as a high-impedance state.
Another programmable option for unselected analog inputs is to hold them weakly at the common-mode input
voltage of the ADC PGA (which is determined by an internal band-gap voltage reference). This is useful to keep
the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for
them to charge up suddenly when the input is changed from being unselected to selected for connection to an
ADC PGA. This option is controlled in page 0, registers 20 and 23 of each partition. The user should ensure this
option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input
bypass path, because it can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input terminals on the TLV320AIC34 should be ac-coupled to analog input sources,
the only exception to this generally being if an ADC is being used for dc voltage measurement. The ac-coupling
capacitor causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of
0 dB, and increasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a
0.1-µF ac-coupling capacitor at an analog input results in a high-pass filter pole of 80 Hz when the 0-dB input
level control setting is selected.
PASSIVE ANALOG BYPASS DURING POWER DOWN
Programming the TLV320AIC34 to passive analog bypass occurs by configuring the output stage switches for
pass-through. This is done by opening switches SW-L0, SW-L3, SW-R0, SW-R3 and closing either SW-L1 or
SW-L2 and SW-R1 or SW-R2. See Figure 32, Passive Analog Bypass Mode Configuration. Programming this
mode is done by writing to page 0, register 108.
Connecting the LINE1LP_x input signal to the LEFT_LOP_x terminal is done by closing SW-L1 and opening
SW-L0; this action is done by writing a 1 to page 0, register 108, bit D0. Connecting the LINE2LP_x input signal
to the LEFT_LOP_x terminal is done by closing SW-L2 and opening SW-L0; this action is done by writing a 1 to
page 0, register 108, bit D2. Connecting the LINE1LM_x input signal to the LEFT_LOM_x terminal is done by
closing SW-L4 and opening SW-L3; this action is done by writing a 1 to page 0, register 108, bit D1. Connecting
the LINE2LM_x input signal to the LEFT_LOM_x terminal is done by closing SW-L5 and opening SW-L3; this
action is done by writing a 1 to page 0, register 108, bit D3.
Connecting the LINE1RP_x input signal to the RIGHT_LOP_x terminal is done by closing SW-R1 and opening
SW-R0; this action is done by writing a 1 to page 0, register 108, bit D4. Connecting the LINE2RP_x input signal
to the RIGHT_LOP_x terminal is done by closing SW-R2 and opening SW-R0; this action is done by writing a 1
to page 0, register 108, bit D6. Connecting the LINE1RM_x input signal to the RIGHT_LOM_x terminal is done
by closing SW-R4 and opening SW-R3; this action is done by writing a 1 to page 0, register 108, bit D5.
Connecting the LINE2RM_x input signal to the RIGHT_LOM_x terminal is done by closing SW-R5 and opening
SW-R3; this action is done by writing a 1 to page 0, register 108, bit D7. A diagram of the passive analog bypass
mode configuration can be seen in Figure 32.
In general, connecting two switches to the same output terminal should be avoided, as this error shorts two input
signals together, and would likely cause distortion of the signal as the two signals are in contention; poor
frequency response would also likely occur.
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LINE2LP_x
SW-L2
LINE2LP_x
SW-L1
SW-L0
SW-L3
LINE1LP_x
LEFT_LOP_x
LEFT_LOM_x
SW-L4
LINE1LP_x
LINE1LM_x
LINE1LM_x
LINE2LM_x
SW-L5
SW-R2
LINE1RP_x
LINE1RM_x
LINE1RP_x
SW-R1
SW-R0
SW-R3
LINE2RP_x
LINE1RM_x
LINE2RP_x
LINE2RM_x
RIGHT_LOP_x
RIGHT_LOM_x
SW-R4
SW-R5
LINE2RM_x
B0174-03
Figure 32. Passive Analog Bypass Mode Configuration
MICBIAS_x GENERATION
The TLV320AIC34 includes a programmable microphone bias output voltage (MICBIAS_x) in each partition,
capable of providing output voltages of 2 V or 2.5 V (both derived from the on-chip band-gap voltage) with 4-mA
output current drive. In addition, MICBIAS_x can be programmed to be switched to AVDD_ADC directly through
an on-chip switch, or it can be powered down completely when not needed, for power savings. This function is
controlled by register programming in page 0, register 25 in each partition.
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DIGITAL MICROPHONE CONNECTIVITY
The TLV320AIC34 includes support for connection of digital microphones to the device by routing the digital
signal directly into the ADC digital decimation filter, where it is filtered, downsampled, and provided to the host
processor over the audio data serial bus.
When digital microphone mode is enabled, the TLV320AIC34 provides an oversampling clock output on
GPIO1_x for use by the digital microphone to transmit its data, which is applied to the device on GPIO2_x. The
TLV320AIC34 includes the capability to latch the data on either the rising, falling, or both edges of this supplied
clock, enabling support for stereo digital microphones. Digital microphone operation is configured using page 0,
registers 98–99 of each partition. The the oversampling ratio is configured using page 0, register 8, and the
digital microphone and on-chip analog microphone can be selected independently for each ADC channel using
page 0, register 107. For more details on digital microphone support, see the Using the Digital Microphone
Function on TLV320AIC33 With AIC33EVM/USB-MODEVM System application report (SLAA275).
ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
The TLV320AIC34 has two fully differential line output drivers, three in each partition, with each driver capable of
driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers for one
partition is shown in Figure 33 and Figure 34. This design includes extensive capability to adjust signal levels
independently before any mixing occurs, beyond that already provided by the PGA gain and the DAC digital
volume control.
The LINE1LP_x and LINE1LM_x signals refer to the signals that travel through the analog input bypass path to
the output stage. The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed
around the ADC to the output stage. Note that because both left- and right-channel signals of each partition are
routed to all output drivers of that partition, a mono mix of any of the stereo signals can easily be obtained by
setting the volume controls of both left- and right-channel signals to –6 dB and mixing them. Undesired signals
can also be disconnected from the mix through register control.
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DAC_L
Stereo
Audio
DAC
DAC_L1
DAC_L2
DAC_L3
DAC_R
DAC_R1
DAC_R2
DAC_R3
LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
DAC_L1
DAC_R1
LEFT_LOP_x
Volume
Controls,
Mixing
LEFT_LOM_x
Gain = 0 dB to 9 dB,
Mute
DAC_L3
LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
DAC_L1
DAC_R1
RIGHT_LOP_x
Volume
Controls,
Mixing
RIGHT_LOM_x
Gain = 0 dB to 9 dB,
Mute
DAC_L3
LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
DAC_L1
DAC_R1
MONO_LOP_x
Volume
Controls,
Mixing
MONO_LOM_x
Gain = 0 dB to 9 dB,
Mute
B0157-03
Figure 33. Architecture of the Output Stage Leading to the Fully Differential Line Output Drivers
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LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
0 dB to –78 dB
0 dB to –78 dB
0 dB to –78 dB
+
0 dB to –78 dB
DAC_L1
0 dB to –78 dB
DAC_R1
0 dB to –78 dB
B0158-03
Figure 34. Detail of the Volume Control and Mixing Function Shown in Figure 33
The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based
on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC
output is only needed at the stereo line outputs of that partition, then it is recommended to use the routing
through path DAC_L3/R3 to the fully differential stereo line outputs. This results not only in higher-quality output
performance, but also in lower-power operation, because the analog volume controls and mixing blocks ahead of
these drivers can be powered down.
If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to
LEFT_LOP_x, LEFT_LOM_x, RIGHT_LOP_x, RIGHT_LOM_x, MONO_LOP_x, and MONO_LOM_x) or must be
mixed with other analog signals, then the DAC outputs should be switched through the DAC_L1 and DAC_R1
path. This option provides the maximum flexibility for routing of the DAC analog signals to the output drivers.
The TLV320AIC34 includes an output level control on each output driver with limited gain adjustment from 0 dB
to 9 dB. The output driver circuitry in this device is designed to provide a low-distortion output while playing
full-scale stereo DAC signals at a 0-dB gain setting. However, a higher-amplitude output can be obtained at the
cost of increased signal distortion at the output. This output level control allows the user to make this tradeoff
based on the requirements of the end equipment. Note that this output level control is not intended to be used as
a standard output volume control. It is expected to be used only sparingly for level setting, i.e., adjustment of the
full-scale output range of the device.
Each differential line output driver can be powered down independently of the others when it is not needed in the
system. When placed into power down through register programming, the driver output terminals are placed into
a high-impedance state.
ANALOG HIGH-POWER OUTPUT DRIVERS
The TLV320AIC34 includes eight high-power output drivers, four in each partition, with extensive flexibility in their
usage. These output drivers are individually capable of driving 40 mW each into a 16-Ω load in single-ended
configuration, and codec A can be used in pairs to drive up to 500 mW into an 8- load connected in
bridge-terminated load (BTL) configuration between two driver outputs. Codec B is not designed to drive 8-Ω
speakers.
The high-power output drivers can be configured in a variety of ways, including:
• Driving up to four fully differential output signals, using pairs of drivers
• Driving up to eight single-ended output signals
• Driving up to four single-ended output signals, with the remaining drivers driving a fixed VCM level, for
pseudo-differential stereo outputs
• Driving up to two 8-Ω speakers connected BTL between pairs of driver output terminals for codec block A
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Combinations of the foregoing
The output-stage architecture of each partition leading to the high-power output drivers is shown in Figure 35,
with the volume control and mixing blocks being effectively identical to those shown in Figure 34. Note that each
of these drivers has an output level control block like those included with the line output drivers, allowing gain
adjustment up to 9 dB on the output signal. As in the previous case, this output level adjustment is not intended
to be used as a standard volume control, but instead is included for additional full-scale output signal level
control.
Two of the output drivers in each partition, HPROUT_x and HPLOUT_x, include a direct connection path for the
stereo DAC outputs to be passed directly to the output drivers, bypassing the analog volume controls and mixing
networks, by using the DAC_L2/R2 path. As in the line output case, this functionality provides the highest-quality
DAC playback performance with reduced power dissipation, but can only be used if the DAC output is not being
routed to multiple output drivers simultaneously, and if mixing of the DAC output with other analog signals is not
needed.
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LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
DAC_L1
DAC_R1
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Volume
Controls,
Mixing
Volume Level
0 dB to 9 dB, Mute
HPLOUT_x
DAC_L2
LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
DAC_L1
DAC_R1
Volume
Controls,
Mixing
LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
DAC_L1
DAC_R1
Volume
Controls,
Mixing
VCM
VCM
Volume Level
0 dB to 9 dB, Mute
Volume Level
0 dB to 9 dB, Mute
HPLCOM_x
HPRCOM_x
DAC_R2
LINE2LP_x
LINE2LM_x
LINE2RP_x
LINE2RM_x
PGA_LP_x
PGA_LM_x
PGA_RP_x
PGA_RM_x
DAC_L1
DAC_R1
Volume
Controls,
Mixing
Volume Level
0 dB to 9 dB, Mute
HPROUT_x
B0159-03
Figure 35. Architecture of the Output Stage Leading to the High-Power Output Drivers
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The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on
and power-off transient conditions. The user should first program the type of output configuration being used in
page 0, register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts. The
power-up delay time for the high-power output drivers is also programmable over a wide range of time delays,
from instantaneous up to 4 s, using page 0, register 42.
When these output drivers are powered down, they can be placed into a variety of output conditions based on
register programming. If lowest-power operation is desired, then the outputs can be placed into a
high-impedance state, and all power to the output stage is removed. However, this generally results in the output
nodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the terminals. This
then results in a longer delay requirement to avoid output artifacts during driver power-on. In order to reduce this
required power-on delay, the TLV320AIC34 includes an option for the output terminals of the drivers to be weakly
driven to the VCM level at which they would normally when powered with no signal applied. This output VCM
level is determined by an internal band-gap voltage reference, and thus results in extra power dissipation when
the drivers are in power down. However, this option provides the fastest method for transitioning the drivers from
power down to full-power operation without any output artifact introduced.
The device includes a further option that falls between the other two—although it requires less power drawn
while the output drivers are in power down, it takes a slightly longer delay to power up without artifact than if the
band-gap reference is kept alive. In this alternate mode, the powered-down output driver terminal is weakly
driven to a voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This
voltage does not match the actual VCM of a fully powered driver, but due to the output voltage being close to its
final value, a much shorter power-up delay time setting can be used and still avoid any audible output artifacts.
These output voltage options are controlled in page 0, register 42.
The high-power output drivers can also be programmed to power up first with the output level control in a highly
attenuated state, then the output driver automatically slowly reduces the output attenuation to reach the desired
output level setting programmed. This capability is enabled by default but can be enabled in page 0, register 40.
SHORT-CIRCUIT OUTPUT PROTECTION
The TLV320AIC34 includes programmable short-circuit protection for the high-power output drivers, for maximum
flexibility in a given application. By default, if these output drivers are shorted, they automatically limit the
maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from an
overcurrent condition. In this mode, the user can read page 0, register 95 to determine whether the part is in
short-circuit protection or not, and then decide whether to program the device to power down the output drivers.
However, the device includes further capability to power down an output driver automatically whenever it goes
into short-circuit protection, without requiring intervention from the user. In this case, the output driver stays in a
power-down condition until the user specifically programs it to power down and then power back up again, to
clear the short-circuit flag.
JACK/HEADSET DETECTION
The TLV320AIC34 includes extensive capability to monitor a headphone, microphone, or headset jack,
determine if a plug has been inserted into the jack, and then determine what type of headset/headphone is wired
to the plug. Figure 36 shows one configuration of the device that enables detection and determination of headset
type when a pseudodifferential (capless) stereo headphone output configuration is used. The registers used for
this function are page 0, registers 13, 14, 37, and 38. The type of headset detected can be read back from
page 0, register 13. Note that for best results, it is recommended to select a MICBIAS_x value as high as
possible, and to program the output driver common-mode level at a 1.35-V or 1.5-V level.
50
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MICBIAS_x
g
Stereo
s
AVDD
s
MICDET_x
To Detection Block
MIC3L_x or
MIC3R_x
Cellular
g
s
m
HPLOUT_x
Stereo +
Cellular
g
s
m
s
HPROUT_x
m = mic
s = ear speaker
g = ground/vcm
HPRCOM_x
To
Detection
Block
HPLCOM_x
VCM
B0243-01
Figure 36. Configuration of Device for Jack Detection Using a
Pseudo-Differential (Capless) Headphone Output Connection
Figure 37 shows a modified output configuration that is used when the output drivers are ac-coupled. Note that in
this mode, the device cannot accurately determine whether the inserted headphone is a mono or stereo
headphone.
MICBIAS_x
g
Stereo
s
s
MICDET_x
AVDD
To Detection Block
MIC3L_x or
MIC3R_x
Cellular
g
s
m
HPLOUT_x
Stereo +
Cellular
g
m
s
s
HPROUT_x
m = mic
s = ear speaker
g = ground/vcm
B0244-01
Figure 37. Configuration of Device for Jack Detection Using an
AC-Coupled Stereo Headphone Output Connection
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An output configuration for the case of the outputs driving fully differential stereo headphones is shown in
Figure 38. In this mode, there is a requirement on the jack side that either HPLCOM_x or HPLOUT_x be shorted
to ground if the plug is removed. This requirement can be implemented using a spring terminal in a jack. For this
mode to function properly, short-circuit detection should be enabled and configured to power down the drivers if a
short circuit is detected. The register that controls this functionality is in page 0, register 38, bits D2–D1.
MICDET_x
This switch closes when
jack is removed
To Detection block
HPLOUT_x
HPLCOM_x
HPRCOM_x
HPROUT_x
B0245-01
Figure 38. Configuration of Device for Jack Detection Using
a Fully Differential Stereo Headphone Output Connection
CONTROL REGISTERS
The control registers for the TLV320AIC34 are mapped into page 0 and page 1. Page 0 is used to configure the
codec analog and digital pathways, whereas page 1 is used to program digital filter coefficients. The
TLV320AIC34 is a four-channel codec that contains a partition of two stereo codecs, codec A and codec B.
Because all of the functionality of each partition is identical, page 0 and page 1 are only shown once in the
following register descriptions. Note that only page 0, register 101 for codec block A is different than page 0,
register 101 for codec block B, so page 0, register 101 is shown twice in the following register listing. Each of
these status registers displays the I2C register address based on the respective state of the ADDR_A and
ADDR_B terminals.
Because the two stereo codecs in the TLV320AIC34 are independent, none of the register values are shared.
Therefore, BOTH codecs, codec A and codec B, must be completely and independently programmed—codec A
using its unique I2C address, and also codec B using its unique I2C address. All I2C registers are 8 bits in width,
with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.
Page 0 / Register 0:
READ/
WRITE
RESET
VALUE
D7–D1
X
0000 000
D0
R/W
0
BIT (1)
(1)
52
Page Select Register
DESCRIPTION
Reserved. Write only zeros to these register bits.
Page Select Bit
Writing zero to this bit sets page 0 as the active page for subsequent register accesses. Writing a one to
this bit sets page 1 as the active page for subsequent register accesses. It is recommended that the user
read this register bit back after each write, to ensure that the proper page is being accessed for future
register read/writes.
When resetting registers related to routing and volume controls of output drivers, it is recommended to reset them by writing directly to
the registers instead of using software reset.
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Page 0 / Register 1:
BIT
READ/
WRITE
RESET
VALUE
D7
W
0
D6–D0
W
000 0000
Software Reset Register
DESCRIPTION
Software Reset Bit
0 : Don’t care
1 : Self-clearing software reset
Reserved. Do not write to these bits.
Page 0 / Register 2:
Codec Sample Rate Select Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
ADC Sample Rate Select
0000: ADC fS = fS(ref)/1
0001: ADC fS = fS(ref)/1.5
0010: ADC fS = fS(ref)/2
0011: ADC fS = fS(ref)/2.5
0100: ADC fS = fS(ref)/3
0101: ADC fS = fS(ref)/3.5
0110: ADC fS = fS(ref)/4
0111: ADC fS = fS(ref)/4.5
1000: ADC fS = fS(ref)/5
1001: ADC fS = fS(ref)/5.5
1010: ADC fS = fS(ref)/6
1011–1111: Reserved. Do not write these sequences to these register bits.
D3–D0
R/W
0000
DAC Sample Rate Select
0000 : DAC fS = fS(ref)/1
0001 : DAC fS = fS(ref)/1.5
0010 : DAC fS = fS(ref)/2
0011 : DAC fS = fS(ref)/2.5
0100 : DAC fS = fS(ref)/3
0101 : DAC fS = fS(ref)/3.5
0110 : DAC fS = fS(ref)/4
0111 : DAC fS = fS(ref)/4.5
1000 : DAC fS = fS(ref)/5
1001: DAC fS = fS(ref)/5.5
1010: DAC fS = fS(ref) / 6
1011–1111 : Reserved. Do not write these sequences to these register bits.
DESCRIPTION
Page 0 / Register 3:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D3
R/W
0010
PLL Q Value
0000: Q = 16
0001: Q = 17
0010: Q = 2
0011: Q = 3
0100: Q = 4
…
1110: Q = 14
1111: Q = 15
D2–D0
R/W
000
PLL P Value
000: P = 8
001: P = 1
010: P = 2
011: P = 3
100: P = 4
101: P = 5
110: P = 6
111: P = 7
PLL Programming Register A
DESCRIPTION
PLL Control Bit
0: PLL is disabled.
1: PLL is enabled.
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Page 0 / Register 4:
BIT
READ/
WRITE
RESET
VALUE
D7–D2
R/W
0000 01
D1–D0
R/W
00
DESCRIPTION
PLL J Value
0000 00: Reserved. Do not write this sequence to these register bits.
0000 01: J = 1
0000 10: J = 2
0000 11: J = 3
…
1111 10: J = 62
1111 11: J = 63
Reserved. Write only zeros to these bits.
Page 0 / Register 5:
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0000 0000
(1)
PLL Programming Register B
PLL Programming Register C (1)
DESCRIPTION
PLL D value – Eight most-significant bits of a 14-bit unsigned integer. Valid values for D are from zero to
9999, represented by a 14-bit integer located in page 0, registers 5–6. Values should not be written into
these registers that would result in a D value outside the valid range.
Note that whenever the D value is changed, register 5 should be written, immediately followed by register 6. Even if only the MSB or
LSB of the value changes, both registers should be written.
Page 0 / Register 6:
BIT
READ/
WRITE
RESET
VALUE
D7–D2
R/W
0000 00
D1–D0
R
00
PLL Programming Register D
DESCRIPTION
PLL D value – Six least-significant bits of a 14-bit unsigned integer. Valid values for D are from zero to
9999, represented by a 14-bit integer located in page 0, registers 5–6. Values should not be written into
these registers that would result in a D value outside the valid range.
Reserved. Write only zeros to these bits.
Page 0 / Register 7:
Codec Data-Path Setup Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
fS(ref) Setting
This register setting controls timers related to the AGC time constants.
0: fS(ref) = 48 kHz
1: fS(ref) = 44.1 kHz
D6
R/W
0
ADC Dual Rate Control
0: ADC dual-rate mode is disabled.
1: ADC dual-rate mode is enabled.
Note: ADC dual-rate mode must match DAC dual-rate mode.
D5
R/W
0
DAC Dual Rate Control
0: DAC dual rate mode is disabled.
1: DAC dual rate mode is enabled.
D4–D3
R/W
00
Left-DAC Data-Path Control
00: Left-DAC data path is off (muted).
01: Left-DAC data path plays left-channel input data.
10: Left-DAC data path plays right-channel input data.
11: Left-DAC data path plays mono mix of left- and right-channel input data.
D2–D1
R/W
00
Right-DAC Data Path Control
00: Right-DAC data path is off (muted).
01: Right-DAC data path plays right-channel input data.
10: Right-DAC data path plays left-channel input data.
11: Right-DAC data path plays mono mix of left- and right-channel input data.
D0
R/W
0
Reserved. Write only zero to this bit.
54
DESCRIPTION
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Page 0 / Register 8:
Audio Serial Data Interface Control Register A
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Bit Clock Directional Control
0: BCLK_x (or GPIO2_x if programmed as BCLK_x) is an input (slave mode).
1: BCLK_x (or GPIO2_x if programmed as BCLK_x) is an output (master mode).
D6
R/W
0
Word Clock Directional Control
0: WCLK_x (or GPIO1_x if programmed as WCLK_x) is an input (slave mode).
1: WCLK_x (or GPIO1_x if programmed as WCLK_x) is an output (master mode).
D5
R/W
0
Serial Output Data Driver (DOUT_x) 3-State Control
0: Do not place DOUT_x in high-impedance state when valid data is not being sent.
1: Place DOUT_x in high-impedance state when valid data is not being sent.
D4
R/W
0
Bit/ Word Clock Drive Control
DESCRIPTION
0:
BCLK_x (or GPIO2_x if programmed as BCLK_x) / WCLK_x (or GPIO1_x if programmed as
WCLK_x) does not continue to be transmitted when running in master mode if codec is powered
down.
1:
BCLK_x (or GPIO2_x if programmed as BCLK_x) / WCLK_x (or GPIO1_x if programmed as
WCLK_x) continues to be transmitted when running in master mode, even if codec is powered down.
D3
R/W
0
Reserved. Do not write to this register bit.
D2
R/W
0
3-D Effect Control
0: Disable 3-D digital effect processing.
1: Enable 3-D digital effect processing.
D1–D0
R/W
00
Digital Microphone Functionality Control
00: Digital microphone support is disabled.
01: Digital microphone support is enabled with an oversampling rate of 128.
10: Digital microphone support is enabled with an oversampling rate of 64.
11: Digital microphone support is enabled with an oversampling rate of 32.
Page 0 / Register 9:
Audio Serial Data Interface Control Register B
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
Audio Serial Data Interface Transfer Mode
00: Serial data bus uses I2S mode.
01: Serial data bus uses DSP mode.
10: Serial data bus uses right-justified mode.
11: Serial data bus uses left-justified mode.
D5–D4
R/W
00
Audio Serial Data Word Length Control
00: Audio data word length = 16 bits
01: Audio data word length = 20 bits
10: Audio data word length = 24 bits
11: Audio data word length = 32 bits
D3
R/W
0
Bit Clock Rate Control
This register only has effect when bit clock is programmed as an output.
0: Continuous-transfer mode used to determine master-mode bit clock rate
1: 256-clock transfer mode used, resulting in 256 bit clocks per frame
D2
R/W
0
DAC Re-Sync
0: Don’t care
1: Re-sync stereo DAC with codec interface if the group delay changes by more than ±DAC (fS/4).
D1
R/W
0
ADC Re-Sync
0: Don’t care
1: Re-sync stereo ADC with codec interface if the group delay changes by more than ±ADC (fS/4).
D0
R/W
0
Re-Sync Mute Behavior
0: Re-sync is done without soft-muting the channel. (ADC/DAC)
1: Re-sync is done by internally soft-muting the channel. (ADC/DAC)
DESCRIPTION
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Page 0 / Register 10:
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R/W
0000 0000
Audio Serial Data Interface Control Register C
DESCRIPTION
Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling the offset
from the beginning of the frame where valid data begins. The offset is measured from the rising edge of
the word clock when in DSP mode.
0000 0000: Data offset = 0 bit clocks
0000 0001: Data offset = 1 bit clock
0000 0010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode, the maximum offset is 17 for I2S/LJF/RJF modes and 16 for DSP
mode. In 256-clock mode, the maximum offset is 242 for I2S/LJF/RJF and 241 for DSP modes.
1111 1110: Data offset = 254 bit clocks
1111 1111: Data offset = 255 bit clocks
Page 0 / Register 11:
Audio Codec Overflow Flag Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
Left-ADC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
D6
R
0
Right-ADC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
D5
R
0
Left-DAC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
D4
R
0
Right DAC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
D3–D0
R/W
0001
56
DESCRIPTION
PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
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Page 0 / Register 12:
Audio Codec Digital Filter Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
Left-ADC High-Pass Filter Control
00: Left-ADC high-pass filter disabled
01: Left-ADC high-pass filter –3-dB frequency = 0.0045 × ADC fS
10: Left-ADC high-pass filter –3-dB frequency = 0.0125 × ADC fS
11: Left-ADC high-pass filter –3-dB frequency = 0.025 × ADC fS
D5–D4
R/W
00
Right-ADC High-Pass Filter Control
00: Right-ADC high-pass filter disabled
01: Right-ADC high-pass filter –3-dB frequency = 0.0045 × ADC fS
10: Right-ADC high-pass filter –3-dB frequency = 0.0125 × ADC fS
11: Right-ADC high-pass filter –3-dB frequency = 0.025 × ADC fS
D3
R/W
0
Left-DAC Digital Effects Filter Control
0: Left-DAC digital effects filter disabled (bypassed)
1: Left-DAC digital effects filter enabled
D2
R/W
0
Left-DAC De-Emphasis Filter Control
0: Left-DAC de-emphasis filter disabled (bypassed)
1: Left-DAC de-emphasis filter enabled
D1
R/W
0
Right-DAC Digital Effects Filter Control
0: Right-DAC digital effects filter disabled (bypassed)
1: Right-DAC digital effects filter enabled
D0
R/W
0
Right-DAC De-Emphasis Filter Control
0: Right-DAC de-emphasis filter disabled (bypassed)
1: Right-DAC de-emphasis filter enabled
DESCRIPTION
Page 0 / Register 13:
Headset / Button Press Detection Register A
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Headset Detection Control
0: Headset detection disabled
1: Headset detection enabled
D6–D5
R
00
Headset Type Detection Results
00: No headset detected
01: Headset without microphone detected
10: Ignore (reserved)
11: Headset with microphone detected
D4–D2
R/W
000
Headset Glitch Suppression Debounce Control for Jack Detection
000: Debounce = 16 ms (sampled with 2-ms clock)
001: Debounce = 32 ms (sampled with 4-ms clock)
010: Debounce = 64 ms (sampled with 8-ms clock)
011: Debounce = 128 ms (sampled with 16-ms clock)
100: Debounce = 256 ms (sampled with 32-ms clock)
101: Debounce = 512 ms (sampled with 64-ms clock)
110–111: Reserved. Do not write these sequences to these register bits.
D1–D0
R/W
00
Headset Glitch Suppression Debounce Control for Button Press
00: Debounce = 0 ms
01: Debounce = 8 ms (sampled with 1-ms clock)
10: Debounce = 16 ms (sampled with 2-ms clock)
11: Debounce = 32 ms (sampled with 4-ms clock)
DESCRIPTION
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Page 0 / Register 14:
Headset / Button Press Detection Register B
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
D6 (1)
R/W
0
Stereo Output Driver Configuration A
Note: Do not set bits D6 and D3 both high at the same time.
0: A stereo fully-differential output configuration is not being used.
1: A stereo fully-differential output configuration is being used.
D5
R
0
Button Press Detection Flag
This register is a sticky bit, and stays set to 1 after a button press has been detected, until the register is
read. On reading this register, the bit is reset to zero.
0: A button press has not been detected.
1: A button press has been detected.
D4
R
0
Headset Detection Flag
0: A headset has not been detected.
1: A headset has been detected.
D3 (1)
R/W
0
Stereo Output Driver Configuration B
Note: Do not set bits D6 and D3 both high at the same time.
0: A stereo pseudodifferential output configuration is not being used.
1: A stereo pseudodifferential output configuration is being used.
D2–D0
R
000
(1)
DESCRIPTION
Reserved. Write only zeros to these bits.
Do not set D6 and D3 to 1 simultaneously.
Page 0 / Register 15:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
D6–D0
R/W
000 0000
DESCRIPTION
Left-ADC PGA Mute
0: The left-ADC PGA is not muted.
1: The left-ADC PGA is muted.
Left-ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
Page 0 / Register 16:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
D6–D0
R/W
000 0000
58
Left-ADC PGA Gain Control Register
Right-ADC PGA Gain Control Register
DESCRIPTION
Right-ADC PGA Mute
0: The right-ADC PGA is not muted.
1: The right-ADC PGA is muted.
Right-ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
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Page 0 / Register 17:
MIC3L_x and MIC3R_x to Left-ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
1111
MIC3L_x Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3L_x to the
left-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3L_x is not connected to the left-ADC PGA.
D3–D0
R/W
1111
MIC3R_x Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3R_x to the
left-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3R_x is not connected to the left-ADC PGA.
DESCRIPTION
Page 0 / Register 18:
MIC3L_x and MIC3R_x to Right-ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
1111
MIC3L_x Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3L_x to the
right-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3L_x is not connected to the right-ADC PGA.
D3–D0
R/W
1111
MIC3R_x Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects MIC3R_x to the
right-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: MIC3R_x is not connected to the right-ADC PGA.
DESCRIPTION
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Page 0 / Register 19:
LINE1LP_x and LINE1LP_x and LINE1LM_xM_x to Left-ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D3
R/W
1111
D2
R/W
0
Left-ADC Channel Power Control
0: Left-ADC channel is powered down.
1: Left-ADC channel is powered up.
D1–D0
R/W
00
Left-ADC PGA Soft-Stepping Control
00: Left-ADC PGA soft-stepping at once per sample period
01: Left-ADC PGA soft-stepping at once per two ηe periods
10–11: Left-ADC PGA soft-stepping is disabled.
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D3
R/W
1111
D2
R/W
0
Left-ADC Channel Weak Common-Mode Bias Control
0: Left-ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage.
1: Left-ADC channel unselected inputs are biased weakly to the ADC common-mode voltage.
D1–D0
R
00
Reserved. Write only zeros to these register bits.
DESCRIPTION
LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left- and right-ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode.
1: LINE1L is configured in fully differential mode.
LINE1L Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1L to the left-ADC
PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1L is not connected to the left-ADC PGA.
Page 0 / Register 20:
(1)
60
LINE2LP_x and LINE2LM_x to Left-ADC Control Register
DESCRIPTION
LINE2L Single-Ended vs Fully Differential Control (1)
If LINE2L is selected to both left- and right-ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE2L is configured in single-ended mode.
1: LINE2L is configured in fully differential mode.
LINE2L Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE2L to the left-ADC
PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE2L is not connected to the left-ADC PGA.
LINE1R single-ended vs fully differential control is available for both left and right channels. However, this setting must be same for both
the channels.
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Page 0 / Register 21:
LINE1RP_x and LINE1RM_x to Left-ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D3
R/W
1111
LINE1R Input Level Control for Left-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1R to the left-ADC
PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1R is not connected to the left-ADC PGA.
D2–D0
R
000
Reserved. Write only zeros to these register bits.
DESCRIPTION
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left- and right-ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode.
1: LINE1R is configured in fully differential mode.
Page 0 / Register 22:
LINE1RP_x and LINE1RM_x to Right-ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left- and right-ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode.
1: LINE1R is configured in fully differential mode.
D6–D3
R/W
1111
LINE1R Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1R to the
right-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1R is not connected to the right-ADC PGA.
D2
R/W
0
Right-ADC Channel Power Control
0: Right-ADC channel is powered down.
1: Right-ADC channel is powered up.
D1–D0
R/W
00
Right-ADC PGA Soft-Stepping Control
00: Right-ADC PGA soft-stepping at once per sample period
01: Right-ADC PGA soft-stepping at once per two sample periods
10–11: Right-ADC PGA soft-stepping is disabled.
DESCRIPTION
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Page 0 / Register 23:
LINE2RP_x and LINE2RM_x to Right-ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2R Single-Ended vs Fully Differential Control
If LINE2R is selected to both left- and right-ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE2R is configured in single-ended mode.
1: LINE2R is configured in fully differential mode.
D6–D3
R/W
1111
LINE2R Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE2R to the
right-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE2R is not connected to the right-ADC PGA.
D2
R/W
0
Right-ADC Channel Weak Common-Mode Bias Control
0: Right-ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage.
1: Right-ADC channel unselected inputs are biased weakly to the ADC common-mode voltage.
D1–D0
R
00
Reserved. Write only zeros to these register bits.
DESCRIPTION
Page 0 / Register 24:
LINE1LP_x and LINE1LM_x to Right-ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left- and right-ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode.
1: LINE1L is configured in fully differential mode.
D6–D3
R/W
1111
LINE1L Input Level Control for Right-ADC PGA Mix
Setting the input level control to one of the following gains automatically connects LINE1L to the
right-ADC PGA mix.
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits.
1111: LINE1L is not connected to the right-ADC PGA.
D2–D0
R
000
Reserved. Write only zeros to these register bits.
62
DESCRIPTION
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Page 0 / Register 25:
MICBIAS_x Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
MICBIAS_x Level Control
00: MICBIAS_x output is powered down.
01: MICBIAS_x output is powered to 2 V.
10: MICBIAS_x output is powered to 2.5 V.
11: MICBIAS_x output is connected to AVDD.
D5–D4
R/W
00
Digital Microphone Control
00: If digital MIC is enabled, both left and right digital MICs are available.
01: If digital MIC is enabled, left digital MIC and right ADC are available.
10: If digital MIC is enabled, left ADC and right digital MIC are available.
11: Reserved. Do not write this sequence to these register bits.
D3
R
0
Reserved. Do not write to this register bit.
D2–D0
R
XXX
DESCRIPTION
Reserved. Write only zeros to these register bits.
Page 0 / Register 26:
Left-AGC Control Register A
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D4
R/W
000
Left-AGC Target Level
000: Left-AGC target level = –5.5 dB
001: Left-AGC target level = –8 dB
010: Left-AGC target level = –10 dB
011: Left-AGC target level = –12 dB
100: Left-AGC target level = –14 dB
101: Left-AGC target level = –17 dB
110: Left-AGC target level = –20 dB
111: Left-AGC target level = –24 dB
D3–D2
R/W
00
Left-AGC Attack Time
These time constants (1) are not accurate when double-rate audio mode is enabled.
00: Left-AGC attack time = 8 ms
01: Left-AGC attack time = 11 ms
10: Left-AGC attack time = 16 ms
11: Left-AGC attack time = 20 ms
D1–D0
R/W
00
Left-AGC Decay Time
These time constants (1) are not accurate when double-rate audio mode is enabled.
00: Left-AGC decay time = 100 ms
01: Left-AGC decay time = 200 ms
10: Left-AGC decay time = 400 ms
11: Left-AGC decay time = 500 ms
(1)
DESCRIPTION
Left-AGC Enable
0: Left AGC is disabled.
1: Left AGC is enabled.
Time constants are valid when double-rate audio is not enabled. The values would change if double-rate audio is enabled.
Page 0 / Register 27:
BIT
READ/
WRITE
RESET
VALUE
D7–D1
R/W
1111 111
D0
R/W
0
Left-AGC Control Register B
DESCRIPTION
Left-AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111–1111 111: Maximum gain = 59.5 dB
Reserved. Write only zero to this register bit.
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Page 0 / Register 28:
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
D5–D1
R/W
00 000
D0
R/W
0
DESCRIPTION
Noise Gate Hysteresis Level Control
00: Hysteresis = 1 dB
01: Hysteresis = 2 dB
10: Hysteresis = 3 dB
11: Hysteresis is disabled.
Left-AGC Noise Threshold Control
00 000: Left-AGC noise/silence detection disabled
00 001: Left-AGC noise threshold = –30 dB
00 010: Left-AGC noise threshold = –32 dB
00 011: Left-AGC noise threshold = –34 dB
…
11 101: Left-AGC noise threshold = –86 dB
11 110: Left-AGC noise threshold = –88 dB
11 111: Left-AGC noise threshold = –90 dB
Left-AGC Clip Stepping Control
0: Left-AGC clip stepping disabled
1: Left-AGC clip stepping enabled
Page 0 / Register 29:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D4
R/W
000
Left-AGC Control Register C
Right-AGC Control Register A
DESCRIPTION
Right-AGC Enable
0: Right AGC is disabled.
1: Right AGC is enabled.
Right-AGC Target Level
000: Right-AGC target level
001: Right-AGC target level
010: Right-AGC target level
011: Right-AGC target level
100: Right-AGC target level
101: Right-AGC target level
110: Right-AGC target level
111: Right-AGC target level
= –5.5 dB
= –8 dB
= –10 dB
= –12 dB
= –14 dB
= –17 dB
= –20 dB
= –24 dB
D3–D2
R/W
00
Right-AGC Attack Time
These time constants are not accurate when double-rate audio mode is enabled.
00: Right-AGC attack time = 8 ms
01: Right-AGC attack time = 11 ms
10: Right-AGC attack time = 16 ms
11: Right-AGC attack time = 20 ms
D1–D0
R/W
00
Right-AGC Decay Time
These time constants are not accurate when double-rate audio mode is enabled.
00: Right-AGC decay time = 100 ms
01: Right-AGC decay time = 200 ms
10: Right-AGC decay time = 400 ms
11: Right-AGC decay time = 500 ms
Page 0 / Register 30:
BIT
READ/
WRITE
RESET
VALUE
D7–D1
R/W
1111 111
D0
R/W
0
64
Right-AGC Control Register B
DESCRIPTION
Right-AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111–1111 111: Maximum gain = 59.5 dB
Reserved. Write only zero to this register bit.
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Page 0 / Register 31:
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
D5–D1
R/W
00 000
D0
R/W
0
Right-AGC Control Register C
DESCRIPTION
Noise Gate Hysteresis Level Control
00: Hysteresis = 1 dB
01: Hysteresis = 2 dB
10: Hysteresis = 3 dB
11: Hysteresis is disabled.
Right-AGC Noise Threshold Control
00 000: Right-AGC noise/silence detection disabled
00 001: Right-AGC noise threshold = –30 dB
00 010: Right-AGC noise threshold = –32 dB
00 011: Right-AGC noise threshold = –34 dB
…
11 101: Right-AGC noise threshold = –86 dB
11 110: Right-AGC noise threshold = –88 dB
11 111: Right-AGC noise threshold = –90 dB
Right-AGC Clip Stepping Control
0: Right-AGC clip stepping disabled
1: Right-AGC clip stepping enabled
Page 0 / Register 32:
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
DESCRIPTION
Left-Channel Gain Applied by AGC Algorithm
1110 1000: Gain = –12 dB
1110 1001: Gain = –11.5 dB
1110 1010: Gain = –11 dB
…
0000 0000: Gain = 0 dB
0000 0001: Gain = 0.5 dB
…
0111 0110: Gain = 59 dB
0111 0111: Gain = 59.5 dB
Page 0 / Register 33:
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
Left-AGC Gain Register
Right-AGC Gain Register
DESCRIPTION
Right-Channel Gain Applied by AGC Algorithm
1110 1000: Gain = –12 dB
1110 1001: Gain = –11.5 dB
1110 1010: Gain = –11 dB
…
0000 0000: Gain = 0 dB
0000 0001: Gain = 0.5 dB
…
0111 0110: Gain = 59 dB
0111 0111: Gain = 59.5 dB
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Page 0 / Register 34:
Left-AGC Noise Gate Debounce Register
BIT
READ/
WRITE
RESET
VALUE
D7–D3
R/W
0000 0
Left-AGC Noise Detection Debounce Control
These times (1) are not accurate when double-rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1,472 ms
1111 1: Debounce = 64 × 24 = 1,536 ms
D2–D0
R/W
000
Left-AGC Signal Detection Debounce Control
These times (1) are not accurate when double-rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
(1)
DESCRIPTION
Time constants are valid when double-rate audio is not enabled. The values change when double-rate audio is enabled.
Page 0 / Register 35:
Right-AGC Noise Gate Debounce Register
BIT
READ/
WRITE
RESET
VALUE
D7–D3
R/W
0000 0
Right-AGC Noise Detection Debounce Control
These times (1) are not accurate when double-rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1,472 ms
1111 1: Debounce = 64 × 24 = 1,536 ms
D2–D0
R/W
000
Right-AGC Signal Detection Debounce Control
These times (1) are not accurate when double-rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
(1)
66
DESCRIPTION
Time constants are valid when DRA is not enabled. The values change when DRA is enabled.
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Page 0 / Register 36:
ADC Flag Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
Left-ADC PGA Status
0: Applied gain and programmed gain are not the same.
1: Applied gain = programmed gain
D6
R
0
Left-ADC Power Status
0: Left ADC is in a power-down state.
1: Left ADC is in a power-up state.
D5
R
0
Left-AGC Signal Detection Status
0: Signal power is greater than noise threshold.
1: Signal power is less than noise threshold.
D4
R
0
Left-AGC Saturation Flag
0: Left AGC is not saturated.
1: Left-AGC gain applied = maximum allowed gain for left AGC
D3
R
0
Right-ADC PGA Status
0: Applied gain and programmed gain are not the same.
1: Applied gain = programmed gain
D2
R
0
Right-ADC Power Status
0: Right ADC is in a power-down state.
1: Right ADC is in a power-up state.
D1
R
0
Right-AGC Signal Detection Status
0: Signal power is greater than noise threshold.
1: Signal power is less than noise threshold.
D0
R
0
Right-AGC Saturation Flag
0: Right AGC is not saturated.
1: Right-AGC gain applied = maximum allowed gain for right AGC
DESCRIPTION
Page 0 / Register 37:
DAC Power and Output Driver Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Left-DAC Power Control
0: Left DAC is not powered up.
1: Left DAC is powered up.
D6
R/W
0
Right-DAC Power Control
0: Right DAC is not powered up.
1: Right DAC is powered up.
D5–D4
R/W
00
HPLCOM_x Output Driver Configuration Control
00: HPLCOM_x configured as differential of HPLOUT_x
01: HPLCOM_x configured as constant VCM output
10: HPLCOM_x configured as independent single-ended output
11: Reserved. Do not write this sequence to these register bits.
D3–D0
R
0000
DESCRIPTION
Reserved. Write only zeros to these register bits.
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Page 0 / Register 38:
BIT
READ/
WRITE
High-Power Output Driver Control Register
RESET
VALUE
DESCRIPTION
D7–D6
R
00
Reserved. Write only zeros to these register bits.
D5–D3
R/W
000
HPRCOM_x Output Driver Configuration Control
000: HPRCOM_x configured as differential of HPROUT_x
001: HPRCOM_x configured as constant VCM output
010: HPRCOM_x configured as independent single-ended output
011: HPRCOM_x configured as differential of HPLCOM_x
100: HPRCOM_x configured as external feedback with HPLCOM_x as constant VCM output
101–111: Reserved. Do not write these sequences to these register bits.
D2
R/W
0
Short-Circuit Protection Control
0: Short-circuit protection on all high-power output drivers is disabled.
1: Short-circuit protection on all high-power output drivers is enabled.
D1
R/W
0
Short-Circuit Protection-Mode Control
D0
R
0
0:
If short-circuit protection is enabled, it limits the maximum current to the load.
1:
If short-circuit protection is enabled, it powers down the output driver automatically when a short is
detected.
Reserved. Write only zero to this register bit.
Page 0 / Register 39:
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
Reserved Register
DESCRIPTION
Reserved. Do not write to this register.
Page 0 / Register 40:
High-Power Output Stage Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
Output Common-Mode Voltage Control
00: Output common-mode voltage = 1.35 V
01: Output common-mode voltage = 1.5 V
10: Output common-mode voltage = 1.65 V
11: Output common-mode voltage = 1.8 V
D5–D4
R/W
00
LINE2L Bypass Path Control
00: LINE2L bypass is disabled.
01: LINE2L bypass uses LINE2LP_x single-ended.
10: LINE2L bypass uses LINE2LM_x single-ended.
11: LINE2L bypass uses LINE2LP_x and LINE2LM_x differentially.
D3–D2
R/W
00
LINE2R Bypass Path Control
00: LINE2R bypass is disabled.
01: LINE2R bypass uses LINE2RP_x single-ended.
10: LINE2R bypass uses LINE2RM_x single-ended.
11: LINE2R bypass uses LINE2RP_x and LINE2RM_x differentially.
D1–D0
R/W
00
Output Volume Control Soft-Stepping
00: Output soft-stepping = one step per sample period
01: Output soft-stepping = one step per two sample periods
10: Output soft-stepping disabled
11: Reserved. Do not write this sequence to these register bits.
68
DESCRIPTION
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Page 0 / Register 41:
DAC Output Switching Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
Left-DAC Output Switching Control
00: Left-DAC output selects DAC_L1 path.
01: Left-DAC output selects DAC_L3 path to left line output driver.
10: Left-DAC output selects DAC_L2 path to left high-power output drivers.
11: Reserved. Do not write this sequence to these register bits.
D5–D4
R/W
00
Right-DAC Output Switching Control
00: Right-DAC output selects DAC_R1 path.
01: Right-DAC output selects DAC_R3 path to right line output driver.
10: Right-DAC output selects DAC_R2 path to right high-power output drivers.
11: Reserved. Do not write this sequence to these register bits.
D3–D2
R/W
00
Reserved. Write only zeros to these bits.
D1–D0
R/W
00
DAC Digital Volume Control Functionality
00: Left- and right-DAC channels have independent volume controls.
01: Left-DAC volume follows the right-channel control register.
10: Right-DAC volume follows the left-channel control register.
11: Left- and right-DAC channels have independent volume controls (same as 00).
DESCRIPTION
Page 0 / Register 42:
Output Driver Pop Reduction Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3–D2
R/W
00
Driver Ramp-Up Step Timing Control
00: Driver ramp-up step time = 0 ms
01: Driver ramp-up step time = 1 ms
10: Driver ramp-up step time = 2 ms
11: Driver ramp-up step time = 4 ms
D1
R/W
0
Weak Output Common-Mode Voltage Control
0: Weakly driven output common-mode voltage is generated from resistor divider off the AVDD supply.
1: Weakly driven output common-mode voltage is generated from band-gap reference.
D0
R/W
0
Reserved. Write only zero to this register bit.
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
D6–D0
R/W
000 0000
DESCRIPTION
Output Driver Power-On Delay Control
0000: Driver power-on time = 0 µs
0001: Driver power-on time = 10 µs
0010: Driver power-on time = 100 µs
0011: Driver power-on time = 1 ms
0100: Driver power-on time = 10 ms
0101: Driver power-on time = 50 ms
0110: Driver power-on time = 100 ms
0111: Driver power-on time = 200 ms
1000: Driver power-on time = 400 ms
1001: Driver power-on time = 800 ms
1010: Driver power-on time = 2 s
1011: Driver power-on time = 4 s
1100–1111: Reserved. Do not write these sequences to these register bits.
Page 0 / Register 43:
Left-DAC Digital Volume Control Register
DESCRIPTION
Left-DAC Digital Mute
0: The left-DAC channel is not muted.
1: The left-DAC channel is muted.
Left-DAC Digital Volume Control Setting
000 0000: Gain = 0 dB
000 0001: Gain = –0.5 dB
000 0010: Gain = –1 dB
…
111 1101: Gain = –62.5 dB
111 1110: Gain = –63 dB
111 1111: Gain = –63.5 dB
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Page 0 / Register 44:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
1
D6–D0
R/W
000 0000
70
Right-DAC Digital Volume Control Register
DESCRIPTION
Right-DAC Digital Mute
0: The right-DAC channel is not muted.
1: The right-DAC channel is muted.
Right-DAC Digital Volume Control Setting
000 0000: Gain = 0 dB
000 0001: Gain = –0.5 dB
000 0010: Gain = –1 dB
…
111 1101: Gain = –62.5 dB
111 1110: Gain = –63 dB
111 1111: Gain = –63.5 dB
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Output Stage Volume Controls
A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output
stage network, connected to each of the analog signals that route to the output stage. In addition, to enable
completely independent mixing operations to be performed for each output driver, each analog signal coming into
the output stage may have up to seven separate volume controls. These volume controls all have approximately
0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations.
Table 7 lists the detailed gain versus programmed setting for this basic volume control.
Table 7. Output Stage Volume Control Settings and Gains
Gain Setting
Analog Gain
(dB)
Gain Setting
0
0
30
1
–0.5
31
2
–1
32
3
–1.5
33
4
–2
5
–2.5
6
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
–15
60
–30.1
90
–45.2
–15.5
61
–30.6
91
–45.8
–16
62
–31.1
92
–46.2
–16.5
63
–31.6
93
–46.7
34
–17
64
–32.1
94
–47.4
35
–17.5
65
–32.6
95
–47.9
–3
36
–18
66
–33.1
96
–48.2
7
–3.5
37
–18.6
67
–33.6
97
–48.7
8
–4
38
–19.1
68
–34.1
98
–49.3
9
–4.5
39
–19.6
69
–34.6
99
–50
10
–5
40
–20.1
70
–35.1
100
11
–5.5
41
–20.6
71
–35.7
101
–51
12
–6
42
–21.1
72
–36.1
102
–51.4
13
–6.5
43
–21.6
73
–36.7
103
–51.8
14
–7
44
–22.1
74
–37.1
104
–52.2
15
–7.5
45
–22.6
75
–37.7
105
–52.7
16
–8
46
–23.1
76
–38.2
106
–53.7
17
–8.5
47
–23.6
77
–38.7
107
–54.2
18
–9
48
–24.1
78
–39.2
108
–55.3
19
–9.5
49
–24.6
79
–39.7
109
–56.7
20
–10
50
–25.1
80
–40.2
110
–58.3
21
–10.5
51
–25.6
81
–40.7
111
–60.2
22
–11
52
–26.1
82
–41.2
112
–62.7
23
–11.5
53
–26.6
83
–41.7
113
–64.3
24
–12
54
–27.1
84
–42.2
114
–66.2
25
–12.5
55
–27.6
85
–42.7
115
–68.7
26
–13
56
–28.1
86
–43.2
116
–72.2
27
–13.5
57
–28.6
87
–43.8
117
–78.3
28
–14
58
–29.1
88
–44.3
118–127
Mute
29
–14.5
59
–29.6
89
–44.8
Page 0 / Register 45:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Analog Gain
(dB)
–50.3
LINE2LP_x and LINE2LM_x to HPLOUT_x Volume Control Register
DESCRIPTION
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to HPLOUT_x.
1: LINE2LP_x and LINE2LM_x is routed to HPLOUT_x.
LINE2LP_x and LINE2LM_x to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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Page 0 / Register 46:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
PGA_LP_x and PGA_LM_x to HPLOUT_x Volume Control Register
DESCRIPTION
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to HPLOUT_x.
1: PGA_LP_x and PGA_LM_x is routed to HPLOUT_x.
PGA_LP_x and PGA_LM_x to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 47:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLOUT_x.
1: DAC_L1 is routed to HPLOUT_x.
DAC_L1 to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 48:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2RP_x and LINE2RM_x to HPLOUT_x Volume Control Register
DESCRIPTION
LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to HPLOUT_x.
1: LINE2RP_x and LINE2RM_x is routed to HPLOUT_x.
LINE2RP_x and LINE2RM_x to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 49:
BIT
DAC_L1 to HPLOUT_x Volume Control Register
PGA_RP_x and PGA_RM_x to HPLOUT_x Volume Control Register
DESCRIPTION
PGA_RP_x and PGA_RM_x Output Routing Control
0: PGA_RP_x and PGA_RM_x is not routed to HPLOUT_x.
1: PGA_RP_x and PGA_RM_x is routed to HPLOUT_x.
PGA_RP_x and PGA_RM_x to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 50: DAC_R1 to HPLOUT_x Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
72
DESCRIPTION
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLOUT_x.
1: DAC_R1 is routed to HPLOUT_x.
DAC_R1 to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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Page 0 / Register 51:
HPLOUT_x Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
HPLOUT_x Mute
0: HPLOUT_x is muted.
1: HPLOUT_x is not muted.
D2
R/W
1
HPLOUT_x Power Down Drive Control
0: HPLOUT_x is weakly driven to a common mode when powered down.
1: HPLOUT_x is high-impedance when powered down.
D1
R
1
HPLOUT_x Volume Control Status
0: All programmed gains to HPLOUT_x have been applied.
1: Not all programmed gains to HPLOUT_x have been applied yet.
D0
R/W
0
HPLOUT_x Power Control
0: HPLOUT_x is not fully powered up.
1: HPLOUT_x is fully powered up.
DESCRIPTION
HPLOUT_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
Page 0 / Register 52:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to HPLCOM_x.
1: LINE2LP_x and LINE2LM_x is routed to HPLCOM_x.
LINE2LP_x and LINE2LM_x to HPLCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 53:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2LP_x and LINE2LM_x to HPLCOM_x Volume Control Register
PGA_LP_x and PGA_LM_x to HPLCOM_x Volume Control Register
DESCRIPTION
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to HPLCOM_x.
1: PGA_LP_x and PGA_LM_x is routed to HPLCOM_x.
PGA_LP_x and PGA_LM_x to HPLCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 54:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DAC_L1 to HPLCOM_x Volume Control Register
DESCRIPTION
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLCOM_x.
1: DAC_L1 is routed to HPLCOM_x.
DAC_L1 to HPLCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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Page 0 / Register 55:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to HPLCOM_x.
1: LINE2RP_x and LINE2RM_x is routed to HPLCOM_x.
LINE2RP_x and LINE2RM_x to HPLCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 56:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2RP_x and LINE2RM_x to HPLCOM_x Volume Control Register
PGA_RP_x and PGA_RM_x to HPLCOM_x Volume Control Register
DESCRIPTION
PGA_RP_x and PGA_RM_x Output Routing Control
0: PGA_RP_x and PGA_RM_x is not routed to HPLCOM_x.
1: PGA_RP_x and PGA_RM_x is routed to HPLCOM_x.
PGA_RP_x and PGA_RM_x to HPLCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 57:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DAC_R1 to HPLCOM_x Volume Control Register
DESCRIPTION
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLCOM_x.
1: DAC_R1 is routed to HPLCOM_x.
DAC_R1 to HPLCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 58:
HPLCOM_x Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
HPLCOM_x Mute
0: HPLCOM_x is muted.
1: HPLCOM_x is not muted.
D2
R/W
1
HPLCOM_x Power-Down Drive Control
0: HPLCOM_x is weakly driven to a common mode when powered down.
1: HPLCOM_x is high-impedance when powered down.
D1
R
1
HPLCOM_x Volume Control Status
0: All programmed gains to HPLCOM_x have been applied.
1: Not all programmed gains to HPLCOM_x have been applied yet.
D0
R/W
0
HPLCOM_x Power Control
0: HPLCOM_x is not fully powered up.
1: HPLCOM_x is fully powered up.
74
DESCRIPTION
HPLCOM_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
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Page 0 / Register 59:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to HPROUT_x.
1: LINE2LP_x and LINE2LM_x is routed to HPROUT_x.
LINE2LP_x and LINE2LM_x to HPROUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 60:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2LP_x and LINE2LM_x to HPROUT_x Volume Control Register
PGA_LP_x and PGA_LM_x to HPROUT_x Volume Control Register
DESCRIPTION
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to HPROUT_x.
1: PGA_LP_x and PGA_LM_x is routed to HPROUT_x.
PGA_LP_x and PGA_LM_x to HPROUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 61:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPROUT_x.
1: DAC_L1 is routed to HPROUT_x.
DAC_L1 to HPROUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 62:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2RP_x and LINE2RM_x to HPROUT_x Volume Control Register
DESCRIPTION
LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to HPROUT_x.
1: LINE2RP_x and LINE2RM_x is routed to HPROUT_x.
LINE2RP_x and LINE2RM_x to HPROUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 63:
BIT
PGA_RP_x and PGA_RM_x to HPROUT_x Volume Control Register
DESCRIPTION
PGA_RP_x and PGA_RM_x Output Routing Control
0: PGA_RP_x and PGA_RM_x is not routed to HPROUT_x.
1: PGA_RP_x and PGA_RM_x is routed to HPROUT_x.
PGA_RP_x and PGA_RM_x to HPROUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 64:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DAC_L1 to HPROUT_x Volume Control Register
DAC_R1 to HPROUT_x Volume Control Register
DESCRIPTION
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPROUT_x.
1: DAC_R1 is routed to HPROUT_x.
DAC_R1 to HPROUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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Page 0 / Register 65:
HPROUT_x Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
HPROUT_x Mute
0: HPROUT_x is muted.
1: HPROUT_x is not muted.
D2
R/W
1
HPROUT_x Power-Down Drive Control
0: HPROUT_x is weakly driven to a common mode when powered down.
1: HPROUT_x is high-impedance when powered down.
D1
R
1
HPROUT_x Volume Control Status
0: All programmed gains to HPROUT_x have been applied.
1: Not all programmed gains to HPROUT_x have been applied yet.
D0
R/W
0
HPROUT_x Power Control
0: HPROUT_x is not fully powered up.
1: HPROUT_x is fully powered up.
DESCRIPTION
HPROUT_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
Page 0 / Register 66:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to HPRCOM_x.
1: LINE2LP_x and LINE2LM_x is routed to HPRCOM_x.
LINE2LP_x and LINE2LM_x to HPRCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 67:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2LP_x and LINE2LM_x to HPRCOM_x Volume Control Register
PGA_LP_x and PGA_LM_x to HPRCOM_x Volume Control Register
DESCRIPTION
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to HPRCOM_x.
1: PGA_LP_x and PGA_LM_x is routed to HPRCOM_x.
PGA_LP_x and PGA_LM_x to HPRCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 68:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
76
DAC_L1 to HPRCOM_x Volume Control Register
DESCRIPTION
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPRCOM_x.
1: DAC_L1 is routed to HPRCOM_x.
DAC_L1 to HPRCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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Page 0 / Register 69:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to HPRCOM_x.
1: LINE2RP_x and LINE2RM_x is routed to HPRCOM_x.
LINE2RP_x and LINE2RM_x to HPRCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 70:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2RP_x and LINE2RM_x to HPRCOM_x Volume Control Register
PGA_RP_x and PGA_RM_x to HPRCOM_x Volume Control Register
DESCRIPTION
PGA_RP_x and PGA_RM_x Output Routing Control
0: PGA_RP_x and PGA_RM_x is not routed to HPRCOM_x.
1: PGA_RP_x and PGA_RM_x is routed to HPRCOM_x.
PGA_RP_x and PGA_RM_x to HPRCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 71:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DAC_R1 to HPRCOM_x Volume Control Register
DESCRIPTION
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPRCOM_x.
1: DAC_R1 is routed to HPRCOM_x.
DAC_R1 to HPRCOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 72:
HPRCOM_x Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
HPRCOM_x Mute
0: HPRCOM_x is muted.
1: HPRCOM_x is not muted.
D2
R/W
1
HPRCOM_x Power-Down Drive Control
0: HPRCOM_x is weakly driven to a common mode when powered down.
1: HPRCOM_x is high-impedance when powered down.
D1
R
1
HPRCOM_x Volume Control Status
0: All programmed gains to HPRCOM_x have been applied.
1: Not all programmed gains to HPRCOM_x have been applied yet.
D0
R/W
0
HPRCOM_x Power Control
0: HPRCOM_x is not fully powered up.
1: HPRCOM_x is fully powered up.
DESCRIPTION
HPRCOM_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
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Page 0 / Register 73:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 74:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2LP_x and LINE2LM_x to MONO_LOP_x and MONO_LOM_x Volume Control
Register
DESCRIPTION
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to MONO_LOP_x and MONO_LOM_x.
1: LINE2LP_x and LINE2LM_x is routed to MONO_LOP_x and MONO_LOM_x.
LINE2LP_x and LINE2LM_x to MONO_LOP_x and MONO_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
PGA_LP_x and PGA_LM_x to MONO_LOP_x and MONO_LOM_x Volume Control
Register
DESCRIPTION
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to MONO_LOP_x and MONO_LOM_x.
1: PGA_LP_x and PGA_LM_x is routed to MONO_LOP_x and MONO_LOM_x.
PGA_LP_x and PGA_LM_x to MONO_LOP_x and MONO_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 75:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 76:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 77:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
78
DAC_L1 to MONO_LOP_x and MONO_LOM_x Volume Control Register
DESCRIPTION
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to MONO_LOP_x and MONO_LOM_x.
1: DAC_L1 is routed to MONO_LOP_x and MONO_LOM_x.
DAC_L1 to MONO_LOP_x and MONO_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
LINE2RP_x and LINE2RM_x to MONO_LOP_x and MONO_LOM_x Volume Control
Register
DESCRIPTION
LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to MONO_LOP_x and MONO_LOM_x.
1: LINE2RP_x and LINE2RM_x is routed to MONO_LOP_x and MONO_LOM_x.
LINE2RP_x and LINE2RM_x to MONO_LOP_x and MONO_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
PGA_RP_x and PGA_RM_x to MONO_LOP_x and MONO_LOM_x Volume Control
Register
DESCRIPTION
PGA_RP_x and PGA_RM_x Output Routing Control
0: PGA_RP_x and PGA_RM_x is not routed to MONO_LOP_x and MONO_LOM_x.
1: PGA_RP_x and PGA_RM_x is routed to MONO_LOP_x and MONO_LOM_x.
PGA_RP_x and PGA_RM_x to MONO_LOP_x and MONO_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 78:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DAC_R1 to MONO_LOP_x and MONO_LOM_x Volume Control Register
DESCRIPTION
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to MONO_LOP_x and MONO_LOM_x.
1: DAC_R1 is routed to MONO_LOP_x and MONO_LOM_x.
DAC_R1 to MONO_LOP_x and MONO_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 79:
MONO_LOP_x and MONO_LOM_x Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
MONO_LOP_x and MONO_LOM_x Mute
0: MONO_LOP_x and MONO_LOM_x is muted.
1: MONO_LOP_x and MONO_LOM_x is not muted.
D2
R
0
Reserved. Do not write to this register bit.
D1
R
1
MONO_LOP_x and MONO_LOM_x Volume Control Status
0: All programmed gains to MONO_LOP_x and MONO_LOM_x have been applied.
1: Not all programmed gains to MONO_LOP_x and MONO_LOM_x have been applied yet.
D0
R
0
MONO_LOP_x and MONO_LOM_x Power Status
0: MONO_LOP_x and MONO_LOM_x is not fully powered up.
1: MONO_LOP_x and MONO_LOM_x is fully powered up.
Page 0 / Register 80:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 81:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
MONO_LOP_x and MONO_LOM_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
LINE2LP_x and LINE2LM_x to LEFT_LOP_x and LEFT_LOM_x Volume Control
Register
DESCRIPTION
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to LEFT_LOP_x and LEFT_LOM_x.
1: LINE2LP_x and LINE2LM_x is routed to LEFT_LOP_x and LEFT_LOM_x.
LINE2LP_x and LINE2LM_x to LEFT_LOP_x and LEFT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
PGA_LP_x and PGA_LM_x to LEFT_LOP_x and LEFT_LOM_x Volume Control
Register
DESCRIPTION
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to LEFT_LOP_x and LEFT_LOM_x.
1: PGA_LP_x and PGA_LM_x is routed to LEFT_LOP_x and LEFT_LOM_x.
PGA_LP_x and PGA_LM_x to LEFT_LOP_x and LEFT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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Page 0 / Register 82:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 83:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 84:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to LEFT_LOP_x and LEFT_LOM_x.
1: DAC_L1 is routed to LEFT_LOP_x and LEFT_LOM_x.
DAC_L1 to LEFT_LOP_x and LEFT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
LINE2RP_x and LINE2RM_x to LEFT_LOP_x and LEFT_LOM_x Volume Control
Register
DESCRIPTION
LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to LEFT_LOP_x and LEFT_LOM_x.
1: LINE2RP_x and LINE2RM_x is routed to LEFT_LOP_x and LEFT_LOM_x.
LINE2RP_x and LINE2RM_x to LEFT_LOP_x and LEFT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
PGA_RP_x and PGA_RM_x to LEFT_LOP_x and LEFT_LOM_x Volume Control
Register
DESCRIPTION
PGA_RP_x and PGA_RM_x Output Routing Control
0: PGA_RP_x and PGA_RM_x is not routed to LEFT_LOP_x and LEFT_LOM_x.
1: PGA_RP_x and PGA_RM_x is routed to LEFT_LOP_x and LEFT_LOM_x.
PGA_RP_x and PGA_RM_x to LEFT_LOP_x and LEFT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 85:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
80
DAC_L1 to LEFT_LOP_x and LEFT_LOM_x Volume Control Register
DAC_R1 to LEFT_LOP_x and LEFT_LOM_x Volume Control Register
DESCRIPTION
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to LEFT_LOP_x and LEFT_LOM_x.
1: DAC_R1 is routed to LEFT_LOP_x and LEFT_LOM_x.
DAC_R1 to LEFT_LOP_x and LEFT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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Page 0 / Register 86:
LEFT_LOP_x and LEFT_LOM_x Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
LEFT_LOP_x and LEFT_LOM_x Mute
0: LEFT_LOP_x and LEFT_LOM_x is muted.
1: LEFT_LOP_x and LEFT_LOM_x is not muted.
D2
R
0
Reserved. Do not write to this register bit.
D1
R
1
LEFT_LOP_x and LEFT_LOM_x Volume Control Status
0: All programmed gains to LEFT_LOP_x and LEFT_LOM_x have been applied.
1: Not all programmed gains to LEFT_LOP_x and LEFT_LOM_x have been applied yet.
D0
R
0
LEFT_LOP_x and LEFT_LOM_x Power Status
0: LEFT_LOP_x and LEFT_LOM_x is not fully powered up.
1: LEFT_LOP_x and LEFT_LOM_x is fully powered up.
Page 0 / Register 87:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 88:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DESCRIPTION
LEFT_LOP_x and LEFT_LOM_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
LINE2LP_x and LINE2LM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
DESCRIPTION
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: LINE2LP_x and LINE2LM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
LINE2LP_x and LINE2LM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
PGA_LP_x and PGA_LM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
DESCRIPTION
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: PGA_LP_x and PGA_LM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
PGA_LP_x and PGA_LM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 89:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DAC_L1 to RIGHT_LOP_x and RIGHT_LOM_x Volume Control Register
DESCRIPTION
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: DAC_L1 is routed to RIGHT_LOP_x and RIGHT_LOM_x.
DAC_L1 to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 90:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
Page 0 / Register 91:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
LINE2RP_x and LINE2RM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
DESCRIPTION
LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: LINE2RP_x and LINE2RM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
LINE2RP_x and LINE2RM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
PGA_RP_x and PGA_RM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
DESCRIPTION
PGA_RP_x and PGA_RM_x Output Routing Control
0:PGA_RP_x and PGA_RM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1:PGA_RP_x and PGA_RM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
PGA_RP_x and PGA_RM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 92:
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
D6–D0
R/W
000 0000
DAC_R1 to RIGHT_LOP_x and RIGHT_LOM_x Volume Control Register
DESCRIPTION
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: DAC_R1 is routed to RIGHT_LOP_x and RIGHT_LOM_x.
DAC_R1 to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7.
Page 0 / Register 93:
RIGHT_LOP_x and RIGHT_LOM_x Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
RIGHT_LOP_x and RIGHT_LOM_x Mute
0: RIGHT_LOP_x and RIGHT_LOM_x is muted.
1: RIGHT_LOP_x and RIGHT_LOM_x is not muted.
D2
R
0
Reserved. Do not write to this register bit.
D1
R
1
RIGHT_LOP_x and RIGHT_LOM_x Volume Control Status
0: All programmed gains to RIGHT_LOP_x and RIGHT_LOM_x have been applied.
1: Not all programmed gains to RIGHT_LOP_x and RIGHT_LOM_x have been applied yet.
D0
R
0
RIGHT_LOP_x and RIGHT_LOM_x Power Status
0: RIGHT_LOP_x and RIGHT_LOM_x is not fully powered up.
1: RIGHT_LOP_x and RIGHT_LOM_x is fully powered up.
82
DESCRIPTION
RIGHT_LOP_x and RIGHT_LOM_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 94:
Module Power-Status Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
Left-DAC Power Status
0:Left DAC is not fully powered up.
1: Left DAC is fully powered up.
D6
R
0
Right-DAC Power Status
0: Right DAC is not fully powered up.
1: Right DAC is fully powered up.
D5
R
0
MONO_LOP_x and MONO_LOM_x Power Status
0: MONO_LOP_x and MONO_LOM_x output driver is powered down.
1: MONO_LOP_x and MONO_LOM_x output driver is powered up.
D4
R
0
LEFT_LOP_x and LEFT_LOM_x Power Status
0: LEFT_LOP_x and LEFT_LOM_x output driver is powered down.
1: LEFT_LOP/M_ output driver is powered up.
D3
R
0
RIGHT_LOP_x and RIGHT_LOM_x Power Status
0:RIGHT_LOP_x and RIGHT_LOM_x is not fully powered up.
1: RIGHT_LOP_x and RIGHT_LOM_x is fully powered up.
D2
R
0
HPLOUT_x Driver Power Status
0: HPLOUT_x driver is not fully powered up.
1: HPLOUT_x driver is fully powered up.
D1
R
0
HPROUT_x Driver Power Status
0: HPROUT_x Driver is not fully powered up.
1: HPROUT_x Driver is fully powered up.
D0
R
0
Reserved. Do not write to this register bit.
DESCRIPTION
Page 0 / Register 95:
Output Driver Short-Circuit Detection Status Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
HPLOUT_x Short-Circuit Detection Status
0: No short circuit detected at HPLOUT_x
1: Short circuit detected at HPLOUT_x
D6
R
0
HPROUT_x Short-Circuit Detection Status
0: No short circuit detected at HPROUT_x
1: Short circuit detected at HPROUT_x
D5
R
0
HPLCOM_x Short-Circuit Detection Status
0: No short circuit detected at HPLCOM_x
1: Short circuit detected at HPLCOM_x
D4
R
0
HPRCOM_x Short-Circuit Detection Status
0: No short circuit detected at HPRCOM_x
1: Short circuit detected at HPRCOM_x
D3
R
0
HPLCOM_x Power Status
0: HPLCOM_x is not fully powered up.
1: HPLCOM_x is fully powered up.
D2
R
0
HPRCOM_x Power Status
0: HPRCOM_x is not fully powered up.
1: HPRCOM_x is fully powered up.
D1–D0
R
00
Reserved. Do not write to these register bits.
DESCRIPTION
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 96:
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
HPLOUT_x Short-Circuit Detection Status
0: No short circuit detected at HPLOUT_x driver
1: Short circuit detected at HPLOUT_x driver
D6
R
0
HPROUT_x Short-Circuit Detection Status
0: No short circuit detected at HPROUT_x driver
1: Short circuit detected at HPROUT_x driver
D5
R
0
HPLCOM_x Short-Circuit Detection Status
0: No short circuit detected at HPLCOM_x driver
1: Short circuit detected at HPLCOM_x driver
D4
R
0
HPRCOM_x Short-Circuit Detection Status
0: No short circuit detected at HPRCOM_x driver
1: Short circuit detected at HPRCOM_x driver
D3
R
0
Button Press Detection Status
0: No headset button press detected
1: Headset button pressed
D2
R
0
Headset Detection Status
0: No headset insertion/removal is detected.
1: Headset insertion/removal is detected.
D1
R
0
Left-ADC AGC Noise Gate Status
0: Left-ADC signal power greater than noise threshold for left AGC
1: Left-ADC signal power lower than noise threshold for left AGC
D0
R
0
Right-ADC AGC Noise Gate Status
0: Right-ADC signal power greater than noise threshold for right AGC
1: Right-ADC signal power lower than noise threshold for right AGC
DESCRIPTION
Page 0 / Register 97:
(1)
84
Sticky Interrupt Flags Register
Real-Time Interrupt Flags Register
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
HPLOUT_x Short-Circuit Detection Status
0: No short circuit detected at HPLOUT_x driver
1: Short circuit detected at HPLOUT_x driver
D6
R
0
HPROUT_x Short-Circuit Detection Status
0: No short circuit detected at HPROUT_x driver
1: Short circuit detected at HPROUT_x driver
D5
R
0
HPLCOM_x Short-Circuit Detection Status
0: No short circuit detected at HPLCOM_x driver
1: Short circuit detected at HPLCOM_x driver
D4
R
0
HPRCOM_x Short-Circuit Detection Status
0: No short circuit detected at HPRCOM_x driver
1: Short circuit detected at HPRCOM_x driver
D3
R
0
Button-Press Detection Status (1)
0: No headset button press detected
1: Headset button pressed
D2
R
0
Headset Detection Status
0: No headset is detected.
1: Headset is detected.
D1
R
0
Left-ADC AGC Noise Gate Status
0: Left-ADC signal power greater than noise threshold for left AGC
1: Left-ADC signal power lower than noise threshold for left AGC
D0
R
0
Right-ADC AGC Noise Gate Status
0: Right-ADC signal power greater than noise threshold for right AGC
1: Right-ADC signal power lower than noise threshold for right AGC
DESCRIPTION
This bit is a sticky bit, cleared only when page 0, register 14 is read.
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 98:
GPIO1_x Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
GPIO1_x Clock Mux Output Control
0: GPIO1_x clock mux output = PLL output
1: GPIO1_x clock mux output = clock divider mux output
D2
R/W
0
GPIO1_x Interrupt Duration Control
0: GPIO1_x interrupt occurs as a single active-high pulse of typical 2-ms duration.
1: GPIO1_x interrupt occurs as continuous pulses until the interrupt flags register (register 96) is read by
the host.
D1
R
0
GPIO1_x General-Purpose Input Value
0: A logic-low level is input to GPIO1_x.
1: A logic-high level is input to GPIO1_x.
D0
R/W
0
GPIO1_x General-Purpose Output Value
0: GPIO1_x outputs a logic-low level.
1: GPIO1_x outputs a logic-high level.
DESCRIPTION
GPIO1_x Output Control
0000: GPIO1_x is disabled.
0001: GPIO1_x used for audio serial data bus ADC word clock
0010: GPIO1_x output = clock mux output divided by 1 (M = 1)
0011: GPIO1_x output = clock mux output divided by 2 (M = 2)
0100: GPIO1_x output = clock mux output divided by 4 (M = 4)
0101: GPIO1_x output = clock mux output divided by 8 (M = 8)
0110: GPIO1_x output = short-circuit interrupt
0111: GPIO1_x output = AGC noise interrupt
1000: GPIO1_x = general-purpose input
1001: GPIO1_x = general-purpose output
1010: GPIO1_x output = digital microphone modulator clock
1011: GPIO1_x = word clock for audio serial data bus (programmable as input or output)
1100: GPIO1_x output = hook-switch/button-press interrupt (interrupt polarity: active-high, typical interrupt
duration: button pressed time + clock resolution. Clock resolution depends on debounce programmability.
Typical interrupt delay from button: debounce duration + 0.5 ms)
1101: GPIO1_x output = jack/headset detection interrupt
1110: GPIO1_x output = jack/headset detection interrupt OR button-press interrupt
1111: GPIO1_x output = jack/headset detection OR button press OR short-circuit detection OR AGC
noise-detection interrupt
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SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 99:
GPIO2_x Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D4
R/W
0000
D3
R/W
0
GPIO2_x General-Purpose Output Value
0: GPIO2_x_x outputs a logic-low level.
1: GPIO2_x outputs a logic-high level.
D2
R
0
GPIO2_x General-Purpose Input Value
0: A logic-low level is input to GPIO2_x.
1: A logic-high level is input to GPIO2_x.
D1
R/W
0
GPIO2_x Interrupt Duration Control
0: GPIO2_x interrupt occurs as a single active-high pulse of typical 2-ms duration.
1: GPIO2_x interrupt occurs as continuous pulses until the interrupt flags register (register 96) is read by
the host.
D0
R
0
Reserved. Do not write to this register bit.
DESCRIPTION
GPIO2_x Output Control
0000: GPIO2_x is disabled.
0001: Reserved. Do not write this sequence to these register bits.
0010: GPIO2_x output = jack/headset detect interrupt (interrupt polarity: active-high. Typical interrupt
duration: 1.75 ms)
0011: GPIO2_x = general-purpose input
0100: GPIO2_x = general-purpose output
0101–0111: GPIO2_x input = digital microphone input, data sampled on clock rising and falling edges
1000: GPIO2_x = bit clock for audio serial data bus (programmable as input or output)
1001: GPIO2_x output = headset detect OR button-press interrupt
1010: GPIO2_x output = headset detect OR button press OR short-circuit detect OR AGC noise-detect
interrupt
1011: GPIO2_x output = short-circuit detect OR AGC noise-detect interrupt
1100: GPIO2_x output = headset detect OR button press or short-circuit detect interrupt
1101: GPIO2_x output = short-circuit detect interrupt
1110: GPIO2_x output = AGC noise-detect interrupt
1111: GPIO2_x output = button-press/hookswitch interrupt
Page 0 / Register 100:
Additional GPIO Control Register A
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
SDA Terminal Control (1)
The SDA terminal hardware includes pulldown capability only (open-drain NMOS), so an external pullup
resistor is required when using this terminal, even in GPIO mode.
00: SDA terminal is not used as general-purpose I/O.
01: SDA terminal used as general-purpose input
10: SDA terminal used as general-purpose output
11: Reserved. Do not write this sequence to these register bits.
D5
R/W
0
SDA General-Purpose Output Control (1)
0: SDA driven to logic-low when used as general-purpose output
1: SDA driven to logic-high when used as general-purpose output (requires external pullup resistor)
D4
R
0
SDA General-Purpose Input Value (1)
0: SDA detects a logic-low when used as general-purpose input.
1: SDA is detects a logic-high when used as general-purpose input.
D3–D2
R/W
00
SCL Terminal Control (1)
The SCL terminal hardware includes pulldown capability only (open-drain NMOS), so an external pullup
resistor is required when using this terminal, even in GPIO mode.
00: SCL terminal is not used as general-purpose I/O.
01: SCL terminal used as general-purpose input
10: SCL terminal used as general-purpose output
11: Reserved. Do not write this sequence to these register bits.
D1
R/W
0
SCL General-Purpose Output Control (1)
0: SCL driven to logic-low when used as general-purpose output
1: SCL driven to logic-high when used as general-purpose output (requires external pullup resistor)
D0
R
0
SCL General-Purpose Input Value (1)
0: SCL detects a logic-low when used as general-purpose input.
1: SCL detects a logic-high when used as general-purpose input.
(1)
86
DESCRIPTION
The control bits in register 100 are only valid in SPI mode, when SELECT = 1.
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Page 0 / Register 101:
Codec A, I2C Address Select
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
Reserved
D6
R
0
Codec A I2C Address ADDR_A Terminal Status
0: When ADDR_A is in a reset condition, then the I2C address is 001 1000.
1: When ADDR_A is in a reset condition, then the I2C address is 001 1010.
D5–D0
R
00 0000
DESCRIPTION
Reserved
Page 0 / Register 101:
Codec B, I2C Address Select
BIT
READ/
WRITE
RESET
VALUE
D7
R
0
Reserved
D6
R
0
Codec B I2C Address ADDR_B Terminal Status
0: When ADDR_B is in a reset condition, then the I2C address is 001 1001.
1: When ADDR_B is in a reset condition, then the I2C address is 001 1011.
D5–D0
R
00 0000
DESCRIPTION
Reserved
Page 0 / Register 102:
Clock Generation Control Register
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
CLKDIV_IN Source Selection
00: CLKDIV_IN uses MCLK_x.
01: CLKDIV_IN uses GPIO2_x.
10: CLKDIV_IN uses BCLK_x.
11: Reserved. Do not write this sequence to these register bits.
D5–D4
R/W
00
PLLCLK_IN Source Selection
00: PLLCLK_IN uses MCLK_x.
01: PLLCLK_IN uses GPIO2_x.
10: PLLCLK _IN uses BCLK_x.
11: Reserved. Do not write this sequence to these register bits.
D3–D0
R/W
0010
DESCRIPTION
PLL Clock Divider N Value
0000: N = 16
0001: N = 17
0010: N = 2
0011: N = 3
…
1111: N = 15
Page 0 / Register 103:
Left-AGC New Programmable Attack Time Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Attack Time Register Selection
0: Attack time for the left AGC is generated from register 26.
1: Attack time for the left AGC is generated from this register.
D6–D5
R/W
00
Baseline AGC Attack Time
00: Left-AGC attack time = 7 ms
01: Left-AGC attack time = 8 ms
10: Left-AGC attack time = 10 ms
11: Left-AGC attack time = 11 ms
D4–D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline
001: Multiplication factor for the baseline
010: Multiplication factor for the baseline
011: Multiplication factor for the baseline
100: Multiplication factor for the baseline
101: Multiplication factor for the baseline
110: Multiplication factor for the baseline
111: Multiplication factor for the baseline
D1–D0
R/W
00
DESCRIPTION
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
time
time
time
time
time
time
time
time
=1
=2
=4
=8
= 16
= 32
= 64
= 128
Reserved. Write only zeros to these register bits.
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Page 0 / Register 104:
Left-AGC New Programmable Decay Time Register (1)
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Decay Time Register Selection
0: Decay time for the left AGC is generated from register 26.
1: Decay time for the left AGC is generated from this register.
D6–D5
R/W
00
Baseline AGC Decay Time
00: Left-AGC decay time = 50 ms
01: Left-AGC decay time = 150 ms
10: Left-AGC decay time = 250 ms
11: Left-AGC decay time = 350 ms
D4–D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline
001: Multiplication factor for the baseline
010: Multiplication factor for the baseline
011: Multiplication factor for the baseline
100: Multiplication factor for the baseline
101: Multiplication factor for the baseline
110: Multiplication factor for the baseline
111: Multiplication factor for the baseline
D1–D0
(1)
R/W
00
DESCRIPTION
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
time
time
time
time
time
time
time
time
=1
=2
=4
=8
= 16
= 32
= 64
= 128
Reserved. Write only zeros to these register bits.
Decay time is limited based on the NADC ratio that is selected. For
NADC = 1, maximum decay time = 4 seconds
NADC = 1.5, maximum decay time = 5.6 seconds
NADC = 2, maximum decay time = 8 seconds
NADC = 2.5, maximum decay time = 9.6 seconds
NADC = 3 or 3.5, maximum decay time = 11.2 seconds
NADC = 4 or 4.5, maximum decay time = 16 seconds
NADC = 5, maximum decay time = 19.2 seconds
NADC = 5.5 or 6, maximum decay time = 22.4 seconds
Page 0 / Register 105:
Right-AGC New Programmable Attack Time Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Attack Time Register Selection
0: Attack time for the right AGC is generated from register 29.
1: Attack time for the right AGC is generated from this register.
D6–D5
R/W
00
Baseline AGC Attack Time
00: Right-AGC attack time = 7 ms
01: Right-AGC attack time = 8 ms
10: Right-AGC attack time = 10 ms
11: Right-AGC attack time = 11 ms
D4–D2
R/W
000
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline
001: Multiplication factor for the baseline
010: Multiplication factor for the baseline
011: Multiplication factor for the baseline
100: Multiplication factor for the baseline
101: Multiplication factor for the baseline
110: Multiplication factor for the baseline
111: Multiplication factor for the baseline
D1–D0
88
R/W
00
DESCRIPTION
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
AGC attack
time
time
time
time
time
time
time
time
=1
=2
=4
=8
= 16
= 32
= 64
= 128
Reserved. Write only zeros to these register bits.
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Page 0 / Register 106:
Right-AGC New Programmable Decay Time Register (1)
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Decay Time Register Selection
0: Decay time for the right AGC is generated from register 29.
1: Decay time for the right AGC is generated from this register.
D6–D5
R/W
00
Baseline AGC Decay time
00: Right-AGC decay time
01: Right-AGC decay time
10: Right-AGC decay time
11: Right-AGC decay time
D4–D2
D1–D0
(1)
R/W
R/W
000
00
DESCRIPTION
= 50 ms
= 150 ms
= 250 ms
= 350 ms
Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline
001: Multiplication factor for the baseline
010: Multiplication factor for the baseline
011: Multiplication factor for the baseline
100: Multiplication factor for the baseline
101: Multiplication factor for the baseline
110: Multiplication factor for the baseline
111: Multiplication factor for the baseline
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
AGC decay
time
time
time
time
time
time
time
time
=1
=2
=4
=8
= 16
= 32
= 64
= 128
Reserved. Write only zeros to these register bits.
Decay time is limited based on the NADC ratio that is selected. For
NADC = 1, maximum decay time = 4 seconds
NADC = 1.5, maximum decay time = 5.6 seconds
NADC = 2, maximum decay time = 8 seconds
NADC = 2.5, maximum decay time = 9.6 seconds
NADC = 3 or 3.5, maximum decay time = 11.2 seconds
NADC = 4 or 4.5, maximum decay time = 16 seconds
NADC = 5, maximum decay time = 19.2 seconds
NADC = 5.5 or 6, maximum decay time = 22.4 seconds
Page 0 / Register 107:
New Programmable ADC Digital Path and I2C Bus Condition Register
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
Left-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
D6
R/W
0
Right-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
D5–D4
R/W
00
ADC Decimation Filter configuration
00: Left and right digital microphones are used.
01: Left digital microphone and right analog microphone are used.
10: Left analog microphone and right digital microphone are used.
11: Left and right analog microphones are used.
D3
R/W
0
ADC Digital Output to Programmable Filter Path Selection
0: No additional programmable filters other than the HPF are used for the ADC.
1: The programmable filter is connected to ADC output if both DACs are powered down.
D2
R/W
0
I2C Bus Condition Detector
0: Internal logic is enabled to detect an I2C bus error, and clears the bus error condition.
1: Internal logic is disabled to detect an I2C bus error.
D1
R
0
Reserved. Write only zero to this register bit.
D0
R
0
I2C Bus Error Detection Status
0: I2C bus error is not detected.
1: I2C bus error is detected. This bit is cleared by reading this register.
DESCRIPTION
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Page 0 / Register 108:
(1)
Passive Analog Signal Bypass Selection During Power Down Register (1)
BIT
READ/
WRITE
RESET
VALUE
D7
R/W
0
LINE2RM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM_x.
D6
R/W
0
LINE2RP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP_x.
D5
R/W
0
LINE1RM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM_x.
D4
R/W
0
LINE1RP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP_x.
D3
R/W
0
LINE2LM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM_x.
D2
R/W
0
LINE2LP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP_x.
D1
R/W
0
LINE1LM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM_x.
D0
R/W
0
LINE1LP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP_x.
DESCRIPTION
Based on the settings of this register, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches
used for the connection short the two input signals together on the output terminals. The shorting resistance between the two input
terminals is two times the bypass switch resistance (Rdson). In general, this condition of shorting should be avoided, as higher drive
currents are likely to occur on the circuitry that feeds these two input terminals of this device.
Page 0 / Register 109:
BIT
READ/
WRITE
RESET
VALUE
D7–D6
R/W
00
D5–D0
R/W
00 0000
DAC Dynamic Range Selection Register
DESCRIPTION
DAC Dynamic Range Adjustment
00: Default (Dynamic range specified in electrical characteristics table)
01: Dynamic range enhancement level 1
10: Reserved
11: Dynamic range enhancement level 2
Reserved. Write only zeros to these register bits.
Page 0 / Register 110–127:
BIT
READ/
WRITE
RESET
VALUE
D7–D0
R
0000 0000
DESCRIPTION
Reserved. Do not write to these registers.
Page 1 / Register 0:
BIT
READ/
WRITE
RESET
VALUE
D7–D1
X
0000 000
D0
R/W
0
90
Reserved Registers
Page Select Register
DESCRIPTION
Reserved. Write only zeros to these register bits.
Page Select Bit
Writing zero to this bit sets page 0 as the active page for subsequent register accesses. Writing a one to
this bit sets page 1 as the active page for subsequent register accesses. It is recommended that the user
read this register bit back after each write, to ensure that the proper page is being accessed for future
register read/writes. This register has the same functionality on page 0 and page 1.
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The remaining page-1 registers are either reserved registers or are used for setting coefficients for the various
filters in the TLV320AIC34. Reserved registers should not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are
interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When
programming any coefficient value for a filter, the MSB register should always be written first, immediately
followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers
should be written in this sequence. Table 8 is a list of the page-1 registers, excepting the previously described
register 0.
Table 8. Page-1 Registers
REGISTER
NUMBER
RESET VALUE
1
0110 1011
Left-channel audio effects filter N0 coefficient MSB register
2
1110 0011
Left-channel audio effects filter N0 coefficient LSB register
3
1001 0110
Left-channel audio effects filter N1 coefficient MSB register
4
0110 0110
Left-channel audio effects filter N1 coefficient LSB register
5
0110 0111
Left-channel audio effects filter N2 coefficient MSB register
6
0101 1101
Left-channel audio effects filter N2 coefficient LSB register
7
0110 1011
Left-channel audio effects filter N3 coefficient MSB register
8
1110 0011
Left-channel audio effects filter N3 coefficient LSB register
9
1001 0110
Left-channel audio effects filter N4 coefficient MSB register
10
0110 0110
Left-channel audio effects filter N4 coefficient LSB register
11
0110 0111
Left-channel audio effects filter N5 coefficient MSB register
12
0101 1101
Left-channel audio effects filter N5 coefficient LSB register
13
0111 1101
Left-channel audio effects filter D1 coefficient MSB register
14
1000 0011
Left-channel audio effects filter D1 coefficient LSB register
15
1000 0100
Left-channel audio effects filter D2 coefficient MSB register
16
1110 1110
Left-channel audio effects filter D2 coefficient LSB register
17
0111 1101
Left-channel audio effects filter D4 coefficient MSB register
18
1000 0011
Left-channel audio effects filter D4 coefficient LSB register
19
1000 0100
Left-channel audio effects filter D5 coefficient MSB register
20
1110 1110
Left-channel audio effects filter D5 coefficient LSB register
21
0011 1001
Left-channel de-emphasis filter N0 coefficient MSB register
22
0101 0101
Left-channel de-emphasis filter N0 coefficient LSB register
23
1111 0011
Left-channel de-emphasis filter N1 coefficient MSB register
24
0010 1101
Left-channel de-emphasis filter N1 coefficient LSB register
25
0101 0011
Left-channel de-emphasis filter D1 coefficient MSB register
26
0111 1110
Left-channel de-emphasis filter D1 coefficient LSB register
27
0110 1011
Right-channel audio effects filter N0 coefficient MSB register
28
1110 0011
Right-channel audio effects filter N0 coefficient LSB register
29
1001 0110
Right-channel audio effects filter N1 coefficient MSB register
30
0110 0110
Right-channel audio effects filter N1 coefficient LSB register
31
0110 0111
Right-channel audio effects filter N2 coefficient MSB register
32
0101 1101
Right-channel audio effects filter N2 coefficient LSB register
33
0110 1011
Right-channel audio effects filter N3 coefficient MSB register
34
1110 0011
Right-channel audio effects filter N3 coefficient LSB register
35
1001 0110
Right-channel audio effects filter N4 coefficient MSB register
36
0110 0110
Right-channel audio effects filter N4 coefficient LSB register
37
0110 0111
Right-channel audio effects filter N5 coefficient MSB register
REGISTER NAME
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Table 8. Page-1 Registers (continued)
92
REGISTER
NUMBER
RESET VALUE
38
0101 1101
Right-channel audio effects filter N5 coefficient LSB register
39
0111 1101
Right-channel audio effects filter D1 coefficient MSB register
40
1000 0011
Right-channel audio effects filter D1 coefficient LSB register
41
1000 0100
Right-channel audio effects filter D2 coefficient MSB register
42
1110 1110
Right-channel audio effects filter D2 coefficient LSB register
43
0111 1101
Right-channel audio effects filter D4 coefficient MSB register
44
1000 0011
Right-channel audio effects filter D4 coefficient LSB register
45
1000 0100
Right-channel audio effects filter D5 coefficient MSB register
46
1110 1110
Right-channel audio effects filter D5 coefficient LSB register
47
0011 1001
Right-channel de-emphasis filter N0 coefficient MSB register
48
0101 0101
Right-channel de-emphasis filter N0 coefficient LSB register
49
1111 0011
Right-channel de-emphasis filter N1 coefficient MSB register
50
0010 1101
Right-channel de-emphasis filter N1 coefficient LSB register
51
0101 0011
Right-channel de-emphasis filter D1 coefficient MSB register
52
0111 1110
Right-channel de-emphasis filter D1 coefficient LSB register
53
0111 1111
3-D attenuation coefficient MSB register
54
1111 1111
3-D attenuation coefficient LSB register
55–64
0000 0000
Reserved registers
65
0011 1001
Left-channel ADC high-pass filter N0 coefficient MSB register
66
0101 0101
Left-channel ADC high-pass filter N0 coefficient LSB register
67
1111 0011
Left-channel ADC high-pass filter N1 coefficient MSB register
68
0010 1101
Left-channel ADC high-pass filter N1 coefficient LSB register
69
0101 0011
Left-channel ADC high-pass filter D1 coefficient MSB register
70
0111 1110
Left-channel ADC high-pass filter D1 coefficient LSB register
71
0011 1001
Right-channel ADC high-pass filter N0 coefficient MSB register
72
0101 0101
Right-channel ADC high-pass filter N0 coefficient LSB register
73
1111 0011
Right-channel ADC high-pass filter N1 coefficient MSB register
74
0010 1101
Right-channel ADC high-pass filter N1 coefficient LSB register
75
0101 0011
Right-channel ADC high-pass filter D1 coefficient MSB register
76
0111 1110
Right-channel ADC high-pass filter D1 coefficient LSB register
77–127
0000 0000
Reserved registers
REGISTER NAME
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV320AIC34IZAS
ACTIVE
NFBGA
ZAS
87
490
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
TAIC34I
TLV320AIC34IZASR
ACTIVE
NFBGA
ZAS
87
2500
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
TAIC34I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV320AIC34IZASR
Package Package Pins
Type Drawing
NFBGA
ZAS
87
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.3
B0
(mm)
K0
(mm)
P1
(mm)
6.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV320AIC34IZASR
NFBGA
ZAS
87
2500
336.6
336.6
31.8
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
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applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
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other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
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third party, or a license from TI under the patents or other intellectual property of TI.
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and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
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requirements. Nonetheless, such components are subject to these terms.
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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Copyright © 2014, Texas Instruments Incorporated
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