NXP UDA1341TS Economy audio CODEC Data Sheet

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NXP UDA1341TS Economy audio CODEC Data Sheet | Manualzz

INTEGRATED CIRCUITS

DATA SHEET

UDA1341TS

Economy audio CODEC for

MiniDisc (MD) home stereo and portable applications

Product specification

Supersedes data of 2001 Jun 29

2002 May 16

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

CONTENTS

4

5

2

3

1

1.1

1.2

1.3

1.4

6

7

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.17

7.18

7.19

7.20

7.21

7.21.1

7.21.2

7.21.3

7.21.4

FEATURES

General

Multiple format data interface

DAC digital sound processing

Advanced audio configuration

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

System clock

Pin compatibility

Analog front end

Programmable Gain Amplifier (PGA)

Analog-to-Digital Converter (ADC)

Digital Automatic Gain Control (AGC)

AGC status detection

Digital mixer

Decimation filter (ADC)

Overload detection (ADC)

Mute (ADC)

Interpolation filter (DAC)

Peak detector

Quick mute

Noise shaper (DAC)

Filter Stream Digital-to-Analog Converter

(FSDAC)

Multiple format input/output interface

L3-interface

Address mode

Data transfer mode

Programming the sound processing and other features

STATUS control

DATA0 direct control

DATA0 extended programming registers

DATA1 control

16

17

8

9

10

11

12

13

14

15

15.1

15.2

15.3

15.4

15.5

Product specification

UDA1341TS

LIMITING VALUES

THERMAL CHARACTERISTICS

DC CHARACTERISTICS

AC CHARACTERISTICS (ANALOG)

AC CHARACTERISTICS (DIGITAL)

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

Introduction to soldering surface mount packages

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for wave and reflow soldering methods

DATA SHEET STATUS

DISCLAIMERS

2002 May 16 2

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

1 FEATURES

1.1

General

• Low power consumption

• 3.0 V power supply

• 256f s

, 384f s

or 512f s

system clock frequencies (f sys

)

• Small package size (SSOP28)

• Partially pin compatible with UDA1340M and

UDA1344TS

• Fully integrated analog front end including digital AGC

• ADC plus integrated high-pass filter to cancel DC offset

• ADC supports 2 V (RMS value) input signals

• Overload detector for easy record level control

• Separate power control for ADC and DAC

• No analog post filter required for DAC

• Easy application

• Functions controllable via L3-interface.

• Optional differential input configuration for enhanced

ADC sound quality

• Stereo line output (under microcontroller volume control)

• Digital peak level detection

• High linearity, dynamic range and low distortion.

1.2

Multiple format data interface

• I 2 S-bus, MSB-justified and LSB-justified format compatible

• Three combinational data formats with MSB data output and LSB 16, 18 or 20 bits data input

• 1f s

input and output format data rate.

1.3

DAC digital sound processing

• Digital dB-linear volume control (low microcontroller load)

• Digital tone control, bass boost and treble

• Digital de-emphasis for 32, 44.1 or 48 kHz audio sample frequencies (f s

)

• Soft mute.

1.4

Advanced audio configuration

• DAC and ADC polarity control

• Two channel stereo single-ended input configuration

• Microphone input with on-board PGA

2 GENERAL DESCRIPTION

The UDA1341TS is a single-chip stereo Analog-to-Digital

Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. Its fully integrated analog front end, including Programmable Gain Amplifier (PGA) and a digital Automatic Gain Control (AGC). Digital Sound

Processing (DSP) featuring makes the device an excellent choice for primary home stereo MiniDisc applications, but by virtue of its low power and low voltage characteristics it is also suitable for portable applications such as MD/CD boomboxes, notebook PCs and digital video cameras.

The UDA1341TS is similar to the UDA1340M and the

UDA1344TS but adds features such as digital mixing of two input signals and one channel with a PGA and a digital

AGC.

The UDA1341TS supports the I 2 S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits, the LSB-justified serial data format with word lengths of 16, 18 and 20 bits and three combinations of MSB data output combined with

LSB 16, 18 and 20 bits data input. The UDA1341TS has

DSP features in playback mode like de-emphasis, volume, bass boost, treble and soft mute, which can be controlled via the L3-interface with a microcontroller.

3 ORDERING INFORMATION

TYPE

NUMBER

UDA1341TS

NAME

SSOP28

PACKAGE

DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm

VERSION

SOT341-1

2002 May 16 3

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN.

TYP.

MAX.

UNIT

I

I

Supplies

V

V

V

DDA(ADC)

DDA(DAC)

DDD

DDA(ADC)

DDA(DAC)

ADC analog supply voltage

DAC analog supply voltage digital supply voltage

ADC analog supply current

DAC analog supply current operation mode

ADC power-down operation mode

DAC power-down operation mode

2.4

2.4

3.0

3.0

2.4

3.0

12.5

6.0

7.0

50

7.0

−20 −

3.6

3.6

V

V

3.6

V mA

− mA

− mA

μA mA

+85

°C

I

DDD

T amb digital supply current operating ambient temperature

Analog-to-digital converter

V i(rms) input voltage (RMS value)

(THD + N)/S total harmonic distortion-plus-noise to signal ratio

S/N signal-to-noise ratio

notes 1 and 2

stand-alone mode

0 dB

−60 dB; A-weighted double differential mode

0 dB

−60 dB; A-weighted

V i

= 0 V; A-weighted stand-alone mode double differential mode

1.0

−85

−37

−90

−40

−80

−33

−85

−36

V dB dB dB dB

α cs channel separation

Programmable gain amplifier

(THD + N)/S total harmonic distortion-plus-noise to signal ratio

1 kHz; f s

= 44.1 kHz

0 dB

−60 dB; A-weighted

V i

= 0 V; A-weighted

97

100

100

−85 −

−37 −

95

− dB dB dB dB dB dB S/N

V o(rms) signal-to-noise ratio

Digital-to-analog converter output voltage (RMS value)

(THD+N)/S total harmonic distortion-plus-noise to signal ratio

S/N

α cs signal-to-noise ratio channel separation

supply voltage = 3 V; note 3

0 dB

−60 dB; A-weighted code = 0; A-weighted

900

−91

−40

100

100

−86

− mV dB dB dB dB

Notes

1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 k

Ω is used in series with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS).

2. The ADC input signal scales inversely proportional with the power supply voltage.

3. The DAC output voltage scales linear with the DAC analog supply voltage.

2002 May 16 4

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

5 BLOCK DIAGRAM

Product specification

UDA1341TS handbook, full pagewidth

VINL2

VINL1

6

VDDA(ADC) VSSA(ADC)

3 1

PGA

VDDD

10

VSSD

ADC2 ADC2

11

PGA

2 0 dB/6 dB

SWITCH

VADCP VADCN

7

0 dB/6 dB

SWITCH

5

8

4

ADC1 ADC1

22

UDA1341TS DIGITAL AGC

VINR2

VINR1

AGCSTAT

DIGITAL MIXER

DECIMATION FILTER

DATAO

BCK

WS

DATAI

18

16

17

19

QMUTE

23

Vref

28

DIGITAL INTERFACE

DSP FEATURES

INTERPOLATION FILTER

NOISE SHAPER

9

OVERFL

L3-BUS

INTERFACE

13

14

15

L3MODE

L3CLOCK

L3DATA

12

SYSCLK

PEAK

DETECTOR

20

21

TEST1

TEST2

DAC DAC

VOUTL

26

25

VDDA(DAC)

27

VSSA(DAC)

24

VOUTR

MGR427

2002 May 16

Fig.1 Block diagram.

5

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

6 PINNING

V

SSA(ADC)

VINL1

V

DDA(ADC)

VINR1

V

ADCN

VINL2

V

ADCP

VINR2

OVERFL

V

DDD

V

SSD

SYSCLK

L3MODE

L3CLOCK

SYMBOL PIN DESCRIPTION

1

2

ADC analog ground

ADC1 input left

5

6

3

4

ADC analog supply voltage

ADC1 input right

ADC negative reference voltage

ADC2 input left

7

8

ADC positive reference voltage

ADC2 input right

9 decimation filter overflow output

10 digital supply voltage

11 digital ground

12 system clock 256f s

, 384f s

or 512f s

13 L3-bus mode input

14 L3-bus clock input

SYMBOL

L3DATA

BCK

WS

DATAO

DATAI

TEST1

TEST2

AGCSTAT

QMUTE

VOUTR

V

DDA(DAC)

VOUTL

V

SSA(DAC)

V ref

PIN DESCRIPTION

15 L3-bus data input and output

16 bit clock input

17 word select input

18 data output

19 data input

20 test control 1 (pull-down)

21 test control 2 (pull-down)

22 AGC status

23 quick mute input

24 DAC output right

25 DAC analog supply voltage

26 DAC output left

27 DAC analog ground

28 ADC and DAC reference voltage handbook, halfpage

VSSA(ADC) 1

VINL1 2

VDDA(ADC) 3

VINR1 4

VADCN

5

VINL2 6

28 Vref

27 VSSA(DAC)

26 VOUTL

25 VDDA(DAC)

24 VOUTR

23 QMUTE

VADCP 7

VINR2 8

UDA1341TS

22 AGCSTAT

21 TEST2

OVERFL 9

VDDD 10

VSSD 11

SYSCLK 12

L3MODE 13

L3CLOCK 14

20 TEST1

19 DATAI

18 DATAO

17 WS

16 BCK

15 L3DATA

MGR428

2002 May 16

Fig.2 Pin configuration.

6 handbook, halfpage

VSSA(ADC) 1

VINL1 2

VDDA(ADC) 3

VINR1 4

VADCN

5

28

Vref

27

VSSA(DAC)

26 VOUTL

25 VDDA(DAC)

24 VOUTR

VINL2 6 23 QMUTE

VADCP 7

VINR2 8

UDA1341TS

22 AGCSTAT

21 TEST2

OVERFL 9

VDDD 10

VSSD

11

SYSCLK 12

L3MODE 13

L3CLOCK 14

20 TEST1

19 DATAI

18 DATAO

17 WS

16 BCK

15 L3DATA

MGR429

Marked pins are compatible with UDA1340M

Fig.3 Compatible pins with UDA1340M.

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7 FUNCTIONAL DESCRIPTION

7.1

System clock

The UDA1341TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256f s

, 384f s

or 512f s

.

The system clock must be locked in frequency to the digital interface signals.

7.5

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1341TS consists of two

3rd-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128.

7.2

Pin compatibility

The UDA1341TS is partially pin compatible with the

UDA1340M and UDA1344TS, making an upgrade of a printed-circuit board from UDA1340M to UDA1341TS easier. The pins that are compatible with the UDA1340M

are marked in Fig.3.

7.6

Digital Automatic Gain Control (AGC)

Input channel 2 has a digital AGC to compress the dynamic range when a microphone signal is applied to input channel 2. The digital AGC can be switched on and off via the L3-interface. In the on state the AGC compresses the dynamic range of the input signal of input channel 2. Via the L3-interface the user can set the parameters of the AGC: attack time, decay time and output level. When the AGC is set off via the L3-interface, the gain of input channel 2 can be set manually. In this case the gain of the PGA and digital AGC are combined. The range of the gain of the input channel 2 is from

−3 to +60.5 dB in steps of 0.5 dB.

7.3

Analog front end

The analog front end of the UDA1341TS consists of two stereo ADCs with a Programmable Gain Amplifier (PGA) in channel 2. The PGA is intended to pre-amplify a microphone signal applied to the input channel 2.

Input channel 1 has a selectable 0 or 6 dB gain stage, to be controlled via the L3-interface. In this way, input signals of 1 V (RMS value) or 2 V (RMS value) e.g. from a

CD source can be supported using an external resistor of

12 k

Ω in series with the input channel 1. The application

modes are given in Table 1.

7.7

AGC status detection

The AGCSTAT signal from the digital AGC is HIGH when the gain level of the AGC is below 8 dB. This signal can be used to give the PGA a new gain setting via the

L3-interface and to power e.g. a LED.

Table 1

Note

7.4

Application modes using input gain stage

RESISTOR

(12 k

Ω)

Present

INPUT

GAIN

SWITCH

0 dB

Present

Absent

Absent

6 dB

0 dB

6 dB

MAXIMUM INPUT VOLTAGE

2 V (RMS value) input signal;

note 1

1 V (RMS value) input signal

1 V (RMS value) input signal

0.5 V (RMS value) input signal

1. If there is no need for 2 V (RMS value) input signal support, the external resistor should not be used.

Programmable Gain Amplifier (PGA)

The PGA can be set via the L3-interface at the gain settings:

−3, 0, 3, 9, 15, 21 or 27 dB.

7.8

Digital mixer

The two stereo ADCs (including the AGC) can be used in four modes:

• ADC1 only mode (for line input); input channel 2 is off

• ADC2 only mode, including PGA and digital AGC (for microphone input); input channel 1 is off

• ADC1 + ADC2 mixer mode, including PGA and AGC

• ADC1 and ADC2 double differential mode (improved

ADC performance).

Important: In order to prevent crosstalk between the line inputs no signal should be applied to the microphone input in the double differential mode.

In all modes (except the double differential mode) a reference voltage is always present at the input of the

ADC. However, in the double differential mode there is no reference voltage present at the microphone input.

In the mixer mode, the output signals of both ADCs in channel 1 and channel 2 (after the digital AGC) can be mixed with coefficients that can be set via the L3-interface.

The range of the mixer coefficients is from 0 to

−∞ dB in

1.5 dB steps.

2002 May 16 7

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7.9

Decimation filter (ADC)

The decimation from 128f s

is performed in two stages.

The first stage realizes 3rd order characteristic, x decimating by 16. The second stage consists of

3 half-band filters, each decimating by a factor of 2.

7.12

Interpolation filter (DAC)

The digital filter interpolates from 1f s to 128f s

by means of a cascade of a recursive filter and a Finite Impulse

Response (FIR) filter.

Table 3 Interpolation filter characteristics

Table 2 Decimation filter characteristics

ITEM

Passband ripple

Stop band

Dynamic range

Overall gain

CONDITIONS

0 to 0.45f

s

>0.55f

s

0 to 0.45f

s input channel 1;

0 dB input

VALUE

(dB)

±0.05

−60

108

−1.16

7.10

Overload detection (ADC)

This name is convenient but a little inaccurate. In practice the output is used to indicate whenever that output data, in either the left or right channel, is bigger than

−1 dB (actual figure is

−1.16 dB) of the maximum possible digital swing.

If this condition is detected the OVERFL output is forced

HIGH for at least 512f s cycles (11.6 ms at f

This time-out is reset for each infringement.

s

= 44.1 kHz).

7.11

Mute (ADC)

On recovery from power-down or switching on of the system clock, the serial data output on pin DATAO is held at LOW level until valid data is available from the decimation filter. This time depends on whether the

DC-cancellation filter is selected:

• DC cancel off: t = ; t = 23.2 ms at f f s

• DC cancel on: s

= 44.1 kHz t = ; t = 279 ms at f s

= 44.1 kHz.

f s

ITEM

Passband ripple

Stop band

Dynamic range

7.13

Peak detector

CONDITIONS

0 to 0.45f

s

>0.55f

s

0 to 0.45f

s

In the playback path a peak level detector is build in.

The position of the peak detection can be set via the

L3-interface to either before or after the sound features.

The peak level detector is implemented as a peak-hold detector, which means that the highest sound level is hold until the peak level is read out via the L3-interface. After read-out the peak level registers are reset.

7.14

Quick mute

A hard mute can be activated via the static pin QMUTE.

When QMUTE is set HIGH, the output signal is instantly muted to zero. Setting QMUTE to LOW, the mute is instantly de-activated.

7.15

Noise shaper (DAC)

VALUE

(dB)

±0.03

−50

108

The 3rd-order noise shaper operates at 128f s

. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique allows for high signal-to-noise ratios. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter.

2002 May 16 8

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Product specification

UDA1341TS

7.16

Filter Stream Digital-to-Analog Converter

(FSDAC)

The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

7.17

Multiple format input/output interface

The UDA1341TS supports the following data formats:

• I

2 S-bus with word length up to 20 bits

• MSB-justified serial format with word length up to 20 bits

• LSB-justified serial format with word length of

16, 18 or 20 bits

• MSB data output with LSB 16, 18 or 20 bits input.

Left and right data-channel words are time multiplexed.

The formats are illustrated in Fig.4.

The UDA1341TS allows for double speed data monitoring purposes. In this case the sound features bass boost, treble and de-emphasis cannot be used. However, volume control and soft-mute can still be controlled. The double speed monitoring option can be set via the L3-interface.

The bit clock frequency must be 64 times word select frequency or less, so f

BCK

≤ 64 × f

WS

.

2002 May 16 9

WS

BCK

DATA

1 2

LEFT

3

MSB B2

WS

1 2

LEFT

3

BCK

DATA MSB B2

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

> =8 1 2

RIGHT

3 > =8

LSB MSB B2

INPUT FORMAT I

2

S-BUS

LSB MSB

LEFT

> =8 1 2

RIGHT

3

LSB MSB B2

> =8

LSB MSB B2

MSB-JUSTIFIED FORMAT

16 15 2 1

MSB B2 B15 LSB

LSB-JUSTIFIED FORMAT 16 BITS

LEFT

18 17 16 15

MSB B2 B3 B4

2 1

B17 LSB

LSB-JUSTIFIED FORMAT 18 BITS

20 19

LEFT

18 17 16 15 2 1

MSB B2 B3 B4 B5 B6 B19 LSB

LSB-JUSTIFIED FORMAT 20 BITS

Fig.4 Serial interface formats.

18

MSB

RIGHT

MSB

RIGHT

17

B2

16

16

B3

15

B2

15

B4

20 19 18

RIGHT

17 16 15

MSB B2 B3 B4 B5 B6

2 1

B15 LSB

2 1

B17 LSB

2 1

B19 LSB

MGG841

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7.18

L3-interface

The UDA1341TS has a microcontroller input mode. In the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller.

The controllable features are:

• Reset

• System clock frequency

• Power control

• DAC gain switch

• ADC input gain switch

• ADC/DAC polarity control

• Double speed playback

• De-emphasis

• Volume

• Mode switch

• Bass boost

• Treble

• Mute

• MIC sensitivity control

• AGC control

• Input amplifier gain control

• Digital mixer control

• Peak detection position.

Via the L3-interface the peak level value of the signal in the

DAC path can be read out from the UDA1341TS to the microcontroller.

The exchange of data and control information between the microcontroller and the UDA1341TS is accomplished through a serial hardware L3-interface comprising the following pins:

• L3DATA: microcontroller interface data line

• L3MODE: microcontroller interface mode line

• L3CLOCK: microcontroller interface clock line.

Information transfer through the microcontroller bus is organized in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished: address mode and data transfer mode.

The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode.

Data transfer can be in both directions: input to the

UDA1341TS to program its sound processing and system controlling features and output from the UDA1341TS to provide the peak level value.

7.19

Address mode

The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is

shown in Fig.5.

Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the

UDA1341TS is 000101.

Data bits 0 to 1 indicate the type of the subsequent data

transfer as shown in Table 4.

In the event that the UDA1341TS receives a different address, it will deselect its microcontroller interface logic.

7.20

Data transfer mode

The selection activated in the address mode remains active during subsequent data transfers, until the

UDA1341TS receives a new address command.

The fundamental timing of data transfers is essentially the same as the timing in the address mode and is given in

Fig.6.

Note that ‘L3DATA write’ denotes data transfer from the microcontroller to the UDA1341TS and ‘L3DATA peak read’ denotes data transfer in the opposite direction.

The maximum input clock and data rate is 64f s

.

All transfers are byte-wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1341TS after the eighth bit of a byte has been received.

A multibyte transfer is illustrated in Fig.7.

2002 May 16 11

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

Table 4 Selection of data transfer

BIT 1 BIT 0 MODE

0

0

1

1

0 DATA0

TRANSFER direct addressing registers: volume, bass boost, treble, peak detection position, de-emphasis, mute and mode extended addressing registers: digital mixer control, AGC control, MIC sensitivity control, input gain, AGC time constant and AGC output level

1 DATA1 peak level value read-out (information from UDA1341TS to microcontroller)

0 STATUS reset, system clock frequency, data input format, DC-filter, input gain switch, output gain switch, polarity control, double speed and power control

1 not used handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA th(L3)A tsu(L3)A tCLK(L3)L tCLK(L3)H

BIT 0 tsu(L3)DA th(L3)DA tsu(L3)A th(L3)A

Tcy(CLK)(L3)

BIT 7

MGR431

Fig.5 Timing address mode.

2002 May 16 12

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS handbook, full pagewidth

L3MODE tstp(L3)

L3CLOCK tsu(L3)D

L3DATA write

L3DATA read tCLK(L3)H tCLK(L3)L

Tcy(CLK)L3 th(L3)D tstp(L3) th(L3)DA

BIT 0 tsu(L3)DA

PL0 PL1 PL2 PL3 PL4 PL5

Fig.6 Timing for data transfer mode.

th(L3)DA

BIT 7

MGR430 handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

2002 May 16 tstp(L3) address data byte #1 data byte #2 address MGR432

Fig.7 Multibyte transfer.

13

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7.21

Programming the sound processing and other features

The sound processing and other feature values are stored in independent registers.

The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the

address mode using bit 0 and bit 1 (see Table 4).

The second selection is performed by the 2 or 3 MSBs of the data byte (bits 7 and 6 or bits 7, 6 and 5).

The other bits in the data byte (bits 5 to 0 or bits 4 to 0) represent the value that is placed in the selected registers.

For the UDA1341TS the following modes can be selected:

• STATUS

In this mode the features reset, system clock frequency, data input format, DC-filter, input gain switch, output gain switch, polarity control, double speed and power control can be controlled.

• DATA0

There are two addressing modes: direct addressing mode and extended addressing mode.

Direct addressing mode is using the 2 MSB bits of the data byte. Via this addressing mode the features volume, bass boost, treble, peak position, de-emphasis, mute, and mode can be controlled directly.

Extended addressing mode is provided for controlling the features digital mixer, AGC control, MIC sensitivity, input gain, AGC time constants, and AGC output level.

An extended address can be set via the EA registers

(3 bits). The data in the extended registers can be set by writing data to the ED registers (5 bits).

• DATA1

In this mode the detected peak level value can be read out.

Table 5 Default settings

SYMBOL FEATURE

Status

OGS

IGS

PAD

PDA

DS

PC

Output gain switch

Input gain switch

Polarity of ADC

Polarity of DAC

Double speed

Power control ADC and DAC

Direct control

VC

BB

TR

PP

DE

MT

M

Volume control

Bass boost

Treble

Peak detection position

De-emphasis

Mute

Mode switch

Extended programming

MA

MB

MS

MM

AG

AT

AL

Mixer gain channel 1

Mixer gain channel 2

MIC sensitivity

Mixer mode switch

AGC control

AGC attack and decay time

AGC output level

2002 May 16 14

0 dB

0 dB

SETTING OR VALUE non-inverting non-inverting single speed on

0 dB

0 dB

0 dB after the tone features no de-emphasis no mute flat

−6 dB

−6 dB

0 dB double differential disable AGC

11 ms and100 ms

−9 dB FS

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7.21.1

STATUS CONTROL

Table 6 Data transfer of type ‘STATUS’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED

0 RST SC1 SC0 IF2 IF1 IF0 DC RST = reset

SC = system clock frequency (2 bits)

IF = data input format (3 bits)

DC = DC-filter

1 OGS IGS PAD PDA DS PC1 PC0 OGS = output gain (6 dB) switch

IGS = input gain (6 dB) switch

PAD = polarity of ADC

PDA = polarity of DAC

DS = double speed

PC = power control (2 bits)

7.21.1.1

Reset

A 1-bit value to initialize the L3-registers with the default settings except system clock frequency.

Table 7 Reset settings

RST

0

1 no reset reset

FUNCTION

7.21.1.2

System clock frequency

A 2-bit value to select the used external clock frequency.

Table 8 System clock settings

FUNCTION

1

1

0

0

SC1 SC0

0 512f s

1 384f s

0 256f s

1 not used

7.21.1.3

DC-filter

A 1-bit value to enable the digital DC-filter.

Table 9 DC-filtering settings

DC

0

1 no DC-filtering

DC-filtering

FUNCTION

7.21.1.4

Data input format

A 3-bit value to select the data input format.

Table 10 Data input format settings

IF2 IF1 IF0

0 0 0 I 2 S-bus

FUNCTION

0 0 1 LSB-justified 16 bits

0 1 0 LSB-justified 18 bits

0 1 1 LSB-justified 20 bits

1 0 0 MSB-justified

1 0 1 LSB-justified 16 bits input and

MSB-justified output

1 1 0 LSB-justified 18 bits input and

MSB-justified output

1 1 1 LSB-justified 20 bits input and

MSB-justified output

2002 May 16 15

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

7.21.1.5

Output gain switch

A 1-bit value to control the DAC output gain switch.

The default setting is given in Table 5.

Table 11 Gain switch of DAC settings

OGS

0

1

GAIN OF DAC

0 dB

6 dB

7.21.1.6

Input gain switch

A 1-bit value to control the ADC input gain switch.

The default setting is given in Table 5.

Table 12 Gain switch of ADC settings

IGS

0

1

GAIN OF ADC

0 dB

6 dB

7.21.1.7

Polarity of ADC

A 1-bit value to control the ADC polarity. The default

setting is given in Table 5.

Table 13 Polarity control of ADC settings

PAD

0 non-inverting

1 inverting

POLARITY OF ADC

7.21.1.8

Polarity of DAC

A 1-bit value to control the DAC polarity. The default

setting is given in Table 5.

Table 14 Polarity control of DAC settings

PDA

0 non-inverting

1 inverting

POLARITY OF DAC

Product specification

UDA1341TS

7.21.1.9

Double speed

A 1-bit value to enable the double speed playback.

The default setting is given in Table 5.

Table 15 Double speed settings

DS FUNCTION

0 single speed playback

1 double speed playback

7.21.1.10 Power control

A 2-bit value to disable the ADC and/or DAC to reduce

power consumption. The default setting is given in Table 5.

Table 16 Power control settings

FUNCTION

PC1 PC0

0

0

1

1

0

1

0

1

ADC off off on on

DAC off on off on

2002 May 16 16

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Product specification

UDA1341TS

7.21.2

DATA0 DIRECT CONTROL

Table 17 Data transfer of type ‘DATA0’

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0

0

1

1

1

0

1

0

1

1

VC5

BB3

VC4

BB2

VC3

BB1

VC2

BB0

VC1

TR1

VC0

TR0

REGISTER SELECTED

VC = volume control (6 bits)

BB = bass boost (4 bits)

TR = treble (2 bits)

PP DE1 DE0 MT M1 M0 PP = peak detection position

0

1

DE = de-emphasis (2 bits)

MT = mute

0 0 EA2 EA1 EA0

M = mode switch (2 bits)

EA = extended address (3 bits)

ED4 ED3 ED2 ED1 ED0 ED = extended data (5 bits)

7.21.2.1

Volume control

A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to

−∞ dB in steps of 1 dB.

The default setting is given in Table 5.

7.21.2.2

Bass boost

A 4-bit value to program the bass boost settings. The used set depends on the mode bits. The default setting is given

in Table 5.

Table 18 Volume settings

VC5 VC4 VC3 VC2 VC1 VC0

1

1

1

1

1

0

0

0

0

:

0

0

0

0

:

1

1

1

1

1

0

0

0

0

:

1

1

1

1

1

0

0

0

0

:

0

1

1

1

1

0

1

1

0

1

1

1

0

0

:

1

0

1

0

1

0

1

0

1

:

VOLUME

(dB)

0

0

−1

−2

:

−58

−59

−60

−∞

−∞

Table 19 Bass boost settings

BB3 BB2 BB1 BB0

1

1

1

1

1

0

0

1

1

0

0

0

0

0

0

0

0

1

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

FLAT

(dB)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

BASS BOOST

MIN.

(dB)

18

18

18

12

14

16

18

4

6

0

2

8

10

18

18

MAX.

(dB)

20

22

24

12

14

16

18

4

6

0

2

8

10

24

24

2002 May 16 17

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Product specification

UDA1341TS

7.21.2.3

Treble

A 2-bit value to program the treble setting. The used set depends on the mode bits. The default setting is given in

Table 5.

7.21.2.6

Mute

A 1-bit value to enable the digital mute. The default setting

is given in Table 5.

Table 20 Treble settings

TR1

1

1

0

0

TR0

0

1

0

1

FLAT

(dB)

0

0

0

0

TREBLE

MIN.

(dB)

4

6

0

2

MAX.

(dB)

4

6

0

2

Table 23 Mute settings

MT

7.21.2.7

0

1

Mode no mute mute

FUNCTION

A 2-bit value to program the mode of the sound processing filters of bass boost and treble. The default setting is given

in Table 5.

7.21.2.4

Peak detection position

A 1-bit value to control the position of the peak level detector in the signal processing path. The default setting

is given in Table 5.

Table 24 Mode filter switch settings

M1

0

0

1

1

M0

0

1

0

1 flat minimum minimum maximum

FUNCTION

Table 21 Peak detection position settings

PP

0

1

FUNCTION before tone features after tone features

7.21.2.5

De-emphasis

A 2-bit value to enable the digital de-emphasis filter.

The default setting is given in Table 5.

Table 22 De-emphasis settings

DE1

0

0

1

1

DE0

0

1

0

1

FUNCTION no de-emphasis de-emphasis: 32 kHz de-emphasis: 44.1 kHz de-emphasis: 48 kHz

2002 May 16 18

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7.21.3

DATA0 EXTENDED PROGRAMMING REGISTERS

Table 25 Extended control registers

EA2 EA1 EA0 ED4 ED3 ED2 ED1 ED0

0

0

0

1

1

1

0

0

1

0

0

1

0

1

0

MA4

MB4

MS2

MA3

MB3

MS1

MA2

MB2

MA1

MB1

REGISTER SELECTED

MA0 MA = mixer gain channel 1 (5 bits)

MB0 MB = mixer gain channel 2 (5 bits)

MS0 MM1 MM0 MS = MIC sensitivity (3 bits)

MM = mixer mode (2 bits)

0 AG 0 0 IG1 IG0 AG = AGC control

IG = input amplifier gain channel 2 (2 bits)

1 IG6 IG5 IG4 IG3 IG2 IG = input amplifier gain channel 2 (5 bits)

0 AT2 AT1 AT0 AL1 AL0 AT = AGC time constant (3 bits)

AL = AGC output level (2 bits)

Programming via extended addressing is done by first sending a DATA0 data byte EA (3 bits) which specifies the addresses of the extended register followed by a DATA0 data byte which specifies the contents of the extended data register (5 bits). The EA extended addresses and names of the extended data registers are given in

Table 25.

7.21.3.2

MIC sensitivity

A 3-bit value to program eight gain settings of the microphone amplifier. These settings are valid only when

AGC control is enabled and not in the double differential

mode. The default setting is given in Table 5.

7.21.3.1

Mixer gain control

Two 5-bit values to program the channel 1 (MA) and channel 2 (MB) coefficients in the mixer mode. The range is from 0 to

−∞ dB in steps of 1.5 dB. The default settings

are given in Table 5.

Table 26 Mixer gain control channel 1 and channel 2

MA4

MB4

0

:

0

0

1

1

1 settings

MA3

MB3

0

:

0

0

1

1

1

MA2

MB2

0

:

0

0

1

1

1

MA1

MB1

1

:

0

0

0

1

1

MA0

MB0

0

:

0

1

1

0

1

MIXER GAIN

(dB)

0

−1.5

−3.0

:

−43.5

−45.0

−∞

Table 27 MIC sensitivity settings

MS2

1

1

1

0

0

0

0

1

MS1

0

0

1

1

0

0

1

1

MS0

0

1

0

1

0

1

0

1

+9

+15

+21

+27

−3

MIC AMPLIFIER GAIN

(dB)

0

+3 not used

2002 May 16 19

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7.21.3.3

Mixer mode

A 2-bit value to program the mode of the digital mixer.

There are four modes: double differential, input channel 1 select, input channel 2 select and digital mixer mode.

The default setting is given in Table 5.

7.21.3.6

Input channel 2 amplifier gain

A 7-bit value to program the input channel 2 amplifier gain.

The range is from

−3 to +60.5 dB in steps of 0.5 dB. These settings are only valid when AGC control is disabled and not valid in the double differential mode.

Table 28 Mixer mode switch settings

MM1 MM0

1

1

0

0

7.21.3.4

FUNCTION

0 double differential mode

1 input channel 1 select (input channel 2 off)

0 input channel 2 select (input channel 1 off)

1 digital mixer mode

(input 1

× MA + input 2 × MB)

AGC control

A 1-bit value to enable the AGC input. The default setting

is given in Table 5.

Table 29 AGC control settings

AG

0

1

FUNCTION disable AGC: manual gain setting through

IG (7 bits) enable AGC: gain control with manual MIC sensitivity setting

Table 31 Input channel 2 amplifier gain settings

IG6 IG5 IG4 IG3 IG2 IG1 IG0

0

:

1

0

0

0

0

0

0

1

1

0

:

1

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

:

1

1

1

0

0

0

0

0

0

0

:

1

1

1

0

0

0

0

1

1

1

:

1

1

1

0

0

1

1

0

0

1

:

0

1

1

0

1

0

1

0

1

0

:

1

0

1

INPUT

CHANNEL 2

AMPLIFIER

GAIN

(dB)

−3.0

−2.5

−2.0

−1.5

−1.0

−0.5

0.0

:

59.5

60.0

60.5

7.21.3.5

AGC output level

A 2-bit value to program the AGC output level. The default

setting is given in Table 5.

7.21.3.7

AGC time constant

A 3-bit value to program the attack and the decay parameters of the digital AGC. The default setting is given

in Table 5.

Table 30 AGC output level settings

AL1

0

0

1

1

AL0

0

1

0

1

−9.0

−11.5

−15.0

−17.5

OUTPUT LEVEL

(dB FS)

Table 32 AGC time constant settings

AT2

0

1

1

1

0

1

0

0

AT1

0

0

1

1

1

0

0

1

AT0

0

1

0

1

1

0

1

0

ATTACK TIME

(ms)

11

11

16

21

16

11

16

21

DECAY TIME

(ms)

100

100

200

200

200

400

400

400

2002 May 16 20

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

7.21.4

DATA1 CONTROL

Table 33 Data transfer of type ‘DATA1’

BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

PL5 PL4 PL3 PL2 PL1 PL0 peak level value (6 bits)

READ-OUT DATA

7.21.4.1

Peak level value

A 6-bit value to indicate the peak level value of the playback data. The largest value of the left and right channel data in the playback signal path is held since the last read-out of the microcontroller.

Table 34 Peak level read-out data

PL5

:

1

0

0

0

:

0

0

1

1

0

0

0

0

0

PL4

0

0

0

0

0

0

0

0

:

1

1

:

1

1

1

PL3

0

0

0

0

0

:

1

0

0

0

:

0

0

1

1

PL2

0

0

0

0

1

:

1

0

1

1

:

1

1

1

1

Notes

1. Peak value (dB) = (Peak level

− 63.5) × 5 × log 2.

2. For peak data >010011, the error in the peak value is <

×

4 log 2

3. For peak data <010100, the error is larger due to limited bit length.

PL1

0

0

1

1

0

0

1

1

:

1

0

:

0

1

1

PL0

0

1

0

1

0

1

0

1

:

1

0

:

1

0

1 n.a.

n.a.

−84.29

:

note 2 note 3

:

−2.87

−1.48

−∞

PEAK

VALUE

(1)

(dB) n.a.

n.a.

−90.31

n.a.

0.00

2002 May 16 21

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Product specification

UDA1341TS

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); V

DDD respect to ground; T amb

= 25

°C; unless otherwise specified.

= V

DDA

= 3 V; all voltages measured with

I

I

SYMBOL

V

DD

T xtal(max)

T stg

T amb

V es lu(prot) sc(DAC)

PARAMETER supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling latch-up protection current

DAC short-circuit current: output short-circuited to V output short-circuited to V

SSA(DAC)

DDA(DAC)

CONDITIONS MIN.

note 1

−65

−20

note 2 note 3

T amb

= 125

°C; V

DD

T amb

note 4

= 0

°C; V

DD

= 3.6 V

= 3.0 V;

−2000

−250

MAX.

5.0

150

+125

+85

+2000

+250

200

482

346

V

V

V

°C

°C

°C

UNIT mA mA mA

Notes

1. All V

DD and V

SS

connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 k

Ω series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 2.5

μH series inductor.

4. DAC operation cannot be guaranteed after a short-circuit has occurred.

9 THERMAL CHARACTERISTICS

SYMBOL

R th(j-a)

PARAMETER thermal resistance from junction to ambient

CONDITIONS in free air

VALUE

90

UNIT

K/W

10 DC CHARACTERISTICS

V

DDD

= V

DDA

= 3 V; T amb

= 25

°C; R

L otherwise specified.

= 5 k

Ω; all voltages measured with respect to ground (pins 1, 11 and 27); unless

CONDITIONS MIN.

TYP.

MAX.

UNIT

I

I

SYMBOL

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDD

I

DDA(ADC)

PARAMETER

ADC analog supply voltage

DAC analog supply voltage digital supply voltage

ADC analog supply current

DDA(DAC)

DDD

DAC analog supply current digital supply current

note 1 note 1 note 1

operation mode

ADC power-down operation mode

DAC power-down operation mode

DAC power-down

ADC power-down

2.4

2.4

2.4

3.0

3.0

3.0

12.5

6.0

7.0

50

7.0

4.0

3.0

3.6

3.6

3.6

V

V

V mA mA mA

μA mA mA mA

2002 May 16 22

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

SYMBOL PARAMETER CONDITIONS MIN.

TYP.

MAX.

UNIT

Digital input pins

V

IH

V

IL

|I

LI

|

C i

HIGH-level input voltage

LOW-level input voltage input leakage current input capacitance

0.8V

−0.5

DDD

Digital output pins

V

OH

V

OL

HIGH-level output voltage

LOW-level output voltage

Analog-to-digital converter

V

V

R

C i i

ADCP

ADCN

R o(ref)

I

I

OH

OL

=

−2 mA

= 2 mA

0.85V

− positive reference voltage

− negative reference voltage

V ref

reference output resistance pin 28 input resistance input capacitance measured at 1 kHz stand-alone mode

− double differential mode

0.0

DDD

Programmable gain amplifier (input channel 2)

R i input resistance microphone mode double differential mode

V

DDA

0.0

24

12.5

6.25

20

V

DDD

+ 0.5 V

0.2V

10

DDD

V

μA

10 pF

0.4

0.0

V

V

V

V k

Ω k

Ω k

Ω pF

12.5

>1

− k

Ω

M

Ω

Digital-to-analog converter

R o

I o(max)

R

L

C

L output resistance maximum output current load resistance load capacitance

Reference voltage

V ref reference voltage

(THD + N)/S < 0.1%

note 2

3

0.13

0.22

3.0

50

Ω mA k

Ω pF with respect to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

Notes

1. All power supply pins (V

DD

and V

SS

) must be connected to the same external power supply unit.

2. When higher capacitive loads (above 50 pF) must be driven then a resistor of 100

Ω

must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier.

2002 May 16 23

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

11 AC CHARACTERISTICS (ANALOG)

V

DDD

= V

DDA

= 3 V; f i

= 1 kHz; f s

= 44.1 kHz; T amb

(pins 1, 11 and 27); unless otherwise specified .

= 25

°C; R

L

= 5 k

Ω; all voltages measured with respect to ground

TYP.

MAX.

UNIT SYMBOL PARAMETER CONDITIONS

Analog-to-digital converter

V i(rms)

Δ

V i input voltage (RMS value)

notes 1 and 2

unbalance between channels

(THD + N)/S total harmonic distortion-plus-noise to signal ratio stand-alone mode

0 dB

−60 dB; A-weighted double differential mode

S/N

α cs

PSRR signal-to-noise ratio channel separation power supply rejection ratio f

V i

= 0 V; A-weighted stand-alone mode

− double differential mode

− ripple

= 1 kHz;

V ripple(p-p)

= 30 mV

Manual gain mode (AGC disabled)

0 dB

−60 dB; A-weighted

G min

G max

G step minimum gain maximum gain digital gain step

Programmable gain amplifier

V i(rms)

(THD + N)/S input voltage (RMS value) at full-scale

−3 dB setting

0 dB setting

3 dB setting

9 dB setting total harmonic distortion-plus-noise to signal ratio

15 dB setting

21 dB setting

27 dB setting at 0 dB

−3 dB setting

0 dB setting

3 dB setting

9 dB setting

15 dB setting

21 dB setting

27 dB setting

MIN.

1.0

0.1

−85

−37

−90

−40

97

100

100

30

−3

60.5

0.5

1414

1000

708

355

178

89

44

−75

−85

−85

−85

−80

−75

−75

−80

−33

−85

−36

V dB dB dB dB dB dB dB dB dB dB dB dB mV mV mV mV mV mV mV dB dB dB dB dB dB dB

2002 May 16 24

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

SYMBOL PARAMETER

(THD + N)/S total harmonic distortion-plus-noise to signal ratio

CONDITIONS at

−60 dB; A-weighted

−3 dB setting

0 dB setting

3 dB setting

9 dB setting

15 dB setting

27 dB setting

Digital-to-analog converter

V o(rms)

Δ

V o

output voltage (RMS value) note 3

unbalance between channels

(THD + N)/S total harmonic distortion-plus-noise to signal ratio

S/N

α cs

PSRR signal-to-noise ratio channel separation

0 dB

−60 dB; A-weighted code = 0; A-weighted power supply rejection ratio f ripple

= 1 kHz;

V ripple(p-p)

= 100 mV

MIN.

TYP.

tbf tbf tbf tbf

−37 tbf

900

0.1

−91

−40

100

100

50

MAX.

−86

UNIT dB dB dB dB dB dB mV dB dB dB dB dB dB

Notes

1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 k

Ω is used in series with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS).

2. The ADC input signal scales inversely proportional with the power supply voltage.

3. The DAC output voltage scales linear with the DAC analog supply voltage.

2002 May 16 25

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Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

12 AC CHARACTERISTICS (DIGITAL)

V

DDD

= V

DDA

= 2.7 to 3.6 V; T amb

=

−20 to +85 °C; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified.

MIN.

TYP.

MAX.

UNIT SYMBOL PARAMETER CONDITIONS

System clock timing (see Fig.8)

t t

T sys

CWL

CWH clock cycle time

LOW-level pulse width

HIGH-level pulse width t

Serial input/output data timing (see Fig.9)

t t t t t t t t

T cy f

BCK(H)

BCK(L) r s;DATI h;DATI d;DATO(BCK) d;DATO(WS) t h;DATO t s;WS t h;WS bit clock cycle time bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time data output delay time

(from BCK falling edge) data output delay time

(from WS edge) data output hold time word select set-up time word select hold time

MSB-justified format

Microcontroller L3-interface timing (see Figs 5 and 6)

T cy(CLK)(L3) t

CLK(L3)H t

CLK(L3)L t su(L3)A t h(L3)A t su(L3)D t h(L3)D t su(L3)DA h(L3)DA

L3CLOCK

L3CLOCK HIGH time

L3CLOCK LOW time

L3MODE set-up time

L3MODE hold time

L3MODE set-up time

L3MODE hold time

L3DATA set-up time

L3DATA hold time addressing mode addressing mode data transfer mode data transfer mode data transfer and addressing mode data transfer and addressing mode t stp(L3)

L3MODE halt time f sys

= 256f s f sys

= 384f s f sys

= 512f s f f sys

< 19.2 MHz sys

≥ 19.2 MHz f f sys

< 19.2 MHz sys

≥ 19.2 MHz

78

52

39

20

0

0.30T

sys

0.40T

sys

0.30T

sys

0.40T

sys

300

100

100

0

20

10

500

250

250

190

190

190

190

190

30

190

88

59

44

131

87

66

0.70T

sys

0.60T

sys

0.70T

sys

0.60T

sys

20

20

80

80

− ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

2002 May 16 26

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS handbook, full pagewidth tCWH

Tsys tCWL

MGL443

Fig.8 System clock timing.

handbook, full pagewidth

WS

BCK tr tBCK(H) tf th;WS

Tcy tBCK(L) td(DATO)(WS) ts;WS th;DATO td(DATO)(BCK)

DATAO ts;DATI

DATAI th;DATI

MGG840

2002 May 16

Fig.9 Serial interface timing.

27

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

13 APPLICATION INFORMATION

Product specification

UDA1341TS

+ 3 V ground system clock overflow flag left line input right left

MIC input right

L1

BLM32A07

L2

BLM32A07

C12

100 μ F

(16 V)

R30

47 Ω

C1

47 μ F

(16 V)

C6

C4

47 μ F

(16 V)

47 μ F

(16 V)

C7

47 μ F

(16 V)

VDDA VDDD

VDDA

VDDD

C11

100 μ F

(16 V)

C2

100 μ F

(16 V)

C21

R21

1 Ω

C25

C9

100 μ F

(16 V)

C29

R28

1 Ω

SYSCLK

12

1

100 nF

(63 V)

VSSA(ADC)

3

100 nF

(63 V)

100 nF

(63 V)

VDDA(ADC) VADCN VADCP VSSD

5 7 11 10

VDDD

DATAO

18

BCK

16

WS

17

DATAI

19

OVERFL

9

28

Vref

VINL1

2

C22

100 nF

(63 V)

26

VOUTL

C5

47

μ

F

(16 V)

C3

47 μ F

(16 V)

R23

R22

100 Ω

10 k Ω

UDA1341TS

VINR1 4

VINL2

6

24

VOUTR

C8

47 μ F

(16 V)

R26

R27

100 Ω

10 k Ω

VINR2 8

L3MODE

13

L3CLOCK

14

L3DATA

15

23

QMUTE

AGCSTAT

22

TEST2

21

TEST1

20

27

VSSA(DAC)

C27

25

VDDA(DAC)

100 nF

(63 V)

C10

100 μ F

(16 V)

R29

1 Ω

VDDA

MGR433 left output right output

Fig.10 Application diagram.

2002 May 16 28

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

14 PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

Product specification

UDA1341TS

SOT341-1

Z

28 y

1 pin 1 index e

D c

E

H

E

15 b p

14 w M

A

2

A

1

L

L p detail X

Q

θ

A

A

X v

M A

0 2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c mm 2

0.21

0.05

1.80

1.65

0.25

0.38

0.25

0.20

0.09

D

(1)

10.4

10.0

E

(1)

5.4

5.2

e

0.65

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

OUTLINE

VERSION

SOT341-1

IEC

REFERENCES

JEDEC JEITA

MO-150

H

E

7.9

7.6

L

1.25

L p

1.03

0.63

Q

0.9

0.7

v w y

0.2

0.13

0.1

EUROPEAN

PROJECTION

Z

(1)

1.1

0.7

ISSUE DATE

99-12-27

03-02-19

θ

8 o

0 o

2002 May 16 29

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

15 SOLDERING

15.1

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is recommended.

15.2

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from

215 to 250

°C. The top-surface temperature of the packages should preferable be kept below 220

°C for thick/large packages, and below 235

°C for small/thin packages.

15.3

Reflow soldering

Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45

° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250

°C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

15.4

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300

°C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between

270 and 320

°C.

2002 May 16 30

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

15.5

Suitability of surface mount IC packages for wave and reflow soldering methods

SOLDERING METHOD

PACKAGE (1)

WAVE

REFLOW (2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

PLCC

(4) , SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO not suitable not suitable

(3)

suitable suitable suitable suitable

not recommended (4)(5)

suitable

not recommended (6)

suitable

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your NXP Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45

° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2002 May 16 31

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

16 DATA SHEET STATUS

DOCUMENT

STATUS (1)

Objective data sheet

PRODUCT

STATUS

(2)

DEFINITION

Development This document contains data from the objective specification for product development.

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary data sheet

Product data sheet

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

17 DISCLAIMERS

Limited warranty and liability

⎯ Information in this document is believed to be accurate and reliable.

However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort

(including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial

sale of NXP Semiconductors.

Right to make changes

⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use

⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications

⎯ Applications that are described herein for any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP

Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

2002 May 16 32

NXP Semiconductors

Economy audio CODEC for MiniDisc (MD) home stereo and portable applications

Product specification

UDA1341TS

Limiting values

⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and

(proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale

⎯ NXP

Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP

Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license

⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control

⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

Quick reference data

⎯ The Quick reference data is an extract of the product data given in the Limiting values and

Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products

⎯ Unless this data sheet expressly states that this specific NXP

Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies

NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP

Semiconductors’ standard warranty and NXP

Semiconductors’ product specifications.

2002 May 16 33

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.

Contact information

For additional information please visit: http://www.nxp.com

For sales offices addresses send e-mail to: [email protected]

© NXP B.V. 2010

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 753505/04/pp34 Date of release: 2002 May 16 Document order number: 9397 750 09805

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