Master of Technology Electrical Engineering Rahul Verma

Master of Technology  Electrical Engineering Rahul Verma
Study and Comparison of various Digital Control
Techniques for DC-DC Converters
Thesis submitted in partial fulfillment of the requirements for the degree of
Master of Technology
in
Electrical Engineering
(Specialization: Control & Automation)
by
Rahul Verma
Department of Electrical Engineering
National Institute of Technology Rourkela
Rourkela, Odisha, 769008, India
May 2015
Study and Comparison of various Digital Control
Techniques for DC-DC Converters
Dissertation submitted in
in May 2015
to the department of
Electrical Engineering
of
National Institute of Technology Rourkela
in partial fulfillment of the requirements for the degree of
Master of Technology
by
Rahul Verma
(Roll 213EE3316 )
under the supervision of
Prof. Susovon Samanta
Department of Electrical Engineering
National Institute of Technology Rourkela
Rourkela, Odisha, 769008, India
May 2015
ii
Certificate
This is to certify that the work in the thesis entitled “Study and Comparison of various Digital
Control Techniques for DC-DC Converters” by Rahul Verma is a record of an original research
work carried out by him under my supervision and guidance in partial fulfillment of the
requirements for the award of the degree of Master of Technology with the specialization of
Control & Automation in the department of Electrical Engineering, National Institute of
Technology Rourkela. Neither this thesis nor any part of it has been submitted for any degree or
academic award elsewhere.
Place: NIT Rourkela
Prof. Susovon Samanta
Date: May, 2015
Professor, EE Department
NIT Rourkela, Odisha
iii
Acknowledgment
First and Foremost, I would like to express my sincere gratitude towards my supervisor Prof.
Susovon Samanta for his advice during my project work. He has constantly encouraged me to
remain focused on achieving my goal. His observations and comments helped me to establish the
overall direction of the research and to move forward with investigation in depth. He has helped
me greatly and been a source of knowledge.
I extend my thanks to our HOD, Prof. A.K Panda and to all the professors of the department
for their support and encouragement.
I am really thankful to my seniors especially Mahendra Chandra Joshi, and Muralidhar Killi
and my batchmate Debashish Mohapatra who helped me during my course work and also in
writing the thesis.
Also I would like to thanks my all friends particularly Amit, Anupam, Ankit, Krishnaja and
Pramisha for their personal and moral support. My sincere thanks to everyone who has provided
me with kind words, a welcome ear, new ideas, useful criticism, or their invaluable time, I am truly
indebted.
I must acknowledge the academic resources that I have got from NIT Rourkela. I would like
to thank administrative and technical staff members of the Department who have been kind enough
to advise and help in their respective roles.
Last, but not the least, I would like to acknowledge the love, support and motivation I received
from my parents and therefore I dedicate this thesis to my family.
Rahul Verma
213EE3316
iv
Abstract
Recent years have seen enormous amount of research and development in designing a
highly efficient power supply that has good transient performance. In present scenario portable
hand held applications have been dominated by integrated power supply management. In this
thesis voltage mode control and current mode control of DC-DC converter has been presented.
The overall design of a closed loop DC-DC converter is divided into the following different parts.
First of all design of open loop Buck or Boost converter, state space analysis of the converter to
find the open loop transfer function, and design of the compensator. State space averaging and
then linearization is applied to obtain the small signal model of the converter to derive the various
transfer functions. After obtaining the control to output transfer function, a compensator is
designed to stabilize the closed loop response of the system. Normally, the compensator is
designed in in analog domain and then it is transformed into equivalent discrete domain by using
some transformation method like Backward Euler method, Bilinear method or pole-zero matching
etc. Z-domain transfer function of the converter and modulator is needed for designing a digital
controller directly. In the feedback loop, an analog to digital converter (ADC) is used before the
compensator and a digital pulse width modulator (PWM) is used after the compensator. For
Zeigler-Nichols tuned PID controllers a new tuning method is introduced for fast transient
response and application requiring precise control. The performance of the system having autotuned PID controller is improved as compared to Z-N tuned PID controllers and robustness and
the dead time is controlled by changing the parameter of the controller. Current mode control is
used to improve the dynamic response of the system. Normally, there are two control loop in the
current mode control, one is voltage control loop and another is current control loop. There are
different type of digital current mode control techniques like peak current mode control, average
current mode control and valley current mode control. The dynamic response of current mode
control is better than voltage mode control.
v
Table of Contents
Certificate ....................................................................................................................................... iii
Acknowledgment ........................................................................................................................... iv
Abstract ........................................................................................................................................... v
List of Figures .............................................................................................................................. viii
List of Abbreviations ...................................................................................................................... x
1
2
Introduction ............................................................................................................................. 1
1.1
Background ...................................................................................................................... 1
1.2
Motivation ........................................................................................................................ 2
1.3
Objective .......................................................................................................................... 2
1.4
Literature Review ............................................................................................................. 3
Small Signal Modeling of DC-DC Converter ......................................................................... 5
2.1
Buck Converter ................................................................................................................ 5
2.1.1
Derivation of State Equations ................................................................................... 7
2.1.2
State-Space Averaging ............................................................................................ 10
2.1.3
Linearization ........................................................................................................... 11
2.2
Boost Converter.............................................................................................................. 13
2.2.1
3
Digital Feedback Control ...................................................................................................... 20
3.1
Pulse Width Modulator .................................................................................................. 21
3.1.1
Dynamic response of analog PWM modulator ....................................................... 23
3.1.2
Dead time in PWM modulator ................................................................................ 24
3.2
Digital Pulse Width Modulator ...................................................................................... 26
3.2.1
Quantization and Limit Cycle ................................................................................. 28
3.2.2
Elimination of Limit Cycle ..................................................................................... 29
3.3
4
Derivation of state equations .................................................................................. 16
Design of PID controller ................................................................................................ 30
3.3.1
Root Locus Method................................................................................................. 30
3.3.2
Frequency Response Method .................................................................................. 31
3.3.3
Ziegler-Nichols Tuning Method ............................................................................. 33
3.3.4
Analog to digital PID .............................................................................................. 35
Voltage Mode Control .......................................................................................................... 37
4.1
Voltage Mode controlled Buck Converter ..................................................................... 37
vi
4.1.1
Simulation Result .................................................................................................... 38
4.1.2
Hardware Result...................................................................................................... 41
4.2
Voltage Mode controlled Boost Converter .................................................................... 43
4.2.1
5
Current Mode Control ........................................................................................................... 46
5.1
Current Mode Control for Buck Converter without Slope Compensation..................... 46
5.1.1
Principle of Current Control Law ........................................................................... 47
5.1.2
Result and Discussion ............................................................................................. 49
5.1.3
Hardware Output ..................................................................................................... 52
5.2
6
Simulation Result .................................................................................................... 45
Auto-tuned PID controller for Fast Transient Response of Buck Converter ................. 54
Conclusion ............................................................................................................................ 58
Future Scope ................................................................................................................................. 59
References ..................................................................................................................................... 60
vii
List of Figures
Fig. 2.1 Circuit diagram of open loop asynchronous Buck converter ............................................ 5
Fig. 2.2 Inductor current of Buck converter in steady state ............................................................ 6
Fig. 2.3 Circuit diagram of Buck converter during ON time .......................................................... 7
Fig. 2.4 Circuit diagram of Buck converter during OFF time ........................................................ 9
Fig. 2.5 Block diagram of the open loop power stage of Buck converter .................................... 13
Fig. 2.6 Circuit diagram of open loop asynchronous Boost converter ......................................... 14
Fig. 2.7 Capacitor current of Boost converter in steady state ....................................................... 15
Fig. 2.8 Circuit diagram of Boost converter during ON time ....................................................... 16
Fig. 2.9 Circuit diagram of Boost converter during OFF time ..................................................... 18
Fig. 3.1 Block diagram of closed loop DC-DC converter ............................................................ 20
Fig. 3.2 Naturally sampled implementation of a PWM modulator............................................... 22
Fig. 3.3 Dynamic response of PWM modulator ........................................................................... 24
Fig. 3.4 Circuit diagram of synchronous buck converter.............................................................. 24
Fig. 3.5 Dead time representation of PWM signal........................................................................ 25
Fig. 3.6 Digital PWM modulator typical structure ....................................................................... 26
Fig. 3.7 Analysis plot of the digital PWM modulator................................................................... 27
Fig. 3.8 A general uniformly sampled PWM ................................................................................ 27
Fig. 3.9 Qualitative behaviour of Vout with ADC resolution greater than the DPWM resolution 28
Fig. 3.10 Qualitative behaviour of Vout with DPWM resolution greater than ADC resolution and
with integral term .......................................................................................................................... 29
Fig. 3.11 Block diagram of a closed loop system ......................................................................... 31
Fig. 3.12 Unit step Response of the open loop system ................................................................. 33
Fig. 3.13 Closed loop system with proportional controller .......................................................... 34
Fig. 3.14 Sustained oscillation with period Pcr ............................................................................. 34
viii
Fig. 4.1 Voltage mode controlled Buck converter ........................................................................ 37
Fig. 4.2 Step response of the open loop and closed loop system .................................................. 38
Fig. 4.3 Bode plot of the system ................................................................................................... 39
Fig. 4.4 Simulation output voltage of buck converter with constant load .................................... 39
Fig. 4.5 Simulation output voltage of buck converter with small load variation.......................... 40
Fig. 4.6 Simulation output of buck converter with large load variation ....................................... 40
Fig. 4.7 Hardware setup for voltage mode control ....................................................................... 41
Fig. 4.8 Output voltage and PWM signal with 2V reference signal ............................................. 41
Fig. 4.9 Output voltage and PWM signal with 3V reference signal ............................................. 42
Fig. 4.10 AC coupled output voltage ............................................................................................ 43
Fig. 4.11 Output voltage of boost converter ................................................................................. 45
Fig. 4.12 Load current of the boost converter ............................................................................... 45
Fig. 5.1 Block diagram of current mode control without slope compensation ............................. 46
Fig. 5.2 Steady state inductor current ........................................................................................... 47
Fig. 5.3 Step Response of the open loop and closed loop system ................................................ 50
Fig. 5.4 Bode Plot of the system ................................................................................................... 51
Fig. 5.5 Output Voltage Response of current mode controlled Buck converter ........................... 51
Fig. 5.6 Inductor current of current mode controlled Buck converter .......................................... 52
Fig. 5.7 Hardware setup for current mode control ........................................................................ 52
Fig. 5.8 Inductor current and output voltage with 1V reference signal ........................................ 53
Fig. 5.9 Inductor current and output voltage with 2V reference signal ........................................ 53
Fig. 5.10 Output voltage with AC coupling.................................................................................. 54
Fig. 5.11 Simulation diagram of auto-tuned buck converter ........................................................ 56
Fig. 5.12 Variable load and input voltage plot.............................................................................. 56
Fig. 5.13 Output voltage of the auto-tuned buck converter .......................................................... 57
Fig. 5.14 Load current variation of the auto-tuned buck converter .............................................. 57
ix
List of Abbreviations
AC: Alternating Current
BW: Bandwidth
CCM: Continuous Conduction Mode
D: Duty ratio
DC: Direct Current
DCM: Discontinuous Conduction Mode
CMC: Current Mode Control
DPWM: Digital Pulse Width Modulator
ESR: Effective Series Resistance
GCF: Gain Cross-over Frequency
GM: Gain Margin
MOSFET: Metal Oxide Semiconductor Field Effect Transistor
PCF: Phase Cross-over Frequency
PM: Phase Margin
PWM: Pulse Width Modulator
VMC: Voltage Mode Control
ZOH: Zero Order Hold
x
CHAPTER 1
1 Introduction
1.1
Background
From the last decade the power electronic converter related to DC energy source came into
focus with the increasing worldwide interest in the electronic gadgets like computer, cellphone,
digital sound system and home appliance. These electronic gadgets requires different power
supply, voltage and current rating. A suitable voltage regulator is required for the power supply of
these electronics gadgets. A DC-DC converter is required to produce a constant stable DC output
voltage while the input voltage and load current is varies. Earlier the implementation of the control
of switched mode power supplies had been done using analog components due to high bandwidth
and low cost. The need of fast regulation has increased with the increasing performance in the
electronic circuitry. This requirement paved a way for designing higher functionality based on
digital control of power converters. The digital control is having a lot of advantages over analog
control like better noise immunity, flexibility of programming, easy to configure for different
applications, low cost of implementation, low aging factor and ability to implement complex
control algorithms. By controlling the gate pulse of the MOSFET, the closed loop control regulates
the output voltage. The gate pulse of MOSFET is generated by the pulse width modulator (PWM)
and PWM duty cycle is controlled by the PID controller. The closed loop control of the DC-DC
converter can be operated either in voltage mode or current mode. In voltage mode control signal
generated by voltage feedback loop is compared with a fixed frequency external ramp to generate
the gate pulse of MOSFET while in current mode control the controlled output voltage generated
by outer loop is used as reference current for the inner loop and inductor current is compared with
the reference current to generate the gate pulse of the MOSFET. Most of the closed loop DC-DC
converters are employ the voltage mode feedback control but the current mode feedback control
preferred over voltage mode feedback control because of fast inner current loop.
1
1.2 Motivation
The digital controllers are the only solution in the industrial power supply production area.
Nowadays Uninterruptible power supplies (UPSs) and adjustable speed drives (ASDs) are digitally
controlled. One of the main consideration for DC-DC converter is to improve the efficiency of
converter and to produce a constant output voltage in spite of fluctuation the input voltage and
load current. Therefore in spite of operating the MOSFET in active region, it is operated in
saturation and cut-off region as a switch and the control signal of the transistor is binary in nature.
During the ON time of the MOSFET the voltage across the transistor is low therefore power loss
is low. During the OFF time of MOSFET the current in the MOSFET is low therefore power loss
is low. In the converter resistors are avoided and inductor and capacitors are used to obtain low
loss. By using the digital control the output response improves as compared to analog control
methods. By using the digital control auto-tuning and self-analysis strategies can be implemented
which can take care of parameter variation, nonlinearities and construction tolerance of the system.
The software based digital control is having a lot of advantages like better noise immunity,
flexibility of programming, easy to configure for different applications, low cost of
implementation, low aging factor and ability to implement complex control algorithms.
1.3 Objective
The objective of this thesis has been formulated from the above motivations. The main
objective of the thesis has been categorized and is given below:
 To study the insight of DC-DC converters and develop the small signal modelling of
converters to find the open loop transfer function of the DC-DC converters.
 To develop a voltage mode digital closed loop control for the buck and boost converter and
study the effect of sampling in the digital control. Also a comparative study between digital
control and analog control algorithms.
 Implementation of an auto-tuning control algorithm for fast varying input voltage and load
current.
 Implementation of current mode control to improve the dynamic response of the system.
2
1.4 Literature Review
A lot of efforts has been devoted to design a digitally controlled DC-DC converter [1]-[6].
These papers are about the design of digital compensator for the voltage mode control or current
mode control. For designing digital compensator an equivalent s-domain small signal model for
converters with voltage mode digital control has been proposed [5]-[7]. It is a practical way to
design the feedback control system for voltage mode DC-DC converters. Since Laplace-domain
model of DC-DC converters with analog control is very familiar among most of the engineers,
analog techniques are used to design the controller. Therefore, this type of digital controller design
technique is used which unified the intuitiveness of analog control design [8]-[11]. However, first
of all the controller should be designed in Laplace-domain and then Laplace-domain transfer
function of compensator is mapped into z-domain by approximation methods. The continuous
Laplace-domain transfer function can be easily translated into discrete equivalent by using
Backward Euler method, Bilinear method and pole-zero matching. Z-domain transfer function of
the converter and modulator is needed for designing a digital controller directly. Small signal
analysis of digitally controlled converters in z-domain is required to find the transfer function of
converter and modulator in z-domain [12]. There are two nonlinear effects of digitally controlled
DC-DC converters: modulation effect and quantization effect. Due to modulation effect there is a
delay in the feedback of the system. The drawback of the modulator can be improved by using
Laplace and frequency domain models for uniformly sampled pulse width modulator (PWM). Due
to quantization effect there is a steady- state limit cycle in digitally controlled PWM converters.
By applying suitable constraints on the quantization resolution and control law the steady state
limit cycle in the output can be eliminated [13]-[14]. Digital control using Digital signal processors
allows implementation of flexibility of quick change in design parameter, more functional control
methods and single hardware design for multiple system.
The first PI controller was introduced by Foxboro in 1934-1935. However, PI controllers
can over-correct errors and cause closed-loop instability. This happens when the controller reacts
too fast and too aggressively; it creates a new set of errors, even opposite to the real error. This is
known as “hunting” problem. In 1942, Taylor Instrument Company’s Ziegler and Nichols
introduced Ziegler-Nichols (Z-N) tuning rules. Their well-known paper “Optimum settings for
automatic controllers”, presented two procedures for establishing the appropriate parameters for
3
PID controllers. However, the PID controller was not popular at that time, as it was not a simple
concept; the parameters the manufacturers required to be tuned did not make much sense to the
users. The involvement of digital computer for controlling purpose in process control industry
came into account in the 1960s. On 15th march 1959, the implementation of closed loop control by
a digital computer has been done in Texaco’s Port Arthur plant. Afterwards a lot of research has
been done in the field of digital PID controller and the implementation of digital PID controller in
microprocessor has been done [15]. Digital control is having a lot of advantages like better noise
immunity, flexibility of programming, easy to configure for different applications, low cost of
implementation, low aging factor and ability to implement complex control algorithms.
The Z-N tuning of PID controllers is not useful for fast transient response and application
requiring precise control. To overcome this problem some modification has been made in ZeiglerNichols tuning method [16]. For Zeigler-Nichols tuned PID controllers a new auto-tuning method
is presented for nonlinear and higher order system with fast transient response [17]. The
performance of the system having auto-tuned PID controller is improved as compare to Z-N tuned
PID controllers and robustness and the dead time is controlled by changing the parameter of the
controller.
Most of the closed loop DC-DC converters are employ the voltage mode feedback control
but the current mode feedback control preferred over voltage mode feedback control because of
fast inner current loop [18]. Different type of digital current mode control techniques like peak
current mode control, average current mode control and valley current mode control are
implemented [19-21]. The dynamic response of current mode control is better than voltage mode
control.
4
CHAPTER 2
2 Small Signal Modeling of DC-DC Converter
2.1 Buck Converter
Buck converter is used to step down the input voltage. The general configuration of open
loop asynchronous buck converter is shown in Fig.2.1. Asynchronous buck converter can be
converted into synchronous buck converter by replacing the diode with an identical MOSFET and
the controlling pulse of this MOSFET will be 180̊ out of phase with the controlling pulse of the
first MOSFET.
L
N  MOSFET
rL
iL
C
 (t)
vin
+
+
vc
-
Diode
R
rc
v0
iinj
-
Fig. 2.1 Circuit diagram of open loop asynchronous Buck converter
For the system to be in continuous conduction mode (CCM), specific value of capacitor
and inductor are required. To determine the value of inductor (L) and capacitor (C) applied input
voltage ( Vin ) and nominal output voltage ( V0 ) is required.
Due to very high switching frequency of the MOSFET in the Buck converter the switch
produces discontinuous current but the inductor keeps the output current continuous. During ON
state of the MOSFET an electric current flows from source to load and inductor gets charged.
During OFF state of the MOSFET no electric current flows from source to load. In this state the
inductor acts as a source and releases its stored energy i.e. inductor discharges, hence there is a
5
current flow from inductor to load. The inductor current
iL
in CCM is shown in Fig.2.2. The
inductor current should never reach zero value in the continuous conduction mode.
imax
iL
Inductor Current
iL
iLavg  i0avg
imin
T on
Toff
Toff
Ton
Ton
Toff
Time
Fig. 2.2 Inductor current of Buck converter in steady state
From the fig. 2.2 it can be seen that the inductor current varies between a maximum current imax
and minimum current imin and the difference between maximum and minimum current is peak to
peak inductor current ripple iL . In steady state the average inductor current iLavg is equal to
average output current i0avg . The inductor current should never exceed the saturation current
otherwise there will be instantaneous increase in the inductor current and insignificant inductance
loss. The key factor for choosing the inductor value is peak to peak inductor current iL . The peak
to peak inductor current should be 30-40% of average output current i0avg . The equation for finding
inductor value L in CCM is given below.
L
V0 1  Dmin  T
I L max
Where,
 V0
Average output voltage (Volt)
 I L max Maximum inductor ripple current (Amp.)
6
(2.1)
 T
Switching time period (Sec.)
 Dmin
Minimum duty ratio
The capacitor maintains constant output voltage and makes output voltage ripple free. In
practical there is always an equivalent series resistance (ESR) present with the capacitor. The
capacitor should be selected with minimum ESR. For certain output voltage ripple the maximum
ESR of the capacitor and the capacitor value can be calculated with the following equations.
ESR 
C
V0ripple
(2.2)
I L
I LT
8Vc
(2.3)
Where,
 V0ripple Output voltage ripple (Volt)
 I L
Inductor current ripple (Amp.)
 Vc
Capacitor voltage ripple (Volt)
2.1.1 Derivation of State Equations
There are two different system configuration of buck converter in CCM are considered,
one during ON time of MOSFET and another during OFF time of the MOSFET. The circuit
diagram of buck converter during ON time of MOSFET is shown in Fig. 2.3.
L
rL
iL
C
-
vin
+
+
vc
R
rc
Fig. 2.3 Circuit diagram of Buck converter during ON time
7
v0
-
iinj
From Fig. 2.3 the following equations are obtained:
diL 1
  vin  v0 
dt L
(2.4)
dvc 1 
v

  iL  0  iinj 
dt C 
R

(2.5)
v


v0  vc  Rc  iL  0  iinj 
R


(2.6)
By rearranging eq. (2.6) it can be written as:
rc
v0  vc  rc  iL  iinj 
R
(2.7)
vc  rc  iL  iinj 
r
1 c
R
(2.8)
rc  R
r R
R
iL 
vc  c
iinj
rc  R
rc  R
rc  R
(2.9)
v0 
v0 
v0 
On substituting the value of v 0 from eq. (2.9) in eq. (2.4) and (2.5):
r R
r R
diL
R
1
 c
iL 
vc  vin  c c iinj
dt
L(rc  R)
L(rc  R)
L
L(rc  R)
(2.10)
dvc 1
rc
rc
1
1
 iL 
iL 
vc 
iinj  iinj
dt C
C(rc  R)
C(rc  R)
C(rc  R)
C
(2.11)
On simplifying eq. (2.11) it can be written as:
dvc
R
1
R

iL 
vc 
iinj
dt C(rc  R)
C(rc  R)
C(rc  R)
(2.12)
The open loop buck converter shown in Fig. 2.1 is a second order system since it is having
two energy storage component. Let the current of inductor iL and capacitor voltage vc be chosen
as state variables. Let input voltage vin and load current iinj as input signals and output voltage v 0
8
as output signal. The state space system obtained by using eq. (2.9), (2.10), and (2.12) are as
follows:
 dx(t)
 A1  x(t)  B1  u (t)

 dt
 y (t)  C1  x(t)  F1  u (t)
(2.13)
After substituting the matrixes A1 , B1 , C1 , F1 state variable x(t) , input signal u (t) , and output
signal y (t) in eq. (2.13):
rc .R



L(rc  R)
iL 
 
R
vc  
 C(r  R)
c

 r .R
v0   c
 (rc  R)
R

1

L(rc  R) iL   L
 
1
 vc  

0
C(rc  R) 


rc .R

L(rc  R)  vin 
 
R
 iinj 

C(rc  R) 
(2.14)
rc .R  vin 
R  iL  
    0 
 
(rc  R)  vc  
(rc  R)  iinj 
(2.15)
When the MOSFET is OFF, the diode is forward bias and the diode is replaced by short circuit.
The circuit diagram of buck converter during OFF time of MOSFET is shown in Fig. 2.4.
L
rL
iL
+
+
C
vc
-
R
rc
v0
iinj
-
Fig. 2.4 Circuit diagram of Buck converter during OFF time
If the input voltage vin is zero, the circuit of buck converter during ON time of MOSFET and OFF
time of MOSFET are same. Hence the state space model of buck converter during OFF can be
obtained by putting the coefficients for vin to zero in eq. (2.13).
9
 dx(t)
 A2  x(t)  B2  u (t)

 dt

 y (t)  C2  x(t)  F2  u (t)
(2.16)
After substituting the matrixes A2 , B2 , C2 , F2 state variable x(t) , input signal u (t) , and output
signal y (t) in eq. (2.16):
rc .R


iL   L(rc  R)
 
R
vc  
 C(r  R)
c

 r .R
v0   c
 (rc  R)
rc .R
R



0


L(rc  R) iL 
L(rc  R)  vin 
 
 
1
 vc  
R
 iinj 

0 


C(rc  R) 
C(rc  R) 

(2.17)
rc .R  vin 
R  iL  
    0 
 
(rc  R)  vc  
(rc  R)  iinj 
(2.18)

2.1.2 State-Space Averaging
In continuous conduction mode the buck converter ON time and OFF time configurations
are shown in Fig. 2.3 and 2.4. Let the ON time duration of the MOSFET for nth cycle is d nT and
the OFF time duration is dnT  (1  dn )T . Where dn  Ton T duty ratio of the converter. The state
space equations of the converter can be written as:
Ton : xˆ (t)  A1  x(t)  B1  u(t)
for
nT  t  nT  dnT ,
n  1, 2, ...... (2.19)
Toff : xˆ(t)  A2  x(t)  B2  u(t)
for
nT  dnT  t  (n  1)T ,
n  1, 2,...... (2.20)
The solution of the eq. (2.19) and (2.20) are obtained by integrating them over each period of
operation.


x(n  dn )T  e A1dnT x(nT )  A11 e A1dnT  I B1u

(2.21)

x(n  1)T  e A2dnT x(nT  dnT )  A21 e A2dnT  I B2u
(2.22)
On substituting eq. (2.21) in (2.22):




x(n  1)T  e( A1dn  A2dn )T x(nT )  A11 e( A1dn  A2dn )T  e A2dnT B1u  A11 e A2dnT  I B2u
10
(2.23)
By using linear approximation e AT  1  AT eq. (2.23) is written as:
x(n  1)T  x(nT )   A2dn'  A1d n  T  x(nT )  d n TB1u  d nTB2u
(2.24)
x(n  1)T  x(nT )
  A2 dn  A1d n   x(nT )  ( B1 d n  B2 d n )u
T
(2.25)
By using the forward Euler’s approximation x 
x(n  1)T  x(nT )
eq. (2.25) is written as:
T
x   A1dn  A2 dn  x  ( B1 dn  B2 dn )u
(2.26)
Similarly output state equation is written as:
y   C1dn  C2dn  x  ( F1dn  F2dn )u
(2.27)
2.1.3 Linearization
The linear small signal model of eq. (2.26) and (2.27) can be derived by using perturbation
around a steady state point  X , D,U  . Let d
x  X  xˆ, d  D  dˆ , and u  U  uˆ
(2.28)
On substituting the value of x, d , and u from eq.2.28 in eq. (2.27) and (2.27) and separating the
small signals:
xˆ   A1D  A2 D xˆ   B1D  B2 D uˆ    B1  B2 U   A1  A2  X  dˆ
(2.29)
yˆ   C1D  C2 D xˆ   F1D  F2 D uˆ
(2.30)
Let A1D  A2 D  A, B1D  B2 D  B, C1D  C2 D  C , F1D  F2 D  F , then eq. (2.29) and (2.30) is
rewritten as:
xˆ  Axˆ  Buˆ    B1  B2 U   A1  A2  X  dˆ
(2.31)
yˆ  Cxˆ  Fuˆ
(2.32)
11
After considering the perturbation a constant term the study state value of state variables and duty
ratio are obtained and is given as:
AX  BU  0
(2.33)
Y  CX  FU
By using eq. (2.33) the output variable is expressed as:
Y   CA1B  E U
(2.34)
Let the initial state of the linearized model is zero. The Laplace transform of eq. (2.31) and (2.32)
is written as:
sxˆ (s)  Axˆ  s   Buˆ  s     B1  B2 U   A1  A2  X  dˆ  s 
(2.35)
yˆ  s   Cxˆ  s   Fuˆ  s 
(2.36)
By using superposition theorem eq. (2.35) and (2.36) is simplified as:
ˆ   SI  A Buˆ  s    SI  A
x(s)
1

yˆ  s   C  SI  A Buˆ  s    SI  A
1
1
1
 B  B U   A  A  X  dˆ  s 
1
2
1
2
 B  B U   A  A  X  dˆ  s   Fuˆ  s 
1
2
1
2
(2.37)
(2.38)
By substituting the state space matrixes A, B, C, and F of buck converter in eq. (2.38), the
following transfer functions are obtained for open loop power stage:
Gv0d  s  
vˆ0  s 
vin R 1  srcC 
 2
dˆ  s  s  R  rc  LC  s  L  rc RC   R
(2.39)
Gv0vin  s  
vˆ0  s 
RD 1  srcC 
 2
vˆin  s  s  R  rc  LC  s  L  rc RC   R
(2.40)
vˆ0  s 
sRL 1  srcC 
 2
s  R  rc  LC  s  L  rc RC   R
iˆinj  s 
(2.41)
vin 1  s  R  rc  C 
iˆL  s 
 2
dˆ  s  s  R  rc  LC  s  L  rc RC   R
(2.42)
Gv0iinj  s  
GiL d  s  
12
GiL vin  s  
D 1  s  R  rc  C 
iˆL  s 
 2
vˆin  s  s  R  rc  LC  s  L  rc RC   R
(2.43)
GiLiinj  s  
iˆL  s 
R 1  srcC 
 2
iˆinj  s  s  R  rc  LC  s  L  rc RC   R
(2.44)
The block diagram of the buck converter in terms of the transfer function is shown in Fig. 2.5.
dˆ
Gv0 d  s 
vˆin
Gv0vin s
iˆin j
G v 0 iinj


v̂0

s
GiL d  s 
GiL vin  s 


iˆL

GiL iinj  s 
Fig. 2.5 Block diagram of the open loop power stage of Buck converter
2.2 Boost Converter
Boost converter is used to step-up the DC input voltage. The general configuration of open
loop asynchronous boost converter is shown in Fig. 2.6. The asynchronous boost converter can be
converted into synchronous boost converter by replacing the diode with another similar MOSFET
and the gate pulse of the second MOSFET will be 1800 out of phase with the first MOSFET gate
pulse.
13
L
iL
Diode
C
vin
+
+
N  MOSFET
vc
-
R
rc
 (t)
v0
iinj
-
Fig. 2.6 Circuit diagram of open loop asynchronous Boost converter
For the system to be in continuous conduction mode (CCM), specific value of capacitor
and inductor are required. To determine the value of inductor (L) and capacitor (C) applied input
voltage ( Vin ) and nominal output voltage ( V0 ) is required.
Due to very high switching frequency of the MOSFET in the Boost converter the switch
produces discontinuous current but capacitor keeps output current continuous. During OFF state
of the MOSFET an electric current flows from source to load and capacitor gets charged. During
ON state of the MOSFET no electric current flows from source to load. In this state the capacitor
acts as a source and releases its stored energy i.e. capacitor discharges, hence there is a current
flow from capacitor to load. The capacitor voltage vc in CCM is shown in Fig.2.7. In continuous
conduction mode the capacitor voltage never reaches to zero value.
From Fig. 2.7 it can be seen that the capacitor voltage varies between vmax and vmin and
the difference between the maximum and minimum voltage is peak-to-peak capacitor voltage
ripple vc . The capacitor voltage should never exceed the saturation voltage otherwise there will
be instantaneous increase in output current.
14
vmax
vc
Capacitor Voltage
vc
vcavg  v0avg
vmin
T on
Toff
Toff
Ton
Ton
Toff
Time
Fig. 2.7 Capacitor current of Boost converter in steady state
The equation for finding the value of capacitance C in CCM is given below:
C
v0 DT
vc R
(2.45)
Where,
 v0
Output voltage (Volt)
 vc
Capacitor voltage ripple (Volt)
 D
Duty cycle
 T
Switching time period (Sec.)
The equation for finding the value of inductance L in CCM is giver below:
L
v0 D 1  D  T
iL
Where,
 iL
Inductor current ripple (Amp.)
 v0
Output voltage (Volt)
 T
Switching time period (Sec.)
15
(2.46)
2.2.1 Derivation of state equations
There are two different system configuration of boost converter in CCM are considered,
one during ON time of MOSFET and another during OFF time of the MOSFET. The circuit
diagram of boost converter during ON time of MOSFET is shown in Fig. 2.8.
L
iL
+
+
C
vc
-
vin
rc
R
v0
iinj
-
Fig. 2.8 Circuit diagram of Boost converter during ON time
From Fig. 2.8 the following equations are obtained:
diL 1
 vin
dt L
(2.47)
dvc 1  v0

    iinj 
dt C  R

(2.48)
 v

v0  vc  rc   0  iinj 
 R

(2.49)
By rearranging eq. (2.49) it can be written as:
rc
v0  vc  rciinj
R
(2.50)
vc  rciinj
r
1 c
R
(2.51)
rR
R
vc  c iinj
rc  R
rc  R
(2.52)
v0 
v0 
v0 
16
After substituting the value of v0 from eq. (2.52) to (2.48):
dvc
rc
1
1

vc 
iinj  iinj
dt
C  rc  R 
R  rc  R 
C
(2.53)
On simplifying the eq. (2.53) it can be written as:
dvc
1
R

vc 
iinj
dt
C  rc  R 
C  rc  R 
(2.54)
The open loop boost converter shown in Fig. 2.7 is a second order system since it is having
two energy storage component. Let the current of inductor iL and capacitor voltage vc be chosen
as state variables. Let input voltage vin and load current iinj as input signals and output voltage v 0
as output signal. The state space system obtained by using eq. (2.47), (2.52), and (2.54) are as
follows:
 dx(t)
 A1  x(t)  B1  u (t)

 dt
 y (t)  C1  x(t)  F1  u (t)
(2.55)
After substituting the matrixes A1 , B1 , C1 , F1 state variable x(t) , input signal u (t) , and output
signal y (t) in eq. (2.55):
1
0
0


iL  
 iL    L

1
  0 
 vc  
vc  
0
C(rc  R) 



 vin 
 
R
 iinj 

C(rc  R) 
0

rc .R  vin 
R  iL  
v0  0
    0 
 
(rc  R)  vc  
(rc  R)  iinj 

(2.56)
(2.57)
When the MOSFET is OFF, the diode is forward bias and the diode is replaced by short circuit.
The circuit diagram of boost converter during OFF time of MOSFET is shown in Fig. 2.9.
17
L
iL
+
+
C
vc
-
vin
R
rc
v0
iinj
-
Fig. 2.9 Circuit diagram of Boost converter during OFF time
The circuit of boost converter during OFF time is same as the circuit of buck converter
during ON time. Hence it can be used as model of boost converter during OFF time. By using eq.
(2.13), (2.14), and (2.15) the state space model of boot converter during OFF time is given as:
 dx(t)
 A1  x(t)  B1  u (t)

 dt
 y (t)  C1  x(t)  F1  u (t)
(2.58)
After substituting the matrixes A1 , B1 , C1 , F1 state variable x(t) , input signal u (t) , and output
signal y (t) in eq. (2.58):
rc .R



L(rc  R)
iL 
 
R
vc  
 C(r  R)
c

 r .R
v0   c
 (rc  R)
R

1

L(rc  R) iL   L
 
1
 vc  

0
C(rc  R) 


rc .R

L(rc  R)  vin 
 
R
 iinj 

C(rc  R) 
rc .R  vin 
R  iL  
    0 
 
(rc  R)  vc  
(rc  R)  iinj 
(2.59)
(2.60)
By substituting the state space matrixes A, B, C, and F of boost converter in eq. (2.38), the
following transfer functions are obtained for open loop power stage:
18


vin  D  rc  RD    R 2 D2  sL  rc  R   1  sCrc 
vˆ0  s 
Gv0d  s  
 2
dˆ  s  s LC  rc  R   s  rc RCD  L   RD  rc  RD   rc  R 
(2.61)
vˆ0  s 
RD 1  sCrc 
 2
vˆin  s  s LC  rc  R   s  rc RCD  L   RD  rc  RD   rc  R 
(2.62)
Gv0vin  s  


1  sCrc   rc R 2 DD  rc  R    sLR
vˆ0  s 
Gv0iinj  s  
 2
s LC  rc  R   s  rc RCD  L   RD  rc  RD   rc  R 
iˆinj  s 

vin 
RD
 sC  rc  R  
1 
D   rc  RD 

(2.63)
GiL d  s  
iˆL  s 
 2
dˆ  s  s LC  rc  R   s  rc RCD  L   RD  rc  RD   rc  R 
(2.64)
GiLvin  s  
iˆL  s 
1  sC  rc  R 
 2
vˆin  s  s LC  rc  R   s  rc RCD  L   RD  rc  RD   rc  R 
(2.65)
GiLiinj  s  
iˆL  s 
RD 1  sCrc 
 2
iˆinj  s  s LC  rc  R   s  rc RCD  L   RD  rc  RD   rc  R 
(2.66)
19
CHAPTER 3
3 Digital Feedback Control
Nowadays the controllers are exclusively being implemented in digital domain. In digital
controllers the microprocessor and encoders are used in place of mechanical integrator and
differentiator in analog controllers. The implementation of microprocessor based control is less
expensive than its analog counterpart. Digital control allows implementation of flexibility of quick
change in design parameter, more functional control methods and single hardware design for
multiple system. Due to its speed, versatility, simplicity, reliability, robustness, and flexibility,
most of the industries rely on digital controller for all types of control. Further, the interfacing
between a digital controller and other digital hardware is very easy. Most of the dynamic system
in industries are continuous in nature in spite of discrete. Hence, the output signal of the system is
required to be processed before using in microprocessor. An analog to digital converter is required
to process the output signal of the system from analog to discrete domain. In the same way the
output of the microprocessor is required to be convert in analog domain from discrete domain
before applying to the system. The block diagram of digitally controlled DC-DC converter is
shown in Fig. 3.1.
DC-DC Converter
y0 (t)
ADC
DPWM
y0 n
d ( n)
Control Law
Error
yref
Fig. 3.1 Block diagram of closed loop DC-DC converter
As shown in the above diagram the output of DC-DC converter is converted to discrete signal by
using ADC and the output of the controller is given to digital pulse width modulator to generate
the control signal. The structure of a discrete time PID control law is given below:
20
d  n   K p  e  n   e  n  1  Kd  e  n   e  n  2  2e  n  1   Ki Tse  n   d  n  1
(3.1)
Where, K p is proportional gain, K d is derivative gain, K i is integral gain, e  n  is the error
signal and d  n  id duty cycle at time n .
e  n   yref  n   y0  n 
(3.2)
Where, yref  n  is the reference signal and y0  n  is the digital representation of the output of the
plant.
3.1 Pulse Width Modulator
PWM provides an intermediate amount of electric power between fully OFF and fully ON.
The output of the PWM circuit is a square wave with varying ON and OFF time. Duty cycle is
defined as ON time ( Ton ) to time period ( T ) ratio of the PWM output signal. The analog
implementation of PWM is given below:
21
c t  , m t 
c pk
c t 
m t 
VG1 t 
t
Ts
VG1  t 
+
c t 
-
t
VG2  t 
Voc  t 
m t 
VMO  t 
VG2 t 
COMPARATOR
t
dTs
t
Fig. 3.2 Naturally sampled implementation of a PWM modulator
As shown in the Fig. 3.2 the controlled output of the compensator m  t  and a triangular
pulse c  t  is applied to the input of the compensator. The duty ratio of the PWM output signal
depends on the amplitude of the m  t  . We can explicitly relate signal m  t  to the resulting PWM
duty-cycle. Simple calculations show that, in each modulation period, where a constant m is
assumed, the following equation holds:
m c pk

dTs Ts

d
m
c pk
(3.3)
The above result is correct only if the modulating signal changes slowly along time, with
respect to the carrier signal, i.e. the upper limit of m  t  bandwidth is well below. This means that,
in the hypothesis of a limited bandwidth m  t  , the information carried by this signal is transferred
by the PWM process to the duty-cycle that will change slowly along time following the evolution.
Based on the previous relation, it means that:
22
d
1

m c pk
(3.4)
The duty-cycle, in turn, is transferred to the load voltage waveform by the power converter.
The slow variations of the load voltage average value will therefore copy those of signal m  t  .
Therefore, the modulator transfer function, including the inverter gain will be given by:
V oc V oc d 2VDC


m
d m
c pk
(3.5)
3.1.1 Dynamic response of analog PWM modulator
Indeed, it is possible to see that any change in the modulating signal’s amplitude, provided
that its bandwidth limitation is maintained, implies an “immediate”, i.e. in phase, adjustment of
the resulting duty-cycle. This means that the analog implementation of PWM guarantees the
minimum delay between modulating signal and duty-cycle.
The dynamic response of analog PWM modulator is shown in Fig. 3.3. Where, the
modulating signal m  t  is decomposed in a dc component M and a small signal perturbation m
i.e.m t   M  m . The corresponding duty-cycle has been found, whose small signal component
is called d .
23
Fig. 3.3 Dynamic response of PWM modulator
3.1.2 Dead time in PWM modulator
In the synchronous DC-DC converter to avoid cross conduction dead time is required. A
synchronous buck converter is shown in the Fig. 3.4. When the switch S1 will go from ON to OFF,
at the same time switch S 2 will go from OFF to ON. In this transition period both the switches will
be in ON state and short circuit will occur.
L
S1
I0
iL
C
VGE1
S2
Vdc
+
+
vC
-
rC
VGE 2
R
v0
-
Fig. 3.4 Circuit diagram of synchronous buck converter
The representation of dead time of PWM signal is shown in Fig. 3.5. To avoid cross
conduction, the modulator delays S1 turn-on by a time tdead , applying the VG1 and VG 2 command
signals to the switches. The duration of tdead is long enough to allow the safe turn off of switch S 2
24
before switch S1 is commanded to turn on, considering propagation delays through the driving
Load Voltage
Applied Gate Signal
Logic Gate Signal
circuitry, inherent switch turn off delays and suitable safety margins.
VG1






tdead
tdead

G2
V
VG1
ton1
Ts
ton2
VG 2
V0
t
Ts
t
Ts
t
Ts
t
 V dc



Vdc
Ts
t
Fig. 3.5 Dead time representation of PWM signal
The effect of the dead time application is the creation of a time interval where both switches
are in the off state. Because of that, an undesired difference is created between the duration of the
S1 switch on-time and the actual one that turns into an error in the voltage applied to the load. This
error V0 , whose entity is a direct function of dead time duration and whose polarity depends on
the load current sign, according to the following relation:
25
V0  2VDC
tdead
sign  I 0 
Ts
(3.6)
3.2 Digital Pulse Width Modulator
Digital pulse width modulator (DPWM) provides a digital to time domain conversion. In the
DPWM first of all the time is quantized into discrete slots by using quantizer and then it is
compared with digital input d  n  in spite of a ramp signal. The block diagram of DPWM is shown
in Fig. 3.6.
Clock
Binary Counter
Timer Interrupt
n-bits
Binary Comparator
Match Interrupt
n-bits
Duty Cycle
Fig. 3.6 Digital PWM modulator typical structure
As shown in the Fig. 3.6 the counter is incremented at every clock pulse; any time the
binary counter value is equal to the programmed duty-cycle (match condition), the binary
comparator triggers an interrupt to the microcontroller and at the same time sets the gate signal
low. A typical analysis of the Fig. 3.6 is shown in graph below.
26
Ts
Programmed duty
cycle
Timer count
t
Timer interrupt
request
t
Gate signal
t
Fig. 3.7 Analysis plot of the digital PWM modulator
The gate signal is set high at the beginning of each counting (i.e. modulation) period, where
another interrupt is typically generated for synchronization purposes. The counter and comparator
have a given number of bits, n, which is often 16, but can be as low as 8, in the case a very simple
microcontroller is used.
The dynamics of digitally controlled DC-DC converter are affected by two nonlinear
effects: quantization effect and modulation effect. Due to the modulation effect there is a delay in
the feedback loop. A uniformly sampled PWM is shown in Fig.3.8.
Fig. 3.8 A general uniformly sampled PWM
As shown in the above figure, the input signal m  t  is sampled with a time period Ts and
then the sampled input is hold with a zero order hold (ZOH) and then finally it is compared with
27
a triangular waveform C  t  to generate the gate pulse of the MOSFET. Because of the sample and
hold effect, the response of the modulator to any disturbance, e.g. to one requiring a rapid change
in the programmed duty-cycle value, can take place only during the modulation period following
the one where the disturbance actually takes place. This delay amounts to a dramatic difference
with respect to the analog modulator implementation, where the response could take place already
during the current modulation period, i.e. with negligible delay. The general perception of the
dynamic behavior of the uniformly sampled PWM is improved by using Laplace domain and Zdomain models for uniformly sampled PWM [23].
3.2.1 Quantization and Limit Cycle
There is a limit cycle due to quantization effect of ADC and the DPWM in the digitally
controlled DC-DC converter. Limit cycles refer to steady-state oscillations of output voltage Vout
and other system variables at frequencies lower than the converter switching frequency f sw . As
shown in the Fig. 3.1 there are two quantizer in control loop of a digitally controlled DC-DC
converter: one is in ADC and another in the DPWM. Let us assume that the resolution of the ADC
is N adc bit and the resolution of DPWM is N dpwm . Then, for a buck converter the voltage
quantization for ADC Vadc  Vin 2Nadc and for the DPWM Vdpwm  Vin 2
Ndpwm
. The quantitative
behavior of output voltage Vout in steady state is shown in Fig. 3.9 when ADC resolution is greater
than DPWM resolution.
Vout
voltage
1 bit error bin
Vref
0 bit error bin
-1 bit error bin
DAC levels
-2 bit error bin
ADC level
transient
state state
time
Fig. 3.9 Qualitative behaviour of Vout with ADC resolution greater than the DPWM resolution
28
As shown in the above figure, corresponding to reference voltage Vref , no DPWM level
maps into ADC bin. In the steady state, the control loop will try to drive output voltage Vout into
zero error bin but due to no DPWM level in the zero error bin, it will alternate around zero error
bin between the DPWM levels resulting into steady state limit cycle.
3.2.2 Elimination of Limit Cycle
To eliminate the limit cycle first of all there should be always a DPWM level that maps
into zero error bin and this is possible only when the DPWM resolution is greater than the ADC
resolution i.e. Ndpwm  Nadc . After meeting this condition, there can be still limit cycle if there is no
integral term in the control law. In such case to drive output voltage Vout into zero error bin, the
controller depends on the error signal. When the output voltage will reach in zero error bin, the
error signal will become zero and Vout will drop again out of zero error bin. Repetition of this
sequence will result in the steady state limit cycle. For solving this problem an integral term is
necessary in the control law. So, the second limit cycle condition is 0  Ki  1 . The qualitative
behavior of the output voltage Vout with DPWM resolution greater resolution and with an integral
term included in control law is shown in Fig. 3.10.
Vout
voltage
1 bit error bin
Vref
0 bit error bin
-1 bit error bin
ADC level
DAC levels
-2 bit error bin
transient
state state
time
Fig. 3.10 Qualitative behaviour of Vout with DPWM resolution greater than ADC resolution and with integral term
29
As shown in the above figure after including the integral term in the controller, Vout reaches
into zero error bin. After a transient, the integrator will gradually converges to a value that drives
Vout into zero error bin.
3.3 Design of PID controller
In most of the cases the analog PID controllers are designed firstly and then it is converted
into the equivalent discrete domain by using some transformation method like Backward Euler
method, Bilinear method and pole-zero matching etc. Z-domain transfer function of the converter
and modulator is needed for designing a digital controller directly. Small signal analysis of
digitally controlled converters in z-domain is required to find the transfer function of converter
and modulator in z-domain.
3.3.1 Root Locus Method
Root locus method is used to design the controller transfer function in a closed loop system.
In the root locus method with the gain variation from zero to infinity, the closed loop poles of the
system are plotted in the complex plane. By this method as the gain varies, the stability of the
system and the pole location can be analyzed. In the root locus plot the pole radius from the origin
corresponds to natural frequency and the imaginary part of the pole corresponds to damped natural
frequency. The slowest response of the system determines the settling time of the system. The
settling time of the system can be reduced by placing a pole for left in the left hand plane of the
plot and the overshoot can be decreased by placing a real pole.
First of all the open loop transfer function of the system should be obtained to design the
PID controller using root locus method. In the root locus plot if the locus of the system transfer
function passes through right hand plane then the system is unstable and if the locus remains in
the left hand plane then the system is stable. A system is considered as marginally stable when the
root locus falls in the imaginary axis.
3.3.1.1 Procedure to Design PID Controller using Root Locus Method
The block diagram of a closed loop system is shown in Fig. 3.11. Where Gc is the transfer
function of the PID controller, G p is the plant transfer function and H is the feedback parameter.
30
X  s

Gp
Gc

Ys
H
Fig. 3.11 Block diagram of a closed loop system
The procedure to design the PID controller is given below:
 On the basis of the requirement of the application define a set of transient specification.
 To meet these transient specification, find a pair closed loop poles s1 and s2 .
 Find the steady state error ess of the system and define K I for the defined ess .
 Lump integral term K I S into Gc together with plant transfer function G p .
 Find K p and K d by using the equation given below:
GpGc  s1   1
or
K p  K d s1  
1
Gc  s1 
(3.7)

KI
s1
(3.8)
 Find K p and K d by equating the real and imaginary part of eq. 3.8.
3.3.2 Frequency Response Method
Root locus method is also used to design the controller transfer function in a closed loop
system. From frequency response method it is easy to design a compensator in spite of PID
controller. In frequency response method magnitude and phase of the system is used to meet the
design specification in spite of poles and zeros in root locus method. In the bode plot each term of
PID controller is defined differently. The proportional term adjusts the gain margin and the phase
margin of the system by changing the magnitude of the bode plot. A slope of -20dB/decade is
added to the phase of the system by inclusion of integral term in the PID controller and it tends to
unstabilize the system by changing the phase angle of the system with a constant -90 degree angle.
The effect of the derivative term is just opposite of the integral term. A slope of +20dB/decade is
31
added to the phase of the system by inclusion of derivative term in the PID controller and it tends
to unstabilize the system by changing the phase angle of the system with a constant +90 degree
angle.
The phase margin and gain margin defines the stability of the system in the frequency
response method. The phase cross over frequency is the frequency when the phase angle -180
degree and the gain magnitude below 0 dB at phase cross over frequency is the gain margin of the
system. The gain cross over frequency is the frequency when the gain of the system is unity and
the angle distance above -180 degree at gain cross over frequency is the phase margin of the
system. If the magnitude plot is not reaching below 0 dB line at phase cross over frequency or if
the phase of system is not above -180 degree at gain cross over frequency then the system is
unstable.
3.3.2.1 Procedure to Design PID Controller using Frequency Response Method
 The open loop system should be stable to apply frequency response method.
 Draw the Bode plot of the open loop system.
 On the basis of the requirement of the application define a set phase margin, gain margin
and crossover frequency of the system.
 From the mathematical analysis of the system, the phase margin of the system is depends
on the damping ratio  of the system. The relation between phase margin and  is given
below.
Phase M arg in  tan 1
2
2  1  4
2
(3.9)
4
 The crossover frequency c and natural frequency n are also related to damping ratio as
given in the eq. 3.10.
c
 2 2  1  4 4
n
(3.10)
 On the basis of the design specification of the closed loop system, the K p , K I and K d are
designed so that phase margin and crossover frequency of the system can be fulfilled.
32
3.3.3 Ziegler-Nichols Tuning Method
Based on the transient response of the given system the values of proportional gain K p ,
derivative time Td and integral time Ti are determined using Zeigler-Nichols method. There are two
methods for Zeigler-Nichols tuning, one is based on the step response and another is based on the
critical period Pcr and critical gain K cr . The Zeigler-Nichols tuned PID controller is represented as:


1
Gc  S   K p 1 
 Td S 
 Ti S

(3.11)
3.3.3.1 Ziegler-Nichols Tuning Rule based on Step Response
 Find the unit step response of the system. The graph will look like S-shape as shown in
Fig. 3.12.
c t 
Tangent line at
Inflection point
K
u t 
Plant
c t 
t
L
T
Fig. 3.12 Unit step Response of the open loop system
 Find delay time L and time constant T by drawing a tangent line as shown Fig. 3.12
 A first order system approximated transfer function with a transport delay is given as:
C  S  Ke LS

U  S  TS  1
(3.12)
 According to Ziegler and Nichols the values of K p , Ti and Td are given in the Table 3.1.
33
Table 3.1 Step Response based Ziegler-Nichols tuning of Controller
Type of Controller
P
PI
PID
Kp
T L
0.9T L
1.2T L
Ti

L 0.3
2L
Td
0
0
0.5L
 Put the value of K p , Ti and Td from the Table 3.1 in eq. 3.11 to find the transfer function of
the controller.
3.3.3.2 Ziegler-Nichols Tuning Rule based Critical Period and Critical Gain
 In this method first of all apply only proportional controller K p in the closed loop unity
feedback system as shown in the Fig. 3.13.
r t  

Kp
u t 
Plant
c t 
Fig. 3.13 Closed loop system with proportional controller
 Increase K p from zero to a value where output exhibits oscillation, this value of K p is
called critical gain K cr and the corresponding period is called critical period Pcr as shown in
Fig. 3.14.
c t 
Pcr
t
0
Fig. 3.14 Sustained oscillation with period Pcr
34
 According to Ziegler and Nichols the values of K p , Ti and Td are given in the Table
3.2.Table 3.2 Ziegler-Nichols tuning of Controller based on K cr and Pcr
Type of Controller
P
PI
PID
Kp
0.5Kcr
0.45Kcr
0.6 Kcr
Ti

Pcr 1.2
0.5Pcr
Td
0
0
0.125Pcr
 Put the value of K p , Ti and Td from the Table 3.2 in eq. 3.11 to find the transfer function of
the controller.
3.3.4 Analog to digital PID
Laplace-domain transfer function of compensator is mapped into z-domain by
approximation methods. The continuous Laplace-domain transfer function can be easily translated
into discrete equivalent by using difference approximation, Backward Euler method, ZOH (zeroorder hold), Bilinear method and pole-zero matching. The difference approximation equation is
derived in this section. The approximation of the proportional term K p of the PID controller is
given below:
KPe  n 
(3.13)
The integral term K I of the PID controller using backward rectangular rule is approximated as:
K I Te  n  1
(3.14)
Also, the derivative term K d of PID controller using backward difference is approximated as:
Kd
e  n   e  n  1 
T 
(3.15)
Where, e  n  is the error input to PID controller and T is the sample period.
From the above equations it can be seen that the integral term needed previous information. By
adding the above three equations the complete structure of PID is defined as:
35
d  n   KPe  n  
Kd
e  n   e  n  1  a  n 
T 
a  n   a  n  1  K I Te  n  1
(3.16)
(3.17)
The above equation defines the position algorithm depends on the present control output and the
velocity algorithm for the PID controller is given as:
d  n  1  K P e  n  1 
Kd
e  n  1  e  n  2    a  n  1
T 
a  n  1  a  n  1  K I Te  n  2
(3.18)
(3.19)
By subtracting Eq. (3.18) from Eq. (3.16), the approximation of digital PID controller is given as:
d  n   d  n  1  K P e  n   e  n  1 
Kd
e  n   e  n  2   2e  n  1  K I Te  n  1
T 
(3.20)
36
CHAPTER 4
4 Voltage Mode Control
4.1 Voltage Mode controlled Buck Converter
In the voltage mode control the output voltage of the DC-DC converter is used as feedback
signal. The error input to the PID controller is generated by comparing the output voltage v0 with
the desired output vref . The controller generates the control signal in accordance with the error
signal. The voltage mode controlled Buck converter is shown in Fig. 4.1.
L
N  MOSFET
rL
iL
+
+
C
vc
-
vin
Diode
R
rc
v0
-
v0 (t)
DPWM
d k 
Gain
Digital PID
Controller
ek 
ADC
Error
vref
Fig. 4.1 Voltage mode controlled Buck converter
As shown in the above figure the output voltage is used for feedback signal. The proposed voltage
mode controlled Buck converter is tasted for input voltage vin  6 V , switching frequency
f s  100 k z , inductance L  22.5 mH , ESR of inductor rL  20 m , capacitance C  12.5  F ,
and ESR of capacitor rC  3 m . By using Eq. (2.39) the transfer function of the buck converter is
defined as:
37
Gv0d  s  
vˆ0  s 
4.5 106 s  120

8 2
4
dˆ  s  2.8110 s  2.28 10 s  10
(4.1)
By using Ziegler-Nicholas step response method the following PID controller is obtained:
Gc  s   0.2002 
By using Bilinear Transformation i.e. S 
4004.7
 2.5 104 s
s
(4.2)
2  Z  1
Eq. (4.2) is transformed into discrete form,
Ts  Z  1
which is given below:
Gc (Z) 
50.22Z 2  99.96Z  49.82
Z 2 1
(4.3)
4.1.1 Simulation Result
Step response of the above system is given in Fig. (4.2). The settling time, peak over shoot
and the rise time of the open loop system is greater than the close loop system.
Fig. 4.2 Step response of the open loop and closed loop system
From the step response of the system it is clear that the closed loop system with PID
controller is more stable than the open loop system and the transient response of the closed loop
system is also better than the open loop system. Bode plot of the system is given in Fig. (4.3).
38
Fig. 4.3 Bode plot of the system
From the bode plot in the above figure it can be seen that the phase margin of the system
with PID controller is greater than the system alone. That means the stability of the system is
increased with inclusion of PID controller.
Fig. 4.4 Simulation output voltage of buck converter with constant load
The simulation output of the buck converter is shown in the Fig. (4.4). The system with
feedback delay is lagging behind the system without feedback delay.
39
Fig. 4.5 Simulation output voltage of buck converter with small load variation
Fig. 4.6 Simulation output of buck converter with large load variation
The simulation output of the buck converter is shown in the Fig. (4.5) and (4.6). The peak
overshoot of the system with large load variation is larger than the peak overshoot of the system
having small load variation. The settling time of both of the system is same.
40
4.1.2 Hardware Result
The hardware setup for voltage mode control is given in Fig.4.7. The PWM signal and
corresponding output voltages are given below.
Fig. 4.7 Hardware setup for voltage mode control
Fig. 4.8 Output voltage and PWM signal with 2V reference signal
41
The PWM signal and the output voltage is shown in Fig. 4.8. Channel 1 (CH1) of the CRO
is showing the PWM signal and channel 2 (CH2) is showing the output voltage. The output voltage
is following the reference signal in steady state.
Fig. 4.9 Output voltage and PWM signal with 3V reference signal
The above figure shows the output voltage and the PWM signal with 3V reference signal.
From the above two output is can be observed that the output voltage and PWM duty cycle is
synchronized and in accordance with the reference signal. The AC coupled output voltage is shown
in Fig. 4.10.
42
Fig. 4.10 AC coupled output voltage
4.2 Voltage Mode controlled Boost Converter
In the voltage mode control the output voltage of the DC-DC converter is used as feedback
signal. The error input to the PID controller is generated by comparing the output voltage v0 with
the desired output vref . The controller generates the control signal in accordance with the error
signal. The voltage mode controlled Boot converter is shown in Fig. 4.12.
43
L
iL
Diode
+
+
C
vc
-
N  MOSFET
vin
R
rc
v0
-
v0 (t)
DPWM
Gain
d k 
Digital PID
Controller
ek 
ADC
Error
vref
Fig. 4.12 Voltage mode controlled Boost converter
As shown in the above figure the output voltage is used for feedback signal. The proposed voltage
mode controlled Buck converter is tasted for input voltage vin  5 V , switching frequency
f s  100 k z , inductance L  80  H , capacitance C  1.68  F , and ESR of capacitor rC  5 m .
By using Eq. (2.39) the transfer function of the buck converter is defined as:
Gv0d  s  
vˆ0  s  4.398 1012 s 2  5.225 104 s  120

1.152s 2  11.582s  2.2 103
dˆ  s 
(4.4)
By using Ziegler-Nicholas step response method the following controller is obtained:
Gc  s  
6.2583 103 s 2  0.30339s  1.3605
8.1104 s 2  s
By using Bilinear Transformation i.e. S 
(4.5)
2  Z  1
Eq. (4.5) is transformed into discrete form,
Ts  Z  1
which is given below:
7.681Z 2  15.36Z  7.677
Gc  z  
Z 2  1.988Z  0.9877
44
(4.6)
4.2.1 Simulation Result
The output voltage and the load current of the boost converter is given below. The settling
time of the output voltage is 12m sec . From the results it can be observed that the load current and
output voltage is synchronized.
Fig. 4.11 Output voltage of boost converter
Fig. 4.12 Load current of the boost converter
45
CHAPTER 5
5 Current Mode Control
The current mode control is based on the inductor current. In the current mode control the
transient response of the system is faster because of two control loops. The reference current is
generated by additional loop and is used in the current control loop as the reference signal. The
inductor current is forced to follow the reference current in the current mode control and the
reference current is generated by the outer loop.
5.1 Current Mode Control for Buck Converter without Slope Compensation
In the current mode control without slope compensation the desired inductor current is forced
in the next switching cycle to find the desired output voltage quickly. In this method input voltage
Vin , output voltage V0 and inductor current iL
is used in the control loop. The control signal
generated by the outer loop is used as the reference current and is fed to the inner loop. The control
signal generated by the inner loop contains two parallel terms and one of which vanishes when
present inductor current follows previous reference current i.e. steady state.
Buck Converter
vin (t )
I L (t )
ADC
v0(t)
ADC
DPWM
d ( n)
vin (n)
Current Mode
Controller
v0 (n)
I L ( n)
I ref (n  1)
Compensator
Fig. 5.1 Block diagram of current mode control without slope compensation
46
vref
5.1.1 Principle of Current Control Law
As shown in the Fig. 4.1 the feedback control loop consists of several ADC, a DPWM, a
compensator to control the reference current and a programmable current mode controller. By
using Eq. (2.4) the inductor current of buck converter during ON time is defined as:
dI L  t  1
  vin  t   v0  t  
dt
L
for
t  n   t  t  n   d  n  Ts
(5.1)
t  n   d  n  Ts  t  t  n  1
(5.2)
During OFF time the inductor current is given as:
dI L  t  1
  v0  t  
dt
L
IL
for
IL tn dnTs 
IL
IL tn 
tn
IL tn1 
tn  d  n  Ts
tn 1
t
Fig. 5.2 Steady state inductor current
If the switching frequency of the converter is very high then the change in the inductor current
over a very small time can be considered as:
dI L  t  I L  t  t   I L  t 

dt
t
On substituting the value of Eq. (5.3) in Eq. (5.1) and (5.2):
47
(5.3)
I L  tn  d  n  Ts   I L  tn 
d  n  Ts

1
 vin  tn   v0  t  
L
I L  tn 1   I L  tn  d  n  Ts 
1  d  n   T

s
(5.4)
1
 v0  tn  
L
(5.5)
On simplifying Eq. (5.4):
I L  tn  d  n  Ts   I L  tn  
v t   v t  d  nT
in
n
0
n
s
L
(5.6)
On substituting the value of I L  tn  d  n  Ts  from Eq. (5.6) to Eq. (5.5):
I L  tn1   I L  tn   
v0  tn  Ts vin  tn  d  n  Ts

L
L
(5.7)
On simplifying Eq. (5.7) to find d  n  :
d  tn  
L  I L  tn 1   I L  tn   v0  tn 

Ts
vin  tn 
vin  tn 
(5.8)
To simplifying the Eq. (5.8), the following discrete form is proposed:
d  n 
L  I L  n  1  I L  n   v0  n 

Ts
vin  n 
vin  n 
(5.9)
The following discrete form of the Eq. (5.9) is proposed:
d  n 
L  I L  n  1  I L  n   v0  n 

Ts
vin  n 
vin  n 
(5.10)
In the steady state I L  n  1 should follow reference current I L  n  1 and output voltage v0  n 
should follow reference voltage vref . Hence Eq. (5.10) can be expressed as:
d  n 
L  I ref  n  1  I L  n   vref  n 

Ts
vin  n 
vin  n 
d  n   d1  n   d 2  n 
48
(5.11)
(5.12)
Where,
d1  n  
L  I ref  n  1  I L  n  
Ts
vin  n 
and
d2  n  
vref  n 
vin  n 
(5.13)
Similarly, the current control law for Boost and Buck-Boost converter is derived by changing the
second term d 2  n  by their steady state duty ratio and is given below in Eq. (5.14) and (5.15)
respectively.
L  I ref  n  1  I L  n    vref  n  
 1 

Ts
vin  n 
vin  n  

(5.14)
vref  n 
L  I ref  n  1  I L  n  

Ts vin  n   vref  n 
vin  n   vref  n 
(5.15)
d  n 
d  n 
For designing compensator transfer function output voltage v0 to I ref transfer function is required.
The current loop expression given below is obtained ignoring the feed forward term.
F G S 
v0
 m vd
I ref 1  FmGid  S 
(5.16)
From Eq. (2.39) and (2.42):
Gvd  s  
vˆ0  s 
vin R 1  srcC 
 2
dˆ  s  s  R  rc  LC  s  L  rc RC   R
(5.17)
GId  s  
vin 1  s  R  rc  C 
IˆL  s 
 2
dˆ  s  s  R  rc  LC  s  L  rc RC   R
(5.18)
5.1.2 Result and Discussion
The proposed method is tested on Buck converter having input voltage vin  5V , switching
frequency 400 kHz, inductance L  0.33 H , and capacitance C  220 F . By substituting these
values in Eq. (5.17) and (5.18) the following transfer function obtained:
Gvd 
72.6 10
12
3.125
S  0.33 106 S  0.625
2
49
(5.19)
GId 
72.6 10
12
8.125
S  0.33 106 S  0.625
2
(5.20)
On substituting Eq. (5.19) and (5.20) in (5.16) and assuming Fm  1 the following transfer function
is obtained:
V0
3.125

12 2
I ref 72.6 10 S  0.33 106 S  0.625
(5.21)
Compensator for above transfer function having 60 kHz bandwidth and 58̊ phase margin of the
closed loop system is given below.
8.62 106 S 2  1.53S  6.03 104
Gc  S  
S
By using Bilinear Transformation i.e. S 
(5.22)
2  Z  1
Eq. (5.22) is transformed into discrete form,
Ts  Z  1
which is given below:
GC  Z  
3.615Z 2  2.965Z  0.555
Z 2 1
(5.23)
Fig. 5.3 Step Response of the open loop and closed loop system
The step response of the open loop and closed loop system is shown in the Fig. 5.3. From
the figure it can be seen that the open loop step response is oscillatory while the close loop response
50
is stable with very small maximum overshoot, settling time and rise time as compared to the open
loop system.
The
Fig. 5.4 Bode Plot of the system
The bode plot of the system without controller and with controller is shown in the Fig. 5.4.
The phase margin of the system with controller is 660 while the phase margin of the system
without controller is 1.50 . That means the system with controller is more stable. The output voltage
and the inductor current response of the simulation is shown in Fig. 5.5 and 5.6.
Fig. 5.5 Output Voltage Response of current mode controlled Buck converter
51
Fig. 5.6 Inductor current of current mode controlled Buck converter
5.1.3 Hardware Output
The hardware setup for the current mode control without slope compensation is shown in
Fig. 5.7. The hardware output of the system is shown below.
Fig. 5.7 Hardware setup for current mode control
52
Fig. 5.8 Inductor current and output voltage with 1V reference signal
Fig. 5.9 Inductor current and output voltage with 2V reference signal
53
The inductor current and the output voltage of the current mode controlled buck converter
is shown in Fig. 5.8 and 5.9. From the above two figure it can be observed that the output voltage
is following the reference signal. The output voltage with AC coupling is shown in Fig. 5.10.
Fig. 5.10 Output voltage with AC coupling
5.2 Auto-tuned PID controller for Fast Transient Response of Buck Converter
Auto-Tuned PID controller is used for fast response time. When the load varies very fast
and/or there is a fluctuation in the input voltage then auto-tuned PID controller is required to follow
the desired voltage. The transfer function of PID in S-domain is given as:
1


Y  S    K p S  K I  Kd S 
S


(5.24)
By using the backward difference method i.e. S   z  1 z.Ts the Eq. (4.1) is transformed into
discrete time domain (Z-domain) and is given below:
54


Kd
1
1

y  z    K p  K I Ts

1

z




1  z 1  Ts
(5.25)
In the Eq. (4.2) derivative term is replaced with backward difference function and the integral term
is replaced with a sum using rectangular integration to obtain digital PID control algorithm which
is given in Eq. (4.3).
 n

y  n   e  n  K p  e  n  K d    e  j   K I
 j 1

(5.26)
e  n   e  n   e  n  1 and e  n   vref  v0  n 
(5.27)
Where,
An updating factor 𝛽(𝑛) is proposed and is given as:
  n   eN  n  eN  n 
(5.28)
 e  n 
eN  n    eN  n   eN  n  1  and eN  n   

 emax 
(5.29)
Where,
The gain updating factor 𝛽(𝑘) will update the controller gains K p , K I and K d in each cycle. The
relation between   n  and controller gains K p , K I and K d is given in Eq. (4.7).
K p  n   K p  K1 |   n  | 1
K I  n   K I  K 2   n   1
(5.30)
K d  n   K d  K3 |   n  | 1
Where K1 , K 2 , K3 are three positive constant and K p , K I and K d are controller parameters which
can be obtained by any one of the PID tuning methods. By substituting the value of e  n  from
Eq. (4.4) in (4.3) the digital form of auto-tuned PID controller algorithm is obtained and is given
as:
n
y  n   K p  n  e  n   K I  n   e  j   K d e  n   e  n  1 
j 0
55
(5.31)
Fig. 5.11 Simulation diagram of auto-tuned buck converter
The nominal voltage of 5V changes to 5.5V, 5V, 4.5V and back to 5V at 3 ms, 6ms, 9ms
and 12ms respectively. The converter has load of 1.25 amps and changes to 2.5 amps and back to
1.25 amps in t= 0, 5ms, 10ms respectively corresponding to R=2-1-2 ohms as shown in Fig 5.12.
Fig. 5.12 Variable load and input voltage plot
56
Fig. 5.13 Output voltage of the auto-tuned buck converter
Fig. 5.14 Load current variation of the auto-tuned buck converter
The load current variation and the output voltage of the auto-tuned buck converter is shown
in the above figures. From the Fig. 5.12 and 5.14 it can be observed that the load current is changing
according to the load variation while the output voltage is almost constant in spite of changing the
input voltage and the load.
57
CHAPTER 6
6 Conclusion
Different type of controlling of buck converter is presented in the thesis. First of all the small
signal modeling of Buck converter and Boost converter is presented to find the transfer function
of the converter and a model is proposed for compensator design. In the subsequent chapter digital
feedback control is described in which different type of tuning method of PID controller, DPWM,
ADC and their effects on the system is discussed. In chapter 4 a voltage mode controlled buck
converter is designed. In the voltage mode controlled buck converter the output is stabilizing after
0.8msec of the variation in the load current, if the load current varies faster than the settling time
of the system then output will never stabilize. To overcome this problem an auto-tuned PID
controller is applied in the voltage controlled system which is able to respond the fast transient
response. The output of the system having auto-tuned PID controller is following the fast change
in the load current and input voltage. A current mode controlled buck converter is presented to
improve the transient response of the system. The current mode control is having faster transient
response due to two control loop in the system. The outer loop controls the reference inductor and
the inner loop controls the PWM duty ratio. In the thesis current mode controlled buck converter
without slope compensation is presented. Normally, in the current mode control slope
compensation is required for duty ratio greater than 0.5 but in this system there is no need of slope
compensation. The settling time of the output of the current mode controlled buck converter is
0.5msec and that is of voltage mode control is 0.8msec. That means the transient response of the
system in the current mode control is improved.
58
Future Scope
The proposed current mode controlled system requires two voltage sensor since input
voltage is also required in the current controller design. A current controller can be designed
without using input voltage which will reduce the cost of one voltage sensor.
The proposed controlling approach may be extended to other current control strategies like
current mode control without current sensor, average current mode control without slope
compensation.
The auto-tuning method can be extended to adaptive tuning of the controller and robust
compensator design which is another problem for future work.
59
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61
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