CC1150

CC1150

CC1150

CC1150

Low Power Sub-1 GHz RF Transmitter

Applications

Ultra low power UHF wireless transmitters

Operating in the 315/433/868/915 MHz

ISM/SRD bands

AMR – Automatic Meter Reading

Consumer Electronics

RKE – Remote Keyless Entry

Low power telemetry

Home and building automation

Wireless alarm and security systems

Industrial monitoring and control

Wireless sensor networks

Product Description

The

CC1150

is a low cost true single chip UHF transmitter designed for very low power wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and

Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915

MHz, but can easily be programmed for operation at other frequencies in the 300-348

MHz, 400-464 MHz and 800-928 MHz bands.

The RF transmitter is integrated with a highly configurable baseband modulator. The modulator supports various modulation formats and has a configurable data rate up to

500 kBaud. The

CC1150 provides extensive hardware support for packet handling, data buffering and burst transmissions.

The main operating parameters and the 64byte transmit FIFO of

CC1150 can be controlled via an SPI interface. In a typical system, the

CC1150 will be used together with a microcontroller and a few additional passive components.

CC1150 is part of Chipcon’s SmartRF®04 technology platform based on 0.18 µm CMOS technology.

Key Features

Small size (QLP 4x4 mm package, 16 pins)

True single chip UHF RF transmitter

Frequency bands: 300-348 MHz, 400-464

MHz and 800-928 MHz

Programmable data rate up to 500 kBaud

Low consumption

Programmable output power up to +10

• dBm for all supported frequencies

Programmable modulator

Ideal for multi-channel operation

Very few external components:

Completely on-chip frequency synthesizer, no external filters needed

Configurable packet handling hardware

Suitable for frequency hopping systems due to a fast settling frequency synthesizer

Optional Forward Error Correction with interleaving

64-byte TX data FIFO

SWRS037A Page 1 of 60

Features (continued from front page)

Suited for systems compliant with EN 300

220 and FCC CFR Part 15

Many powerful digital features allow a high-performance RF system to be made using an inexpensive microcontroller

Efficient SPI interface: All registers can be programmed with one “burst” transfer

Integrated analog temperature sensor

Lead-free “green” package

Flexible support for packet oriented systems: On chip support for sync word insertion, flexible packet length and automatic CRC handling

CC1150

OOK and flexible ASK shaping supported

2-FSK, GFSK and MSK supported

Optional automatic whitening of data

Support for asynchronous transparent transmit mode for backwards compatibility with existing radio communication protocols

EIRP

ESR

FCC

FEC

FIFO

FSK

GFSK

ISM

LC

LO

Abbreviations

Abbreviations used in this data sheet are described below.

ADC

AFC

AGC

AMR

ASK

BER

CCA

CFR

CRC

CW

Analog to Digital Converter

Automatic Frequency Compensation

Automatic Gain Control

Automatic Meter Reading

Amplitude Shift Keying

Bit Error Rate

Clear Channel Assessment

Code of Federal Regulations

Cyclic Redundancy Check

Contionus Wave (Unmodulated Carrier)

Equivalent Isotropic Radiated Power

NRZ

OOK

PA

PCB

PD

PER

PLL

POR

Non Return to Zero (Coding)

On-Off-Keying

Power Amplifier

Printed Circuit Board

Power Down

Packet Error Rate

Phase Locked Loop

Power-On Reset

QLP

QPSK

Quad Leadless Package

Quadrature Phase Shift Keying

RC Resistor-Capacitor

RCOSC RC Oscillator

LQI

MCU

MSK

Federal Communications Commission

Forward Error Correction

First-In-First-Out

Frequency Shift Keying

Gaussian shaped Frequency Shift Keying

Industrial, Scientific, Medical

Inductor-Capacitor

Local Oscillator

Link Quality Indicator

Microcontroller Unit

Minimum Shift Keying

RSSI

RX

SAW

SMD

SNR

SPI

SRD

TBD

TX

UHF

VCO

XOSC

Received Signal Strength Indicator

Receive, Receive Mode

Surface Aqustic Wave

Surface Mount Device

Signal to Noise Ratio

Serial Peripheral Interface

Short Range Devices

To Be Defined

Transmit, Transmit Mode

Ultra High frequency

Voltage Controlled Oscillator

Crystal Oscillator

SWRS037A Page 2 of 60

CC1150

Table Of Contents

APPLICATIONS ...........................................................................................................................................1

PRODUCT DESCRIPTION.........................................................................................................................1

KEY FEATURES ..........................................................................................................................................1

FEATURES (CONTINUED FROM FRONT PAGE)................................................................................2

A

BBREVIATIONS

...............................................................................................................................................2

TABLE OF CONTENTS ..............................................................................................................................3

1 A

BSOLUTE

M

AXIMUM

R

ATINGS

...........................................................................................................5

2 O

PERATING

C

ONDITIONS

......................................................................................................................5

3 G

ENERAL

C

HARACTERISTICS

...............................................................................................................5

4 E

LECTRICAL

S

PECIFICATIONS

...............................................................................................................6

4.1

C

URRENT

C

ONSUMPTION

.....................................................................................................................6

4.2

RF T

RANSMIT

S

ECTION

........................................................................................................................7

4.3

C

RYSTAL

O

SCILLATOR

.........................................................................................................................8

4.4

F

REQUENCY

S

YNTHESIZER

C

HARACTERISTICS

.....................................................................................8

4.5

A

NALOG

T

EMPERATURE

S

ENSOR

.........................................................................................................9

4.6

DC C

HARACTERISTICS

.........................................................................................................................9

4.7

P

OWER ON

R

ESET

.................................................................................................................................9

5 P

IN

C

ONFIGURATION

..........................................................................................................................10

6 C

IRCUIT

D

ESCRIPTION

........................................................................................................................11

7 A

PPLICATION

C

IRCUIT

........................................................................................................................11

7.1

B

IAS RESISTOR

...................................................................................................................................11

7.2

B

ALUN AND

RF

MATCHING

................................................................................................................11

7.3

C

RYSTAL

............................................................................................................................................12

7.4

R

EFERENCE SIGNAL

............................................................................................................................12

7.5

A

DDITIONAL FILTERING

......................................................................................................................12

7.6

P

OWER SUPPLY DECOUPLING

..............................................................................................................12

7.7

A

NTENNA

C

ONSIDERATIONS

..............................................................................................................13

7.8

PCB L

AYOUT

R

ECOMMENDATIONS

....................................................................................................15

8 C

ONFIGURATION

O

VERVIEW

..............................................................................................................16

9 C

ONFIGURATION

S

OFTWARE

..............................................................................................................17

10 4-

WIRE

S

ERIAL

C

ONFIGURATION AND

D

ATA

I

NTERFACE

...................................................................18

10.1

C

HIP

S

TATUS

B

YTE

............................................................................................................................19

10.2

R

EGISTER

A

CCESS

..............................................................................................................................20

10.3

SPI R

EAD

...........................................................................................................................................20

10.4

C

OMMAND

S

TROBES

..........................................................................................................................20

10.5

FIFO A

CCESS

.....................................................................................................................................21

10.6

PATABLE A

CCESS

............................................................................................................................22

11 M

ICROCONTROLLER

I

NTERFACE AND

P

IN

C

ONFIGURATION

...............................................................22

11.1

C

ONFIGURATION

I

NTERFACE

..............................................................................................................22

11.2

G

ENERAL

C

ONTROL AND

S

TATUS

P

INS

..............................................................................................22

11.3

O

PTIONAL

R

ADIO

C

ONTROL

F

EATURE

...............................................................................................23

12 D

ATA

R

ATE

P

ROGRAMMING

...............................................................................................................23

13 P

ACKET

H

ANDLING

H

ARDWARE

S

UPPORT

.........................................................................................24

13.1

D

ATA WHITENING

...............................................................................................................................24

13.2

P

ACKET

F

ORMAT

................................................................................................................................25

13.3

P

ACKET

H

ANDLING IN

T

RANSMIT

M

ODE

............................................................................................26

13.4

P

ACKET

H

ANDLING IN

F

IRMWARE

......................................................................................................26

14 M

ODULATION

F

ORMATS

.....................................................................................................................27

14.1

F

REQUENCY

S

HIFT

K

EYING

................................................................................................................27

14.2

M

INIMUM

S

HIFT

K

EYING

....................................................................................................................27

14.3

A

MPLITUDE

M

ODULATION

.................................................................................................................28

15 F

ORWARD

E

RROR

C

ORRECTION WITH

I

NTERLEAVING

........................................................................28

15.1

F

ORWARD

E

RROR

C

ORRECTION

(FEC)...............................................................................................28

15.2

I

NTERLEAVING

...................................................................................................................................28

SWRS037A Page 3 of 60

CC1150

16 R

ADIO

C

ONTROL

................................................................................................................................30

16.1

P

OWER ON

S

TART

-

UP

S

EQUENCE

........................................................................................................31

16.2

C

RYSTAL

C

ONTROL

............................................................................................................................31

16.3

V

OLTAGE

R

EGULATOR

C

ONTROL

.......................................................................................................32

16.4

A

CTIVE

M

ODE

....................................................................................................................................32

16.5

T

IMING

...............................................................................................................................................32

17 D

ATA

FIFO ........................................................................................................................................33

18 F

REQUENCY

P

ROGRAMMING

..............................................................................................................34

19 VCO...................................................................................................................................................34

19.1

VCO

AND

PLL S

ELF

-C

ALIBRATION

...................................................................................................34

20 V

OLTAGE

R

EGULATORS

.....................................................................................................................35

21 O

UTPUT

P

OWER

P

ROGRAMMING

........................................................................................................35

21.1

S

HAPING AND

PA R

AMPING

...............................................................................................................36

22 G

ENERAL

P

URPOSE

/ T

EST

O

UTPUT

C

ONTROL

P

INS

...........................................................................37

23 A

SYNCHRONOUS AND

S

YNCHRONOUS

S

ERIAL

O

PERATION

................................................................39

23.1

A

SYNCHRONOUS

S

ERIAL

O

PERATION

.................................................................................................39

23.2

S

YNCHRONOUS

S

ERIAL

O

PERATION

...................................................................................................39

24 S

YSTEM CONSIDERATIONS AND

G

UIDELINES

......................................................................................39

24.1

SRD R

EGULATIONS

............................................................................................................................39

24.2

F

REQUENCY

H

OPPING AND

M

ULTI

-C

HANNEL

S

YSTEMS

.....................................................................40

24.3

W

IDEBAND

M

ODULATION NOT USING

S

PREAD

S

PECTRUM

.................................................................40

24.4

D

ATA

B

URST

T

RANSMISSIONS

............................................................................................................41

24.5

C

ONTINUOUS

T

RANSMISSIONS

...........................................................................................................41

24.6

L

OW

C

OST

S

YSTEMS

..........................................................................................................................41

24.7

B

ATTERY

O

PERATED

S

YSTEMS

..........................................................................................................41

24.8

I

NCREASING

O

UTPUT

P

OWER

.............................................................................................................41

25 C

ONFIGURATION

R

EGISTERS

..............................................................................................................42

25.1

C

ONFIGURATION

R

EGISTER

D

ETAILS

.................................................................................................45

25.2

S

TATUS REGISTER DETAILS

.................................................................................................................55

26 P

ACKAGE

D

ESCRIPTION

(QLP 16) ......................................................................................................57

26.1

R

ECOMMENDED

PCB

LAYOUT FOR PACKAGE

(QLP 16) .....................................................................57

26.2

S

OLDERING INFORMATION

..................................................................................................................57

27 R

EFERENCES

.......................................................................................................................................58

28 G

ENERAL

I

NFORMATION

....................................................................................................................59

28.1

D

OCUMENT

H

ISTORY

.........................................................................................................................59

SWRS037A Page 4 of 60

CC1150

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress

exceeding one or more of the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device.

Precaution should be used when handling the device in order to prevent permanent damage.

Parameter

Supply voltage

Voltage on any digital pin

Min

–0.3

Max

3.6

Units Condition

V All supply pins must have the same voltage

–0.3 VDD+0.3 max 3.6

V

–0.3 2.0 V Voltage on the pins RF_P, RF_N and DCOUPL

Voltage ramp-up

Input RF level

Storage temperature range

Solder reflow temperature

ESD

–50

120

+10

150

260

<500 kV/ µ s dBm

°

C

°

C

V

According to IPC/JEDEC J-STD-020C

According to JEDEC STD 22, method A114,

Human Body Model

Table 1: Absolute Maximum Ratings

The operating conditions for

CC1150

are listed Table 2 in below.

Parameter

Operating temperature

Operating supply voltage

Min

-40

1.8

Max

85

3.6

Unit Condition

°

C

V All supply pins must have the same voltage

Table 2: Operating Conditions

Parameter

Frequency range

Min Typ Max Unit Condition/Note

Data rate 1.2

1.2

26

250

500 kBaud kBaud

2-FSK

GFSK, OOK and ASK

(Shaped) MSK (also known as differential offset

QPSK)

Optional Manchester encoding (the data rate in kbps will be half the baud rate)

Table 3: General Characteristics

SWRS037A Page 5 of 60

CC1150

Tc = 25

°

C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1150EM reference

design ( [1] and [2]).

Parameter

Current consumption

Current consumption,

315 MHz

Current consumption,

433 MHz

Current consumption,

868 MHz

Current consumption,

915 MHz

Min Typ Max

200

Unit Condition

nA Voltage regulator to digital part off, register values lost (SLEEP state)

222

µ

A Voltage regulator to digital part on, all other modules in power down (XOFF state)

1.1 mA Only voltage regulator to digital part and crystal oscillator running

(IDLE state)

7.7

25.6

14.1

26.1

14.6

29.3

15.5

29.3

15.2 mA Only the frequency synthesizer running (FSTXON state). This current consumptions also representative for the other intermediate states when going from IDLE until reaching TX, and frequency calibration states mA Transmit mode, +10 dBm output power (0xC4)

Transmit mode, 0 dBm output power (0x60)

See more in section 21 and DN012 [3]

mA Transmit mode, +10 dBm output power (0xC2)

Transmit mode, 0 dBm output power (0x60)

See more in section 21 and DN012 [3]

mA Transmit mode, +10 dBm output power (0xC3)

Transmit mode, 0 dBm output power (0x60)

See more in section 21 and DN012 [3]

mA Transmit mode, +10 dBm output power (0xC0)

Transmit mode, 0 dBm output power (0x50)

See more in section 21 and DN012 [3]

Table 4: Electrical Specifications

SWRS037A Page 6 of 60

CC1150

4.2 RF Transmit Section

Tc = 25

°

C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference

design ( [1] and [2]).

Parameter

Differential load impedance

315 MHz

433 MHz

868/915 MHz

Output power, highest setting

Output power, lowest setting

Spurious emissions and harmonics,

433/868 MHz

Spurious emissions,

315/915 MHz

Harmonics 315 MHz

Harmonics 915 MHz

TX latency

Min Typ

122 + j31

116 + j41

86.5 + j43

Max Unit Condition/Note

Differential impedance as seen from the RF-port (RF_P and

RF_N) towards the antenna. Follow the CC1150EM reference

design ( [1] and [2]) available from the TI website.

+10 Output power is programmable, and full range is available across all frequency bands. Output power may be restricted by regulatory limits. See also Application Note

AN039 [4] and Design Note

DN006 [5].

Delivered to a 50

single-ended load via CC1150 EM reference

design ( [1] and [2]) RF matching network. Maximum output power

can be increased 1-2 dB by using wire-wound inductors instead of multilayer inductors in the balun and filter circuit for the 868/915

MHz band, see more in DN017 [6].

–30 Output power is programmable, and full range is available across all frequency bands.

Delivered to a 50

single-ended load via CC1150 EM reference

design ( [1] and [2]) RF matching network

–54

–30 dBm dBm

25 MHz - 1 GHz

47-74, 87.5 - 118, 174 - 230, 470 - 862 MHz

Otherwise above 1 GHz

Note that close-in spurs vary with centre frequency and limits the frequencies and output power level which the CC1150 can operate

at without violating regulatory restrictions, see more in AN039 [4].

See also section 7.5 for information regarding additional filtering.

dBm

EIRP

<200

µ

V/m at 3 m below 960 MHz.

–41.2 dBm

EIRP

<500

µ

V/m at 3 m above 960 MHz

–20

–41.2 dBc dBm

2 nd

, 3 rd

and 4 th

harmonic when the output power is maximum 6 mV/m at 3 m (-19.6 dBm EIRP)

5 th

harmonic

–20

–41.2 dBc dBm

2 nd

harmonic with +10 dBm output power

3 rd

, 4 th

and 5 th

harmonic

8 Bits Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports.

Table 5: RF Transmit Parameters

SWRS037A Page 7 of 60

CC1150

4.3 Crystal Oscillator

Tc = 25

°

C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference

design ( [1] and [2]).

Parameter

Crystal frequency

Tolerance

Min Typ Max Unit Condition/Note

26 26 27 MHz

±40 ppm This is the total tolerance including a) initial tolerance, b) aging and c) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth

10 13 20 pF Simulated over operating conditions Load capacitance

Start-up time 150 µ s

Measured on the CC1150EM reference design ( [1] and [2]). This

parameter is to a large degree crystal dependent.

Table 6: Crystal Oscillator Parameters

4.4 Frequency Synthesizer Characteristics

Tc = 25

°

C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design

( [1] and [2]).

Parameter

Programmed frequency resolution

Synthesizer frequency tolerance

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

PLL turn-on / hop time 85.1

PLL calibration time

Min

397 F

Typ Max

XOSC

2

16

±40

/ 412

694

–82

–86

–90

–98

–106

–113

–119

–127

88.4

18739

721

88.4

721

Unit Condition/Note

Hz ppm

26 MHz-27 MHz crystals. The resolution (in Hz) is equal for all frequency bands.

Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. dBc/Hz @ 50 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 100 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 200 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 500 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 1 MHz offset from carrier, carrier at 868 MHz dBc/Hz @ 2 MHz offset from carrier, carrier at 868 MHz dBc/Hz @ 5 MHz offset from carrier, carrier at 868 MHz dBc/Hz @ 10 MHz offset from carrier, carrier at 868 MHz

µ s

XOSC cycles

µ s

Time from leaving the IDLE state until arriving in the

FSTXON or TX state, when not performing calibration.

Crystal oscillator running.

Calibration can be initiated manually or automatically before entering or after leaving TX.

Min/typ/max time is for 27/26/26 MHz crystal frequency.

Table 7: Frequency Synthesizer Parameters

SWRS037A Page 8 of 60

CC1150

4.5 Analog Temperature Sensor

Tc = 25

°

C, VDD = 3.0 V if nothing else is stated. Note that it is necessary to write 0xBF to the PTEST register to use the

analog temperature sensor in the IDLE state.

Parameter

Output voltage at –40

°

C

Output voltage at 0

°

C

Output voltage at +40

°

C

Output voltage at +80

°

C

Temperature coefficient

Absolute error in calculated temperature

Min Typ Max Unit Condition/Note

0.651 V

0.747 V

0.847 V

0.945 V

–2

*

2.45 mV/

°

C Fitted from –20

°

C to +80

°

C

°

C From

°

C to +80

°

C when using 2.45 mV /

°

C, after 1-point calibration at room temperature

*

Indicated minimum and maximum error with 1point calibration is based on simulated values for typical process parameters

0.3 mA Current consumption increase when enabled

Table 8: Analog Temperature Sensor Parameters

Tc = 25

°

C if nothing else stated.

Digital Inputs/Outputs

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage

Logic "1" output voltage

Logic "0" input current

Logic "1" input current

Min

0

VDD-0.7

0

VDD-0.3

N/A

N/A

Max

0.7

VDD

0.5

VDD

–1

1

Unit

V

V

V

V

µ

A

µ

A

Condition

For up to 4 mA output current

For up to 4 mA output current

Input equals 0 V

Input equals VDD

Table 9: DC Characteristics

4.7 Power on Reset

For proper Power-On-Reset functionality, the power supply must comply with the requirements in

Table 10 below. Otherwise, the chip should be assumed to have unknown state until transmitting

an

SRES

strobe over the SPI interface. See section 16.1 on page 31 for a description of the

recommended start up sequence after turning power on.

Parameter

Power-up ramp-up time

Power off time

Min Typ Max Unit Condition/Note

1

5 ms ms

From 0 V until reaching 1.8 V

Minimum time between power-on and power-off

Table 10: Power-on Reset Requirements

SWRS037A Page 9 of 60

5 Pin Configuration

The

CC1150

pin-out is shown in Figure 1 and Table 11.

CC1150

SCLK 1

SO (GDO1) 2

DVDD 3

DCOUPL 4

16 15 14 13

5 6 7 8

12 AVDD

11 RF_N

10 RF_P

9 CSn

GND

Exposed die attach pad

Pin # Pin name

1

SCLK

2

Pin type

Digital Input

SO (GDO1)

Digital Output

3

4

7

8

5

6

Figure 1: Pinout Top View

Note: The exposed die attach pad

must

be connected to a solid ground plane as this is the main ground connection for the chip.

DVDD

DCOUPL

XOSC_Q1

AVDD

XOSC_Q2

GDO0

(ATEST)

13

14

15

16

9

10

11

12

CSn

RF_P

RF_N

AVDD

AVDD

RBIAS

DGUARD

SI

Power (Digital)

Power (Digital)

Analog I/O

Power (Analog)

Analog I/O

Digital I/O

Digital Input

RF I/O

RF I/O

Power (Analog)

Power (Analog)

Analog I/O

Power (Digital)

Digital Input

Description

Serial configuration interface, clock input.

Serial configuration interface, data output.

Optional general output pin when

CSn

is high.

1.8 V - 3.6 V digital power supply for digital I/O’s and for the digital core voltage regulator.

1.6 V - 2.0 V digital power supply output for decoupling.

NOTE: This pin is intended for use with the to provide supply voltage to other devices.

CC1150

only. It can not be used

Crystal oscillator pin 1, or external clock input.

1.8 V - 3.6 V analog power supply connection.

Crystal oscillator pin 2.

Digital output pin for general use:

Test

FIFO status signals

Clock output, down-divided from XOSC

Serial input TX data

Also used as analog test I/O for prototype/production testing.

Serial configuration interface, chip select.

Positive RF output signal from PA.

Negative RF output signal from PA.

1.8 V - 3.6 V analog power supply connection.

1.8 V - 3.6 V analog power supply connection.

External bias resistor for reference current .

Power supply connection for digital noise isolation.

Serial configuration interface, data input.

Table 11: Pinout Overview

SWRS037A Page 10 of 60

CC1150

RADIO CONTROL

RF_P

RF_N

PA

FREQ

SYNTH

SCLK

SO (GDO1)

SI

CSn

GDO0 (ATEST)

BIAS XOSC

RBIAS XOSC_Q1 XOSC_Q2

Figure 2:

CC1150

Simplified Block Diagram

A simplified block diagram of

CC1150 is shown

in Figure 2.

The

CC1150

transmitter is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC

VCO.

A crystal is to be connected to XOSC_Q1 and

XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the digital part.

A 4-wire SPI serial interface is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling and data buffering.

Only a few external components are required for using the

CC1150

. The recommended

application circuits are shown in Figure 4 and

Figure 5 .

The external components are

described in Table 13, and typical values are

given in Table 14.

The bias resistor R141 is used to set an

7.2 Balun and RF matching

The components between the RF_N/RF_P pins and the point where the two signals are joined together (C111, C101, L101 and L111 for the 315/433 MHz design. L101, L111,

C101, L102, C111, C102 and L112 for the

868/915 MHz reference design) form a balun that converts the differential RF signal on

CC1150

to a single-ended RF signal. C104 is needed for DC blocking. Together with an appropriate LC filter network, the balun components also transform the impedance to match a 50

antenna (or cable). C105 provides DC blocking and is only needed if there is a DC path in the antenna. For the accurate bias current.

868/915 MHz reference design, this component may also be used for additional

filtering, see section 7.5 below.

Suggested values for 315 MHz, 433 MHz and

868/915 MHz are listed in Table 14.

The balun and LC filter component values and their placement are important to achieve optimal performance. It is highly recommended to follow the CC1150EM reference design

( [1] and [2]). Gerber files and

schematics for the reference designs are available for download from the TI website.

SWRS037A Page 11 of 60

C

L

=

1

1

C

51

+

1

C

71

+

C parasitic

The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance.

Total parasitic capacitance is typically 2.5 pF.

The crystal oscillator circuit is shown in Figure

3. Typical component values for different

values of C

L

are given in Table 12.

CC1150

7.3 Crystal

A crystal in the frequency range 26-27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C51 and C71) for the crystal are required. The loading capacitor values depend on the total load capacitance,

C

L

, specified for the crystal. The total load capacitance seen between the crystal terminals should equal C

L

for the crystal to oscillate at the specified frequency.

XOSC_Q1 XOSC_Q2

XTAL

C51 C71

Figure 3: Crystal Oscillator Circuit

The crystal oscillator is amplitude regulated.

This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see section

4.3 on page 8).

The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application.

Component

C51

C71

C

L

= 10 pF

15 pF

15 pF

C

L

=13 pF

22 pF

22 pF

C

L

=16 pF

27 pF

27 pF

Table 12: Crystal Oscillator Component Values

The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This input clock can either be a fullswing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak-peak amplitude.

The reference signal must be connected to the

XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. The XOSC_Q2 line must be left unconnected. C51 and C71 can be omitted when using a reference signal.

In the 868/915 MHz reference design, C106 and L105 together with C105 build an optional filter to reduce emission at 699 MHz. This filter may be necessary for applications seeking compliance with ETSI EN 300-220, for more

information, see DN017 [6]. If this filtering is

not necessary, C105 will work as a DC block

(only necessary if there is a DC path in the antenna). C106 and L105 should in that case be left unmounted.

Additional external components (e.g. an RF

SAW filter) may be used in order to improve the performance in specific applications. The use of wire-wound inductors in the application circuit will also improve the RF performance and give higher output power. For more

information, see DN017 [6].

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The

CC1150EM reference design should be

followed closely ( [1] and [2]).

SWRS037A Page 12 of 60

CC1150

The reference designs ( [1] and [2]) contains a

SMA connector and is match for a 50

load.

The SMA connector makes it easy to connect evaluation modules and prototypes to different test equipment for example a spectrum analyzer. The SMA connector can also be replaced by an antenna suitable for the desired application. Please refer to the

antenna selection guide AN058 [7] for further

details regarding antenna solutions provided by TI.

Component Description

C41 Decoupling capacitor for on-chip voltage regulator to digital part

C51/C71

C101/C111

C102

Crystal loading capacitors

RF balun/matching capacitors

C103

C104

RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz).

RF LC filter/matching capacitors

RF balun DC blocking capacitor

C105

C106

L101/L111

L102

RF LC filter DC blocking capacitor and part of optional RF LC filter (868/915 MHz)

Part of optional RF LC filter and DC Block (868/915 MHz)

RF balun/matching inductors (inexpensive multi-layer type)

RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor

(868/915 MHz) (inexpensive multi-layer type)

L103

L104

L105

R141

XTAL

RF LC filter/matching inductor (inexpensive multi-layer type)

RF LC filter/matching inductor (inexpensive multi-layer type)

Part of optional RF LC filter (868/915 MHz)(inexpensive multi-layer type)

Resistor for internal bias current reference

26-27 MHz crystal

Table 13: Overview of External Components (excluding supply decoupling capacitors)

SWRS037A Page 13 of 60

CC1150

1.8V-3.6V power supply

SI

R141

SCLK

SO

(GDO1)

1 SCLK

2 SO

(GDO1)

CC1150

DIE ATTACH PAD:

3 DVDD

AVDD 12

RF_N 11

RF_P 10

4 DCOUPL CSn 9

C41

GDO0

(optional)

CSn

C111

L111

L101

C104

C101

L102

C105

L103

C102 C103

Antenna

(50 Ohm)

XTAL

C51 C71

Figure 4: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply decoupling capacitors)

1.8V-3.6V power supply

R141

SI

SCLK

SO

(GDO1)

C41

GDO0

(optional)

CSn

1 SCLK

2 SO

(GDO1)

3 DVDD

4 DCOUPL

CC1150

DIE ATTACH PAD:

AVDD 12

RF_N 11

RF_P 10

CSn 9

C111

L111 L112

C101

L103

C103

L101

L102

C102

L104

C104

Antenna

(50 Ohm)

C105

C106

L105

C106 and L105 may be added to build an optional filter to reduce emission at 699 MHz

XTAL

C51 C71

Figure 5: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply decoupling capacitors)

SWRS037A Page 14 of 60

CC1150

Component

C41

C51

C71

C101

C102

C103

C104

C105

C106

C111

L101

L102

L103

L104

L105

L111

L112

Value at 31 5MHz

6.8 pF ± 0.5 pF, 0402 NP0

12 pF ± 5%, 0402 NP0

6.8 pF ± 0.5 pF, 0402 NP0

220 pF ± 5%, 0402 NP0

220 pF ± 5%, 0402 NP0

Value at 433 MHz

100 nF ± 10%, 0402 X5R

27 pF ± 5%, 0402 NP0

27 pF ± 5%, 0402 NP0

3.9 pF ± 0.25 pF, 0402 NP0

8.2 pF ± 0.5 pF, 0402 NP0

5.6pF±0.5pF, 0402 NP0

220 pF ± 5%, 0402 NP0

220 pF ± 5%, 0402 NP0

Value at 868/915 MHz

1.0 pF ± 0.25 pF, 0402 NP0

1.5 pF ± 0.25 pF, 0402 NP0

3.3 pF ± 0.25 pF, 0402 NP0

100 pF ± 5%, 0402 NP0

100 pF ± 5%, 0402 NP0

(12 pF ± 5%, 0402 NP0 if optionally

699 MHz filter is desired)

(47 pF ± 5%, 0402 NP0 if optionally

699 MHz filter is desired)

1.5 pF ± 0.25pF, 0402 NP0 6.8 pF ± 0.5 pF, 0402 NP0

33nH±5%, 0402 monolithic

3.9 pF ± 0.25 pF, 0402 NP0

27 nH ± 5%, 0402 monolithic

18nH±5%, 0402 monolithic 22 nH ± 5%, 0402 monolithic

33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic

12 nH ± 5%, 0402 monolithic

18 nH ± 5%, 0402 monolithic

12 nH ± 5%, 0402 monolithic

(12 nH ± 5%, 0402 monolithic if optionally 699 MHz filter is desired)

33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic

3.3 nH ± 5%, 0402 monolithic

12 nH ± 5%, 0402 monolithic

18 nH ± 5%, 0402 monolithic

XTAL 26.0 MHz surface mount crystal

Table 14: Bill of Materials for the Application Circuit (Murata LQG15HS and GRM1555C series inductors and capacitors, resistor from the Koa RK73 series, and AT-41CD2 crystal from NDK)

The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias.

The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias for good thermal performance and sufficiently low inductance to ground.

In the CC1150EM reference designs ( [1] and

[2]), 5 vias are placed inside the exposed die

attached pad. These vias should be “tented”

(covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process.

The solder paste coverage should not be

100%. If it is, out gassing may occur during the reflow process, which may cause defects

(splattering, solder balling). Using “tented” vias reduces the solder paste coverage below

100%. See Figure 6 for top solder resist and

top paste masks.

All the decoupling capacitors should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the

CC1150 supply pin. Supply power filtering is very important.

Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. Routing in the ground plane underneath and between the chip, the balun/RF matching circuit and the decoupling capacitor’s ground vias should also be

SWRS037A Page 15 of 60

CC1150 avoided. This improves the grounding and ensures the shortest possible return path for stray currents.

The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Please note that components smaller than those specified may have differing characteristics.

Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry.

It is strongly advised that the CC1150EM

reference design ( [1] and [2]) layout is followed

very closely in order to get the best performance. Gerber files and schematics for the reference designs are available for download from the TI website.

Figure 6: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias

CC1150

can be configured to achieve optimum performance for many different applications.

Configuration is done using the SPI interface.

The following key parameters can be programmed:

Power-down / power-up mode

Crystal oscillator power-up / power – down

Transmit mode

RF channel selection

Data

Modulation

RF output power

Data buffering with 64-byte transmit FIFO

Packet radio hardware support

Forward Error Correction with interleaving

Whitening

Details of each configuration register can be

found in section 25, starting on page 42.

Figure 7 shows a simplified state diagram that

explains the main

CC1150

states, together with typical usage and current consumption. For detailed information on controlling the

CC1150 state machine, and a complete state diagram,

see section 16, starting on page 30.

SWRS037A Page 16 of 60

CC1150

SIDLE

SPWD

Sleep

Lowest power mode.

Register values are lost.

Current consumption typ

200nA.

Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.1 mA.

Used for calibrating frequency synthesizer upfront (entering transmit mode can then be done quicker). Transitional state. Typ. current consumption: 7.7 mA.

Manual freq. synth. calibration

SCAL

CSn=0

IDLE

SRX or STX or SFSTXON

SXOFF

CSn=0

Crystal oscillator off

All register values are retained. Typ. current consumption; 0.22 mA.

Frequency synthesizer startup, optional calibration, settling

Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency.

Transitional state. Typ. current consumption: 7.7 mA.

Frequency synthesizer is on, ready to start transmitting.

Transmission starts very quickly after receiving the STX command strobe.Typ. current consumption: 7.7 mA.

SFSTXON

Frequency synthesizer on

STX

STX

TXOFF_MODE=01

Typ. current consumption 868 MHz:

14 mA at -10 dBm output,

15 mA at 0 dBm output,

24 mA at +7 dBm output,

29 mA at +10 dBm output.

Transmit mode

TXOFF_MODE=00

In FIFO-based modes, transmission is turned off and this state entered if the TX

FIFO becomes empty in the middle of a packet. Typ. current consumption: 1.1 mA.

TX FIFO underflow

Optional transitional state. Typ. current consumption: 7.7 mA.

Optional freq. synth. calibration

SFTX

IDLE

Figure 7: Simplified State Diagram with Typical Usage and Current Consumption

CC1150

can be configured using the SmartRF

®

Studio [11] software, available for download

from www.ti.com/smartrfstudio. The SmartRF

Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF Studio user interface for

CC1150

is shown in Figure 8.

After chip reset, all the registers have default

values as shown in the tables in section 25.

The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface.

SWRS037A Page 17 of 60

CC1150

Figure 8: SmartRF Studio User Interface

10 4-wire Serial Configuration and Data Interface

CC1150 is configured via a simple 4-wire SPIcompatible interface (

SI

,

SO

,

SCLK

and

CSn

) where

CC1150

is the slave. This interface is also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first.

All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address. and data transfer on the SPI interface is shown

in Figure 9 with reference to Table 15.

When

CSn

is pulled low, the MCU must wait until the

CC1150

SO

pin goes low before starting to transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip is in the

SLEEP or XOFF states, the

SO

pin will always go low immediately after taking

CSn

low.

During address and data transfer, the

CSn

pin

(Chip Select, active low) must be kept low. If

CSn

goes high during the access, the transfer will be cancelled. The timing for the address

SWRS037A Page 18 of 60

t sp t ch t cl t sd t hd t ns

CC1150

SCLK:

CSn:

Write to register:

SI

SO

X

Hi-Z

SI

X

SO

Hi-Z

0

S7

Read from register:

1

A6 A5 A4 A3 A2

S7

A6

S

S

6

6

A5

S

S

5

5

A4

S4

S4

A3

S

S

3

3

A2

S

S

2

2

A1

S

A1

S

1

1

A0

S0

A0

S0

X D

W

7 D

W

6

S7

D

R

7

S6

D

R

6

D

W

5

S5

D

R

5

D

W

4 D

W

3

S4

D

R

4

S3

X

D

R

3

D

W

2

S2

D

R

2

D

W

1

S1

D

R

1

D

W

0

S0

D

R

0

S7

X

Hi-Z

Hi-Z

Figure 9: Configuration Registers Write and Read Operations

Min

t ch t cl t rise t fall t sd

Parameter Description

f

SCLK

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).

t sp,pd

SCLK

frequency, single access

No delay between address and data byte

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

CSn

low to positive edge on

SCLK

, in power-down mode t sp

CSn

low to positive edge on

SCLK

, in active mode t hd

Clock rise time

Clock fall time

Setup data (negative

SCLK edge) to positive edge on

SCLK

(t sd

applies between address and data bytes, and between data bytes)

Hold data after positive edge on

SCLK

Single access

Burst access t ns

Negative edge on

SCLK

to

CSn

high

Max Units

9

6.5

150 - µ s

20 - ns

-

-

55

76

-

-

5

5 ns ns ns ns

20 - ns

20 - ns

Table 15: SPI Interface Timing Requirements

Note that the minimum t sp,pd

figure in Table 15 can be used in cases where the user does not read the

CHIP_RDYn

signal. CSn low to positive edge on SCLK when the chip is woken from power-down

depends on the start-up time of the crystal being used. The 150 µs in Table 15 is the crystal oscillator

start-up time measured using crystal AT-41CD2 from NDK.

When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is sent by the

CC1150

on the

SO

pin.

The status byte contains key status signals, useful for the MCU. The first bit, s7, is the

CHIP_RDYn

signal; this signal must go low

before the first positive edge of

SCLK

. The

CHIP_RDYn

signal indicates that the crystal is

running and the regulated digital supply voltage is stable.

Bit 6, 5 and 4 comprises the

STATE

value. This

value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down.

The frequency and channel configuration should only be updated when the chip is in this state. The TX state will be active when the chip is transmitting.

The last four bits (3:0) in the status byte contains

FIFO_BYTES_AVAILABLE.

This field

SWRS037A Page 19 of 60

CC1150 contains the number of bytes free for writing into the TX FIFO. When

FIFO_BYTES_AVAILABLE=15

, 15 or more

bytes are free. Table 16 gives a status byte

summary.

Bits Name

7 CHIP_RDYn

6:4 STATE[2:0]

Description

Stays high until power and crystal have stabilized. Should always be low when using the SPI interface.

Indicates the current main state machine mode

Value State Description

000 Idle

001 Not used state

(Also reported for some transitional states instead of SETTLING or CALIBRATE, due to a small error)

Not used

010 TX

011 FSTXON

100 CALIBRATE

101 SETTLING

110 Not used

Fast TX ready

Frequency synthesizer calibration is running

PLL is settling

Not used

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

SFTX

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO.

The configuration registers on the

CC1150

are located on SPI addresses from 0x00 to 0x2E.

Table 26 on page 43 lists all configuration

registers. The detailed description of each

register is found in Section 25.1, starting on page 45.

Table 16: Status Byte Summary

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting

CSn

high.

All configuration registers can be both written and read. The read/write bit controls if the register should be written or read. When writing to registers, the status byte is sent on the

SO

pin each time a header byte or data byte is transmitted on the

SI

pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

For register addresses in the range 0x30-

0x3D, the burst bit is used to select between status registers (burst bit is 1) and command strobes (burst bit is 0). See more in section

10.3 below. Because of this, burst access is

not available for status registers, so they must be read one at a time. The status registers can only be read.

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or

TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the

CC1150

Errata Notes [8] for more details.

Command Strobes may be viewed as single byte instructions to

CC1150

. By addressing a

Command Strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable transmit mode, flush the TX FIFO etc. The nine

SWRS037A Page 20 of 60

command strobes are listed in Table 25 on page 42.

CC1150

Note that an SIDLE strobe will clear all pending command strobes until IDLE state is reached. This means that if for example an

SIDLE strobe is issued while the radio is in TX state, any other command strobes issued before the radio reaches IDLE state will be ignored.

The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30 through 0x3D) are written.

When writing command strobes, the status byte is sent on the

SO

pin.

However, if an

SRES

command strobe is being issued, on will have to wait for the

SO

pin to go low before the next command strobe can be

issued as shown in Figure 10.The command

strobes are executed immediately, with the exception of the

SPWD

and the

SXOFF

strobes that are executed when

CSn

goes high.

Figure 10: SRES Command Strobe

A command strobe may be followed by any other SPI access without pulling

CSn

high.

The 64-byte TX FIFO is accessed through the

0x3F addresses. When the read/write bit is zero, the TX FIFO is accessed. The TX FIFO is write-only.

The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte.

After the data byte a new address is expected; hence,

CSn

can remain low. The burst access method expects one address byte and then consecutive data bytes until terminating the access by setting

CSn

high.

The following header bytes access the FIFO:

0x3F: Single byte access to TX FIFO

0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte

(see Section 10.1) is output for each new data

byte on

SO

, as shown in Figure 10. This status

byte can be used to detect TX FIFO underflow

CSn:

Command strobe(s):

Read or write register(s):

Read or write consecutive registers (burst):

Read or write n+1 bytes from/to RF FIFO:

Combinations:

ADDR strobe

ADDR reg

ADDR reg

DATA

ADDR reg n

DATA

ADDR

FIFO n

DATA while writing data to the TX FIFO. Note that the status byte contains the number of bytes free

before

writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX

FIFO is transmitted to the SI pin, the status byte received concurrently on the SO pin will indicate that one byte is free in the TX FIFO.

The TX FIFO may be flushed by issuing a

SFTX

command strobe. The

SFTX

command

strobe can only be issues in the IDLE or

TX_UNDERFLOW states. The FIFO is cleared when going to the SLEEP state.

Figure 11 gives a brief overview of different

register access types possible.

...

DATA

...

...

DATA

Figure 11: Register Access Types

DATA

...

DATA byte n

ADDR

FIFO

DATA byte 0

DATA

...

SWRS037A Page 21 of 60

CC1150

The 0x3E address is used to access the

PATABLE

, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address.

By programming the

PATABLE

, controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for reduced bandwidth. Note that the ASK modulation shaping is limited to output powers below -1 dBm. See SmartRF Studio

[11] for

recommended shaping sequence. See also

section 21 on page 35 for details on output

power programming.

The

PATABLE

is an 8-byte table that defines the PA control settings to use for each of the eight PA power values (selected by the 3-bit value

FREND0.PA_POWER

). The table is

written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when

CSn

is high. When the highest value is reached the counter restarts at zero.

The access to the

PATABLE

is either single byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).

If one byte is written to the

PATABLE

and this value is to be read out then

CSn

must be set high before the read access in order to set the index counter back to zero.

Note that the content of the

PATABLE

is lost when entering the SLEEP state. For more

information, see DN501 [8].

11 Microcontroller Interface and Pin Configuration

In a typical system,

CC1150

will interface to a microcontroller. This microcontroller must be able to:

Program into different modes,

Write buffered data

Read back status information via the 4-wire

SPI-bus configuration interface (

SI

,

SO

,

SCLK

and

CSn

).

The microcontroller uses four I/O pins for the

SPI configuration interface (

SI

,

SO

,

SCLK

and

11.2 General Control and Status Pins

The

CC1150

has one dedicated configurable pin

(

GDO0

) and one shared pin (

GDO1/SO

) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See section

22 page 37 for more details of the signals that

can be programmed. The shared pin is the

SO pin in the SPI interface. The default setting for

GDO1/SO

is 3-state output. By selecting any other of the programming options the

GDO1/SO

pin will become a generic pin. When

CSn

is low, the pin will always function as a normal

SO

pin.

In the synchronous and asynchronous serial modes, the

GDO0

pin is used as a serial TX data input pin while in transmit mode.

CSn

). The SPI is described in Section

10 on page 18.

The

GDO0

pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the

GDO0

pin with an external ADC, the temperature can be calculated.

Specifications for the temperature sensor are

found in section 4.5 on page 9. With default

PTEST

register setting (0x7F)

, the temperature sensor output is only available when the frequency synthesizer is enabled (e.g. the

MANCAL, FSTXON and TX states). It is

necessary to write 0xBF to the

PTEST

register

to use the analog temperature sensor in the

IDLE state. Before leaving the IDLE state, the

PTEST

register should be restored to its

default value (0x7F).

SWRS037A Page 22 of 60

11.3 Optional Radio Control Feature

The

CC1150

has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE, and TX.

This optional functionality is enabled with the

MCSM0.PIN_CTRL_EN

configuration bit.

State changes are commanded as follows:

If CSn is high, the SI and SCLK are set to

the desired state according to Table 17.

If CSn goes low, the state of SI and SCLK is latched and a command strobe is generated internally according to the pin configuration.

It is only possible to change state with the latter functionality. That means that for instance TX will not be restarted if SI and

CC1150

SCLK are set to TX and CSn toggles. When

CSn is low the SI and SCLK has normal SPI functionality.

All pin control command strobes are executed

immediately except the

SPWD

strobe. The

SPWD

strobe is delayed until CSn goes high.

CSn SCLK SI Function

1 X X Chip unaffected by SCLK/

SI

0

1 0 Generates strobe

1 1

Defined on the transceiver version (

CC1101

)

SPI mode

SPI mode

SPI mode (wakes up into

IDLE if in SLEEP/XOFF)

Table 17: Optional Pin Control Coding

12 Data Rate Programming

The data rate used when transmitting is

programmed by the

MDMCFG3.DRATE_M

and

the

MDMCFG4.DRATE_E

configuration

registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.

R

DATA

=

(

256

+

DRATE

2

28

_

M

)

2

DRATE

_

E

f

XOSC

The following approach can be used to find suitable values for a given data rate:

DRATE

_

E

DRATE

_

M

=

=

⎢ log

2

⎜⎜

R

DATA f

XOSC

2

20

f

R

DATA

XOSC

2

2

28

DRATE

_

E

⎟⎟

256

If

DRATE_M

is rounded to the nearest integer

and becomes 256, increment

DRATE_E

and

use

DRATE_M

=0.

The data rate can be set from 0.8 kBaud to

500 kBaud with the minimum data rate step

size changes according to Table 18 below.

Min Data rate

[kBaud]

0.8

Typical data rate

[kBaud]

1.2 / 2.4

Max Data rate

[kBaud]

3.17

Data rate step size

[kBaud]

0.0062

Table 18: Data Rate Step Size

SWRS037A Page 23 of 60

CC1150

13 Packet Handling Hardware Support

The

CC1150 has built-in hardware support for packet oriented radio protocols.

In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO:

A programmable number of preamble bytes.

A two byte Synchronization Word. Can be duplicated to give a 4-byte sync word

(recommended). It is not possible to only insert preamble or only insert a sync word.

Optionally whitening the data with a PN9 sequence.

Optionally Interleave and Forward Error

Code the data.

Optionally compute and add a 2 byte CRC checksum over the data field.

In a system where

CC1150 is used as the transmitter and

CC1101 as the receiver the recommended setting is 4-byte preamble and

4-byte sync word except for 500 kBaud data rate where the recommended preamble length is 8 bytes.

Note that register fields that control the packet handling features should only be altered when

CC1150

is in the IDLE state.

From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies).

Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening in the receiver.

With

CC1150

, in combination with a

CC1101

at the receiver end, this can be done

automatically by setting

PKTCTRL0

.

WHITE_DATA=1

. All data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9) sequence

before being transmitted as shown in Figure

12. The PN9 sequence is initialized to all 1’s.

At the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening is reversed, and the original data appear in the receiver.

Setting

PKTCTRL0

.

WHITE_DATA=1

is recommended for all uses, except when overthe-air compatibility with other systems is needed.

Figure 12: Data Whitening in TX Mode

SWRS037A Page 24 of 60

CC1150

The format of the data packet can be configured and consists of the following items:

Preamble

• word

Optional length byte

Optional Address byte

Payload

Optional 2 byte CRC

Optional data whitening

Optionally FEC encoded/decoded

Optional CRC-16 calculation

Legend:

Inserted automatically in TX, processed and removed in RX.

Preamble bits

(1010...1010)

Data field

Optional user-provided fields processed in TX, processed but not removed in RX.

Unprocessed user data (apart from FEC and/or whitening)

8 x

n

bits 16/32 bits

8 bits

8 bits

8 x n bits 16 bits

Figure 13: Packet Format

The preamble pattern is an alternating sequence of ones and zeros (01010101…).

The number of preamble bytes is programmed

with the

MDMCFG1.NUM_PREAMBLE

value.

When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is written to the TX

FIFO. The modulator will then send the sync word and then the data bytes. payload data, excluding the length byte and the optional automatic CRC.

With

PKTCTRL0.LENGTH_CONFIG=2

, the packet length is set to infinite and transmission will continue until turned off manually. The infinite mode can be turned off while a packet is being transmitted. As described in the next section, this can be used to support packet formats with different length configuration than natively supported by

CC1150

. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the

CC1150

Errata Notes [8] for

more details.

Note that the minimum packet length supported (excluding the optional length byte and CRC) is one byte of payload data.

The synchronization word is a two-byte value

set in the

SYNC1

and

SYNC0

registers. The

sync word provides byte synchronization of the incoming packet. A one-byte synch word can

be emulated by setting the

SYNC1

value to the

preamble pattern. It is also possible to emulate a 32 bit sync word by using

MDMCFG2.SYNC_MODE

set to 3 or 7. The sync

word will then be repeated twice.

CC1150 supports both fixed packet length protocols and variable packet length protocols.

Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.

Fixed packet length mode is selected by setting

PKTCTRL0.LENGTH_CONFIG=0

. The

desired packet length is set by the

PKTLEN

register. In variable packet length mode

PKTCTRL0.LENGTH_CONFIG=1,

the packet length is configured by the first byte after the sync word. The packet length is defined as the

(

13.2.1 Arbitrary Length Field Configuration

The packet automation control register,

PKTCTRL0,

can be reprogrammed during TX.

This opens the possibility to transmit packets that are longer than 256 bytes and still be able to use the packet handling hardware support.

At the start of the packet, the infinite mode

PKTCTRL0.LENGTH_CONFIG=2

) must be

active. The

PKTLEN

register is set to mod(length, 256).

When less than 256 bytes remains of the packet, the MCU disables infinite packet length and activates fixed length packets. When the internal byte counter

reaches the

PKTLEN

value, the transmission ends (the radio enters the state determined by

TXOFF_MODE)

. Automatic CRC appending can be used (by setting

PKTCTRL0.CRC_EN=1

).

SWRS037A Page 25 of 60

When for example a 600-byte packet is to be transmitted, the MCU should do the following

(see also Figure 14):

Set

.

CC1150

Transmit at least 345 bytes, for example by filling the 64-byte TX FIFO six times

(384 bytes transmitted).

Set

Pre-program the

PKTLEN

register to

mod(600,256)=88

.

The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted.

Figure 14: Arbitrary Length Field Configuration

13.3 Packet Handling in Transmit Mode

The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written to the TX FIFO is interpreted as the destination address, if this feature is enabled in the device that receives the packet.

The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO and the result is sent as two extra bytes at the end of the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter

TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe.

Writing to the TX FIFO after it has underflowed will not restart TX mode.

If whitening is enabled, the length byte, payload data and the two CRC bytes will be whitened. This is done before the optional

FEC/Interleaver stage. Whitening is enabled by setting

PKTCTRL0.WHITE_DATA=1

.

If FEC/Interleaving is enabled, the length byte, payload data and the two CRC bytes will be scrambled by the interleaver, and FEC encoded before being modulated. FEC is enabled by setting

MDMCFG1.FEC_EN=1.

13.4 Packet Handling in Firmware

When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been transmitted.

Additionally, for packets longer than 64 bytes, the TX FIFO needs to be refilled while in TX.

This means that the MCU needs to know the number of bytes that can be written to the TX

FIFO. There are two possible solutions to get the necessary status information: a) Interrupt Driven Solution

The GDO pins can be used in TX to give an interrupt when a sync word has been transmitted or when a complete packet has been transmitted by setting

IOCFGx.GDOx_CFG=0x06

. In addition, there

are two configurations for the

IOCFGx.GDOx_CFG

register that can be used

as an interrupt source to provide information on how many bytes that is in the TX FIFO. The

IOCFGx.GDOx_CFG=0x02

and the

SWRS037A Page 26 of 60

IOCFGx.GDOx_CFG=0x03

configurations are

associated with the TX FIFO. See Table 24 for

more information. b) SPI Polling

The

PKTSTATUS

register can be polled at a

given rate to get information about the current

GDO2 and GDO0 values respectively. The

TXBYTES

register can be polled at a given rate

to get information about the number of bytes in the TX FIFO. Alternatively, the number of bytes in the TX FIFO can be read from the chip status byte returned on the MISO line

CC1150 each time a header byte, data byte, or command strobe is sent on the SPI bus.

It is recommended to employ an interrupt driven solution due to that when using SPI polling, there is a small, but finite, probability that a single read from registers

PKTSTATUS and

TXBYTES

is being corrupt. The same is

the case when reading the chip status byte.

This is explained in the

CC1150

Errata Notes [8]

Refer to the TI website for SW examples [12]

14 Modulation Formats

CC1150

supports amplitude, frequency and phase shift modulation formats. The desired modulation format is set in the

MDMCFG2.MOD_FORMAT

register.

Optionally, the data stream can be Manchester coded by the modulator. This option is enabled by setting

MDMCFG2.MANCHESTER_EN=1.

Manchester encoding cuts the effective data rate in half, and thus Manchester is not supported for 500 kBaud. Further note that

Manchester encoding is not supported at the same time as using the FEC/Interleaver option or when using MSK modulation.

14.1 Frequency Shift Keying

CC1150

has the possibility to use Gaussian shaped 2_FSK (GFSK). The 2-FSK signal is then shaped by a Gaussian filter with BT=1, producing a GFSK modulated signal. This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth.

In “true” 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift “softer”, the spectrum can be made significantly narrower.

Thus, higher data rates can be transmitted in the same bandwidth using GFSK.

The frequency deviation is programmed with the

DEVIATION_M

and

DEVIATION_E

values

in the

DEVIATN

register. The value has an

14.2 Minimum Shift Keying

When using MSK

MSK modulated.

1

, the complete transmission

(preamble, sync word and payload) will be

Phase shifts are performed with a constant transition time. The fraction of a symbol period

1

Identical to offset QPSK with half-sine shaping (data coding may differ) exponent/mantissa form, and the resultant deviation is given by:

f dev

=

f xosc

2

17

( 8

+

DEVIATION

_

M

)

2

DEVIATION

_

E

The symbol encoding is shown in Table 19.

Format Symbol

2-FSK/GFSK ‘0’

Coding

Table 19: Symbol Encoding for 2-FSK/GFSK

Modulation

used to change the phase can be modified

with the

DEVIATN.DEVIATION_M

setting.

This is equivalent to changing the shaping of the symbol.

Note that when using MSK, Manchester encoding must be disabled by setting

MDMCFG2.MANCHESTER_EN=0

. Further note that the MSK modulation format implemented in

CC1150

inverts the data compared to e.g. signal generators.

SWRS037A Page 27 of 60

CC1150

CC1150

supports two different forms of amplitude modulation: On-Off Keying (OOK) and Amplitude Shift Keying (ASK).

OOK modulation simply turns on or off the PA to modulate 1 and 0 respectively.

The ASK variant supported by the

CC1150 allows programming of the modulation depth

(the difference between 1 and 0), and shaping

15 Forward Error Correction with Interleaving

of the pulse amplitude. Pulse shaping will produce a more bandwidth constrained output spectrum.

Note that the OOK/ASK pulse shaping feature on the

CC1150

does only support output power up to about -1 dBm.

The

DEVIATN

register has no effect when using ASK/OOK.

15.1 Forward Error Correction (FEC)

CC1150

has built in support for Forward Error

Correction (FEC) that can be used with

CC1101 at the receiver end. To enable this option, set

MDMCFG1.FEC_EN

to 1. FEC is only supported

in fixed packet length mode, i.e. when

PKTCTRL0.LENGTH_CONFIG=0.

FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit.

Redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors.

The use of FEC allows correct reception at a lower Signal-to-Noise RATIO (SNR), thus extending communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate

(PER) is related to BER by

PER

=

1

( 1

BER

)

packet

_

length

A lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully.

15.2 Interleaving

Data received through real radio channels will often experience burst errors due to interference and time-varying signal strengths.

In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart.

CC1150

employs matrix interleaving, which is

illustrated in Figure 15. The on-chip

interleaving buffer is a 4 x 4 matrix. In the transmitter, the data bits are written into the

Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors).

The FEC scheme adopted for

CC1150

is convolutional coding, in which

n

bits are generated based on

k

input bits and the

m

most recent input bits, forming a code stream able to withstand a certain number of bit errors between each coding state (the

m

-bit window).

The convolutional coder is a rate 1/2 code with a constraint length of m=4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. This means that in order to transmit at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate. rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix and fed to the rate ½ convolutional coder. Conversely, in a

CC1101 receiver, the received symbols are written into the rows of the matrix, whereas the data passed onto the convolutional decoder is read from the columns of the matrix.

When FEC and interleaving is used, at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of

SWRS037A Page 28 of 60

CC1150 the size of the interleaver buffer (two bytes).

The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO in a

CC1101

.

When FEC and interleaving is used, the minimum data payload is 2 bytes in fixed and variable packet length mode.

Interleaver

Write buffer

Interleaver

Read buffer

Packet

Engine

FEC

Encoder

Modulator

Interleaver

Write buffer

Interleaver

Read buffer

Demodulator

FEC

Decoder

Figure 15: General Principle of Matrix Interleaving

Packet

Engine

SWRS037A Page 29 of 60

16 Radio Control

MANCAL

3,4,5

SIDLE

CAL_COMPLETE

SCAL

IDLE

1

SPWD

CSn = 0

SXOFF

CSn = 0

SLEEP

0

STX | SFSTXON

FS_WAKEUP

6,7

FS_AUTOCAL = 00 | 10 | 11

&

STX | SFSTXON

FS_AUTOCAL = 01

&

STX | SFSTXON

CALIBRATE

8

XOFF

2

CAL_COMPLETE

FSTXON

18

SFSTXON

SETTLING

9,10

STX

TXOFF_MODE = 01

STX

CC1150

TX

19,20 TXOFF_MODE = 10

TXFIFO_UNDERFLOW

TX_UNDERFLOW

22

TXOFF_MODE = 00

&

FS_AUTOCAL = 00 | 01

TXOFF_MODE = 00

&

FS_AUTOCAL = 10 | 11

CALIBRATE

12

SFTX

IDLE

1

Figure 16: Radio Control State Diagram

CC1150

has a built-in state machine that is used to switch between different operations states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow.

SWRS037A Page 30 of 60

A simplified state diagram, together with typical usage and current consumption, is

shown in Figure 7 on page 17. The complete

radio control state diagram is shown in Figure

CC1150

16. The numbers refer to the state number

readable in the

MARCSTATE

status register.

This functionality is primarily for test purposes.

16.1 Power on Start-up Sequence

When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described below, i.e.

Automatic power-on reset or manual reset.

After the automatic power-on reset or manual reset it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192, but to optimize performance in TX, an alternative GDO setting should be selected from the settings found in

Table 24 on page 38.

The other global reset possibility on

CC1150

is the

SRES

command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The power-up

sequence is as follows (see Figure 18):

Set = 1 and

SI

= 0.

Strobe low / high. Make sure to hold

CSn

high for at least 40 µ s relative to pulling

CSn

low.

Pull low and wait for

SO

to go low

(

CHIP_RDYn

).

Issue

SRES

strobe on the

SI l ine.

When

SO

goes low again, reset is complete and the chip is in the IDLE state.

A power-on reset circuit is included in the

CC1150

. The minimum requirements stated in

Section

4.7 must be followed for the power-on

reset to function properly. The internal power-

up sequence is completed when

CHIP_RDYn goes low.

CHIP_RDYn

is observed on the

SO pin after

CSn

is pulled low. See Section 10.1

for more details on

CHIP_RDYn

.

When the

CC1150

reset is completed the chip will be in the IDLE state and the crystal oscillator running. If the chip has had sufficient time for the crystal oscillator and voltage regulator to stabilize after the power-on-reset, the

SO

pin will go low immediately after taking

CSn

low. If

CSn

is taken low before reset is completed the

SO

pin will first go high, indicating that the crystal oscillator and voltage regulator is not stabilized, before going low as

shown in Figure 17.

Figure 18: Power-up with

SRES

Note that the above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the

CC1150 after this, it is only necessary to issue an

SRES command strobe.

It is recommended to always send a

SRES command strobe on the SPI interface after power-on even though power-on reset is used.

Figure 17: Power-on Reset

16.2 Crystal Control

The crystal oscillator is automatically turned on when

CSn

goes low. It will be turned off if the

SXOFF

or

SPWD

command strobes are issued; the state machine then goes to XOFF or

SLEEP respectively. This can only be done from IDLE state. The XOSC will be turned off when

CSn

is released (goes high). The XOSC will be automatically turned on again when

SWRS037A Page 31 of 60

CSn

goes low. The state machine will then go to the IDLE state. The

SO

pin on the SPI interface must be pulled low before the SPI interface is ready to be used; as described in

Section 10.1 on page 19.

CC1150

Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in section

4.3 on page 8.

16.3 Voltage Regulator Control

The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state, which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after

CSn

is released when a

SPWD

command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting

CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.

On the

CC1150

, all register values (with the

exception of the

MCSM0.PO_TIMEOUT

field)

are lost in the SLEEP state. After the chip gets back to the IDLE state, the registers will have default (reset) contents and must be reprogrammed over the SPI interface.

The active transmit mode is activated by the

MCU by using the

STX

command strobe.

The frequency synthesizer must be calibrated regularly.

CC1150

has one manual calibration option (using the

SCAL

strobe), and three automatic calibration options, controlled by the

MCSM0.FS_AUTOCAL

setting:

Calibrate when going from IDLE to TX

(or FSTXON)

Calibrate when going from TX to IDLE

Calibrate every fourth time when going from TX to IDLE

The calibration takes a constant number of

XOSC cycles; see Table 20 for timing details.

When TX is active, the chip will remain in the

16.5 Timing

The radio controller controls most timing in

CC1150

, such as synthesizer calibration and

PLL lock. Table 20 shows timing in crystal

clock cycles for key state transitions. Timing from IDLE to TX is constant, dependent on the auto calibration setting. The calibration time is constant 18739 clock periods. Power on time

TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the

MCSM1.TXOFF_MODE

setting. The possible

destinations are:

IDLE

FSTXON: Frequency synthesizer on and ready at the TX frequency.

Activate TX with

STX

.

TX: Start sending preambles

The

SIDLE

command strobe can always be used to force the radio controller to go to the

IDLE state. Note that if the radio goes from TX to IDLE by issuing an

SIDLE

strobe, the automatic calibration-when-going-from-TX-to-

IDLE will not be performed. and XOSC start-up times are variable, but

within the limits stated in Table 6. Note that in

a frequency hopping spread spectrum or a multi-channel protocol the calibration time can be reduced from 721 µ s to approximately 150

µ

s. This is explained in section 24.2.

SWRS037A Page 32 of 60

CC1150

Description XOSC periods

26 MHz crystal

Idle to TX/FSTXON, no calibration 2298 88.4 µs

Idle to TX/FSTXON, with calibration ~21037 809 µs

TX to IDLE, no calibration

TX to IDLE, including calibration

Manual calibration

2

~18739

~18739

0.1 µs

721 µs

721 µs

Table 20: State Transition Timing

17 Data FIFO

The

CC1150

contains a 64 byte FIFO for data to be transmitted. The SPI interface is used for writing to the TX FIFO. Section

10.5 contains

details on the SPI FIFO access. The FIFO controller will detect underflow in the TX FIFO.

When writing to the TX FIFO, it is the responsibility of the MCU to avoid TX FIFO overflow. This will not be detected by the

CC1150

. A TX FIFO overflow will result in an error in the TX FIFO content.

FIFO_THR

Bytes in TX FIFO

0 (0000) 61

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

57

53

49

45

41

37

33

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

29

25

21

17

13

9

5

1

Table 21:

FIFO_THR

Settings and the corresponding FIFO Thresholds

The chip status byte that is available on the

SO pin while transferring the SPI address contains

the fill grade of the TX FIFO. Section 10.1 on page 19 contains more details on this.

The number of bytes in the TX FIFO can also be read from the

TXBYTES.NUM_TXBYTES

status register.

The 4-bit

FIFOTHR.FIFO_THR

setting is used

to program the FIFO threshold point. Table 21

lists the 16

FIFO_THR

settings and the

corresponding thresholds for the TX FIFO.

FIFO_THR=13

Underflow margin

8 bytes

TXFIFO

Figure 19: Example of FIFO at Threshold

A flag will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. The flag is used to generate the FIFO status signals that can be

viewed on the GDO pins (see section 22 on page 37).

Figure 19 shows the number of bytes in the TX

FIFO when the threshold flag toggles, in the

case of

FIFO_THR

=13. Figure 20 shows the

flag as the FIFO is filled above the threshold, and then drained below.

NUM_TXBYTES

6 7 8 9 10 9 8

GDO

7 6

Figure 20:

FIFO_THR

=13 vs. Number of

Bytes in FIFO

SWRS037A Page 33 of 60

CC1150

18 Frequency Programming

The frequency programming in

CC1150 is designed to minimize the programming needed in a channel-oriented system.

The base or start frequency is set by the 24 bit

frequency word located in the

FREQ2

,

FREQ1

To set up a system with channel numbers, the desired channel spacing is programmed with and

FREQ0

registers. This word will typically

be set to the centre of the lowest channel frequency that is to be used. the

MDMCFG0.CHANSPC_M

and

The desired channel number is programmed

MDMCFG1.CHANSPC_E

registers. The channel

with the 8-bit channel number register, spacing registers are mantissa and exponent respectively.

CHANNR.CHAN

, which is multiplied by the

channel offset. The resultant carrier frequency is given by:

f carrier

=

f

XOSC

2

16

(

FREQ

+

CHAN

(

(

256

+

CHANSPC

_

M

)

2

CHANSPC

_

E

2

) )

With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get e.g. 1 MHz channel spacing on solution is to use 333 kHz channel spacing and select each third channel in

CHANNR.CHAN

.

If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state.

19 VCO

The VCO is completely integrated on-chip.

19.1 VCO and PLL Self-Calibration

The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation,

CC1150 includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency

(or channel). The number of XOSC cycles for completing the PLL calibration is given in

Table 20 on page 33.

The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off. This is configured with the

MCSM0.FS_AUTOCAL

register setting.

In manual mode, the calibration is initiated when the

SCAL

command strobe is activated in the IDLE mode.

The calibration values are not maintained in sleep mode. Therefore, the

CC1150

must be recalibrated after reprogramming the configuration registers when the chip has been in the SLEEP state.

To check that the PLL is in lock the user can program register

IOCFGx.GDOx_CFG

to 0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x =

0,1 or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register

FSCAL1

.

The PLL is in lock if the register content is different from 0x3F. See more information in the

CC1150

Errata Notes [8].

For more robust operation the source code could include a check so that the PLL is recalibrated until PLL lock is achieved if the PLL does not lock the first time.

SWRS037A Page 34 of 60

CC1150

20 Voltage Regulators

CC1150

contains several on-chip linear voltage regulators, which generate the supply voltage needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and

required pin voltages in Table 1 and Table 11

are not exceeded.

Setting the

CSn

pin low turns on the voltage regulator to the digital core and start the crystal oscillator. The

SO

pin on the SPI interface must go low before the first positive edge on the

SCLK

(setup time is s given in

Table 15).

If the chip is programmed to enter power-down mode (

SPWD

strobe issued), the power will be turned off after

CSn

goes high. The power and crystal oscillator will be turned on again when

CSn

goes low.

The voltage regulator for the digital core requires one external decoupling capacitor.

The voltage regulator output should only be used for driving the

CC1150

.

21 Output Power Programming

The RF output power level from the device has two levels of programmability, as illustrated in

Figure 21. Firstly, the special

PATABLE register can hold up to eight user selected output power settings. Secondly, the 3-bit

FREND0.PA_POWER

value selects the

PATABLE

entry to use. This two-level functionality provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK modulation shaping. In each case, all the PA power settings in the

PATABLE

from index 0 up to the

FREND0.PA_POWER

value are used.

The power ramping at the start and at the end of a packet can be turned off by setting

FREND0.PA_POWER

to zero and then programming the desired output power to index 0 in the

PATABLE

.

PATABLE(7)[7:0]

PATABLE(6)[7:0]

PATABLE(5)[7:0]

PATABLE(4)[7:0]

PATABLE(3)[7:0]

PATABLE(2)[7:0]

PATABLE(1)[7:0]

PATABLE(0)[7:0]

If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively.

Table 22 contains recommended

PATABLE settings for various output levels and frequency bands. DN012

[3] gives complete

tables for the different frequency bands. Using

PA settings from 0x61 to 0x6F is not

recommended. Table 23 contains output

power and current consumption for default

PATABLE setting (0xC6).

PATABLE must be programmed in burst mode if you want to write to other entries than

PATABLE[0].

See section

10.6 on page 22

for

PATABLE

programming details.

The PA uses this setting.

Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for

ASK/OOK modulation.

Index into PATABLE(7:0) e.g 6

PA_POWER[2:0] in FREND0 register

The SmartRF® Studio software should be used to obtain optimum

PATABLE settings for various output powers.

Figure 21: PA_POWER and PATABLE

SWRS037A Page 35 of 60

CC1150

Output power

[dBm]

Setting

315 MHz

Current consumption, typ. [mA]

Setting

433 MHz

Current consumption, typ. [mA]

Setting

868 MHz

Current consumption, typ. [mA]

Setting

915 MHz

Current consumption, typ. [mA]

Table 22: Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands

Default power setting

Output power

[dBm]

315 MHz

Current consumption, typ. [mA]

Output power

[dBm]

433 MHz

Current consumption, typ. [mA]

Output power

[dBm]

868 MHz

Current consumption, typ. [mA]

Output power

[dBm]

915 MHz

Current consumption, typ. [mA]

Table 23: Output Power and Current Consumption for Default PATABLE Setting

21.1 Shaping and PA Ramping

With ASK modulation, up to eight power settings are used for shaping. The modulator contains a counter that counts up when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate. The counter saturates at

FREND0.PA_POWER

and 0 respectively.

This counter value is used as an index for a lookup in the power table. Thus, in order to

Output Power

PATABLE[7]

PATABLE[6]

PATABLE[5]

PATABLE[4]

PATABLE[3]

PATABLE[2]

PATABLE[1]

PATABLE[0]

1 0 0 1 0

utilize the whole table,

FREND0.PA_POWER

should be 7 when ASK is active. The shaping of the ASK signal is dependent on the configuration of the

PATABLE

.

Figure 22

shows some examples of ASK shaping. Note that the OOK/ASK pulse shaping feature on the

CC1150

is only supported for output power levels below -1 dBm.

1 1 0

Time

Bit Sequence

FREND0.PA_POWER = 3

FREND0.PA_POWER = 7

Figure 22: Shaping of ASK Signal

SWRS037A Page 36 of 60

CC1150

22 General Purpose / Test Output Control Pins

The two digital output pins

GDO0

and

GDO1

are general control pins. Their functions are programmed by

IOCFG0.GDO0_CFG

and

IOCFG1.GDO1_CFG

respectively. Table 24

shows the different signals that can be monitored on the GDO pins. These signals can be used as an interrupt to the MCU.

The default value for

GDO0

is a 125 - 146 kHz clock output (XOSC frequency divided by

192). Since the XOSC is turned on at poweron-reset, this can be used to clock the MCU in systems with only one crystal. When the MCU is up and running it can change the clock frequency by writing to

IOCFG0.GDO0_CFG.

GDO1

is the same pin as the

SO

pin on the SPI interface, thus the output programmed on this pin will only be valid when

CSn

is high. The default value for

GDO1

is 3-stated, which is useful when the SPI interface is shared with other devices.

An on-chip analog temperature sensor is enabled by writing the value 128 (0x80h) to the

IOCFG0.GDO0_CFG

register. The voltage

on the

GDO0

pin is then proportional to

temperature. See section 4.5 on page 9 for

temperature sensor specifications.

SWRS037A Page 37 of 60

CC1150

GDOx

_CFG[5:0] Description

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

Reserved – defined on the transceiver version (

Reserved – defined on the transceiver version (

Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU.

Serial Clock. Synchronous to the data in synchronous serial mode.

In TX mode, data is sampled by

CC1150

CC1101

).

CC1101

Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX

FIFO is below the same threshold.

Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below the TX FIFO threshold.

Reserved – defined on the transceiver version ( ).

Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.

Asserts when sync word has been sent, and de-asserts at the end of the packet. In TX the pin will also de-assert if the TX

FIFO underflows.

Reserved – defined on the transceiver version (

Reserved – defined on the transceiver version (

Reserved – defined on the transceiver version ( on the rising edge of the serial clock when

12 (0x0C) Reserved – defined on the transceiver version (

13 (0x0D) Reserved – defined on the transceiver version (

14 (0x0E) Reserved – defined on the transceiver version (

CC1101

CC1101

CC1101

CC1101

).

).

).

).

CC1101

).

CC1101

).

CC1101

).

15 (0x0F) Reserved – defined on the transceiver version (

16 (0x10) Reserved – used for test.

17 (0x11) Reserved – used for test.

18 (0x12) Reserved – used for test.

19 (0x13) Reserved – used for test.

20 (0x14) Reserved – used for test.

21 (0x15) Reserved – used for test.

22 (0x16) Reserved – defined on the transceiver version (

23 (0x17) Reserved – defined on the transceiver version (

24 (0x18) Reserved – used for test.

25 (0x19) Reserved – used for test.

26 (0x1A) Reserved – used for test.

27 (0x1B)

PA_PD. PA is enabled when 1, in power-down when 0.

28 (0x1C) Reserved – defined on the transceiver version (

29 (0x1D) Reserved – defined on the transceiver version (

30 (0x1E) Reserved – used for test.

31 (0x1F) Reserved – used for test.

32 (0x20) Reserved – used for test.

33 (0x21) Reserved – used for test.

34 (0x22) Reserved – used for test.

CC1101

CC1101

CC1101

CC1101

CC1101

).

).

).

).

).

GDOx_INV=0

.

35 (0x23) Reserved – used for test.

36 (0x24) Reserved – defined on the transceiver version (

37 (0x25) Reserved – defined on the transceiver version (

38 (0x26) Reserved – used for test.

39 (0x27) Reserved – defined on the transceiver version (

40 (0x28) Reserved – used for test.

41 (0x29) CHIP_RDYn.

42 (0x2A) Reserved – used for test.

43 (0x2B) XOSC_STABLE.

44 (0x2C) Reserved – used for test.

45 (0x2D)

GDO0

CC1101

CC1101

CC1101

).

).

).

_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).

46 (0x2E) High impedance (3-state).

47 (0x2F) HW to 0 (HW1 achieved by setting

48 (0x30) CLK_XOSC/1

49 (0x31) CLK_XOSC/1.5

50 (0x32) CLK_XOSC/2

51 (0x33) CLK_XOSC/3

52 (0x34) CLK_XOSC/4

53 (0x35) CLK_XOSC/6

54 (0x36) CLK_XOSC/8

55 (0x37) CLK_XOSC/12

56 (0x38) CLK_XOSC/16

57 (0x39) CLK_XOSC/24

58 (0x3A) CLK_XOSC/32

59 (0x3B) CLK_XOSC/48

60 (0x3C) CLK_XOSC/64

61 (0x3D) CLK_XOSC/96

62 (0x3E) CLK_XOSC/128

63 (0x3F) CLK_XOSC/192

GDOx_INV=1

).

Note: There are 2 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other GDO pin must be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.

To optimize RF performance, these signals should not be used while the radio is in TX mode.

Table 24: GDO signal selection(x = 0 or 1)

SWRS037A Page 38 of 60

CC1150

23 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have been included in the

CC1150

to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, significantly offload the microcontroller and simplify software development.

23.1 Asynchronous Serial Operation

For backward compatibility with systems already using the asynchronous data transfer from other Chipcon products, asynchronous transfer is also included in

CC1150

.

When asynchronous transfer is enabled, several of the support mechanisms for the

MCU that are included in

CC1150

will be disabled, such as packet handling hardware, buffering in the FIFO and so on. The asynchronous transfer mode does not allow the use of the data whitener, interleaver and

FEC, and it is not possible to use Manchester encoding. MSK is not supported for asynchronous transfer.

Setting

PKTCTRL0.PKT_FORMAT

to 3 enables asynchronous transparent (serial) mode. In TX, the

GDO0

pin is used for data input (TX data).

The MCU must control start and stop of transmit with the

STX

and

SIDLE

strobes.

The

CC1150

modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate.

23.2 Synchronous Serial Operation

Setting

PKTCTRL0.PKT_FORMAT

to 1 enables synchronous serial operation mode. In this operational mode the data must be NRZ encoded (

MDMCFG2.MANCHESTER_EN=0

). In synchronous serial operation mode, data is transferred on a two wire serial interface. The

CC1150

provides a clock that is used to set up new data on the data input line. Data input (TX data) is the

GDO0

pin. This pin will automatically be configured as an input when

TX is active. The TX latency is 8 bits.

Preamble and sync word insertion may or may not be active, dependent on the sync mode set

by the

MDMCFG3.SYNC_MODE

.

If preamble and sync word is disabled, all other packet handler features and FEC should also be disabled. The MCU must then handle preamble and sync word insertion in software.

If preamble and sync word insertion is left on, all packet handling features and FEC can be used. When using the packet handling features synchronous serial mode, the

CC1150 will insert the preamble and sync word and the

MCU will only provide the data payload. This is equivalent to the recommended FIFO operation mode.

24 System considerations and Guidelines

International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz or 915 MHz frequency bands. The

CC1150

is specifically designed for such use with its 300-

348 MHz, 400-464 MHz and 800-928 MHz operating ranges. The most important regulations when using the

CC1150

in the 315

MHz, 433 MHz, 868 MHz or 915 MHz frequency bands are EN 300 220 (Europe) and FCC CFR47 part 15 (USA). A summary of the most important aspects of these

regulations can be found in AN001 [10].

Please note that compliance with regulations is dependent on complete system performance.

It is the end product manufactor’s

SWRS037A Page 39 of 60

CC1150 responsibility to ensure that the system

24.2 Frequency Hopping and Multi-Channel Systems

The 315 MHz, 433 MHz, 868 MHz or 915 MHz bands are shared by many systems both in industrial, office and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multichannel protocol because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading.

CC1150

is highly suited for FHSS or multichannel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller.

can then be replaced by writing the

FSCAL3

,

FSCAL2

and

FSCAL1

register values that

corresponds to the next RF frequency. The

PLL turn on time is approximately 90 µ s. The blanking interval between each frequency hop is then approximately 90 µ s.

3) Run calibration on a single frequency at

startup. Next write 0 to

FSCAL3[5:4]

to

disable the charge pump calibration. After

writing to

FSCAL3[5:4]

, strobe

STX

with

MCSM0.FS_AUTOCAL=1

for each new frequency hop. That is, VCO current and VCO capacitance calibration is done, but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from approximately 720 µ s to approximately 150 µ s. The blanking interval between each frequency hop is then approximately 240 µ s.

Charge pump current, VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for

CC1150

. There are 3 ways of obtaining the calibration data from the chip:

1) Frequency hopping with calibration for each hop. The PLL calibration time is approximately

720 µ s. The blanking interval between each frequency hop is then approximately 810 µ s.

2) Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting

FSCAL3

,

FSCAL2 in MCU memory. The VCO capacitance calibration

and

FSCAL1

FSCAL1

register values register value must be found for each RF frequency to be used. The

VCO current calibration value and the charge pump current calibration value available in

FSCAL2

and

FSCAL3

respectively are not

dependent on the RF frequency, so the same value can therefore be used for all RF frequencies for these two registers. Between each frequency hop, the calibration process

There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. This solution also requires that the supply voltage and temperature do not vary much in order to have a robust solution.

Solution 3) gives approximately 570 µ s smaller blanking interval than solution 1).

The recommended settings for

TEST0.VCO_SEL_CAL_EN

change with frequency. This means that one should always use SmartRF

[11] to get the correct

settings for a specific frequency before doing a calibration, regardless of which calibration method is being used. It must be noted that the content of the

CC1150

is not retained in

SLEEP state, and thus it is necessary to write

to the

TEST0

register, along with other

registers, when returning from the SLEEP state and initiating calibrations.

24.3 Wideband Modulation not using Spread Spectrum

Digital modulation systems under FFC part

15.247 include FSK and GFSK modulation. A maximum peak output power of 1W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band.

Operating at high data rates and frequency deviation the

CC1150 is suited for systems targeting compliance with digital modulation system as defined by FFC part 15.247. An external power amplifier is needed to increase the output above +10 dBm. Please refer to

[5] for further details concerning

wideband modulation and

CC1150

.

SWRS037A Page 40 of 60

24.4 Data Burst Transmissions

The high maximum data rate of

CC1150

opens up for burst transmissions. A low average data rate link (e.g. 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kBaud) will reduce the time in

CC1150 active mode, and hence also reduce the average current consumption significantly.

Reducing the time in active mode will reduce the likelihood of collisions with other systems in the same frequency range.

In data streaming applications the

CC1150 opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate).

As the

CC1150 provides 500 kBaud multichannel performance without any external filters, a very low cost system can be made. A

HC-49 type SMD crystal is used in the

CC1150EM reference design (

24.7 Battery Operated Systems

In low power applications, the SLEEP state

24.8 Increasing Output Power

In some applications it may be necessary to extend the link range. Adding an external power amplifier is the most effective way of doing this.

Note that the crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used. should be used when the

CC1150

is not active.

The power amplifier should be inserted between the antenna and the balun as shown

in Figure 23.

Figure 23 Block Diagram of

CC1150

Usage with External Power Amplifier

SWRS037A Page 41 of 60

25 Configuration Registers

The configuration of

CC1150

is done by programming 8-bit registers. The configuration data based on selected system parameters are most easily found by using the SmartRF

Studio

[11] software. Complete descriptions of

the registers are given in the following tables.

After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset, all registers that shall be different from the default value therefore needs to be programmed through the SPI interface.

There are 9 Command Strobe Registers, listed

in Table 25 Accessing these registers will

initiate the change of an internal state or mode. There are 29 normal 8-bit Configuration

Registers, listed in Table 26. Many of these

registers are for test purposes only, and need not be written for normal operation of

CC1150

.

There are also 6 Status registers, which are

listed in Table 27. These registers, which are

read-only, contain information about the status of

CC1150

.

Address Strobe Name Description

CC1150

The TX FIFO is accessed through one 8-bit register. Only write operations are allowed to the TX FIFO.

During the address transfer and while writing to a register or the TX FIFO, a status byte is

returned. This status byte is described in Table

16 on page.20.

Table 28 summarizes the SPI address space.

Registers that are only defined on the

CC1101 transceiver are also listed.

CC1101 and

CC1150 are register compatible, but registers and fields only implemented in the transceiver always contain 0 in

CC1150

.

The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F.

0x32

0x33

0x36

0x3B

0x3D

SXOFF

SCAL

SIDLE

SFTX

SNOP

MCSM0.FS_AUTOCAL

=1).

Turn off crystal oscillator.

Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed in

IDLE state without setting manual calibration mode (

MCSM0.FS_AUTOCAL

=0)

MCSM0.FS_AUTOCAL

=1.

Exit TX and turn off frequency synthesizer.

CSn

goes high.

Flush the TX FIFO buffer.

No operation. May be used to pad strobe commands to two bytes for simpler software.

Table 25: Command Strobes

SWRS037A Page 42 of 60

Address

CC1150

0x04

0x05

0x08

0x0D

0x0E

0x0F

0x15

0x17

0x18

0x22

0x23

0x24

0x25

0x26

0x29

0x2C

0x2D

0x2E

Register

SYNC1

SYNC0

PKTCTRL0

FREQ2

FREQ1

FREQ0

DEVIATN

MCSM1

MCSM0

FREND0

FSCAL3

FSCAL2

FSCAL1

FSCAL0

FSTEST

TEST2

TEST1

TEST0

Description

GDO1

output pin configuration

GDO0

output pin configuration

Sync word, high byte

Sync word, low byte

Packet automation control

Frequency control word, high byte

Frequency control word, middle byte

Frequency control word, low byte

Modulator deviation setting

Main Radio Control State Machine configuration

Main Radio Control State Machine configuration

Front end TX configuration

Frequency synthesizer calibration

Frequency synthesizer calibration

Frequency synthesizer calibration

Frequency synthesizer calibration

Frequency synthesizer calibration control

Various test settings

Various test settings

Various test settings

Table 26: Configuration Registers Overview

Details on page number

45

45

53

53

54

52

52

53

53

54

54

54

54

47

47

47

48

49

50

50

51

51

45

46

46

46

46

47

47

47

Address

0x30 (0xF0)

0x31 (0xF1)

0x35 (0xF5)

0x38 (0xF8)

0x39 (0xF9)

0x3A (0xFA)

Register

PARTNUM

VERSION

MARCSTATE

PKTSTATUS

Description

Part number for

CC1150

Current version number

Control state machine state

Current GDOx status and packet status

VCO_VC_DAC

Current setting from PLL calibration module

TXBYTES

Underflow and number of bytes in the TX FIFO

Details on page number

55

55

55

56

56

56

Table 27: Status Registers Overview

SWRS037A Page 43 of 60

CC1150

Write Read

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

IOCFG2

IOCFG1

IOCFG0

FIFOTHR

SYNC1

SYNC0

PKTLEN

PKTCTRL1

PKTCTRL0

ADDR

CHANNR

FSCTRL1

FSCTRL0

FREQ2

FREQ1

FREQ0

MDMCFG4

MDMCFG3

MDMCFG2

MDMCFG1

MDMCFG0

DEVIATN

MCSM2

MCSM1

MCSM0

FOCCFG

BSCFG

AGCCTRL2

AGCCTRL1

AGCCTRL0

WOREVT1

WOREVT0

WORCTRL

FREND1

FREND0

FSCAL3

FSCAL2

FSCAL1

FSCAL0

RCCTRL1

RCCTRL0

FSTEST

PTEST

AGCTEST

TEST2

TEST1

TEST0

SRES SRES

SFSTXON SFSTXON

SXOFF SXOFF

SCAL SCAL

SRX SRX

STX STX

SIDLE SIDLE

SAFC SAFC

SWOR SWOR

SPWD SPWD

PARTNUM

VERSION

FREQEST

LQI

RSSI

MARCSTATE

WORTIME1

WORTIME0

PKTSTATUS

VCO_VC_DAC

SFRX SFRX

SFTX SFTX

TXBYTES

RXBYTES

SWORRST SWORRST

SNOP SNOP

PATABLE

TX FIFO

PATABLE

TX FIFO

PATABLE

RX FIFO

PATABLE

RX FIFO

Table 28: SPI Address Space (greyed text: not implemented on

CC1150

thus only valid for the transceiver version (

CC1101

))

SWRS037A Page 44 of 60

25.1 Configuration Register Details

Bit Field Name

7 GDO_DS

6

5:0

GDO1

_INV

GDO1

_CFG[5:0]

CC1150

0x01: IOCFG1 –

GDO1

output pin configuration

Reset R/W Description

0

0

R/W Set high (1) or low (0) output drive strength on the

GDO pins.

R/W Invert output, i.e. select active low (1) / high (0).

46 (0x2E)

R/W Default is tri-state (See Table 24 on page 38).

6

5:0

GDO0

_INV

GDO0

_CFG[5:0]

0x02: IOCFG0 –

GDO0

output pin configuration

Bit Field Name

7 TEMP_SENSOR_ENABLE

Reset R/W Description

0 R/W Enable analog temperature sensor. Write 0 in all other register bits when using temperature sensor.

R/W Invert output, i.e. select active low (1) / high (0). 0

63 (0x3F) R/W

Default is CLK_XOSC/192 (See Table 24 on page 38).

It is recommended to disable the clock output during initialization in order to optimize RF performance.

Bit Field Name

7:4 Reserved

3:0 FIFO_THR[3:0]

0x03: FIFOTHR – FIFO threshold

Reset

0

7 (0x07)

R/W Description

R/W Write 0 for compatibility with possible future extensions.

R/W Set the threshold for the TX FIFO. The threshold is exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value.

Setting Bytes in TX FIFO

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

45

41

37

33

29

61

57

53

49

13

9

5

1

25

21

17

SWRS037A Page 45 of 60

CC1150

Bit Field Name

7:0 SYNC[15:8]

0x04: SYNC1 – Sync word, high byte

Reset

211 (0xD3)

R/W Description

R/W 8 MSB of 16-bit sync word.

Bit Field Name

7:0 SYNC[7:0]

0x05: SYNC0 – Sync word, low byte

Reset

145 (0x91)

R/W Description

R/W 8 LSB of 16-bit sync word.

Bit Field Name

7:0 PACKET_LENGTH

0x06: PKTLEN – Packet length

Reset

255 (0xFF)

R/W Description

R/W Indicates the packet length when fixed length packets are enabled. If variable packet length mode is used, this value indicates the maximum packet length allowed.

Bit Field Name

7

6 WHITE_DATA

5:4 PKT_FORMAT[1:0]

0x08: PKTCTRL0 – Packet automation control

R/W Description Reset

1

0

R/W Turn data whitening on / off

0: Whitening off

1: Whitening on

R/W Format of TX data

3

2 CRC_EN

1:0 LENGTH_

CONFIG[1:0]

1

1

0 (00) Normal mode, use TX FIFO

1 (01) Serial Synchronous mode, data in on

GDO0

2 (10)

Random TX mode; sends random data using PN9 generator. Used for test/debug.

3 (11) Asynchronous transparent mode. Data in on

GDO0

R/W 1: CRC calculation enabled

0: CRC disabled

R/W Configure the packet length

Setting Packet length configuration

0 (00) Fixed length packets, length configured in

PKTLEN register

1 (01) Variable length packets, packet length configured by the first byte after sync word

2 (10) Infinite packet length packets

3 (11) Reserved

SWRS037A Page 46 of 60

CC1150

Bit Field Name Reset

7:0 DEVICE_ADDRESS

[7:0]

0

0x09: ADDR – Device address

R/W Description

R/W Address used for packet filtration. Optional broadcast addresses are

0 (0x00) and 255 (0xFF).

Bit Field Name

7:0 CHAN[7:0]

Reset

0

0x0A: CHANNR – Channel number

R/W Description

R/W The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency.

Bit Field Name

7:6 FREQ[23:22]

5:0 FREQ[21:16]

0x0D: FREQ2 – Frequency control word, high byte

Reset R/W Description

0 R FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26

MHz or higher crystal frequency).

30 (0x1E) R/W FREQ[23:0] is the base frequency for the frequency synthesiser in increments of F

XOSC

/2

16

.

f carrier

=

f

XOSC

2

16

FREQ

[

23 : 0

]

Bit Field Name

7:0 FREQ[15:8]

0x0E: FREQ1 – Frequency control word, middle byte

R/W Description Reset

196

(0xC4)

Bit Field Name

7:0 FREQ[7:0]

0x0F: FREQ0 – Frequency control word, low byte

R/W Description Reset

236

(0xEC)

Bit Field Name

7:4 Reserved

3:0 DRATE_E[3:0]

0x10: MDMCFG4 – Modulator configuration

Reset R/W Description

CC1101

).

12 (0x0C) R/W The exponent of the user specified symbol rate.

SWRS037A Page 47 of 60

Bit Field Name

7:0 DRATE_M[7:0]

CC1150

0x11: MDMCFG3 – Modulator configuration

Reset

34 (0x22)

R/W Description

R/W The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9 th

bit is a hidden

‘1’. The resulting data rate is:

R

DATA

=

(

256

+

DRATE

_

M

)

2

DRATE

_

E

2

28

f

XOSC

The default values give a data rate of 115.051 kBaud (closest setting to 115.2 kBaud), assuming a 26.0 MHz crystal.

SWRS037A Page 48 of 60

Bit Field Name

7 Reserved

6:4 MOD_FORMAT[2:0]

0x12: MDMCFG2 – Modulator configuration

Reset

0

0

R/W Description

R0 Defined on the transceiver version (

CC1101

).

R/W The modulation format of the radio signal

CC1150

3 MANCHESTER_EN 0

2:0 SYNC_MODE[2:0] 2

0 (000) 2-FSK

1 (001) GFSK

2 (010) -

3 (011) ASK/OOK

4 (100) -

5 (101) -

6 (110) -

7 (111) MSK

The OOK/ASK pulse shaping feature is only supported for output powers up to -1 dBm.

MSK is only supported for data rates above 26 kBaud.

0 = Disable

1 = Enable

R/W Combined sync-word qualifier mode.

The values 0 (000) and 4 (100) disables preamble and sync word transmission. The values 1 (001), 2 (001), 5 (101) and 6

(110) enables 16-bit sync word transmission. The values 3

(011) and 7 (111) enables repeated sync word transmission.

The table below lists the meaning of each mode (for compatibility with the

CC1101

transceiver):

Setting Sync-word qualifier mode

0 (000) No preamble/sync word

1 (001) 15/16 sync word bits detected

2 (010) 16/16 sync word bits detected

3 (011) 30/32 sync word bits detected

4 (100) No preamble/sync, carrier-sense above threshold

5 (101) 15/16 + carrier-sense above threshold

6 (110) 16/16 + carrier-sense above threshold

7 (111) 30/32 + carrier-sense above threshold

SWRS037A Page 49 of 60

CC1150

Bit Field Name

7 FEC_EN

0x13: MDMCFG1 – Modulator configuration

Reset

0

6:4 NUM_PREAMBLE[2:0] 2

R/W Description

R/W Enable Forward Error Correction (FEC) with interleaving for packet payload

0 = Disable

1 = Enable (Only supported for fixed packet length mode, i.e.

PKTCTRL0.LENGTH_CONFIG=0

)

R/W Sets the minimum number of preamble bytes to be transmitted

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

6

8

12

16

24

3

4

Number of preamble bytes

2

3:2

1:0 CHANSPC_E[1:0] 2

Bit Field Name

7:0 CHANSPC_M[7:0]

0x14: MDMCFG0 – Modulator configuration

Reset

248 (0xF8)

R/W Description

R/W 8-bit mantissa of channel spacing (initial 1 assumed). The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format:

f

CHANNEL

=

f

XOSC

2

18

(

256

+

CHANSPC

_

M

)

2

CHANSPC

_

E

CHAN

The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency.

SWRS037A Page 50 of 60

CC1150

Bit Field Name

7

6:4 DEVIATION_E[2:0]

3

2:0 DEVIATION_M[2:0]

0x15: DEVIATN – Modulator deviation setting

R/W Description Reset

4

7 R/W When MSK modulation is enabled:

Specifies the fraction of symbol period (1/8-8/8) during which a phase change occurs (‘0’: +90deg, ‘1’:-90deg). Refer to the

SmartRF Studio [11] software for correct DEVIATN setting when

using MSK.

When 2-FSK/GFSK modulation is enabled:

Deviation mantissa, interpreted as a 4-bit value with MSB implicit

1. The resulting frequency deviation is given by:

f dev

=

f xosc

2

17

( 8

+

DEVIATION

_

M

)

2

DEVIATION

_

E

The default values give ±47.607 kHz deviation, assuming 26.0

MHz crystal frequency.

When ASK/OOK modulation is enabled:

This setting has no effect.

0x17: MCSM1 – Main Radio Control State Machine configuration

Bit Field Name

7:6

5:2 Reserved

1:0 TXOFF_MODE[1:0]

Reset R/W Description

12 R0 Defined on the transceiver version (

CC1101

).

0 R/W Select what should happen when a packet has been sent (TX)

Setting Next state after finishing packet transmission

0 (00)

1 (01)

2 (10)

3 (11)

IDLE

FSTXON

Stay in TX (start sending preamble)

Do not use, not implemented on

CC1150

SWRS037A Page 51 of 60

CC1150

0x18: MCSM0 – Main Radio Control State Machine configuration

R/W Description Bit Field Name

7:6

5:4 FS_AUTOCAL[1:0]

Reset

0)

3:2 PO_TIMEOUT

1:0 Reserved

1

R/W Automatically calibrate when going to TX, or back to IDLE

Setting When to perform automatic calibration

0 (00) Never (manually calibrate using

SCAL

strobe)

1 (01) When going from IDLE to TX (or FSTXON)

2 (10) When going from TX back to IDLE

3 (11) Every 4 th

time when going from TX to IDLE

R/W Programs the number of times the six-bit ripple counter must expire after XOSC has stabilized before CHP_RDY_N goes low.

The XOSC is off during power-down and if the regulated digital supply voltage has sufficient time to stabilize while waiting for the crystal to be stable, PO_TIMEOUT can be set to 0. For robust operation it is recommended to use PO_TIMEOUT=2.

Setting Expire count Timeout after XOSC start

0 (00) 1

1 (01) 16

2 (10) 64

3 (11) 256

Approx. 2.3 µs – 2.7 µs

Approx. 37 µs – 43 µs

Approx. 146 µs – 171 µs

Approx. 585 µs – 683 µs

Exact timeout depends on crystal frequency.

In order to reduce start up time from the SLEEP state, this field is preserved in powerdown (SLEEP state).

R0 Defined on the transceiver version (

CC1101

)

Bit Field Name

7:6

5:4 LODIV_BUF_

CURRENT_TX[1:0]

3

2:0 PA_POWER[2:0]

0x22: FREND0 – Front end TX configuration

Description Reset

1

R/W

R0

R/W Adjusts current TX LO buffer (input to PA). The value to use in

register field is given by the SmartRF Studio [11] software.

0 R/W Selects PA power setting. This value is an index to the PATABLE, which can be programmed with up to 8 different PA settings. In

ASK mode, this selects the PATABLE index to use when transmitting a ‘1’. PATABLE index zero is used in ASK when transmitting a ‘0’. The PATABLE settings from index ‘0’ to the

PA_POWER value are used for ASK TX shaping, and for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats.

SWRS037A Page 52 of 60

CC1150

Bit Field Name

7:6 FSCAL3[7:6]

0x23: FSCAL3 – Frequency synthesizer calibration

5:4 CHP_CURR_CAL_EN[1:0]

3:0 FSCAL3[3:0]

Reset

2 (0x02)

2 (0x02)

9 (0x09)

R/W Description

R/W Frequency synthesizer calibration configuration. The value to write in this field before calibration is given by the

SmartRF

®

Studio software.

R/W Disable charge pump calibration stage when 0.

R/W Frequency synthesizer calibration result register. Digital bit vector defining the charge pump output current, on an exponential scale: I_OUT = I0·2FSCAL3[3:0]/4

Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and

saving the resulting FSCAL3, FSCAL2 and FSCAL1 register

values. Between each frequency hop, calibration can be

replaced by writing the FSCAL3, FSCAL2 and FSCAL1

register values corresponding to the next RF frequency.

Bit Field Name

7:6

5 VCO_CORE_H_EN

5:0 FSCAL2[5:0]

0x24: FSCAL2 – Frequency synthesizer calibration

Reset R/W Description

0 R/W Choose high (1)/ low (0) VCO.

10 (0x0A) R/W Frequency synthesizer calibration result register. VCO current calibration result and override value.

Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values.

Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.

Bit Field Name

7:6

5:0 FSCAL1[5:0]

0x25: FSCAL1 – Frequency synthesizer calibration

Reset R/W Description

32 (0x20) R/W Frequency synthesizer calibration result register. Capacitor array setting for VCO coarse tuning.

Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values.

Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.

Bit Field Name

7 Reserved

6:0 FSCAL0[6:0]

0x26: FSCAL0 – Frequency synthesizer calibration

Reset R/W Description

13 (0x0D) R/W Frequency synthesizer calibration control. The value to use in

register field is given by the SmartRF Studio [11] software.

SWRS037A Page 53 of 60

Bit Field Name

7:0 FSTEST[7:0]

0x29: FSTEST – Frequency synthesizer calibration control

Reset R/W Description

87 (0x57) R/W For test only. Do not write to this register.

CC1150

Bit Field Name

7:0 PTEST[7:0]

Reset

127

(0x7F)

0x2A: PTEST – Production test

R/W Description

R/W Writing 0xBF to this register makes the on-chip temperature sensor available in the IDLE state. The default 0x7F value should then be written back before leaving the IDLE state. Other use of this register is for test only.

Bit Field Name

7:0 TEST2[7:0]

Reset

0x2C: TEST2 – Various test settings

R/W Description

R/W

The value to use in this register is given by the SmartRF Studio [11]

software.

Bit Field Name

7:0 TEST1[7:0]

0x2D: TEST1 – Various test settings

Reset

49

(0x21)

R/W Description

R/W

The value to use in this register is given by the SmartRF Studio [11]

software.

Bit Field Name

7:2 TEST0[7:2]

1 VCO_SEL_CAL_EN

0 TEST0[0]

0x2E: TEST0 – Various test settings

Reset R/W

2(0x02) R/W

1

1

R/W

R/W

Description

The value to use in this register is given by the SmartRF Studio [11]

software.

Enable VCO selection calibration stage when 1. The value to use in

this register is given by the SmartRF Studio [11] software.

The value to use in this register is given by the SmartRF Studio [11]

software.

SWRS037A Page 54 of 60

CC1150

25.2 Status register details

Bit Field Name

7:0 PARTNUM[7:0]

0x30 (0xF0): PARTNUM – Chip ID

Reset R/W

2 (0x02) R

Description

Chip part number.

Bit Field Name

7:0 VERSION[7:0]

0x31 (0xF1): VERSION – Chip ID

Reset R/W

4 (0x04) R

Description

Chip version number.

0x35 (0xF5): MARCSTATE – Main Radio Control State Machine state

Bit Field Name

7:5 Reserved

4:0 MARC_STATE[4:0]

Reset R/W Description

R0

R Main Radio Control FSM State

Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

State name

SLEEP

IDLE

XOFF

VCOON_MC

REGON_MC

MANCAL

VCOON

State (Figure 16, page 30)

SLEEP

IDLE

XOFF

MANCAL

MANCAL

MANCAL

FS_WAKEUP

7 (0x07)

8 (0x08)

REGON

STARTCAL

9 (0x09) BWBOOST

10 (0x0A) FS_LOCK

11 (0x0B) N/A

12 (0x0C) ENDCAL

13 (0x0D) N/A

14 (0x0E) N/A

15 (0x0F) N/A

16 (0x10) N/A

17 (0x11) N/A

18 (0x12) FSTXON

FS_WAKEUP

CALIBRATE

SETTLING

SETTLING

N/A

CALIBRATE

N/A

N/A

N/A

N/A

N/A

FSTXON

19 (0x13) TX

20 (0x14) TX_END

21 (0x15) N/A

TX

TX

N/A

22 (0x16) TX_UNDERFLOW TX_UNDERFLOW

Note: it is not possible to read back the SLEEP or XOFF state numbers because setting CSn low will make the chip enter the

IDLE mode from the SLEEP or XOFF states.

SWRS037A Page 55 of 60

CC1150

Bit Field Name

7:2 Reserved

1

0

GDO0

0x38 (0xF8): PKTSTATUS – Current GDOx status

Reset R/W Description

R0 Defined on the transceiver version (

CC1101

).

GDO0

value. Note: the reading gives the non-inverted value irrespective what

IOCFG0.GDO0_INV

is programmed to.

It is not recommended to check for PLL lock by reading

PKTSTATUS[0]

with

GDO0_CFG

= 0x0A.

0x39 (0xF9): VCO_VC_DAC – Current setting from PLL calibration module

Bit Field Name

7:0 VCO_VC_DAC[7:0]

Reset R/W Description

R Status registers for test only.

0x3A (0xFA): TXBYTES – Underflow and number of bytes

Bit Field Name

7 TXFIFO_UNDERFLOW

6:0 NUM_TXBYTES

Reset R/W Description

R

R Number of bytes in TX FIFO.

SWRS037A Page 56 of 60

26 Package Description (QLP 16)

26.1 Recommended PCB layout for package (QLP 16)

CC1150

Figure 24: Recommended PCB layout for QLP 16 package

Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC1150EM

reference design ( [1] and [2]).

The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed.

SWRS037A Page 57 of 60

CC1150

27 References

[1]

[2]

[3]

[4]

[5]

CC1150EM 315 - 433 MHz Reference Design www.ti.com/lit/zip/swrr041

CC1150EM 868 - 915 MHz Reference Design www.ti.com/lit/zip/swrr042

DN012 Programming Output Power on CC1100 and CC1150 www.ti.com/lit/swra150

AN039 Using the CC1100/CC1150 in the European 433 and 868 MHz ISM Bands www.ti.com/lit/swra054

DN006 CC11xx Settings for FCC 15.247 Solutions www.ti.com/lit/swra123

[6]

[7]

[8]

[9]

DN017 CC11xx 868/915 MHz Matching www.ti.com/lit/swra168

AN058 Antenna Selection Guide www.ti.com/lit/swra161

CC1150 Errata Notes www.ti.com/lit/swrz018

DN501 PATABLE Access www.ti.com/lit/swra110

[10] AN001 SRD Regulations for Licence Free Transceiver Operation www.ti.com/lit/swra090

Studio

[12] CC1100/CC1150DK& CC2500/CC2550DK Development Kit Examples and Libraries User

Manual

SWRS037A Page 58 of 60

28 General Information

CC1150

Revision Date Description/Changes

SWRS037A 2009-07-20

Changed title of the datasheet

Updated from preliminary datasheet to active

Removed “Chipcon Products from Texas Instruments” Logo

Generally updated text, edited and formatted text

Added Voltage ramp-up and ESD info in Table 1

Moved the General Characteristics before the Electrical Specifications

Updated data rate and modulation info in Table 3

Added links to reference designs

Updated numbers in Table 4 and added link to DN012

Added links to AN039 and DN006

Added information regarding load impedance, TX harmonics and spurious

emission information and TX latency in Table 5

Added information regarding crystal load capacitance and changed start-up

time in Table 6

Added phase noise information in Table 7

Updated information regarding the analog temperature sensor in Table 8

Updated the application circuit figures and corresponding information and

tables in section 7

Moved and added figures and information regarding the crystal to section

7.3 and regarding using an external reference signal instead of a crystal in section 7.4, removed information regarding SmartRF Studio and crystal

choice

Added information regarding the 699 MHz filter and wire wound inductors in

section 7.5 and added link to DN017

Added information regarding the 699 MHz filter and wire wound inductors in

section 7.5 and added link to DN017

Added section 7.7 and link to AN058

Added section regarding PCB layout recommendations (section 7.8) and

Figure 6

Updated Figure 7

Updated SmartRF Studio appearance figure and added information on where to find default configuration register values

Added more information in section 10

Moved Figure 9 and added Figure 11 and Table 15 and Table 16.

Added section 10.3 SPI Read and link to the CC1150 Errata Notes

Added information in section 10.4 and Figure 10

Added link to DN501 and output power limit when using ASK

Added section 11.3 and Table 17

Added Table 18

Added more information in section 13 (recommended number of preamble

and sync word bytes, not turn of TX during first part of a byte, how to leave

TXFIFO UNDERFLOW etc)

Added section 13.4

SWRS037A Page 59 of 60

Revision

1.1

1.0

CC1150

Date Description/Changes

Added more information in section 14

Added 12

Added Table 19

Added more information in section 15 and updated Figure 15

Updated section 16.1 and added Figure 17

Added information regarding the PLL lock signal in section 19

Updated section 21, Table 22 and Table 23 and added Figure 22

Updated 24

Added more information in section 23

Added section 24 and link to AN001

Updated section 25 and register descriptions

Changed IOCFG0 –

GDO0

output pin configuration description

Changed MDMCFG2 – Modulator configuration description

Updated the FSCAL registers and TEST registers

Replaced old Chipcon packet information with the TI packet information and updated this to fit TI formatting.

Added reference to SmartRF Studio website

Link to swru109

Added the Reference Chapter

2005-06-27 Added matching information. Added information about using a reference signal instead of a crystal.

2005-04-20 First preliminary data sheet release

Table 29: Document History

SWRS037A Page 60 of 60

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

CC1150-RTR1

CC1150-RTY1

Status

(1)

ACTIVE

ACTIVE

Package Type Package

Drawing

VQFN

VQFN

RST

RST

Pins Package

16

16

Qty

Eco Plan

(2)

2500 Green (RoHS

& no Sb/Br)

490 TBD

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-3-260C-168 HR

Call TI Call TI

Op Temp (°C)

-40 to 85

-40 to 85

Top-Side Markings

(4)

CC1150

CC1150

CC1150RST

CC1150RSTG3

ACTIVE

ACTIVE

VQFN

VQFN

RST

RST

16

16

490

490

TBD

TBD

Call TI

Call TI

Call TI

Call TI

-40 to 85

-40 to 85

CC1150

CC1150

CC1150RSTR ACTIVE VQFN RST 16 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 CC1150

CC1150RSTRG3 ACTIVE VQFN RST 16 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

CC1150

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

14-Mar-2013

*All dimensions are nominal

Device

CC1150RSTR

Package

Type

Package

Drawing

VQFN RST

Pins

16

SPQ

2500

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

12.4

A0

(mm)

4.3

B0

(mm)

4.3

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.5

8.0

12.0

Q2

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

14-Mar-2013

*All dimensions are nominal

Device

CC1150RSTR

Package Type Package Drawing Pins

VQFN RST 16

SPQ

2500

Length (mm) Width (mm) Height (mm)

338.1

338.1

20.6

Pack Materials-Page 2

IMPORTANT NOTICE

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Products Applications

Audio

Amplifiers

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

Logic

Power Mgmt

Microcontrollers

RFID

OMAP Applications Processors

Wireless Connectivity www.ti.com/audio amplifier.ti.com

dataconverter.ti.com

www.dlp.com

dsp.ti.com

www.ti.com/clocks interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

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Computers and Peripherals

Consumer Electronics

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Industrial

Medical

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Space, Avionics and Defense www.ti.com/space-avionics-defense

Video and Imaging

TI E2E Community

www.ti.com/wirelessconnectivity www.ti.com/video e2e.ti.com

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Copyright © 2013, Texas Instruments Incorporated

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