Ismael Omar Tunable Microwave Phase Locked Oscillator Phase Locked Loop Implementation Helsinki Metropolia University of Applied Sciences Bachelor of Engineering Electronics Thesis November 2015 Abstract Author(s) Title Ismael Omar Tunable Microwave Phase Locked Oscillator Number of Pages Date 52 pages + 3 appendices 19 November 2015 Degree Bachelor of Engineering Degree Programme Electronics Specialisation option Instructor(s) Thierry Baills, Senior Lecturer The demand for high data rates and low power consumption has had a major impact on the design of RF frequency synthesis systems. The need for highly stable oscillators is one of the main driving force in most communication systems that utilise the super heterodyne architecture. Not only the communication systems, but a variety of measurement equipment require a low noise local oscillator such the spectrum analyser. The goal of this thesis work was to design and analyse frequency synthesis in the microwave range for laboratory use. The design utilises the Analog Devices ADF4155 Phase Locked Loop synthesizer integrated circuit. The chip incorporates the control circuitry required to implement a phase locked oscillator. The Phase Locked Oscillator system compromises the ADF4155 PLL, Zcomm V940ME03 Voltage Controlled Oscillator and a fourth order Loop Filter. The thesis concentrates mainly on the design and analysis of the loop filter and the characterisation of the phase noise of the generated signal. Finally, an L-Band signal of 1.45 GHz is generated and phase noise measurement is done. The measured value of the phase noise is compared with the simulated value. Further work may involve doing measurements on frequency settling time and phase jitter of the generated signal. Keywords Phase Locked Oscillator, Loop Filter, Phase Noise, Frequency Synthesis, L-Band, Fractional-N. Contents Acronyms 1 Introduction 1 2 Theoretical Background 1 2.1 Purpose 1 2.3 Linear Analysis of Classical PLL Circuits 5 2.3.2 7 2.2 2.4 3 2.5 2.3.1 Type and Order of the PLL The Steady-State Error 2 6 Nonlinear analysis of Classical PLL Circuits 7 2.4.2 7 2.4.1 Phase Plane 2.4.3 Circle/Popov Criteria Lyapunov redesign Phase Noise (Spectral Purity) 7 8 8 Phase-Locked Oscillator Components 9 3.1 Introduction 9 3.3 Phase Detectors 3.2 3.4 3.5 3.6 3.7 4 PLL Basics Reference oscillator 10 Loop Filter 15 3.4.1 3.4.2 Stability of the control system PLL Control Theory 10 16 18 Voltage Controlled Oscillator 20 3.6.1 20 Digital PLL Synthesis 3.6.2 Integer-N PLL Fractional-N PLL 20 22 Analog Devices ADF4155 PLL Synthesizer 23 3.7.2 24 3.7.1 Reference Input 3.7.3 Phase Frequency Detector and Charge Pump 3.7.4 RF N Counter Output Stage Noise Parameters 24 26 26 27 4.1 Noise in Voltage Controlled Oscillator 28 4.3 PLO Phase Noise Contributors 31 4.2 Leeson’s Equation 29 5 Design Task 33 5.1 33 Loop Filter Design 5.1.1 Loop Filter Topology and Order 5.1.3 Loop Filter Transfer function and Open Loop Gain 34 Component Values Calculation from Time Constants 36 5.2.1 Circuit Topology 36 5.2.3 Calculating Component Values from the Time Constants 5.1.2 5.1.4 5.2 5.1.5 5.4 6 Time Constants Derivation Loop Filter Component Values Calculation 5.2.2 5.3 Phase Margin, Loop Bandwidth, and Pole Ratios Loop Transfer Function and Time Constant Derivation 1.45 GHz L-Band signal generation System Simulation 5.4.1 5.4.2 Frequency Domain Time Domain 33 34 35 36 37 39 41 42 43 44 Measurement 45 6.1 Phase Noise Measurements 45 6.1.2 47 6.1.1 Measurement procedure 6.1.3 Measured Phase Noise Values 7 Discussion 8 Conclusion Measurement Setup References Appendices Appendix 1. MathCAD Code for Loop Filter Calculation Appendix 2. ADF4155 Synthesizer Values Calculation Appendix 3. ADF4155 Evaluation Board and Spectrum Analyser Output 46 48 48 50 51 Acronyms VCO Voltage Controlled Oscillator PLL Phase Locked Loop PFD Phase Frequency Detector LO TCXO CP Local Oscillator Temperature Compensated Crystal Oscillator Charge Pump DPLL Digital Phase Locked Loop PLO Phase Locked Oscillator CMOS Complementary Metal Oxide Semiconductor AM Amplitude Modulated RF ECL PM DUT SSB RMS SRD OCXO ASIC Radio Frequency Emitter Coupled Logic Phase Modulated Device under Test Single Sideband Root Mean Square Step Recovery Diode Oven Compensated Crystal Oscillator Application Specific Integrated Circuit 1 1 Introduction Today’s communication systems demand higher frequency, higher data rates, and more channels of operation. The need for low power, portable equipment is also pushing the limits of modern electronic design. Since most of the modern communication systems use the super heterodyne architecture, there is a need for designing highly stable, low noise local oscillator. For simple design a free running Voltage Controlled Oscillator (VCO) will suffice but when low phase noise and high stability is required the design needs to be reconsidered. Typical local oscillator (LO) synthesizers combine a Voltage Controlled Oscillator (VCO) with a Phase-Locked Loop (PLL) IC, high stable frequency reference (e.g. Crystal/TCXO) and a loop filter. The VCO is used to generate the RF output frequency, typically in the Gigahertz (GHz) range, and the PLL is used to stabilize and control the frequency. The loop filter design must integrate all of the components to establish a trade-off between noise and transient response. These all interacting components make up the PhaseLocked Oscillator circuit which acts as local oscillator in many super heterodyne architectures. 2 Theoretical Background In this chapter the theory behind frequency synthesis will be examined. The purpose of the synthesizer as a part of the transceiver architecture is also introduced. The phaselocked loop method is studied and the technique used to control the slave oscillator (VCO) with the master oscillator temperature compensated crystal oscillator (TCXO) is presented. 2.1 Purpose While there are several forms for receiving and processing signals, the most widely used one is the super heterodyne. The super heterodyne (RX, TX) makes use of the heterodyne principle of mixing an incoming signal with the local oscillator (LO) signal in a non- linear element. The super heterodyne receiver RX uses LO frequency offset by a fixed intermediate frequency (IF) from the desired signal. This can be expressed as =| ± | (1) 2 Where IF is the output or intermediate frequency frf is the frequency of received signal of bandwidth Bw fLO is the local oscillator frequency The mixer is a nonlinear element that produces frequencies at the sum and difference of the input frequencies (and a variety of other undesired signals). Figure 1 Mixing of RF with LO signal to produce Intermediate Frequency (IF) Figure 1 illustrates the mixing produces two different signals the unwanted one will be filtered and the other is further processed. 2.2 PLL Basics A phase-locked loop is a feedback system that is combining a voltage controlled oscilla- tor (VCO), a reference oscillator and a phase frequency detector (PFD), allowing the phase control given specific accuracy. The first phase-locked loops were implemented in the early 1930s by a French engineer, de Bellescize. However the PLL found broad acceptance in the marketplace when the integrated circuit PLLs became available at lower cost components in the mid-1960s. [1.] The PLL allows the generation of a variety of output frequencies as multiples or fractions of a single reference frequency. The PLL can be used to accomplish many tasks such as carrier recovery, clock recovery, tracking filters, frequency and phase demodulation, frequency synthesis, and clock synchronization. The main application of the PLL in this thesis work is to generate a local oscillator (LO) that can be used in a microwave systems. The phase-locked loop can be analysed in general as a negative feedback system with a forward gain term and a feedback term. A simple block diagram of a voltage-based negative-feedback system is shown in Figure 2. 3 Figure 2 Standard negative-feedback control system model (Modified from Curtin et al (1999) [1]). In a PLL, the error signal e(s) from the phase frequency detect (PFD) is the difference between the input frequency or the phase and that of the signal fed back to the system. The system will push the frequency or phase error signal to zero in the steady state. The standard equation for a negative-feedback system apply. [1; 2.] = ( ) = ( )× ( ) _ ( )= ( ) ( )− ( )× ( ) ( ) 1+ ( )× ( ) = ( )× ( ) ( ) = 1+ ( )× ( ) _ (2) (3) (4) Because of the integration in the loop the steady state gain, G(s), is high and , _ = 1 ( ) (5) The different components of a phase-locked loop that contribute to the loop gain include: 1. The phase frequency detector (PFD) and charge pump (CP), sensitivity Kd. 2. The loop filter, with transfer function of Z(s) 3. The voltage-controlled oscillator (VCO), with a sensitivity of 4. The feedback divider, 1/N 4 Figure 3 Basic phase-locked loop model (Copied from Curtin et al (1999) [1]). If a multiplier is employed as the PFD, the loop filter and VCO are also analog elements, this is called an analog, or linear PLL (LPLL). Instead of the multiplier if Exclusive OR (EXOR) gate or J-K flip flop is used as the PFD and everything else stays the same, then it is a digital PLL (DPLL). Further if the PLL is built exclusively from digital blocks, without any passive components or linear elements, it becomes all-digital PLL (ADPLL). [1.] As shown in Figure 3, a PLL is used to generate a signal output that has the stability of the reference source. The VCO oscillates at an angular frequency . The fre- quency/phase signal is fed back to the PFD, via a frequency divider with a ratio of 1/N for integer-N PLL. When the two signals in to the PFD are almost equal in phase the error tends to be zero, the loop will be in a locked condition. The input, output frequency and error signal are related as When Hence ( )= ( ) = 0, − = (6) (7) = (8) In commercial PLL chips, the phase frequency detector and charge pump form the error detector block. When the two input signals are not equivalent the error detector will out- put source/sink current pulses to the low-pass loop filter. The loop filter smooths the current pulses into a voltage that controls the VCO frequency. The voltage is applied to the VCO to adjust its output frequency by ∆ , where is the VCO sensitivity in 5 MHz/Volt, and ∆ is the change in the tune voltage of the VCO input. The relationship between the output frequency and VCO tune voltage is shown in Figure 4. [1; 2.] Figure 4 VCO transfer characteristics (Reprinted from Curtin et al (1999) [1]). = (9) The closed-loop gain of the PLL can then be expressed by applying the concept of the negative-feedback system presented earlier. [1.] = 1+ , ( )= , ( ) ( )= ( ) ( ) (10) (11) (12) When the Loop Gain is >>1, the closed-loop transfer function for the PLL system becomes N and hence 2.3 = × Linear Analysis of Classical PLL Circuits (13) The model shown in Figure 3 is a closed-loop feedback system. The transfer function from reference phase input to VCO phase output, T(s), can be obtained as 6 ( ) = ( ) 1+ ( )= = + ( ) ( ) ( ) / ( ) / (14) (15) Similarly, the sensitivity transfer function from the reference phase input to the phase error, ( ), is ( ) = ( ) 1+ ( )= 1 ( ) / (16) The basic properties of interest in this transfer function are the loop stability, order, and the system type. The stability of the system can be determined by a variety of methods, such as root locus, Bode plots, Nyquist plots, and Nichols charts. [3; 5.] 2.3.1 Type and Order of the PLL The type of the PLL refers to the number of poles at DC of the loop transfer function G(s)H(s) located at the origin. The pole usually refers to the denominator in the transfer function. For example: ( ) ( )= 3 ( + 3) (17) This system is type I as there is only one pole at the origin. The order of the PLL refers to the total number of poles or to the highest degree of s in the denominator. 1 + ( ) ( ) = 0∆ . . (18) Where C.E. is the Characteristic Equation. The roots of the C.E. become the closed loop poles of the transfer function: 1+ ( ) ( )= 1+ Then 3 =0 ( + 3) (19) . . = ( + 3) + 3 (20) . .= (21) +3 +3 Which is a 2nd order polynomial. Thus, for the given G(s)H(s), is the type 1 second order system. 7 2.3.2 The Steady-State Error Steady state errors of the PLL can be obtained by applying the Final Value Theorem lim → ( ) = lim = lim → → ( ) ( ) ( ). (22) (23) From equation 16, the presence of a voltage controlled oscillator (VCO) makes every PLL at least a Type 1 system, achieving zero steady state error to a phase step at . For a ramp or a frequency step, there must be another integrator in the forward path, and the natural place for this is the loop filter, ( ). [3; 5.] A third order PLL, which can be Type 3 and have a zero steady state error to a frequency ramp, is relatively rare. There two reasons for this. First, the applications that require that type of performance are found only in very high frequency communications where the Doppler shift of the signal produces a frequency ramp. The second reason is to do with the stability of the third order loop versus that of the second order loop. [1; 3; 5.] 2.4 Nonlinear analysis of Classical PLL Circuits For simplicity, in most cases, when a phase-locked loop is analysed, it is assumed, or approximated, that the components behave linearly. This can help with faster analysis as seen in section 2.3 but when the PLL is implemented there will be discrepancies be- tween measured and simulated values. The reason for this is because the components are behaving differently when implemented in circuit then simulated. There are many nonlinear analysis of PLL devised during the years but only three will be discussed here. [3; 5.] 2.4.1 Phase Plane One of the earliest methods of nonlinear system analysis is the graphical method of phase plane design. This method of analysis dates back to the early days of PLL before the widespread use of computers for such calculations. The use of phase plane portraits is made more practical by the fact that most PLLs are first or second order which does not go beyond the restrictions on phase plane techniques. 2.4.2 Lyapunov redesign Starting with sinusoidal phase detector, mixer, shown in Figure 15, it is possible to apply the technique of Lyapunov Redesign to phase-locked loops. More recently, this method has been extended to classical digital PLLs. 8 2.4.3 Circle/Popov Criteria The difficulty of applying Lyapunov methods to higher order loops has led to the exploration of nonlinear analysis methods suitable for numerical techniques. In particular, the Circle Criterion and the Popov Criterion have been used to check the stability of higher order PLLs. 2.5 Phase Noise (Spectral Purity) Phase noise is a measure of the short-time stability of oscillators. Phase noise is caused by variations of phase or frequency and amplitude of an oscillator output signal, although the amplitude effect is negligible in most cases. These variations have a modulating effect on the oscillator signal. [14.] The phase noise is specified as single-sideband phase noise referenced to the carrier power and as a function of the carrier offset. Figure 5 Phase noise contributions of reference OCXO and VCO The effects of phase noise are illustrated in Figure 5. With high resolution it is expected a single spectral line for a purely sinusoidal signal in the frequency domain but due to noise this is not the case. Phase noise analysis of the VCO is covered in detail in Chapter 4. 9 3 3.1 Phase-Locked Oscillator Components Introduction Phase-locked oscillator (PLO) are the most used systems to synthesize microwave local oscillator frequencies of high spectral purity which are very important in communications and radar application. It combines the far-out phase noise of fundamental oscillators, especially in the microwave frequency range, an excellent long-term stability, and the close-in phase noise of a crystal oscillator (from carrier frequency to 100 kHz away). A voltage-controlled oscillator can be phase locked by two methods [8]: 1. Digital phase lock: This is usually achieved by using a frequency divider to divide the higher frequency of the VCO to the same frequency of the crystal reference. A digital phase detector is then used to acquire the phase lock. The advantage of this method is that it is self-acquiring and can operate at very low frequencies. It is widely used at low frequencies from 1 MHz to 3 GHz. However, this method has two disadvantages. First, the noise floor of the divider will limit its close in phase noise; and second, at microwave frequencies it will not be economical. 2. Analog phase lock: This is achieved by using Step Recovery Diode (SRD) as a comb generator to create a comb of reference frequencies to the frequency of the VCO. The phase detecting is accomplished by using a multiplier (mixer) to detect the phase difference between the reference and the VCO. Phase-locked oscillator consists of various elements which form the complete system. Most of the components that form the phase-locked oscillator can be obtained as a ready-made integrated circuit chips. Figure 6 shows a basic block diagram of a phase- locked oscillator. The design of the passive loop filter will be the focus of this thesis since the other parts are available in IC form. Figure 6 Basic Diagram of Phase-locked Oscillator 10 For the implementation of the PLO the digital phase lock technique is used by employing the Analog Devices ADF4511 PLL synthesizer chip. 3.2 Reference oscillator A reference oscillator is one of the most important components that define the stability and phase noise characteristics of frequency synthesizer. In a frequency synthesis sys- tem the reference oscillator is the master clock and VCO is the slave clock. Various reference oscillator schemes are possible as shown in Figure 7. A 10 MHz temperaturecompensated crystal oscillator (TCXO) provides a small size and cost benefits for lowto moderate-performance applications. [9.] Figure 7 Reference frequency generation schemes (Adapted from Chenakin (2008) [9]). Better stability and noise characteristics can be achieved by using an oven-compensated crystal oscillator (OCXO), but this is a more expensive and bulky part with higher power consumption. It is worth mentioning, that using higher frequency OCXO (e.g., 100 MHz instead of 10 MHz) can potentially result in a better synthesizer noise. There is a comparable noise floor for both parts, but the high frequency reference requires a significantly lower overall multiplication factor. Though better phase noise performance at higher frequency offsets (100 kHz and above) can be obtained with additional low-noise oscillators (e.g., SAW, CRO, or DRO) locked to the main OCXO. The chain of oscillators provides the lowest phase noise profile at any frequency offset and can be used in high-end synthesizer designs [9]. 3.3 Phase Detectors Phase detectors employed in phase locked oscillator (PLO) are multiplier circuits and sequential circuits. Multipliers output average DC value which is the product of input- 11 signal waveform and VCO waveform. Well-designed multipliers are very capable on op- erating at an input signal buried deeply in noise and that is one reason they are mostly employed at frequencies above 10 GHz. [5,114; 9.] Sequential phase detectors contain memory and can recall past events. They are mostly more flexible compared to the multiplier but they have poor noise-handling capability. Sequential phase detectors are usually built up from digital circuits (flip-flops, gates) and operate mostly with binary, rectangular input waveforms. Although they are mostly re- ferred to as “digital” phase detectors this is basically incorrect since the output of a sequential phase detector is an analog quantity and the loops are analog. [4; 5.] The phase detector generates the error signal required in the feedback loop of the syn- thesizer. The majority of PLL application specific integrated circuits (ASICs) use a sequential circuit called a Phase Frequency Detector (PFD) similar to the one shown in Figure 8. Compared with mixers or XOR gates, which can only resolve the phase differ- ences in +/- π range, the PFD can resolve phase differences in the +/- 2π range or more typically “frequency difference” is used to describe a phase difference of more than 2π, hence the term “phase frequency detector”. This circuit shortens the transient switching times and performs the function in a simple and elegant digital circuit. Figure 8 Phase Frequency Detector Schematic (Copied from Barrett (1999) [6]). The PFD compares the Fr with that of (FVCO/N) and activates the charge pumps based on the difference in phase between these two signals. The operational characteristics of the phase detector circuitry can be broken down into three modes: frequency detect, 12 phase detect, and phase locked mode. When the phase difference is greater than ±2π, the device is considered to be in frequency detect mode. In frequency detect mode the output of the charge pump will be a constant current (sink or source, depending on which signal is higher in frequency.) The loop filter integrates this current and the result is continuously changing control voltage applied to the VCO. The PFD will continue to operate in this mode until the phase error between the two input signals drops below 2π. Once the phase difference between the two signals is less than 2π, the PFD begins to operate in the phase detect mode. In this mode of operation the charge pump is only active for a portion of each phase detector cycle that is proportional to the phase difference between the two signals as shown in Figure 9. Once the phase difference between the two signals reaches zero, the device enters the phase locked state. Figure 9 Phase Detector Output (Voltage, Current) Waveforms, for Fv/N<Fr (Copied from Barrett (1999) [6]). In phase locked state, the PFD output will be narrow “spikes” that occur at a frequency equal to Fr. These current spikes are due to the finite speed of the logic circuits (see Figure 10, DOA blow-up) and will have to be filtered so they do not modulate the VCO and generate spurious signals. 13 Figure 10 Phase Detector Timing Waveforms (Copied from Barrett (1999) [6]). The PFD suffers from a zero phase error dead-zone. Because of the logic circuits inside the PFD have non-zero propagation delays and rise time, therefore, the PFD is never capable of generating short pulses for resolving small phase error between the two input signals. The minimum time difference that the phase-frequency detector can sense is called the backlash time. The dead-zone results in undesired behavior of the phase-frequency detector and may lead to unexpected behavior of the phase-locked loop operation. One way to tackle this phenomenon is the charge pump output approach, also another solution is defining the minimum on time for both source and sink charge pumps in locked 14 state. This undesired behavior of the phase-frequency detector will be the reference spurs to be generated. These spurs are mostly the result of mismatches and leakages in the charge pump circuit. Phase frequency detectors (PFD) operate in a frequency discriminator mode for large initial frequency errors and to perform as a coherent phase detector once the system transient response is within the pull-in range of the phase-locked loop as shown in Figure 11. Figure 11 Operating ranges of PLL (Modified from Karhu [4]). The PLL should have a good tracking capability. The hold range, ∆ , is the frequency range that the PLL is able to maintain phase tracking. It can be determined by the calcu- lation of the frequency offset at the reference input that causes the phase error to be beyond the range of linear analysis. For a multiplier or XOR phase detector the phase error is 90˚. For sequential detectors, such as the phase frequency detector (PFD) it will be larger. The phase detector and the hold range is related by the following equation. [3; 5.] The lock range, ∆ ∆ = (0). (24) , is defined as the frequency range within which the PLL locks within one single-beat note between the reference frequency and output frequency. The lock range is calculated from nonlinear equation, but there are useful approximations that are made. In particular, if the relative order of numerator and denominator of the PLL is 1, then the loop can be said to behave like a first order loop at higher frequencies, and thus the lock range can be estimated as. [3; 5.] ∆ ≈± (∞) . (25) 15 The pull-in range, ∆ become locked. [3.] 3.4 , is defined as the frequency range in which the PLL will always Loop Filter Phase-frequency detectors with the current source charge pump seem to be the most used in commercial low cost synthesizer chips. The charge pump PLL offers many advantages over the traditional ones such as an infinite pull-in range and zero steady state error. The design of the loop filter involves a trade-off between reference sidebands and switching speed. The loop filter should be designed for the correct balance between reference spurs and the lock time that the system requires. [2; 3.] There are two types of loop filters employed in PLL design, active and passive. Active loops use op-amps, are usually differential, and allow the synthesizer to generate tuning voltage levels higher than PLL IC can generate on-chip. The op-amp itself provides the DC amplification necessary to develop a control voltage that is higher than the on-chip supply of the phase detector. Active loops are mostly used in wideband applications. Most PLL ASICs use a current source for the output to generate the control voltage. This output is proportional to the phase error. This current source loop filter configuration is the most popular for wireless, narrow-band applications. [3.] There are many types of passive loop filter. The most employed one, in simple designs, is the third-order shown in Figure 12. As a rule of thumb, the loop filter bandwidth should be 1/10 of the PFD frequency (channel spacing). Increasing the loop bandwidth will re- duce lock time, but the filter bandwidth should never be more than PFD/5, to avoid significantly increasing the risk of instability. Figure 12 A third-order loop filter. The bandwidth of the loop filter can be doubled by either doubling the PFD frequency or the charge-pump current. If the actual Kv of the VCO is significantly higher than the nominal Kv used to design the loop filter, the loop bandwidth will be significantly wider than expected. The variation of the loop bandwidth with Kv presents a major design challenge 16 in wideband PLL designs, where Kv can vary by more than 300%. Adjusting the programmable charge-pump current of the chip is the easiest way to compensate for changes in the loop bandwidth caused by variation in Kv. 3.4.1 Stability of the control system Determining the stability of the phase-locked loop is very important part of the design of a frequency synthesizer. Stability analysis not only determines whether the loop will os- cillate, but determines the overall performance of the loop. Bode-plot is one of the useful tools for analysing the stability of a control system. It displays the open-loop transfer function magnitude and phase. If G(s) = -1 then <G(s) = -180o then in these conditions the denominator of the transfer function = 1+ (26) Becomes zero and the transfer response becomes infinite making the loop unstable. [4.] This is the reason why the difference of the phase of the open-loop gain from 180o at the frequency when the gain equals unity is the common measure of the stability, called phase margin. A second order loop is unconditionally stable because the maximum phase shift of the two poles is -180o and this occurs at very high frequencies when the gain is less than unity. As a rule of thumb, in order for a system to be stable, phase margin should be somewhere between 45o to 50o. [4.] The loop filter shown in Figure 13 is a low-pass type. The transient response of the loop depends on: 1. the magnitude of the pole/zero, 2. the charge pump sensitivity Kd, 3. the VCO sensitivity Kv, 4. the feedback factor, N in case of integer-N PLL The above four parameters should be taken into account when designing the loop filter. Also the filter should be designed so the system (PLL) is stable (around 45˚ phase margin). The 3-dB cutoff frequency is the loop bandwidth, . Larger loop bandwidths have the advantage of fast settling time but with the cost of increased noise in the PLL which is mostly avoided. [1; 2.] 17 Figure 13 Second Order Passive Lag Filter For a 2nd loop with natural frequency (loop bandwidth) and damping factor , the switching speed (TSW ) is proportional to the inverse of their product. 1 ∝ (27) Further the second order PLL system can be described as follows: 2 ( )= Where And 1 = 2 ( = Figure 14 Complex Poles S-Plane Plot − +2 + + + ) ( + + ) (28) (29) (30) 18 From Figure 14 the poles are located at distance from the origin and at an angle . The damping factor, , is a measure of stability. 3.4.2 = PLL Control Theory Phase-locked Loops have many unique characteristics when viewed from the control theory perspective. The first part is that their correct operation depends on the fact that they are nonlinear devices contrary to one presented in Section 2.2 for simplifying the analysis. The loop does not work as expected without the presence of nonlinear devices, namely the phase-detector, when the phase detector is employed as a mixer, and VCO. These devices take the problem from signal response to phase response and back again. This is further accompanied by the time scale shift involved since the PLLs operate on signal whose centre frequency is much higher than the loop bandwidth. Most of the time the order of the PLL is either first or second order. The complete feedback loop design replaces control law design, and the design is governed only by the required characteristics of the input reference signal and the required output signal. [3.] Figure 15 Classical PLL using mixer as phase detector (Modified from Abramovitch (2003) [3]). The idea is that if a sinusoidal signal is injected into the reference, the internal oscillator will lock to the reference such that the frequency and phase differences between them will be driven to some constant value or 0 (depending on the system type). The internal sinusoid then represents a smoothed version of the reference. [2; 3.] Practical PLLs mostly resemble the diagram shown in Figure 15, in which a high frequency low-pass filter is used to attenuate the double frequency term of the mixer and bandpass filter is mostly used to limit the bandwidth of input signal to the loop. 19 A general sinusoidal signal at the reference input of a PLL as shown in Figure 15 can be written as [3]: ( = ). + (31) For simplicity it is assumed that the output signal from the Voltage Controlled Oscillator (VCO) into the mixer is given by = = cos( ( )= sin( The output of the mixer is then given by = Where + + ). (32) ) cos( + ) (33) is the conversion gain of the mixer. The analysis is done by taking several steps. One that is mostly used is the trigonometric identity in terms of the PLL: 2 sin( + ) cos( = sin ( + + ) ) + + = − + sin(( − ) + − ) (34) Taking two fundamental assumptions leads to the most commonly used model of the analog PLL. Let Then the assumptions are: (35) 1. The first part in Equation 34 is attenuated by the loop filter and by the low pass 2. nature of the PLL itself. ≈ , so the difference can be incorporated into . Making these assumptions leads to the PLL model shown in Figure 3. The problem is that the system is still nonlinear and as such in general difficult to analyze. The typical methods of analysis include [3]: 1. Linearization: For sin small and slowly varying ≈ , ≈ 1, ≈ 0. (36) This is useful for studying loops that are near lock and it does not help in the analysis of the loop when is large. 2. Phase plane portraits is the graphical method of analyzing the behavior of low order, usually up to 2, nonlinear systems about a singular point. 3. Simulation is another type of analysis but it is not easy so most of the time the response of the components of the PLL (phase detector, filter, VCO) are simulated in signal space and then the entire loop is simulated only in phase space. 20 The linearized model shown in Figure 3 is what is used mostly for the analysis and meas- urements of phase-locked loops. It is possible to learn a few things about the behavior of the PLL from linear analysis. However, this model does not accurately represent the system and some issues come up when constructing the PLL. 3.5 Voltage Controlled Oscillator Voltage Controlled Oscillator is a fundamental building block in the frequency synthesizer architecture. The VCO has a variety of applications e.g. in communication, PLL, medical field etc. In the above mentioned applications, high frequency with low power is required. There are many requirements placed on VCOs in different applications. These requirements are usually in conflict with one another, and therefore a compromise is needed. Some of the more important requirements include [12]: 1. Phase noise(dBc/Hz) 2. Tuning sensitivity (Hz/V) 3. RF power (dBm) 4. Harmonic/Spurious (dBc) 5. Frequency pushing (Hz/V) and frequency pulling (Hz p-p) To achieve optimal circuit performance, many VCO characteristics should be evaluated under varying conditions. For example, a very fundamental parameter is the VCO output frequency versus tuning voltage (F-V). One extension of this parameter is tuning sensitivity (Hz/V), which is the differential of the F-V curve. Ideally this is a constant, but it is not in most cases. The slope change, as a function of frequency, is also very important to know since this is a critical design parameter for the loop filter. [5; 12.] 3.6 Digital PLL Synthesis Among the many different frequency synthesis techniques, the dominant method used in the wireless communications industry is the digital PLL circuit. While there are some benefits to using other synthesis technique, they are outside the scope of this thesis and will not be discussed. 3.6.1 Integer-N PLL Compared to the analog techniques used in the frequency synthesis, the modern PLL is now a mostly digital circuit. Figure 16 shows a typical block diagram of PLL implemented with a TCXO reference [6]. 21 Figure 16 Integer-N PLL Block Diagram (Copied from Barrett (1999) [6]). The PLL circuit performs frequency multiplication, via a negative feedback mechanism, to generate the output frequency, FVCO, in terms of the phase detector comparison frequency, Fr [6]. = × (37) To achieve this, a reference frequency must be provided to the phase detector. Typically, the TCXO frequency (Fx), is divided down (by R) “on-board” the PLL IC. The phase detector utilizes this signal as a reference to tune the VCO and, in a “locked state,” it must be equal to the desired output frequency, Fvco, divided by N. [1; 6.] = = (38) Therefore, the output frequency that the synthesizer generates, F VCO, can be changed by reprogramming the divider N to a new value. By changing the value N, the VCO can be tuned across the frequency band of interest. The only constraint to the frequency output of the system is that the minimum frequency resolution, or channel spacing, is equal to Fr. ℎ = = (39) When the phase-locked loop is in unlocked state (such as during initial power up or immediately after reprogramming a new value for N) the phase detector will create an error voltage based on the difference of the phase value between the two input signals. The error voltage will tune the VCO frequency until the system is in lock state. If the crystal (TCXO) has an accuracy of 1 part-per-million (ppm), the output frequency of the synthesizer has high frequency stability and accuracy to 1 ppm. [6.] 22 As an example, when Fr = 30 kHz and N = 32000, the only way for this circuit to be in a stable state locked is when FVCO = 960 MHz If N were changed to 32001, a frequency and phase error will develop at the input of the phase detector that will, in turn, retune the VCO frequency until a locked state has been reached. The locked state will be reached when FVCO = 960 MHz and, if the TCXO has an accuracy of 1ppm, the output of the VCO will be accurate to ~ +/- 960 Hz. 3.6.2 Fractional-N PLL In digital phase-locked loop frequency synthesis an unavoidable situation that almost always arises is that frequency multiplication (by N), raises the signal phase noise by 20Log (N) dB The main source of this noise is the noise characteristics of the phase frequency detector (PFD) active circuitry. Because the PFD are typically the dominant source of close-in phase noise, N becomes a limiting factor when determining the lowest possible phase noise performance of the output signal. A multiplication factor of N = 30,000 will add about 90 dB to the phase detector noise floor. 30,000 is a typical N value used by an integer-N PLL synthesizer for a cellular transceiver with 30 kHz channel spacing. Theoretically the phase noise of the system could be reduced by reducing the value of N but the channel spacing of an integer-N synthesizer is dependent on the value of N. Due to this situation, the phase detectors typically operate at a frequency equal to the channel spacing of the communication system.[6; 7.] A phase frequency detector (PFD) is a digital circuit that generates high levels of transi- ent noise at its frequency of operation, Fr. This noise is superimposed on the control voltage to the VCO and modulates the VCO RF output accordingly. This interference can be seen as spurious signals at offsets of +/- Fr (and its harmonics) around FVCO. To prevent this unwanted spurious noise, a filter at the output of the charge pumps (called the loop filter) must be present and appropriately narrow in bandwidth. Unfortunately, as the loop filter bandwidth decreases, the time required for the synthesizer to switch between channels increases. [1; 5; 6; 7.] If N could be made much smaller, Fr would increase and the loop filter bandwidth required to attenuate the reference spurs could be made large enough so that it does not impact the required switching speed of the system. However, the upper limit of Fr is bound by channel spacing requirement. This illustrates how the desire to optimize both switching speed and spur suppression directly conflict with each other. [6.] 23 Fractional-N PLL technology made it possible to alter the relationship between N, F r, and the channel spacing of the synthesizer. It is now possible to achieve frequency resolution that is a fractional portion of the phase detector frequency. This is accomplished by add- ing internal circuitry that enables the value of N to change dynamically during the locked state. If the value of the divider is “switched” between N and N+1 in the correct proportion, an average division ratio can be realized that is N plus some arbitrary fraction, K/F. This allows the phase detectors to run at a frequency that is higher than the synthesizer channel spacing. [6.] Where = ( + ) (40) F = the fractional modulus of the circuit (i.e. 8 would indicate 1/8th fractional resolution.) K= the fractional channel operation. 3.7 Analog Devices ADF4155 PLL Synthesizer The ADF4155 PLL synthesizer allows the implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with external loop filter, external voltage controlled oscillator (VCO), and external reference frequency (TCXO). As shown in Figure 17 the ADF4155 have a built-in phase comparator and charge pump logic and many peripheral logic circuits that make it highly reconfigurable device for different applications. [11.] 24 Figure 17 ADF4155 PLL Functional Block Diagram (Copied from ADF4155 Datasheet [11]). The ADF4155 is for use with external voltage controlled oscillator (VCO) parts up to an 8 GHz operating frequency. The high resolution programmable modulus allows synthesis of exact frequencies with 0 Hz error. The VCO frequency can be divided up to 64 to allow the designer to generate RF output frequencies as low as 7.8125 MHz frequency. All the on-chip registers are through simple 3-wire interface. The device operates with power supply of 3.3 V and can be powered down when not in use. 3.7.1 Reference Input The reference input can accept both single-ended and differential signals, and the choice is controlled by the reference input mode bit (Bit DB30, Register 6). When differential signal is used as the input, this bit must be programmed high. When a single-ended signal is used as the reference, Bit DB30 in Register 6 must be programmed to 0. 3.7.2 RF N Counter The RF N counter allows a division ratio in the PLL which is determined by the INT, FRAC1, MOD1, FRAC2, and MOD2 values. These build up the divider as can be seen in Figure 18. 25 Figure 18 RF N Counter (Copied from ADF4155 Datasheet [11]). The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD) frequency [11]. The relation with N can be seen from the equation: Where: = 1+ + 1 (41) INT is the 16-bit integer value (23 to 32,767 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler). FRAC1 is the numerator of the primary modulus (1-16,777,215). FRAC2 is the numerator of the 14-bit auxiliary modulus (1-16383). MOD2 is the programmable, 14-bit auxiliary fractional modulus (2-16,383). MOD1 is a 24-bit primary modulus with a fixed value of 224 (16,777,216). If FRAC1 and FRAC2 are zero, then the synthesizer is operating in integer-N mode. Once the value of N is obtained the RFOUT can be calculated as follows [11]: = = Where × × (1 + ) × (1 + ) REFIN is the reference (TCXO) frequency. D is the REFIN doubler bit. (42) (43) 26 R is the preset divide ratio of the binary 10-bit programmable reference counter (1 to 1023). T is the REFIN divide by 2 bit (0 or 1). This results in a very fine frequency resolution with no residual frequency error. 3.7.3 Phase Frequency Detector and Charge Pump The phase frequency detector takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 19 is a simplified schematic of the Phase Frequency Detector. [3; 11.] Figure 19 Simplified PFD Schematic (Copied from ADF4155 Datasheet [11]). The PFD includes a fixed delay element that sets the width of the ant backlash pulse (ABP), which is around 2.6 ns. This pulse ensures that there is no dead zone in the PFD transfer function and provides a consistent reference spur level. 3.7.4 Output Stage For optimal spur performance, the ADF4155 datasheet, recommends the use of the VCO output and disable of the RF output -- although the choice is optional. The RF output stage is used where lower frequency operation is required by enabling one of the output dividers. The RFOUT+ and RFOUT- pins of the ADF4155 are connected to the collectors of an NPN differential pair driven by a signal from the RF divider block, as shown in Figure 20. 27 Figure 20 ADF4155 Output Stage (Copied from ADF4155 Datasheet [11]). For optimal output power the tail current of the differential pair is programmable using Bits [DB5:DB4] in Register 6 (R6). Four current levels can be set. These levels give output power levels of -4 dBm, -1 dBm, +2 dBm, and +5 dBm. The output stage uses an internal 50Ω resistor to RFVDD. An external pull-up inductor to RFVDD is necessary prior to ac coupling into 50Ω load. The output can be combined in a 1 + 1:1 transformer or an 180o microstrip coupler. Another feature of the ADF4155 is that the supply current to the RF output stage can be shut down until the device achieves lock as measured by the digital lock detect circuitry. This shutdown is enabled by using the mute till lock (MTLD) bit (DB11) in Register 6 (R6). 4 Noise Parameters In this chapter the focus is basically on one critical specification associated with the de- signed phase-locked oscillator: Phase Noise. The emphasis is placed on what causes them and how they can be minimized in a phase-locked oscillator system. The instantaneous output of an oscillator may be represented by Where ( )= {1 + ( )}sin{2 + ( )} (44) 28 Vo is the nominal amplitude of the signal f is the nominal frequency A(t) represents the amplitude noise of the signal θ(t) represents the phase noise fluctuation. 4.1 Noise in Voltage Controlled Oscillator In phase-locked oscillator, frequency stability, both short and long term, is of critical importance Long term frequency stability is concerned with how the output signal varies over a long period of time. It is usually specified as the ratio, ∆f/f for a given period of time, expressed as a percentage or in a dB. Short term stability is concerned with variations that occur over a period of seconds or less. The term phase noise is used to describe this phenomenon. These variations can be random or periodic. A spectrum analyser is used to examine the short-term stability of a signal. Figure 21 shows a typical spectrum with random and discrete frequency components causing peaks. [1.] Figure 21 Phase Noise (Reprinted from Curtin et al (1999) [1]). The first, spurious-sidebands, are a form of correlated noise as they have a clear discrete nature and are seen as discrete spikes on both sides of the center frequency. These spurious components could be caused by known clock frequencies in the signal source, power line interference, and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the result of thermal noise, shot noise and/or flicker noise in active and passive devices. [2.] 29 An ideal VCO would have no phase noise. Its output as seen on a spectrum analyzer would be a single spectral line. In practice, of course, this is not the case. There will be jitter present at the output in the time domain and a spectrum analyzer would show phase noise. Figure 22 shows phase noise in a phasor representation. Figure 22 Phasor representation of phase noise (Reprinted from Curtin et al (1999) [1]). ωo represents an output signal of angular velocity. Superimposed on this is an error sig- nal represented by ωm. To quantify this error, it is possible to take the rms value of the phase fluctuations and express them as ∆θ. This is the phase error or jitter and may be expressed in rms picosends (ps rms) or rms degrees (θ rms). In most communication systems, an overall integrated phase error specification must be met. This overall phase error is made up of the PLL phase error, the modulator phase error and the phase error due to base band components. For example, in GSM the total allowed is 5º θ rms. 4.2 Leeson’s Equation Leeson developed an equation to describe the different noise components in a VCO [2]. ≈ 10 × Where: 8 1 (45) LPM is single-sideband phase noise density (dBc/Hz) F is the device noise factor at operating power level A (linear) k is Boltzmann’s constant, 1.38 × 10 J/K 30 T is temperature (K) A is oscillator output power (W) QL is loaded Q (dimensionless) fo is the oscillator carrier frequency fm is the frequency offset from the carrier For Leeson’s equation to be valid, the following must be true: fm, the offset frequency from the carrier, is greater than the 1/f flicker frequency. the device operation is linear the noise factor at the operating power level is known Q includes the effects of component losses, device loading and buffer loading. a single resonator is used in the oscillator. In theory, the phase noise power density is made up of equal magnitudes of AM (amplitude-modulated) and PM (phase-modulated) components. This would mean that the total noise power density is twice that given above. However, in practice, PM noise dominates at frequencies close to the carrier and AM noise dominates at frequencies distant from the carrier. Figure 23 Phase noise in a VCO vs. frequency offset (Copied from Curtin et al (1999) [1]). Leeson’s equation only applies in the knee region between the break (f 1) to the transition from the “1/fᵞ” flicker noise frequency to a frequency beyond which amplified white noise dominates (f2). This is shown in Figure 23 [ᵞ=3]. f1 should be as low as possible; typically, it is less than 1 kHz, while f2 is in the region of a few MHz. High-performance oscillators require devices specially selected for low 1/f transition frequency. 31 There are many ways in general to minimize the noise in VCO some of the most common employed techniques are: 1. Use filtering on the dc voltage supply. 2. When buffering the VCO, use devices with the lowest possible noise figure. 3. Maximize average power at the tank circuit output. 4. Keep the tuning voltage of the varactor sufficiently high (typically between 3 and 3.8 V) 4.3 PLO Phase Noise Contributors Having looked at phase noise in free-running VCO and considered how it can be minimized. The focus is made on the effect of the overall components on phase noise. Figure 24 PLO phase-noise contributors (Reprinted from Curtin et al (1999) [1]). Figure 24 shows the main phase noise contributors in a PLL. The system transfer function may be described by the following equations. = = (46) 1+ × ( ) × = = (47) 1 (48) × 1+ × ( ) × × ( ) × (49) SREF is the noise that appears on the reference input to the phase detector. It is dependent on the reference divider circuitry and the spectral purity of the main reference signal. SN is the noise due to the feedback divider appearing at the frequency input to the phase detector. SCP is the noise due to the charge pump of the phase detector. And SVCO is the phase noise of the VCO as described by equations developed earlier. 32 The overall phase noise performance at the output depends on the terms described above. All the effects at the output are added in a root mean square fashion to give the total noise of the system. Hence [1.] Where: = + + (50) is the total phase noise power at the output is the noise power at the output due to SN and SREF. is the noise power at the output due to SCP. is the noise power at the output due to SVCO. The noise terms at the PD inputs, SREF and SN, will be operated on in the same fashion as SREF and will be multiplied by the closed loop gain of the system. =( )× + At low frequencies, inside the loop bandwidth, ≫ 1 and (51) 1+ =( + )× At high frequencies, outside the loop bandwidth, ≪ 1 and →0 (52) (53) The overall output noise contribution due to the phase detector noise, SCP, can be calculated by referencing SCP back to the input of the PFD. The equivalent noise at the PD input is SCP/Kd. This is then multiplied by the closed-loop gain: = × 1 × 1+ (54) Finally, the contribution of the VCO noise, SVCO, to the output phase noise is calculated in a similar manner. The forward gain this time is 1. Therefore its contribution to the output noise is: = × 1 1+ (55) G, is the forward loop gain of the closed loop response, is usually a low pass function; it is very large at low frequencies and small at high frequencies. H is a constant, 1/N. The denominator of the above expression is therefore low pass, so Svco is actually high-pass filtered by the closed loop. 33 5 Design Task The design task involves the design of the loop filter in the first part and in the later part designing a 1.45 GHz L Band signal. 5.1 Loop Filter Design This section presents the many technical issues that are involved with the loop filter design. Loop filter design usually involves choosing the proper loop filter topology, loop filter order, phase margin, loop bandwidth, and pole ratios. Once all these parts are chosen, the poles and zeros of the filter can be determined which will lead that the loop filter components to be easily calculated. This section presents the fundamental principles that are prerequisite for understanding loop filter design. [7.] 5.1.1 Loop Filter Topology and Order Figure 25 A Third Order Passive Loop Filter (Copied from Banerjee (2001) [7]). Passive loop filters, such as one shown in Figure 25, are widely employed in PLL loop filter design for simplicity and because they have less phase noise, complexity, and cost than the active loop filters. However, active filter is sometimes necessary when, for example, the maximum PLL charge pump voltage is lower than the VCO tuning voltage. If higher tuning voltages are applied to the VCO then the phase noise can be reduced. In terms of filter order, the most basic is the second order filter. Additional low pass filtering stages can be added to reduce the reference spurs. In Figure 25, R3 and C3 form an additional low pass filtering stage. 34 5.1.2 Phase Margin, Loop Bandwidth, and Pole Ratios The phase margin (θ) relates to the stability of the system. This value is typically between 40 and 55 degrees. Practically a phase margin of about 48 degrees gives the optimal lock time. Higher phase margins have the effect of decreasing the peaking response of the loop filter at the expense of degrading the lock time. [5; 7.] The loop bandwidth (ωc), on the other hand, is the most critical parameter of the loop filter. Making the loop bandwidth too small will result a design with improved reference spurs rejection and RMS phase error. The most practical method is to choose the loop bandwidth that it is sufficient to meet the lock time requirement with sufficient margin. If there is no lock time requirement, then choosing the loop bandwidth at the frequency where the PLL noise equals the VCO noise is recommended for optimal RMS phase error design. [7.] The pole ratios (T31, T41, ..) have less impact on the design than the loop bandwidth, but still are important. They tell the ration of each pole, relative to the pole T1, for example: 1 = 11 ∙ 1 3 = 31 ∙ 1 Where: 4 = 41 ∙ 1 (56) (57) (58) T1 is trivial and always equal to 1. Choosing all pole ratios to be one is theoretically the lowest reference spur solution. However, choosing them smaller can make sense when the capacitor in the loop filter next to the VCO is not at least three times the VCO input capacitance (typically 10 -100 pF). 5.1.3 Loop Filter Transfer function and Open Loop Gain The loop filter transfer function, impedance, is defined as the ratio of the output voltage at the VCO to the current injected at the PLL charge pump. The loop filter transfer function is shown below. [7.] ( )= 1+ ∙ 2 (1 ∙ ∙ + ∙ 1) ∙ (1 + ∙ 3) ∙ (1 + ∙ 4) Table 1 shows the loop transfer function the poles and for various filter orders. (59) 35 Table 1 Transfer Functions for Various Filter Orders [7] Parameter T1 2nd Order Filter 3rd Order Filter 2∙ 2∙ 1 2∙ 2∙ 1 2∙ 2 T2 T3 2∙ 2 3∙ 3 0 T4 0 0 1+ 2 Ctot 1+ 2+ 3 4th Order Filter 2∙ 2∙ 1 2∙ 2 3∙ 3 4∙ 4 1+ 2+ 3+ 4 Once the transfer function Z(s), charge pump gain (Kᶲ), and VCO gain (Kvco) are known, then the open loop gain G(s) can be obtained as follows: ( )= 5.1.4 ∙ ∙ ( ) (60) Time Constants Derivation The phase margin is specified as 180 degrees plus the open loop gain divide by N. Hence, = 180 + arctan( ∙ 2) − arctan( − arctan( ∙ 1 ∙ 41) ∙ 1) − arctan( ∙ 1 ∙ 31) (61) Since the ϕ and the pole ratios are known, this can be simplified to an expression involving T1 and T2. A second expression involving T1 and T2 can be found by setting the derivative of the phase margin equal to zero at the frequency equal to the loop bandwidth. This maximizes the phase margin at this frequency. [7.] =0= 1+ − 1+ ∙ 2 − ∙ 2 1+ ∙ 1 ∙ 41 ∙ 1 ∙ 41 ∙ 1 − ∙ 1 1+ ∙ 1 ∙ 31 ∙ 1 ∙ 31 (62) The above preceding two equations represent a system of two equations with two un- knowns (T1 and T2). The system can be solved numerically in the case of a second order filter (T3=T4=0), an elegant closed form solution exists. 36 5.1.5 Component Values Calculation from Time Constants This will be discussed in depth in the coming section about implementing the loop filter. However, one thing that arises, regardless of filter order, is the total capacitance. This is the sum of all the capacitance values in the loop filter. Considering, for instance, a delta current spike it should be natural that in the long term, the voltages across all the capac- itors should be the same and that its voltage would be the same as if all four capacitors values were added together. Ctot can be found by setting the forward loop gain G(s) equal to one at the loop bandwidth. = ∙ ∙ ∙ (1 + (1 + ∙ 1 ) ∙ (1 + ∙ 2 ) ∙ 3 ) ∙ (1 + ∙ 4 ) (63) The input capacitance of the VCO usually becomes an issue with third and higher order loop filter designs, because the capacitor shunt with the VCO should at least three times the VCO input capacitance to keep it from distorting the performance of the loop filter. The concepts and formulas presented in this section will form the basis for the implementation of the loop filter in the coming section. The second order loop filter is the case when T3=T4=0. The third order loop filter is the case when T3>0 and T4=0. These formulas could be generalised for filters higher than fourth order if required. [7.] 5.2 Loop Filter Component Values Calculation The order of the system is usually defined as one plus the number of poles in the loop filter. The reason for doing higher order filter designs is reduced spur levels. Fourth order and higher order loop filters become more practical when the spur to be filtered is at least 20 times the loop bandwidth. [5; 7.] In higher order loops, generally greater than three, finding the exact solution for time constants is generally difficult. The standard method can be used to calculate the time constants, but approximations will be introduced to solve for the component values. For the design of a fourth order loop filter it is necessary that the loop bandwidth, ωc, phase margin, ϕ, pole ratio T31, and pole ratio T41 be specified. 5.2.1 Circuit Topology A fourth order passive loop filter is shown in Figure 26. Higher order loop filters are possible by adding additional RC filters. 37 Figure 26 Fourth Order Passive Loop Filter (Reprinted from Banerjee (2001) [7]). 5.2.2 Loop Transfer Function and Time Constant Derivation The loop filter transfer function for the fourth order loop filter is given below: ( )= = Where: 1+ ∙ 2∙ 2 ∙( ∙ + ∙ + ∙ + ) 1+ ∙ 2 ∙ (1 + ∙ 1) ∙ (1 + ∙ 3) ∙ (1 + ∙ 4) ∙ = 1+ 2+ 3+ 4 (67) = 1∙ 2∙ 3∙ 4∙ 2∙ 3∙ 4 (68) = 1 ∙ 2 ∙ 2 ∙ 3 ∙ ( 3 + 4) + 4 ∙ 4 ∙ ( 2 ∙ 3 ∙ 3 + 1 ∙ 3 ∙ 3 + 1 ∙ 2 ∙ 2) = 2 ∙ 2 ∙ ( 1 + 3 + 4) + 3 ∙ ( 1 + 2) ∙ ( 3 + 4) + 4 ∙ 4 ∙ ( 1 + 2 + 3) = 2∙ 2∙ 1 (73) For the kth order loop filter, the transfer function and time constants are: Where: (1 + ∙ 2) ∙ (1 + ∙ 1) ∙ ∏ (1 + ∙ 1≈ 2∙ 2∙ = 2 = 2∙ 2 ∙ (70) (72) 4 ≈ 4∙ 4 ∙ (69) (71) 3 ≈ 3∙ 3 ( )= (65) (66) 2 = 2∙ 2 1= (64) 1 = 3,4, … ) (74) (75) (76) (77) (78) 38 The above equations are good approximations of exact values, although the time constants of the loop filter have been approximated. These approximations hold true as long as: ≪ ≪ 1 + (79) = 3,4, … (80) One possible way to ensure that the above constraints are satisfied is to choose: ≫2∙ The time constant can be calculated assuming the phase margin is given by: = 180 + arctan( ∙ 2) − arctan( ∙ 1) − arctan( From the Taylor series analysis, for small value of x it can be shown: tan( ) ≈ arctan( ) ≈ ∙ ) (81) (82) (83) (84) Applying the tangent function and the two previous identities yields the following simplification: 1+ ≈ sec( ) − tan( ) (85) As a design constraint itself the phase margin is maximized at the loop bandwidth. Making the derivative of the phase margin equal to zero yields: 1+ 2 = ∙ 2 1+ 1 ∙ 1 + 1+ ∙ (86) Cross multiplying both sides and applying some approximations yields: 2≈ ∙ 2 ∙ 1+ (87) This simplification can be justified as long as: 2≫ 1+ (88) Rearranging the equations yields the following: 2≈ 1 ∙( 1+∑ (89) 39 sec( ) − tan( ) 1+ (90) In the case of fourth order loop filter and to satisfy the T i≥ 2*Ti+1, the time constants can be obtained: 4 sec( ) − tan( ) ∙ 7 2 sec( ) − tan( ) = 3= ∙ 7 1 sec( ) − tan( ) = 4= ∙ 7 (91) 1= 5.2.3 (92) (93) Calculating Component Values from the Time Constants Once the time constants are known, the other components can be calculated = ∙ ∙ ∙ 1+ ∙ 1 )∙∏ (1 + 1= ∙ 1 5 3 4= 5 3= = 5 = 4,5,6. . ( 2= = 4,5,6. . ( 1+ (94) ∙ (95) (96) (97) ℎ − 1− 3− 4− 2 2 3 3= 3 4 4= 4 2= = 1 2 ∙ 2 ℎ ) (98) (99) , , ,.. (100) (101) (102) ) (103) The components can be more precisely calculated by writing explicitly the impedance for the components R3, R4, C3, and C4 and solving for the time constants T3 and T4 more exactly. This approximation is similar to putting an operational amplifier before R3, ex- cept for the time constant T1 still takes into account the loading from the rest of the components of the loop filter. 40 The components C1, C2, C3 and R2 are calculated as normal, however, the components R3, R4 and C4 are found more exactly by equating the poles to the expressing for the loop filter impedance. The voltage transfer function from the beginning of resistor R3 to the input of the voltage controlled oscillator (VCO) is: 1 1 + ∙ ( 3 ∙ 3 + 4 ∙ 4 + 3 ∙ 4) + ∙ 3∙ 4∙ 3∙ 4 1 = (1 + ∙ 3) ∙ (1 + ∙ 4) (104) Processing this arithmetic gives the values for R3 and R4. 3, 4 = 3 + 4 ∓ ( 3 + 4) − 4 ∙ 3 ∙ 4 ∙ 1 + 2 ∙ ( 3 + 4) (105) For real component values, the quantity under the square root sign must be non-negative. Applying this restriction yields: 4 ( 3 − 4) ≤ 3 4∙ 3∙ 4 (106) As a rule of thumb, it is desirable to have C4 as large as possible, so this quantity should be made equal. T3 should be larger than T4, that is T31 > T41, so that the capacitor C3 is not zero and it is at least three times larger as the input capacitor of the voltage controlled oscillator (VCO). Taking account into this gives us: ( 3 − 4) 4∙ 3∙ 4 3+ 4 3= 4= 2 ∙ ( 3 + 4) 4= 3∙ (107) (108) Using the equations derived above now it is very trivial to design a simple passive loop filter. This is accomplished by knowing the KVCO, K , FOUT, FCOMP, and FC. The loop filter designed here has the following values that can be used to calculate the values of loop components. = 85 = 0.9 = 900 = 61.44 = 80 Applying the above equations and the values given. The component values for specific frequency and phase detector values can be calculated. In this case, using MathCAD software, the obtained values of the loop components are: 41 Table 2 Loop Filter Component Values Loop Component Value C1 3.128 nF C2 55.192 nF R2 99.035 Ω C3 0.626 nF R3 308.689 Ω C4 78.19 pF R4 308.689 Ω The MathCAD code used in the calculation is shown in Appendix 1. The final loop filter topology is shown in Figure 27. Figure 27 Fourth Order Loop Filter with 80 kHz Loop Bandwidth 5.3 1.45 GHz L-Band signal generation The phase-locked oscillator discussed can be used to generate a wide range of frequency signals. To showcase this process an L-Band signal of 1.45 GHz frequency is generated and measurement of phase noise is done in the following chapter. The output frequency of the synthesizer can be calculated as follows [11]: = where: + 1+ 1 RFout is the RF frequency output. INT is the integer division factor. × (109) 42 FRAC1 is the 24-bit main fractional value. FRAC2 is the 14-bit auxiliary fractional value. MOD2 is the 14-bit auxiliary modulus value. MOD1 is the 24-bit fixed modulus value. RF Divider is the output divider that divides down the VCO frequency. = where: × (1 + ) ( × (1 + ) (110) REFIN is the reference frequency input. D is the reference doubler. R is the reference division factor. T is the reference divide by 2 bit (0 or 1). Assuming a channel spacing of 15 kHz. This value and the phase frequency detector frequency value specify the MOD2 value. Table 3 1.45 GHz RF Frequency Synthesis Parameters N fPFD RFdivider RFOUT INT FRAC1 94 REFIN 10824362 D 122.88 FRAC2 683 0 Mhz N 94.645 MOD1 R 224 2 4 MOD2 1024 T 0 fPFD 61.44 MHz The equations used to obtain the values shown in Table 3 are presented in Appendix 2. 5.4 System Simulation The simulation of the system is done using ADIsimPLL. This software makes it easy to design, analyse and simulate the Phase Locked Loop frequency synthesizers using the ADF range of PLL integrated circuits from Analog Devices. The performance including phase noise, transient response, and lock time to frequency, and phase tolerance is analysed. 43 The ADIsimPLL is configured to simulate the noise contributions from each component in the loop except the reference crystal. The frequency simulated is in the range of 1.452 – 1.492 GHz. This covers the amateur communication band for Region 1. 5.4.1 Frequency Domain In the frequency domain the open loop gain and the closed loop gain response of the 80 60 40 20 0 -20 -40 -60 -80 -100 -120 Open Loop Gain at 1.47GHz Amplitude Phase 0 -20 -40 -60 Phase (deg) Gain (dB) system are presented. -80 -100 -120 -140 1k 10k -160 -180 1M 10M Frequency (Hz) 100k Figure 28 Open Loop Gain at 1.47 GHz Simulated with ADIsimPLL, Figure 28, also called Phase Margin plot, is useful for analyzing the stability of the system. If the | ( )| = 0 when ∡ ( ) = −180 this equals ( ) = −1 which makes the loop, or system in general, unstable. The Phase Margin tells how far the de- 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 Closed Loop Gain at 1.47GHz Amplitude Phase 0 -20 -40 -60 Phase (deg) Gain (dB) sign is from the instability, usually around 45o. -80 -100 -120 -140 1k 10k 100k -160 -180 1M 10M Frequency (Hz) Figure 29 Closed Loop Gain at 1.47 GHz simulated with ADIsimPLL 44 The Closed Loop Gain in Figure 29 above has a low pass nature. It shows how the noise from the reference or the phase detector is handled by the loop. The noise of the refer- ence oscillator is multiplied by N2 within the loop bandwidth and shaped by the closed loop response of the Phase Locked Loop (PLL). At the frequency domain the phase noise contribution of each component is simulated and the overall phase noise of the system. RFout - Phase Noise at 1.47GHz -60 Total Loop Filter SDM Chip Ref VCO Phase Noise (dBc/Hz) -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 1k 10k 100k 1M 10M Frequency (Hz) Figure 30 Phase Noise Characteristics of the System simulated with ADIsimPLL Although the phase noise can be guessed from the graph shown in Figure 30 the ADIsimPLL software can be configured to generate a table at specific offset frequencies. Table 4 Phase Noise Simulation at 10k, 100k, and 1.0M offset frequency Offset Frequency Phase Noise (dBc/Hz) 100k -109.1 10.0k 1.00M 5.4.2 -110.6 -139.9 Time Domain Two important parameters are the frequency settling time and output phase error. Both are useful in the simulation phase because the system can be optimized accordingly to meet the requirements of certain standards. Frequency (GHz) 45 1.500 1.495 1.490 1.485 1.480 1.475 1.470 1.465 1.460 1.455 1.450 Frequency 0 10 20 30 40 50 60 70 80 90 100 110 Time (us) Figure 31 Frequency settling time of the system simulated with ADIsimPLL Figure 31 shows the VCO frequency for the default frequency transient from 1.455 GHz to 1.495 GHz. Tuning the Loop Bandwidth in ADIsimPLL it possible to simulate its effect on the system by analyzing the graph. In other words, the wider the loop bandwidth the faster the settling time. Most of the time the optimum phase margin from settling time point of view is about 45-50 degrees that will result in an overshoot of step response of about 30-35%. Making the phase margin smaller results slowing the settling time con- Phase Error (deg) siderably. 50 40 30 20 10 0 -10 -20 -30 -40 -50 Output Phase Error 0 10 20 30 40 50 60 70 80 90 100 110 Time (us) Figure 32 Output Phase Error of the system simulated with ADIsimPLL From Figure 32 it can be deduced that the phase gets to within 10 degrees of the final value within 65.3 µs. 6 6.1 Measurement Phase Noise Measurements The phase noise of an oscillator is a measure of the oscillator’s short-term stability and hence an essential quality criterion when designing a phase locked oscillator. Special 46 phase noise measurement equipment such as Signal Source Analyser or Spectrum an- alyser when the requirements on the dynamic range are not stringent.is used for doing the measurement.[14.] Phase noise measurement with a spectrum analyser is referred to as a direct measure- ment. The Device under Test (DUT) must have a small frequency drift relative to the sweep time of the spectrum analyser or the measurable frequency variation of the oscillator would be too large and invalidate the measurement results. This case does not apply to the design task of the thesis since the frequency is phase-locked which prevents frequency drifting at all most of the time. But when free running voltage controlled oscil- lator (VCO) phase noise is measured it is better to employ another technique of measurement. 6.1.1 Measurement procedure For phase-locked oscillators the Single Sideband (SSB) phase noise at certain offset frequency relative to the carrier level within 1 Hz bandwidth is usually of interest. The unit is dBc(1 Hz). Figure 33 Single Sideband phase noise (Reprinted from Curtin et al (1999) [1]). Phase noise measurement with spectrum analyzer involves two steps: Measurement of carrier level LC. Measurement of phase noise level LPN at carrier offset foff. For evaluating the phase noise measured at a carrier offset foff and resolution band- width B is first referenced to a 1 Hz bandwidth. The following equation relates the two when a spectrum analyzer utilizing a RMS detector is used [14]: Where , ( )= , ( ) − 10 × 1 (111) 47 phase noise level at carrier offset foff and noise bandwidth B , relative to 1 dB and 1 Hz bandwidth. , B phase noise level measured at carrier offset foff and noise bandwidth B relative to 1 dB. noise bandwidth of resolution filter. The phase noise level within 1 Hz bandwidth must now be referenced to the carrier level: ( )= Where ( )− , ( ) (112) relative phase noise level within 1 Hz bandwidth at carrier offset foff relative to carrier power , . phase noise level at carrier offset foff and noise bandwidth B relative to 1 dB and 1 Hz bandwidth. carrier level relative to 1 dB. For noise measurement with modern Spectrum Analysers and/or Signal Analysers that have noise marker functionality which takes into account all the calculations and displays the noise level at the marker point at offset frequency. During the measurement this feature will be utilized. 6.1.2 Measurement Setup The phase noise measurement is done using Rohde & Schwarz Signal Analyser FSIQ3. Phase noise measurement is made using the phase noise soft-key at specific offset frequency of interest. Figure 34 PLO Measurement Setup with Rohde&Schwarz FSIQ3 Signal Analyzer (Modified from Curtin et al (1999) [1]). 48 6.1.3 Measured Phase Noise Values The measurement is done as shown in Figure 34. The measured values are compared with the values obtained from the ADIsimPLL simulation and presented in Table 4. Table 5 Phase Noise Measurement at 10 kHz, 100 kHz, and 10 MHz offset frequency Offset Frequency Phase Noise (dBc/Hz) 100k -92.62 10.0k 1.00M -90.30 -94.12 The spectrum analyser images and ADF4155 connection is shown in Appendix 3. Figure 35 Simulated vs Measured Phase Noise at 1.405 GHz at 10kHz, 100kHz, and 1 MHz offset from carrier. 7 Discussion The goal of this thesis was to design and investigate the feasibility of frequency synthesis system to be used in conjunction with the Radio Electronics course. The design of the loop filter was simulated but not implemented because the ADF4155 Evaluation Board comes with all the required components to implement a frequency synthesis system. The system generates the programmed frequencies effectively with required power level which is also programmable. The measurement results obtained in Section 6.1.3 are not exactly as the designed values. This is because there are many challenges involved when precise phase noise measurements are required. The method used for measuring 49 the noise values is the Direct Method which is the easiest method since the only thing required is spectrum or signal analyser equipment and hence results in poorer phase noise measurement. Another thing that may be the reason for the discrepancy between the simulated and measured phase noise is the simulated Voltage Controlled Oscillator (VCO) phase noise. The ADIsimPLL does not support the ZComm VCO used hence the phase noise parameters were approximated. Although the reference oscillator is stable the phase noise was also not simulated therefore that may contributing to the discrepancy between measured and the simulated values. The power source for the board was taken from the Lab supply bench which may contribute also to the overall noise of the system. Moreover, to ensure good performance the input signal levels to the Signal Analyser mixers need to be controlled carefully to avoid intermodulation products. This limits the wide band signal to noise ratio of the Sig- nal Analyser which eventually will limit phase noise measurements that can be performed far from the carrier. The filters also sometimes limit the capability of the measurement. The system measurement may be improved by using other measurement techniques such as the Delay Line Discriminators, Quadrature Technique, and Digital Direct Measurement. All these measurements are more accurate than the Direct Method used in the measurement phase. 50 8 Conclusion In this thesis the phase locked oscillator was analysed, designed, and measured by utilising the ADF4155 Evaluation board. The loop filter design was emphasised during the design phase and was analysed mathematically. A fourth order loop filter was designed and analysed with MathCAD software. For generating the desired signal the Fractional-N Phase Locked Loop technique was employed which offers the generation of various frequencies than the Integer-N method by using delta-sigma modulators to control the division of the feedback signal. Phase noise measurement was made at the end and the values obtained were compared with the simulated values. The results were very close, in terms of frequency, to the simulated values. A 1.45 GHz L Band signal was designed and measured as part of the thesis work. The goal of the thesis work, which was to design a tunable phase locked oscillator was successfully achieved, and the phase locked oscillator can be used when a high spectral purity signal is required. 51 References 1. Curtin O. Phase-locked loops for high frequency receivers and transmitters: Analog Dialogue; 1999. 2. Fox A. Ask the Applications Engineer-30 PLL Synthesizers: Analog Dialogue; 2003. 3. Abramovitch D. Phase-locked loops: a control centric tutorial. American Control Conference, 2002. 4. Karhu M. An investigation of synthesizer architectures for future US-TDMA handset terminals. University of Oulu; 2001. 5. Gardner F. Phaselock techniques. Hoboken, N.J: Wiley; 2005. 6. Barrett C. Fractional/Integer-N PLL [online]. National Instruments. URL:http://www.ti.com/lit/an/swra029/swra029.pdf. Accessed 10 October 2015. 7. Banerjee D. PLL Performance, Simulation, and Design. 2nd ed. Dog Ear Publishing; 2001. 8. Skyworks. Theory and Application of Sampling Phase Detector [online]. Skyworks Solutions Inc. URL: https://www.digikey.com/Web%20Export/Sup- plier%20Content/SkyworksSolutions_863/PDF/Skyworks_AN_200328B.pdf. Accessed 15 October 2015. 9. Chenakin A. Building a Microwave Frequency Synthesizer. High Frequency Electronics. 2008. 10. Arrifin S A Design Method for the Fastest Settling Type 2 Phase Lock Loop [online]. High Frequency Electronics. URL: http://www.highfrequencyelectronics.com/Jun10/HFE0610_Salleh_part1.pdf. Accessed 20 September 2015. 11. Analog Devices. Integer-N/Fractional-N PLL Synthesizer [online]. Analog Devices; 2014. URL: http://www.analog.com/media/en/technical-documentation/data-sheets/ADF4155.pdf. Accessed 25 September 2015. 12. Mini-Circuits. Optimizing VCO/PLL Evaluations & PLL Synthesizer Designs [online]. Mini-Circuits;. URL: http://194.75.38.69/pages/pdfs/an95006.pdf. Accessed 28 September 2015. 52 13. Owen D Good Practice Guide to Phase Noise Measurement [online]. Measurement Good Practice Guides. URL:http://jmfriedt.sequanux.org/phase_digital/mgpg68.pdf. Accessed 5 October 2015. 14. Rauscher C. Fundamentals of Spectrum Analysis. Rohde&Schwarz; 2008. Appendix 1 1 (2) MathCAD Code for Loop Filter Calculation Kvco 85 MHz volt K 0.9mA Fout 900MHz Fcomp 61.44MHz Fc 80kHz 50deg T31 1.0 T41 0.5 Calculation N1 Fout Fcomp c 2 Fc Calculate Pole and Zero 1 tan ( ) cos ( ) 1 T1 c 1 T31 T41 T3 T1 T31 T4 T41 T1 T2 1 c ( T1 T3 T4) 2 7 T1 2.896 10 s T2 5.466 10 s T3 2.896 10 s T4 1.448 10 s 6 7 7 Calculate component values from time constants 2 2 1 c T2 Ctot 2 2 2 2 2 2 2 c N1 1 c T1 1 c T3 1 c T4 K Kvco C1 Ctot T1 T2 1 2 Appendix 1 2 (2) C3 C1 5 C4 C3 ( T3 T4) 4 T3 T4 2 C2 Ctot C1 C3 C4 R2 R3 R4 T2 C2 T4 T3 2 ( C3 C4) T4 T3 2 ( C3 C4) Calculated Values: C1 3.128 nF C2 55.192 nF C3 0.626nF R2 99.035 R3 308.689 R4 308.689 C4 78.19 pF Simulation Define loop parameters A1 R2 R3 R4 C1 C2 C3 C4 B1 C1 C2 R2 R3 ( C3 C4) R4 C4 ( C2 C3 R3 C1 C3 R3 C1 C2 R2) Ck R2 C2 ( C1 C3 C4) R3 ( C1 C2) ( C3 C4) R4 C4 ( C1 C2 C3) D C1 C2 C3 C4 Z( s ) G( ) 1 s T2 s Ctot ( 1 s T1) ( 1 s T3) ( 1 s T4) K Kvco Z( i) 10kHz i c1 root ( G( ) N1 ) c1 2 80 kHz 1 arg( G( c ) ) 1 49.27 180 180 Appendix 2 1 (1) ADF4155 Synthesizer Values Calculation = × = = = 1=2 = = ×( − × 2= 2= ( − (1 + ) × (1 + ) 1+ + ( )×2 ) , − 1 ) 1 × 2 Appendix 3 1 (3) ADF4155 Evaluation Board and Spectrum Analyser Output Figure 36 ADF4155 Evaluation Board Appendix 3 2 (3) Figure 37 Phase Noise measured at 10 kHz offset displaying a value of -90.30 dBc/Hz Figure 38 Phase Noise measured at 100 kHz offset displaying a value of -92.62 dBc/Hz Appendix 3 3 (3) Figure 39 Phase Noise measured at 1 MHz offset displaying a value of -94.12 dBc/Hz

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