Stratix V External Memory Interfaces Pin Planning February 28, 2012 Public

Stratix V External Memory Interfaces Pin Planning February 28, 2012 Public

Stratix V External Memory

Interfaces Pin Planning

February 28, 2012

© 2011 Altera Corporation

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Disclaimer

All pictures and examples in this presentation are for illustration purpose only! The actual number and location of resources should be extracted from the Altera official documentation for the specific Device being used

Timing characteristics are preliminary and pending silicon characterization of production devices

This presentation does not fully describe PLL, DLL, or I/Os functionalities

This presentation specifically focuses on Stratix V External

Memory Interface (EMIF) hardware as it pertains to pin planning

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Agenda

EMIF dedicated hardware

Resource sharing hardware

Dedicated hardware limitations

Guideline tables

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Why Guidelines?

Pin Placement for EMIF is limited by the availability of dedicated hardware on the periphery

Some guidelines are mandatory and cannot be violated as they would result in a no-fit error

These guidelines use the word ―

MUST

Some guidelines are not mandatory but strongly recommended and disregarding them might result in timing violations

These guidelines use the term ―

Strong SHOULD

Some guidelines are recommendations and if violated the implementation is legal but timing will be degraded

These guidelines use the word ―

SHOULD

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EMIF Dedicated Hardware

When planning for EMIF pin placement in Stratix V, the following hardware resources must be kept into account

I/O pins

I/O sub-banks

DQS logic and groups

Leveling blocks

Core clocks

Interface type, width, and placement dependent

PHY Clock Tree

PLL

DLL

OCT calibration block

Independent of interface type

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Hardware Resource Sharing

The following resources can be shared only across multiple compatible Interfaces

I/O sub-banks and leveling blocks

OCT calibration block

PLL

DLL

PHY clock tree

Core clocks

User must explicitly set the interfaces to master and slave modes in the IP.

Compatible interfaces for PLL/DLL sharing

Same type

 e.g. DDR2, QDRII, etc...

Same internal clock rate

 e.g. Full Rate, Half Rate, etc...

Same interface clock rate

 e.g. 533 MHz

Same PLL input clock rate

 e.g. 100 MHz reference clock

Same phase requirements

 e.g. Additional core-to-periphery clock phase: 45°

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I/O Sub-Bank and Leveling Blocks

I/O sub-banks and leveling blocks limitations

Each sub-bank contains

One leveling block e.g. sub-banks 8A, 8B, and 8C each has 1 leveling block

I/O pins organized into DQS groups

Each leveling block

Generates delayed (PVT compensated) versions of the source clock (e.g. 0°,

45°, 90°)

Distributes output clocks to I/Os in the whole Sub-Bank

Can be connected to only one of the PHY clock trees (center, left, or right) available

DLL

PLL

*

Stratix V UniPHY uses the PHY clock tree.

There’s no option to use core clock

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PLL & PHY Clock Tree

PLL and PHY clock tree limitations

Each PLL can drive only one PHY clock tree

Each PHY clock tree can reach one device edge

Each leveling block in a sub-bank can only access on PHY clock tree

Figure below illustrates the top and bottom edges of 5SGXAx and 5SGSDx devices

Each side contains three PLL’s only connect to one PHY clock tree

PLL Sub-Bank

Sub-Bank Sub-Bank

Sub-Bank PLL

Center

PLL

Center PHY clock tree

Left PHY clock tree

Right PHY clock tree

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DLL

DLL limitations

Stratix V has 4 DLLs

DLLs are available in the corners of a device

Each DLL can serve the 2 adjacent sides

Maximum number of incompatible interfaces on each side of a device is

2

DLL can be shared without sharing PLLs

DLL is clocked by PLL hence their frequencies must be the same

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OCT Calibration Block

Stratix V has 4 OCT calibration blocks in the corners of a device

Each calibration block can connect to any sub-bank on any side of the device

Each sub-bank can connect to only one OCT calibration block

OCT calibration blocks can be shared by multiple interfaces provided that they have the same

Series/Parallel Termination

Sub-bank voltage

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MUST NOT

split interfaces between top and bottom sides

MUST NOT

place pins from separate interfaces in the same I/O sub-banks

unless sharing resources

MUST -> Strong Should

(1)

place all CK,

CK#, address, control, and command pins of an interface in the same I/O sub-bank

this guideline is not enforced in QII

Strong SHOULD

(1)

place all CK, CK#, address, control, and command pins of an interface in the same I/O sub-bank

this

guideline is not enforced in QII

SHOULD

(1)

place all CK, CK#, address, control, and command pins of an interface in the same I/O sub-bank

this guideline

is not enforced in QII

Any

Any

> 800 MHz

800 MHz

< 800 MHz

All

All

All

All

All

(1) DDR3 RESET pin may be placed in a separate sub bank.

Due to PLL/DLL limitations

All pins require access to the same leveling block

For optimum timing, clock and data output paths should share as much hardware as possible. e.g. for write data pins the best timing is achieved through DQS Groups.

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MUST

avoid using I/Os at the device corners (i.e. subbank ―A‖)

Strong SHOULD

avoid using I/Os at the device corners (i.e. subbank ―A‖)

SHOULD

avoid using I/Os at the device corners (i.e. subbank ―A‖)

> 800 MHz

800 MHz

< 800 MHz

SHOULD

place the data strobe pins such that all data groups of the same interface are next to each other

do not span

across the center PLL

SHOULD

place CK, CK#, address, control, and command pins in the same quadrant as data groups for improved timing in general

SHOULD

place the data strobe pins such that all data groups of the same interface are next to each other

do not span

across the center PLL

Any

Any

Any

A7

A7

A7

All

All

All

Due to extra delay to reach the subbanks in the corners

To ease core timing closure; if pins are too far apart then core logic is placed apart which results in difficult timing closure

To ease core timing closure; if pins are too far apart then core logic is placed apart which results in difficult timing closure

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MUST NOT

share the same PLL input reference clock

unless the interfaces share PLL/DLL resources

Any All

Strong SHOULD

use center PLL

ensure that the PLL input reference clock pin is placed at a location that can drive the center PLL

Strong SHOULD

place pins in the same quadrant as the PLL

if center PLL is not accessible

SHOULD

use the center PLL for a wide interface that must straddle across center

PLL

SHOULD

avoid straddling an interface across the center PLL

>= 800 MHz All

>= 800 MHZ All

>= 800 MHz All

Any All

Because sharing the same PLL input reference clock forces the same PLL to be used. Each PLL can drive only one PHY clock tree and interfaces not sharing a PLL can’t share one PHY clock tree.

Using a non-center PLL hence a noncenter PHY clock tree to drive a subbank in the opposite quadrant is not recommended due to long PHY clock tree delay

Straddling PLL results in timing degradation because it increases the length of the PHY clock tree hence generates higher jitter

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