Aiwa XD-DV290K Service manual

XD-DV290

K(B),EZ(B)

SERVICE MANUAL

BASIC DVD MECHANISM : LDM-H109

(6721R-0300A)

DVD PLAYER

This Service Manual is the “Revision Publishing” and replaces “Simple Manual”

K<B>:(S/M Code No.09-99C-337-5T2)

EZ<B>:(S/M Code No.09-99C-337-5T3).

S/M Code No. 09-99C-337-5R2

TABLE OF CONTENTS

SPECIFICATIONS .................................................................................................................................. 3

ACCESSORIES/PACKAGE LIST ........................................................................................................... 3

PROTECTION OF EYES FROM LASER BEAM DURING SERVICING/

Precaution to replace Optical block ......................................................................................................... 4

DISASSEMBLY INSTRUCTIONS ...................................................................................................... 5-10

ELECTRICAL MAIN PARTS LIST ........................................................................................................ 11

TRANSISTOR ILLUSTRATION ............................................................................................................ 12

BLOCK DIAGRAM-1 (OVERALL) ......................................................................................................... 13

BLOCK DIAGRAM-2 (POWER) ............................................................................................................ 14

BLOCK DIAGRAM-3 (RF/DSP/SERVO) ............................................................................................... 15

BLOCK DIAGRAM-4 (AUDIO) .............................................................................................................. 16

BLOCK DIAGRAM-5 (MPEG) ............................................................................................................... 17

BLOCK DIAGRAM-6 (SYSTEM CONTROL) ........................................................................................ 18

WIRING-1 (MAIN: COMPONENT SIDE) ........................................................................................ 19, 20

WIRING-2 (MAIN: CONDUCTOR SIDE) ........................................................................................ 21, 22

SCHEMATIC DIAGRAM-1 (MAIN 1/5) ............................................................................................ 23, 24





SCHEMATIC DIAGRAM-6 (JACK) ................................................................................................. 33, 34

WIRING-3 (JUNCTION/JACK) ........................................................................................................ 35, 36

SCHEMATIC DIAGRAM-7 (JUNCTION) ........................................................................................ 37, 38

WIRING-4 (TIMER/KEY/POWER) .................................................................................................. 39, 40

SCHEMATIC DIAGRAM-8 (TIMER/KEY) ....................................................................................... 41, 42

SCHEMATIC DIAGRAM-9 (POWER) ............................................................................................. 43, 44

WAVE FORM ................................................................................................................................... 45-47

TROUBLE-SHOOTING .................................................................................................................... 48-57

LCD DISPLAY ....................................................................................................................................... 58

IC DESCRIPTION ............................................................................................................................ 59-77

IC BLOCK DIAGRAM ....................................................................................................................... 78-80

MECHANICAL EXPLODED VIEW 1/1 .................................................................................................. 81

MECHANICAL PARTS LIST 1/1 ........................................................................................................... 82

MECHANISM EXPLODED VIEW 1/1 ............................................................................................. 83, 84

MECHANISM PARTS LIST 1/1 ............................................................................................................. 85

2

DVD VIDEO PLAYER

Power supply

Power consumption

Mass

External dimensions

Signal system

Laser

Frequency range (digital audio)

Signal-to-noise ratio (digital audio)

Audio dynamic range (digital audio)

Harmonic distortion(digital audio)

Wow and flutter

Operating conditions

OUTPUTS

Video outputs

S video outputs

Component video output

Audio output (digital audio)

Audio output (optical audio)

Audio output (analog audio)

SPECIFICATIONS

100V~240V, 50Hz

20 W

3.5kg(7.7lbs)

430 * 91 * 293 (W * H * D)

NTSC

SSemiconductor laser, wavelength 655nm (DVD) /795nm (CD)

2Hz to 44kHz

More than 105dB (EIAJ)

More than 95dB (EIAJ)

0.003%

Below measurable level (less than +0.001% (W.PEAK) (EIAJ)

Temperature : 5˚C(41˚F) to 35˚C(95˚F),

Operation status : Horizontal

1.0V (p-p), 75

Ω

, negative sync., RCA jack x 1

(Y) 1.0V (p-p), 75

Ω

, negative sync., Mini DIN 4-pin

(C) 0.286V (p-p), 75

Ω

(Y) 1.0V (p-p), 75

Ω

,negative sync., RCA jack * 1

(Pb)/(Pr) 0.7V (p-p), 75

Ω

0.5V(p-p), 75

Ω

, RCA jack * 1

* 1

Optical connector * 1

2.0Vrms (1kHz, 0dB), 330

Ω

, RCA jack (L, R) * 2

•

Design and specifications are subject to change without notice

.

•

Weight and dimensions shown are approximate.

ACCESSORIES/PACKAGE LIST

REF. NO PART NO.

KANRI

NO.

DESCRIPTION

1 S8-35R-S00-09G INSTRUCTION ASSY

2 S8-615-20G-000 DVD-2520N CABLE ASSY

3 S7-11R-2N0-13A REMOTE CONTROLLER A

4 S5-640-17B-000 PLUG ASSY PHONE CORD 1WAY

5 S5-640-18B-000 PLUG ASSY PHONO CORD

3

PROTECTION OF EYES FROM LASER BEAM DURING SERVICING

This set employs laser. Therefore, be sure to follow carefully the instructions below when servicing.

CAUTION

Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

WARNING!

WHEN SERVICING, DO NOT APPROACH THE LASER EXIT

WITH THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO

CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE

FROM A DISTANCE OF MORE THAN 30cm FROM THE

SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL

PICK-UP BLOCK.

ATTENTION

L'utilisation de commandes, réglages ou procédures autres que ceux spécifiés peut entraîner une dangereuse exposition aux radiations.

Caution: Invisible laser radiation when open and interlocks defeated avoid exposure to beam.

Advarsel:Usynling laserståling ved åbning, når sikkerhedsafbrydere er ude af funktion.

Undgå udsættelse for stråling.

ADVARSEL!

Usynlig laserståling ved åbning, når sikkerhedsafbrydereer ude af funktion. Undgå udsættelse for stråling.

This Compact Disc player is classified as a CLASS 1 LASER product.

The CLASS 1 LASER PRODUCT label is located on the rear exterior.

VAROITUS!

Laiteen Käyttäminen muulla kuin tässä käyttöohjeessa mainitulla tavalla saattaa altistaa käyt-täjän turvallisuusluokan 1 ylittävälle näkymättömälle lasersäteilylle.

CLASS 1

KLASSE 1

LUOKAN 1

KLASS 1

LASER PRODUCT

LASER PRODUKT

LASER LAITE

LASER APPARAT

VARNING!

Om apparaten används på annat sätt än vad som specificeras i denna bruksanvising, kan användaren utsättas för osynling laserstrålning, som överskrider gränsen för laserklass 1.

Precaution to replace Optical block

(LPC-512A)

Body or clothes electrostatic potential could ruin laser diode in the optical block. Be sure ground body and workbench, and use care the clothes do not touch the diode.

1) After the connection, remove solder shown in the right figure.

Solder

4

DISASSEMBLY INSTRUCTIONS

CAUTION BEFORE STARTING SERVICING

Electronic parts are susceptible to static electricity and may easily damaged, so do not forget to take a proper grounding treatment as required.

Many screws are used inside the unit. To prevent missing, dropping, etc. of the screws, always use a magnetized screw driver in servicing. Several kinds of screws are used and some of them need special cautions. That is, take care of the tapping screws securing molded parts and fine pitch screws used to secure metal parts. If they are used improperly, the screw holes will be easily damaged and the parts can not be fixed.

CABINET DISASSEMBLY

1. Top Case

1) Release 7 screws (A). (See Fig-1)

2) Lift the top case with holding the back of it, and remove it in the direction of the arrow.

Top Case

(A)

(A)

(A)

(A)

(A)

(A)

(A)

3. Front Panel

1) Eject the disc tray. (See Fig-2)

2) Remove the tray door. (See Fig-2)

3) Release 2 screws (B).

4) Pull the front panel toward you while pressing 7 stoppers to disengage, and remove the front panel. (See

Fig-3)

(B)

Stopper

Front Panel

(B)

Stopper

Fig-1

2. Tray Door

1) Eject the disc tray.

2) Lift up the tray door in the direction of the arrow.

Tray Door

Fig-3

Fig-2

Disc Tray

5

CIRCUIT BOARD DISASSEMBLY

Note: Before removing the main circuit board, be sure to shortcircuit the laserdiode output land.

After replacing the main circuit board, open the land after inserting the flexible connector.

(Refer to Mechanism Disassembly)

4. Main/JACK C.B

1) Remove the top case. (See Fig-1)

2) Release 10 screws (C), and take out the main/JACK

C.B. (See Fig-4)

3) Remove the flexible connectors and the connector from main circuit board.

4) Then, remove the main JACK C.B.

(C)

JACK C.B

(C)

(C)

Main C.B

(C)

Flexible connector

(C)

Flexible connector

(C)

(C) (C)

(C)

6. TIMER and Key C.B

1) Remove the front panel. (See Fig-3)

2) Release 5 screws (E), and remove the TIMER C.B.

Key C.B

(E)

(E)

(E)

(E)

(E)

TIMER C.B

Fig-6

Fig-4

5. Power C.B

1) Release 4 screws (D). (See Fig-5)

Power Code

(D)

(D)

(D)

(D)

Power C.B

Fig-5

6

DECK MECHANISM PARTS LOCATION

• Bottom View

• Top View

Procedure

Starting No.

Parts Fixing Type

5

5, 6

2

2, 8

2, 8

2, 8

2, 8, 11

2, 8, 11

2, 8, 12, 13

2, 8, 12-14

2, 8, 12-14

2, 8, 12-16

2, 8, 9

2, 8, 9

2, 8, 9

2, 8, 9-20

1, 2, 8, 9

1, 2, 8, 9

2, 8, 9

2, 8, 9

20

21

22

23

24

25

2, 8

2, 8, 26

2, 8, 26, 27

2, 8, 26-28

2, 8, 26-29

26

27

28

29

30

1, 2, 8, 26-30 31

1, 2, 8, 26-31 32

15

16

17

18

19

1

10

11

12

13

14

8

9

4

5

2

3

6

7

Junction P.C.Board

Bracket Assembly Clamp

Bracket Clamp

Clamp Assembly Disk

Plate Clamp

Magnet Clamp

Clamp Lower

Tray Disk

Base Assembly Feed

Rubber R

Spring Skew

Shaft PU Main

4 Screws,

4 Locking Tabs

2 Screws

1 Locking Tab

1 Connector

1 Screw

1 Hook

Shaft PU Sub

Mechanism Assembly

PU Unit

Guide Freed PU

Spring Guide Feed

Pick up Assembly General

1Screw

Motor (Mech.)

Shaft Lead Screw

3Screws

Motor Assembly PU Freed 2 Locking Tabs

Base PU (Outsert)

Base Assembly Main

Holder Assembly Deck on 1 Locking Tab

2 Locking Tabs Frame Assembly Up/Down

Rubber F

Belt Loading

GearPulley

Gear Loading

Gear Emergency

1 Screw

Cam Loading

Motor Assembly Loading

Base Main

2 Screws

1 Locking Tab

Disassembly Figure

Bottom

Bottom

Bottom

Bottom

Bottom

4-1

4-3

4-4

4-4

4-4

4-4

4-4

4-4

4-2

4-2

4-2

4-2

4-2

4-2

4-5

4-5

4-5

4-5

4-5

4-5

4-5

4-5

4-4

4-4

4-4

4-4

4-4

4-4

4-4

4-5

4-5

4-5

Note: When reassembling, perform the procedure in reverse order.

The “Bottom” on Disassembly column of above

Table indicates the part should be disassembled at the

Bottom side.

7

DECK MECHANISM ASSEMBLY

DECK ASSEMBLY

(L1)

(L1)

TRAY DISK

(B)

(L2)

EMERGENCY

EJECT HOLE

(L1)

(C2)

(C3)

(C1)

(L1)

(C4)

JUNCTION

C.B

(A) (A)

(B)

LEVER

(S1) (S1)

Fig-7

(S1) (S1)

Fig-9

BOTTOM SIDE VIEW

PLATE CLAMP

MAGNET CLAMP

CLAMP LOWER

BRACKET CLAMP

CLAMP

ASSEMBLY DISK

(S2)

(S2)

(A)

(Fig-A)

BRACKET CLAMP

Fig-8

7. Junction C.B (Fig-7)

DECK ASSEMBLY

1) Put the Deck Assembly face down. (Bottom side)

2) Release 4 Screws (S1).

3) Unlock 4 Locking tabs (L1).

4) Lift up the Junction C.B a little to disconnect the

Connector (C1).

5) Disconnect 3 Connectors (C2, C3, C4).

8. Bracket Assembly Clamp (Fig-8)

1) Put the Deck Assembly on original position. (Top side)

2) Release 2 Screws (S2).

3) Lift up the Bracket Assembly Clamp.

8-1.

Clamp Assembly Disk

1) Place the Clamp Assembly Disk as Fig-(A).

2) Lift up the Clamp Assembly Disk in direction of arrow

(A).

3) Separate the Clamp Assembly Disk from the Bracket

Clamp.

8-1-1. Plate Clamp

1) Turn the Plate Clamp to counterclockwise direction and then lift up the Plate Clamp.

8-1-2. Magnet Clamp

8-1-3. Clamp Lower

8-2.

Bracket Clamp

9. Tray Disk (Fig-9)

1) Insert and push a Driver in the emergency eject hole (A) at the front side, or put the Driver on the Lever (B) of the Gear Emergency and pull the Lever (B) in direction of arrow (A) so that the Tray Disk is ejected about 15-

20mm.

2) Pull the Tray Disk until the moving is locked by the

Locking Tab (L2).

3) Unlock the Locking tab (L2) in direction of arrow (B).

4) Separate the Tray Disk completely.

8

CABLE FLEXIBLE

MOTOR ASSEMBLY PU FEED

BASE PU (OUTSERT)

(A)

SHAFT PU SUB SHAFT PU MAIN

PICK UP

ASSEMBLY GENERAL

(C5)

GUIDE FEED PU

BASE PU (OUTSERT)

SPRING SKEW

(S4)

SPRING

GUIDE FEED

(S3)

RUBBER R

(L4)

(A)

Fig-(A)

P.C. BOARD

RED

BLACK

MOTOR

ASSEMBLY PU

FEED

(A)

(L3)

MOTOR (MECH.)

SHAFT LEAD SCREW

(S5)

(S5)

10. Base Assembly Feed (Fig-10)

1) Disconnect the Connector (C5)

2) Release the Screw (S3).

10-1. Rubber R

10-2. Spring Skew

1) Press the (A) position of the Spring Skew and unlock the Spring Skew locking.

10-3. Shaft PU Main

10-4. Shaft PU SUB

Note: When reassembling, be careful not to change the

Shaft PU Main (Long) and the Shaft PU Sub (Short).

10-5. Mechanism Assembly PU Unit

10-5-1. Guide Feed PU

1) Release the Screw (S4) and separate the Guide Feed PU from the Pick up Assembly General.

10-5-2. Spring Guide Feed

Fig-10

10-5-3. Pick Up Assembly General

10-6. Motor (mech.)

1) Release the 3 Screws (S5) at bottom side.

2) Push down the Motor (Mech.) and separate from the

Base PU (Outsert).

10-7. Shaft Lead Screw

1) Push the Shaft Lead Screw in direction on arrow (A) a little and lift up the Shaft Lead Screw.

10-8. Motor Assembly PU Feed.

1) Unlock the Locking tab (L3) and lift up the P.C.Board.

2) Unlock two Locking Tabs (L4) and push down the

Motor Assembly PU Feed.

3) Separate the Motor Assembly PU Feed from the Base

PU (Outsert).

Note: When reassembling, place the Motor Assembly PU

Feed as Fig-(A) and insert the Cable Flexible to the

Hole (A) of the Base PU (Outsert). (See Fig-(A))

10-9. Motor (mech.)

9

(R2)

(R1)

Fig-(B)

Fig-(D)

GEAR EMERGENCY

(S6)

GEAR PULLY

(R2)

GEAR LOADING

CAM LOADING

(R1)

(L6)

(S7)

(L7)

FRAME ASSEMBLY UP/DOWN

RUBBER F

(L6)

(L5)

Fig-(C)

BELT LOADING

MOTOR ASSEMBLY LOADING

CONNECTOR(2 PIN)

(L5)

BASE MAIN

HOLDER

ASSEMBLY

DECK ON

11. Base Assembly Main (Fig-11)

11-1. Holder Assembly Deck On

1) Push the Locking tabs (L5) at bottom side of the Holder

Assembly Deck On in direction of arrow (A) and separate to bottom side. (See Fig-(A))

11-2. Frame Assembly Up/Down.

1) Push the two Locking tabs (L6) and lift up the Frame

Assembly Up/Down.

Note: When reassembling, insert the Lever (R1) of the

Frame Assembly Up/Down to the Groove (R2) of the

Gear Emergency and lock the two Locking Tabs

(L6). (See Fig-(B))

11-3. Rubber F

11-4. Belt Loading

11-5. Gear Pulley

1) Release the Screw (S6) and lift up the Gear Pulley.

Fig-(E)

BOTTOM SIDE VIEW

Fig-(A)

(A)

Fig-11

11-6. Gear Loading

11-7. Gear Emergency

Note: When reassembling, confirm that the Hole (A) of the

Cam Loading is aligned to the Hole (B) of the Gear

Emergency as Fig-(C).

For this alignment, place the Gear Emergency and

Cam Loading as Fig-(D), and then move the Gear

Emergency in direction of arrow (B) until these two gears are aligned as Fig-(C).

11-8. Cam Loading

11-9. Motor Assembly Loading

1) Release two Screws (S7).

2) Unlock the Locking tab (L7) and separate the Motor

Assembly Loading to bottom side.

Note: When reassembling, confirm that the Connector (2

Pin) is aligned as Fig-(E)

11-10. Base Main

10

ELECTRICAL MAIN PARTS LIST

REF. NO PART NO.

KANRI

NO.

DESCRIPTION

IC

SI-AM2-980-01A IC,AM29F800B-120EC

SI-AL2-402-10E IC,AT24C02N-10SC-2.7

SI-AL4-981-92B IC,AT49F8192A-90TC

SI-RH5-983-20A IC,BA5983FP-E2

SI-RH6-859-20A IC,BA6859AFP-E2

SI-RW8-610-00A IC,BT861

SI-HY2-580-10A IC,GDC25D801AA

SI-GS7-142-60E IC,GM71C4260CJ-60

SI-HI6-417-03B IC,HD6417034AFI20

SI-SS4-310-00A IC,KA431AZ

SI-SS7-542-00A IC,KA7542Z

SI-SS7-808-00H IC,KA78R08 4P

SI-KE3-930-00G IC,KIA393F-EL

SI-KE4-310-00A IC,KIA431 3P

87-001-196-010 IC,KIA7042P

SI-SS4-161-02F IC,KM4161020CT-G7

SI-SA8-661-12C IC,LC866112B-5N21

SI-JR3-414-00C IC,NJM3414AM-TE1,3K/REEL

SI-JR4-580-00B IC,NJM4580M

SI-BB1-716-00A IC,PCM1716E 28P

SI-BB1-700-00A IC,PLL1700E 20P

SI-SH2-050-00A IC,PQ20WZ5U 20WZ51

SI-SH3-130-00A IC,PQ3DZ13U

SI-TI7-437-40K IC,SN74AHC374PWLE

SI-SK6-153-00A IC,STR-G6153T 5P

SI-TO1-254-00B IC,TA1254AF

SI-TO1-254-00A IC,TA1254F

SI-TO7-040-00F IC,TC7W04FU

SI-MQ5-316-25A IC,V53C16256HK50

SI-CU3-000-00A IC,ZIVA3-PE0

SI-GS7-216-16C ICGM72V161621ET-7

TRANSISTOR

ST-R10-500-9AD TR,KRA105M

ST-R10-300-9AE TR,KRC103M

ST-R10-500-9AB TR,KRC105M

ST-R11-510-0AA TR,KSB1151-Y

ST-R12-670-9AC TR,KTA1267-GR

ST-R15-040-9BF TR,KTA1504S-Y

ST-R15-050-9AD TR,KTA1505S-Y

ST-R31-980-9AC TR,KTC3198-TP-BL

ST-R13-040-9BA TR,KTD1304S

ST-R10-000-9CB TR,UMX1N

ST-R10-000-9BM TR,UMZ1N 3K

87-070-334-070 ZENER,MTZ10B

SM-TZ6-8CT-000 ZENER,MTZ6.8C

DIODE

SD-D19-300-9AB C-DIODE,KDS193

ST-R10-370-9BB C-TR,2SA1037K-Q

ST-R10-300-9AA C-TR,KRC103S-T1

ST-R38-750-9AC C-TR,KTC3875S-GR-T1

SD-R15-402-0BA DIODE,1N5402

87-020-465-080 DIODE,1SS133

SD-R10-451-0AA DIODE,B10A45V1

SD-D01-000-9CA DIODE,EG01CW

SD-R18-020-9AA DIODE,ERA18-02KFRB

87-A40-284-080 DIODE,ERA22-10

SD-D01-000-9AC DIODE,EU01W

83-NEG-677-080 DIODE,MTZ5.6B

SD-R49-500-9AA DIODE,RB495D

87-017-352-010 DIODE,RU3YXLF-C1 100V2

87-070-173-010 DIODE,S1WBA60

MAIN C.B

11

REF. NO PART NO.

KANRI

NO.

DESCRIPTION

C204 SC-H71-06C-611 C-CAP,10UF-6.3V

C207 SC-H71-06C-611 C-CAP,10UF-6.3V

C213 SC-H71-06C-611 C-CAP,10UF-6.3V

C214 SC-H71-06C-611 C-CAP,10UF-6.3V

C215 SC-H71-06C-611 C-CAP,10UF-6.3V

C216 SC-H71-06C-611 C-CAP,10UF-6.3V

C218 SC-H71-06C-611 C-CAP,10UF-6.3V

C219 SC-H71-06C-611 C-CAP,10UF-6.3V

C220 SC-H81-07C-621 C-CAP,100UF-6.3V

C224 SC-H71-06C-611 C-CAP,10UF-6.3V

C226 SC-H71-06C-611 C-CAP,10UF-6.3V

C230 SC-H71-06C-611 C-CAP,10UF-6.3V

C302 SC-H81-07C-691 C-CAP,100UF-6.3V

C310 SC-H71-06F-621 C-CAP,10UF-16V

C311 SC-H71-06F-621 C-CAP,10UF-16V

C708 SC-H71-06C-611 C-CAP,10UF-6.3V

C709 SC-H82-27D-611 C-CAP,220UF-10V

C712 SC-H71-06C-611 C-CAP,10UF-6.3V

C713 SC-H71-06C-611 C-CAP,10UF-6.3V

C714 SC-H71-06F-621 C-CAP,10UF-16V

C718 SC-H71-06C-611 C-CAP,10UF-6.3V

CE201 SC-H84-76C-611 C-CAP,47UF-6.3V

CE202 SC-H84-76C-611 C-CAP,47UF-6.3V

CE203 SC-H84-76C-611 C-CAP,47UF-6.3V

CE205 SC-H84-76C-611 C-CAP,47UF-6.3V

CE206 SC-H84-76C-611 C-CAP,47UF-6.3V

CE210 SC-H84-76C-611 C-CAP,47UF-6.3V

CE211 SC-H84-76C-611 C-CAP,47UF-6.3V

CE221 SC-H84-76C-611 C-CAP,47UF-6.3V

CE223 SC-H84-76C-611 C-CAP,47UF-6.3V

CE228 SC-H84-76C-611 C-CAP,47UF-6.3V

CE609 SC-H81-07F-611 C-CAP,100UF-16V

CE610 SC-H81-07F-611 C-CAP,100UF-16V

CE710 SC-H84-76C-611 C-CAP,47UF-6.3V

X101 S2-12H-B20-02A CCR20.0MC6T TDK 20000000H

X301 S2-02R-427-01G C-RESO 27MHZ 20P

JUNCTION C.B

CE450 87-010-140-080 CAP,E 47-16V

CE451 87-010-140-080 CAP,E 47-16V

CE452 87-010-140-080 CAP,E 47-16V

CE453 87-010-140-080 CAP,E 47-16V

R451 SR-D01-01H-633 RES,1-1/2W

R452 SR-D01-01H-633 RES,1-1/2W

TIMER C.B

C500 SC-E22-73D-638 CAP,E 220-10V

C502 SC-E10-63F-638 CAP,E 10-16V

C506 SC-E47-63J-638 CAP,E 47UF-35V

C507 SC-E10-63F-638 CAP,E 10-16V

C512 87-010-140-080 CAP,E 47-16V

C513 87-010-140-080 CAP,E 47-16V

DIG501 S3-02H-V00-1D0 7-BT-259GK DH

LED501 SD-L32-531-9AA LED SPR325MVWT31(GRN)

RC501 S7-12R-083-8GA TSOP1238UQ1 TEMIC 8MM 37 RC

SW501 S5-562-19B-000 SW,SKHV10910B

SW502 S5-562-19B-000 SW,SKHV10910B

SW503 S5-562-19B-000 SW,SKHV10910B

SW503 S5-562-19B-000 SW,SKHV10910B

SW504 S5-562-19B-000 SW,SKHV10910B

SW505 S5-562-19B-000 SW,SKHV10910B

SW506 S5-562-19B-000 SW,SKHV10910B

SW507 S5-562-19B-000 SW,SKHV10910B

SW510 S5-562-19B-000 SW,SKHV10910B

SW511 S5-562-19B-000 SW,SKHV10910B

SW512 S5-562-19B-000 SW,SKHV10910B

SW513 S5-562-19B-000 SW,SKHV10910B

REF. NO PART NO.

KANRI

NO.

DESCRIPTION

SW514 S5-562-19B-000 SW,SKHV10910B

X501 S6-160-20P-000 CSA6.00MGU MURATA 6MHZ

JACK C.B

CV1 87-010-060-080 CAP,E 100-16V

CV2 SC-E22-76F-638 CAP,E 220UF-16V

CV3 87-010-237-910 CAP,E 1000UF-16V

CV6 87-015-681-080 CAP,E 10-16V

CV8 87-010-140-080 CAP,E 47-16V

CV10 SC-E10-86F-630 CAP,E 1000-16V

CV12 87-015-681-080 CAP,E 10-16V

CV13 87-015-684-080 CAP,E 47-16V

CV14 87-015-681-080 CAP,E 10-16V

CV15 87-015-681-080 CAP,E 10-16V

CV16 87-016-577-080 CAP,E 470UF-16V

CV21 87-010-060-080 CAP,E 100-16V

JACK1 S6-12H-K26-02A TOTX178 TOSHIBA AN/DIP

JACK2 S5-720-75A-000 BJP-202L BAEEN BLACK

JACK3 S6-12R-IH0-05D JACK,PPJ6031J

REF. NO PART NO.

KANRI

NO.

DESCRIPTION

C906 S6-240-87B-000 CAP,100P-1KV

C907 SA-1B3-0KH-2M0 CAP,220PF-400V

C913 87-012-379-010 CAP,3300PF-400V

C916 87-010-387-010 CAP,E 470UF-25V KME

C918 87-010-112-080 CAP,E 100-16V

C919 87-010-408-040 CAP,E 47UF-50V

C921 SC-E22-76F-638 CAP,E 220UF-16V

C923 87-010-237-910 CAP,E 1000UF-16V

C924 87-010-237-910 CAP,E 1000UF-16V

C925 87-010-375-080 CAP,E 330-10V

C926 87-010-408-040 CAP,E 47UF-50V

C927 87-015-684-080 CAP,E 47-16V

C929 87-010-112-080 CAP,E 100-16V

C932 SC-E47-7CD-638 CAP,E 470UF-10V

C934 SC-E47-7CD-638 CAP,E 470UF-10V

!

F901 S5-850-11T-000 FUSE,1600MA 250V

!

IC903 S6-570-62B-000 SENSOR PC123Y

!

L901 S6-161-45H-000 FILTER SHT LFS2020V4-04350

!

L901 S6-161-45J-000 FL BUJEON V-04350

L902 S6-330-88G-000 COIL,CHOCK TP 5MM

JACK4 S6-12R-BH0-08A YKF51-5506 JALCO HORIZONT4P

JACK8

KEY C.B

SW508 S5-562-19B-000 SW,SKHV10910B

L903 S6-330-88D-000 COIL,20UH

R901 S6-140-07R-000 RES,2.7-2W

R902 SR-S10-03K-619 RES,100K-2W

R911 SR-S05-10K-619 RES,0.51-2W

R922 SR-S12-00J-619 RES,M/F 120-1W

!

T901 S6-420-23T-000 PT,SHT-023T/KSE-023T

!

V901 S6-560-04F-000 SVR681D10A SAMYANG 680V

POWER C.B

C900 87-010-408-040 CAP,E 47UF-50V

C901 S6-240-88B-000 CAP,0.1UF-250V

C902 S6-240-88B-000 CAP,0.1UF-250V

C902 S6-240-88F-000 CAP,PCX2 275V 0.1UF,M

C905 87-016-375-010 CAP,0.01UF-630V

• Regarding connectors, they are not stocked as they are not the initial order items.

The connectors are available after they are supplied from connector manufacturers upon the order is received.

CHIP RESISTOR PART CODE

Chip Resistor Part Coding

8 8

A

Resistor Code

Figure

Value of resistor

Chip resistor

Wattage

1/16W

1/16W

1/10W

1/8W

Type

1005

1608

2125

3216

Tolerance

5%

5%

5%

5%

TRANSISTOR ILLUSTRATION

Symbol

CJ

CJ

CJ

CJ

Form

L

W

Dimensions (mm)

L W t

1.0

0.5

0.35

t

1.6

0.8

0.45

2 1.25

0.45

3.2

1.6

0.55

: A

Resistor Code : A

104

108

118

128

ECB

KRA105M

KRC105M

KRC103M

ECB

KSB1151

C

B

E

2SA1037K

KTA1504S

KTA1505S

KTC3198

KTC3875S

KTC4419

KTD1304S

12

BCE

KSE13005F

C2

B1

E1

E2

B2

C1

UMX1N

UMZ1N

BLOCK DIAGRAM-1 (OVERALL)

A[0:7]

Hsync

VDAT

Vsync

27MHz

Composite

A[00:15] ICDAT

ICADDR[0:8]

13

BLOCK DIAGRAM-2 (POWER)

TRANS

Q901

KTC4419

SWITCHING IC

RECTIFIER LINE FILTER

14

BLOCK DIAGRAM-3 (RF/DSP/SERVO)

9

16

A[00:15] ICDAT

ICADDR[0:8]

15

BLOCK DIAGRAM-4 (AUDIO)

16

BLOCK DIAGRAM-5 (MPEG) BLOCK DIAGRAM-6 (SYSTEM CONTROL)

17 18

WIRING-1 (MAIN: COMPONENT SIDE)

14 13 12 11

NOTE

Cxxx

Lxxx

Rxxx

E

B

C

E

MAIN C.B

(COMPONENT SIDE)

10

1

2

TO/FROM

JUNCTION C.B

CN404

20

19

R184

C128

R191

14

15

2

1

85

84 57

56

1 5

105

104

112

1

14

15

2

1

1 40

28

29

20 21

9

156

157

8 7 6 5 4 3 2

TO/FROM

JUNCTION C.B

CN402

TO/FROM

POWER C.B

CON902

1

2

1

64 49

48

16

17 32

33

25

26 1

53

52

157

156

10

5 1

105

104

E

E

E

1

2

5 1

R787

R714

R801

8 5

1 4

CE711

C712

R726

C715

R723

R721

C713

R732

21

22

E

1

2

208

1

21

22

R384

R385

208

1

R309

R312

52

53

1

C

D

E

F

G

H

A

B

I

J

19 20

WIRING-2 (MAIN: CONDUCTOR SIDE)

1 2 3

A

MAIN C.B

(CONDUCTOR SIDE)

B

4

C

D

E

F

NOTE

Cxxx

G

H

Lxxx

Rxxx

E

I

B

C

E

1

4

8

5

25

48

5 6 7 8 9 10 11 12

20 11

1 10

6 4

1 3

8 5

1 4

R188

R193

1 50 1 50

24

1

8 5

1 4

E

E

1

44 34

33

1

11

12 22

23

8 5

1 4

20

40

21

11

20

10

1

25 26 25 26

8

1

5

4

E

E

E

5

1

1

20

80

21

28

1

61

60

40

41

E

R823

E

E

15

R717

CE712

14

R736

E

E

E

3 1

4 6

E

C728

13

J

14

21 22

SCHEMATIC DIAGRAM-1 (MAIN 1/5)

23 24


25 26


27 28


29 30


31 32

SCHEMATIC DIAGRAM-6 (JACK)

33

RV31

180

QV07

KTA1267

CV16

470

µ

F

/16V

RV32

680

RV33

75

CV24

220 µ F

/16V

QV01

KTA1267

RV08

820

QV03

KRC103M

CV12

10 µ F

RV03

10K

RV04

2.2K

DV02

1SS133

QV02

KRC103M

RV05

1.0K

FV06

FV07

FV08

FV05

BVD01

BEAD

BVD02

BEAD

BVD03

BEAD

JK08

SCART JACK

A Rout

JACK08

EURO AV (TV)

A Lout

GND

GND

BLUE

CONTROL

GREEN

GND

GND

RED

GND

GND

V.–out

GND

34

G

H

J

I

E

F

C

D

WIRING-3 (JUNCTION/JACK)

1 2 3

A

B

4 5 6

JACK C.B

DIGITAL OUT

JACK01 JACK02

OPTICAL COAXIAL

3 1

7 8

JUNCTION C.B

M2

(SLED MOTOR)

M

TO/FROM

MAIN C.B

CON202

SW1

INSIDE

LIMIT

SW

M1

M

SPINDLE

MOTOR

TO/FROM

MAIN C.B

CON201

TO/FROM

MAIN C.B

CON201

M3

(LOADING MOTOR)

M

TO/FROM

MAIN C.B

CON801

9 10

JACK03

AUDIO OUT

L

R

VIDEO

OUT

JACK04

S-VIDEO

OUT

11 12 13

JACK08

EURO AV (TV)

1 5

10

15

20

14

OPEN/CLOSE

SWITCH

NOTE

E C B

PICK UP

ASSY

TO/FROM

POWER C.B

CON904

K

35 36

SCHEMATIC DIAGRAM-7 (JUNCTION)

37 38

G

H

J

I

E

F

C

D

WIRING-4 (TIMER/KEY/POWER)

1 2 3

A

B

K

39

4 5 6 7 8 9 10 11 12 13 14

40

SCHEMATIC DIAGRAM-8 (TIMER/KEY)

41 42

SCHEMATIC DIAGRAM-9 (POWER)

POWER C.B

T901

AC 200-240V

50Hz

43

4 1

3

INSULATOR

2

+8V REG.

C932

470

µ

/10V

A5V REG.

POWER

CONTROL

44

WAVE FORM

1

IC201 Pin ( (LVL) SBADD VOLT/DIV: 500mV

TIME/DIV: 2mS

IC201 Pin ¡ (FEO) Focus Error VOLT/DIV: 2.9V

TIME/DIV: 2mS

5

IC206 Pin (A OUT3)

SLED Drive (FMO)

VOLT/DIV: 2.12V

TIME/DIV: 10mS

2

IC201 Pin ) (TEO)

Tracking Error

VOLT/DIV: 2.2V

TIME/DIV: 2mS

6

IC201 Pin ¡ (FEO)

Focus Error (In Focus search)

Focus Drive (FDO)

VOLT/DIV: 200mV

TIME/DIV: 100mS

VOLT/DIV: 2.14V

TIME/DIV: 100mS

3

IC201 Pin ) (TEO)

VBR Tracking Error

4

IC201 Pin • (RFO)

VOLT/DIV: 2.27V

TIME/DIV: 500µS

7

IC801 Pin #-^ (P0-P3)

IC801 Pin (-™ (P4-P7)

MPEG Data

VOLT/DIV: 280mV

TIME/DIV: 500µS

Tek Stop : 1 00kS/s 3290 Acqs

Record

Length

3

Ch3

Time Base

Main

1.00V

Trigger

Position

50%

Record

Length

2500

T

M 500 µ s CH1

Horiz

Scale

(/div)

Horiz

Pos

280/mV

Fit to Screen

OFF

500 points in

10divs

1000 points in

20divs

2500 points in

50divs more

1 of 3

FastFrame

Setup

VOLT/DIV: 0.5V

TIME/DIV: 0.1µS

45

8

9

IC801 Pin (DACC)

Composite

IC801 Pin (DACB)

Chrominance

VOLT/DIV: 500mV

TIME/DIV: 20µS

@

IC801 Pin (CLK IN)

MPEG Clock

Tek Stop : 1 00kS/s 3290 Acqs

VOLT/DIV: 280mV

TIME/DIV: 500µS

Edge Slope

T

VOLT/DIV: 500mV

TIME/DIV: 20µS

3

Ch3 1.00V

Type

<Edge>

M 500 µ s CH1

Source

Ch1

Coupling

DC

Slope

280/mV

Level

280mV

Mode

&

Holdoff

#

IC801 Pin ≤ (VSYNC)

Vertical SYNC

Tek Stop : 10.0kS/s 13 Acqs

[ T ]

VOLT/DIV: 280mV

TIME/DIV: 5mS

Edge Slope

T

0

IC801 Pin (DACA)

Luminance

59

Tek Stop : 2.50MS/s 4 Acqs

[T ]

VOLT/DIV: 500mV

TIME/DIV: 20µS

3

Ch3 1.00V

Type

<Edge>

Source

Ch1

M 5 .00ms CH1

Coupling

DC

Slope

280/mV

Level

280mV

Mode

&

Holdoff

$

IC801 Pin ∞ (HSYNC)

Tek Stop : 2.50MS/s 7 Acqs

[ T ]

VOLT/DIV: 280mV

TIME/DIV: 20µS

Edge Slope

T

T

3

Ch3 500mV

!

IC801 Pin (SID)

SDA/SCL

M20.0

µ s Glitch Ch1 2 Apr 1999

14:47:27

VOLT/DIV: 2.06V

TIME/DIV: 25mS

3

Ch3 1.00V

Type

<Edge>

M 20.0

µ s CH1

Source

Ch1

Coupling

DC

Slope

280/mV

Level

280mV

Mode

&

Holdoff

%

IC801 Pin + (DACF)

Component Pb

VOLT/DIV: 500mV

TIME/DIV: 20µS

46

^

IC801 Pin , (DACE)

Component Pr

VOLT/DIV: 500mV

TIME/DIV: 20µS

&

IC801 Pin < (DACA)

Component Y

VOLT/DIV: 500mV

TIME/DIV: 20µS

47

TROUBLE-SHOOTING

1. Power Circuit

• Input Voltage: 120V

• It is possible to malfunction, if the unload condition is left for a long time when power is on.

(More than Dummy load 100mA)

• A Primary side is abnormal when the fuse is short, secondary side is abnormal when the IC103 oscillates intermittently.

• The resistor value of both terminal is measured with DVM crossing each other to check the each element is normal or abnormal.

(It is normal when the numerical value is different each other.)

START

Check the GND of C901 and

IC901 Pin 3 with oscilloscope.

NO

Is CON903 Pin 3

5.2V?

YES

NO

Replace

IC902.

NO

Replace defective parts.

Check Q904 and ZD903.

Is F901 normal?

YES

YES

Front Circuit

Board is

abnormal

When IC901 oscillating

Does oscillate

continuously when

the CON903 is

disconnected ?

NO

Secondary side is abnormal.

Are D908, D909,

D907, D910, D906 and D905 normal?

YES

NO

Replace Q908 and Q909.

(A)

Is IC901 Pin 3 switching normally?

<Fig-3-1>

YES

NO Is IC905 normal?

In condition of DC140V.

(Feedback is abnormal)

YES

Is CN903 Pin 3 5.2V?

NO

Check or replace

D908.

YES

After connect

CON903

Pin 1 , 3 short.

Are R922, C927, R921 and R918 normal?

NO

Are CON902

Pin 5, 6 and

9 5V?

YES

Is CON904

Pin 3 8V?

YES

Is CON902

Pin 3 12V?

YES

NO

A primary side is abnormal.

To (A).

Are CON903

Pin 5 -24V, Pin 7 -20V and

Pin 8 -16V?

YES

NO

END

Is voltage of

BD901 140V?

YES

Are R907, D902,

D903 and R902 normal?

YES

Are D901, R904,

R905 and R906 normal?

YES

Is PC901 normal?

YES

END

Replace defective parts.

IC901 Pin 3

Normal switching waveform on the stand-by mode at the AC110V

NO

NO

NO

NO

48

2. µ-COM Circuit

A. No Power

POWER ON

NO

Power RED LED on?

YES

Does Bar appear at FLD?

NO

Refer to Front Part.

YES

Does Logo appear on the screen?

YES

OK

Do all five Bars appear?

NO

NO

1

Is oscillation of

X101 normal?

YES

NO

Check the oscillation

Are IC107 Pin $, • and ª normal?

YES

A

NO

Check short.

OK

Replace IC107 or IC108.

NO Is CON107 connected normally?

Reconnect it.

YES

Refer to Front Part

NO

NO

Check power.

(Refer to power)

If power is normal

Is CON107 Pin 6 normal?

YES

A

1

The waveform on A [00:21] and D [00:15] of IC108 normal?

YES

Check short

Replace IC101.

NO Are IC101

Pin 7, 8 normal?

YES

Replace Main B/D.

END

49

B. Audio abnormal C. Video abnormal

AUDIO ABNORMAL

Check Audio jack.

YES (If OK)

Check PLL FC of

MPEG part.

YES (If OK)

Refer to Audio part.

YES (If OK)

Refer to MPEG part.

YES (If OK)

Replace B/D.

END

D. Open/Close abnormal

OPEN/CLOSE ABNORMAL

Check Front.

YES (If OK)

Check the connection of

CON107.

YES

NO

Check the connection of MD.

YES

NO

Refer to SERVO part.

Check IC101

Pin #, $.

YES

VIDEO ABNORMAL

Check Video jack.

YES (If OK)

Refer to Video part.

YES (If OK)

Refer to Encoder part.

YES (If OK)

Refer to MPEG part.

YES (If OK)

Replace B/D.

END

Reconnect it.

50

E. Picture abnormal

PICTURE ABNORMAL

Check the disc.

Refer to Servo part

If OK

Check PLL IC of MPEG part

YES (If OK)

Check DSP

YES (If OK)

Check MPEG

YES (If OK)

Replace B/D

END

F. Disc Error

DISC ERROR

Check Disc

YES (If OK)

Refer to Servo part

YES (If OK)

Replace B/D

END

51

3. MPEG Circuit

Power is on

Does aiwa Logo appear on the screen?

YES

Does the moving picture of the DVD Disc play on the screen normally?

YES

Does the moving picture of the video

CD play on the screen normally?

YES

Does the audio sound output normally?

YES

END

NO

NO

Check power & clock.

YES

A

Is MPEG data signal normal?

YES

NO

OK

Check CD/DVD DSP output signal.

OK

B

Check MPEG Decoder input signal.

C

YES

Is error signal normal?

NO

I OPTION

If included VCD function.

Is MPEG data signal normal?

YES

Is Clock normal?

YES

NO Does the audio sound output from MPEG decoder?

YES

NO Check CD/DVD DSP output signal.

OK

D


E

NO

Check CD/DVD DSP output signal.

OK

F


G

NO

Check clock signal H

Check clock signal I

52

4. Front Circuit (Digitron & key)

START

Power on.

LED ON?

YES

NO Is oscillation of

X501 normal?

YES

Is Digitron on normally?

YES

Do all the buttons work normally?

YES

NO

CD

Check waveform of IC500 Pin 6.

YES

NO

Check waveform of

IC500 Pin #.

YES

Is waveform of IC500

YES

NO

Solder defective parts again

NO

NO

NO

Check Power.

Replace IC501.

Check waveform of IC500 Pin #.

YES

Replace IC500.

NO

Solder Key part.

Check waveform of Q500 Pin 2.

YES

Replace LED501.

NO

Replace Q500.

Check and replace R516,

R507, R506, R500, R505,

R504, R512 and R503.

Does remote control work normally?

YES

Complete repairing

Front B/D.

NO Does pulse waveform of RE500

Pin 3 appear?

YES

Is IC500

Pin ≤ connected to

RE500 Pin 3?

YES

NO

Replace IC500.

YES

Is RE500 Pin 2

5V?

YES

NO

Solder defective parts

Replace RE500

YES

Re-solder.

YES

Recheck

53

5. RF/Servo Circuit

A.

CHECK POINT (General)

Does signal goes the power is on?

YES

NO

Does signal when the power is on?

YES

Does TTL pulse output to IC206

Pin , ?

YES

NO

NO

Check “2.

µ

-COM Part”.

Does

33.8688MHz clock input

YES

NO

Replace IC206

(IC206 soldering or IC defect).

Replace IC700

(IC700 soldering or IC defect).

Is IC206 about 2.2V?

YES

END

NO

Replace X301 or IC308

(30MHz clock defect)

54

B.

No disc

Power on Check loading Part.

Does tray open or close?

YES

NO Push Pick-up to inner track to the end by hand.

Does

CON202 Pin & change high to low?

YES

NO

Pressing the open/close key repeatedly, check the voltage of CON202 Pin 9 change 0V to 5V

YES

Junction Board

Does the voltage change at

IC401 Pin %, ^ more than 2V on the basis of 4.5V?

YES

NO

NO

Fig-1. SLED Driver waveform

DECK assembly is defective.

DECK assembly is defective.

(Limit sw) check

µ

-COM Part.

Replace IC401.

Does the pick-up slide inner or outer track?

YES

NO

Fig-2. Focus Driver waveform

Check SLED Driver output.

IC206 Pin IC401 Pins *, &.

IC401 Pin * no output : IC401 is defective

Does the pick-up lens move up and down?

YES

NO Check Focus Driver output.

(IC206 Pin , IC401 Pins !, @)

IC401 Pin 1 , 2 no output : IC701 is defective

Slide the pick-up to inner track.

END

55

C.

DISC IN

OPEN/CLOSE

FOCUS ON?

YES

NO

Check the focus error moving the lens up and down. (IC201

Pin ¡)

YES

NO

Fig-3. FOCUS ERROR waveform

IC201 no output: Pick-up is defective.

Does the

TTL level change at IC206 the lens?

YES

NO

Replace IC206.

Replace

µ

-COM or IC206.

Does the disc turn?

YES

NO Check CON404 Pin 4, 6

Motor turn when the Pin 4 is less than 1.6V

Check IC206 and IC403 when the Pin 4 is abnormal

NO

Check A

YES

Is OK the track jump.

YES

NO Does the signal pulse input at IC700 Pin ≥,

• and ª?

YES

NO

µ

-COM part is defective. Check

“2.

µ

-COM Circuit.”

Does the screen appear?

YES

NO Video Par is defective.

Check “5.MPEG Circuit.”

Check “7.OSD/Video Circuit.”

END

Replace IC700.

56

D.

CHECK A

Fig-5. RF waveform

Check RF Eye-Pattern.

RF: 1.0-2.1V (IC201 Pin •)

YES

NO

No signal: Pick-up is defective

Is the eye-pattern vivid?

YES

NO Does the sawtooth waveform emit at IC201 Pin )?

YES

NO

Does the 1.6V emit?

YES

NO

Replace IC201.

Replace IC206.

No signal at IC206: IC206 is defective

• Check IC206 Pin

162

• Check the clock at the IC206

Pin •, º.

• Both are normal: IC206 is defective

END

57

LCD DISPLAY

58

IC DESCRIPTION

IC, BT861

Pin No.

Pin Name

1-6 VID2-7

7

8

9

VDD

GND

VIDCLK

10

11

12

13-16

17

18

19-22

23

24

25

26

27

28

VIDVALID

VIDVACT

VIDHACT

P0-P3

GND

VDDMAX

P4-P7

BLANK

VSYNC

HSYNC

FIELD

GND

VDD

—

—

I

I/O

—

—

I

I

I

I

I

I

I

I/O

I/O

O

—

—

Description

Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A higher index corresponds to a greater bit significance. Data on the VID port is latched by rising edge of VIDCLK. (Connected to GND.)

Digital power.

Digital ground.

2x pixel clock for secondary video input port. Synchronization circuitry exists for this port to lock it to the primary video port. (Connected to GND.)

Video data valid qualifier. A logical 1 indicates data on VID [7:0] is valid data. The sense of this signal is controlled by the VIDVALIDI bit of register 0x1C. (Connected to GND.)

Vertical active display region. The sense of this signal is controlled by the VIDVACTI bit of register 0x1C. (Connected to GND.)

Horizontal active pixel signal. A logical 1 indicates data on VID [7:0] is in the horizontal display region. The sense of this signal is controlled by the VIDHACTI bit of register 0x1C. (Connected to GND.)

Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher index corresponds to a greater bit significance. (1) Data is latched on the rising edge of the system clock.

Digital ground. Refer to the PC Board Considerations section of this

This pin must be tied to the maximum digital input value. Use 3.3 V if only “3.3 V inputs are used, and 5 V if 5 V inputs are used.”

Primary video input port. TTL compatible pixel data in 8-bit YCrCb format. A higher index corresponds to a greater bit significance. (1) Data is latched on the rising edge of the system clock.

Composite blanking control input (TTL compatible). BLANK is registered on the rising edge of the system clock. The P [7:0] inputs are ignored while BLANK is a logical 0. The sense of this signal is controlled by the BLANKI bit of register 0x19.

Vertical sync input/output (TTL compatible). As an output (master mode “operation),

VSYNC is output following the rising edge of the system” “clock. As an input (slave mode operation), VSYNC is registered on the” rising edge of the system clock. The sense of this signal is controlled by the VSYNCI bit of register 0x19.

Horizontal sync input/output (TTL compatible). As an output (master mode

“operation), HSYNC is output following the rising edge of the system” “clock. As an input (slave mode operation), HSYNC is registered on the” rising edge of the system clock. The sense of this signal is controlled by the HSYNCI bit of register 0x19.

Field control output (TTL compatible). FIELD transitions after the rising “edge of the system clock, two clock cycles following falling HSYNC. The” sense of this signal is controlled by the FIELDI bit of register 0x19. The state of this pin at power-up determines the default state of the PCLK_SEL “register. If not loaded, this pin will be pulled low with an internal pull-down” resistor.

Digital ground.

Digital power.

59

48

49

50

51

52

53

58

59

60

61

54

55

56

57

62

Pin No.

29, 30

41

42

43

44

45

46

31-36

37

38

39, 40

47

Pin Name

ALPHA0, 1

COMP1

VAA

VBIAS1

DACC

DACB

DACA

AGND

GND

OSD0-5

GND

VDD

OSD6 ,7

AGND

DACF

DACE

DACD

VBIAS2

VAA

COMP2

FSADJ2

VREF

N/C

AGND

VAA

FSADJ1

ALTADDR

O

—

—

—

—

—

O

O

O

—

—

O

I

—

—

I

—

O

O

O

I/O

I

I

I

I

Description

“Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection” between video and graphic overlay data. Signals are latched using the system clock. (Connected to

GND.)

Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.

Signals are latched using the system clock. (Connected to GND.)

Digital ground.

Digital power.

Dedicated graphic overlay port. Pixel data (TTL compatible) in 8-bit YCrCb format.

Signals are latched using the system clock. (Connected to GND.)

Analog ground.

Component chrominance U channel, component blue, or composite video.

Component chrominance V channel, component green, or composite video.

“Component luminance, component red, or optional luma-delayed” composite video.

AGND; the capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum.

Analog power.

This pin to VAA. The capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. COMP1 is used with DACs A/B/C and COMP2 is used with DACs D/E/F.

Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these pins and AGND controls the full-scale output current on the “analog outputs. For standard operation, use the nominal values shown” under Recommended Operating

Conditions. FSADJ2 controls DACs D/E/F.

Voltage reference pin.

Not used.

Analog ground.

Analog power.

Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these pins and AGND controls the full-scale output current on the “analog outputs. For standard operation, use the nominal values shown” under Recommended Operating

Conditions. FSADJ1 controls DACs A/B/C.

Compensation pin.

Analog power.

DAC bias voltage.

Composite video.

Modulated chrominance video signal or optional luma-delayed composite video.

Luminance video or optional composite video.

Analog ground.

Digital ground.

Alternate slave address input (TTL compatible). A logical 1 corresponds to “write address of 0x88 and a read address of 0x89, while a logical 0” corresponds to a write address of 0x8A and a read address of 0x8B. See the Serial Programming Interface section for more detail. (Connected to GND.)

60

Pin No.

63

72

73

74

75

76

77

78

79, 80

64

65

66

67

68

69

70

71

Pin Name

RESET

VIDFIELD

TTXREQ

TTXDAT

SID

SIC

GND

VDD

VID0, 1

VDD

GND

PGND

XTI

XTO

VPLL

CLKO

CLKIN

O

I

I/O

I

—

—

—

—

—

I

O

—

O

I

I/O

I

I

I

Description

Reset control input (TTL compatible). Setting to zero resets both video “timing

(horizontal, vertical, subcarrier counters to the start of VSYNC of” “first field) and the serial control interface, and resets the registers. RESET” must be a logical 1 for normal operation.

Digital power. Refer to the PC Board Considerations section of this

Digital ground.

Dedicated ground for PLL.

Crystal input for genlock PLL. (Not used.)

Crystal output for genlock PLL. (Not used.)

Dedicated power supply for PLL. (Connected to VDD.)

2x pixel clock for the primary video port. Generated by PLL or pass-through from

CLKIN pin. (Not used.)

2x pixel clock input (TTL compatible).

Field indicator for video input port. A logical 1 indicates data is from an odd field. The sense of this signal is controlled by the VIDFIELDI bit of register 0x1C. (Connected to

GND.)

Teletext request output (TTL compatible). (Connected to VDD.)

Teletext bit stream input (TTL compatible). (Connected to GND.)

Serial interface data input/output (TTL compatible). Data is written to and read from the device via this serial bus.

Serial interface clock input (TTL compatible). The maximum clock rate is 400 kHz.

Digital ground.

Digital power.

Secondary video input port. Pixel data (TTL compatible) in 8-bit YCrCb format. A higher index corresponds to a greater bit significance. Data on the VID port is latched by rising edge of VIDCLK. (Connected to GND.)

61

IC, CL61330

Pin No.

1

2-4

5

13

14

16

37

38

39

40

28

29

30

31-35

36

41

42

43-46

17

18

19

20

21-26

27

8-11

12

6

7

15

Pin Name

P100

HDATA0-2

VDD_3.3

HDATA3

VSS

HDATA4-7

VDD_2.5

RESET

VSS

/WAIT

/INT

VDD

/AMWE

VSS

O

—

—

—

I/O

I/O

I/O

—

I/O

—

I/O

—

I

—

O

Description

Programmable I/O pins.

8-bit bi-directional host data bus. Host writes data to the decoder Code FIFO via

HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HDATA [7:0].

3.3-V supply voltage for I/O signals.


HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HDATA [7:0].

Ground for core logic and I/O signals.


HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal egisters and local SDRAM/ROM via HDATA [7:0].

2.5-V supply voltage for core logic.

Hardware reset. An external device asserts RESET (activeLOW) to execute a decoder hardware reset. “ To ensure proper initialization after power is stable, assert RESET for at least 20 ms.”


Transfer not complete/data acknowledge. Active LOW to indicate host initiated transfer is not complete. WAIT is asserted after the falling edge of CS and reassertedwhendecoderis ready to “complete transfer cycle. Open drain signal,” must be pulled-up via 1kW to 3.3 volts. Driven high for 10 ns before tristate.

“Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Driven high for” 10 ns before tristate.


Not used.


HDATA8-13

VDD

HDATA14

VSS

HDATA15

HADDR12-16

VDD

HADDR17

VSS

HADDR18

VDD

HADDR19

VSS

HADDR20-23

I/O

—

I/O

—

I/O

—

I/O

—

I/O

I/O

—

I/O

—

I/O

Programmable I/O pins. Input mode after reset.





Programmable I/O pins. Output mode after reset.









62

70

71

72-74

75

76

77

78

64

65

66

67

57

58-60

61

62

63

68

69

79

80

81

Pin No.

47

48

49

50, 51

52

53, 54

55

56

82

88

89

90

91

92

83

84

85

86

87

—

I/O

—

I/O

I/O

—

I/O

O

O

—

I/O

—

I/O

—

—

I/O

—

I/O

—

I/O

—

I/O

I/O

—

I/O

I/O

—

I/O

—

O

O

O

—

O

—

O

—

O

O

O

—

Pin Name

VDD

BEO

VSS

NC

P101

MDATA15, 0

VDD

MDATA14

VSS

MDATA1, 13, 2

VDD_3.3

MDATA12

VSS

MDATA3

VDD

MDATA11

VSS

MDATA4

VDD

MDATA10

VSS

MDATA5, 9, 6

VDD

MDATA8

VSS

MDATA7

LDQM

UDQM

VDD

/MWE

VSS

SD-CLK

/SD-CAS

/SD-RAS

VDD

SD-CS1

VSS

SD-CS0

VDD

NC


Description



No Connection


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.


Memory data.

SDRAM LDQM.

SDRAM UDQM.


SDRAM write enable. Decoder asserts active LOW to request a write operation to the

SDRAM array.


SDRAM system clock.

Active LOW SDRAM column address.

Active LOW SDRAM row address.


Active LOW SDRAM bank select.


Active LOW SDRAM bank select.


No Connection.

63

118

119

120-122

123

124

125

126, 127

128

129

103

104-106

107

108

109

110-112

113

114

115

116

117

130

131, 132

133

134, 135

136

137

138

139, 140

141

Pin No.

93

94

95

96

97

98-100

101

102

142, 143

144

Pin Name

VSS

NC

VDD

MADDR9

VSS

MADDR1, 8, 10

VDD

MADDR7

VSS

MADDR0, 8, 1

VDD

MADDR5

VSS

MADDR2, 4, 3

VDD

MADDR12

VSS

MADDR13

VDD

MADDR14

VSS

MADDR15-17

VDD

MADDR18

VSS

MADDR19, 20

/ROM_CS

P102

NC

VDD

P103

VDD

VSS

VDD

P104

VDD

P105

VDATA0, 1

VDD

—

O

—

O

O

—

O

O

I/O

O

—

O

—

—

O

—

O

—

O

—

—

I/O

—

I/O

O

—

I/O

—

—

—

O

—

O

I/O

—

O

—

O

O

—

Description


No Connection


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address.


Memory address. (Not used.)


Memory address. (Not used.)

Open drain signal, must be pulled-up via 4.7kW to 3.3 volts.


No Connection.









Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up, the decoder does not drive VDATA. During boot-up, the decoderuses configuration parameters to drive or 3-state VDATA.


64

167

168

169

170

171

172

159

160

161

162

163-165

166

148

149

150

151

Pin No.

145

146

147

152

153

154, 155

156

157

158

Pin Name

VDATA2

VSS

P105

VDATA3

VDD

VDATA4

VSS

VDATA5

P107

VDATA6, 7

P108

/HSYNC

/VSYNC

DA-IEC

VDD

DA-DATA0

VSS

DA-DATA1-3

DA-LRCK

DA-BCK

VDD

DA-XCK

VSS

DAI-DATA

DAI-LRCK

I/O

I/O

O

—

O

—

O

O

O

—

I/O

—

I

I

I/O

O

—

I/O

O

—

O

—

O

I/O

O

I/O

Description












Horizontal sync. The decoder begins out putting pixel data for a new horizontal line after the falling (active) edge of HSYNC.

Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical synchronization or top/bottom field notification from an external source. (VSYNC

HIGH = bottom fie

Bitstream data in IEC-1937 or PCM data out in IEC-958 format.


PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.


PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.

PCM left-right clock. Identifies the channel for each audio sample. the polarity is programmable.

PCM bit clock. Divided by 8 from DA-XCK, DA-BCK can be either 48 or 32 times the sampling clock.


Audio master frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK can be either 384 or 256 times the sampling frequency.


PCM input data, two channels. Serial audio samples relative to DAI-BCK clock.

PCM input left-right clock.

65

Pin No.

173

174

175

176

177

178

179

180

181

182

183

184

185

186-189

190

191

192

193

194

195

196

197

Pin Name

DAI-BCK

P109

CLKSEL

A_VDD

VCLK

SYSCLK

A-VSS

DVD-DATA0/CD-

DATA

VDD

DVD-DATA1/CD-

LRCK

VSS

DVD-DATA2/CD-

BCK

DVD-DATA3/CD-

C2PO

DVD-DATA4/

CDG_SDATA

PI101

VREQUEST

VSTROBE

VDD

AREQUEST

VSS

V-DACK/ASTROBE

VDD

I/O

I

I/O

I

—

I

—

I

I

—

I

—

I

I

I/O

O

—

O

—

I

I

I

—

Description

PCM input bit clock.


Clock Select: Internal = VDD, External = VSS

3.3-V analog supply voltage.

Video clock. Clocks out data on input. VDATA [7:0]. Clock is typically 27 MHz.

System clock. Decoderrequires an external 27MHz TTL oscillator. Drive with the same 27-MHz as VCK.

Analog ground for PLL.

Serial CD data. This pin is shared with DVD compressed data DVD-DATA0. ERROR

200 I Error in input data. If ERROR signal is not available from the DSP it must be grounded.


Programmable polarity 16-bit word synchronization to the decoder (right channel

HIGH). This pin is shared with DVD compressed data DVD-DATA1.


CD bit clock. Decoder acceptmultipleBCKrates. This pin is shared with DVD compressed data DVD-DATA2.

Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture on-screen until the next valid picture is decoded. This pin is shared with DVD compressed data DVD-DATA3.

DVD parallel compressed data from DVD DSP. When DVD DSP sends 32-bit words, it must write the

DVD-DATA5/CDG_VFSY MSB first. CDG-SDATA: CD+G (Subcode) Data.

DVD-DATA6/CDG_SOSI Indicates serial subcode data input.

DVD-DATA7/CDG_SCLK CDG-VSFY: CD+G (Subcode) Frame Sync. Indicates frame-start or composite synchronization input. CDG-S0S1: CD+G (Subcode) Block

Sync. Indicates block-start synchronization input. CDG-SCLK: CD+G (Subcode)

Clock. Indicates subcode data clock input or out-put.


Video request. Decoder asserts VREQUEST to indicate that the video input buffer has available space. Polarity is programmable.

Video strobe. Programmable dual mode pulse. Asynchronous and synchronous. In

Asynchronous mode, anexternal sourcepulses VSTROBE to indicate data is ready for transfer. In synchronous mode VSTROBE clocks data.


Audio request. Decoder asserts AREQUEST to indicate that the audio input buffer has available space. (Not used.)


In synchronous mode, Video data acknowledge. Asserted when DVD data is valid.

Polarity is programmable. In asynchronous mode, data strobing for audio bit stream input.


66

Pin No.

198

199

200

201

202-204

205

206

207

208

Pin Name

A-DACK

VSS

HOST&SEL

HADDR0-2

DTACKSEL

/CS

R/W

/RD

I/O

I

—

Description

Audio data acknowledge.


I

I

I

I

I

I

Pull up.

Host address bus. 3-bit address bus selects one of eight host interface registers.

Tie HIGH to select WAIT signal, LOW to select DTACK signal (Motorola 68K mode).

Host chip select. Host asserts CS to select the decoder for a read or write operation.

The falling edge of this signal triggers the read or write operation.

Read/write strobe in M mode. write strobe in I mode. Host asserts R/W LOW to select write and

Read strobe in I mode. Must be held HIGH in M Mode LOW to select Read.

67

IC, GDC25D801

53-56

57

58

59

60

61

62

63

64

36

37

38

39-45

31

32

33

34

35

46

47-52

72

73

74

75

65

66-68

69

70

71

Pin No.

1-16

17

18-21

22

23-27

28

29

30

76

77

78

79

Pin Name

DAT1-16

VSS

ADD1-4

VDD

ADD5-9

X2_MCK

VSS

MCK

VDD

RAS

UCAS

LCAS

WE

OE

SCAN_IN

TEST_SE

TEST_OUT12-6

T_SEL

TEST_OUT5-0

TEST_SEL0-3

TESTSERVO

E_SIN

E_CLK

E_ENB

E_DRB

VSS

SERVO CLK

E_SOUT

VDD

E_ST0-2

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

VSS

SENS

VDD

I

—

I

I

I

O

I

I

I

I

O

O

I

—

O

O

O

O

I

O

I/O

I/O

I/O

I/O

—

O

I/O

I/O

I/O

I/O

—

O

—

O

I

—

I

I/O

I/O

—

O

I

Description

Bi-directional data to DRAM.

Digital GND.

Address output to DRAM.

Digital power supply.

Address output to DRAM.

Master clock from oscillator for 2x decoding.

Digital GND.

Master clock from oscillator.


Row address strobe to DRAM.

Column address upper byte control strobe to DRAM.

Column address lower byte control strobe to DRAM.

Write enable signal to DRAM.

Output enable signal to DRAM.

Scan data input (Not used.)

Test mode selection (low for normal) (Connected to GND.)

Test output (Not used.)

Test selection : 0 for normal.

Test output (Not used.)

Test mode output selection.

TEST PIN (NORMAL STATE = H ) (Connected to VDD.)

SERVO DSP PGM. DOWNLOADING DATA INPUT.

SERVO DSP PGM. DOWNLOADING CLK.

SERVO DSP DOWNLOADING ENABLE.

SERVO DSP PGM. DOWNLOADING DIRECTION.

Digital GND.

SERVO DSP CLOCK INPUT.

SERVO DSP PGM. DOWNLOADING DATA OUTPUT.


SERVO DSP DOWNLOADING STATUS 0-2.

SERVO DSP GENERAL I/O: FSON (FOCUS OK INVERTING).

SERVO DSP GENERAL I/O: PSEL.

SERVO DSP GENERAL I/O: ADADDR3 (Not used.)

SERVO DSP GENERAL I/O: FKRST (Not used.)

SERVO DSP GENERAL I/O: FKSET (Not used.)

SERVO DSP GENERAL I/O: FEL (Not used.)

SERVO DSP GENERAL I/O.

SERVO DSP GENERAL I/O: DSP_SENSE.

Digital GND.

SERVO DSP INTERNAL STATUS MONITOR.


68

99

100

101

102

103

104

105

106-111

112

93

94

95

96

88

89

90

91

92

97

98

118

119

120

121

113

114

115

116

117

Pin No.

80

81

82

83

84

85

86

87

122

123

124

125

AIN3

AVDD

AIN2

AIN1

AIN0

ADCVCM

SCK

EXT_AD0-5

SELEFM

AOUT3

AOUT4

DGND

RFVCM

DVDD

AGND

VREFN

VREFP

INP

AGND

AIN4

EXCK

SQCK

C16M

DOTX

VDD

SQSO

VSS

PWMCH1

PWMCH2

Pin Name

SCLK

SDATA

XLAT

AOUT1

AOUT2

AVDD

VCM

AGND

PWMCH3

PWMCH4

PWMCH5

PWMCH6

I

O

I

I

I

I

I

—

I

I

I

—

I

O

O

—

I

—

—

I

O

—

O

O

O

O

I

I

—

O

O

O

O

O

—

I

—

I/O

I

I

I

O

Description

Serial Command CLOCK.

Serial Command DATA.

Serial Command LATCH.

TDF.

TDF.

Analog power supply for ADC.

TDF.

Analog GND for ADC.

TDF.

TDF.

Digital GND for ADC.

TDF (Connected to VREF.)

Digital power supply for ADC.

Analog GND for ADC.

TDF.

TDF.


Analog GND for ADC.


TDF.


TDF.

TDF.

TDF.


PLL clock output.

ADC data input (Not used.)

EFMDATA INPUT SELECTION (Connected to GND.)

SUB DATA REQUEST INPUT (Not used.)

SUB Q DATA REQUEST.

5.6448 MHz (DIGITAL OUT CLOCK) (Not used.)

CD DIGITAL DATA OUTPUT (Not used.)


SUB Q DATA OUTPUT.

Digital GND.

PWM CHANNEL1 (x3 CARRIER).

PWM CHANNEL1 (x3 CARRIER).

PWM CHANNEL1 (x3 CARRIER): SLED DRIVE OUTPUT.

PWM CHANNEL1 (x1 CARRIER): PDO_CTR PWM OUTPUT.

PWM CHANNEL1 (x1 CARRIER): RF_GAIN_CTL PWM OUTPUT.

PWM CHANNEL1 (x1 CARRIER): TE_BAL_CTL PWM OUTPUT.

69

145

146

147-154

155

156

157

158

159

160

139

140

141

142

134

135

136

137

138

143

144

166

167

168

169

161

162

163

164

165

Pin No.

126

127

128

129

130

131

132

133

170

171

172

173

Pin Name

DEFECT_IN_A

SI_ENC1

SI_ENC2

TZC

MIRR

MSDATAO

FOK

VDD

DEFECT

VSS

SLD_FG

C_SIG

COMP

INT1_

INT2_

VSS

INT3_

INT4_

VDD

PADCSB

ADCOMP

VDCDATA0-7

ADADDR0

DVDD

ADADDR1

DGND

AGND

VRT

AVDD

RF

VRM

VRB

MDS

MDP

OVER64

MON

LOCK

FG_M

VSS

SCAN_OUT

VDD

O

—

I

—

—

I

I

I

I

O

O

—

O

O

—

O

O

O

I

—

O

O

O

O

I

I

—

I

O

I

—

O

—

I

O

O

—

I/O

I

I

I

I

Description

EXTERNAL DEFECT INPUT PIN.

SLED ENCODER1 INPUT.

SLED ENCODER2 INPUT (Connected to GND.)

TRACK CROSS PULSE 2 INPUT.

TRACK CROSS PULSE 1 INPUT.

SERVO DSP INTENAL STATUS SERIAL OUTPUT.

INTERNAL GENERATED FOK (Focus OK) H=OK.


INTERNAL GENERATED DEFECT: H=DEFECT.

Digital GND.

SLD_FG=(SL_ENC1) XOR (SL_ENC2) (Not used.)

TRACK CROSS PULSE.

TRACK CROSS MONITOR (Not used.)

SERVO DSP INTERRUPT 1 MONITOR (MICOM COMMAND INT) (Not used.)

SERVO DSP INTERRUPT 2 MONITOR (FOCUS SERVO INT) (Not used.)

Digital GND.

SERVO DSP INTERRUPT 1 MONITOR (TRACK SERVO INT) (Not used.)

SERVO DSP INTERRUPT 1 MONITOR (Not used.)


A/D 7824 OUTPUT ENABLE (LOW ACTIVE) (Not used.)

A/D 7824 A/D CONVERTER A/D CONVERSION END STATUS (Not used.)

A/D 7824 A/D CONVERTER DATA BUS0-7. (Connected to GND.)

A/D 7824 A/D CONVERTER ADDRESS (Not used.)

Digital power supply for ADC.

A/D 7824 A/D CONVERTER ADDRESS (Not used.)

Digital GND for ADC.

Analog GND for ADC.

TDF.


TDF.

TDF.

TDF.

Spindle motor control signal (Not used.)

Spindle motor control signal (Not used.)

Not used.

Spindle motor ON/OFF control signal.

CLV servo lock signal.

TDF.

Digital GND.

SCAN DATA OUTPUT (Not used.)


70

187-193

194

195

196

197-204

205

206

207

208

Pin No.

174

175

176

177

178-183

184

185

186

PS1-7

RESET

REQ_DIVX

REQ_MPEG

MPEG1-8

SENB

SDCLK

SERR

SYNC

Pin Name

INT

RN

WN

CS

A0-5

VSS

PS0

VDD

O

O

O

O

I

I

I/O

I

O

I

—

I

—

I/O

O

I

I

I

Interrupt request to Host.

Read strobe from HOST.

Write strobe from HOST.

Chip select from HOST.

Internal register address from HOST.

Digital GND.

Bi-directional data to HOST.


Description

Bi-directional data to Host.

HARDWARE RESET.

Data request from DIVX module.

Data request from MPEG.

MPEG data.

MPEG data valid signal (low for valid).

MPEG data transfer clock.

MPEG data error detection signal (low indicates error occurred).

MPEG data sector sync. signal.

71

40

41, 42

43

44-47

48

49

50

51

52

3

4-11

12

13, 14

15

16-21

22

23-30

31

32-39

58

59

60

61

53

54

55

56

57

62

63

64

65

IC, HD6417034AFI20

Pin No.

1

2

Pin Name

Z06

DSP_INT

O

O

O

O

O

I

I

O

I

I

I/O

I

O

I

I/O

I

I/O

I

O

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

A16, A17

VCC

A18-A21

/ROM_CS

/CASH

/IOCS1

/CASL

GND

GND

D00-D07

GND

D08, D09

VCC

D10-D15

GND

A00-A07

GND

A08-A15

BCA_CODE

/RAS

DPLL_L

/MICOM_WAIT

/WR

E_SOUT

/RD

DSP_SENSE

GND

E_SIN

E_CLK

MPEG_WR

M_REQ

I/O

I/O

I/O

Description

SUB Q Code Sync Detection Signal (CD Disc Mode).

1. Interrupt request signal to µ-COM (DVD disc mode).

2. Type: a. Track miss occurred b. Search End c. New sector out start d. DSI data is ready e. New sector in f. System data is ready g. Back track jump request

GND.

Data Line 00-07.

GND.

Data Line 08, 09.

5VD.

Data Line 10-15.

GND.

Address Line 00-07.

GND.

Address Line 08-15.

GND.

Address Line 16, 17.

5VD.

Address Line 18-21.

Chip Enable For Flash ROM.

CAS for Higher Byte for DRAM.

Chip Enable to Multiplexer (IC101).

CAS for Lower Byte for DRAM.

GND.

BCA Code Input when DIVX Disc Mode ™ Not used.

RAS for DRAM.

Digital PLL IC Serial Data Latch Out.

MPEG IC Internal Status Serial Input.

Write Signal for DRAM/FlashROM/DSP/MPEG.

Servo DSP Program Downloading Data Out.

Read Signal for DRAM/FlashROM/DSP/MPEG.

Command response signal (SERVO/DSP ™ µ-COM).

GND.

Servo DSP Program Downloading Data IN.

Servo DSP Program Downloading Clock.

MPEG and Host I/F Read/Write Control Output.

Serial Communication Request to Front µ-COM.

72

69

102

103

104

105

81, 82

83-85

86

87

88

89

90

91

92

75

76

77

78

70

71

72

73

74

79

80

98

99

100

101

93

94

95

96

97

Pin No.

66

67

68

Pin Name

F_REQ

/STROBE

SENS_MCOM

I/O

I

I

I

I

I

I

I

I

I

I

—

I

—

I

I

I

I

I

—

O

I/O

I

I/O

I/O

I

I

I

I

I/O

I/O

I/O

I/O

I/O

MPEG_INT

VCC

NC

GND

X1

X2

VCC

NC

VCC

NC

MICOM_RESET

VCC

GND

VCC

VCC

SBADD

ECHO

MIC_A

DISC_A

GND

F/R

LOCK

DEFECT

FOK

GND

IIC_DATA

IIC_CLK

VCC

LOAD_FR

MSDATA0

S_DATA

S_CLK

SLD_FG

SPINDLE_FG

I/O

I/O

I/O

I/O

Description

Serial Communication Request from Front µ-COM.

Flash ROM Download I/F (Data Strobe in).

1. Servo Event detection signal input

2. Type: a. Focus Error S-curve detection b. 1 track jump completed c. 10 track jump completed d. etc

Interrupt Input from MPEG (IC301).

5VD.

NC.

GND.

Crystal (20MHz) Input.

Crystal (20MHz) Output.

5VD.

NC.

Low Active Reset Input from Front.

5VD.

GND.

5VD.

3.3VD.

SBADD (Sub Beam Add) Signal Input from RF IC ™ Not used.

DC voltage of Echo Volume Input.

Mic Audio Signal Input for Karaoke Score Function ™ Not used.

Disc Audio Signal Input for Karaoke Score Function ™ Not used.

GND.

Spindle Rotation direction Input from Spindle Motor IC.

CLV Servo Locking Signal Input from DSP IC.

DISC DEFECT DETECTION Signal Input (Active High).

FOCUS OK signal (H=OK) from DSP.

GND.

IIC Bus Data for EEPROM (IC114) and Video ENCODER.

IIC Bus Clock for EEPROM (IC114) and Video ENCODER.

5VD.

Tray Open and Close Control output.

Servo DSP IC Internal Status Serial Input.

Serial command interface port between RF or SERVO/DSP IC and µ-COM.

Sled Motor FG Input.

Input the FG Signal of Spindle Motor.

73

Pin No.

106

107

108

109

110

111

112

Pin Name

GND

RXDO

TXDO

SQSO

MODE_SW

SCKO

SQCK

I/O

I/O

I/O

I/O

I

I/O

I/O

I/O

Description

GND.

Serial Data Input from Front.

Serial Data OUT to Front.

SUB Q Data Input from Servo & DSP IC.

Program Download mode detect (Download mode is “L”).

Serial Interface Clock to Front.

SUB Q Data Request to Servo & DSP IC.

74

IC, LC866112B-5N21

24

25-31

32-40

41

42

43-52

53-56

57

58

14, 15

16

17-20

21

9

10

11

12

13

22

23

59

60-64

65

66

67

68-70

71

72

73

7

8

5

6

Pin No.

1

2

3

4

74

75

76

77

P73

G1-G7

P1-P9

VPP

VKK

P10-P19

S26-S29

S30

S31

VSS

CF1

CF2

VDD

P80

P81, P82

P83

P84-P87

MODE_SW

M_REQ

P72

P00

P01-P05

ZOOM_RST

V07

VSS

P10-P12

F_RXD

F_TXD

F_CLK

Pin Name

P35

P36

P37

PWM1

TEST1

/RES

XT1

XT2

F_REQ

M_RESET

PWR_CTL

P31

O

—

I

I

I

O

O

—

—

I

I/O

I

I

I

I

—

I

O

—

I

I

I

—

O

—

—

I/O

—

—

O

O

O

I/O

—

I

I

O

I/O

I

I

I

O

Description

Select down SW input from CN505 (SW509).

Enter SW input from SW501.

Select right SW input CN505 (SW509).

Not used.

Not used (Test port).

Reset signal input from IC501 3 pin.

Not used (Input for 32.768kHz crystal oscillation).

Not used (Output for 32.768kHz crystal oscillation).

GND.

Ceramic resonator X501 (6MHz) oscillation input.

Ceramic resonator X501 (6MHz) oscillation output.

VCC (5V).

KEY IN input from CN504.

Reserved.

Shuttle 3 line A/D input.

Not used.

“LOW” at program download mode.

Request signal (Active “LOW”) from IC108 (Main µ-COM, SH7034).

Not used.

Remocon receiver signal input.

VFD display control signal output. DIG 501 G1 to G7.

VFD display control signal output. DIG 501 P1 to P9.

VCC (5VAU).

-27V from CN503 (SMPS).

VFD display control signal output. DIG 501 P10 to P19.

Not used.

D503 option (Present at AIWA remocon model).

Not used.

Diode option input.

Not used.

GND.

Reserved.

Serial data to IC108 (Main µ-COM, SH7034).

Serial data input from IC108 (Main µ-COM, SH7034).

Serial clock input from IC108 (Main µ-COM, SH7034).

Request signal (Active “LOW”) to IC108 (Main µ-COM, SH7034).

Reset signal (Active “LOW”) to IC108 (Main µ-COM, SH7034).

Power control (Active “HIGH”) to main board.

Not used.

75

Pin No.

78

79

80

Pin Name

P32

P33

P34

I/O

I

I

I

Description

UP signal input from CN505 (SW509).

JOG signal “JSW1” input CN505 (JS500).

LEFT signal input from CN505 (SW509).

76

IC, XC9536-15VQ44C

23

24

25

26

20

21

22

27

28-30

14

15

16

17

9

10

11

12

13

18

19

36

37

38

39-43

31

32

33

34

35

7

8

5

6

Pin No.

1

2

3

4

44

Pin Name

SCART1

SCART2

TEST PIN

GND

PWR_CTL

TEST PIN

MPEG_CS

DSP_CS

TD1

TMS

TCK

PP_CS

CLOSE_SW

OPEN_SW

VCC

SENSE

GND

ZISERR

DAC_LO

DINO_CS

WR

MICOM_WAIT

MIC_ON

TDO1

GND

VCC

RF_LAT

A21-A19

MPEG_WAIT

LIMIT_SW

MICOM_RESET

EXP_W2

VCC

PWR_CTL

MPEG_ERROR

SENSE_MCOM

DO0-DO4

IOCS1

I

O

—

—

O

I

O

I

O

I

—

I

—

I

O

I

O

I

I

I

I

O

O

I/O

I

O

I

I

—

O

O

O

O

I/O

O

O

O

—

I

Description

Wide disc playback high output (16:9 mode detect).

DVD power on HIGH (HIGH signal output to SCART 8 pin, SCART enable).

For software debugging.

Ground.

Power control output to expander IC.

For software debugging.

IC301 (MPEG IC, ZIBA-3) chip select.

IC206 (DSP IC, GDC25D801) chip select.

JTAG program port for CPLD upgrade.

Software download adapter select.

Tray limit SW input (LOW is input at tray close end position).

Tray limit SW input (LOW is input at tray open end position).

VCC.

Interface signal for IC206 (DSP IC, GDC25D801).

Ground.

EDC (Error detection & correction) signal input from IC206 (DSP IC, GDC25D801).

Audio DAC latch strobe signal.

Not used.

IC108 (Main µ-COM, SH7034) bus write signal.

µ-COM WAIT signal.

Karaoke MIC input.

JTAG program port for CPLD Upgrade.

Ground.

VCC.

IC201 (RF IC, TA1254) serial interface latch signal.

IC108 (Main µ-COM, SH7034) address signal.

Wait signal from IC301. (MPEG IC, ZIBA-3)

Sled limit switch input.

µ-COM, expander reset signal input.

IC103 (Expander, 74HC374) latch strobe.

VCC.

Power control input from IC500 (Front µ-COM).

EDC (Error detection & correction) signal output to IC301 (MPEG IC, ZIBA-3).

IC206 (DSP IC, GDC25D801) interface signal to IC108 (Main µ-COM, SH7034).

IC108 (Main µ-COM, SH7034) data bus.

IC101 (CPLD, XC9536) chip select from IC108 (Main µ-COM, SH7034).

77

IC BLOCK DIAGRAM

IC, BA5983FP

IC, BA6859AFP

78

IC, KIA393F

IC, PLL1700E

79

IC, SN74AHC374PWLE

IC, TA1254F

80

MECHANICAL EXPLODED VIEW 1/1

MECHANICAL PARTS LIST 1/1

REF. NO PART NO.

KANRI

NO.

DESCRIPTION

250 S1-10R-014-3A0 CASE TOP

280 S7-21R-F12-5A0 PANEL ASSY FRONT[NO

283 S5-81R-000-7A0 TRAY DOOR ASSY

300 S4-10R-AHC-02B NI NM CORE SP-2 1 POW<EZ>

452 S3-530-51A-000 SCREW,SPECIAL

462 S3-530-46K-000 SPECIAL SCREW 3-10 B.K

463 S3-530-51B-000 SPECIAL SCREW

464 S3-530-46N-000 SPECIAL SCREW 3-8 BK

Basic color symbol

B

G

LT

R

T

WT

LM

LD

Color

Black

Green

Transparent Blue

Red

Brown

Transparent White

Metallic Blue

Dark Blue

COLOR NAME TABLE

Basic color symbol

C

H

N

S

V

Y

LL

DT

Color

Cream

Gray

Gold

Silver

Violet

Yellow

Light Blue

Transparent Orange

Basic color symbol

D

L

P

ST

W

YT

GT

Color

Orange

Blue

Pink

Titan Silver

White

Transparent Yellow

Transparent Green

81 82

MECHANISM EXPLODED VIEW 1/1

418

011

026

018

012

A02

004

418

031

428

A06

035

038

427

041

040

PU BASE

039

418

037

418

MAIN BASE

423

013

017

419

014

016

015

019

418

P.C.B

418

418

418

83 84

MECHANISM PARTS LIST 1/1

REF. NO PART NO.

KANRI

NO.

DESCRIPTION

004 S8-10H-105-5A0 CLAMP,LDM-R608 BRACKET

011 S2-10H-101-1A0 FRAME UP/DOWN

012 S0-40H-103-9B0 RUBBER F(D2)

013 S4-00H-101-0A0 LOADING BELT

014 S4-70H-112-9A0 PULLEY GEAR

015 S6-81R-102-1A0 LOADING MOTOR ASSY

016 S4-70H-113-1A0 LOADING GEAR

017 S4-30H-000-4A0 LOADING CAM

018 S4-70H-113-0A0 EMERGENCY GEAR

019 S9-31H-000-3A0 HOLDER ASSY DECK ON

026 S3-90H-102-1A0 DISC TRAY

031 S3-70H-108-5B0 SHAFT PU SUB

035 S3-70H-108-5A0 SHAFT PU MAIN

037 S6-80H-B10-24B MOTOR(MECH)

038 S9-70H-110-0A0 SPRING SKEW

039 S3-71H-100-9A0 LEAD SCREW SHAFT

040 S6-81H-102-0A0 PU FEED MOTOR ASSY

041 S0-40H-104-0B0 RUBBER R(D2)

428 SS-ZZH-101-6A0 SCREW,+2.0-3.5

A02 S8-61H-001-1A0 DISC CLAMP ASSY

A06 S4-05H-108-0B0 MECHANISM ASSY

85

931196

2–11, IKENOHATA 1–CHOME, TAITO-KU, TOKYO 110-8710, JAPAN TEL:03 (3827) 3111

Printed in Singapore

Aiwa XD-DV290K Service manual

SERVICE MANUAL

•

•

TRANS

Q901

KTC4419

SWITCHING IC

(COMPONENT SIDE)

(CONDUCTOR SIDE)

Related manuals

Table of contents

Aiwa XD-DV290K Service manual

SERVICE MANUAL

•

•

TRANS

Q901

KTC4419

SWITCHING IC

(COMPONENT SIDE)

(CONDUCTOR SIDE)

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HV-FX5200

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Aiwa

XD-DV370

Aiwa

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Aiwa

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N-06C Medias WP

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Table of contents