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XE1205
XE1205
180 MHz – 1GHz
Low-Power, High Link Budget Integrated UHF Transceiver
GENERAL DESCRIPTION
KEY PRODUCT FEATURES
• Programmable RF output power: up to +15 dBm
• High Rx sensitivity: down to -121 dBm at 1.2 kbit/s,
-116 dBm at 4.8 kbits.
• Low power: RX=14 mA; TX = 62 mA @ 15 dBm
• Can accommodate 300-1000 MHz frequency range
• Wide band operation: up to 304.7 kbit/s, NRZ coding
• Narrow band operation: 25 kHz channels for data
rates up to 4.8 kbit/s, NRZ coding; optional
transmitter pre-filtering to enable adjacent channel
power below -37 dBm at 25 kHz
• On-chip frequency synthesizer with minimum
frequency resolution of 500 Hz
• Continuous phase 2-level FSK modulation
• Incoming data pattern recognition
• Built-in Bit-Synchronizer for incoming data and clock
synchronization and recovery
• FEI (Frequency Error Indicator) with built-in AFC
• RSSI (Received Signal Strength Indicator)
• 16-byte FIFO for transmit / receive data buffering
and transfer via SPI bus
The XE1205 is an integrated transceiver operating in
the 433, 868 and 915 MHz license-free ISM (Industrial,
Scientific and Medical) frequency bands; it can also
address other frequency bands in the 180-1000 MHz
range. Its highly integrated architecture allows for
minimum external components while maintaining
design flexibility. All major RF communication
parameters are programmable and most of them can
be dynamically set. The XE1205 offers the unique
advantage
of
narrow-band
and
wide-band
communication, this without the need to modify the
number or parameters of the external components.
The XE1205 is optimized for low power consumption
while offering high RF output power and channelized
operation suited for both the European (ETSI EN 300220-1) and the North American (FCC part 15)
regulatory standards. TrueRF™ technology enables a
low-cost external component count (elimination of the
SAW filter) whilst still satisfying ETSI and FCC
regulations.
APPLICATIONS
•
•
•
•
•
•
ORDERING INFORMATION
Narrow-band and wide-band security systems
Voice and data over an RF link
Process and building control
Access control
Home automation
Home appliances interconnection
Part number
XE1205I074TRLF
(1)
Rev 10 December 2008
(1)
Temperature range
Package
-40 °C to +85 °C
VQFN48
TR refers to tape & reel.
LF refers to Lead Free package.
This device is WEEE and RoHS compliant
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1
XE1205
TABLE OF CONTENTS
1
2
3
4
4.1
4.2
4.2.1
4.2.2
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
6
6.1
6.1.1
6.1.2
6.1.3
6.2
6.3
6.4
7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
8
8.1
8.2
8.3
8.4
8.5
9
Non-conformance ........................................................................................................................................................ 3
Functional Block Diagram........................................................................................................................................... 3
Pin description............................................................................................................................................................. 4
Electrical Characteristics ............................................................................................................................................ 5
Absolute Maximum Operating Ranges .......................................................................................................................... 5
Specifications................................................................................................................................................................. 5
Operating Range ........................................................................................................................................................... 5
Electrical Specifications ................................................................................................................................................. 5
Description ................................................................................................................................................................... 7
Data Operation Modes................................................................................................................................................... 7
Receiver section ............................................................................................................................................................ 8
LNA & Receiver modes ................................................................................................................................................. 8
Interrupt signal mapping ................................................................................................................................................ 8
Receiver in continuous mode......................................................................................................................................... 8
DATA pin in bidirectional or unidirectional mode (continuous mode only) ................................................................... 14
Receiver in buffered mode........................................................................................................................................... 14
Additional narrowband filter bandwidths ...................................................................................................................... 17
Transmitter section ...................................................................................................................................................... 18
Output power ............................................................................................................................................................... 18
Transmitter in continuous mode................................................................................................................................... 18
Transmitter in buffered mode....................................................................................................................................... 20
Frequency synthesizer................................................................................................................................................. 21
Clock Output for an external processor ....................................................................................................................... 21
Highest Bit RATES: example of 304.7 kbit/s operation .......................................................................................... 22
Registers settings ........................................................................................................................................................ 22
Bitrate (BR) and frequency deviation (fdev) ................................................................................................................. 22
Rx filter ........................................................................................................................................................................ 22
Tx filter......................................................................................................................................................................... 22
Hardware settings........................................................................................................................................................ 23
Operation ..................................................................................................................................................................... 23
Typical performance .................................................................................................................................................... 23
Serial interface definition and principle of operation ............................................................................................. 24
Serial Control Interface ................................................................................................................................................ 24
Chip configuration via SPI_CONFIG interface ............................................................................................................. 25
Data transmission and reception via SPI_DATA interface. .......................................................................................... 26
Configuration and status registers ............................................................................................................................... 28
Configuration register: general description .................................................................................................................. 28
MCParam configuration register (main configuration parameters)............................................................................... 29
IRQParam configuration register (IRQ parameters)..................................................................................................... 30
TXParam configuration register (transmitter configuration parameters) ...................................................................... 31
RXParam configuration register (receiver configuration parameters) .......................................................................... 31
Pattern register ............................................................................................................................................................ 33
OSCParam configuration register (oscillator parameters) ........................................................................................... 34
ADParam configuration register (additional settings)................................................................................................... 35
Operating Modes ......................................................................................................................................................... 36
XE1205 switching time using SPI_CONFIG interface.................................................................................................. 36
XE1205 switching time using SW(1:0) pins. ................................................................................................................ 38
Selection of the reference frequency ........................................................................................................................... 38
Clock output interface .................................................................................................................................................. 39
Default settings at power-up ........................................................................................................................................ 39
Pad configuration versus chip modes .......................................................................................................................... 40
Application information ............................................................................................................................................ 41
Matching network of the receiver ................................................................................................................................. 41
Matching network of the transmitter............................................................................................................................. 41
VCO tank ..................................................................................................................................................................... 44
Loop filter of the frequency synthesizer ....................................................................................................................... 45
Reference crystal for the frequency synthesizer .......................................................................................................... 46
Packaging information .............................................................................................................................................. 47
© Semtech 2008
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2
XE1205
The XE1205 single-chip solution is an integrated circuit intended for use as a low cost FSK transceiver to establish a
frequency-agile, half-duplex, bi-directional RF link, with non-return to zero data coding. The device is available in a VQFN
48 package and is designed to provide a fully functional multi-channel FSK transceiver. It is intended for applications in the
433 MHz and 868 MHz European bands and the North American 915 MHz ISM band. The single chip transceiver operates
down to 2.4V. Its ability to operate with 25 kHz channel spacing makes it compliant with requirements of ETSI EN300 2201 and makes the XE1205 ideal for automatic meter reading and alarms.
1
NON-CONFORMANCE
Please note early version lot codes whose date-codes start with N3K, N4K and N5K (except N5K3760, N5K3760A,
N5K3760B and N5K6993) exhibit a non-conformance to specification. The non-conformance affects the FIFO buffer
described in section 5.2.5. Please use the FIFO in this product only in conjunction with the Technical Note TN1205.01
(available www.semtech.com). All other date-codes are in conformance with the specification.
IAMP
VSS
VSSA
QAMP
IAMP
VDD
VDDA
VSSP2
VSSP
VSSB
VSSF
VSSD
VDDP
VDDB
VDDF
FUNCTIONAL BLOCK DIAGRAM
VDDD
2
IAMP
IRQ_0
IRQ_1
FAMP
LPF
BBAMP
MOSI
LIM
MISO
MATCHING
NETWORK
RFA
LNA
DEMOD
SCK
BITSYNC
RFB
NSS_DATA
FAMP
LPF
BBAMP
LIM
PATTERN
MATCHING
CHIP
INTERFACE
NSS_CONFIG
SW(0)
SW(1)
RSSI
PHASE
SHIFTER
LO_BUF
DATA
FIFO
IREF
FEI
DIVCTL
MMOD
DIVIDER
modulator
/n Synthesizer
Data shaping
filter
CLKXTAL
XE1205
RFOUT
MATCHING
NETWORK
PA
CH PUMP
PFD
VCO
OSCILLATOR
/n
CLOCK OUT
IREF
POR
TKA
VCO
TANK
TKB
LFB
XTA
LOOP
FILTER
XTB
CLKOUT TSUPP TMOD(3:0)
POR
XTAL
Figure 1: XE1205 block diagram.
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3
XE1205
3
PIN DESCRIPTION
PIN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NAME
EPAD
SW(0)
SW(1)
NC
NC
RFA
RFB
VSSP2
VSSP2
RFOUT
VDDP
VSSP
VDDF
VSSF
TKA
VSSF
TKB
VSSF
LFB
VDDD
VSS
NSS_CONFIG
NSS_DATA
VDD
IRQ_0
IRQ_1
DATA
CLKOUT
MISO
MOSI
SCK
XTA
VSSA
XTB
VDDA
POR
NC
TIBIAS
TSUPP
VDDA
VSSA
QAMP
IAMP
TMOD(3)
TMOD(2)
TMOD(1)
TMOD(0)
NC
NC
I/O
I/O
I
I
O
I/O
I/O
I/O
I
I
O
O
I/O
O
O
I
I
I/O
I/O
I/O
I/O
O
O
I/O
I/O
I/O
I/O
DESCRIPTION
Pad below package (should be grounded)
Transmit/Receive/Stand-by/Sleep Mode Select
Transmit/Receive/Stand-by/Sleep Mode Select
Not connected (should be grounded)
Not connected (should be grounded)
RF Input
RF Input
Power Amplifier Ground
Power Amplifier Ground
RF Output
Power Amplifier Supply Voltage
Power Amplifier Ground
Second HF Analog Supply voltage
Second HF Analog Ground
VCO Tank
Second HF Analog Ground
VCO Tank
Second HF Analog Ground
PLL Loop Filter
HF Digital Supply Voltage
LF Digital Ground
SPI SELECT CONFIG
SPI SELECT DATA (DATA_IN in continuous mode)
LF Digital Supply Voltage
Interrupt (refer to chapter 5.2.5 for mapping options)
Interrupt(refer to chapter 5.2.5 for mapping options)
Data input and output (output only in continuous mode)
Output clock at reference frequency divided by 2, 4, 8, 16, 32
SPI Master Input Slave Output
SPI Master Output Slave Input
SPI CLOCK
Ref Xtal / Input of external clock
LF analog ground
Reference Xtal
LF Analog Supply Voltage
Not used (should not be connected)
Not connected (should be grounded)
Test pin (should be grounded in normal operation)
Test pin (should be grounded in normal operation)
LF Analog Supply Voltage
LF analog ground
Output of Q-Ch low-pass filter
Output of -ChI low-pass filter
Test pin (should be grounded in normal operation)
Test pin (should be grounded in normal operation)
Test pin (should be grounded in normal operation)
Test pin (should be grounded in normal operation)
Not connected (should be grounded)
Not connected (should be grounded)
Table 1: Pin description
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4
XE1205
4
ELECTRICAL CHARACTERISTICS
4.1 ABSOLUTE MAXIMUM OPERATING RANGES
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Symbol
Description
Min.
Max.
Unit
VDDmax
Supply voltage
-0.5
3.9
V
Tmr
Storage temperature
Receiver input level
-55
125
5
°C
ML
dBm
Table 2: Absolute Maximum Operation Ranges
The device is ESD sensitive and should be handled with precaution.
4.2
4.2.1
SPECIFICATIONS
Operating Range
Symbol
Description
Min.
Max.
Unit
VDDop
Supply voltage
2.4
3.6
V
Trop
Temperature
-40
85
°C
Clop
Load capacitance on digital ports
-
25
pF
Table 3: Operating Range
4.2.2
Electrical Specifications
The table below gives the electrical specifications of the transceiver under the following conditions:
Supply Voltage = 3.3V, temperature = 25 °C, 2-level FSK without pre-filtering, fc = 915 MHz, Δf = 5 kHz,
Bit rate = 4.8 kbit/s, BWSSB = 10 kHz, BER = 0.1% (at the output of the bit synchronizer), matched impedances,
environment as defined in section 8, unless otherwise specified.
Symbol
Description
Conditions
Min Typ
Max
Unit
IDDSL
Supply current in sleep mode
0.2
1
uA
Quartz oscillator (39 MHz)
IDDST
Supply current in standby mode
0.85
1.10
mA
enabled
IDDR
IDDT
Supply current in receiver mode
Supply current in transmitter mode
RFOP = 5 dBm
RFOP = 15 dBm
-
14
33
62
16.5
40
75
mA
mA
mA
RFS
RF sensitivity
Mode A
Mode B
-
-116
-102
-113
-99
dBm
dBm
RFS_12
RF sensitivity at 1.2 kbit/s
FDA
CCR
IIP3
Mode A
Mode B
Programmable
Frequency deviation
Co-channel rejection
Input intercept point (from LNA input funw = fLO + 1 MHz and
fLO + 1.995 MHz
to base-band filter output)
1
-13
-121
-107
-10
-118
-104
255
-
dBm
dBm
kHz
dBc
Mode A
Mode B
-37
-21
-
-33
-18
10
20
-
dBm
dBm
kHz
kHz
-
40
-
kHz
-
200
-
kHz
BW
Base band filter bandwidth (SSB)
Programmable (1)
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5
XE1205
Symbol
ACR_25
ACR_50
BR
RFOP
ACP
Description
Conditions
Receiver adjacent channel rejection funw = fLO + 25 kHz single tone
Pw=-110 dBm, mode A
ratio at 25 kHz
BW (SSB) = 10 kHz
BW (SSB) = 8 kHz (2)
Receiver adjacent channel rejection funw = fLO + 50 kHz single tone
Pw=-110 dBm, mode A
ratio at 50 kHz
Programmable
Bit rate
Programmable
RF output power
RFOP1
RFOP2
RFOP3
RFOP4
Transmitter adjacent channel power Pre-filter enabled
(RFOP3 mode)
(measured at 25 kHz offset)
FR
Measurement conditions as
defined by EN 300 220-1 V1.3.1
Programmable
Synthesizer frequency range
TS_SRE
TS_STR
TS_FS
Receiver wake-up time
Transmitter wake-up time
Frequency synthesizer wake-up
time
TS_RE
Receiver wake-up time
TS_TR
Transmitter wake-up time
TS_RFSW Receiver recovery time when
switching between 2 channels
TS_TFSW Transmitter recovery time when
switching between 2 channels
TS_RSSI RSSI wake-up time
TS_OS
Quartz oscillator wake-up time
Quartz oscillator enabled
Quartz oscillator enabled
Quartz oscillator enabled
Frequency synthesizer enabled
Frequency synthesizer enabled
Between 2 channels at 1 MHz
from each other
Between 2 channels at 1 MHz
from each other
Receiver enabled
Fundamental
rd
3 overtone
Receiver enabled
Fundamental or third harmonic
Exact step is XTAL / 77’824
Mode A(5), low range:VTHR1
VTHR2
VTHR3
Mode A, high range:VTHR1
VTHR2
VTHR3
TS_FEI
XTAL
FSTEP
VTHR
FEI wake-up time
Quartz oscillator frequency
Frequency synthesizer step
Equivalent input thresholds
of the RSSI
SPR
VIH
VIL
VOH
VOL
Spurious emission in receiver mode
Digital input level high
Digital input level low
Digital output level high
Digital output level low
(3)
% VDD
% VDD
% VDD
% VDD
Min
Typ
Max
Unit
-
20
30
40
-
dBc
dBc
dBc
1.2
-
304.7(4)
kbit/s
-3
+2
+7
+12
-
0
+5
+10
+15
-
-37
dBm
dBm
dBm
dBm
dBm
433
863
902
-
700
250
200
435
870
928
850
350
250
MHz
MHz
MHz
us
us
us
-
500
100
700
600
150
us
us
us
-
150
250
us
75
75
-
1
7
2/BR
39
500
-110
-105
-100
-95
-90
-85
-65
-
1.5
2
25
25
ms
ms
ms
ms
MHz
Hz
dBm
dBm
dBm
dBm
dBm
dBm
dBm
%
%
%
%
Table 4: Electrical Specifications
(1)
(2)
(3)
(4)
(5)
Additional bandwidths can be selected with special settings described in section 7.2.8.
With additional bandwidth configuration register settings as described in sections 5.2.6 and 7.2.8.
SPR strongly depends on the design of the application board and the choice of the external components. Values down to -70 dBm can be
achieved with careful design.
304.7 kbit/s achievable with additional register settings as described in section 6. The 304.7kpbs max bit rate is guaranteed by validation.
The max bit rate guaranteed by production test is 152.3 kbit/s
RSSI also available in mode B with higher thresholds as described in section 5.2.3.4
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6
XE1205
5
DESCRIPTION
The XE1205 is a direct conversion (Zero-IF) half-duplex data transceiver. It includes receiver, transmitter, frequency
synthesizer and control logic. The circuit is intended primarily for operation in the following three ISM frequency bands
433 MHz, 868 MHz, and 915 MHz with a same 39MHz reference crystal and uses 2-level FSK modulation.
Operation of the XE1205 over the frequency range 180 MHz - 1000 MHz beyond the ISM bands described above can be
achieved by modifying the reference oscillator crystal frequency. Please contact Semtech for more details.
The XE1205 is programmed by a microcontroller through the 3-wire fully-compatible SPI serial bus (MOSI, MISO, and
SCK) to write to and read from the configuration registers.
The circuit consists of the following main functional blocks:
The receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver comprises
a low-noise amplifier, down-conversion mixers, baseband filters, baseband amplifiers, limiters, demodulator and bit
synchronizer. The bit synchronizer transforms the data output of the demodulator into a glitch-free bit stream DATAOUT
and synchronized clock DCLK. This may be easily used to sample the DATAOUT signal with minimal external processor
overhead. In addition, the receiver includes a Received Signal Strength Indicator (RSSI) function and a Frequency Error
Indicator (FEI) function that provides an indication of the local oscillator frequency error. A pattern recognition function
may be used to detect a user-programmable reference word in the incoming bit stream. The bandwidth of the base-band
filters, the frequency deviation of the expected incoming FSK signal as well as the bit rate of the received data signal are
all user-programmable. The receiver also embeds an automatic frequency offset cancellation to compensate local
oscillator drifts due to XTAL.
The transmitter performs the modulation of the carrier by an input baseband data signal and the transmission of the
modulated signal. The frequency synthesizer is modulated directly. The modulated signal is then amplified by the on-chip
RF power amplifier. The output power is user-programmable to one of four possible values. The frequency deviation and
the bit rate for the transmit signal are the same as those programmed for the receiver section. User-defined pre-filtering
should be enabled to ensure compliance with the requirements of ETSI EN 300 220-1 regarding transmission at 25 kHz
channel spacing.
The frequency synthesizer generates the local oscillator (LO) signal for the receiver section as well as the FSK
modulated signal for the transmitter section. The core of the synthesizer is implemented with a PLL structure. The
frequency is user-programmable with a frequency resolution of approximately 500 Hz in the 433 MHz, 868 MHz and 915
MHz ISM frequency bands. This section includes a crystal oscillator whose signal is the reference for the PLL. This
reference frequency is divided by 2, 4, 8, 16, or 32 and is made available at the CLKOUT pin to serve as a clock signal
for an external processor.
The control block generates the control signals according to the setting in its set of configuration registers.
The service block performs all the necessary functions for the circuit to work properly, including the internal voltage and
current sources.
5.1 DATA OPERATION MODES
The XE1205 is user-programmable between two modes of operation:
Continuous mode: each bit transmitted or received is accessed directly at the DATA input/output pin.
Buffered mode: a 16-byte FIFO is used to store each data byte transmitted or received. This data is written to/read from
the FIFO via the SPI bus. It reduces processor overhead.
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7
XE1205
5.2 RECEIVER SECTION
The XE1205 is set to receive mode when MCParam_Select_mode is low by setting MCParam_Chip_mode(1:0) to “01”.
If MCParam_Select_mode is high the XE1205 is set to receive mode by setting SW(1:0) to “01”.
5.2.1
LNA & Receiver modes
The LNA of the receiver has two programmable operation modes: the high sensitivity mode, Mode A, for reception of
weak signals; and the high linearity mode, Mode B, for strong signals. The operation mode is defined by the value of the
Rmode bit in RXParam_Rmode configuration register.
Mode A: High sensitivity mode, RFS approximately 13dB better than in Mode B (see 4.2.2, RFS parameter)
Mode B: High Linearity mode, IIP3 approximately 15dB higher than in Mode A (see 4.2.2, IIP3 parameter)
5.2.2
Interrupt signal mapping
In receiver mode, two lines are dedicated to interrupt information. The interrupt pins are IRQ_0 and IRQ_1.
IRQ_0 has 3 selectable sources. IRQ_1 has 2 selectable sources. The two following tables summarize the interrupt
management.
IRQParam_RX_irq_0
00
01
10
11
00
01
10
11
MCParam_Buffered_mode
0
0
0
0
1
1
1
1
IRQ_0
Output
Output
Output
Output
Output
Output
Output
Output
IRQ_0 Interrupt source
Pattern
RSSI_irq
Pattern
Pattern
No interrupt available
Write_byte
/fifoempty
Pattern
Table 5: IRQ_0 interrupt sources in receive mode.
IRQParam_RX_irq_1
00
01
10
11
00
01
10
11
MCParam_Buffered_mode
0
0
0
0
1
1
1
1
IRQ_1
Output
Output
Output
Output
Output
Output
Output
Output
IRQ_1 Interrupt source
DCLK
DCLK
DCLK
DCLK
No interrupt available
Fifofull
RSSI_irq
RSSI_irq
Table 6: IRQ_1 interrupt sources in receive mode.
5.2.3
Receiver in continuous mode
In this mode, the receiver has two output signals indicating recovered clock DCLK and recovered NRZ bit DATA. DCLK
is connected to output pin IRQ_1 and DATA is connected to pin DATA configured in output mode. The bit synchronizer
controls the recovered clock signal, DCLK. If the bit synchronizer is enabled by setting the bit /RXParam_Disable_bitsync
to “0” (default value), the clock recovered from the incoming data stream appears at DCLK.
The function of the bit synchronizer is to remove glitches from the data stream and to provide a synchronous
clock at DCLK. The output DATA is valid at the rising edge of DCLK. The following diagram shows the receiver
chain operating in this mode
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8
XE1205
If the bit synchronizer is disabled, the DCLK output is held low and the raw demodulator output appears at DATA.
.
RXParam_Disable_bitsync
1
I_lim
Q_lim
data
FSK
DEMODULATOR
DATA
0
BIT
SYNCHRONIZER
data
IRQ_1(DCLK)
dclk
RXParam_Pattern
IRQParam_Rx_irq_0(1:0)
PATTERN
MATCHING
RXParam_RSSI
pattern
IRQ_0
RSSI
RSSI_irq
Figure 2: Receiver chain in continuous mode
5.2.3.1 Demodulator in continuous mode
The demodulator section comprises FSK demodulator, bit synchronizer, and Pattern Recognition blocks.
Data from the FSK baseband limited signals I_lim and Q_lim is first demodulated before passing to the bit synchronizer.
If the end-user application requires direct access to the output of the demodulator, then the RXParam_Disable_bitsync
bit must be set high. In this case the demodulator output is directly connected to the DATA pin and the IRQ_1 pin
(DCLK) is set to low.
For best operation of the demodulator it is recommended the modulation index β of the input signal meets the following
condition:
β =
2 Δf
BR
≥2
where Δf is the frequency deviation and BR the bit rate.
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9
XE1205
5.2.3.2 Bit synchronizer in continuous mode
The raw output signal from the demodulator may contain jitter and glitches. The bit synchronizer converts the data output
of the demodulator into a glitch-free bit-stream DATA and generates a synchronized clock DCLK to be used for sampling
the DATA output (see below). DCLK is available on pin IRQ_1 when the chip operates in continuous mode.
DATA (NRZ)
DCLK
Figure 3: Bit synchronizer timing diagram
For proper operation, in addition to the requirement for the modulation index defined in Section 5.2.3.1, the Bit
Synchronizer must first receive three bytes of alternating logic value preamble, i.e. “0101” sequences. After this startup
phase, the rising edge of DCLK signal is centered on the demodulated bit. Subsequent data transitions will preserve this
centering.
This has two implications:
• If the Bit Rates of Transmitter and Receiver are known to be the same, the XE1203F will be able to receive an
infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction.
• If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the
BitSync can withstand can be estimated as:
Number of bits = 0.5⋅
BR
ΔBR
This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily achievable
(crystal tolerance is in the range of 50 to 100 ppm). It is recommended that the bit rate accuracy be better than ±5% (3%
for Konnex mode operation).
The bit synchronizer is enabled by default. It is controlled by RXParam_Disable_bitsync. If the bit synchronizer is
disabled the output of the demodulator is directed to DATA and the DCLK output (IRQ_1 Pin in continuous mode) is set
to ‘0’.
The received bit rate is defined by the value of the MCParam_Br(6:0) configuration register, and is calculated as follows:
Bit rate =
152.34e3
where int(x) is the integer value of the unsigned binary representation of x.
int(Br(6 : 0)) + 1
For the Konnex standard operation, the bit rate is fixed at 32.768 kbit/s. The bit synchronizer is automatically configured
with the right bit rate value if the MCParam_Knx configuration bit is set high.
If needed, it is possible to select intermediate bit rates by changing the Over-Sampling Ratio (OSR) of the bit
synchronizer, whose default value is 32. The latter can be superseded by setting high the register TParam_Chg_OSR. In
this case, the bit rate becomes:
Bit rate =
152.34e3
32
,
⋅
int(Br(6 : 0)) + 1 int(OSR(7 : 0)) + 1
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XE1205
where OSR(7:0) is the content of the register; TParam_OSR(7:0) as described in section 7.2.8.
For a correct operation of the bit synchronizer, the value of this register must be higher or equal to 15 and
(int(OSR)+1) * Bit_rate should be inferior or equal to 4.87MHz.
5.2.3.3 Pattern recognition block in continuous mode
In receive mode this feature is activated by setting the RXParam_Pattern configuration register bit to high. The
demodulated signal is compared with a pattern stored in the Reg_pattern(31:0) registers. The PATTERN signal (mapped
to output pin IRQ_0) is driven by the output of this comparator and is synchronized by DCLK. It is set to high when a
matching condition is detected, otherwise set to low. PATTERN output is updated at the rising edge of DCLK. The
number of bits used for comparison is defined in the RXParam_Psize(1:0) register and the number of tolerated errors for
the pattern recognition is defined in the RXParam_Ptol(1:0) register. Figure 4, illustrates the pattern matching process.
DATA
(NRZ)
Bit N-x =
Reg_pattern[x]
Bit N-1 =
Reg_pattern[1]
Bit N =
Reg_pattern[0]
DCLK
PATTERN
Figure 4: Pattern matching operation.
Note: The pattern recognizer is available only if the bit synchronizer is enabled.
5.2.3.4 RSSI in continuous mode
This function provides a Received Signal Strength Indication based on the signal level at the output of the base-band
filter. To activate this function, the bit RXParam_RSSI must be set to “1”. When activated, the 2-bit status information is
stored in register RXParam_RSSI_OUT(1:0) and may be read through the serial control interface. The meaning of this
status information is given in the table below, where VRFFIL is the differential amplitude of the equivalent input RF signal
when the receiver is operated in mode A. The thresholds VTHRi are at the output of the base-band filter divided by the
gain between the input of the receiver and this output. When operated in mode B, equivalent VTHRi thresholds are
shifted 15dBm higher.
RXPARAM_RSSI_out(1:0)
00
Description
VRFFIL ≤ VTHR1
01
VTHR1 < VRFFIL ≤ VTHR2
10
VTHR2 < VRFFIL ≤ VTHR3
11
VTHR3 < VRFFIL
Table 7: RSSI status description
The operating range of the RSSI measurement may be changed by programming the RXParam_RSSI_range bit; in this
way two ranges with three VTHRi values may be selected. An additional way to increase RSSI operating range is to
combine modes A and B thresholds. One could then cover input signals ranging from -110dBm (VTHR1, low range,
mode A) up to -70dBm (VTHR3, high range, mode B)
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XE1205
The time diagram of an RSSI measurement is given in Figure 5. When the RSSI function has been activated the signal
strength is periodically measured and the result is stored in RSSI_out_int; this result is transferred to the register
RXParam_RSSI_out(1:0) each time this register is read via the SPI interface. TS_RSSI is the wake-up time required
after the function has been activated to get a valid result and its value is given in section 4.2.2. TS_RSSIM is the period
between two successive measurements and its value depends on the selected frequency deviation (100 μs for Δf > 20
kHz, 200 μs for 10 kHz < Δf ≤ 20 kHz, 300 μs for 7 kHz < Δf ≤ 10 kHz, 400 μs for 5 kHz < Δf ≤ 7 kHz, and 500 μs Δf ≤ 5
kHz).
RXParam_RSSI
Read RSSI
NSS_CONFIG
TS_RSSI
RSSI_out_int
Read RSSI
TS_RSSIM
val1
xxx
val2
val3
val4
0
saout_rssi
RXParam_RSSI_out
xxx
val1
val4
Figure 5: RSSI measurement timing diagram
Saout_rssi is internally generated during a read sequence of RXParam_RSSI_out register.
The RSSI block can also be used in interrupt mode by setting the bit IRQParam_RSSI_int to 1. When RSSI_out_int is
equal or greater than a predefined value stored in IRQParam_RSSI_thr(1:0), the signal IRQParam_RSSI_signal_detect
(can be read in the Configuration register) goes high and an interrupt signal RSSI_irq is generated. This interrupt signal
can be used by a microcontroller if IRQParam_RX_irq_0 is set to “01” (see table 5).The interrupt is cleared by writing a 1
to the bit IRQParam_RSSI_signal_detect. If the bit IRQParam_RSSI_int remains high, the process starts again. The next
figure shows the timing diagram of RSSI in interrupt mode.
IRQParam_RSSI_int
RSSI_out_int
00
00
00
10
10
00
00
00
00
00
11
10
00
10
10 11
00
IRQParam_RSSI_signal_detect
IRQParam_RSSI_thr = “10”
Clear interrupt
RSSI_irq
Figure 6: RSSI generating interrupt signal when detecting a threshold
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XE1205
5.2.3.5 Frequency Error Indicator in continuous mode – FEI
The block is switched ON by writing bit RXParam_FEI to ‘1’.This function provides information about the frequency error
of the local oscillator compared with the input carrier frequency and can be used to implement an external AFC. The
condition on the modulation index for proper behavior of the FEI function is:
β=
2 ⋅ Δf
BR
≥ 2,
Where Δf is the frequency deviation and BR is the bit rate.
The time diagram of an FEI measurement is given in the next figure. When the FEI block has been woken up and is
ready, and as long as the block is kept on, the frequency error is measured and the current result of the measurement is
loaded in the register RXParam_FEI_out(15:0) each time registers 12 is read. TS_FEI is the time required for the first
evaluation to be completed after the block has been started up and its value is given in section 4.2.2. Since the contents
of the configuration register is validated at the rising edge of the enable signal NSS_CONFIG, the FEI block is actually
started up at this time.
RXParam_FEI
Read RSSI
NSS_CONFIG
fei_out_int
TS_FEI
TS_FEI
XXX
Read RSSI
val1
val2
val3
val4
val5
val6
0
saout_fei
RXParam_FEI_out
val2
0
val5
Figure 7: Timing diagram of an FEI measurement
To guarantee proper behavior of the FEI, the operation must be done when a preamble as defined in section 5.2.3.1 is
received, and the sum of the frequency offset and the signal bandwidth (single sided) must be lower than the base band
filter bandwidth (single sided). That is:
Foffset + SignalBW < FilterBW.
Where foffset is the difference between the carrier frequency and the LO frequency, SignalBW is the signal bandwidth
(single side) equal to the sum of the bit rate divided by 2 and the frequency deviation (BR/2 + DF), and FilterBW is the
channel filter bandwidth defined by RXParam_BW(1:0) parameters.
The frequency error can be calculated by the following formula:
The frequency error = 500*int(FEI_out(15:0)) in Hz
Where int(x) is the integer value of the signed binary representation of x.
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XE1205
5.2.3.6 Frequency Error Correction
XE1205 offers two possibilities to correct the RF frequency error either by using FEI block with external microcontroller
setting the corrected LO_Frequency or by using the internal Automatic Frequency error Cancellation (AFC).
When using FEI block, RXParam_FEI_out(15:0) can directly be subtracted to the register MCParam_Freq_lo(15:0)
without further calculation by a microcontroller since the PLL step is 500 Hz i.e. RXParam_FEI_out (15:0) represents the
number of step needed to compensate the frequency error .
Saout_fei is internally generated during a read sequence of register 12 in the same way as saout_rssi (refer to Figure 7).
To use AFC block, FEI block should be switched on by writing bit RXParam_FEI to ‘1’ then AFC should be started by
writing bit RX_Param:AFC_start to ‘1’. The LO_frequency error cancellation is effective providing bit RXParam_disable is
written to ‘0’ .Refer to previous chapter to guarantee proper behaviour of the FEI. RXParam_AFC_OK status register is
automatically set to ‘0’ when AFC is completed. RXParam_AFC_overflow will be automatically set to ‘1’ in case the
frequency error is too high to be automatically cancelled.
5.2.4
DATA pin in bidirectional or unidirectional mode (continuous mode only)
The DATA pin is bi-directional by default, and is used in both transmit and receive modes. In receive mode, DATA
represents demodulated received data. In transmit mode baseband data is applied to this pin.
Some applications may require a separate input and output for transmitted and received data respectively. In this case
the MCParam_Data_unidir configuration register bit must be set to ‘1’. The DATA pin is then set permanently to an
output for received data, and NSS_DATA is used as the input.
5.2.5
Receiver in buffered mode
In this mode, the output of the bit synchronizer, i.e. the demodulated and resynchronized signal and the clock signal
DCLK are not sent directly to the output pins DATA and IRQ_1 (DCLK). These signals are used to store the
demodulated signal by packet of 8 bits in a 16 bytes FIFO. The following figure shows the receiver chain in this mode.
The FSK demodulator, bit synchronizer and pattern matching block work as described in section 5.2.2 but they are used
with two additional blocks, FIFO and SPI.
When the chip is in receive mode and the MCParam_Buffered_mode bit is set to high then all the blocks described
above are automatically enabled. In a normal communication frame the data stream comprises a 24 bit preamble,
pattern (refer to section 5.2.3.3) and the data. Upon receipt of a recognized pattern, the receiver recognizes the start of a
frame, strips off the preamble and pattern, then fills the FIFO with payload data to the microcontroller. This automated
data recovery reduces the overhead for the host controller.
The IRQParam_Start_fill bit determines how the FIFO is filled:
If IRQParam_Start_fill is low, data only fills the FIFO subject to a correct pattern match. Data is shifted into the pattern
recognition block which continuously compares the received data with the contents of the Reg_pattern(31:0)
configuration register. If a match occurs a start sequence is detected, and the internal output of the pattern matching
block is asserted for one bit length and the IRQParam_Start_detect bit is also asserted. This internal signal may be
mapped to the IRQ_0 output using interrupt signal mapping (please refer to section 5.2.2). Once a pattern match has
occurred, the pattern recognition block will remain inactive until IRQParam_Start_detect is re-asserted.
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XE1205
/RXParam_Disable_bitsync
= ‘0’
Q_lim
FSK
I_lim DEMODULATOR
BIT
SYNCHRONIZER
RXParam_Pattern
= ‘1’
PATTERN
MATCHING
data
dclk
Shift reg
Fifowrite
byte
8
pattern
write_byte
IRQ_0
/fifoempty
FIFO
RXParam_RSSI
Fifofull
IRQ_1
8
Fiforead
RSSI_irq
Load_spi
RSSI
Fifoout
SPI
DATA
regspidata
MOSI
MISO
SCK
NSS_DATA
.
Figure 8: Receiver chain in buffered mode
If IRQParam_Start_fill is high, FIFO filling is initiated by asserting IRQParam_Start_detect.
Once sixteen bytes have been written to the FIFO the IRQParam_Fifofull signal is asserted. Data should then normally
be read out. If no action is taken the FIFO will overflow and subsequent data will be lost. If this occurs the
IRQParam_Fifooverrun bit is set. The IRQParam_Fifofull signal can be mapped to pin IRQ_1 as an interrupt for a
microcontroller if IRQParam_RX_irq_1 is set to “01” (please refer to section 5.2.2).
To recover from an overflow situation a ‘1’ must be written to IRQParam_Fifooverrun; this clears the contents of the
FIFO, resets all FIFO status flags and re-initiates pattern matching (only when an overrun has occurred).
In order to clear the FIFO in reception, a “1” should be written in IRQParam_start_detect (bit 6 add 6).
Pattern matching can also be re-initiated during a FIFO filling sequence by writing a ‘1’ to IRQParam_Start_detect.
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XE1205
data
“noisy” data
preamble
c
pattern
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11 b12 b13 b14 b15
b16
pattern
/fifoempty
fifofull
Fifooverrun
(flag)
write_byte
FIFO
15
0
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
Figure 9: Start detection and FIFO filling
The FIFO filling process is shown in detail in Figure 9. As the first byte is written into the FIFO the signal /fifoempty goes
high indicating that at least one byte is present. The microcontroller can then read the contents of the FIFO via the SPI
interface. Once all data have been read from the FIFO then /fifoempty goes low. Once the last bit of the sixteenth byte
has been written into the FIFO then the signal Fifofull is asserted; data should be read before the next byte is received.
This is illustrated in Figure 10.
Completion of FIFO filling
DCLK
DATA
Byte 14
Byte 15
Byte 16
Byte 17
PATTERN
Write_byte
/Fifoempty
Fifofull
IRQParam_Fifooverrun
Figure 10: Completion of FIFO filling
The /fifoempty signal can be used as an interrupt signal for a microcontroller by mapping to pin IRQ_0 if
IRQParam_RX_irq_0 is set to “10” (please refer to section 5.2.2). Alternatively, the WRITE_BYTE signal may also be
used as an interrupt if IRQParam_RX_irq_0 is set to “01”.
5.2.5.1 Demodulator in buffered mode
Demodulation in buffered mode occurs in the same way as in continuous mode (section 5.2.3.1). Received data is
directly read from the FIFO and the DATA pin is not used.
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XE1205
5.2.5.2 Bit synchronizer in buffered mode
In buffered mode the bit synchronizer is automatically enabled (DCLK is not externally available).
5.2.5.3 Pattern recognition block in buffered mode
In buffered mode the pattern recognition block is automatically enabled. The PATTERN signal may be mapped to pin
IRQ_0. Please refer to section 5.2.2 for further details.
5.2.5.4 RSSI in buffered mode
In buffered mode the Received Signal Strength Indication operates the same way as in continuous mode. In buffered
mode, however, RSSI_irq may be mapped to IRQ_1 (please refer to section 5.2.2) instead of to IRQ_0 in continuous
mode.
5.2.5.5
Frequency Error Indicator in buffered mode – FEI
In buffered mode the Frequency Error Indication operates the same way as in continuous mode. Please refer to section
5.2.3.5 for more details.
5.2.6
Additional narrowband filter bandwidths
The lowest bandwidth for the base-band filter which can be selected by changing only a 2-bit word in the configuration
register is 10 kHz. However, as described in section 7.2.8, additional register settings allow this bandwidth to be further
reduced. This option allows the user to improve the selectivity of the receiver for very narrow-band applications.
Activating this option is advised for bit rates and frequency deviations not higher than 4.8 kbit/s and 5 kHz and if the LO
frequency of the receiver is well controlled, for instance by means of a very accurate crystal or the activation of an AFC.
The table below gives the sensitivity and the adjacent channel rejection for BR = 4.8 kbit/s and Δf = 5 kHz for different
bandwidths.
Bandwidth
TParam_Low _BW
TParam_Code_BW(8:0)
SSB
10 kHz
0
X
Sensitivity
RFS
(BER=0.1%)
Adjacent Channel Rejection
ACR
(25 kHz offset single tone)
-116 dBm
20 dBc
9 kHz
1
139
-116 dBm
25 dBc
8 kHz
1
160
-115.5 dBm
30 dBc
7 kHz
1
185
-115 dBm
35 dBc
Table 8: Performances of the receiver for very narrow bandwidths and 4.8 kbit/s
Table 9 below gives the sensitivity and the adjacent channel rejection for BR = 1.2 kbit/s and Δf = 2 kHz.
Bandwidth
SSB
TParam_Low _BW
TParam_Code_BW(8:0)
Sensitivity
RFS
(BER=0.1%)
Adjacent Channel Rejection
ACR
(25 kHz offset single tone)
10 kHz
0
X
-117.5 dBm
18 dBc
9 kHz
1
139
-118 dBm
23 dBc
8 kHz
1
160
-119 dBm
28 dBc
7 kHz
1
185
-119.5 dBm
33 dBc
Table 9: Performances of the receiver for very narrow bandwidths and 1.2 kbit/s
It can be seen from table 9 that this option also allows the sensitivity to be improved for very low bit rates and frequency
deviations.
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XE1205
5.3 TRANSMITTER SECTION
The XE1205 is set to transmit mode when MCParam_Select_mode is low by setting MCParam_Chip_mode(1:0) to “10”.
If MCParam_Select_mode is high the XE1205 is set to transmit mode by setting pins SW(1:0) to “10”.
The data directly modulates the LO, or an (optional) pulse shaping filter can be used resulting in an adjacent channel
power down to -37dBm at 25kHz for an output power up to 10dBm.
In continuous mode the transmitted data is sent directly to the frequency synthesizer.
In buffered mode the data is first written into the sixteen byte FIFO via the SPI interface; data from the FIFO is used to
modulate the frequency synthesizer.
5.3.1
Output power
The output power of the power amplifier is programmable on four values with the register TXParam_Power (please refer
to section 7.2.4 below), as shown in Table 10, where RFOP values are given in the Electrical Specifications section
4.2.2.
TXParam_POWER
00
Output power
RFOP1
01
RFOP2
10
RFOP3
11
RFOP4
Table 10: Output power settings
5.3.2
Transmitter in continuous mode
The transmitter works in continuous mode if the bit MCParam_Buffered_mode is low. The transmit data should be
applied to pin DATA if register bit Data_unidir is low or pin NSS_DATA if register bit Data_unidir is high. Figure 11 shows
the transmitter chain in continuous mode:
MCParam_Data_unidir
0
modulator
1
0
Data shaping
filter
datain
TXParam_Filter
DATA
NSS_DATA
1
IRQ_1
Figure 11: Transmitter data path in continuous mode
The pulse shaping function is enabled by setting TXParam_Filter to ‘1’. If the filtering option is selected, the DCLK signal
is used as data clock in the transmission and this clock is generated at a frequency according to the selected bit rate.
The DCLK signal is supplied to the microcontroller via the pin IRQ_1 which must update the data on the falling edge. The
data is sampled at the rising edge of DCLK and filtered.
Figure 12 shows an example of filtered data for a bit rate of 4.8kbit/s and a frequency deviation of 5 kHz:
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XE1205
Figure 12: Pre-filtering of bit stream in transmit mode
The filtering option can be used for all bit rates specified in section 5.2.3.2 and for the following frequency deviations.
Freq_dev(8:0)
Frequency deviation (kHz)
000000101
2.5
000001010
5
000010100
10
000101000
20
001010000
40
010100000
80
101000000
160
Table 11: Available frequency deviations when using the filtering option
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XE1205
5.3.3
Transmitter in buffered mode.
The transmitter works in buffered mode if bit MCParam_Buffered_mode is high. Data to be transmitted is written to the
16-byte FIFO via the SPI interface. The data is loaded into a shift register which passes the data bit by bit to the data
shaping filter or directly to the frequency synthesizer (as explained in the previous section). The transmitter chain is
shown in Figure 13:
IRQ_0
0
modulator
Data
shaping
filter
1
shift register
dclk
/fifoempty
FIFO
TXParam_Filter
IRQ_1
SPI
MOSI
MISO
SCK
NSS_DATA
Figure 13: Transmit chain in buffered mode
FIFO operation in transmit mode is similar to receive mode; transmission either starts immediately after data is written
into the FIFO or when the FIFO is full, determined by the IRQParam_Start_full bit setting.
If the transmit FIFO is full the interrupt signal fifofull is asserted on pin IRQ_1 (if configured accordingly). If data is written
into the FIFO while it is full, the flag IRQParam_Fifooverrun will be set to ‘1’ and the previous FIFO contents will be
overwritten.
The IRQParam_Fifooverrun flag is cleared by writing a ‘1’ to it. At the same time this clears the contents of the FIFO.
Once the last data in the FIFO is loaded into the shift register, the flag /fifoempty is set to high on pin IRQ_0. If new data
is not written in the FIFO and the last bit of the shift register has been transferred to the frequency synthesizer, the bit
IRQParam_Tx_stopped goes high and the data seen by the frequency synthesizer is the last bit sent. If the transmitter is
switched off (e.g. entry into another mode), the transmission will stop immediately even if there is still unsent data in the
shift register.
In transmit mode the two interrupt signals are IRQ_0 and IRQ_1.
IRQ_1 is mapped to IRQParam_Fifofull signal indicating that the transmission FIFO is full when IRQParam_Tx_irq_1 is
set to ‘0’ and to TX_stopped when IRQParam_Tx_irq_1 is set to ‘1’.
IRQ_0 is mapped to the /fifoempty signal; this signal is used to indicate that the transmission FIFO is empty and must be
refilled with data to continue data transmission.
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XE1205
5.4 FREQUENCY SYNTHESIZER
The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver section as well as the continuous
phase FSK (CPFSK) modulated signal for the transmitter section. The core of the synthesizer is implemented with a
Sigma-Delta PLL architecture. The frequency is programmable with a step-size of 500 Hz in the 433, 868 and 915 MHz
frequency bands. This block includes a crystal oscillator which provides the frequency reference for the PLL. This
reference frequency can also be used as a reference clock for the external microcontroller on the CLKOUT pin.
5.4.1
Clock Output for an external processor
A reference clock can be generated for use by an external microcontroller. The OSCParam_Clkout configuration bit
controls the CLKOUT pin. When set to high, CLKOUT is enabled, otherwise it is disabled. The output frequency at
CLKOUT is defined by the value of the OSCParam_Clkout_freq(2:0) parameter. The output frequency at CLKOUT is the
reference oscillator frequency divided by 2, 4, 8, 16 or 32. With a reference oscillator frequency of 39 MHz this provides
a reference clock at 19.5 MHz, 9.75 MHz, 4.87 MHz, 2.44 MHz or 1.22 MHz, respectively.
This clock signal is disabled in Sleep Mode.
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XE1205
6
HIGHEST BIT RATES: EXAMPLE OF 304.7 KBIT/S OPERATION
XE1205 is able to sustain other bit rates between 152.34 kbit/s and 304.7 kbit/s using OSR_minus_1 register as
described in section 5.2.3.2. It is recommended whenever possible to use a modulation index (β=2Δf/BR) ≥2
whenever possible. For the highest bit rates the receiver filter bandwidth will limit the maximal usuable β. Lower
modulation indexes should be used then. In this chapter we provide the example of the highest bit rate.
In order to operate at 304.7 kbit/s the following settings should be used:
Please note that exact bitrate value is 304.6875 kbit/s.
6.1
REGISTERS SETTINGS
6.1.1
Bitrate (BR) and frequency deviation (fdev)
At 304.7 kbit/s, a modulation index close to 1 is compulsory because of the limited bandwidth of the Rx filter.
Frequency deviation will be set to 160 kHz to also take benefit from the Tx filter available (Cf Table 11).
Consequently, following settings should be programmed:
Name
Address
0
1
2
27
28
Freq_dev(8:0)
Br(6:0)
Chg_OSR
OSR (7:0)
Bits
0
7-0
6-0
4
7-0
Value (d)
Note
320
160.36 kHz
0
1
15
152.34 kbit/s…
…=>304.68 kbit/s
Table 12: common registers settings for 304.7 kbit/s
6.1.2
Rx filter
For a correct behavior we recommend to have an Rx filter bandwidth of minimum fdev + (BR/2).
Consequently, following settings should be programmed:
Name
BW(1:0)
Max_BW
TParam_Low_BW
TParam_Code_BW(8:0)
Address
8
8
19
21
22
Bits
6-5
4
2
6-0
7-6
Value (d)
3
0
1
Note
200 kHz…
87
…=>320 kHz
Table 13: Rx registers settings for 304.7 kbit/s
6.1.3
Tx filter
Tx filter is also available at 304.7 kbit/s operation and although not compulsory, its use is recommended to reduce
spectrum bandwidth. Contrary to the other bitrates, an additional specific bit must be set.
Consequently, following settings should be programmed:
Name
Filter
304 kbit/s_filter
Address
7
18
Bits
4
3
Value (d)
1
1
Note
Table 14: Tx registers settings for 304.7 kbit/s
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XE1205
6.2 HARDWARE SETTINGS
When operating at 304.7 kbit/s, the loop filter must be modified. Typical recommended component values are provided
below :
Name
434 MHz
869 MHz
915 MHz
Tolerance
CL1
3.3 nF
10 nF
10 nF
± 5%
CL2
220 pF
150 pF
150 pF
± 5%
RL1
1.5 kΩ
1.5 kΩ
1.5 kΩ
± 5%
Table 15: PLL Loop Filter Bill of Material for 304.7 kbit/s
6.3 OPERATION
Like for any other configuration, in order to avoid crystal misalignment issues and get the best performance it is
recommended to perform an AFC with maximum Rx filter bandwidth before using the 304.7 kbit/s with the settings
described above.
AFC operation may need to be performed at a lower datarate to cover worst case crystal, process and temperature
variations.
Please note that all features including FIFO are available at bit rates up to 304.7 kbit/s.
6.4
•
•
TYPICAL PERFORMANCE
[email protected]%: -102 dBm in mode A and -90 dBm in mode B.
[email protected] offset, single tone: 25 dBc.
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23
XE1205
7
SERIAL INTERFACE DEFINITION AND PRINCIPLE OF OPERATION
7.1 SERIAL CONTROL INTERFACE
The XE1205 contains two SPI-compatible serial interfaces, one to send and read the chip configuration, the other to
send and receive data in buffered mode. Both interfaces are configured in slave mode and share the same pins MISO
(Master In Slave Out), MOSI (Master Out Slave In), SCK (Serial Clock). Two additional pins are required to select the
SPI interface: NSS_CONFIG to change or read the transceiver configuration, and NSS_DATA to send or read data.
SW(1)
SW(0)
Figure 14 shows the connections between the transceiver and a microcontroller when buffered mode is used. IRQ_0 and
IRQ_1 are not mentioned in the drawing but can be used.
SPI
CONFIG
(slave)
NSS_CONFIG
MOSI
MISO
SCK
XE1205
CORE
NSS_CONFIG
MOSI
MISO
SCK
NSS_DATA
µC
SPI
DATA
(slave)
(master)
NSS_DATA
XE1205
Figure 14: Connection between SPI DATA, SPI CONFIG and a micro-controller
It is possible to change between the four modes (sleep, stand-by, receive, transmit) by using the two-bit signal SW(1:0).
This option is enabled by setting the bit MCParam_Select_mode to ‘1’ in the configuration register.
A byte transmission can be seen as a rotate operation between the value stored in an 8 bit shift register of the master
device (the microcontroller for instance) and the value stored in an 8 bit shift register of the selected slave device (the
transceiver). The SCK line is used to synchronize both SPI interfaces. Data is transferred full-duplex from master to
slave through the MOSI line and from slave to master through the MISO line. The most significant bit is always sent first.
In both SPI interfaces the rising SCK edge is used to sample the received bit, and the falling SCK edge shifts the data
inside the shift register. Max SCK frequency is 2MHz.
The NSS_CONFIG or NSS_DATA signal is controlled by the master device and should remain low during the byte
transmission. It is not necessary to toggle the NSS_CONFIG signal back to high and back to low between each
transmitted byte. However It is necessary to toggle the NSS_DATA signal back to high and back to low between each
transmitted byte. The transmission is synchronized by the NSS_CONFIG or NSS_DATA signal. While the NSS_CONFIG
or NSS_DATA is high, the counters controlling transmission are reset. Reception starts with the first clock cycle after the
falling edge of NSS_CONFIG or NSS_DATA; if either signal goes high during a byte transmission the counters are reset
and the byte has to be retransmitted.
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XE1205
7.1.1
Chip configuration via SPI_CONFIG interface
The SPI_CONFIG interface is selected if NSS_CONFIG is low even if the circuit is in buffered mode and NSS_DATA is
low (SPI_CONFIG has priority). To configure the transceiver two bytes are required; the first byte contains a start bit
(equal to 0), R/W information (‘1’ for a read operation or ‘0’ for a write operation), 5 bits for the address of the register
and finally a stop bit (equal to ‘1’). The second byte contains the data to be sent in write mode or the new address to
read from in read mode. Figure 15 shows the timing diagram for a typical write sequence:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
New value of
register A1*
MOSI
start
rw
A(4) A(3) A(2) A(1) A(0) stop D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Data at address
A1*
Address = A1
MISO
HZ
x
x
x
x
x
x
x
x
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
D(0)
HZ
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
Sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
NSS_CONFIG
* when writing the new data at address A1,
the previous contents of A1 can be read by the micro-controller
Figure 15: Write sequence when sending a new configuration to the XE1205 via the SPI _CONFIG
NSS_CONFIG must remain low during the transmission of the two bytes (address and data); if it goes high after the first
byte, then the next byte will be considered as an address byte. When writing more than one register successively,
NSS_CONFIG does not need to make a high to low transmission between two write sequences. The bytes are
alternatively considered as an address byte followed by a data byte.
The read sequence via the SPI_CONFIG interface is similar to the write one except that the data byte contains all zeroes
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XE1205
Figure 16 shows the read sequence of a single register:
1
2
3
start
rw
A(4)
X
X
X
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
MOSI
MISO
HZ
A(3) A(2) A(1) A(0) stop
X
X
X
X
X
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
D(0)
HZ
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
sample
shift
NSS_CONFIG
Figure 16: Read sequence of a single register via the SPI _CONFIG
7.1.2
Data transmission and reception via SPI_DATA interface.
When the transceiver is used in buffered mode, the data exchange with a micro-controller is done via the SPI_DATA
interface.
In transmit mode the16 byte FIFO can be filled as long as it is not full (IRQ_1 can be used if FIFO_full is mapped).
In receive mode, the FIFO may be read if one of the following events occurs:
• at least one byte is present in the FIFO, i.e. a rising edge on IRQ_0 mapped to /fifoempty
• each time a byte is written to FIFO, i.e. a rising edge on IRQ_0 mapped to WRITE_BYTE
• 16 bytes have been written to the FIFO, i.e. a rising edge on IRQ_1 mapped to RX_FIFOfull
The transceiver should be in buffered mode (MCParam_Buffered_mode = ‘1’). The SPI_DATA interface is then selected
if NSS_DATA is low and NSS_CONFIG is high.
The operations with SPI_DATA interface are similar to those with SPI_CONFIG except that there is only a data byte (no
address byte is required) and except that it is necessary to toggle the NSS_DATA signal back to high and back to low
between each transmitted or received byte.
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XE1205
Figure 17 shows the write operation during transmit.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCK
D1(7) D1(6)
MOSI
D1(5)
D1(4) D1(3)
x
D1(2)
D1(1)
D1(0)
D2(7)
D2(6)
D2(5)
D2(4)
D2(0)
sample
sample
sample
HZ
x
x
x
x
x
x
x
x
sample
x
sample
x
sample
x
sample
x
sample
x
sample
x
sample
x
sample
x
sample
HZ
sample
MISO
D2(1)
Byte 2
to read
sample
Byte 1 to
read
D2(3) D2(2)
x
HZ
shift
shift
shift
shift
shift
shift
shift
shift
sample
shift
shift
shift
shift
shift
shift
shift
shift
sample
NSS_DATA
Figure 17 Writing 2 bytes in transmitter mode
Figure 18 shows the read operation in receive mode.
1
2
3
4
5
6
7
8
x
x
x
x
x
1
2
3
x
x
4
5
6
7
8
x
x
x
x
SCK
x
x
MOSI
x
x
x
D2(7) D2(6)
D2(5)
D2(4)
D2(3)
D2(2)
D2(1)
sample
HZ
sample
D1(2) D1(1) D1(0)
sample
D1(4) D1(3)
sample
D1(6) D1(5)
sample
D1(7)
sample
HZ
sample
MISO
Byte 2
to read
sample
Byte 1 to
read
D2(0)
HZ
shift
shift
sample
shift
shift
shift
shift
shift
sample
shift
sample
shift
shift
sample
shift
sample
shift
shift
sample
shift
shift
sample
shift
sample
NSS_DATA
Figure 18: Reading 2 bytes in receive mode.
Note that it is necessary to toggle NSS_DATA signal back to high and then back to low between each
transmitted and received byte.
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XE1205
7.2 CONFIGURATION AND STATUS REGISTERS
The XE1205 has several operating modes, configuration parameters and internal status registers that may be accessed
by the microcontroller via the SPI_CONFIG interface.
The switching pins SW(1:0) allows switching between one of the four operating modes (sleep, stand-by, receive,
transmit) when MCParam_Select_mode is high. If MCParam_Select_mode is low, the modes are defined by the register
through the SPI_CONFIG interface and SW(1:0) may be used as an output to control, for example, an antenna switch.
7.2.1
Configuration register: general description
The description of the registers which are useful for the user is given in Table 16 below:
Name
MCParam
Size
5x8
Address
0-4
IRQParam
TXParam
RXParam
OSCParam
TParam
2 x8
1x8
9x8
2x8
12 x 8
5-6
7
8-16
17-18
19-30
Description
Main parameters common to transmit and
receive modes
Interrupt registers
Transmitter parameters
Receiver parameters
Oscillator parameters
Test and special settings
Table 16: configuration registers
All the bits that are referred to as “reserved” in this section should be set to “0” during write operations.
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XE1205
7.2.2
MCParam configuration register (main configuration parameters)
The detailed description of the MCParam register is given in Table 17.
Chip_mode(1:0)
Bits
7-6
Address RW
0
r/w
Select_mode
5
0
r/w
Buffered_mode
4
0
r/w
Data_unidir
3
0
r/w
Band(1:0)
2-1
0
r/w
Freq_dev(8)
Freq_dev(7:0)
0
7-0
0
1
r/w
r/w
Knx
7
2
r/w
Br(6:0)
6-0
2
r/w
Name
Description
Transceiver mode:
00 -> sleep mode
01 -> receive mode
10 -> transmit mode
11 -> stand-by mode
Transceiver mode selection:
0 -> mode defined by MCParam_chip_mode, SW(1:0) is an output
sleep mode
-> SW(1:0) = ”00”
receiver mode -> SW(1:0) = “01”
transmitter mode -> SW(1:0) = “10”
stand-by mode -> SW(1:0) = “00”
1 -> mode defined by SW(1:0) :
SW(1:0) = 00 -> sleep mode
SW(1:0) = 01 -> receive mode
SW(1:0) = 10 -> transmit mode
SW(1:0) = 11 -> stand-by mode
Enable buffered mode:
0 -> continuous mode
1 -> buffered mode
Configure DATA pin
0 -> DATA is a bidirectional pin:
input in transmit, output in receive mode
1 -> DATA is an output pin:
output in receive mode, high-impedance in transmit mode
Frequency band:
01 -> 433 – 435 MHz
10 -> 863 – 870 MHz
11 -> 902 – 928 MHz
Frequency deviation MSB
Frequency deviation:
Δf = int(Freq_dev(8:0)) * FSTEP
Where int(x) = integer value of the binary representation of x
Example
000000001 -> Δf = FSTEP
111111111 -> Δf = 511*FSTEP
all these frequency deviations are available if the data shaping filter is
disabled (please refer to Table 11)
Konnex mode enable
0 -> default mode -> bit rate defined by MCParam_Br(6:0)
1 -> Konnex mode-> bit rate = 32.7 kbit/s
Bit rate
Br = 152.34e3/(int(Br) + 1)
Where int(x) = integer value of the binary representation of x.
Example:
0000001 -> Br = 76.1 kbit/s
1111111 -> Br = 1.19 kbit/s
Note: if Konnex mode is enabled, then bit rate = 32.7 kbit/s.
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XE1205
Name
Freq_lo(15:8)
Freq_lo(7:0)
(7)
Bits
7-0
7-0
Address RW
3
r/w
4
r/w
Description
LO frequency in 2’s complement:
00…0 -> Flo = middle of the range(6)
0X…X-> Flo = higher than the middle of the range
1X…X-> Flo = lower than the middle of the range
Example: 00…001 -> Flo = middle of the range + FSTEP
Table 17: MCParam configuration register
(6) When frequency band is set to 863-870MHz, 869MHz should be considered as the middle of the range.
(7) When frequency band is set to 433-435MHz, MSB is bit 14 and bit 15 is not used.
7.2.3
IRQParam configuration register (IRQ parameters)
The detailed description of the IRQParam register is given in Table 18.
Name
Rx_irq_0(1:0)
Bits
7-6
Address
5
RW
r/w
Rx_irq_1(1:0)
5-4
5
r/w
Tx_irq_1
3
5
r/w
Fifofull
/fifoempty
Fifooverrun
Start_fill
2
1
0
7
5
5
5
6
r
r
r/w/c
r/w
Start_detect
6
6
r/w/c
Description
Select IRQ_0 source in Rx mode:
If Buffered_mode = 0
00 -> IRQ_0 mapped to Pattern signal
01 -> IRQ_0 mapped to RSSI_irq signal
10 -> IRQ_0 mapped to Pattern signal
11 -> IRQ_0 mapped to Pattern signal
if Buffered_mode = 1
00 -> IRQ_0 set to ‘0’
01 -> IRQ_0 mapped to Write_byte signal
10 -> IRQ_0 mapped to /fifoempty signal
11 -> IRQ_0 mapped to Pattern signal
Select IRQ_1 source in Rx mode
If Buffered_mode = 0
00 -> IRQ_1 mapped to DCLK signal
01 -> IRQ_1 mapped to DCLK signal
10 -> IRQ_1 mapped to DCLK signal
11 -> IRQ_1 mapped to DCLK signal
if Buffered_mode = 1
00 -> IRQ_1 set to ‘0’
01 -> IRQ_1 mapped to Fifofull signal
10 -> IRQ_1 mapped to RSSI_irq signal
11 -> IRQ_1 mapped to RSSI_irq signal
Select IRQ_1 source in Tx mode
If Buffered_mode = 0
0 or 1 -> IRQ_1 is mapped to DCLK
0 or 1 -> IRQ_0 is set to low
if Buffered_mode = 1
0 -> IRQ_1 is mapped to Fifofull signal
1 -> IRQ_1 is mapped to TX_stopped signal
(IRQ_0 is mapped to /Fifoempty in Buffered mode)
FIFO full (IRQ source)
FIFO empty (IRQ source)
FIFO overrun error : Write ‘1’ clear FIFO after Overrun occurred
FIFO filling selection mode
0 -> The FIFO is filled if a pattern is detected
1 -> The FIFO is filled as long as Start_detect is high
Start of FIFO filling
If start_fill = ‘0’ goes high when a start sequence is detected
writing a ‘1’ clears the bit and wait for a new start sequence
If start_fill = ‘1’, 1 -> start to fill the FIFO, 0 -> stop to fill the FIFO.
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XE1205
Name
Tx_stopped
Bits
5
Address
6
RW
r
Description
Transmission stopped ( IRQ source)
Start_full
4
6
r/w
RSSI_int
3
6
r/w
RSSI_signal_detect
2
6
r/w/c
RSSI_thr
1-0
6
r/w
0 -> Start transmission when the FIFO is full
1 -> Start transmission when FIFO is not empty (/fifoempty = ‘1’)
Enable interrupt RSSI_irq when RSSI_thr is reached:
0 -> no interrupt generated
1 -> interrupt allowed
Detection of a signal above RSSI_thr (IRQ source)
0 -> signal power lower than the threshold defined by RSSI_thr.
1 -> signal power equal or greater than the threshold defined by RSSI_thr
Writing ‘1’ clear RSSI_signal_detect
RSSI threshold for interrupt
00 -> input power ≥ VTHR1
01 -> input power ≥ VTHR2
10 -> input power ≥ VTHR3
11 -> input power ≥ VTHR3
Table 18: IRQParam configuration register
7.2.4
TXParam configuration register (transmitter configuration parameters)
The detailed description of the TXParam register is given in Table 19.
Name
Power(1:0)
Bits
7-6
Address
7
RW
r/w
/Modul
5
7
r/w
Filter
4
7
r/w
RESERVED
Fix_bsync
3-2
1
7
7
r/w
r/w
RESERVED
0
7
r/w
Description
Transmitter output power:
00 -> 0 dBm
01 -> 5 dBm
10 -> 10 dBm
11 -> 15 dBm
Inhibition of the modulation in transmitter mode:
0 -> modulation
1 -> no modulation
Pre-filtering of the bit stream in transmitter mode:
0 -> no filtering
1-> data shaping filter enabled
all bit rates defined by Br are available
frequency deviations given in Table 11 are available
RESERVED
0 -> bit sync in normal environment
1-> bit sync in noisy environment
RESERVED
Table 19: TXParam configuration register
7.2.5
RXParam configuration register (receiver configuration parameters)
The detailed description of the RXParam register is given in Table 20.
Disable_bitsync
Bits
7
Address
8
RW
r/w
BW(1:0)
6-5
8
r/w
Max_BW
4
8
r/w
Name
Description
Bit synchronizer on/off:
0 -> ON
1 -> OFF
Bandwidth of the base band filter(SSB): must be ≥ Freq_dev + Br/2
00 -> 10 kHz
01 -> 20 kHz
10 -> 40 kHz
11 -> 200 kHz
Forces the bandwidth of the base band filter to its maximum value
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XE1205
Name
Bits
Address
RW
Reg_BW(1:0)
3-2
8
r/w
Init_filter(1:0)
1-0
8
r/w
RSSI
7
9
r/w
RSSI_range
6
9
r/w
RSSI_out
5-4
9
r
FEI
3
9
r/w
AFC_start
2
9
r/w
AFC_OK
1
9
r/w
AFC_disable
0
9
r/w
AFC_overflow
7
10
r/w
IQAMP
6
10
r/w
Rmode
5
10
r/w
Pattern
4
10
r/w
Psize(1:0)
3-2
10
r/w
Description
(about 400 kHz SSB) and disables calibration:
0 -> bandwidth defined by BW(1:0)
1 -> bandwidth forced to its maximal value
Calibration of the bandwidth of the base band filter:
00 -> calibration at start up
01 -> no calibration
10 -> calibration when the bandwidth of the base band filter changes
11 -> calibration is forced each time 11 is written
Base band filter initialization:
00 -> default initialize at start up
01 -> RESERVED
10 -> initialize each time the bandwidth change
11 -> force re-initialization
RSSI off/on:
0 -> off
1 -> on
Range of the RSSI:
0 -> low range
1 -> high range
00 -> input power ≤ VTHR1
01 -> VTHR1 ≤ input power ≤ VTHR2
10 -> VTHR2 ≤ input power ≤ VTHR3
11 -> VTHR3 ≤ input power
Frequency Error Indicator off/on:
0 -> off
1 -> on
0 -> AFC not running process
1 -> AFC running
Writing 0 will start the AFC process. At the end of the AFC process, the
bit goes automatically back low.
Result of the AFC
0 -> AFC operation successful
1 -> AFC operation unsuccessful
Disabling the AFC
0 -> the error cancelation is automatically applied on the LO frequency
1 -> the error cancelation is not applied on the LO frequency
AFC overflow indicator
0 -> no overflow
1 -> the integrator of the frequency error is too high
writing 1 to this bit will reset the integrator
IQ amplifier off/on:
0 -> off
1 -> on
Linearity/sensitivity mode
0 -> Mode A (high sensitivity)
1 -> Mode B (high linearity)
Pattern recognition off/on:
0 -> off
1 -> on
Size of the reference Pattern:
00 -> 8 bits
01 -> 16 bits
10 -> 24 bits
11 -> 32 bits
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XE1205
Ptol(1:0)
Bits
1-0
Address
10
RW
r/w
FEI_out(15:8)
FEI_out(7:0)
7-0
7-0
11
12
r
r
Name
Description
Number of tolerated errors for the pattern recognition:
00 -> 0 error
01 -> 1 error
10 -> 2 errors
11 -> 3 errors
FEI output
in a 2’s complement representation
Table 20: RXParam configuration register
7.2.6
Pattern register
Name
Reg_pattern(31:24)
Reg_pattern(23:16)
Reg_pattern(15:8)
Reg_pattern(7:0)
Bits
7-0
7-0
7-0
7-0
Address
13
14
15
16
RW
r/w
Description
1st byte of the reference pattern
2nd byte of the reference pattern
3rd byte of the reference pattern
4th byte of the reference pattern
Table 21: Pattern register
This register holds the user supplied reference pattern of 8, 16, 24, or 32 bits (see the RXParam_Psize(1:0) parameter).
The first byte of this pattern is always stored in the byte at address 13. If used, the 2nd byte is stored at address 14, the
3rd byte at address 15 and finally the 4th byte at 16. The MSB bit of the reference pattern is always bit 7 of address 13.
Comparing the demodulated data, the first bit received is compared with bit 7 (the MSB) of byte address 13. The last bit
received is compared with bit 0 (the LSB) in the Pattern register.
Table 22 provides an example of pattern recognition with a 32-bit pattern.
Byte Address
13
Bit 7
Bit 0
10010011
101 10010011
Byte Address
14
Bit 7
Bit 0
10101010
10101010
Byte Address
15
Bit 7
Bit 0
10010011
10010011
previous bits from
demodulator
Byte Address
16
Bit 7
Bit 0
10101010
10101010
last bit received
Table 22: Pattern recognition example (32 bits)
Table 23 provides an example of pattern recognition with an 8-bit pattern.
Byte Address
13
Bit 7
Bit 0
10010011
101 10010011
Byte Address
14
Bit 7
Bit 0
Xxxxxxxx
previous bits from
demodulator
last bit received
Byte Address
15
Bit 7
Bit 0
Xxxxxxxx
Byte Address
16
Bit 7
Bit 0
Xxxxxxxx
Table 23: Pattern recognition example (8 bits)
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XE1205
7.2.7
OSCParam configuration register (oscillator parameters)
Osc
Bits
7
Address
17
RW
r/w
Clkout
6
17
r/w
Clkout_freq(2:0)
5-3
17
r/w
RESERVED
Resxosc
2-0
7-4
17
18
r/w
r/w
304 kbit/s_filter
3
18
r/w
RESERVED
2-0
18
r/w
Name
Description
Sources of reference frequency
0 -> internal quartz oscillator (for XTAL or TCXO)
1 -> external signal applied on pin XTA (CMOS type signal, external clock)
Enable clkout
0 -> no signal provided on pin CLKOUT
1 -> Signal at reference frequency divided by 2, 4, 8,16, 32 provided on
CLKOUT (19.5 MHz down to 1.22 MHz)
Frequency of signal provided on CLKOUT:
000 -> 1.22 MHz
001 -> 2.44 MHz
010 -> 4.87 MHz
011 -> 9.75 MHz
others -> 19.5 MHz
RESERVED
Select the value of the resistor placed between TKA and TKB in order to
use the transceiver with a crystal operating on its third overtone
0000 -> no resistor ( 3.8 MΩ)
0001 -> 1.48 kΩ
0010 -> 1.56 kΩ
0011 -> 1.66 kΩ
0100 -> 1.78 kΩ
0101 -> 1.91 kΩ
0110 -> 2.07 kΩ
0111 -> 2.26 kΩ
1000 -> 2.55 kΩ
1001 -> 2.81 kΩ
1010 -> 3.22 kΩ
1011 -> 3.79 kΩ
1100 -> 4.65 kΩ
1101 -> 6.04 kΩ
1110 -> 8.79 kΩ
1111 -> 16.55 kΩ
304.7 kbit/s Tx filter
0 -> disabled
1 -> enabled
RESERVED
Table 24: OSCParam configuration register
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XE1205
7.2.8
ADParam configuration register (additional settings)
Most of the parameters of this category are for test purposes. Some of them can be used to supersede settings that are
described in previous sections to optimize special applications. These last parameters are described in the table below.
Name
Bits
Address
RW
Add_BW
1
19
r/w
Description
Change of RXParam_BW(1:0) decoding, allowing additional
bandwidths for the base-band filter to be selected:
Add_BW = 0 -> default values of RXParam_BW(1:0):
RXParam_BW(1:0) = 00 => 10 kHz
RXParam_BW(1:0) = 01 => 20 kHz
RXParam_BW(1:0) = 10 => 40 kHz
RXParam_BW(1:0) = 11 => 200 kHz
Add_BW = 1 -> new bandwidth values:
RXParam_BW(1:0) = 00 => 14.3 kHz
RXParam_BW(1:0) = 01 => 28.5 kHz
RXParam_BW(1:0) = 10 => 66.7 kHz
RXParam_BW(1:0) = 11 => 100 kHz
Low_BW
2
19
r/w
Flag allowing selection of base-band filter bandwidths lower than 10
kHz:
0 -> default values given by RXParam_BW(1:0) and
TParam_Add_BW
1-> bandwidths defined by TParam_Code_BW(8:0)
Code_BW(8:0)
6-0
21
7-6
22
r/w
Low base-band filter bandwidths, when TParam_Low_BW = 1:
Code_BW(8:0) = 139 => 9 kHz
Code_BW(8:0) = 160 => 8 kHz
Code_BW(8:0) = 185 => 7 kHz
MSB Code_BW(8) = bit 6 of address 21
Add_HPF(2:0)
5-3
22
r/w
Chg_OSR
4
27
r/w
OSR
7-0
28
r/w
Cut-off frequency of the HPF stages allowing cancellation of the DC
and low-frequency offsets in the baseband circuit:
0 0 0 -> 660 Hz (default value)
0 0 1 -> 1.48 kHz
0 1 0 -> 1.75 kHz
0 1 1 -> 1.96 kHz
1 0 0 -> 2.55 kHz
1 0 1 -> 3.34 kHz
1 1 0 -> 5.11 kHz
1 1 1 -> 10.2 kHz
Flag allowing the over-sampling ratio of the bit synchronizer to be
changed:
0 -> default OSR (32)
1 -> OSR defined by TParam_OSR(7:0)
Over-sampling ratio of the bit synchronizer when
TParam_Chg_OSR = 1
Actual OSR = TParam_OSR(7:0) + 1
Table 25: Useful special settings from TParam register
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XE1205
7.3
OPERATING MODES
The XE1205 has four main operating modes illustrated in Table 26 below. These modes are defined by register
MCParam_Chip_mode(1:0) when bit MCParam_Select_mode is low and defined by SW(1:0) pins when
MCParam_Select_mode is high. Please note that in both cases the changes will be applied to the transceiver upon the
rising edge of the NSS_CONFIG signal (ie NSS_CONFIG must be set low even when using SW(1:0) as inputs).
00
SW(1:0)
mode
Output
SW(1:0)
value
00
Operating
Mode
Sleep
Enabled blocks of the
transceiver
-
0
01
Output
01
Receive
0
10
Output
10
Transmit
0
11
Output
11
Standby
Quartz oscillator, Frequency
synthesizer, Receiver
Quartz oscillator, Frequency
synthesizer, Transmitter
Quartz oscillator
1
00
Input
00
Sleep
-
1
01
Input
01
Receive
1
10
Input
10
Transmit
1
11
Input
11
Standby
Quartz oscillator, Frequency
synthesizer, Receiver
Quartz oscillator, Frequency
synthesizer, Transmitter
Quartz oscillator
MCParam_Select_mode
MCParam_Chip_mode(1:0)
0
Table 26: Operating modes
7.3.1
XE1205 switching time using SPI_CONFIG interface.
The transceiver is able to switch between modes by using the SPI_CONFIG interface.(MCParam_Chip_mode(1:0)) or by
using the pin SW(1:0). This section describes the switching sequence of the transceiver when register
MCParam_Select_mode is low i.e. the configuration is done via the SPI_CONFIG and SW(1:0) is an output.
The sequence from sleep mode to receive mode via stand-by mode is shown in Figure 19Error! Reference source not
found. TS_SRE is the receiver wake-up time when the oscillator is enabled, defined as the initialization time for the
frequency synthesizer and the base band filter. The base band filter initialization and calibration processes occur when
the transceiver switches from stand-by to receive.
Programmed mode
Stand-by
Sleep
Receive
NSS_CONFIG
Actual mode
Sleep
Stand-by
TS_OS
Receive
TS_SRE
Figure 19 Sequence from sleep mode to receive mode via standby mode.
The sequence from sleep to transmit mode via stand-by mode is displayed in Figure 20. TS_STR is the initialization
time of the frequency synthesizer and the power amplifier.
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XE1205
Programmed mode
Sleep
Transmit
Stand-by
NSS_CONFIG
Actual mode
Sleep
Stand-by
Transmit
TS_OS
TS_STR
Figure 20. Sequence from sleep to transmit mode via stand-by mode.
The sequence from transmit to receive mode is shown in Figure 21. TS_RE is the initialization time of the receiver base
band filter when the frequency synthesizer is enabled. The base band filter initialization and calibration processes occur
when the transceiver switches from transmit to receive.
Programmed mode
Transmit
Receive
NSS_CONFIG
Actual mode
Transmit
Receive
TS_RE
Figure 21 Sequence from transmit to receive mode.
Figure 22 represents the sequence from receive to transmit mode. TS_TR is the initialization time of the power amplifier
if the frequency synthesizer is already enabled:
Programmed mode
Receive
Transmit
NSS_CONFIG
Actual mode
Receive
Transmit
TS_TR
Figure 22: Sequence from receiver to transmitter mode
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XE1205
Figure 23 illustrates the switching time between two carrier frequencies in receive mode. TS_RFSW is defined as the
switching time of the frequency synthesizer and the time needed by the base band filter to reach the steady-state when
the boost process is used (Init_filter set to “11”).
Actual mode
Programmed frequency
receive
f1
f2
NSS_CONFIG
Actual frequency
f1
f2
TS_RFSW
Figure 23. Switching between two carrier frequencies in receive mode.
Figure 24 shows the switching time between two carrier frequencies in transmit mode. TS_TFSW is defined as the
switching time of the frequency synthesizer and the time required by the power amplifier to reach the steady-state
operating conditions.
Actual mode
Programmed frequency
transmit
f1
f2
NSS_CONFIG
Actual frequency
f1
f2
TS_TFSW
Figure 24. Switching between two carrier frequencies in transmit mode.
7.3.2
XE1205 switching time using SW(1:0) pins.
If MCParam_Select_mode is high then the transceiver mode is fixed by SW(1:0)
MCParam_Chip_mode can be used in read mode but has no effect on the transceiver mode.
pins
and
register
7.4 SELECTION OF THE REFERENCE FREQUENCY
The reference clock used for the frequency synthesizer and the internal digital circuitry may be generated by either an
external 39 MHz quartz crystal or a TCXO or an external clock. If an external clock is used, the register OSCParam_Osc
has to be set high, and the 39 MHz clock signal should to be supplied to the pin “XTA” and the pin “XTB” should be left
open. If a TCXO is used, its output signal should be connected to the pin “XTA” and the pin “XTB” should be left.
The transceiver can be used with a 39 MHz fundamental mode quartz crystal or with a 3rd overtone crystal. Third
overtone operation requires an internal resistor to be connected in parallel with the crystal. This resistor can be
connected by programming the register OSCParam_Resxosc(3:0). The required value depends on the crystal
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XE1205
specification. OSCParam_Resxosc(3:0) is set to ”0000’’ by default, which selects a parallel resistor of 3.8 MΩ. This
default value is used with a 39 MHz crystal enabled on its fundamental frequency.
In the case of overtone operation where the microcontroller uses the XE1205 as a clock source, the user should note
that during the power up sequence of the XE1205, the oscillator may start and run at its fundamental frequency until the
correct value of parallel resistor in the register OSCParam_Resxosc(3:0) is programmed. Before time-sensitive
operations an oscillator settling period should be observed to ensure the desired oscillation frequency.
7.5 CLOCK OUTPUT INTERFACE
When OSCParam_Clkout is set high, a CLKOUT clock frequency is provided for a microcontroller or external circuitry. A
user-programmable frequency divider ratio of 2, 4, 8, 16, 32 is selectable depending on OSCParam_Clkout_freq(2:0).
The input frequency of this divider is the 39.0 MHz reference clock; the possible output frequencies are listed in Table
27:
OSC_Param_Clkout_freq(1:0)
000
001
010
011
others
CLKOUT frequency
1.22 MHz
2.44 MHz
4.87 MHz
9.75 MHz
19.5 MHz
Table 27: Frequency divider output
When the XE1205 is in sleep mode, CLKOUT is inactive even if bit OSCParam_Clkout remains high.
7.6 DEFAULT SETTINGS AT POWER-UP
The internally generated power on reset signal sets the MCParam, RXParam, and TXParam registers to ‘0’. The only
exception is the CLKOUT generation: though OSCParam_Clkout is set to low (i.e. disabled) the XE1205 provides a
signal at 1.22 MHz on the pin CLKOUT.
The first rising edge on the NSS_CONFIG pin causes the registers to be updated and this will result in CLKOUT being
disabled. For this reason the first programming sequence should be to enable CLKOUT by setting OSCParam_Clkout to
high for applications using CLKOUT. It is recommended to initialize the XE1205 registers immediately after power-up.
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XE1205
7.7
PAD CONFIGURATION VERSUS CHIP MODES
The table below gives the pad configuration for the different chip modes and settings.
CHIP
…….Mode
Sleep
Standby
Receive
Transmit
Comment
NSS_CONFIG
OUTPUT when
Select_mode = ‘0’
else
Input
OUTPUT when
Select mode = ‘0’
else
Input
INPUT
OUTPUT when
Select_mode = ‘0’
else
Input
OUTPUT when
Select mode = ‘0’
else
Input
INPUT
OUTPUT when
Select_mode = ‘0’
else
Input
OUTPUT when
Select mode = ‘0’
else
Input
INPUT
OUTPUT when
Select_mode = ‘0’
else
Input
OUTPUT when
Select mode = ‘0’
else
Input
INPUT
If Select_mode = ‘1’,
SW0 and SW1
defines the chip
mode
If Select_ mode = ‘1’,
SW0 and SW1
defines the chip
mode
NSS_CONFIG has
the priority over
NSS_DATA
NSS_DATA
INPUT
INPUT
INPUT
INPUT
NSS_DATA is used
as data modulation
input if Data_unidir is
high
IRQ_0
IRQ_1
DATA
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
OUTPUT
OUTPUT
OUTPUT
CLKOUT
MISO
OUTPUT
OUTPUT if
NSS_CONFIG=’0’
or NSS_DATA = ‘0’
else
High Impedance
INPUT
INPUT
OUTPUT
OUTPUT if
NSS_CONFIG=’0’
or NSS_DATA = ‘0’
else
High Impedance
INPUT
INPUT
OUTPUT
OUTPUT if
NSS_CONFIG=’0’
or NSS_DATA = ‘0’
else
High Impedance
INPUT
INPUT
OUTPUT
OUTPUT
Input if Data_unidir
is low ELSE output
(refer to 5.2.5)
OUTPUT
OUTPUT if
NSS_CONFIG=’0’
or NSS_DATA = ‘0’
else
High Impedance
INPUT
INPUT
PAD
SW0
SW1
MOSI
SCK
Condition on
NSS_DATA only
applies in buffered
mode
Table 28. Pad configuration vs chip modes
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XE1205
8
APPLICATION INFORMATION
This section provides details of the recommended component values for the frequency dependant blocks of the XE1205.
Note that these values are dependent upon circuit layout and PCB structure, and that decoupling components have been
omitted for clarity.
8.1
MATCHING NETWORK OF THE RECEIVER
The schematic of the matching network at the input of the receiver is given below (for a source impedance of 50Ω).
CR1
SOURCE
RFA
XE1205
LR1
RFB
CR2
VSS
Figure 25 Matching network at the input of the receiver.
The typical component values of the matching circuit are shown in Table 29 below.
Name
CR1
CR2
LR1
Typical Value for
434 MHz
1.5pF
1.5pF
100nH
Typical Value for
869 MHz
1.2pF
1.5pF
27nH
Typical Value for
915 MHz
1.2pF
1.2pF
27nH
Tolerance
± 5%
± 5%
±5%
Table 29: Matching network values
8.2 MATCHING NETWORK OF THE TRANSMITTER
The optimum load impedances for 15 dBm output power at the three main frequencies are given in Table 30.
PA optimum load
0 dBm
5 dBm
10 dBm
15 dBm
434 MHz
174 + j17
117 + j22
111 + j17
89 - j19
869 MHz
120 + j80
115 + j79
95 + j49
80 + j17
915 MHz
103 + j94
101 + j77
95 + j49
84 + j11
Table 30: Optimum load impedances for 15dBm output power
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XE1205
The Smith charts in Figure 26 and Figure 27 below show contours of output power versus load impedance when the
highest output level is selected (15 dBm mode).
869 MHz 15 dBm
0.8 0.9 1
1.2
1.4
1.6
0.6
1.8
2
0.5
2.4
0.4
3
0.3
4
0.2
5
0.1
10
15 dBm
0.1
0.2
0.5
20
1
20
14 dBm
10
0.1
12 dBm
0.2
5
4
0.3
3
0.4
2.4
0.5
0.6
0.8 0.9 1
1.2
1.4
1.6
1.8
2
Figure 26: Output power vs. load impedance at 869 MHz.
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XE1205
915 MHz 15 dBm
1
0.4
0.2
0.1
15 dBm
0.1
0.2
0.5
1
14 dBm
0.1
0.2
12 dBm
0.4
1
Figure 27: Output power vs. load impedance at 915 MHz.
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XE1205
The schematic of the recommended matching network at the output of the transmitter is given in Figure 28 below. The
two Π-sections are used to provide harmonic filtering to satisfy FCC and ETSI regulations.
CT2
LT3
LT1
VDD
XE1205
CT3
OUTPUT
CT1
CT4
CT5
RFOUT
LT2
Figure 28 Matching network at the output of the transmitter.
The typical component values of the matching circuit are shown in Table 31 below.
Name
CT1
CT2
CT3
CT4
CT5
LT1
LT2
LT3
Typical Value
for 434 MHz
6.8 pF
1.0 pF
22 pF
6.8 pF
4.7 pF
33 nH
22 nH
22 nH
Typical Value
for 869 MHz
1.5 pF
0.56 pF
15 pF
3.3 pF
2.2 pF
39 nH
10 nH
8.2 nH
Typical Value
for 915 MHz
1.8 pF
NC
33 pF
3.3 pF
2.2 pF
47 nH
10 nH
8.2 nH
Tolerance
± 5%
± 5%
± 5%
± 5%
± 5%
± 5%
± 5%
± 5%
Table 31: Matching circuit component values
8.3
VCO TANK
The VCO tank circuit should implemented with an inductor and capacitor in parallel. Typical component values are
shown in Table 32.
Name
434 MHz
869 MHz
915 MHz
Tolerance
CV1
1.0 pF
NC
NC
±5%
LV1
33 nH
6.8 nH
5.6 nH
±2%
Table 32: VCO tank component values
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XE1205
8.4
LOOP FILTER OF THE FREQUENCY SYNTHESIZER
The loop filter of the frequency synthesizer is shown in Figure 29 below.
LFB
RL1
XE1205
CL2
CL1
VSS
Figure 29: Frequency synthesizer loop filter
Typical recommended component values for the frequency synthesizer loop filter are provided in Table 33 below:
Name
CL1
CL2
RL1
434 MHz
22 nF
1 nF
560Ω
869 MHz
12 nF
1 nF
560Ω
915 MHz
10 nF
1 nF
680Ω
Tolerance
± 5%
± 5%
± 5%
Table 33: Typical frequency synthesizer component values
For 304.7 kbit/s operation, refer to section 6.
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XE1205
8.5
REFERENCE CRYSTAL FOR THE FREQUENCY SYNTHESIZER
For narrow band applications, where users select the lowest frequency deviation and the narrowest baseband filter, the
crystal for reference oscillator of the frequency synthesizer should have the following typical characteristics:
Name
Fs
Description
Nominal frequency
CL
Rm
Cm
C0
Δfs(0)
Δfs(ΔT)
Load capacitance for fs (on-chip)
Motional resistance
Motional capacitance
Shunt capacitance
Calibration tolerance at 25 °C
Stability over temperature range
(-40 °C to 85 °C)
Aging tolerance in first 5 years
Δfs(Δt)
Min. value
-
Typ. value
39.0 MHz
(fundamental)
8 pF
-
Max. value
40Ω
30 fF
7 pF
10 ppm
10 ppm
5 ppm
Table 34: Crystal characteristics
The electrical specifications given in section 4.2.2 are valid for a crystal having the specifications given in Table 34. For
wide band applications requiring less frequency stability, the values for Δfs(0), Δfs(ΔT), and/or Δfs(Δt) can be relaxed. In
this case foffset + BWssb should be lower than BWfilter, where foffset is the offset (error) on the carrier frequency (the
sum of Δfs(0), Δfs(ΔT), and/or Δfs(Δt)), BWssb is the single side-band bandwidth of the signal, and BWfilter is the single
side-band bandwidth of the base-band filter.
The overtone crystal usage can result in higher oscillator start-up time than fundamental mode. The overtone crystal
should be designed for Cload = 8 to 10 pF and has parameters of Rm < 60Ω, C0 < 7 pF.
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XE1205
9
PACKAGING INFORMATION
XE1205 comes in a 48-lead VQFN 8X8 package as shown in Figure 30 below.
Figure 30: Package dimensions
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XE1205
© Semtech 2008
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes
no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper
installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to
parameters beyond the specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF
SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S
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Contact Information
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Korea
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Japan
Switzerland
Tel: 886-2-2748-3380
Fax: 886-2-2748-3390
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Tel: 82-2-527-4377
Fax: 82-2-527-4376
Tel: 86-21-6391-0830
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