®

L5991

L5991A

PRIMARY CONTROLLER WITH STANDBY

CURRENT-MODE CONTROL PWM

SWITCHING FREQUENCY UP TO 1MHz

LOW START-UP CURRENT (< 120

µ

A)

HIGH-CURRENT OUTPUT DRIVE SUITABLE

FOR POWER MOSFET (1A)

FULLY LATCHED PWM LOGIC WITH DOU-

BLE PULSE SUPPRESSION

PROGRAMMABLE DUTY CYCLE

100% AND 50% MAXIMUM DUTY CYCLE LIMIT

STANDBY FUNCTION

PROGRAMMABLE SOFT START

PRIMARY OVERCURRENT FAULT DETEC-

TION WITH RE-START DELAY

PWM UVLO WITH HYSTERESIS

IN/OUT SYNCHRONIZATION

LATCHED DISABLE

INTERNAL 100ns LEADING EDGE BLANK-

ING OF CURRENT SENSE

PACKAGE: DIP16 AND SO16

DESCRIPTION

This primary controller I.C., developed in BCD60II technology, has been designed to implement off

BLOCK DIAGRAM

SYNC

1

TIMING

DC-LIM

15

RCT

2

DC

3

DIS

14

2.5V

-

+

+

-

DIS

T

8

V

CC

25V

15V/10V

+

-

MULTIPOWER BCD TECHNOLOGY

DIP16

ORDERING NUMBERS: L5991/L5991A (DIP16)

L5991D/L5991AD (SO16) line or DC-DC power supply applications using a fixed frequency current mode control.

Based on a standard current mode PWM controller this device includes some features such as programmable soft start, IN/OUT synchronization, disable (to be used for over voltage protection and for power management), precise maximum Duty

Cycle Control, 100ns leading edge blanking on current sense, pulse by pulse current limit, overcurrent protection with soft start intervention, and

Standby function for oscillator frequency reduction when the converter is lightly loaded.

PWM UVLO

Vref

VREF

4

SO16

9

V

C

13V

10

OUT

BLANKING S Q

R

PWM

ISEN

SS

OVER CURRENT

13

7

1.2V

+

-

FAULT

SOFT-START

2R

VREF OK

CLK

DIS

+

E/A

-

VREF

STAND-BY

2.5V

11

PGND

16

ST-BY

5

VFB

1V R

12

SGND

6

COMP

D97IN725A

August 2001 1/23

L5991 - L5991A

ABSOLUTE MAXIMUM RATINGS

Symbol

I

V

CC

OUT

P tot

T j

T stg

Parameter

Supply Voltage (I

CC

< 50mA) (*)

Output Peak Pulse Current

Analog Inputs & Outputs (6,7)

Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16)

Power Dissipation @ T amb

@ T amb

= 70

°

C (DIP16)

= 50

°

C (SO16)

Junction Temperature, Operating Range

Storage Temperature, Operating Range

(*) maximum package power dissipation limits must be observed

PIN CONNECTION

Value

selflimit

1.5

-0.3 to 8

-0.3 to 6

1

0.83

-40 to 150

-55 to 150

SYNC

RCT

DC

VREF

VFB

COMP

SS

V

CC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ST-BY

DC-LIM

DIS

ISEN

SGND

PGND

OUT

V

C

THERMAL DATA

Symbol

R th j-amb

Parameter

Thermal Resistance Junction -Ambient (DIP16)

Thermal Resistance Junction -Ambient (SO16)

PIN FUNCTIONS

11

12

13

14

15

7

8

9

10

5

6

3

4

N.

1

2

16

Name

SYNC

RCT

DC

VREF

VFB

COMP

SS

V

CC

V

C

OUT

PGND

SGND

ISEN

DIS

DC-LIM

ST-BY

Value

80

120

Unit

°

C/W

°

C/W

Function

Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct

Oscillator pin for external C

T

, R

A

, R

B

components

Duty Cycle control

5.0V +/-1.5% reference voltage @ 25°C

Error Amplifier Inverting input

Error Amplifier Output

Soft start pin for external capacitor Css

Supply for internal "Signal" circuitry

Supply for Power section

High current totem pole output

Power ground

Signal ground

Current sense

Disable. It must never be left floating. TIE to SGND if not used.

Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is imposed

Standby. Connect a resistor to RCT. Connect to VREF or floating if not used.

Unit

V

A

V

V

W

W

°

C

°

C

2/23

L5991 - L5991A

ELECTRICAL CHARACTERISTICS (V

CC

= 15V; T j

= 0 to 105

°

C; R

T unless otherwise specified.)

= 13.3k

Ω

(*) C

T

= 1nF;

Test Condition Min.

Typ.

Max.

Symbol Parameter

REFERENCE SECTION

V

REF

Output Voltage

Line Regulation

Load Regulation

I

T

S

OS

Temperature Stability

Total Variation

Short Circuit Current

Power Down/UVLO

OSCILLATOR SECTION

Initial Accuracy

Duty Cycle

T j

= 25

°

C; I

O

= 1mA

V

CC

= 12 to 20V; T j

= 25°C

I

O

= 1 to 10mA; T j

= 25°C

Line, Load, Temperature

Vref = 0V

V

CC

= 6V; I sink

= 0.5mA

pin 15 = Vref; T j

= 25°C; V comp

= 4.5V

pin 15 = Vref; V

CC

= 12 to 20V

V comp

= 4.5V

pin 15 = Vref; V

CC

= 12 to 20V

V comp

= 2V pin 3 = 0,7V, pin 15 = V

REF pin 3 = 0.7V, pin 15 = OPEN pin 3 = 3.2V, pin 15 = V

REF pin 3 = 3.2V, pin 15 = OPEN pin 3 = 2.79V, pin 15 = OPEN

4.925

4.80

30

95

93

46.5

47

93

75

2.8

0.75

5.0

2.0

2.0

0.4

5.0

0.2

100

100

50

80

3.0

0.9

5.075

10

10

5.130

150

0.5

105

107

53.5

0

0

85

3.2

1.05

Duty Cycle Accuracy

Oscillator Ramp Peak

Oscillator Ramp Valley

ERROR AMPLIFIER SECTION

Input Bias Current

V

I

G

OPL

SVR

V

OL

V

OH

I

O

Input Voltage

Open Loop Gain

Supply Voltage Rejection

Output Low Voltage

Output High Voltage

Output Source Current

Output Sink Current

S

R

Unit Gain Bandwidth

Slew Rate

PWM CURRENT SENSE SECTION

I

I b

S

Input Bias Current

Maximum Input Signal

Delay to Output

Gain

V t

Fault Threshold Voltage

SOFT START SECTION

I

I

SSC

SSD

V

SSSAT

SS Charge Current

SS Discharge Current

SS Saturation Voltage

V

SSCLAMP

SS Clamp Voltage

LEADING EDGE BLANKING

Internal Masking Time

OUTPUT SECTION

V

OL

V

OH

Output Low Voltage

Output High Voltage

V

OUT CLAMP

Output Clamp Voltage

Collector Leakage

(*) R

T

= R

A

//R

B

, R

A

= R

B

= 27k

Ω

, see Fig. 23.

V

FB

to GND

V

COMP

= V

FB

V

COMP

= 2 to 4V

V

CC

= 12 to 20V

I sink

= 2mA

I source

= 0.5mA, V

FB

= 2.3V

V

COMP

> 4V, V

FB

= 2.3V

V

COMP

= 1.1V, V

FB

= 2.7V

I sen

= 0

V

COMP

= 5V

T j

= 25

°

C

VSS = 0.6V T j

= 25

°

C

DC = 0%

I

O

= 250mA

I

O

= 20mA; V

CC

= 12V

I

O

= 200mA; V

CC

= 12V

I

O

= 5mA; V

CC

= 20V

V

CC

= 20V V

C

= 24V

2.42

60

5

0.5

2

1.7

0.92

2.85

1.1

14

5

10

9

6

1.3

6

4

8

0.2

2.5

90

85

3

1.0

70

3

1.2

20

10

7

100

10.5

10

13

2

3.0

2.58

1.1

2.5

15

1.08

100

3.15

1.3

26

15

0.6

1.0

20

Unit

V mV mV mV/

°

C

V mA

V kHz kHz kHz

µ

A

µ

A

V

V ns

V

V

V

V

µ

A

%

%

%

%

%

V

V

V

V mA mA

µ

A

V dB dB

MHz

V/

µ s

µ

A

V ns

V/V

V

3/23

L5991 - L5991A

ELECTRICAL CHARACTERISTICS (continued.)

Symbol Parameter

OUTPUT SECTION

Fall Time

Test Condition Min.

Typ.

Max.

Unit

UVLO Saturation

SUPPLY SECTION

V

CCON

Startup voltage

V

CCOFF

V hys

I

S

I op

I q

Rise Time

Minimum Operating

Voltage

UVLO Hysteresis

Start Up Current

Operating Current

Quiescent Current

C

O

= 1nF

C

O

= 2.5nF

C

O

= 1nF

C

O

= 2.5nF

V

CC

= V

C

= 0 to V

CCON;

I sink

= 10mA

Before Turn-on at:

V

CC

= V

C

= V

CCON

-0.5V

C

T

= 1nF, R

T

= 13.3k

Ω

, C

O

=1nF

(After turn on), CT = 1nF,

R

T

= 13.3k

Ω

, C

O

=0nF

I

8

= 20mA

L5991

L5991A

L5991

L5991A

L5991

L5991A

14

7.8

9

7

4.5

0.5

40

20

35

50

70

15

8.4

10

7.6

5

0.8

75

9

7.0

60

100

1.0

16

9

11

8.2

120

13

10 ns ns ns ns

V mA mA

V

Z

Zener Voltage

STANDBY FUNCTION

V

REF

-V

ST-BY

V

T1

Standby Threshold

I

ST-BY

= 2mA

V comp

Falling

V comp

Rising

21 25

45

2.5

4.0

30 V mV

V

V

SYNCHRONIZATION SECTION

V

1

I

1

V

1

Clock Amplitude

Clock Source Current

Sync Pulse

Master Operation

I

SOURCE

= 0.8mA

Vclock = 3.5V

Slave Operation

Low Level

High Level

VSYNC = 3.5V

I

1

Sync Pulse Current

OVER CURRENT PROTECTION

V t

Fault Threshold Voltage

DISABLE SECTION

I qSH

Shutdown threshold

Input Bias Current

Quiescent current After

Disable

V pin14

= 0 to 3V

V

CC

= 15V

Figure 1. L5991 - Quiescent current vs. input voltage.

(X = 7.6V and Y= 8.4V for L5991A)

Iq [m A ]

3 0

4

3

3.5

0.5

1.1

2.4

-1

7

1.2

2.5

330

1

1.3

2.6

1

V mA

V

V mA

V

V

µ

A

µ

A

Figure 2. L5991 - Quiescent current vs. input voltage (after disable).

(X = 7.6V and Y= 8.4V for L5991A)

I q [ µ A ]

3 5 0

2 0

V 1 4 = 0 , P in 2 = o p e n

T j = 2 5 °C

3 0 0

8

2 5 0

V

V

V

V

V

V

µ

A

6

2 0 0

4

1 5 0

1 0 0

V 1 4 = V r e f

T j = 2 5 ° C

0 .2

0 .1 5

0 .1

0 .0 5

0

0 4 8

X

Y

1 2 1 6

V c c [V ]

2 0 2 4

2 8

5 0

0

0 4 8

X

Y

1 2

V c c [ V ]

1 6 2 0 2 4

4/23

Figure 3. Quiescent current vs. input voltage.

Iq [m A ]

9 .0

8 .5

V 1 4 = 0 , V 5 = V re f

R t = 4 .5 Ko h m ,T j = 2 5 °C

1 M h z

5 0 0 K h z

3 0 0 K h z

8 .0

1 0 0 K h z

7 .5

L5991 - L5991A

Figure 4. Quiescent current vs. input voltage and switching frequency.

Iq [m A ]

3 6

3 0

2 4

1 8

1 2

6

0

8

C o = 1 n F, T j = 2 5 °C

D C = 0 %

1 M H z

5 00 K H z

3 00 K H z

1 00 K H z

1 0 1 2 1 4 1 6

V c c [V ]

1 8 2 0

Figure 6. IC Consumption vs. Temperature.

2 2

7 .0

8 1 0 1 2 1 4 1 6

V c c [V ]

1 8 2 0 2 2 2 4

Figure 5. Quiescent current vs. input voltage and switching frequency.

Iq [mA]

36

Co = 1nF, Tj = 25°C

30

DC = 100%

1MHz

24

18

12

500KHz

300KHz

100KHz

6

0

8 10 12 14

Vcc [V]

16 18 20

Figure 7. Reference voltage vs. load current.

Vref [V]

5.1

22

5.05

Vcc=15V

Tj = 25°C

5

[mA]

100

10

1

Quiescent current

Vcc =15V, after turn-on

RT=13.3 k

Ω

, CT=1nF

DC = 0

Vcc = 15V

Iref = 1mA

Operating current

Vcc =15V, after turn-on

RT=13.3k

Ω

, CT=1nF

DC=75%, Co=1nF

0.1

0.01

-50 -25

Start-up current

Vc=Vcc= Vccon-0.5V, before turn-on

0 25 50 75 100 125 150

Junction temperature [˚C]

Figure 8. Vref vs. junction temperature.

Vref [V])

5.1

5.05

5

4.95

4.95

4.9

0 5 10

Iref [mA]

15 20 25

4.9

-50 -25 0 25 50

Tj (°C)

75 100 125 150

5/23

L5991 - L5991A

Figure 9. Vref vs. junction temperature.

Vref [V]

5.1

5.05

Vcc = 15V

Iref= 20mA

5

Figure 10. Vref SVRR vs. switching frequency.

SVRR (dB)

120

Vcc=15V

Vp-p=1V

80

4.95

40

4.9

-50 -25 0 25 50

Tj (°C)

75

Figure 11. Output saturation.

16

Vsat = V [V]

10

100 125 150

14

Vcc = Vc = 15V

Tj = 25°C

12

0

1 10 100 1000 fsw (Hz)

Figure 12. Output saturation.

2.5

V sat = V [V]

10

2

Vc c = Vc = 15V

T j = 25°C

10000

10

1.5

1

8

6

0 0.2

0.4

0.6

Isource [A]

0.8

Figure 13. UVLO Saturation

Ipin10 [mA]

50

40

Vcc < Vccon before turn-on

30

1 1.2

20

10

0

0 200 400 600 800 1,000 1,200 1,400

Vpin10 [mV]

6/23

0.5

0

0 0.2

0.4

0.6

Isink [A ]

0.8

1 1.2

Figure 14. Timing resistor vs. switching frequency.

fsw (KHz)

5000

2000

1000

500

200

100

50

20

10

5.6nF

Vcc = 15V, V15 =0V

Tj = 25°C

2.2nF

100pF

220pF

470pF

1nF

10 20

Rt (kohm)

30 40

Figure 15. Switching frequency vs. temperature.

fsw (KHz)

320

310

Rt= 4.5Kohm, Ct = 1nF

Vcc = 15V, V15=Vref

300

L5991 - L5991A

Figure 16. Switching frequency vs. temperature.

fsw (KHz)

320

310

300

Rt= 4.5Kohm, Ct = 1nF

Vcc = 15V, V15= 0

290

290

280

-50 -25 0 25 50

Tj (°C)

75 100 125 150

Figure 17. Dead time vs Ct.

Dead time [ns]

1,500

1,200

900

600

300

Rt =4.5Kohm

V15 = 0V

V15 = Vref

2.5

2

1.5

280

-50 -25 0 25 50

Tj (°C)

75 100 125 150

Figure 18. Maximum Duty Cycle vs Vpin3.

DC Control Voltage Vpin3 [V]

3.5

V15 = Vref

3

V15 = 0V

Rt = 4.5Kohm,

Ct = 1nF

2 4 6

Timing capacitor Ct [nF]

8 10

Figure 19. Delay to output vs junction temperature.

42

Delay to output (ns)

40

38

36

34

32

30

28

-50 -25 0 25 50

Tj (°C)

75

PIN10 = OPEN

1V pulse on PIN13

100 125 150

1

0 10 20 30 40 50 60 70 80 90 100

Duty Cycle [%]

Figure 20. E/A frequency response.

G [dB]

150

100

50

0

0.01

0.1

1

Phase

140

120

60

40

100

80

10 f (KHz)

20

100 1000 10000 100000

7/23

L5991 - L5991A

STANDBY FUNCTION

The standby function, optimized for flyback topology, automatically detects a light load condition for the converter and decreases the oscillator frequency on that occurrence. The normal oscillation frequency is automatically resumed when the output load builds up and exceeds a defined threshold.

This function allows to minimize power losses related to switching frequency, which represent the majority of losses in a lightly loaded flyback, without giving up the advantages of a higher switching frequency at heavy load.

This is accomplished by monitoring the output of the Error Amplifier (V

COMP

) that depends linearly on the peak primary current, except for an offset.

If the the peak primary current decreases (as a result of a decrease of the power demanded by the load) and V

COMP

falls below a fixed threshold

(V

T1

), the oscillator frequency will be set to a lower value (f

SB

). When the peak primary current increases and V

COMP

exceeds a second threshold

(V

T2

) the oscillator frequency is set to the normal value (f osc

). An appropriate hysteresis (V

T2

-V

T1

) prevents undesired frequency change when power is such that V

COMP

moves close to the threshold. This operation is shown in fig. 21.

Both the normal and the standby frequency are externally programmable. V

T1

and V

T2

are internally fixed but it is possible to adjust the thresholds in terms of input power level.

APPLICATION INFORMATION

Detailed Pin Function Description

Pin 1. SYNC (In/Out Synchronization). This function allows the IC’s oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave).

As a master, the pin delivers positive pulses during the falling edge of the oscillator (see pin 2). In slave operation the circuit is edge triggered. Refer to fig. 23 to see how it works. When several IC work in parallel no master-slave designation is needed because the fastest one becomes auto-

Figure 22. Synchronizing the L5991.

R

B

SYNC

1

L5991

16

4

ST-BY

VREF

2

R

A

RCT

C

T

(a)

Figure 21. Standby dynamic operation.

Pin

P

NO

P

SB

SYNC

1

L5991

2

RCT

R

OSC

L4981A

(MASTER)

16

17 18

C

OSC

SYNC

ST-BY

16

L5991

1

(SLAVE)

4

2

RCT

VREF

R

A

C

T

R

B

(b)

Normal operation

Stand-by f osc f

SB

1 2

V

T1

VCOMP

3

V

T2

4 matically the master.

During the ramp-up of the oscillator the pin is pulled low by a 600

µ

A internal sink current generator. During the falling edge, that is when the pulse is released, the 600

µ

A pull-down is disconnected. The pin becomes a generator whose source capability is typically 7mA (with a voltage still higher than 3.5V).

In fig. 22, some practical examples of synchronizing the L5991 are given.

Since the device automatically diminishes its operating frequency under light load conditions, it is reasonable to suppose that synchronization will refer to normal operation and not to standby.

Pin 2. RCT (Oscillator). Two resistors (R

A

and R

B

) and one capacitor (C

T

), connected as shown in fig. 23, allow to set separately the operating frequency of the oscillator in normal operation (f osc

) and in standby mode (f

SB

).

C

T

is charged from Vref through R

A

and R

B

in normal operation (STANDBY = HIGH), through R

A only in standby ( STANDBY = LOW). See pin 16 description to see how the STANDBY signal is generated.

When the voltage on C

T

reaches 3V, the capacitor is quickly internally discharged. As the voltage has dropped to 1V it starts being charged again.

RCT

R

B

VREF

4

2

L5991

(MASTER)

1

16

SYNC

ST-BY

C

T

R

A

SYNC

L4981A

(SLAVE)

16

17 18

R

OSC C

OSC

D97IN728A

(c)

8/23

L5991 - L5991A

Figure 23. Oscillator and synchronization internal schematic.

V

REF

4

R1

CLAMP

R

A

C

T

RCT 2

R

B

ST-BY 16

STANDBY

D1

50

Ω

R3 R2

+

-

SYNC

1

600

µ

A

D

R

Q

CLK

D97IN729A

The oscillation frequency can be established with the aid of the diagrams of fig. 14, where R

T

will be intended as the parallel of R

A

and R

B

in normal operation and R

T

= R

A

in standby, or considering the following approximate relationships: f osc

≅

1

C

T

⋅ (

0.693

⋅ (

R

A

// R

B

) +

K

T

(

1

)

, which gives the normal operating frequency, and: f

SB

≅

1

C

T

⋅ (

0.693

⋅

R

A

+

K

T

)

(

2

)

, which gives the standby frequency, that is the one the converter will operate at when lightly loaded.

In the above expressions, RA // RB means:

R

A

//

R

B

=

R

A

⋅

R

B

R

A

+

R

B

, while K

T

is defined as:

K

T

=



90 V

15

=

160

V

15

=

VREF

GND

/OPEN

(

3

)

, and is related to the duration of the falling-edge of the sawtooth:

T d

≈

30

⋅

10

−

9 +

K

T

⋅

C

T

(

4

)

.

T d

is also the duration of the sync pulses delivered at pin 1 and defines the upper extreme of the duty cycle range, D x

(see pin 15 for D

X

definition and calculation) since the output is held low during the falling edge.

In case V15 is connected to VREF, however, the switching frequency will be a half the values taken from fig. 14 or resulting from (1) and (2).

To prevent the oscillator frequency from switching back and forth from f osc

to f

SB

, the ratio f osc

/ f

SB must not exceed 5.5.

If during normal operation the IC is to be synchronized to an external oscillator, R

A

, R

B

and C

T should be selected for a f osc

lower than the master frequency in any condition (typically, 10-20% ), depending also on the tolerance of the parts.

Pin 3. DC (Duty Cycle Control). By biasing this pin with a voltage between 1 and 3 V it is possible to set the maximum duty cycle between 0 and the upper extreme D x

(see pin 15).

If D max

is the desired maximum duty cycle, the voltage V3 to be applied to pin 3 is:

V

3

= 5 - 2

(2-Dmax)

(5)

D max

is determined by internal comparison between V3 and the oscillator ramp (see fig. 24), thus in case the device is synchronized to an external frequency f ext

(and therefore the oscillator amplitude is reduced), (5) changes into:

V

3

=

5

−

4

⋅

exp







−

D max

R

T

⋅

C

T

⋅

f ext







(6)

A voltage below 1V will inhibit the driver output stage. This could be used for a not-latched device disable, for example in case of overvoltage protection (see application ideas).

If no limitation on the maximum duty cycle is required (i.e. D

MAX

= D

X

), the pin has to be left floating. An internal pull-up (see fig. 24) holds the voltage above 3V. Should the pin pick up noise (e.g.

9/23

L5991 - L5991A

during ESD tests), it can be connected to VREF through a 4.7k

Ω

resistor.

Figure 24. Duty cycle control.

R

A

V

REF

4

R1

DC 3

R2

ST-BY

R

B

RCT

16

2

3

µ

A

23K

28K

+

-

TO PWM LOGIC

C

T

D97IN727A

Pin 4. VREF (Reference Voltage). The device is provided with an accurate voltage reference

(5V

±

1.5%) able to deliver some mA to an external circuit.

A small film capacitor (0.1

µ

F typ.), connected between this pin and SGND, is recommended to ensure the stability of the generator and to prevent noise from affecting the reference.

Before device turn-on, this pin has a sink current capability of 0.5mA.

Pin 5. VFB (Error Amplifier Inverting Input). The feedback signal is applied to this pin and is compared to the E/A internal reference (2.5V). The

E/A output generates the control voltage which fixes the duty cycle.

The E/A features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current capability, which improves its large signal behavior.

Usually the compensation network, which stabilizes the overall control loop, is connected between this pin and COMP (pin 6).

Pin 6. COMP (Error Amplifier Output). Usually, this pin is used for frequency compensation and the relevant network is connected between this pin and VFB (pin 5). Compensation networks towards ground are not possible since the L5991

E/A is a voltage mode amplifier (low output impedance). See application ideas for some example of compensation techniques.

It is worth mentioning that the calculation of the part values of the compensation network must take the standby frequency operation into account. In particular, this means that the open-loop crossover frequency must not exceed f

SB

/4

÷ f

SB

/5.

The voltage on pin 6 is monitored in order to re-

10/23 duce the oscillator frequency when the converter is lightly loaded (standby).

Pin 7. SS (Soft-Start). At device start-up, a capacitor (Css) connected between this pin and

SGND (pin 12) is charged by an internal current generator, ISSC, up to about 7V. During this ramp, the E/A output is clamped by the voltage across Css itself and allowed to rise linearly, starting from zero, up to the steady-state value imposed by the control loop. The maximum time interval during which the E/A is clamped, referred to as soft-start time, is approximately:

T ss

≅

3

⋅

R sense

⋅

I

Qpk

I

SSC

⋅

C ss

(7) where R sense

is the current sense resistor (see pin

13) and I

Qpk

is the switch peak current (flowing through R sense

), which depends on the output load. Usually, C

SS

is selected for a T

SS

in the order of milliseconds.

As mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. Referring to fig. 25, pulse-by-pulse current limitation is somehow effective as long as

Figure 25. Regulation characteristic and related quantities.

V

OUT

I

Qpk

A

D.C.M.

C.C.M.

1-2 ·I

Qpk

I

Qpk(max)

C

B

T

ON

D

D97IN495

I

SHORT

I

OUT(max)

T

ON(min)

I

OUT the ON-time of the power switch can be reduced

(from A to B). After the minimum ON-time is reached (from B onwards) the current is out of control.

To prevent this risk, a comparator trips an overcurrent handling procedure, named ’hiccup’ mode operation, when a voltage above 1.2V (point C) is detected on current sense input (ISEN, pin 13).

Basically, the IC is turned off and then soft-started as long as the fault condition is detected. As a result, the operating point is moved abruptly to D, creating a foldback effect. Fig. 26 illustrates the operation.

The oscillation frequency appearing on the softstart capacitor in case of permanent fault, referred to as ’hiccup" period, is approximately given by:

T hic

≅

4.5

⋅







1

I

SSC

+

1

I

SSD







⋅

C ss

(

8

)

Since the system tries restarting each hiccup cycle, there is not any latchoff risk.

"Hiccup" keeps the system in control in case of short circuits but does not eliminate power components overstress during pulse-by-pulse limitation (from A to C). Other external protection circuits are needed if a better control of overloads is required.

L5991 - L5991A

MOS. At turn-on the gate resistance is R g

+ R g’

, at turn-off is R g

only.

Figure 27. Turn-on and turn-off speeds adjustment.

Rg'

Pin 8. VCC (Controller Supply). This pin supplies the signal part of the IC. The device is enabled as

VCC voltage exceeds the start threshold and works as long as the voltage is above the UVLO threshold. Otherwise the device is shut down and the current consumption is extremely low

(<150

µ

A). This is particularly useful for reducing the consumption of the start-up circuit (in the simplest case, just one resistor), which is one of the most significant contributions to power losses in standby.

An internal Zener limits the voltage on VCC to

25V. The IC current consumption increases considerably if this limit is exceeded.

A small film capacitor between this pin and SGND

(pin 12), placed as close as possible to the IC, is recommended to filter high frequency noise.

Pin 9. VC (Supply of the Power Stage). It supplies the driver of the external switch and therefore absorbs a pulsed current. Thus it is recommended to place a buffer capacitor (towards PGND, pin 11, as close as possible to the IC) able to sustain these current pulses and in order to avoid them inducing disturbances.

This pin can be connected to the buffer capacitor directly or through a resistor, as shown in fig. 27, to control separately the turn-on and turn-off speed of the external switch, typically a Power-

Figure 26. Hiccup mode operation.

I

OUT

SHORT

V

CC

8

13V

DRIVE &

CONTROL

L5991

D97IN726

V

C

9

PGND

11

10

OUT

Rg

Rg(ON)=Rg+Rg'

Rg(OFF)=Rg

Pin 10. OUT (Driver Output). This pin is the output of the driver stage of the external power switch. Usually, this will be a PowerMOS, although the driver is powerful enough to drive

BJT’s (1.6A source, 2A sink, peak).

The driver is made up of a totem pole with a highside NPN Darlington and a low-side VDMOS, thus there is no need of an external diode clamp to prevent voltage from going below ground. An internal clamp limits the voltage delivered to the gate at 13V. Thus it is possible to supply the driver (Pin 9) with higher voltages without any risk of damage for the gate oxide of the external MOS.

The clamp does not cause any additional increase of power dissipation inside the chip since the current peak of the gate charge occurs when the gate voltage is few volts and the clamp is not active. Besides, no current flows when the gate voltage is 13V, steady state.

Under UVLO conditions an internal circuit (shown

I

SEN

FAULT

SS

5V

0.5V

T hic

D98IN986

7V time

11/23

L5991 - L5991A

in fig.28) holds the pin low in order to ensure that the external MOS cannot be turned on accidentally. The peculiarity of this circuit is its ability to mantain the same sink capability (typically, 20mA

@ 1V) from V

CC

= 0V up to the start-up threshold.

When the threshold is exceeded and the L5991 starts operating, V

REFOK

is pulled high (refer to fig.

28) and the circuit is disabled.

It is then possible to omit the "bleeder" resistor

(connected between the gate and the source of the MOS) ordinarily used to prevent undesired switching-on of the external MOS because of some leakage current.

Figure 28. Pull-Down of the output in UVLO.

V

REFOK

10

OUT

12

SGND

D97IN538

Pin 11. PGND (Power Ground). The current loop during the discharge of the gate of the external

MOS is closed through this pin. This loop should be as short as possible to reduce EMI and run separately from signal currents return.

Pin 12. SGND (Signal Ground). This ground references the control circuitry of the IC, so all the ground connections of the external parts related to control functions must lead to this pin. In laying out the PCB, care must be taken in preventing switched high currents from flowing through the

SGND path.

Pin 13. ISEN (Current Sense). This pin is to be connected to the "hot" lead of the current sense resistor R sense

(being the other one grounded), to get a voltage ramp which is an image of the current of the switch (I

Q

). When this voltage is equal to:

V

13pk

=

I

Qpk

⋅

R sense

=

V

COMP

−

3

1.4

(

9

) the conduction of the switch is terminated.

To increase the noise immunity, a "Leading Edge

Blanking" of about 100ns is internally realized as shown in fig. 29. Because of that, the smoothing

RC filter between this pin and R sense

could be removed or, at least, considerably reduced.

Pin 14. DIS (Device Disable). When the voltage on pin 14 rises above 2.5V the IC is shut down and it is necessary to pull VCC (IC supply voltage, pin 8) below the UVLO threshold to allow the device to restart.

The pin can be driven by an external logic signal in case of power management, as shown in fig.

30. It is also possible to realize an overvoltage protection, as shown in the section " Application

Ideas".If used, bypass this pin to ground with a filter capacitor to avoid spurious activation due to noise spikes. If not, it must be connected to

SGND.

Pin 15. DC-LIM (Maximum Duty Cycle Limit). The upper extreme, Dx, of the duty cycle range depends on the voltage applied to this pin. Approximately,

D x

≅

R

T

R

T

+

230

(

10

) if DC-LIM is grounded or left floating. Instead,

Figure 29. Internal LEB.

ISEN

13

I

1.2V

2V

0

3V

+

-

CLK

FROM E/A

OVERCURRENT

COMPARATOR

+

-

+

-

PWM

COMPARATOR

TO PWM

LOGIC

D97IN503

TO FAULT

LOGIC

12/23

Figure 30. Disable (Latched).

DISABLE

SIGNAL

DIS 14

+

-

D

R

Q

DISABLE

C

2.5V

UVLO

D97IN502 connecting DC-LIM to VREF (half duty cycle option), Dx will be set approximately at:

D x

≅

R

T

2

⋅

R

T

+

260

(

11

)

Figure 31. Half duty cycle option.

t d

V15=GND

V5=V13=GND

L5991 - L5991A

and the output switching frequency will be halved with respect to the oscillator one because an internal T flip-flop (see block diagram) is activated.

Fig. 31 shows the operation.

The half duty cycle option speeds up the discharge of the timing capacitor C

T

(in order to get duty cycles as close to 50% as possible) so the oscillator frequency - with the same timing components will be slightly higher.

Pin 16. S-BY (Standby Function). The resistor R

B

, along with R

A

, sets the operating frequency of the oscillator in normal operation (f osc

). In fact, as long as the STANDBY signal is high, the pin is internally connected to the reference voltage VREF by a N-channel FET (see fig. 32), so the timing capacitor C

T

is charged through R

A

and R

B

. When the STANDBY signal goes low the N-channel FET is turned off and the pin becomes floating. R

B

is

V2

D

X

= tc tc + td t d

V10 tc

V15=VREF

V5=V13=GND

V2

D

X

= tc

2 ·tc + td

V10 tc

D97IN498

Figure 32. Standby function internal schematic and operation.

COMP

6 13

ISEN

2R

+

-

R

R

DRIVER

OUT

FB

5

2.5

-

+

10V

+

-

2.5/4

LEVEL SHIFT

STANDBY BLOCK

STANDBY

STANDBY

4

16

VREF

ST-BY

2

HIGH

R

B

R

A

RCT

C

T

LOW

D97IN752B

V

T1

2.5V

V

T2

4V

V

COMP

13/23

L5991 - L5991A

now disconnected and C

T

is charged through R

A only. In this way the oscillator frequency (f

SB

) will be lower. Refer to pin 2 description to see how to calculate the timing components.

Typical values for V

T1

and V

T2

are 2.5 V and 4V respectively. This 1.5V hysteresis is enough to prevent undesired frequency change up to a 5.5

to 1 f osc

/ f

SB

ratio.

The value of V

T1

is such that in a discontinuous flyback the standby frequency is activated when the input power is about 13% of the maximum. If necessary, it is possible to decrease the power threshold below 13% by adding a DC offset (V o

) on the current sense pin (13, ISEN). This will also allow a frequency change greater than 5.5 to 1.

The following equations, useful for design, apply:

P inSB

=

1

2

⋅

L

P

⋅ ƒ osc

⋅







0.367

−

V o

R sense







2

(

12

)

,

P inNO

=

1

2

⋅

L

P

⋅ ƒ

SB

⋅







0.867

−

V o

R sense







2

(

13

)

,

ƒ osc

ƒ

SB

<







0.867

−

V o

0.367

−

V o







2

(

14

)

, where P inSB

is the input power below which the

L5991 recognizes a light load and switches the oscillator frequency from

ƒ osc

to f

SB

, P inNO

is the input power above which the L5991 switches back from

ƒ

SB

to

ƒ osc

and L p

the primary inductance of the flyback transformer.

Connect to Vref or leave open this pin when stand-by function is not used.

Layout hints

Generally speaking a proper circuitboard layout is vital for correct operation but is not an easy task.

Careful component placing, correct traces routing, appropriate traces widths and, in case of high voltages, compliance with isolation distances are the major issues. The L5991 eases this task by putting two pins at disposal for separate current returns of bias (SGND) and switch drive currents

(PGND) The matter is complex and only few important points will be here reminded.

1) All current returns (signal ground, power ground, shielding, etc.) should be routed separately and should be connected only at a single ground point.

2) Noise coupling can be reduced by minimizing the area circumscribed by current loops. This applies particularly to loops where high pulsed currents flow.

3) For high current paths, the traces should be doubled on the other side of the PCB whenever possible: this will reduce both the resistance and the inductance of the wiring.

4) Magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying switched currents as short as possible.

5) In general, traces carrying signal currents should run far from traces carrying pulsed currents or with quickly swinging voltages. From this viewpoint, particular care should be taken of the high impedance points (current sense input, feedback input, ...). It could be a good idea to route signal traces on one PCB side and power traces on the other side.

6) Provide adequate filtering of some crucial points of the circuit, such as voltage references,

IC’s supply pins, etc.

14/23

L5991 - L5991A

APPLICATION IDEAS

Here follows a series of ideas/suggestions aimed at either improving performance or solving common application problems of L5991 based supplies.

Figure 33. Typical application circuit for computer monitors (90W).

15/23

L5991 - L5991A

Figure 34. Typical application circuit for inkjet printers (40W).

16/23

L5991 - L5991A

Figure 35. Standby thresholds adjustment.

SGND

12

4

L5991

13

VREF

10

ISEN

R

A

R

OPTIONAL

D97IN751A

R

SENSE

Figure 36. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies.

V

IN

ISOLATION

BOUNDARY

9

V

C

10 OUT

L5991

13

ISEN

PGND

12 11

SGND

Figure 37. Low consumption start-up.

V

IN

2.2M

Ω

33K

Ω

20V

47K

Ω

V

REF

STD1NB50-1

4

12

V

CC

8

L5991

11

D97IN762B

Figure 38. Bipolar transistor driver.

D97IN761

T

SELF-SUPPLY

WINDING

V

IN

8

V

CC

L5991

V

C

9

10 OUT

13

11

PGND

ISEN

D97IN763

17/23

L5991 - L5991A

Figure 39. Typical E/A compensation networks.

From V

O

R i

2.5V

+

1.3mA

R d

C f

VFB 5

+

-

EA

2R

R f

R

COMP 6 12

SGND

Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current.

From V

O

R

P

R i

VFB 5

2.5V

+

-

EA

+

1.3mA

2R

C

P

R d

C f

R f

R

COMP 6 12

SGND

D97IN507

Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current.

Figure 40. Feedback with optocoupler.

V

OUT

6

COMP

L5991

5

VFB

TL431

D97IN759

Figure 41. Slope compensation techniques.

I

R

B

R

SLOPE

R

SENSE

ST-BY

V

REF

R

A

RCT

C

T

16

4

2

L5991

ISEN

13

12

SGND

I

OPTIONAL

R

SLOPE

R

SENSE

R

B

ST-BY

V

REF

R

A

RCT

C

T

16

4

2

ISEN

L5991

13

12

SGND

OPTIONAL

10

OUT

R

L5991

SGND

12

13

ISEN

OPTIONAL

D97IN760A

R

SLOPE

C

SLOPE

R

SENSE

18/23

L5991 - L5991A

Figure 42. Protection against overvoltage/feedback disconnection (latched)

R

START

R

START

DIS

V

CC

14

12

8

L5991

11

SGND PGND

D97IN754

V

Z

DIS

2.2K

V

CC

14

12

8

L5991

11

SGND PGND

D98IN905

Figure 43 Protection against overvoltage/feed-

back disconnection (not latched)

Figure 44. Device shutdown on overcurrent

R

START

VREF

4

V

CC

8

DC

3

L5991

12 11

L5991

4

VREF

R

1

I pk max

≅

2.5

R

SENSE

• 1-

R

2

R

1

I pk

I

14

DIS

R

2

PGND

11

SGND

12

13

ISEN

OPTIONAL

R

SENSE

D97IN756A

D97IN755A

Figure 45. Constant power in pulse-by-pulse current limitation (flyback discontinuous)

V

IN

80

÷

400V

DC

Lp

R

FF

R

FF

= 6·10

6

R·Lp

RSENSE

PGND

OUT

L5991

10

11 12

13

SGND

ISEN

R

RSENSE

D97IN757

Figure 46. Voltage mode operation.

DC

3

10K

L5991

COMP

6

SGND

12 13

ISEN

D97IN758A

19/23

L5991 - L5991A

Figure 47. Device shutdown on mains undervoltage.

V

IN

80÷400V

DC

5.1

R1

R2

VREF

4.7K

4

L5991

3

10K

Ω

SGND

D97IN750B

12

PGND

11

Figure 48. Synchronization to flyback pulses (for monitors).

1K

Ω

5.1V

SYNC

1

L5991

12

SGND

D97IN753A

20/23

L

Z

F

I e e3

D

E a1

B b b1

DIM.

mm inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

0.51

0.77

1.65

0.020

0.030

0.065

0.5

0.25

0.020

0.010

20 0.787

8.5

2.54

17.78

3.3

7.1

5.1

1.27

0.335

0.100

0.700

0.130

0.280

0.201

0.050

L5991 - L5991A

OUTLINE AND

MECHANICAL DATA

DIP16

21/23

L5991 - L5991A

DIM.

G

L

M

S

E e e3

F (1) b1

C c1

D (1)

A a1 a2 b

mm inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

0.1

1.75

0.25

0.004

0.069

0.009

0.35

0.19

1.6

0.46

0.014

0.25

0.007

0.063

0.018

0.010

0.5

0.020

9.8

5.8

45˚ (typ.)

10 0.386

6.2

0.228

0.394

0.244

1.27

8.89

0.050

0.350

3.8

4.6

0.4

4

5.3

0.150

0.181

1.27

0.016

0.62

8˚(max.)

0.157

0.209

0.050

0.024

OUTLINE AND

MECHANICAL DATA

SO16 Narrow

(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).

22/23

L5991 - L5991A

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

© 2001 STMicroelectronics – Printed in Italy – All Rights Reserved

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23/23