L6392D скачать даташит
L6392
High-voltage high and low side driver
Features
■
High voltage rail up to 600 V
■
dV/dt immunity ± 50 V/nsec in full temperature
range
■
Driver current capability:
– 290 mA source
– 430 mA sink
■
Switching times 75/35 nsec rise/fall with 1 nF
load
■
3.3 V, 5 V TTL/CMOS inputs with hysteresis
■
Integrated bootstrap diode
■
Operational amplifier for advanced current
sensing
■
Adjustable dead-time
■
Interlocking function
■
Compact and simplified layout
■
Bill of material reduction
■
Flexible, easy and fast design
SO-14
DIP-14
Description
The L6392 is a high-voltage device manufactured
with the BCD “OFF-LINE” technology. It is a single
chip half-bridge gate driver for N-channel Power
MOSFET or IGBT.
The high side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP
The IC embeds an operational amplifier suitable
for advanced current sensing in applications such
as field oriented motor control.
Applications
■
Motor driver for home appliances, factory
automation, industrial drives.
■
HID ballasts, power supply units.
Table 1.
August 2010
Device summary
Order codes
Package
Packaging
L6392N
DIP-14
Tube
L6392D
SO-14
Tube
L6392DTR
SO-14
Tape and reel
Doc ID 14494 Rev 5
1/20
www.st.com
20
Contents
L6392
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.1
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Doc ID 14494 Rev 5
L6392
1
Block diagram
Block diagram
Figure 1.
VCC
Block diagram
BOOTSTRAP DRIVER
4
UV
DETECTION
FLOATING STRUCTURE
from LVG
14
BOOT
13
HVG
12
OUT
UV
DETECTION
HVG
DRIVER
HIN
3
LEVEL
SHIFTER
S
R
LOGIC
5V
SHOOT
THROUGH
PREVENTION
LIN
1
VCC
SD
GND
DT
LVG
DRIVER
LVG
10
2
7
5
DEAD
TIME
VCC
OPOUT
OPAMP
6
+
8
OP+
OP-
9
Doc ID 14494 Rev 5
3/20
Pin connection
2
L6392
Pin connection
Figure 2.
Table 2.
Pins connection (top view)
LIN
1
14
BOOT
SD
2
13
HVG
HIN
3
12
OUT
VCC
4
11
NC
DT
5
10
LVG
OPOUT
6
9
OP-
GND
7
8
OP+
Pin description
Pin N#
Pin name
Type
1
LIN
I
Low side driver logic input (active low)
I
Shut down logic input (active low)
2
SD
(1)
Function
3
HIN
I
High side driver logic input (active high)
4
VCC
P
Lower section supply voltage
5
DT
I
Dead time setting
6
OPOUT
O
Opamp output
7
GND
P
Ground
8
OP+
I
Opamp non inverting input
9
OP-
I
Opamp inverting input
O
Low side driver output
10
LVG
(1)
11
NC
12
OUT
(1)
13
HVG
14
BOOT
Not connected
P
High side (floating) common voltage
O
High side driver output
P
Bootstrapped supply voltage
1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows
to omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/20
Doc ID 14494 Rev 5
L6392
3
Truth table
Truth table
Table 3.
Truth table
Inputs
Note:
Outputs
SD
LIN
HIN
LVG
HVG
L
X
X
L
L
H
L
L
H
L
H
L
H
L
L
H
H
L
L
L
H
H
H
L
H
X: don’t care
Doc ID 14494 Rev 5
5/20
Electrical data
L6392
4
Electrical data
4.1
Absolute maximum ratings
Table 4.
Absolute maximum rating
Value
Symbol
Parameter
Unit
Min
Max
VCC
Supply voltage
- 0.3
+ 21
V
Vout
Output voltage
Vboot -21
Vboot +0.3
V
Vboot
Bootstrap voltage
- 0.3
620
V
Vhvg
High side gate output voltage
Vout - 0.3
Vboot + 0.3
V
VIvg
Low side gate output voltage
-0.3
VCC + 0.3
V
Vop+
Opamp non-inverting input
-0.3
VCC + 0.3
V
Vop-
Opamp inverting input
-0.3
VCC + 0.3
V
Logic input voltage
-0.3
15
V
50
V/ns
Vi
dVout/dt
Allowed output slew rate
Ptot
Total power dissipation (TA = 25 °C)
800
mW
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
-50
Note:
ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (Human body model)
4.2
Thermal data
Table 5.
Symbol
Rth(JA)
6/20
Thermal data
Parameter
Thermal resistance junction to ambient
Doc ID 14494 Rev 5
SO-14
DIP-14
Unit
165
100
°C/W
L6392
4.3
Electrical data
Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Pin
VCC
4
VBO (1)
Vout
Min
Max
Unit
Supply voltage
12.5
20
V
14-12 Floating supply voltage
12.4
20
V
580
V
800
kHz
125
°C
12
Parameter
Test condition
DC output voltage
fsw
Switching frequency
TJ
Junction temperature
-9
(2)
HVG, LVG load CL = 1nF
-40
1. VBO = Vboot -Vout
2. LVG off. VCC = 12.5 V.
Logic is operational if Vboot > 5 V.
Doc ID 14494 Rev 5
7/20
Electrical characteristics
L6392
5
Electrical characteristics
5.1
AC operation
Table 7.
AC operation electrical characteristics (VCC = 15 V; TJ =+25 °C)
Symbol
ton
toff
tsd
Pin
tf
Typ
Max
Unit
50
125
200
ns
50
125
200
ns
50
125
200
ns
30
ns
5
Dead time setting range
(1)
Matching dead time (2)
RDT = 0; CL = 1 nF; CDT = 100 nF
0.1
0.18
0.25
RDT = 37 kΩ;CL = 1 nF; CDT=100 nF
0.48
0.6
0.72
RDT = 136 kΩ;CL=1 nF; CDT=100 nF
1.35
1.6
1.85
RDT = 260 kΩ;CL=1 nF; CDT=100 nF
2.6
3.0
3.4
RDT = 0 Ω; CL=1 nF; CDT =100 nF
80
RDT = 37 kΩ;CL=1 nF; CDT=100 nF
120
RDT = 136 kΩ;CL=1 nF; CDT=100 nF
250
RDT = 260 kΩ;CL=1 nF; CDT=100 nF
400
μs
ns
Rise time
CL = 1 nF
75
120
ns
Fall time
CL = 1 nF
35
70
ns
10, 13
1. See Figure 4 on page 9
2. MDT = | DTLH - DTHL | see Figure 5 on page 13
8/20
Min
Delay matching, HS and
LS turn-on/off
MDT
tr
Test condition
High/low side driver turnVout = 0 V
1 vs 10 on propagation delay
= Vcc
V
3 vs 13 High/low side driver turn- boot
CL = 1 nF
off propagation delay
Vi = 0 to 3.3 V
2 vs Shut down to high/low
See Figure 3
10, 13 side propagation delay
MT
DT
Parameter
Doc ID 14494 Rev 5
L6392
Electrical characteristics
Figure 3.
Timing characteristics
50%
LIN
50%
tr
tf
90%
LVG
90%
10%
10%
ton
toff
50%
HIN
50%
tr
tf
90%
HVG
90%
10%
10%
ton
toff
50%
SD
tf
90%
LVG/HVG
10%
tsd
Figure 4.
Typical dead time vs. DT resistor value
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Doc ID 14494 Rev 5
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Electrical characteristics
L6392
5.2
DC operation
Table 8.
DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Vcc UV hysteresis
1200
1500
1800
mV
Vcc_thON
Vcc UV turn ON
threshold
11.5
12
12.5
V
Vcc_thOFF
Vcc UV turn OFF
threshold
10
10.5
11
V
Undervoltage quiescent
supply current
VCC = 10 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
120
150
μA
Quiescent current
VCC = 15 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
680
1000
μA
Low supply voltage section
Vcc_hys
Iqccu
4
Iqcc
Bootstrapped supply voltage section (1)
VBO_hys
VBO UV hysteresis
1200
1500
1800
mV
VBO_thON
VBO UV turn ON
threshold
10.6
11.5
12.4
V
VBO_thOFF
VBO UV turn OFF
threshold
9.1
10
10.9
V
Undervoltage VBO
quiescent current
VBO = 9 V
SD = 5 V; LIN and HIN = 5 V;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
70
110
μA
IQBO
VBO quiescent current
VBO = 15 V
SD = 5 V; LIN and HIN = 5 V;
RDT = 0 Ω;
OP + = GND; OP - = 5 V
150
210
μA
ILK
High voltage leakage
current
Vhvg = Vout = Vboot = 600 V
10
μA
Bootstrap driver on
resistance (2)
LVG ON
14
IQBOU
RDS(on)
10/20
Doc ID 14494 Rev 5
120
Ω
L6392
Table 8.
Symbol
Electrical characteristics
DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) (continued)
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Driving buffers section
Iso
High/low side source
short circuit current
Vi = Vih (tp < 10 ms)
200
290
mA
High/low side sink short
circuit current
Vi = Vil (tp < 10 ms)
250
430
mA
10, 13
Isi
Logic inputs
Vil
Low logic level voltage
0.8
High logic level voltage
Vih
1, 3
2.25
Single input voltage
LIN and HIN connected together
and floating
HIN logic “1” input bias
current
HIN = 15 V
IHINl
HIN logic “0” input bias
current
HIN = 0 V
ILINI
LIN logic “0” input bias
current
LIN = 0 V
ILINh
LIN logic “1” input bias
current
LIN = 15 V
ISDh
SD logic “1” input bias
current
SD = 15 V
SD logic “0” input bias
current
SD = 0 V
Vil_S
V
1, 2, 3
IHINh
110
V
175
0.8
V
260
μA
1
μA
20
μA
1
μA
100
μA
1
μA
3
3
6
1
10
30
2
ISDl
1. VBO = Vboot - Vout
2. RDSon is tested in the following way:
RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 14 current when
VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
Doc ID 14494 Rev 5
11/20
Electrical characteristics
Table 9.
Symbol
OPAMP characteristics (VCC = 15 V, TJ = +25 °C)
Pin
Parameter
Test condition
Input offset voltage
Vio
Iio
Iib
L6392
Min
Input bias current
Max
Unit
6
mV
4
40
nA
100
200
nA
VCC-4
V
150
mV
Vic = 0 V, Vo = 7.5 V
Input offset current
8, 9
Typ
Vic = 0 V, Vo = 7.5 V
(1)
Vicm
Input common mode voltage
range
VOL
Low level output voltage
RL = 10 kΩ to VCC
VOH
High level output voltage
RL = 10 kΩ to GND
14
14.7
V
Source,
Vid = + 1 V; Vo = 0 V
16
30
mA
Sink
Vid = -1 V; Vo = VCC
50
80
mA
Slew rate
Vi = 1÷4;
CL = 100 pF; unity gain
2.5
3.8
V/μs
GBWP
Gain bandwidth product
Vo = 7.5 V
8
12
MHz
Avd
Large signal voltage gain
RL = 2 kΩ
70
85
dB
SRV
Power supply rejection ratio
vs Vcc
60
75
dB
55
70
dB
6
Io
SR
CMRR
Output short circuit current
0
Common mode rejection
ratio
1. The direction of input current is out of the IC.
12/20
Doc ID 14494 Rev 5
75
L6392
Waveforms definitions
6
Waveforms definitions
Figure 5.
Dead time - timing waveforms
INTE
RLO
CKIN
G
HIN
INTE
RLO
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CKIN
G
LIN
LVG
DTHL
DTLH
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
Doc ID 14494 Rev 5
13/20
Typical application diagram
L6392
7
Typical application diagram
Figure 6.
Application diagram
BOOTSTRAP DRIVER
VCC
4
UV
DETECTION
FLOATING STRUCTURE
from LVG
14
BOOT
UV
DETECTION
H.V.
HVG
DRIVER
HIN
3
LEVEL
SHIFTER
S
13
HVG
12
OUT
Cboot
R
LOGIC
5V
SHOOT
THROUGH
PREVENTION
LIN
1
TO LOAD
VCC
SD
GND
DT
2
LVG
DRIVER
LVG
10
SD
LATCH
7
5
DEAD
TIME
OPAMP
OPOUT
+
6
8
9
14/20
Doc ID 14494 Rev 5
OP+
OP-
-
L6392
8
Bootstrap driver
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 7 a). In the L6392 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in
Figure 7 b.
An internal charge pump (Figure 7 b) provides the DMOS driving voltage.
8.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Q gate
C EXT = ------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
CBOOT >>> CEXT
e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 200 μA, so if HVG TON is 5 ms, CBOOT has
to supply 1 μC to CEXT. This charge on a 1μF capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value:
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Q gate
V drop = I ch arg e R dson → V drop = ------------------ R dson
T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor.
Doc ID 14494 Rev 5
15/20
Bootstrap driver
L6392
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 μs. In fact:
30nC
V drop = --------------- ⋅ 120Ω ∼ 0.7V
5μs
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 7.
Bootstrap driver
DBOOT
VS
BOOT
BOOT
VS
H.V.
HVG
H.V.
HVG
CBOOT
VOUT
TO LOAD
TO LOAD
LVG
LVG
a
16/20
CBOOT
VOUT
b
Doc ID 14494 Rev 5
D99IN1067
L6392
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 8.
DIP-14 mechanical data and package dimensions
mm
DIM.
MIN.
a1
0.51
B
1.39
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
15.24
0.600
F
7.1
0.280
I
5.1
0.201
L
OUTLINE AND
MECHANICAL DATA
3.3
0.130
DIP14
Z
1.27
2.54
0.050
0.100
Doc ID 14494 Rev 5
17/20
Package mechanical data
Figure 9.
L6392
SO-14 mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.35
1.75
0.053
0.069
A1
0.10
0.30
0.004
0.012
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.01
8.55
8.75
0.337
0.344
3.80
4.0
0.150
0.157
D
(1)
E
e
1.27
0.050
H
5.8
6.20
0.228
0.244
h
0.25
0.50
0.01
0.02
L
0.40
1.27
0.016
0.050
k
ddd
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO14
0016019 D
18/20
Doc ID 14494 Rev 5
L6392
10
Revision history
Revision history
Table 10.
Document revision history
Date
Revision
Changes
29-Feb-2008
1
Initial release
18-Mar-2008
2
Cover page updated
17-Sep-2008
3
Updated Table 4 on page 6, Table 4 on page 6, Table 9 on page 12
17-Feb-2009
4
Updated Table 7 on page 8, Table 8 on page 10, Table 9 on page 12
Added Table 4 on page 9
11-Aug-2010
5
Updated cover page, Table 1 on page 1, Table 7 on page 8, Table 9
on page 12
Doc ID 14494 Rev 5
19/20
L6392
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