AOZ8001KI скачать даташит

AOZ8001KI скачать даташит
AOZ8001K
Ultra-Low Capacitance TVS Diode Array
General Description
Features
The AOZ8001K is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
●
– IEC 61000-4-2, level 4 (ESD) immunity test
– ±15kV (air discharge) and ±8kV (contact discharge)
This device incorporates four surge rated, low capacitance
steering diodes and a TVS in a single package. During
transient conditions, the steering diodes direct the
transient to either the positive side of the power supply
line or to ground. They may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4.
The TVS diodes provide effective suppression of ESD
voltages: ±15kV (air discharge) and ±8kV (contact
discharge).
m
m
co
e
r
ot
ESD protection for high-speed data lines:
– IEC 61000-4-5 (Lightning) 5A (8/20µs)
.
s
n
ig
s
Low insertion losse
dlines
w
Protects
four
I/O
e
Lown
capacitance from IO to Ground: 1.0pF
r
foLow clamping voltage
d
e
d
Low operating voltage: 5.0V
n
e
The AOZ8001K comes in a RoHS compliant SC-89
package and is rated over a -40°C to +85°C ambient
temperature range. It is compatible with both lead free
and SnPb assembly techniques.
N
The very small 1.7 x 1.7 x 0.6mm SC-89 package makes
it ideal for applications where PCB space is a premium.
The SC-89 has a flow through package design for an
optimal and user friendly PCB layout design. The small
size, low capacitance and high ESD protection makes
it ideal for protecting high speed video and data
communication interfaces.
– Human Body Model (HBM) ±15kV
●
Small package saves board space
●
●
●
●
●
●
Pb-free device
●
Green product
Applications
●
USB 2.0 power and data line protection
●
Video graphics cards
●
Monitors and flat panel displays
●
Digital Video Interface (DVI)
●
10/100/1000 Ethernet
●
Notebook computers
Typical Application
USB Controller
USB Controller
+5V
+5V
AOZ8001K
D+
+5V
D-
D+
D-
GND
GND
Figure 1. USB 2.0 High Speed Port
Rev. 1.1 January 2011
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Page 1 of 10
AOZ8001K
Ordering Information
Part Number
Ambient Temperature Range
Package
-40°C to +85°C
SC-89
Environmental
AOZ8001KI
AOZ8001KIL
RoHS Compliant
RoHS Compliant
Green Product
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
CH1
1
6
NC
VN
2
5
VP
NC
3
4
CH2
SC-89
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
VP – VN
6V
Peak Pulse Current (IPP), tP = 8/20µs
5A
Storage Temperature (TS)
-65°C to +150°C
ESD Rating per IEC61000-4-2,
Contact(1)
ESD Rating per IEC61000-4-2, Air
ESD Rating per Human Body
±8kV
(1)
±15kV
Model(2)
±15kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
Rev. 1.1 January 2011
-40°C to +125°C
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Page 2 of 10
AOZ8001K
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Symbol
VRWM
Parameter
Reverse Working Voltage
Conditions
Min.
Between pin 5 and 2(3)
(4)
VBR
Reverse Breakdown Voltage
IT = 1mA, between pins 5 and 2
IR
Reverse Leakage Current
VRWM = 5V, between pins 5 and 2
VF
Diode Forward Voltage
IF = 15mA
VCL
Cj
Units
5.5
V
6.6
0.70
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 1A, tp = 100ns, any I/O pin to Ground
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5A, tp = 100ns, any I/O pin to Ground(5)(7)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 12A, tp = 100ns, any I/O pin to Ground(5)(7)
Junction Capacitance
VR = 0V, f = 1MHz, between I/O pins(6)
Channel Input Capacitance
Matching
Max.
V
1.0
µA
1
V
10.00
-2.00
V
V
11.00
-5.00
V
V
14.50
-10.50
V
V
0.1
0.12
pF
1.0
1.17
pF
0.03
pF
0.85
(5)(7)
VR = 0V, f = 1MHz, any I/O pin to
ΔCj
Typ.
VR = 0V, f = 1MHz, between I/O
Ground(6)
pins(5)
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed with no external capacitor on VP (pin 5 floating).
6. Measurements performed with VP biased to 3.3 Volts (pin 5 @ 3.3V).
7. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Rev. 1.1 January 2011
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Page 3 of 10
AOZ8001K
Typical Performance Characteristics
Typical Variation of CIN vs VR
Clamping Voltage vs. Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
(f = 1MHz, T = 25∞C)
15
Clamping Voltage, VCL (V)
1.5
1.25
1.0
0.75
Vp = 3.3V
0.50
0.25
14
13
12
11
10
9
0
0
1
2
3
4
5
0
Input Voltage (V)
Forward Voltage vs. Forward Current
2
4
6
8
Peak Pulse Current, IPP (A)
(Vp = 3.3V)
12
Insertion Loss (dB)
Forward Voltage (V)
10
8
6
4
2
0
2
4
6
8
12
I/O – Gnd Insertion Loss (S21) vs. Frequency
(tperiod = 100ns, tr = 1ns)
0
10
10
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
12
1
10
100
1000
Forward Current (A)
Frequency (MHz)
Analog Crosstalk (I/O–I/O) vs. Frequency
ESD Response (8kV Contact per IEC61000-4-2)
Insertion Loss (dB)
20
0
-20
-40
-60
-80
10
100
1000
Frequency (MHz)
Rev. 1.1 January 2011
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Page 4 of 10
AOZ8001K
Application Information
The AOZ8001K TVS is design to protect two data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8001K devices should be located as close as possible to the noise source. The placement of the AOZ8001K
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing
the AOZ8001K devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8001K device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most
interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the
reference or chassis ground. Shunting the surge voltage
directly to the IC’s signal ground can cause ground
bounce. The clamping performance of TVS diodes on a
single ground PCB can be improved by minimizing the
impedance with relatively short and wide ground traces.
The PCB layout and IC package parasitic inductances
can cause significant overshoot to the TVS’s clamping
voltage. The inductance of the PCB can be reduced by
using short trace lengths and multiple layers with
separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8001K
ultra-low capacitance TVS is designed to protect four
high speed data transmission lines from transient
over-voltages by clamping them to a fixed reference.
The low inductance and construction minimizes voltage
overshoot during high current surges. When the voltage
on the protected line exceeds the reference voltage the
internal steering diodes are forward biased, conducting
the transient current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
Connector
Protected IC
D+
D+
D-
DFlow Through Layout
Rev. 1.1 January 2011
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Page 5 of 10
AOZ8001K
AOZ8001K
VCC
Reset
AOZ8001K
Clock
SIM
I/O
GND
SIM Card Port Connection
TPBIASx
AOZ8001K
TPAx+
TPAx-
IEEE 1394
PHY
IEEE 1394
Connector
AOZ8001K
TPBx+
TPBx-
GND
IEEE1394 Port Connection
Rev. 1.1 January 2011
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Page 6 of 10
AOZ8001K
AOZ8001K
TRD0+
TRD0-
AOZ8001K
TRD1+
TRD1-
Ethernet
Controller
AOZ8001K
RJ45
Connector
TRD2+
TRD2-
AOZ8001K
TRD3+
TRD3-
10/100 Ethernet Port Connection
Rev. 1.1 January 2011
www.aosmd.com
Page 7 of 10
AOZ8001K
Package Dimensions, SC-89
e
b
D
L3
E
L4
L1
L2
Pin 1
θ (4x)
b1
e1
A3
A
RECOMMENDED LAND PATTERN
0.52
0.50
1.24
0.30
88
0.18
UNIT: mm
Dimensions in millimeters
Symbols
A
A3
b
Min.
0.53
0.13
0.17
D
E1
e
E
L1
1.50
1.50
L2
L3
L4
b1
e1
0.10
0.05
θ
8°
Nom.
0.57
0.17
—
Dimensions in inches
Max.
0.60
0.18
0.25
Symbols
A
A3
b
Min.
0.021
0.005
0.007
1.70
1.70
0.060
0.060
1.30
0.26
D
E1
e
E
L1
0.23
0.30
0.10
—
0.83 REF
—
0.27
0.34
0.20
—
—
L2
L3
L4
b1
e1
0.004
0.002
θ
8°
1.66
1.65
0.50 BSC
1.10
1.20
0.11
0.19
10°
12°
Nom.
0.022
0.007
—
Max.
0.024
0.007
0.010
0.065 0.067
0.065 0.067
0.020 BSC
0.043 0.047 0.051
0.004 0.007 0.010
0.009 0.012
0.004
—
0.033 REF
—
0.011 0.013
0.008
—
—
10°
12°
Notes:
1. All dimensions are in millimeters.
2. Dimension are inclusive of plating.
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 3 mils each.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.1 January 2011
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Page 8 of 10
AOZ8001K
Tape and Reel Dimensions, SC-89
Carrier Tape
P1
D1
P2
T
E1
E2
E
B0
K0
D0
A0
Feeding Direction
P0
UNIT: mm
Package
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
SC-89, 6L
(8mm)
1.78
±0.05
1.78
±0.05
0.89
±0.05
0.50
±0.05
1.50
±0.10
8.00
+0.30/-0.10
1.75
±0.10
3.50
±0.05
4.00
±0.10
4.00
±0.10
2.00
±0.05
0.25
±0.05
Reel
W1
S
G
N
M
K
V
R
H
W
W
N
Tape Size Reel Size
M
8mm
ø180
ø180.00 ø60.50 9.00
±0.30
±0.50
W1
11.40
±1.00
H
K
ø13.00
10.60
+0.50/-0.20
S
2.00
±0.50
G
ø9.00
R
5.00
V
18.00
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.1 January 2011
Components Tape
Orientation in Pocket
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Leader Tape
500mm min. or
125 empty pockets
Page 9 of 10
AOZ8001K
Part Marking
AOZ8001KI
(SC-89)
LWB
Assembly Lot and
Location Code
Part Number Code
Week & Year Code
AOZ8001KIL
(SC-89)
LWB
Assembly Lot and
Location Code
Part Number Code,
Underscore Denotes Green Code
Week & Year Code
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.1 January 2011
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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