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Actual Size
9mm Square
DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
±3-A HIGH-EFFICIENCY PWM POWER DRIVER
Check for Samples: DRV593 , DRV594
1
FEATURES
2
• Operation Reduces Output Filter Size and Cost by 50% Compared to DRV591
• ±3-A Maximum Output Current
• Low Supply Voltage Operation: 2.8 V to 5.5 V
• High Efficiency Generates Less Heat
• Overcurrent and Thermal Protection
• Fault Indicators for Overcurrent, Thermal and
Undervoltage Conditions
• Two Selectable Switching Frequencies
• Internal or External Clock Sync
• PWM Scheme Optimized for EMI
• 9×9 mm PowerPAD™ Quad Flatpack Package
APPLICATIONS
• Thermoelectric Cooler (TEC) Driver
• Laser Diode Biasing
10
µ
F
V
DD
DESCRIPTION
The DRV593 and DRV594 are high-efficiency, high-current power amplifiers ideal for driving a wide variety of thermoelectric cooler elements in systems powered from 2.8 V to 5.5 V. The operation of the device requires only one inductor and capacitor for the output filter, saving significant printed-circuit board area. Pulse-width modulation (PWM) operation and low output stage on-resistance significantly decrease power dissipation in the amplifier.
The DRV593 and DRV594 are internally protected against thermal and current overloads. Logic-level fault indicators signal when the junction temperature has reached approximately 128°C to allow for system-level shutdown before the amplifier's internal thermal shutdown circuitry activates.
The fault indicators also signal when an overcurrent event has occurred. If the overcurrent circuitry is tripped, the devices automatically reset (see application information section for more details).
The PWM switching frequency may be set to 500 kHz or 100 kHz depending on system requirements. To eliminate external components, the gain is fixed at
2.3 V/V for the DRV593. For the DRV594, the gain is fixed at 14.5 V/V.
1
µ
F
1
µ
F
120 k
Ω
DC Control
Voltage
1 k
Ω
1 k
Ω
1
µ
220 pF
F
Shutdown Control
AVDD
AGND (Connect to PowerPAD)
ROSC
COSC
AREF
IN+
SHUTDOWN
DRV593
DRV594
PWM
PGND
PGND
PGND
PGND
PGND
PGND
H/C
10
µ
H
To TEC or Laser
Diode Anode
10
µ
F
FAULT1
FAULT0
To TEC or Laser
Diode Cathode
1
µ
F
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
T
A
Table 1. ORDERING INFORMATION
(1)
–40°C to 85°C
PowerPAD QUAD FLATPACK
(VFP)
DRV593VFP
(2)
DRV594VFP
(2)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com
(2) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., DRV593VFPR or DRV594VFPR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
AVDD, PVDD
V
I
I
O
(FAULT0, FAULT1)
T
A
T
J
T stg
Supply voltage
Input voltage
Output current
Continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
DRV593, DRV594
–0.3 V to 5.5 V
–0.3 V to V
DD
+ 0.3 V
1 mA
See Dissipation Rating Table
–40°C to 85°C
–40°C to 150°C
–65°C to 165°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
AVDD, PVDD Supply voltage
V
IH
V
IL
T
A
High-level input voltage
Low-level input voltage
Operating free-air temperature
FREQ, INT/EXT, SHUTDOWN, COSC
FREQ, INT/EXT, SHUTDOWN, COSC
MIN MAX UNIT
2.8
5.5
V
2
–40
V
0.8
V
85 °C
PACKAGE
PACKAGE DISSIPATION RATINGS
q
JA
(1)
(°C/W)
29.4
q
JC
(°C/W)
1.2
T
A
=25°C
POWER RATING
4.1 W VFP
(1) This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard
4-layer 3 in × 3 in PCB.
2
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
|V
OO
|
|I
IH
|
|I
IL
|
V n
V
ICM
A v
V
O r
DS(on)
I q
I q(SD)
Z
I
PARAMETER TEST CONDITIONS
Output offset voltage (measured differentially) V
I
= V
DD
/2,
High-level input current V
DD
= 5.5V,
Low-level input current
Integrated output noise voltage
V
DD
= 5.5V, f = <1 Hz to 10 kHz
I
O
= 0 A
V
I
= V
DD
V
I
= 0 V
Common-mode voltage range
Closed-loop voltage gain
V
DD
= 5 V
V
DD
= 3.3 V
DRV593
DRV594
Full power bandwidth
Voltage output (measured differentially)
Drain-source on-state resistance
I
O
= ±1 A, r
DS(on)
= 65 m
Ω
, V
DD
= 5 V
I
O
= ±3 A, r
DS(on)
= 65 m Ω , V
DD
= 5 V
V
T
DD
A
= 5 V, I
= 25°C
O
= 4 A,
High side
Low side
V
T
DD
A
= 3.3 V, I
= 25°C
O
= 4 A,
High side
Low side
Maximum continuous current output
Status flag output pins (FAULT0, FAULT1)
Fault active (open drain output)
Sinking 200 m A
External clock frequency range
Quiescent current
For 500 kHz operation
For 100 kHz operation
V
DD
= 5 V, No load or filter
V
DD
= 3.3 V, No load or filter
V
DD
= 5 V, SHUTDOWN = 0.8 V
SHUTDOWN = 0.8 V
Quiescent current in shutdown mode
Output resistance in shutdown
Power-on threshold
Power-off threshold
Thermal trip point
Thermal shutdown
Input impedance (IN+, IN-)
FAULT0 active
Power off
MIN TYP MAX UNIT
14 100 mV
1
1 m m
A
A
40 m V
1.2
1.2
3.8
2.1
V
2.1
2.3
2.6
V/V
13.7
14.5
15.3
V/V kHz 60
4.87
4.61
V
25
25
25
25
60
65
80
3
95
95
140
90 140 m m
A
Ω
Ω
V 0.1
225 250 300
45 50 55
0
1
4
2.5
40
2
12
8
80
1.7
1.6
2.8
2.6
128
158
100 kHz mA m A k Ω
V
V
°C
°C k Ω
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s):
DRV593 DRV594
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
PIN ASSIGNMENTS
VFP PACKAGE
(TOP VIEW)
AVDD
AGND
ROSC
COSC
AREF
IN+
IN−
SHUTDOWN
5
6
7
8
3
4
1
2
32 31 30 29 28 27 26 25
PowerPAD
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
PWM
PGND
PGND
PGND
PGND
PGND
PGND
H/C
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NAME
AGND
AREF
AVDD
COSC
TERMINAL
NO.
2
5
1
4
FAULT0
FAULT1
FREQ
IN–
IN+
INT/EXT
10
9
32
7
6
31
H/C
PWM
PGND
PVDD
ROSC
SHUTDOWN
14, 15,
16, 17
24, 25,
26, 27
18, 19,
20, 21,
22, 23
11, 12,
13, 28,
29, 30
3
8
I
I
I
O
I
I
O
O
I
I/O
O
TERMINAL FUNCTIONS
DESCRIPTION
Analog ground
Connect 1 m F capacitor to ground for AREF voltage filtering
Analog power supply
Connect capacitor to ground to set oscillation frequency (220 pF for 500 kHz, 1 nF for 100 kHz) when the internal oscillator is selected; connect clock signal when an external oscillator is used
Fault flag 0, low when active open drain output (see application information)
Fault flag 1, high when active open drain output (see application information)
Selects 500 kHz switching frequency when a TTL logic low is applied to this terminal; selects 100 kHz switching frequency when a TTL logic high is applied
Negative differential input
Positive differential input
Selects the internal oscillator when a TTL logic high is applied to this terminal; selects the use of an external oscillator when a TTL logic low is applied to this terminal
Direction control output for heat and cool modes (4 pins)
O PWM output for voltage magnitude (4 pins)
High-current ground (6 pins)
I High-current power supply (6 pins)
I
I Connect 120-k Ω resistor to AGND to set oscillation frequency (either 500 kHz or 100 kHz). Not needed if an external clock is used.
Places the amplifier in shutdown mode when a TTL logic low is applied to this terminal; places the amplifier in normal operation when a TTL logic high is applied
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AVDD AGND
FUNCTIONAL BLOCK DIAGRAM
DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
IN−
IN+
R
R
AVDD
2.3 x R (DRV593)
14.5 x R (DRV594)
_
+
+
_
2.3 x R (DRV593)
14.5 x R (DRV594)
_
+
+
_
+
_
+
_
Gate
Drive
Gate
Drive
r
DS(on)
I q
PSRR
I
O
V
IO
SHUTDOWN
INT/EXT
FREQ
COSC
ROSC
AREF
TTL
Input
Buffer
Biases and
References
Ramp
Generator
Efficiency
Drain-source on-state resistance
TYPICAL CHARACTERISTICS
Table of Graphs
vs Load resistance vs Supply voltage vs Free-air temperature vs Free-air temperature vs Supply voltage vs Frequency
Supply current
Power supply rejection ratio
Closed loop response
Maximum output current
Input offset voltage vs Output voltage vs Ambient temperature
Common-mode input voltage
Start-Up
Protection
Logic
Thermal VDDok
OC
Detect
FAULT0
FAULT1
FIGURE
2, 3
4
5
6
7
8, 9
12, 13
14
15
16, 17
PVDD
H/C
PGND
PVDD
PWM
PGND
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s):
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
TEST SETUP FOR GRAPHS
The LC output filter used in
, and
is shown below.
L1
PWM
C1 R
L
H/C www.ti.com
70
60
50
100
90
80
40
30
20
10
0
1 2
L1 = 10
µ
H (part number: CDRH104R, manufacturer: Sumida)
C1 = 10
µ
F (part number: ECJ-4YB1C106K, manufacturer: Panasonic)
Figure 1. LC Output Filter
EFFICIENCY vs
LOAD RESISTANCE
EFFICIENCY vs
LOAD RESISTANCE
P
O
= 0.5 W
P
O
= 1 W
P
O
= 2 W
V
DD
= 5 V f
S
= 500 kHz
9 3 4 5 6 7
R
L
− Load Resistance −
Ω
8
Figure 2.
10
70
60
50
100
90
80
40
30
20
10
0
1 2
P
O
= 0.25 W
P
O
= 0.5 W
P
O
= 1 W
V
DD
= 3.3 V f
S
= 500 kHz
9 3 4 5 6 7
R
L
− Load Resistance −
Ω
8
Figure 3.
10
6
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DRAIN-SOURCE ON-STATE RESISTANCE vs
SUPPLY VOLTAGE
300
I
O
T
A
= 1 A
= 25
°
C
250
Total
200
150
100
50
Low Side
High Side
0
2.7
3.1
3.5
3.9
4.3
4.7
V
DD
− Supply Voltage − V
Figure 4.
5.1
DRAIN-SOURCE ON-STATE RESISTANCE vs
FREE-AIR TEMPERATURE
300
250
V
DD
= 3.3 V
I
O
= 1 A
VFP Package
Total
200
5.5
150
100
50
0
−40
Low Side
High Side
−15 10 35 60
T
A
− Free-Air Temperature −
°
C
Figure 6.
85
DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
DRAIN-SOURCE ON-STATE RESISTANCE vs
FREE-AIR TEMPERATURE
300
250
V
DD
= 5 V
I
O
= 1 A
VFP Package
200
150
Total
100
Low Side
High Side
50
0
−40 −15 10 35
T
A
− Free-Air Temperature −
°
C
60
Figure 5.
SUPPLY CURRENT vs
SUPPLY VOLTAGE
10
9
8
7
6
5
4
3
2
1
0
2.7
No Load
3.1
3.5
3.9
4.3
4.7
V
DD
− Supply Voltage − V
Figure 7.
85
5.1
5.5
Copyright © 2002–2010, Texas Instruments Incorporated
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
POWER SUPPLY REJECTION RATIO vs
FREQUENCY
−20
−30
V
DD
= 5 V f
S
R
L
= 500 kHz
= 1
Ω
V ripple
= 100 mV pp
−40
−50
−60
−70
4
3
2
1
−80
10
0
10
V
DD
= 5 V
No Load
100 1k f − Frequency − Hz
Figure 8.
10k
DRV593
CLOSED LOOP RESPONSE
Phase
Gain
100k
−60
−70
−80
100k
−30
−40
−50
10
0
−10
−20
100 1k f − Frequency − Hz
Figure 10.
10k
POWER SUPPLY REJECTION RATIO vs
FREQUENCY
−20
−30
V
DD
= 3.3 V f
S
R
L
= 500 kHz
= 1
Ω
V ripple
= 100 mV pp
−40 www.ti.com
−50
−60
−70
16
14
12
10
8
−80
10
6
4
2
0
10
V
DD
= 5 V
No Load
100 1k f − Frequency − Hz
10k
Figure 9.
DRV594
CLOSED LOOP RESPONSE
Gain
Phase
100k
10
−40
−50
−60
−70
100 k
0
−10
−20
−30
100 1 k f − Frequency − Hz
10 k
Figure 11.
8
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4
3
2
1
0
10
V
DD
= 3.3 V
No Load
Phase
Gain
100 1k f − Frequency − Hz
10k
Figure 12.
MAXIMUM OUTPUT CURRENT vs
OUTPUT VOLTAGE
−60
−70
100k
−80
−30
−40
−50
10
0
−10
−20
3.5
DRV593
CLOSED LOOP RESPONSE
3
2.5
2
1.5
T
J
= 125
°
T
C
J
= 85
°
T
C
J
= 100
°
C
1
I O
0.5
0
0
V
DD
T
A
VFP Package
1 2 3
V
O
− Output Voltage − V
Figure 14.
= 5 V
= 25
°
C
4 5
16
14
12
10
DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
DRV594
CLOSED LOOP RESPONSE
10
Gain
0
Phase
−10
−20
8
6
4
2
0
10
V
DD
= 3.3 V
No Load
100 1 k f − Frequency − Hz
Figure 13.
10 k
MAXIMUM OUTPUT CURRENT vs
AMBIENT TEMPERATURE
−30
−40
−50
−60
−70
100 k
3.5
3
2.5
2
1.5
1
I O
0.5
T
J
≤
125
°
C
VFP Package
0
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80
T
A
− Ambient Temperature −
°
C
Figure 15.
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
INPUT OFFSET VOLTAGE vs
COMMON-MODE INPUT VOLTAGE
10
V
DD
= 5 V
No Load
7
6
5
4
3
9
8
2
1
0
1.2
1.6
2.0
2.4
2.8
3.2
V
IC
− Common-Mode Input Voltage − V
Figure 16.
3.6 3.8
www.ti.com
INPUT OFFSET VOLTAGE vs
COMMON-MODE INPUT VOLTAGE
20
19
18
V
DD
= 3.3 V
No Load
14
13
12
11
17
16
15
10
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
V
IC
− Common-Mode Input Voltage − V
Figure 17.
10
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
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APPLICATION INFORMATION
PULSE-WIDTH MODULATION SCHEME FOR DRV593 AND DRV594
The pulse-width modulation scheme implemented in the DRV593 and DRV594 eliminates one-half of the full output filter previously required for PWM drivers. The DRV593 and DRV594 require only one inductor and capacitor for the output filter. The H/C outputs determine the direction of the current and do not switch back and forth. The PWM outputs switch to produce a voltage across the load that is proportional to the input control voltage.
COOLING MODE
shows the DRV593 and DRV594 in cooling mode. The H/C outputs (pins 14-17) are at ground and the
PWM outputs (pins 24-27) create a voltage across the load that is proportional to the input voltage.
The differential voltage across the load is determined using
and the duty cycle using
. The differential voltage is defined as the voltage measured after the filter on the PWM output relative to the H/C output.
V
Load
+
D V
DD
(1)
D
+
A v ǒ
V
IN
)
–V
IN–
Ǔ
V
DD
(2) where D duty cycle of the PWM signal A v
Positive input terminal of the DRV593/594 V
Gain of DRV593/594 (DRV593: 2.3 V/V, DRV594: 14.5 V/V) V
IN+
IN–
Negative input terminal of the DRV593/594 V
DD
Power supply voltage
For example, a 50% duty cycle, shown in
Figure 18 , results in 2.5 V across the load for V
DD
= 5 V.
VDD
PWM
0
VDD
H/C
0
VDD
VDD/2
Load
Voltage
0
Figure 18. Cooling Mode
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
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HEATING MODE
shows the DRV593 and DRV594 in heating mode. The H/C output is at VDD and the PWM output is proportional to the voltage across the load.
The differential voltage across the load is determined using
Equation 3 . The variables are the same as used
previously for
and
V
Load
+
–(1–D) V
DD
(3)
For example, a 50% duty cycle, shown in
Figure 19 , results in –2.5 V across the load for VDD = 5 V. The
differential voltage across the load is defined as the voltage measured after the filter on the PWM output relative to the H/C output.
VDD
PWM
0
VDD
H/C
0
Load
Voltage
0
−VDD/2
−VDD
Figure 19. Heating Mode
HEAT/COOL TRANSITION
As the device transitions from cooling to heating, the duty cycle of the PWM outputs decrease to a small value and the H/C outputs remains at ground. When the device transitions to heating mode, the H/C outputs change from zero volts to VDD and the PWM outputs change to a high duty cycle. The direction of the current flow is reversed, but a low voltage is maintained across the load. The duty cycle decreases as the part is put further into heating mode to drive more current through the load.
illustrates the transition from cooling to heating.
ZERO-CROSSING REGION
When the differential output voltage is near zero, the control logic in the DRV593 and DRV594 causes the outputs to change between heating and cooling modes. There are two possible states for the PWM and H/C outputs to obtain zero volts differentially: both outputs can be at VDD or both outputs can be at ground.
Therefore, random noise causes the outputs to change between the two states when the two input voltages are equal. The outputs switch from zero to VDD, although not at a fixed frequency rate. Some of the pulses may be wider than others, but the two outputs (PWM and H/C) track each other to provide zero differential voltage.
These uneven pulse widths can increase the switching noise during the zero-crossing condition.
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DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
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To avoid this phenomenon, hysteresis should be implemented in the control loop to prevent the device from operating within this region. Although planning for operation during the zero-crossing is important, the normal operating points for the DRV593 and DRV594 are outside of this region. For laser temperature/wavelength regulation, the zero volts output condition is only a concern when the laser temperature or wavelength, relative to the ambient temperature, requires no heating or cooling from the TEC element.
VDD
IN +
IN −
0
VDD
PWM
0
VDD
H/C
0
Figure 20. Transition From Cooling to Heating
10
µ
F
V
DD
1
µ
F
1
µ
F
120 k
Ω
DC Control
Voltage
1 k
Ω
1 k
Ω
1
µ
220 pF
F
Shutdown Control
AVDD
AGND (Connect to PowerPAD)
ROSC
COSC
AREF
IN+
SHUTDOWN
DRV593
DRV594
PWM
PGND
PGND
PGND
PGND
PGND
PGND
H/C
10
µ
H
To TEC or Laser
Diode Anode
10
µ
F
FAULT1
FAULT0
1
µ
F
Figure 21. Typical Application Circuit
To TEC or Laser
Diode Cathode
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DRV593
DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
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OUTPUT FILTER CONSIDERATIONS
TEC element manufacturers provide electrical specifications for maximum dc current and maximum output voltage for each particular element. The maximum ripple current, however, is typically only recommended to be less than 10% with no reference to the frequency components of the current. The maximum temperature differential across the element, which decreases as ripple current increases, may be calculated with the following equation:
D T
+
1 ǒ
1
)
N
2
Ǔ
D
Tmax
(4) where
Δ T = actual temperature differential
Δ T max
= maximum temperature differential (specified by manufacturer)
N = ratio of ripple current to dc current
According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. An LC network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more importantly, protect the rest of the system from any electromagnetic interference (EMI).
FILTER COMPONENT SELECTION
The LC filter, which may be designed from two different perspectives, both described below, helps estimate the overall performance of the system. The filter should be designed for the worst-case conditions during operation, which is typically when the differential output is at 50% duty cycle. The following section serves as a starting point for the design, and any calculations should be confirmed with a prototype circuit in the lab.
Any filter should always be placed as close as possible to the DRV593 and DRV594 to reduce EMI.
L
PWM
C
TEC R
H/C
Figure 22. Output Filter
LC FILTER IN THE FREQUENCY DOMAIN
The transfer function for a second-order low-pass filter (
Figure 22 ) is shown in Equation 5
:
H
LP
(j w )
+
1
– ǒ w w
0
Ǔ
2
)
1
Q j w w
0
)
1 w
0
+
1
Ǹ
LC
Q
+ quality factor w
+
DRV593 or DRV594 switching frequency
(5)
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For the DRV593 and DRV594, the differential output switching frequency is typically selected to be 500 kHz. The resonant frequency for the filter is typically chosen to be at least one order of magnitude lower than the switching frequency.
may then be simplified to give the following magnitude
. These equations assume the use of the filter in
Ť
H
LP
Ť dB
+
–40 log ǒ fs fo
Ǔ fo
+
1
2 p
Ǹ
LC fs
+
500 kHz (DRV593 or DRV594 switching frequency)
(6)
If L=10 m H and C=10 m F, the cutoff frequency is 15.9 kHz, which corresponds to –60 dB of attenuation at the 500 kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element is approximately 5 mV.
The average TEC element has a resistance of 1.5
Ω , so the ripple current through the TEC is approximately 3.4
mA. At the 3-A maximum output current of the DRV593 and DRV594, this 5.4 mA corresponds to 0.11% ripple current, causing less than 0.0001% reduction of the maximum temperature differential of the TEC element (see
).
LC FILTER IN THE TIME DOMAIN
The ripple current of an inductor may be calculated using
:
D I
L
+ ǒ
V
O
–V
TEC
Ǔ
DTs
L
D
+ duty cycle (0.5 worst case)
T s
+
1 ń f s
+
1 ń
500 kHz
(7)
For V
O
= 5 V, V
TEC
= 2.5 V, and L = 10 m H, the inductor ripple current is 250 mA. To calculate how much of that ripple current flows through the TEC element, however, the properties of the filter capacitor must be considered.
For relatively small capacitors (less than 22 m F) with very low equivalent series resistance (ESR, less than
10 m Ω , such as ceramic capacitors, the following
may be used to estimate the ripple voltage on the capacitor due to the change in charge:
D V
C
+ p
2
2 ǒ
1–D
Ǔ ǒ fo fs
Ǔ
2
V
TEC
D
+ duty cycle fs
+
500 kHz fo
+
1
2 p
Ǹ
LC
(8)
For L = 10 m H and C = 10 m F, the cutoff frequency, f o
V
TEC
, is 15.9 kHz. For worst case duty cycle of 0.5 and
=2.5 V, the ripple voltage on the capacitors is 6.2 mV. The ripple current may be calculated by dividing the ripple voltage by the TEC resistance of 1.5
Ω , resulting in a ripple current through the TEC element of 4.1 mA.
Note that this is similar to the value calculated using the frequency domain approach.
For larger capacitors (greater than 22 m F) with relatively high ESR (greater than 100 m Ω ), such as electrolytic capacitors, the ESR dominates over the charging/discharging of the capacitor. The following simple
may be used to estimate the ripple voltage:
D V
C
+ D
I
L
R
ESR
D I
L
+ inductor ripple current
R
ESR
+ filter capacitor ESR
(9)
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For a 100 m F electrolytic capacitor, an ESR of 0.1
Ω is common. If the 10 µH inductor is used, delivering 250 mA of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times that of the 10 m F ceramic capacitor, as ceramic capacitors typically have negligible ESR.
SWITCHING FREQUENCY CONFIGURATION: OSCILLATOR COMPONENTS R
OSC
FREQ OPERATION and C
OSC
AND
The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. The frequency may be either 500 kHz or 100 kHz by selecting the proper capacitor value and by holding the FREQ pin either low (500 kHz) or high (100 kHz).
shows the values required and FREQ pin configuration for each switching frequency.
Table 2. Frequency Configuration Options
SWITCHING FREQUENCY
500 kHz
100 kHz
R
OSC
120 k Ω
120 k Ω
C
OSC
220 pF
1 nF
FREQ
LOW (GND)
HIGH (VDD)
For proper operation, the resistor R
OSC should have 1% tolerance while capacitor C
OSC should be a ceramic type with 10% tolerance. Both components should be grounded to AGND, which should be connected to PGND at a single point, typically where power and ground are physically connected to the printed-circuit board.
EXTERNAL CLOCKING OPERATION
To synchronize the switching to an external clock signal, pull the INT/EXT terminal low, and drive the clock signal into the COSC terminal. This clock signal must be from 10% to 90% duty cycle and meet the voltage requirements specified in the electrical specifications table. Since the DRV593 and DRV594 include an internal frequency doubler, the external clock signal must be approximately 250 kHz. Deviations from the 250 kHz clock frequency are allowed and are specified in the electrical characteristic table. The resistor connected from ROSC to ground may be omitted from the circuit in this mode of operation—the source is disconnected internally.
INPUT CONFIGURATION: DIFFERENTIAL AND SINGLE-ENDED
If a differential input is used, it should be biased around the midrail of the DRV593 or DRV594 and must not exceed the common-mode input range of the input stage (see the operating characteristics at the beginning of the data sheet).
The most common configuration employs a single-ended input. The unused input should be tied to V
DD
/2, which may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values chosen should be at least 100 times lower than the input resistance of the DRV593 or DRV594. This prevents the bias voltage at the unused input from shifting when the signal input is applied. A small ceramic capacitor should also be placed from the input to ground to filter noise and keep the voltage stable. An op amp configured as a buffer may also be used to set the voltage at the unused input.
FIXED INTERNAL GAIN
The differential output voltage may be calculated using
V
O
+
V
OUT
)
–V
OUT–
+
A v ǒ
V
IN
)
–V
IN–
Ǔ
(10)
A
V is the voltage gain, which is fixed internally at 2.3 V/V for DRV593 and 14.5 V/V for DRV594. The maximum and minimum ratings are provided in the electrical specification table at the beginning of the data sheet.
POWER SUPPLY DECOUPLING
To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor, typically 0.1
m
F to 1 m
F, should be placed as close to each set of PVDD pins of the DRV593 and DRV594 as possible. For bulk decoupling, a 10 m
F to 100 m
F tantalum or aluminum electrolytic capacitor should be placed relatively close to the DRV593 and DRV594.
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AREF CAPACITOR
The AREF terminal is the output of an internal mid-rail voltage regulator used for the onboard oscillator and ramp generator. The regulator may not be used to provide power to any additional circuitry. A 1 m F ceramic capacitor must be connected from AREF to AGND for stability (see oscillator components above for AGND connection information).
SHUTDOWN OPERATION
The DRV593 and DRV594 include a shutdown mode that disables the outputs and places the device in a low supply current state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is held high, the device operates normally. When SHUTDOWN is held low, the device is placed in shutdown. The
SHUTDOWN pin must not be left floating. If the shutdown feature is unused, the pin may be connected to VDD.
FAULT REPORTING
The DRV593 and DRV594 include circuitry to sense three faults:
• Overcurrent
• Undervoltage
• Overtemperature
These three fault conditions are decoded via the FAULT1 and FAULT0 terminals. Internally, these are open-drain outputs, so an external pullup resistor of 5 k
Ω or greater is required.
FAULT1
0
1
0
1
Table 3. Fault Indicators
FAULT0
0
0
1
1
Overcurrent
Undervoltage
Overtemperature
Normal operation
The overcurrent fault is reported when the output current exceeds four amps. As soon as the condition is sensed, the overcurrent fault is set and the outputs go into a high-impedance state for approximately 3 m s to 5 m s
(500 kHz operation). After 3 m s to 5 m s, the outputs are re-enabled. If the overcurrent condition has ended, the fault is cleared and the device resumes normal operation. If the overcurrent condition still exists, the above sequence repeats.
The undervoltage fault is reported when the operating voltage is reduced below 2.8 V. This fault is not latched, so as soon as the power supply recovers, the fault is cleared and normal operation resumes. During the undervoltage condition, the outputs go into a high-impedance state to prevent overdissipation due to increased r
DS(on)
.
The overtemperature fault is reported when the junction temperature exceeds 128°C. The device continues operating normally until the junction temperature reaches 158°C, at which point the IC is disabled to prevent permanent damage from occurring. The system's controller must reduce the power demanded from the DRV593 or DRV594 once the overtemperature flag is set, or else the device switches off when it reaches 158°C. This fault is not latched; once the junction temperature drops below 128°C, the fault is cleared, and normal operation resumes.
POWER DISSIPATION AND MAXIMUM AMBIENT TEMPERATURE
Though the DRV593 and DRV594 are much more efficient than traditional linear solutions, the power drop across the on-resistance of the output transistors does generate some heat in the package, which may be calculated as shown in
P
DISS
+ ǒ
I
OUT
Ǔ
2 r
DS(on), total
(11)
For example, at the maximum output current of 3 A through a total on-resistance of 130 m
Ω
(at T
J power dissipated in the package is 1.17 W.
= 25°C), the
Calculate the maximum ambient temperature using
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DRV594
SLOS401C – OCTOBER 2002 – REVISED JULY 2010
T
A
+
T
J
* ǒ θ
JA
P
DISS
Ǔ
www.ti.com
(12)
PRINTED-CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS
Since the DRV593 and DRV594 are high-current switching devices, a few guidelines for the layout of the printed-circuit board (PCB) must be considered:
1. Grounding. Analog ground (AGND) and power ground (PGND) must be kept separated, ideally back to where the power supply physically connects to the PCB, minimally back to the bulk decoupling capacitor (10
µF ceramic minimum). Furthermore, the PowerPAD ground connection should be made to AGND, not
PGND. Ground planes are not recommended for AGND or PGND, traces should be used to route the currents. Wide traces (100 mils) should be used for PGND while narrow traces (15 mils) should be used for
AGND.
2. Power supply decoupling. A small 0.1
m F to 1 m F ceramic capacitor should be placed as close to each set of PVDD pins as possible, connecting from PVDD to PGND. A 0.1
m
F to 1 m
F ceramic capacitor should also be placed close to the AVDD pin, connecting from AVDD to AGND. A bulk decoupling capacitor of at least
10 m
F, preferably ceramic, should be placed close to the DRV593 or DRV594, from PVDD to PGND. If power supply lines are long, additional decoupling may be required.
3. Power and output traces. The power and output traces should be sized to handle the desired maximum output current. The output traces should be kept as short as possible to reduce EMI, i.e., the output filter should be placed as close to the DRV593 or DRV594 outputs as possible.
4. PowerPAD. The DRV593 and DRV594 in the Quad Flatpack package use TI's PowerPAD technology to enhance the thermal performance. The PowerPAD is physically connected to the substrate of the DRV593 and DRV594 silicon, which is connected to AGND. The PowerPAD ground connection should therefore be kept separate from PGND as described above. The pad underneath the AGND pin may be connected underneath the device to the PowerPAD ground connection for ease of routing. For additional information on
PowerPAD PCB layout, refer to the PowerPAD Thermally Enhanced Package application note, ( SLMA002 ).
5. Thermal performance. For proper thermal performance, the PowerPAD must be soldered down to a thermal land, as described in the PowerPAD Thermally Enhanced Package application note, ( SLMA002 ). In addition, at high current levels (greater than 2 A) or high ambient temperatures (greater than 25°C), an internal plane may be used for heat sinking. The vias under the PowerPAD should make a solid connection, and the plane should not be tied to ground except through the PowerPAD connection, as described above.
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Changes from Revision A (October 2002) to Revision B Page
• Changed Thermal trip point from 115°C to 128°C ................................................................................................................
• Changed Thermal shtudown point from 128°C to 158°C .....................................................................................................
Changes from Revision B (November 2008) to Revision C Page
• Changed figure cross reference from "Figure 17 and Figure 18" to "Figure 22" in the "LC FILTER......." section. ............
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PACKAGE OPTION ADDENDUM
22-Jan-2010 www.ti.com
PACKAGING INFORMATION
Orderable Device
DRV593VFP
DRV593VFPG4
DRV593VFPR
DRV593VFPRG4
DRV594VFP
DRV594VFPG4
DRV594VFPR
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package
Type
HLQFP
HLQFP
HLQFP
HLQFP
HLQFP
HLQFP
HLQFP
Package
Drawing
VFP
VFP
VFP
VFP
VFP
VFP
VFP
Eco Plan
(2)
Pins Package
Qty
32 250 Green (RoHS & no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-2-260C-1 YEAR
32
32
32
32
32
32
TBD
1000 Green (RoHS & no Sb/Br)
TBD
250 Green (RoHS & no Sb/Br)
TBD
Call TI
CU NIPDAU
Call TI
CU NIPDAU
Call TI
CU NIPDAU
Call TI
Level-2-260C-1 YEAR
Call TI
Level-2-260C-1 YEAR
Call TI
Level-2-260C-1 YEAR
32
1000 Green (RoHS & no Sb/Br)
TBD Call TI Call TI DRV594VFPRG4 ACTIVE HLQFP VFP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
21-Jan-2010
*All dimensions are nominal
Device
DRV593VFPR
DRV594VFPR
Package
Type
Package
Drawing
HLQFP
HLQFP
VFP
VFP
Pins
32
32
SPQ
1000
1000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
16.4
330.0
16.4
A0
(mm)
9.6
9.6
B0
(mm)
9.6
9.6
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
1.9
1.9
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
21-Jan-2010
*All dimensions are nominal
Device
DRV593VFPR
DRV594VFPR
Package Type Package Drawing Pins
HLQFP
HLQFP
VFP
VFP
32
32
SPQ
1000
1000
Length (mm) Width (mm) Height (mm)
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
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