Digi NS9750 Microprocessor

Digi NS9750 Microprocessor
NS9750B-A1 Datasheet
The Digi NS9750B-A1 is a single chip 0.13μm CMOS network-attached processor. The CPU is the
ARM926EJ-S core with MMU, DSP extensions, Jazelle Java accelerator, and 8 kB of instruction cache
and 4 kB of data cache in a Harvard architecture. The NS9750B-A1 runs up to 200 MHz, with a 100
MHz system and memory bus and 50 MHz peripheral bus. The NS9750B-A1 operates at a 1.5V core
and 3.3V I/O ring voltages.
With its extensive set of I/O
CLK Generation
I C
JTAG Test
interfaces, Ethernet high-speed
Interrupt
and Debug
ARM
ARM
Controller
USB
ARM926EJ-S
performance and processing
Power Manager 200, 162, or 125MHz
8kB
capacity, the NS9750B-A1 is the
4K I-Cache
1284
AHB Arbiter
4kB D-Cache
most capable of highly integrated
Serial
Multiple
10/100
Module
32-bit network-attached
x4
Bus Master
Ethernet
Architecture
MII/RMII
SIM
processors available. The
100MHz
MAC
UART
100, 81, or 62.5 MHz AMBA AHB Bus
NS9750B-A1 is designed specifically
Memory
32b-D, 32b-A
Controller
for use in high-performance
SPI
Ext. Peripheral
Controller
intelligent networked devices and
LCD Controller
Internet appliances including highPCI/CardBus Bridge
16 General Purpose
performance/low-latency remote
33 MHz
Timers/Counters
I/O, intelligent networked
information displays, and
streaming and surveillance cameras. The NS9750B-A1 is a member of the award-winning NET+ARM
family of system-on-chip (SOC) solutions for embedded systems.
27-Channel DMA
50, 40.5, or 31 MHz Peripheral Bus
Bridge32b-D, 32b-A
GPIO (50 Pins)
2
The NS9750B-A1 offers a connection to an external bus expansion module as well as a glueless
connection to SDRAM, PC100 DIMM, Flash, EEPROM, and SRAM memories. It includes a versatile
embedded LCD controller that supports up to 16M color TFT or 3375 color STN. The NS9750B-A1
features a PCI/CardBus port as well as a USB port for applications that require WLAN, external
storage, or external sensors, imagers, or scanners. Four multi-function serial ports, an I2C port, and
1284 parallel port provide a standard glueless interface to a variety of external peripherals. The
NS9750B-A1 also features up to 50 general purpose I/O (GPIO) pins and highly-configurable power
management with sleep mode.
NET+ARM processors are the foundation for the NET+Works® family of integrated hardware and
software solutions for device networking. These comprehensive platforms include drivers,
operating systems, networking software, development tools, APIs, and complete development
boards.
Using the NS9750B-A1 and associated Net+Works packages allows system designers to achieve
dramatic time-to-market reductions with pre-integrated and tested NET+ARM hardware,
NET+Works software, and tools. Product unit costs are reduced dramatically with a complete
system-on-chip, including Ethernet, display support, a robust peripheral set, and the processing
headroom to meet the most demanding applications. Customers save engineering resources, as no
network development is required. Companies will reduce their design risk with a fully integrated
and tested solution.
A complete NET+Works development package includes ThreadX™ picokernel RTOS, Green Hills™
MULTI® 2000 IDE or Microcross GNU X-Tools™, drivers, networking protocols and services with APIs,
NET+ARM-based development board, Digi-supplied utilities, integrated file system, JTAG In Circuit
Emulator (ICE), and support for boundary scan description language (BSDL). One year software
maintenance and technical support is available.
Contents
NS9750B-A1 Features...................................................................... 1
System-level interfaces ................................................................... 4
System configuration ...................................................................... 5
General Purpose ID register..................................................... 7
System boot................................................................................. 8
Reset......................................................................................... 8
System Clock ............................................................................... 9
USB clock................................................................................... 11
NS9750B-A1 pinout and signal descriptions ........................................... 12
System Memory interface ...................................................... 12
System Memory interface signals ............................................. 16
Ethernet interface............................................................... 18
Clock generation/system pins ................................................. 19
bist_en_n, pll_test_n, and scan_en_n........................................ 20
PCI interface ..................................................................... 20
PCI/CardBus signals ............................................................. 22
GPIO MUX ......................................................................... 25
LCD module signals.............................................................. 31
I2C interface ..................................................................... 35
USB Interface..................................................................... 35
JTAG interface for ARM core/boundary scan ............................... 36
Reserved pins .................................................................... 37
Power ground .................................................................... 38
Address and register maps .............................................................. 38
System address map ............................................................ 38
BBus peripheral address map .................................................. 39
Electrical characteristics ................................................................ 40
Absolute maximum ratings..................................................... 40
Recommended operating conditions ......................................... 40
Maximum power dissipation ................................................... 41
Typical power dissipation ...................................................... 41
DC electrical characteristics ............................................................ 42
Inputs.............................................................................. 42
Outputs............................................................................ 43
Reset and edge sensitive input timing requirements ............................... 44
Power sequencing......................................................................... 45
Memory timing ............................................................................ 46
SDRAM timing .................................................................... 46
SRAM timing ...................................................................... 51
Slow peripheral acknowledge timing ......................................... 57
Ethernet timing ........................................................................... 59
PCI timing .................................................................................. 61
I2C timing .................................................................................. 65
iii
LCD timing ................................................................................. 66
SPI timing .................................................................................. 70
IEEE 1284 timing .......................................................................... 73
USB timing ................................................................................. 74
Reset and hardware strapping timing ................................................. 76
JTAG timing................................................................................ 77
Clock timing ............................................................................... 78
Packaging .................................................................................. 80
Product specifications .......................................................... 83
iv
NS9750B-A1 Datasheet
03/2006
NS9750B-A1 Features
NS9750B-A1 Features
32-bit ARM926EJ-S RISC processor
125 to 200 MHz
5-stage pipeline with interlocking
Harvard architecture
8 kB instruction cache and 4 kB data cache
32-bit ARM and 16-bit Thumb instruction
sets. Can be mixed for performance/code
density tradeoffs
MMU to support virtual memory-based OSs
such as Linux, WinCE/Pocket PC, VxWorks,
others
Two external DMA channels for external
peripheral support
System Boot
High-speed boot from 8-bit, 16-bit, or
32-bit ROM or Flash
Hardware-supported low cost boot from
serial EEPROM through SPI port (patent
pending)
High performance 10/100 Ethernet MAC
10/100 Mbps MII/RMII PHY interfaces
Full-duplex or half-duplex
DSP instruction extensions, improved
divide, single cycle MAC
Station, broadcast, or multicast address
filtering
ARM Jazelle, 1200CM (coffee marks) Java
accelerator
2 kB RX FIFO
EmbeddedICE-RT debug unit
256 byte TX FIFO with on-chip buffer
descriptor ring
JTAG boundary scan, BSDL support
–
External system bus interface
32-bit data, 32-bit internal address bus,
28-bit external address bus
Glueless interface to SDRAM, SRAM,
EEPROM, buffered DIMM, Flash
4 static and 4 dynamic memory chip
selects
1-32 wait states per chip select
A shared Static Extended Wait register
allows transfers to have up to 16368
wait states that can be externally
terminated.
Self-refresh during system sleep mode
Automatic dynamic bus sizing to 8 bits, 16
bits, 32 bits
Burst mode support with automatic data
width adjustment
Eliminates underruns and decreases
bus traffic
Separate TX and RX DMA channels
Intelligent receive-side buffer size
selection
Full statistics gathering support
External CAM filtering support
PCI/CardBus port
PCI v2.2, 32-bit bus, up to 33 MHz bus
speed
Programmable to:
–
PCI device mode
–
PCI host mode:
Supports up to 3 external PCI
devices
Embedded PCI arbiter or external
arbiter
CardBus host mode
www.digi.com
1
NS9750B-A1 Features
Flexible LCD controller
Supports most commercially available
displays:
–
Active Matrix color TFT displays — Up
to 24bpp direct 8:8:8 RGB; 16M colors
–
Single and dual panel color STN
displays — Up to 16bpp 4:4:4 RGB;
3375 colors
–
Single and dual-panel monochrome
STN displays — 1, 2, 4bpp palettized
gray scale
High-performance hardware and
software flow control
–
Odd, even, or no parity
–
5, 6, 7, or 8 bits
–
1 or 2 stop bits
–
Receive-side character and buffer gap
timers
Internal or external clock support, digital
PLL for RX clock extraction
4 receive-side data match detectors
Formats image data and generates timing
control signals
2 dedicated DMA channels per module, 8
channels total
Internal programmable palette LUT and
grayscaler support different color
techniques
32 byte TX FIFO and 32 byte RX FIFO per
module
Programmable panel-clock frequency
USB ports
USB v.2.0 full speed (12 Mbps) and low
speed (1.5 Mbps)
I2C port
I2C v.1.0, configurable to master or slave
mode
Bit rates: fast (400 kHz) or normal (100
kHz) with clock stretching
7-bit and 10-bit address modes
Configurable to device or OHCI host
–
USB host is bus master
–
USB device supports one bidirectional
control endpoint and 11
unidirectional endpoints
All endpoints supported by a dedicated
DMA channel; 13 channels total
Supports I2C bus arbitration
1284 parallel peripheral port
All standard modes: ECP, byte, nibble,
compatibility (also known as SPP or
“Centronix”)
RLE (run length encoding) decoding of
compressed data in ECP mode
20 byte RX FIFO and 20 byte TX FIFO
Serial ports
4 serial modules, each independently
configurable to UART mode, SPI master
mode, or SPI slave mode
Bit rates from 75 bps to 921.6 kbps:
asynchronous x16 mode
Bit rates from 1.2 kbps to 6.25 Mbps:
synchronous mode
UART provides:
2
–
Operating clock from 100 kHz to 2 MHz
Two dedicated DMA channels
High performance multiple-master/distributed
DMA system
Intelligent bus bandwidth allocation
(patent pending)
System bus and peripheral bus
System bus:
Every system bus peripheral is a bus
master with a dedicated DMA engine
NS9750B-A1 Datasheet
03/2006
NS9750B-A1 Features
Peripheral bus:
One 13-channel DMA engine supports USB
device
–
2 DMA channels support control
endpoint
–
11 DMA channels support 11 endpoints
One 12-channel DMA engine supports:
–
4 serial modules (8 DMA channels)
–
1284 parallel port (4 DMA channels)
All DMA channels support fly-by mode
External peripheral:
One 2-channel DMA engine supports
external peripheral connected to memory
bus
Each DMA channel supports memory-tomemory transfers
Power management (patent pending)
Power save during normal operation
–
Disables unused modules
Power save during sleep mode
–
Sets memory controller to refresh
–
Disables all modules except selected
wakeup modules
–
Wakeup on valid packets or characters
Vector interrupt controller
Decreased bus traffic and rapid interrupt
service
Hardware interrupt prioritization
General purpose timers/counters
16 independent 16-bit or 32-bit
programmable timers or counters
–
Each with an I/O pin
Mode selectable into:
–
–
External gated timer mode
–
External event counter
Can be concatenated
Resolution to measure minute-range
events
Source clock selectable: internal clock or
external pulse event
Each can be individually enabled/disabled
System timers
Watchdog timer
System bus monitor timer
System bus arbiter timer
Peripheral bus monitor timer
General purpose I/O
50 programmable GPIO pins (muxed with
other functions)
Software-readable powerup status
registers for every pin for customerdefined bootstrapping
External interrupts
4 external programmable interrupts
–
Rising or falling edge-sensitive
–
Low level- or high level-sensitive
Clock generator
On-chip phase locked loop (PLL)
Software programmable PLL parameters
Optional external oscillator
Separate PLL for USB
Operating grades/Ambient temperatures
200 MHz: 0 – 70° C
162 MHz: -40 – +85° C
125 MHz: 0 – 70° C
Internal timer mode
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3
System-level interfaces
System-level interfaces
Figure 1 shows the NS9750B-A1 system-level hardware interfaces.
I 2C
JTAG
USB Host or Device
Ethernet
Serial
1284
NS9750B-A1
LCD
GPIO
Controls
System
Memory/
Peripheral
Data
Ext. DMA control
Address
Ext. IRQ
Timers/Counters
PCI/Cardbus
USB Host control
Clocks & Reset
Power & Ground
Figure 1: System-level hardware interfaces
NS9750B-A1 interfaces
–
Ethernet MII/RMII interface to an external
PHY
Up to 24-bit TFT or STN color and
monochrome LCD controller
–
Two external DMA channels
System Memory interface
–
Four external interrupt pins
programmed to rising or falling edge,
or to high or low level
–
Sixteen 16-bit or 32-bit programmable
timers or counters
–
Two control signals to support USB
host
–
Glueless connection to SDRAM
–
Glueless connection to buffered
PC100 DIMM
–
Glueless connection to SRAM
–
Glueless connection to Flash memory
or ROM
PCI muxed with CardBus interface
USB host or device interface
I2C interface
50 GPIO pins muxed with:
4
–
Four 8-pin-each serial ports, each
programmable to UART or SPI
–
1284 port
JTAG development interface
Clock interfaces for crystal or external
oscillator
–
System clock
–
USB clock
Clock interface for optional LCD external
oscillator
Power and ground
NS9750B-A1 Datasheet
03/2006
System configuration
System configuration
The PLL and other system settings can be configured at powerup before the CPU boots. External
pins configure the necessary control register bits at powerup. External pulldown resistors can be
used to configure the PLL and system configuration registers depending on the application. The
recommended value is 2.2k ohm to 2.4k ohm.
This table describes how each bit is used to configure the powerup settings, where 1 indicates the
internal pullup resistor and 0 indicates an external pulldown resistor. Table 2 shows PLL ND[4:0]
multiplier values. Figure 9, "NS9750B-A1 BGA layout," on page 82 shows the bootstrap pins.
Pin name
Configuration bits
rtck
PCI arbiter configuration
0 External PCI arbiter
1 Internal PCI arbiter
boot_strap[0]
Chip select 1 byte_lane_enable_n/write_enable_n configuration bootstrap
select
0 byte_lane_enable_n (2.4K pulldown added)
1 write_enable_n for byte-wide devices (default)
boot_strap[4:3]
Chip
00
01
11
boot_strap[2]
Memory interface read mode bootstrap select
Note: An external pulldown resistor must be used; this selects command
delayed mode. Clock delayed mode is reserved for future use.
0 Command delayed mode
Commands are launched on a 90-degree phase-shifted AHB clock, and
AHB clock is routed to the external dynamic memory.
1 Clock delayed mode
Reserved for future use.
boot_strap[1]
CardBus mode bootstrap select
0 CardBus mode
1 PCI mode
gpio[49]
Chip select polarity
0 Active high
1 Active low
gpio[44]
Endian mode
0 Big Endian
1 Little Endian
reset_done
Bootup mode
0 Boot from SDRAM using serial SPI EEPROM
1 Boot from flash/ROM
select 1 data width bootstrap select
16 bits
8 bits
32 bits
Table 1: Configuration pins— Bootstrap initialization
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5
System configuration
Pin name
Configuration bits
gpio[19]
RESERVED. This pin must not be pulled to logic 0 until reset_done is a logic 1.
gpio[17], gpio[12],
gpio[10], gpio [8],
gpio[4]
PLL ND[4:0] (PLL multiplier, ND+1)
See Table 2: PLL ND[4:0].
gpio[2], gpio[0]
PLL FS[1:0] (PLL
gpio[2], [0]
10
11
00
01
frequency select)
FS
Divide by
00
1
01
2
10
4
11
8
Table 1: Configuration pins— Bootstrap initialization
Register configuration: gpio 17, 12, 10, 8, 4
Multiplier
11010
32
00100
31
11000
30
11001
29
11110
28
11111
27
11100
26
11101
25
10010
24
10011
23
10000
22
10001
21
10110
20
10111
19
10100
18
10101
17
01010
16
01011
15
01000
14
01001
13
Table 2: PLL ND[4:0]
6
NS9750B-A1 Datasheet
03/2006
General Purpose ID register
Register configuration: gpio 17, 12, 10, 8, 4
Multiplier
01110
12
01111
11
01100
10
01101
9
00010
8
00011
7
00000
6
00001
5
00110
4
00111
3
00100
2
00101
1
Table 2: PLL ND[4:0]
General Purpose ID register
There are 32 additional GPIO pins that are used to create a general purpose, user-defined ID
register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
gpio
[41]
gpio
[40]
gpio
[39]
gpio
[38]
gpio
[37]
gpio
[36]
gpio
[35]
gpio
[34]
gpio
[33]
gpio
[32]
gpio
[31]
gpio
[30]
gpio
[29]
gpio
[28]
gpio
[27]
gpio
[26]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
gpio
[25]
gpio
[23]
gpio
[22]
gpio
[21]
gpio
[18]
gpio
[16]
gpio
[15]
gpio
[14]
gpio
[13]
gpio
[11]
gpio
[09]
gpio
[07]
gpio
[06]
gpio
[05]
gpio
[03]
gpio
[01]
These external signals are registered at powerup. Read these signals for general purpose status
information.
www.digi.com
7
System boot
System boot
There are two ways to boot the NS9750B-A1 system:
From a fast Flash over the system memory bus
From an inexpensive, but slower, serial EEPROM through SPI port B
Both boot methods are glueless. The bootstrap pin, RESET_DONEn, indicates where to boot on a
system powerup. Flash boot can be done from 8-bit, 16-bit, or 32-bit ROM or Flash.
Serial EEPROM boot is supported by NS9750B-A1 hardware. A configuration header in the EEPROM
specifies total number of words to be fetched from EEPROM, as well as a system memory
configuration and a memory controller configuration. The boot engine configures the memory
controller and system memory, fetches data from low-cost serial EEPROM, and writes the data to
external system memory, holding the CPU in reset, then enables the CPU.
Reset
Master reset using an external reset pin resets NS9750B-A1. Only the AHB bus error status registers
retain their values; software read resets these error status registers. The input reset pin can be
driven by a system reset circuit or a simple power-on reset circuit.
RESET_DONE as an input
Used at bootup only:
When set to 0, the system boots from SDRAM through the serial SPI EEPROM.
When set to 1, the system boots from Flash/ROM. This is the default.
RESET_DONE as an output
Sets to 1, per Step 6 in the boot sequence:
If the system is booting from serial EEPROM through the SPI port, the boot program must be loaded
into the SDRAM before the CPU is released from reset. The memory controller is powered up with
dy_cs_n[0] enabled with a default set of SDRAM configurations. The default address range for
dy_cs_n[0] is from 0x0000 0000. The other chip selects are disabled.
SPI boot sequence
1
When the system reset turns to inactive, the reset signal to the CPU is still held active.
2
An I/O module on the peripheral bus (BBus) reads from a serial ROM device that contains the
memory controller settings and the boot program.
3
The BBus-to-AHB bridge requests and gets the system bus.
8
NS9750B-A1 Datasheet
03/2006
System Clock
4
The memory controller settings are read from the serial EEPROM and used to initialize the
memory controller.
5
The BBus-to-AHB bridge loads the boot program into the SDRAM, starting at address 0.
6
The reset signal going to the CPU is released once the boot program is loaded. RESET_DONE is
now set to 1.
7
The CPU begins to execute code from address 0x0000 0000.
You can use one of these software resets to reset the NS9750B-A1. Select the reset by setting the
appropriate bit in the appropriate register:
Watchdog timer can issue reset upon Watchdog timer expiration.
Software reset can reset individual internal modules or all modules except memory and CPU.
The system is reset whenever software sets the PLL SW change bit to 1.
Hardware reset duration is 4ms for PLL to stabilize. Software reset duration depends on speed
grade, as shown in Table 3.
Speed grade
CPU clock cycles
Duration
200 MHz
128
640 ns
162 MHz
128
790 ns
125 MHz
128
1024 ns
Table 3: Software reset duration
The minimum reset pulse width is 10 crystal clocks.
System Clock
The system clock reference is provided to the NS9750B-A1 by an external oscillator; Table 4 shows
sample clock frequency settings for each chip speed grade.
Speed
cpu_clk
hclk (main bus)
bbus_clk
200 MHz
200 (199.0656)
99.5328
49.7664
162 MHz
162.2016
81.1008
40.5504
125 MHz
125.3376
62.6688
31.3344
Table 4: Sample clock frequency settings with 29.4912 MHz oscillator
The oscillator must be connected to the x1_sys_osc input (C8 pin) on the NS9750B-A1, as shown in
Figure 2.
www.digi.com
9
System Clock
3R3V
TB2
Y2
Y2_PWR
C9
100nF
4
2
1
VCC
GND
TEST
OUT
Y2_OUT
3
330 OHM
SM_Oscillator
The clock input range is 20-40MHz. A
29.4912 MHz oscillator allows full speed
operation.
C19
330 OHM
10pF
X2
X1_SYS_OSC
(20-40MHz)
R12
1M
2
C20
C8
4
X1_SYS
10pF
NS9750B-A1
X2_XTAL
U1
SN74LVC1GU04
Figure 2: NS9750B-A1 system clock
The PLL parameters are initialized on powerup reset and can be changed by software from fmax to
1/2 fmax. For a 200 MHz grade, then, the CPU may change from 200 MHz to 100 MHz, the AHB
system bus may change from 100 MHz to 50 MHz, and the peripheral BBus may change from 50 MHz
to 25 MHz. If changed by software, the system resets automatically after the PLL stabilizes
(approximately 4 ms).
The system clock provides clocks for CPU, AHB system bus, peripheral BBus, PCI/CardBus, LCD,
timers, memory controller, and BBus modules (serial modules and 1284 parallel port).
The Ethernet MAC uses external clocks from a MII PHY or a RMII PHY. For a MII PHY, these clocks are
input signals: rx_clk on pin T3 for receive clock and tx_clk on pin V3 for transmit clock. For a RMII,
there is only one clock, and it connects to the rx_clk on pin T3. In this case, the transmit clock
tx_clk, pin V3, should be tied low.
PCI/CardBus, LCD controller, serial modules (UART, SPI), and 1284 port can optionally use external
clock signals.
10
NS9750B-A1 Datasheet
03/2006
USB clock
USB clock
USB is clocked by a separate PLL driven by an external 48 MHz crystal, or it can be driven directly
by an external 48 MHz oscillator. Figure 3 shows a USB circuit.
** = Optional 48.000MHz Oscillator
3R3V
TB1 **
Y1_PWR
BEAD_0805_601
**
C9
100nF
4
2
1
Y1
**
VCC
GND
TEST
OUT
Y1_OUT
3
R6
**
X1_USB
X1_USB_OSC
100 OHM
SM_Oscillator_48M
NS9750B-A1
L4
Crystal circuit
1uH_5%
X1_IN
TANK_LC
R8
1
2
C16
100pF_5%
TANK_RC
R7
62 OHMS
Tank Circuit
1.5M
4
3
48.0000MHz
X1
C15
C17
10pF
10pF
R9
X2_USB
X2_USB_OSC
100 OHM
X1 is a 48 MHz 3rd harmonic (OT) crystal. It
has the same physical characteristics as a 16
MHz crystal. The circuit may have a tendency
to oscillate at 16 MHz unless precautions are
taken. A LC-tank circuit is added to provide a
“low-impedance” for the 16 MHz oscillation to
ground.
Figure 3: USB clock
www.digi.com
11
NS9750B-A1 pinout and signal descriptions
NS9750B-A1 pinout and signal descriptions
Each pinout table applies to a specific interface, and contains the following information:
Heading
Description
Pin #
The pin number assignment for a specific I/O signal.
Signal
Name
The pin name for each I/O signal.Some signals have multiple function modes and are identified
accordingly. The mode is configured through firmware using one or more configuration registers.
_n in the signal name indicates that this signal is active low.
U/D
U or D indicates whether the pin is a pullup resistor or a pulldown resistor:
U — Pullup (input current source)
D — Pulldown (input current sink)
If no value appears, that pin is neither a pullup nor pulldown resistor.
I/O
The type of signal — input, output, or input/output.
OD
(mA)
The output drive strength of an output buffer. The NS9750B-A1 uses one of three drivers:
2 mA
4 mA
8 mA
More detailed signal descriptions are provided for selected modules.
System Memory interface
OD
(mA)
I/O
Description
addr[0]
8
O
Address bus signal
B20
addr[1]
8
O
Address bus signal
C19
addr[2]
8
O
Address bus signal
A20
addr[3]
8
O
Address bus signal
B19
addr[4]
8
O
Address bus signal
C18
addr[5]
8
O
Address bus signal
A19
addr[6]
8
O
Address bus signal
A17
addr[7]
8
O
Address bus signal
C16
addr[8]
8
O
Address bus signal
B16
addr[9]
8
O
Address bus signal
A16
addr[10]
8
O
Address bus signal
D15
addr[11]
8
O
Address bus signal
Pin #
Signal Name
A21
U/D
Table 5: System Memory interface pinout
12
NS9750B-A1 Datasheet
03/2006
System Memory interface
OD
(mA)
I/O
Description
addr[12]
8
O
Address bus signal
B15
addr[13]
8
O
Address bus signal
A15
addr[14]
8
O
Address bus signal
C14
addr[15]
8
O
Address bus signal
B14
addr[16]
8
O
Address bus signal
A14
addr[17]
8
O
Address bus signal
A13
addr[18]
8
O
Address bus signal
B13
addr[19]
8
O
Address bus signal
C13
addr[20]
8
O
Address bus signal
A12
addr[21]
8
O
Address bus signal
B12
addr[22]
8
O
Address bus signal
C12
addr[23]
8
O
Address bus signal
D12
addr[24]
8
O
Address bus signal
A11
addr[25]
8
O
Address bus signal
B11
addr[26]
8
O
Address bus signal
C11
addr[27]
8
O
Address bus signal
G2
clk_en[0]
8
O
SDRAM clock enable
H3
clk_en[1]
8
O
SDRAM clock enable
G1
clk_en[2]
8
O
SDRAM clock enable
H2
clk_en[3]
8
O
SDRAM clock enable
A10
clk_out[0]
8
O
SDRAM reference clock. Connect to clk_in using
series termination.
A9
clk_out[1]
8
O
SDRAM clock
A5
clk_out[2]
8
O
SDRAM clock
A4
clk_out[3]
8
O
SDRAM clock
G26
data[0]
8
I/O
Data bus signal
H24
data[1]
8
I/O
Data bus signal
G25
data[2]
8
I/O
Data bus signal
F26
data[3]
8
I/O
Data bus signal
G24
data[4]
8
I/O
Data bus signal
F25
data[5]
8
I/O
Data bus signal
E26
data[6]
8
I/O
Data bus signal
Pin #
Signal Name
C15
U/D
Table 5: System Memory interface pinout
www.digi.com
13
System Memory interface
OD
(mA)
I/O
Description
data[7]
8
I/O
Data bus signal
E25
data[8]
8
I/O
Data bus signal
D26
data[9]
8
I/O
Data bus signal
F23
data[10]
8
I/O
Data bus signal
E24
data[11]
8
I/O
Data bus signal
D25
data[12]
8
I/O
Data bus signal
C26
data[13]
8
I/O
Data bus signal
E23
data[14]
8
I/O
Data bus signal
D24
data[15]
8
I/O
Data bus signal
C25
data[16]
8
I/O
Data bus signal
B26
data[17]
8
I/O
Data bus signal
D22
data[18]
8
I/O
Data bus signal
C23
data[19]
8
I/O
Data bus signal
B24
data[20]
8
I/O
Data bus signal
A25
data[21]
8
I/O
Data bus signal
C22
data[22]
8
I/O
Data bus signal
D21
data[23]
8
I/O
Data bus signal
B23
data[24]
8
I/O
Data bus signal
A24
data[25]
8
I/O
Data bus signal
A23
data[26]
8
I/O
Data bus signal
B22
data[27]
8
I/O
Data bus signal
C21
data[28]
8
I/O
Data bus signal
A22
data[29]
8
I/O
Data bus signal
B21
data[30]
8
I/O
Data bus signal
C20
data[31]
8
I/O
Data bus signal
E1
data_mask[0]
8
O
SDRAM data mask signal
F2
data_mask[1]
8
O
SDRAM data mask signal
G3
data_mask[2]
8
O
SDRAM data mask signal
F1
data_mask[3]
8
O
SDRAM data mask signal
C5
clk_in
I
SDRAM feedback clock. Connect to clk_out[0].
B4
byte_lane_sel_n[0]
O
Static memory byte_lane_enable[0] or
write_enable_n[0] for byte-wide device signals
Pin #
Signal Name
F24
U/D
8
Table 5: System Memory interface pinout
14
NS9750B-A1 Datasheet
03/2006
System Memory interface
OD
(mA)
I/O
Description
byte_lane_sel_n[1]
8
O
Static memory byte_lane_enable[1] or
write_enable_n[1] for byte-wide device signals
D1
byte_lane_sel_n[2]
8
O
Static memory byte_lane_enable[2] or
write_enable_n[2] for byte-wide device signals
F3
byte_lane_sel_n[3]
8
O
Static memory byte_lane_enable[3] or
write_enable_n[3] for byte-wide device signals
B5
cas_n
8
O
SDRAM column address strobe
A8
dy_cs_n[0]
8
O
SDRAM chip select signal
B8
dy_cs_n[1]
8
O
SDRAM chip select signal
A6
dy_cs_n[2]
8
O
SDRAM chip select signal
C7
dy_cs_n[3]
8
O
SDRAM chip select signal
C6
st_oe_n
8
O
Static memory output enable
D6
ras_n
8
O
SDRAM row address strobe
H1
dy_pwr_n
8
O
SyncFlash power down
B10
st_cs_n[0]
8
O
Static memory chip select signal
C10
st_cs_n[1]
8
O
Static memory chip select signal
B9
st_cs_n[2]
8
O
Static memory chip select signal
C9
st_cs_n[3]
8
O
Static memory chip select signal
B6
we_n
8
O
SDRAM write enable. Used for static and SDRAM
devices.
J3
ta_strb
I
Slow peripheral transfer acknowledge
Pin #
Signal Name
F4
U/D
U
Table 5: System Memory interface pinout
www.digi.com
15
System Memory interface signals
System Memory interface signals
Table 6 describes the System Memory interface signals in more detail. All signals are internal to the
chip.
Name
I/O
Description
addr[27:0]
O
Address output. Used for both static and SDRAM devices. SDRAM
memories use bits [14:0]; static memories use bits [25:0].
clk_en[3:0]
O
SDRAM clock enable. Used for SDRAM devices.
Note: The clk_en signals are associated with the dy_cs_n signals.
clk_out[3:1]
O
SDRAM clocks. Used for SDRAM devices.
clk_out[0]
O
SDRAM clk_out[0] is connected to clk_in.
data[31:0]
I/O
Data to/from memory. Used for the static memory controller and the
dynamic memory controller.
data_mask[3:0]
O
Data mask output to SDRAMs. Used for SDRAM devices.
clk_in
I
Feedback clock. Always connects to clk_out[0].
byte_lane_sel_n[3:0]
O
Static memory byte lane select, active low, or write_enable_n for bytewide devices.
cas_n
O
Column address strobe. Used for SDRAM devices.
dy_cs_n[3:0]
O
SDRAM chip selects. Used for SDRAM devices.
st_oe_n
O
Output enable for static memories. Used for static memory devices.
ras_n
O
Row address strobe. Used for SDRAM devices.
st_cs_n[3:0]
O
Static memory chip selects. Default active low. Used for static memory
devices.
we_n
O
Write enable. Used for SDRAM and static memories.
ta_strb
I
Slow peripheral transfer acknowledge can be used to terminate static
memory cycles sooner than the number of wait states programmed in the
chip select setup register.
Table 6: System Memory interface signal descriptions
16
NS9750B-A1 Datasheet
03/2006
System Memory interface signals
Figure 4 shows NS9750B-A1 SDRAM clock termination.
All series termination resistors
must be placed close to driver
clk_out[0]
clk_in
CLK_IN
NS9750B-A1
clk_out[1]
Always connect clk_out[0] to clk_in
using series termination.
Must not drive any SDRAM loads.
Data in from SDRAMs is sampled on
the rising edge of this clock.
This trace can be a loop 2 to 3 inches in length.
Read data clock will be delayed 180pS/per inch.
UNUSED_CLK
Unused clk_outs are
terminated only
clk_out[2]
SDRAM_CLK[2]
R1
C3
clk_out[3]
SDRAM Bank A
Address, data, and commands are
sampled by SDRAMs on the rising edge
of these clocks.
SDRAM_CLK[3]
R3
C4
SDRAM Bank B
SDRAM banks have AC
termination placed at end
of traces
Figure 4: SDRAM clock termination
www.digi.com
17
Ethernet interface
Ethernet interface
Signal name
Pin #
MII
RMII
AB1
col
AA2
OD
(mA)
Description
I/O
MII
RMII
N/C
I
Collision
Pull low external to
NS9750B-A1
crs
crs_dv
I
Carrier sense
Carrier sense
AC1
enet_phy_
int_n
enet_phy_
int_n
I
Ethernet PHY interrupt
Ethernet PHY interrupt
AA3
mdc
mdc
4
O
MII management
interface clock
MII management
interface clock
AB2
mdio
mdio
2
I/O
MII management data
MII management data
T3
rx_clk
ref_clk
I
Receive clock
Reference clock
V2
rx_dv
N/C
I
Receive data valid
Pull low external to
NS9750B-A1
W1
rx_er
rx_er
I
Receive error
Optional signal; pull low
to NS9750B-A1 if not
used.
V1
rxd[0]
rxd[0]
I
Receive data bit 0
Receive data bit 0
U3
rxd[1]
rxd[1]
I
Receive data bit 1
Receive data bit 1
U2
rxd[2]
N/C
I
Receive data bit 2
Pull low external to
NS9750B-A1
U1
rxd[3]
N/C
I
Receive data bit 3
Pull low external to
NS9750B-A1
V3
tx_clk
N/C
I
Transmit clock
Pull low external to
NS9750B-A1
AA1
tx_en
tx_en
2
O
Transmit enable
Transmit enable
Y3
tx_er
N/C
2
O
Transmit error
N/A
Y2
txd[0]
txd[0]
2
O
Transmit data bit 0
Transmit data bit 0
W3
txd[1]
txd[1]
2
O
Transmit data bit 1
Transmit data bit 1
Y1
txd[2]
N/C
2
O
Transmit data bit 2
N/A
W2
txd[3]
N/C
2
O
Transmit data bit 3
N/A
U/D
U
U
Table 7: Ethernet interface pinout
18
NS9750B-A1 Datasheet
03/2006
Clock generation/system pins
Clock generation/system pins
Pin #
Signal name
C8
OD
(mA)
I/O
Description
x1_sys_osc
I
System clock oscillator circuit input
D9
x1_usb_osc
I
USB clock crystal oscillator circuit input. (Connect
to GND if USB is not used.)
A7
x2_usb_osc
O
USB clock crystal oscillator circuit output
AC21
reset_done
U
I/O
CPU is enabled once the boot program is loaded.
Reset_done is set to 1.
H25
reset_n
U
I
System reset input signal.
AD20
bist_en_n
I
Enable internal BIST operation
AF21
pll_test_n
I
Enable PLL testing
AE21
scan_en_n
I
Enable internal scan testing
B18
sys_pll_dvdd
System clock PLL 1.5V digital power
A18
sys_pll_dvss
System clock PLL digital ground
B17
sys_pll_avdd
System clock PLL 3.3V analog power
C17
sys_pll_avss
System clock PLL analog ground
J2
lcdclk
D2
E3
U/D
2
U
I
External LCD clock input
sreset_n
I
System reset. sreset_n is the same as reset, but
does not reset the system PLL.
sreset_n_enable
I
Tie to 3.3V to enable the sreset_n input.
Tie to ground to disable the sreset_n input.
T2
boot_strap[0]
U
2
I/O
Chip select 1 static memory byte_lane_enable_n,
or write_enable_n for byte-wide devices bootstrap
select
N3
boot_strap[1]
U
2
I/O
CardBus mode bootstrap select
P1
boot_strap[2]
U
2
I/O
Memory interface read mode bootstrap select
P2
boot_strap[3]
U
2
I/O
Chip select 1 data width bootstrap select
P3
boot_strap[4]
U
2
I/O
Chip select 1 data width bootstrap select
Table 8: Clock generation/system pins pinout
www.digi.com
19
bist_en_n, pll_test_n, and scan_en_n
bist_en_n, pll_test_n, and scan_en_n
Table 9 is a truth/termination table for bist_en_n, pll_test_n, and scan_en_n.
Normal operation
Arm debug
pll_test_n
pull up
pull up
10K recommended
bist_en_n
pull down
pull up
10K pullup = debug
2.4K pulldown = normal
scan_en_n
pull down
pull down
2.4K recommended
Table 9: bist_en_n, pll_test_n, & scan_en_n truth/termination table
PCI interface
The PCI interface can be set to PCI host or PCI device (slave) using the pci_central_resource_n
pin.
Notes:
All output drivers for PCI meet the standard PCI driver specification.
All table notes can be found after Table 11: CardBus IO muxed signals.
OD
(mA)
I/O
Description
ad[0]1
N/A
I/O
PCI time-multiplexed address/data bus
H26
ad[1]1
N/A
I/O
PCI time-multiplexed address/data bus
J25
ad[2]1
N/A
I/O
PCI time-multiplexed address/data bus
J26
ad[3]1
N/A
I/O
PCI time-multiplexed address/data bus
K24
ad[4]1
N/A
I/O
PCI time-multiplexed address/data bus
K25
ad[5]1
N/A
I/O
PCI time-multiplexed address/data bus
K26
ad[6]1
N/A
I/O
PCI time-multiplexed address/data bus
L24
ad[7]1
N/A
I/O
PCI time-multiplexed address/data bus
L26
ad[8]1
N/A
I/O
PCI time-multiplexed address/data bus
1
N/A
I/O
PCI time-multiplexed address/data bus
Pin #
Signal Name
J24
U/D
M24
ad[9]
M25
ad[10]1
N/A
I/O
PCI time-multiplexed address/data bus
M26
1
ad[11]
N/A
I/O
PCI time-multiplexed address/data bus
N24
ad[12]1
N/A
I/O
PCI time-multiplexed address/data bus
N25
1
ad[13]
N/A
I/O
PCI time-multiplexed address/data bus
N26
ad[14]1
N/A
I/O
PCI time-multiplexed address/data bus
P26
ad[15]1
N/A
I/O
PCI time-multiplexed address/data bus
Table 10: PCI interface pinout
20
NS9750B-A1 Datasheet
03/2006
PCI interface
OD
(mA)
I/O
Description
ad[16]1
N/A
I/O
PCI time-multiplexed address/data bus
V26
1
ad[17]
N/A
I/O
PCI time-multiplexed address/data bus
V25
ad[18]1
N/A
I/O
PCI time-multiplexed address/data bus
W26
1
ad[19]
N/A
I/O
PCI time-multiplexed address/data bus
V24
ad[20]1
N/A
I/O
PCI time-multiplexed address/data bus
W25
1
ad[21]
N/A
I/O
PCI time-multiplexed address/data bus
Y26
ad[22]1
N/A
I/O
PCI time-multiplexed address/data bus
W24
ad[23]1
N/A
I/O
PCI time-multiplexed address/data bus
Y24
ad[24]1
N/A
I/O
PCI time-multiplexed address/data bus
AA25
ad[25]1
N/A
I/O
PCI time-multiplexed address/data bus
AB26
ad[26]1
N/A
I/O
PCI time-multiplexed address/data bus
AA24
ad[27]1
N/A
I/O
PCI time-multiplexed address/data bus
AB25
ad[28]1
N/A
I/O
PCI time-multiplexed address/data bus
AC26
ad[29]1
N/A
I/O
PCI time-multiplexed address/data bus
AD26
ad[30]1
N/A
I/O
PCI time-multiplexed address/data bus
AC25
ad[31]1
N/A
I/O
PCI time-multiplexed address/data bus
L25
cbe_n[0]1
N/A
I/O
Command/byte enable
P25
cbe_n[1]1
N/A
I/O
Command/byte enable
U25
cbe_n[2]1
N/A
I/O
Command/byte enable
AA26
cbe_n[3]1
N/A
I/O
Command/byte enable
T26
devsel_n2
N/A
I/O
Device select
U26
frame_n2
N/A
I/O
Cycle frame
Y25
idsel3, 4
N/A
I
Initialization device select:
Pin #
Signal Name
U24
U/D
For PCI host applications, connect to AD11.
For PCI device applications, connection is
determined by the PCI device number assigned
to the NS9750B-A1.
For CardBus applications, connect to external
pullup resistor.
Do not allow input to float in any application.
T24
irdy_n2
N/A
I/O
Initiator ready
P24
1
par
N/A
I/O
Parity signal
R25
perr_n2
N/A
I/O
Parity error
Table 10: PCI interface pinout
www.digi.com
21
PCI/CardBus signals
OD
(mA)
I/O
Description
serr_n2
N/A
I/O
System error:
Input: pci_central_resource_n = 0
Output: pci_central_resource_n = 1
R24
stop_n2
N/A
I/O
Stop signal
T25
2
trdy_n
N/A
I/O
Target ready
AC24
pci_arb_gnt_1_n6
N/A
O
PCI channel 1 grant
AD23
6
pci_arb_gnt_2_n
N/A
O
PCI channel 2 grant
AE24
pci_arb_gnt_3_n6
N/A
O
PCI channel 3 grant
AD25
pci_arb_req_1_n2
N/A
I
PCI channel 1 request
AB23
pci_arb_req_2_n2
N/A
I
PCI channel 2 request
AC22
pci_arb_req_3_n2
N/A
I
PCI channel 3 request
AF23
pci_central_resource_n
N/A
I
PCI internal central resource enable
AF25
pci_int_a_n2
N/A
I/O
PCI interrupt request A, output if external central
resource used
AF24
pci_int_b_n2
N/A
I/O
PCI interrupt request B, CCLKRUN# for CardBus
applications
AE23
pci_int_c_n2
N/A
I
PCI interrupt request C
AD22
pci_int_d_n2
N/A
I
PCI interrupt request D
AE26
pci_reset_n3
N/A
I/O
PCI reset, output if internal central resource
enabled
AB24
pci_clk_in
N/A
I
PCI clock in. (Connected to pci_clk_out or an
externally generated PCI reference clock.)
AA23
pci_clk_out
N/A
O
PCI clock out
Pin #
Signal Name
R26
U/D
D
U
Table 10: PCI interface pinout
PCI/CardBus signals
Most of the CardBus signals are the same as the PCI signals. Other CardBus signals are unique and
multiplexed with PCI signals for the NS9750B-A1. Table 11 shows these unique signals.
PCI signal
CardBus signal
CardBus type
Description
INTA#
CINT#4
Input
CardBus interrupt pin. The INTA2PCI pin in the
PCI Miscellaneous Support register must be
set to 0.
Table 11: CardBus IO muxed signals
22
NS9750B-A1 Datasheet
03/2006
PCI/CardBus signals
PCI signal
CardBus signal
CardBus type
Description
INTB#
CCLKRUN#4
Bidir
CardBus pin used to negotiate with the
external CardBus device before stopping the
clock.
Allows external CardBus device to request
that the clock be restarted.
INTC#
CSTSCHG5
Input
CardBus status change interrupt signal.
4
GNT1#
CGNT#
Output
Grant to external CardBus device from
NS9750B-A1’s internal arbiter.
GNT2#
CVS1
Output
Voltage sense pin. Normally driven low by
NS9750B-A1, but toggled during interrogation
of the external CardBus device to find voltage
requirements.
Note: Do not connect directly to the
CardBus connector. See the diagram
“CardBus system connections to
NS9750B-A1” in the NS9750B-A1
Hardware Reference.
GNT3#
CVS2
Output
Voltage sense pin. Normally driven low by
NS9750B-A1, but toggled during interrogation
of the external CardBus device to find voltage
requirements.
REQ1#
CREQ#4
Input
Request from external CardBus device to
NS9750B-A1’s internal arbiter.
REQ2#
CCD14
Input
Card detect pin. Pulled up when the socket is
empty and pulled low when the external
CardBus device is in the socket.
REQ3#
CCD24
Input
Card detect pin. Pulled up when the socket is
empty and pulled low when the external
CardBus device is in the socket.
Table 11: CardBus IO muxed signals
Notes:
1
Add external pulldown resistor or drive with the NS9750B-A1 only if the PCI interface is not being used.
Figure 5, "NS9750B-A1 unused PCI termination," shows which signals can be driven by the
NS9750B-A1 and which signals require pullups or pulldowns.
2
Add external pullup resistors regardless of whether the PCI interface is being used.
3
Add external pullup resistor only if the PCI interface is not being used.
4
Add external pullup resistor in CardBus mode.
5
Add external pulldown resistor in CardBus mode.
6
Add external pullup only if the PCI interface is being used and this signal is also being used.
www.digi.com
23
PCI/CardBus signals
Figure 5 shows how to terminate an unused PCI.
3.3V
U1D
PCI
R2 10K
R3 10K
R4 10K
R5 10K
R6 10K
PCI_VB
DEVSELFRAMETRDYIRDY-
L25
P25
U25
AA26
T26
U26
Y25
T25
T24
AC24
AD23
AE24
AD25
AB23
AC22
AF25
AF24
AE23
AD22
R7 10K
R8 10K
AE26
PERRSTOP-
R25
P24
R26
R24
AF23
AB24
AD0
AD1
AD2
AD3
AD4
AD5
AD6
DEVSEL*
AD7
FRAME*
AD8
IDSEL in
AD9
TRDY*
AD10
IRDY*
AD11
AD12
GNT1*
AD13
GNT2*
AD14
GNT3*
AD15
AD16
REQ1* in
AD17
REQ2* in
AD18
REQ3* in
AD19
INTA* in if rsc_in =0 AD20
INTB* in if PCI mode AD21
AD22
INTC* in
AD23
INTD* in
AD24
AD25
RESET*
AD26
AD27
PERR*
AD28
PAR
SERR* in if rsc_in =0 AD29
AD30
STOP*
AD31
RSC_IN* pulled down
CBE0*
CBE1*
CBE2*
CBE3*
CLKIN pulled up CLKOUT
J24
H26
J25
J26
K24
K25
K26
L24
L26
M24
M25
M26
N24
N25
N26
P26
U24
V26
V25
W26
V24
W25
Y26
W24
Y24
AA25
AB26
AA24
AB25
AC26
AD26
AC25
AA23
PCI_CLKOUT
R1
NS9750B-A1
PCI_CLKIN
47-56
Figure 5: NS9750B-A1 unused PCI termination
Notes:
Startup code needs to put the PCI bridge into reset.
PCI Mode: Boot_strap[1]. N3 = default; no pulldown.
NS9750B-A1 is the current PCI bus master. Signals that it can drive should have individual
pullups.
24
NS9750B-A1 Datasheet
03/2006
GPIO MUX
GPIO MUX
The BBus utility contains the control pins for each GPIO MUX bit. Each pin can be selected
individually; that is, you can select any option (00, 01, 02, 03) for any pin, by setting the
appropriate bit in the appropriate register.
Some signals are muxed to two different GPIO pins, to maximize the number of possible
applications. These duplicate signals are marked as such in the Descriptions column in the
table. Selecting the primary GPIO pin and the duplicate GPIO pin for the same function is not
recommended. If both the primary GPIO pin and duplicate GPIO pin are programmed for the
same function, however, the primary GPIO pin has precedence and will be used.
The 00 option for the serial ports (B, A, C, and D) are configured for UART and SPI mode,
respectively; that is, the UART option is shown first, followed by the SPI option if there is one.
If only one value appears, it is the UART mode value. SPI options all begin with SPI.
U/D
OD
(mA)
I/O
Descriptions (4 options: 00, 01, 02, 03)
gpio[0]1
U
2
I/O
00
01
02
03
Ser port B TxData / SPI port B dout
DMA ch 1 done (duplicate)
Timer 1 (duplicate)
GPIO 0
AE18
gpio[1]
U
2
I/O
00
01
02
03
Ser port B RxData / SPI port B din
DMA ch 1 req (duplicate)
Ext IRQ 0
GPIO 1
AF18
gpio[2]1
U
2
I/O
00
01
02
03
Ser port B RTS
Timer 0
DMA ch 2 read enable
GPIO 2
AD17
gpio[3]
U
2
I/O
00
01
02
03
Ser port B CTS
1284 nAck (peripheral-driven)
DMA ch 1 req
GPIO 3
AE17
gpio[4]1
U
2
I/O
00
01
02
03
Ser port B DTR
1284 busy (peripheral-driven)
DMA ch 1 done
GPIO 4
AF17
gpio[5]
U
2
I/O
00
01
02
03
Ser port B DSR
1284 PError (peripheral-driven)
DMA ch 1 read enable
GPIO 5
Pin #
Signal name
AF19
Table 12: GPIO MUX pinout
www.digi.com
25
GPIO MUX
Pin #
Signal name
U/D
OD
(mA)
I/O
Descriptions (4 options: 00, 01, 02, 03)
AD16
gpio[6]
U
2
I/O
00
01
02
03
Ser port B RI / SPI port B clk
1284 nFault (peripheral-driven)1
Timer 7 (duplicate)
GPIO 6
AE16
gpio[7]
U
2
I/O
00
01
02
03
Ser port B DCD / SPI port B enable
DMA ch 1 read enable (duplicate)
Ext IRQ 1
GPIO 7
AD15
gpio[8]1
U
2
I/O
00
01
02
03
Ser port A TxData / SPI port A dout
Reserved
Reserved
GPIO 8
AE15
gpio[9]
U
2
I/O
00
01
02
03
Ser port A RxData / SPI port A din
Reserved
Timer 8 (duplicate)
GPIO 9
AF15
gpio[10]1
U
2
I/O
00
01
02
03:
Ser port A RTS
Reserved
Reserved
GPIO 10
AD14
gpio[11]
U
2
I/O
00
01
02
03
Ser port A CTS
Ext IRQ2 (duplicate)
Timer 0 (duplicate)
GPIO 11
AE14
gpio[12]1
U
2
I/O
00
01
02
03
Ser port A DTR
Reserved
Reserved
GPIO 12
AF14
gpio[13]
U
2
00
01
02
03
Ser port A DSR
Ext IRQ 0 (duplicate)
Timer 10 (duplicate)
GPIO 13
AF13
gpio[14]
U
2
I/O
00
01
02
03
Ser port A RI / SPI port A clk
Timer 1
Reserved
GPIO 14
AE13
gpio[15]
U
2
I/O
00
01
02
03
Ser port A DCD / Ser port A enable
Timer 2
Reserved
GPIO 15
I/O
Table 12: GPIO MUX pinout
26
NS9750B-A1 Datasheet
03/2006
GPIO MUX
Pin #
Signal name
U/D
OD
(mA)
I/O
Descriptions (4 options: 00, 01, 02, 03)
AD13
gpio[16]2
U
2
I/O
00
01
02
03
Reserved output
1284 nFault (peripheral-driven, duplicate)3
Timer 11 (duplicate) or USB OVR
GPIO 16
AF12
gpio[17]1,2
U
2
I/O
00
01
02
03
USB power relay
Reserved
Reserved
GPIO 17
AE12
gpio[18]
U
4
I/O
00
01
02
03
Ethernet CAM reject
LCD power enable
Ext IRQ 3 (duplicate)
GPIO 18
AD12
gpio[19]1
U
4
I/O
00
01
02
03
Ethernet CAM req
LCD line-horz sync
DMA ch 2 read enable (duplicate)
GPIO 19
AC12
gpio[20]1
U
8
I/O
00
01
02
03
Ser port C DTR
LCD clock
Reserved
GPIO 20
AF11
gpio[21]
U
4
I/O
00
01
02
03
Ser port C DSR
LCD frame pulse-vert
Reserved
GPIO 21
AE11
gpio[22]
U
4
I/O
00
01
02
03
Ser port C RI / SPI port C clk
LCD AC bias-data enable
Reserved
GPIO 22
AD11
gpio[23]
U
4
I/O
00
01
02
03
Ser port C DCD / SPI port C enable
LCD line end
Timer 14 (duplicate)
GPIO 23
AF10
gpio[24]1
U
4
I/O
00
01
02
03
Ser port D DTR
LCD data bit 0
Reserved
GPIO 24
AE10
gpio[25]
U
4
I/O
00
01
02
03
Ser port D DSR
LCD data bit 1
Timer 15 (duplicate)
GPIO 25
Table 12: GPIO MUX pinout
www.digi.com
27
GPIO MUX
Pin #
Signal name
U/D
OD
(mA)
I/O
Descriptions (4 options: 00, 01, 02, 03)
AD10
gpio[26]
U
4
I/O
00
01
02
03
Ser port D RI / SPI port D clk
LCD data bit 2
Timer 3
GPIO 26
AF9
gpio[27]
U
4
I/O
00
01
02
03
Ser port D DCD / SPI port D enable
LCD data bit 3
Timer 4
GPIO 27
AE9
gpio[28]
U
4
I/O
00
01
02
03
Ext IRQ 1 (duplicate)
LCD data bit 4
LCD data bit 8 (duplicate)
GPIO 28
AF8
gpio[29]
U
4
I/O
00
01
02
03
Timer 5
LCD data bit 5
LCD data bit 9 (duplicate)
GPIO 29
AD9
gpio[30]
U
4
I/O
00
01
02
03
Timer 6
LCD data bit 6
LCD data bit 10 (duplicate)
GPIO 30
AE8
gpio[31]
U
4
I/O
00
01
02
03
Timer 7
LCD data bit 7
LCD data bit 11 (duplicate)
GPIO 31
AF7
gpio[32]
U
4
I/O
00
01
02
03
Ext IRQ 2
1284 Data 1 (bidirectional)
LCD data bit 8
GPIO 32
AD8
gpio[33]
U
4
I/O
00
01
02
03
Timer 8
1284 Data 2 (bidirectional)
LCD data bit 9
GPIO 33
AD7
gpio[34]
U
4
I/O
00
01
02
03
Timer 9
1284 Data 3 (bidirectional)
LCD data bit 10
GPIO 34
AE6
gpio[35]
U
4
I/O
00
01
02
03
Timer 10
1284 Data 4 (bidirectional)
LCD data bit 11
GPIO 35
Table 12: GPIO MUX pinout
28
NS9750B-A1 Datasheet
03/2006
GPIO MUX
Pin #
Signal name
U/D
OD
(mA)
I/O
Descriptions (4 options: 00, 01, 02, 03)
AF5
gpio[36]
U
4
I/O
00
01
02
03
Reserved
1284 Data 5 (bidirectional)
LCD data bit 12
GPIO 36
AD6
gpio[37]
U
4
I/O
00
01
02
03
Reserved
1284 Data 6 (bidirectional)
LCD data bit 13
GPIO 37
AE5
gpio[38]
U
4
I/O
00
01
02
03
Reserved
1284 Data 7 (bidirectional)
LCD data bit 14
GPIO 38
AF4
gpio[39]
U
4
I/O
00
01
02
03
Reserved
1284 Data 8 (bidirectional)
LCD data bit 15
GPIO 39
AC6
gpio[40]
U
4
I/O
00
01
02
03
Ser port C TxData / SPI port C dout
Ext IRQ 3
LCD data bit 16
GPIO 40
AD5
gpio[41]
U
4
I/O
00
01
02
03
Ser port C RxData / SPI port C din
Timer 11
LCD data bit 17
GPIO 41
AE4
gpio[42]
U
4
I/O
00
01
02
03
Ser port C RTS
Timer 12
LCD data bit 18
GPIO 42
AF3
gpio[43]
U
4
I/O
00
01
02
03
Ser port C CTS
Timer 13
LCD data bit 19
GPIO 43
AD2
gpio[44]1
U
4
I/O
00
01
02
03
Ser port D TxData / SPI port D dout
1284 Select (peripheral-driven)
LCD data bit 20
GPIO 44
AE1
gpio[45]
U
4
I/O
00
01
02
03
Ser port D RxData / SPI port D din
1284 nStrobe (host-driven)
LCD data bit 21
GPIO 45
Table 12: GPIO MUX pinout
www.digi.com
29
GPIO MUX
Pin #
Signal name
U/D
OD
(mA)
I/O
Descriptions (4 options: 00, 01, 02, 03)
AB3
gpio[46]
U
4
I/O
00
01
02
03
Ser port D RTS
1284 nAutoFd (host-driven)
LCD data bit 22
GPIO 46
AA4
gpio[47]
U
4
I/O
00
01
02
03
Ser port D CTS
1284 nInit (host-driven)
LCD data bit 23
GPIO 47
AC2
gpio[48]
U
2
I/O
00
01
02
03
Timer 14
1284 SelectIn (host-driven)
DMA ch 2 req
GPIO 48
AD1
gpio[49]1
U
2
I/O
00
01
02
03
Timer 15
1284 peripheral logic high (peripheral-driven)
DMA ch 2 done
GPIO 49
1
This pin is used for bootstrap initialization (see Table 1, “Configuration pins— Bootstrap initialization,”
on page 5). Note that the GPIO pins used as bootstrap pins have a defined powerup state that is
required for the appropriate NS9750B-A1 configuration. If these GPIO pins are also used to control
external devices (for example, power switch enable), the powerup state for the external device should
be compatible with the bootstrap state. If the powerup state is not compatible with the bootstrap
state, either select a different GPIO pin to control the external device or add additional circuitry to
reach the proper powerup state to the external device.
2
gpio[17] is used as both a bootstrap input pin for PLL_ND and an output that controls a power switch for
USB Host power. If the power switch needs to powerup in the inactive state, the enable to the power
switch must be the same value as the bootstrap value for PLL_ND; for example, if PLL_ND requires high on
gpio[17], a high true power switch must be selected. gpio[16] is used for USB_OVR and should have a
noise filter to prevent false indications of overcurrent, unless the USB power IC has this filter built in. See
“Example: Implementing gpio[16] and gpio[17]” on page 31 for an illustration.
3
The nFault signal GPIO6 or GPIO16 can be used as a code-controlled direction pin for the transceiver. The
polarity cannot be altered inside the NS9750B-A1; an inverter will be required.
Table 12: GPIO MUX pinout
30
NS9750B-A1 Datasheet
03/2006
LCD module signals
Example: Implementing gpio[16] and gpio[17]
NS97xx
This circuit is required to prevent USB
power being enabled before code has s et
GPIO[17] to mode 00. Pulling down
GPIO[17] effects CPU speed.
USB Power
Controller
GPIO[xy]
2.4K
O ENABLE_n
NAND2
OVERCUR_n O
USB_PWR,
GPIO[17],
BOOTST_ND4
3.3V
USB_OVR
GPIO[16]
Rfilter
INV
Cfilter
Rpull-up
RC filter = 500uS
LCD module signals
The LCD module signals are multiplexed with GPIO pins. They include seven control signals and up
to 24 data signals. Table 13 describes the control signals. Table 14 and Table 15 provide details for
the data signals.
Signal name
Type
Description
CLPOWER
Output
LCD panel power enable
CLLP
Output
Line synchronization pulse (STN) / horizontal synchronization
pulse (TFT)
CLCP
Output
LCD panel clock
CLFP
Output
Frame pulse (STN) / vertical synchronization pulse (TFT)
CLAC
Output
STN AC bias drive or TFT data enable output
CLD[23:0]
Output
LCD panel data (see Table 14 and Table 15)
CLLE
Output
Line end signal
Table 13: LCD module signal descriptions
www.digi.com
31
LCD module signals
The CLD[23:0] signal has eight modes of operation:
TFT 24-bit interface
4-bit mono STN single panel
TFT 18-bit interface
4-bit mono STN dual panel
Color STN single panel
8-bit mono STN single panel
Color STN dual panel
8-bit mono STN dual panel
Table 14 shows which CLD[23:0] pins provide the pixel data to the STN panel for each mode of
operation.
Legend:
–
Ext pin = External pin
–
CUSTN = Color upper panel STN, dual and/or single panel
–
CLSTN = Color lower panel STN, single
–
MUSTN = Mono upper panel STN, dual and/or single panel
–
MLSTN = Mono lower panel STN, single
–
N/A = not used
–
01 and 02 = The option number/position in the Description field of the GPIO mux pinout.
See “GPIO MUX” on page 25 for more information.
Color
STN
dual
panel
4-bit
mono
STN
single
panel
4-bit
mono
STN
dual
panel
8-bit
mono
STN
single
panel
8-bit
mono
STN
dual
panel
CLD[23] AA4=LCD data bit 23 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[22] AB3=LCD data bit 22 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[21] AE1=LCD data bit 21 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[20] AD2=LCD data bit 20 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[19] AF3=LCD data bit 19 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[18] AE4=LCD data bit 18 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[17] AD5=LCD data bit 17 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[16] AC6=LCD data bit16 (O2) N/A
N/A
N/A
N/A
N/A
N/A
CLD[15] AF4=LCD data bit 15 (O2) N/A
CLSTN[0]1
N/A
N/A
N/A
MLSTN[0]1
CLD[14] AE5=LCD data bit 14 (O2) N/A
CLSTN[1]
N/A
N/A
N/A
MLSTN[1]
CLD[13] AD6=LCD data bit 13 (O2) N/A
CLSTN[2]
N/A
N/A
N/A
MLSTN[2]
CLD[12] AF5=LCD data bit 12 (O2) N/A
CLSTN[3]
N/A
N/A
N/A
MLSTN[3]
Ext
pin
GPIO pin &
description
Color
STN
single
panel
Table 14: CLD[23:0] pin descriptions for STN display
32
NS9750B-A1 Datasheet
03/2006
LCD module signals
Ext
pin
GPIO pin &
description
Color
STN
single
panel
CLD[11] AE6=LCD data bit 11 (O2) N/A
Color
STN
dual
panel
4-bit
mono
STN
single
panel
4-bit
mono
STN
dual
panel
8-bit
mono
STN
single
panel
8-bit
mono
STN
dual
panel
CLSTN[4]
N/A
MLSTN[0]1
N/A
MLSTN[4]
CLSTN[5]
N/A
MLSTN[1]
N/A
MLSTN[5]
AE8=LCD data bit 11 (O2)
CLD[10] AD7=LCD data bit 10 (O2) N/A
AD9=LCD data bit 10 (O2)
CLD[9]
AD8=LCD data bit 9 (O2)
AF8=LCD data bit 9 (O2)
N/A
CLSTN[6]
N/A
MLSTN[2]
N/A
MLSTN[6]
CLD[8]
AF7=LCD data bit 8 (O2)
AE9=LCD data bit 8 (O2)
N/A
CLSTN[7]
N/A
MLSTN[3]
N/A
MLSTN[7]
CLD[7]
AE8=LCD data bit 7 (O1)
CUSTN[0]1
CUSTN[0]1
N/A
N/A
MUSTN[0] MUSTN[0]1
CLD[6]
AD9=LCD data bit 6 (O1)
CUSTN[1]
CUSTN[1]
N/A
N/A
MUSTN[1] MUSTN[1]
CLD[5]
AF8=LCD data bit 5 (O1)
CUSTN[2]
CUSTN[2]
N/A
N/A
MUSTN[2] MUSTN[2]
CLD[4]
AE9=LCD data bit 4 (O1)
CUSTN[3]
CUSTN[3]
N/A
N/A
MUSTN[3] MUSTN[3]
CLD[3]
AF9=LCD data bit 3 (O1)
CUSTN[4]
CUSTN[4]
MUSTN[0] MUSTN[0]1
CLD[2]
AD10=LCD data bit 2 (O1) CUSTN[5]
CUSTN[5]
MUSTN[1] MUSTN[1] MUSTN[5] MUSTN[5]
CLD[1]
AE10=LCD data bit 1 (O1) CUSTN[6]
CUSTN[6]
MUSTN[2] MUSTN[2] MUSTN[6] MUSTN[6]
CLD[0]
AF10=LCD data bit 0 (O1) CUSTN[7]
CUSTN[7]
MUSTN[3] MUSTN[3] MUSTN[7] MUSTN[7]
1
MUSTN[4] MUSTN[4]
This data bit corresponds to the first “pixel position.” For example, for an 8-bit mono STN display,
CUSTN[0] is the leftmost pixel on the panel and CUSTN[7] is the rightmost pixel within the 8-bit data.
For a color STN display, bits [7, 6, 5] form the leftmost pixel.
Table 14: CLD[23:0] pin descriptions for STN display
Table 15 shows which CLD[23:0] pins provide the pixel data to the TFT panel for each of the
multiplexing modes of operation.
External pin
TFT 24 bit
TFT 15 bit
CLD[23]
BLUE[7]
Reserved
CLD[22]
BLUE[6]
Reserved
CLD[21]
BLUE[5]
Reserved
CLD[20]
BLUE[4]
Reserved
CLD[19]
BLUE[3]
Reserved
CLD[18]
BLUE[2]
Reserved
CLD[17]
BLUE[1]
BLUE[4]
CLD[16]
BLUE[0]
BLUE[3]
Table 15: CLD[23:0] pin descriptions for TFT display
www.digi.com
33
LCD module signals
External pin
TFT 24 bit
TFT 15 bit
CLD[15]
GREEN[7]
BLUE[2]
CLD[14]
GREEN[6]
BLUE[1]
CLD[13]
GREEN[5]
BLUE[0]
CLD[12]
GREEN[4]
Intensity bit
CLD[11]
GREEN[3]
GREEN[4]
CLD[10]
GREEN[2]
GREEN[3]
CLD[9]
GREEN[1]
GREEN[2]
CLD[8]
GREEN[0]
GREEN[1]
CLD[7]
RED[7]
GREEN[0]
CLD[6]
RED[6]
Intensity bit
CLD[5]
RED[5]
RED[4]
CLD[4]
RED[4]
RED[3]
CLD[3]
RED[3]
RED[2]
CLD[2]
RED[2]
RED[1]
CLD[1]
RED[1]
RED[0]
CLD[0]
RED[0]
Intensity bit
Table 15: CLD[23:0] pin descriptions for TFT display
This LCD TFT panel signal multiplexing table shows the RGB alignment to a 15-bit TFT with the
intensity bit not used. The intensity bit, if used, should be connected to the LSB (that is, RED[0],
GREEN[0], BLUE[0]) input of an 18-bit LCD TFT panel as shown in the next table.
4
3
2
1
0
Intensity
18-bit TFT
5
4
3
2
1
0
15-bit TFT
4
3
2
1
0
x
12-bit TFT
3
2
1
0
x
x
9-bit TFT
2
1
0
x
x
x
Table 16: RGB bit alignment according to TFT interface size (one color shown)
If you want reduced resolution, the least significant color bits can be dropped, starting with
Red[0], Green[0], and Blue[0].
34
NS9750B-A1 Datasheet
03/2006
I2C interface
I 2 C interface
OD
(mA)
I/O
Description
iic_scl
4
I/O
I2C serial clock line. Add a 10K resistor to
VDDA(3.3V) if not used.
iic_sda
4
I/O
I2C serial data line. Add a 10K resistor to
VDDA(3.3V) if not used.
Pin #
Signal name
AC15
AF16
U/D
Table 17: I2C interface pinout
USB Interface
Notes:
If not using the USB interface, these pins should be pulled down to ground through a 15K ohm
resistor.
All output drivers for USB meet the standard USB driver specification.
Pin #
Signal name
AB4
AC3
OD
(mA)
I/O
Description
usb_dm
I/O
USB data -
usb_dp
I/O
USB data +
U/D
Table 18: USB interface pinout
www.digi.com
35
JTAG interface for ARM core/boundary scan
JTAG interface for ARM core/boundary scan
trst_n must be pulsed low to initialize the JTAG when a debugger is not attached.
Note:
Pin #
Signal name
AE20
tck
AD18
tdi
AE19
tdo
AC18
tms
AF20
AD19
OD
(mA)
I/O
Description
I
Test clock
I
Test data in
O
Test data out
U
I
Test mode select
trst_n
U
I
Test mode reset
rtck
U
I/O
Returned test clock, ARM core only
U/D
U
2
2
Table 19: JTAG interface/boundary scan pinout
JP1 recommended
instead of R9 during
development phase,
Debug Mode
JP1 or R3
OUT
IN
Disable
IN
OUT
3.3V
R6
10K
JP1
R14
10K
R15
10K
3.3V
AF21
AD20
AE21
3.3V
2.4K
R1
2.4K
10K
R3
3.3V
PLLTESTn
BISTENn
SCA NENn
INPUTS
R5
2.4K
19
17
15
13
11
9
7
5
3
1
PD_PIN19
PD_PIN17
SRE SETn
CLK_EN[0]
AE20
AC18
AD18
SRESETn
TCK
TMS
TDI
JTRSTn
R16
D0
AF20
TCK
TMS
TDI
4
+V
GND
Should be positioned on PCB with
pin 1 facing toward board edge.
SW_PB
3
C3 .001
MR
RST
AC21
AE19
TDO
R9
33
GND
RTCK
AD19
RTCK
R12
2.4K
NS9750B-A1
JTDO
D
RESET monitor
Trip = 2.93V
reset_n
D = Full Debug
P = Production Debug
NOTES:
R7: Boot Method
out - Flash/ROM/S_CS1n
in: - SPI_B PROM to SDRAM/CS0n.
R12: PCI Arbiter
out - Internal
In - External
U2 must be duplicated for each
clock enable used
If CKE on the SDRAM devices
is connected to 3.3V dirrectly or
through a pull-up, U2 is not needed
Figure 6: JTAG interface
NS9750B-A1 Datasheet
03/2006
A
B0
NC7SB3157
TRSTn
reset_n
2
MAX811S
B1
1
to
SDRAM
devices
CKE
4
3
2.4K
R8
R10 33
RES ETn
R13
2.4K
SW1
JTAG
2
V+
JRTCK
1
JRTCK
JTAG 20 PIN
HEADER..
TDO
U1
3.3V
6
3.3V
G2
0 = B0 TO A
S
SRE SETn
P0
R11
JTDO
3.3V
D2
H25
TRSTn
U2
5
R4
HEA DER 10X2.1SP
36
R7
2.4K
MODE
RES ET_DONE
P1
20
18
16
14
12
10
8
6
4
2
R2
10K
Debug mode must be disabled on
customer units in production.
R4
Enable
Master RESET
3.3V
Reserved pins
Reserved pins
Pin#
Description
J1
Tie to ground directly
E2
Tie to ground directly
K3
Tie to ground directly
K2
Tie to ground directly
K1
Tie to ground directly
M2
Tie to ground directly
M1
Tie to ground directly
N1
Tie to ground directly
N2
Tie to ground directly
R1
Tie to ground directly
R2
Tie to ground directly
R3
Tie to ground directly
T1
Tie to ground directly
AD4
Tie to 1.5V core power
AF2
Tie to 3.3V I/O power
AE7
No connect
L3
No connect
B7
No connect
L2
No connect
L1
No connect
M3
No connect
AF6
Tie to ground directly
AC5
Tie to ground directly
AE3
Tie to ground directly
AF22
No connect
AD21
No connect
AE22
No connect
Table 20: Reserved pins
www.digi.com
37
Power ground
Power ground
Pin #
Signal name
Description
J23, K23, U23, V23, D17, AC17, D16, AC16, D11, D10,
AC11, AC10, J4, K4, U4, V4
VDDC
Core power, 1.5V
G23, H23, P23, N23, Y23, W23, D20, AC20, D14, D13,
AC14, AC13, D7, AC7, G4, H4, P4, N4, Y4, W4
VDDS
I/O power, 3.3V
A26, B25, AE25, AF26, D23, C24, AD24, AC23, D5, D4,
C4, E4, AC4, A3, A2, D3, C3, C2, B3, B2, AE2, AD3, A1,
C1, B1, AF1, L23, T23, D18, AC9, L4, T4, M23, R23, D19,
AC19, D8, AC8, M4, R4, L11, L12, L13, L14, L15, L16,
M11, M12, M13, M14, M15, M16, N11, N12, N13, N14,
N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13,
R14, R15, R16, T11, T12, T13, T14, T15, T16
VSS2
Ground
Table 21: Power ground pins
Address and register maps
System address map
The system memory address is divided to allow access to the internal and external resources on the
system bus, as shown in Table 22.
Address range
Size
System functions
0x0000 0000 – 0x0FFF FFFF
256 MB
System memory chip select 4 - Dynamic memory (default)
0x1000 0000 – 0x1FFF FFFF
256 MB
System memory chip select 5 - Dynamic memory (default)
0x2000 0000 – 0x2FFF FFFF
256 MB
System memory chip select 6 - Dynamic memory (default)
0x3000 0000 – 0x3FFF FFFF
256 MB
System memory chip select 7 - Dynamic memory (default)
0x4000 0000 – 0x4FFF FFFF
256 MB
System memory chip select 0 - Static memory (default)
0x5000 0000 – 0x5FFF FFFF
256 MB
System memory chip select 1 - Static memory (default)
0x6000 0000 – 0x6FFF FFFF
256MB
System memory chip select 2 - Static memory (default)
0x7000 0000 – 0x7FFF FFFF
256 MB
System memory chip select 3 - Static memory (default)
0x8000 0000 – 0x8FFF FFFF
256 MB
PCI memory
0x9000 0000 – 0x9FFF FFFF
256 MB
BBus peripherals
0xA000 0000 – 0xA00F FFFF
1 MB
PCI IO
0xA010 0000 – 0xA01F FFFF
1 MB
PCI CONFIG_ADDR
0xA020 0000 – 0xA02F FFFF
1 MB
PCI CONFIG_DATA
Table 22: System address memory map
38
NS9750B-A1 Datasheet
03/2006
BBus peripheral address map
Address range
Size
System functions
0xA030 0000 – 0xA03F FFFF
1 MB
PCI arbiter
0xA040 0000 – 0xA04F FFFF
1 MB
BBus-to-AHB bridge
0xA050 0000 – 0xA05F FFFF
1 MB
Reserved
0xA060 0000 – 0xA06F FFFF
1 MB
Ethernet Communication module
0xA070 0000 – 0xA07F FFFF
1 MB
Memory controller
0xA080 0000 – 0xA08F FFFF
1 MB
LCD controller
0xA090 0000 – 0xA09F FFFF
1 MB
System Control module
0xA0A0 0000 – 0xFFFF FFFF
1526 MB
Reserved
Table 22: System address memory map
BBus peripheral address map
The BBus bridge configuration registers are located at base address 0xA040 0000. The BBus
peripherals are located at base address 0x9000 0000 and span a 256 MB address space. Each BBus
peripheral, with the exception of the SER controllers, resides in a 1 MB address space. Table 23
specifies the address space given to each peripheral.
Base address
Peripheral
0x9000 0000
BBus DMA controller
0x9010 0000
USB controller
0x9020 0000
SER Port B
0x9020 0040
SER Port A
0x9030 0000
SER Port C
0x9030 0040
SER Port D
0x9040 0000
IEEE 1284 controller
0x9050 0000
I2C controller
0x9060 0000
BBus utility
Table 23: BBus peripheral address map
www.digi.com
39
Electrical characteristics
Electrical characteristics
The NS9750B-A1 operates at a 1.5V core, with 3.3V I/O ring voltages.
Absolute maximum ratings
Permanent device damage can occur if the absolute maximum ratings are exceeded even for an
instant.
Parameter
Symbol†
Rating
Unit
DC supply voltage
VDDA
-0.3 to +3.9
V
DC input voltage
VINA
-0.3 to VDDA+0.3
V
DC output voltage
VOUTA
-0.3 to VDDA+0.3
V
DC input current
IIN
±10
mA
Storage temperature
TSTG
-40 to +125
oC
† VDDA, VINA, VOUTA: Ratings of I/O cells for 3.3V interface
Recommended operating conditions
Recommended operating conditions specify voltage and temperature ranges over which a circuit’s
correct logic function is guaranteed. The specified DC electrical characteristics (see “DC electrical
characteristics” on page 42) are satisfied over these ranges.
Parameter
Symbol†
Rating
Unit
DC supply voltage
VDDA
3.0 to 3.6
V
VDDC (core)
1.4 to 1.6
V
VDDC (PLL)
1.425 to 1.575
V
TJ
125
o
Maximum junction temperature
† VDDA: Ratings of I/O cells for 3.3V interface
VDDC: Ratings of internal cells
40
NS9750B-A1 Datasheet
03/2006
C
Maximum power dissipation
Maximum power dissipation
Table 24 shows the maximum power dissipation, including sleep mode information, for I/O and
core:
Operation
Sleep mode with wake up on
CPU clock
Full
No PCI
No PCI,
LCD
All
ports
BBus
ports
AHB bus
ports
No wake
up ports
Total @
200 MHz
1.7 W
1.55 W
1.5 W
350 mW
285 mW
240 mW
180 mW
1W
0.55 W
1W
0.5 W
1.4 W
1.25 W
1.2 W
Core 0.9 W
I/O 0.5 W
0.8 W
0.45 W
0.8 W
0.4 W
1W
950 mW
0.65 W
0.35 W
640 mW
310 mW
Core 1.05 W
I/O 0.65 W
Total @
162 MHz
Total @
125 MHz
1.05 W
Core 0.65 W
I/O 0.4 W
260mW
90 mW
285 mW
210 mW
75 mW
235 mW
210 mW
75 mW
220 mW
220 mW
20 mW
200 mW
170 mW
65 mW
180 mW
210 mW
75 mW
180 mW
20 mW
150 mW
130 mW
50 mW
140 mW
10 mW
170 mW
10 mW
145 mW
140 mW
5 mW
110 mW
105 mW
5 mW
Table 24: NS9750B-A1 maximum power dissipation
Typical power dissipation
Figure 25 shows typical power dissipation for I/O and core:
Operation
Full
No PCI
No PCI,
LCD
Core
I/O
952 mW
419 mW
533 mW
886 mW
353 mW
533 mW
809 mW
287 mW
522 mW
Core
I/O
784 mW
345mW
439mW
715 mW
285 mW
430mW
647 mW
230 mW
418 mW
Core
I/O
588 mW
572 mW
259 mW
228 mW
329 mW
344 mW
512 mW
182 mW
331 mW
CPU clock
Total @ 200 MHz
Total @ 162 MHz
Total @ 125 MHz
Table 25: NS9750B-A1 typical power dissipation
www.digi.com
41
DC electrical characteristics
DC electrical characteristics
DC electrical characteristics specify the worst-case DC electrical performance of the I/O buffers
that are guaranteed over the specified temperature range.
Inputs
All electrical inputs are 3.3V interface.
Note:
VSS = 0V (GND)
Sym
Parameter
VIH
High-level input voltage:
LVTTL level
PCI level
Min
Low-level input voltage:
LVTTL level
PCI level
Max
VIL
Condition
Value
Unit
2.0
0.5VDDA
V
V
0.8
0.3VDDA
V
V
Min/Max
-10/10
μA
Min/Max1
10/200
μA
High-level input current (no
pulldown)
Input buffer with pulldown
VINA=VDDA
IIL
Low-level input current (no pullup)
Input buffer with pullup
VINA=VSS
Min/Max
Min/Max2
-10/10
10/200
μA
μA
IOZ
High-impedance leakage current
VOUTA=VDDA or VSS
Min/Max
-10/10
μA
IDDS
Quiescent supply current
VINA=VDDA or VSS
Max
TBD
IIH
1. Min current = VIN- or VIN at 0.0V.
2. Min current = VIN- or VIN at 0.0V.
USB DC electrical inputs
Symbol
Parameter
Min
Max
Units
VIH
Input high level (driven)
2.0
VDDA-0.6
V
VIZ
Input high level (floating)
2.7
3.6
V
VIL
Input low level
0.8
V
VDI
Differential input sensitivity
0.2
VCM
Differential common mode range
0.8
2.5
Notes:
1
|(usb_dp) - (usb_dm)|
2
Includes VDI range.
42
NS9750B-A1 Datasheet
03/2006
Notes
V
1
V
2
Outputs
Outputs
All electrical outputs are 3.3V interface.
Sym
Parameter
Value
Unit
VOH
High-level output voltage (LVTTL)
Min
VDDA-0.6
V
VOL
Low-level output voltage (LVTTL)
Max
0.4
V
VOH
PCI high-level output voltage
Min
0.9VDDA
V
VOL
PCI low-level output voltage
Max
0.1VDDA
V
USB DC electrical outputs
Symbol
Parameter
Min
Max
Units
Notes
VOL
Output low level
0.0
0.3
V
1
VOH
Output high level
2.8
3.6
V
2
VCRS
Output signal crossover voltage
1.3
2.0
V
3
Notes:
2
Measured with RL of 1.425k ohm to 3.6V.
Measured with RL of 14.25k ohm to GND.
3
Excluding the first transition from the idle state.
1
www.digi.com
43
Reset and edge sensitive input timing requirements
Reset and edge sensitive input timing requirements
The critical timing requirement is the rise and fall time of the input. If the rise time is too slow for
the reset input, the hardware strapping options may be registered incorrectly. If the rise time of a
positive-edge-triggered external interrupt is too slow, then an interrupt may be detected on both
the rising and falling edge of the input signal.
A maximum rise and fall time must be met to ensure that reset and edge sensitive inputs are
handled correctly. With Digi processors, the maximum is 500 nanoseconds as shown:
tR
reset_n or positive edge input
t R max = 500nsec
VIN = 0.8V to 2.0V
tF
negative edge input
t F max = 500nsec
VIN = 2.0V to 0.8V
44
NS9750B-A1 Datasheet
03/2006
Ct
10K
DC/DC
Regulator
2.4K
Sense = 2.93V
3.3V_IN
www.digi.com
A
B
3.3V_IN
3.3V_IN
3.3V
1.5V
LT1963AEQ-1.5
LDO
Regulator
C
D
C to D
Ramp-Down
1.0W
Max.
1.5V
3.3V
CORE
NS9750B-A1
I/O
Peripherals connected
to NS9750B-A1 I/O
3.3V_PERPH
C to D = 1.5V maintained at
80%, or above, until 3.3V
reaches 80% or below.
JA = 30 C/W
TPS2022
EN
Power
Switch
1 Amp
U4
U2
A to B = 1.5V at 80%, or above,
preceeds 3.3V at 80%, or above,
by 1 -100 ms
A to B
Ramp-Up
D = 3.3V_IN at 2.0V
C = 3.3V_IN at 2.93V
B = 3.3V_IN at 2.93V + Td (RESET delay)
A = 3.3V_IN at 2.0V
NS9750B-A1 Power Sequencing Block Diagram - 5V or 3V source
Power Down:
Monitor turns off
3.3V I/O before
1.5V drops.
TI LTC7733
3.3V Power Monitor
CONTROL
CT
RESIN
RESET
VDD
SENSE
U3
5V/3.3V @ 2.5A
LT1765
Power Up:
3.3V I/O is held off
by monitor so that
1.5V core comes
up first.
RESET delay is determined
by capacitor on Ct.
Td = 2.1 x 10,0000 x Ct
Td = sec.; Ct = farads
Ct = 0.22uF = 4.6ms delay
3.3V Source
OR
5.0V Source
U1
Power sequencing
Power sequencing
Use these requirements for power sequencing.
45
Memory timing
Memory timing
Memory AC characteristics are measured with 35pF, unless otherwise noted.
Memory timing contains parameters and diagrams for both SDRAM and SRAM timing.
SDRAM timing
Table 26 describes the values shown in the SDRAM timing diagrams.
Parameter
Description
Min
Max
Unit
M1
data input setup time to rising
1.6
ns
M2
data input hold time to rising
1.5
ns
M3
clk_out high to clk_en high
6.1
ns
M4
clk_out high to address valid
6.1
ns
M5
clk_out high to data_mask
6.1
ns
1, 2
M6
clk_out high to dy_cs_n low
6.1
ns
3, 4
M7
clk_out high to ras_n low
6.1
ns
M8
clk_out high to cas_n low
6.1
ns
M9
clk_out high to we_n low
6.1
ns
M10
clk_out high to data out
6.2
ns
M11
address hold time
3.5
M12
data out hold time
3.8
M13
clk_en high to sdram access
2
2
clock
M14
end sdram access to clk_en low
2
2
clock
Table 26: SDRAM timing parameters
Notes:
1
All four data_mask signals are used for all transfers.
2
All four data_mask signals will go low during a read cycle, for both 16-bit and 32-bit transfers.
3
Only one of the four clk_out signals is used.
4
Only one of the four dy_cs_n signals is used.
46
NS9750B-A1 Datasheet
03/2006
Notes
SDRAM timing
SDRAM burst read (16-bit)
pre
act
read
lat
d-A
d-B
d-C
d-D
d-E
d-F
d-G
d-H
clk_out<3:0>
M2
M1
data<31:16>
M11
M4
addr
Note-1
Note-2
M5
data_mask<3:0>
M6
dy_cs_n<3:0>*
M7
ras_n
M8
cas_n
M9
we_n
Notes:
1
This is the bank and RAS address.
2
This is the CAS address
SDRAM burst read (16-bit), CAS latency = 3
pre
act
read
lat
lat
d-A
d-B
d-C
d-D
d-E
d-F
d-G
d-H
clk_out<3:0>
M2
M1
data<31:16>
M11
M4
addr
Note-1
Note-2
M5
data_mask<3:0>
M6
dy_cs_n<3:0>*
M7
ras_n
M8
cas_n
M9
we_n
Notes:
1
This is the bank and RAS address.
2
This is the CAS address
www.digi.com
47
SDRAM timing
SDRAM burst write (16-bit)
pre
act
wr d-A
d-B
d-C
d-D
d-E
d-F
d-G
clk_out<3:0>
M12
M10
data<31:0>
M4
Note-1
addr
Note-2
M5
data_mask<3:2>
M5
data_mask<1:0>*
M6
dy_cs_n<3:0>*
M7
ras_n
M8
cas_n
M9
we_n
Notes:
1
This is the bank and RAS address.
2
This is the CAS address
SDRAM burst read (32-bit)
prechg
active
read
cas lat
data-A
data-B
clk_out<3:0>
M2
M1
data<31:0>
M4
M11
Note-1
addr
Note-2
M5
data_mask<3:0>*
M6
dy_cs_n<3:0>*
M7
ras_n
M8
cas_n
M9
we_n
Notes:
1
This is the bank and RAS address.
2
This is the CAS address
48
NS9750B-A1 Datasheet
03/2006
data-C
data-D
d-H
SDRAM timing
SDRAM burst read (32-bit), CAS latency = 3
pre
act
read
lat
lat
data-A
data-B
data-C
data-D
clk_out<3:0>
M2
M1
data<31:0>
M4
M11
Note-1
addr
Note-2
M5
data_mask<3:0>*
M6
dy_cs_n<3:0>*
M7
ras_n
M8
cas_n
M9
we_n
Notes:
1
This is the bank and RAS address.
2
This is the CAS address.
SDRAM burst write (32-bit)
prechg
active
wr d-A
data-B
data-C
data-D
clk_out
M10
M12
data<31:0>
M4
Note-1
addr
Note-2
M5
data_mask<3:0>*
M6
dy_cs_n<3:0>
M7
ras_n
M8
cas_n
M9
we_n
Notes:
1
This is the bank and RAS address.
2
This is the CAS address.
www.digi.com
49
SDRAM timing
SDRAM load mode
clk_out<3:0>
M5
dy_cs_n<3:0>*
M7
ras_n
M8
cas_n
M9
we_n
M4
op code
addr<11:0>
SDRAM refresh mode
prechg
CS0 rf
CS1 rf
CS2 rf
CS3 rf
clk_out<3:0>
M6
dy_cs0_n
M6
dy_cs1_n
M6
dy_cs2_n
M6
dy_cs3_n
M7
ras_n
M8
cas_n
M9
we_n
Clock enable timing
clk_out<3:0>
M3
M14
clk_en<3:0>
M13
SDRAM cycle
50
NS9750B-A1 Datasheet
03/2006
SRAM timing
SRAM timing
Table 27 describes the values shown in the SRAM timing diagrams.
Parameter
Description
Min
Max
Unit
+2
ns
M15
clock high to data out valid
M16
data out hold time from clock high
M17
clock high to address valid
M18
address hold time from clock high
M19
clock high to st_cs_n low
+2
ns
1
M20
clock high to st_cs_n high
+2
ns
1
M21
clock high to we_n low
+2
ns
M22
clock high to we_n high
+2
ns
M23
clock high to byte_lanes low
+2
ns
M24
clock high to byte_lanes high
+2
ns
M25
data input setup time to rising clk
4.5
ns
M26
data input hold time to rising clk
M27
clock high to oe_n low
+2
ns
M28
clock high to oe_n high
+2
ns
-2
Notes
ns
+2
-2
ns
ns
4.5
ns
Table 27: SRAM timing parameters
Notes:
1
Only one of the four dy_cs_n signals is used. The diagrams show the active low configuration, which
can be reversed (active high) with the PC field. Use this formula to calculate the length of the st_cs_n
signal:
Tacc + board delay + (optional buffer delays, both address out and data in) + 10ns
www.digi.com
51
SRAM timing
Static RAM read cycles with 0 wait states
clk_out<3:0>
M26
M25
data<31:0>
M17
M18
addr<27:0>
M19
M20
M27
M28
M23
M24
st_cs_n<3:0>
oe_n
byte_lane<3:0>
WTRD = 1
WOEN = 1
If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit
read cycles.
If the PB field is set to 0, the byte_lane signal will always be high.
52
NS9750B-A1 Datasheet
03/2006
SRAM timing
Static RAM asynchronous page mode read, WTPG = 1
Note-1
Note-2
Note-2
Note-2
clk_out<3:0>
M26
M26
M25
M25
data<31:0>
M17
M18
Note-3
addr<27:0>
Note-4
M18
Note-5
Note-6
M19
M20
M27
M28
M23
M24
st_cs_n<3:0>
oe_n
byte_lane<3:0>
Note-7
WTPG = 1
WTRD = 2
If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit
read cycles.
The asynchronous page mode will read 16 bytes in a page cycle. A 32-bit bus will do four 32-bit
reads, as shown (3-2-2-2). A 16-bit bus will do eight 16-bit reads (3-2-2-2-3-2-2-2) per page
cycle, and an 8-bit bus will do sixteen reads (3-2-2-2-3-2-2-2-3-2-2-2-3-2-2-2) per page cycle.
3-2-2-2 is the example used here, but the WTRD and WTPG field can set them differently.
Notes:
1
The length of the first cycle in the page is determined by the WTRD field.
2
The length of the 2nd, 3rd, and 4th cycles is determined by the WTPG field.
3
This is the starting address. The least significant two bits will always be ‘00.’
4
The least significant two bits in the second cycle will always be ‘01.’
5
The least significant two bits in the third cycle will always be ‘10.’
6
The least significant two bits in the fourth cycle will always be ‘11.’
7
If the PB field is set to 0, the byte_lane signal will always be high during a read cycle.
www.digi.com
53
SRAM timing
Static RAM read cycle configurable wait states
clk_out<3:0>
M26
M25
data<31:0>
M17
M18
addr<27:0>
M19
M20
Note-1
st_cs_n<3:0>
M27
M28
Note-1
oe_n
M23
M24
Note-1
byte_lane<3:0>
WTRD = from 1 to 15
WOEN = from 0 to 15
If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit
read cycles.
If the PB field is set to 0, the byte_lane signal will always be high.
The length of the read cycle is determined by the WTRD field.
Note:
The length of the st_cs_n, oe_n, and the byte_lane signals are determined by a
combination of the WTRD and the WOEN fields.
Static RAM sequential write cycles
clk_out<3:0>
M15
M16
M17
M18
M19
M20
data<31:0>
addr<27:0>
st_cs_n<3:0>
M21
M22
we_n
M23
M24
byte_lane<3:0>
M21
byte_lane[3:0] as WE*
M22
Note1
WTWR = 0
WWEN = 0
During a 32-bit transfer, all four byte_lane signals will go low.
During a 16-bit transfer, two byte_lane signals will go low.
During an 8-bit transfer, only one byte_lane signal will go low.
Note:
54
If the PB field is set to 0, the byte_lane signals will function as write enable signals and the
we_n signal will always be high.
NS9750B-A1 Datasheet
03/2006
SRAM timing
Static RAM write cycle
clk_out<3:0>
M15
M16
M17
M18
M19
M20
data<31:0>
addr<27:0>
st_cs_n<3:0>
M21
M22
we_n
M23
M24
byte_lane<3:0>
M21
byte_lane[3:0] as WE*
M22
Note-1
WTWR = 0
WWEN = 0
During a 32-bit transfer, all four byte_lane signals will go low.
During a 16-bit transfer, two byte_lane signals will go low.
During an 8-bit transfer, only one byte_lane signal will go low.
Note:
If the PB field is set to 0, the byte_lane signals will function as write enable signals and the
we_n signal will always be high.
www.digi.com
55
SRAM timing
Static write cycle with configurable wait states
clk_out<3:0>
M15
M16
M17
M18
data<31:0>
addr<17:0>
M19
M20
st_cs_n<3:0>
Note-1
M21
we_n
M22
Note-2
M23
M24
byte_lane<3:0>
Note-3
M21
byte_lane[3:0] as WE*
Note-4
M22
Note-5
WTWR = from 0 to 15
WWEN = from 0 to 15
The WTWR field determines the length on the write cycle.
During a 32-bit transfer, all four byte_lane signals will go low.
During a 16-bit transfer, two byte_lane signals will go low.
During an 8-bit transfer, only one byte_lane signal will go low.
Notes:
1
Timing of the st_cs_n signal is determined with a combination of the WTWR and WWEN fields. The
st_cs_n signal will always go low at least one clock before we_n goes low, and will go high one clock
after we_n goes high.
2
Timing of the we_n signal is determined with a combination of the WTWR and WWEN fields.
3
Timing of the byte_lane signals is determined with a combination of the WTWR and WWEN fields. The
byte_lane signals will always go low one clock before we_n goes low, and will go one clock high after we_n
goes high.
4
If the PB field is set to 0, the byte_lane signals will function as the write enable signals and the we_n signal
will always be high.
5
If the PB field is set to 0, the timing for the byte_lane signals is set with the WTWR and WWEN fields.
56
NS9750B-A1 Datasheet
03/2006
Slow peripheral acknowledge timing
Slow peripheral acknowledge timing
Table 28 describes the values shown in the slow peripheral acknowledge timing diagrams.
Parameter
Description
Min
Max
Unit
+2
ns
M15
clock high to data out valid
M16
data out hold time from clock high
M17
clock high to address valid
M18
address hold time from clock high
M19
clock high to st_cs_n low
+2
ns
1
M20
clock high to st_cs_n high
+2
ns
1
M21
clock high to we_n low
+2
ns
M22
clock high to we_n high
+2
ns
M23
clock high to byte_lanes low
+2
ns
M24
clock high to byte_lanes high
+2
ns
M26
data input hold time to rising clk
M27
clock high to oe_n low
+2
ns
M28
clock high to oe_n high
+2
ns
M29
address/chip select valid to ta_strb high
2
M30
ta_strb pulse width
4
8
CPU cycles
M31
ta_strb rising to chip select/address change
4
10
CPU cycles
M32
data setup to ta_strb rising
0
-2
Notes
ns
+2
-2
ns
ns
4.5
ns
CPU cycles
ns
Table 28: Slow peripheral acknowledge
Note:
1
Only one of the four st_cs_n signals is used. The diagrams show the active low configuration, which can
be reversed (active high) with the PC field.
www.digi.com
57
Slow peripheral acknowledge timing
Slow peripheral acknowledge read
0ns
50ns
100ns
150ns
200ns
clk_out<3:0>
M32
M26
data<31:0>
M17
M18
addr<27:0>
M20
M19
M31
st_cs_n<3:0>
M27
M28
M23
M24
oe_n
byte_lane<3:0>
M29
M30
ta_strb
Slow peripheral acknowledge write
0ns
50ns
100ns
150ns
200ns
clk_out<3:0>
M15
M16
M17
M18
data<31:0>
addr<27:0>
M20
M19
M31
st_cs_n<3:0>
M21
M22
we_n
M23
M24
byte_lane<3:0>
3
M29
M30
6
ta_strb
58
NS9750B-A1 Datasheet
03/2006
Ethernet timing
Ethernet timing
Ethernet AC characteristics are measured with 10pF, unless otherwise noted.
Table 29 describes the values shown in the Ethernet timing diagrams.
Parameter
Description
Min
Max
Unit
Notes
E1
MII tx_clk to txd, tx_en, tx_er
3
11
ns
2
E2
MII rxd, rx_dv, rx_er setup to rx_clk rising
3
ns
E3
MII rxd, rx_dv, rx_er hold from rx_clk rising
1
ns
E4
mdio (input) setup to mdc rising
10
ns
E5
mdio (input) hold from mdc rising
0
ns
E6
mdc to mdio (output)
18
E7
mdc period
80
E8
RMII ref_clk to txd, tx_en
3
E9
RMII rxd, crs, rx_er setup to ref_clk rising
3
ns
E10
RMII rxd, crs, rx_er hold from ref_clk rising
1
ns
E11
MII rx_clk to cam_req
3
E12
MII cam_reject setup to rx_clk rising
N/A
ns
3
E13
MII cam_reject hold from rx_clk rising
N/A
ns
3
38
ns
1, 2
ns
12
10
ns
2
ns
Table 29: Ethernet timing characteristics
Notes:
1
Minimum specification is for fastest AHB bus clock of 100 MHz. Maximum specification is for slowest
AHB bus clock of 50 MHz.
2
Cload = 10pF for all outputs and bidirects.
3
No setup and hold requirements for cam_reject because it is an asynchronous input. This is also true for RMII
PHY applications.
www.digi.com
59
Ethernet timing
Ethernet MII timing
tx_clk
E1
txd[3:0],tx_en,tx_er
rx_clk
E3
E2
rxd[3:0],rx_dv,rx_er
E11
cam_req
E12
E13
cam_reject
E7
mdc
E5
E4
mdio (input)
E6
mdio (output)
Ethernet RMII timing
ref_clk
E8
txd[1:0],tx_en
E9
E10
rxd[1:0],crs,rx_er
E7
mdc
E5
E4
mdio (input)
E6
mdio (output)
60
NS9750B-A1 Datasheet
03/2006
PCI timing
PCI timing
PCI AC characteristics are measured with 10pF, unless otherwise noted.
Table 30 and Table 31 describe the values shown in the PCI timing diagrams.
Parameter
Description
Min
Max
Units
Notes
P1
pci_clk_in to signal valid delay
2
9
ns
1, 2
P2
input setup to pci_clk_in
5
ns
1
P3
input hold from pci_clk_in
0
ns
P4
pci_clk_in to signal active
2
ns
2
P5
pci_clk_in to signal float
28
ns
2
P6
pci_clk_out high time
50%-1
50%+1
ns
3
P7
pci_clk_out low time
50%-1
50%+1
ns
3
P8
pci_clk_in cycle time
30
ns
P9
pci_clk_in high time
11
ns
P10
pci_clk_in low time
11
ns
Table 30: PCI timing characteristics
Notes:
1
2
3
Parameters same for bussed and point-to-point signals.
CLOAD = 10pf on all outputs
pci_clk_out high and low times specified as 50% of the clock period ±1 ns.
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61
PCI timing
Parameter
Description
Min
Max
Units
Notes
P1
pci_clk_in to signal valid delay
2
10
ns
1
P2
input setup to pci_clk_in
5
ns
1
P3
input hold from pci_clk_in
0
ns
P4
pci_clk_in to signal active
2
ns
1
P5
pci_clk_in to signal float
28
ns
1
P6
pci_clk_out high time
50%-1
50%+1
ns
2
P7
pci_clk_out low time
50%-1
50%+1
ns
2
P8
pci_clk_in cycle time
30
ns
P9
pci_clk_in high time
11
ns
P10
pci_clk_in low time
11
ns
Table 31: CardBus timing characteristics
Notes:
1
Minimum times are specified with 0pf and maximum times are specified with 30pf.
2
pci_clk_out high and low times specified as 50% of the clock period ±1 ns.
Internal PCI arbiter timing
pci_clk_in
Switch Master
Switch Master
frame_n
irdy_n
Master 1 Cycle
addr
ad[31:0]
data0
data1
Master 2 Cycle
data2
addr
data0
Master 1 Cycle
addr
data0
P3
pci_arb_req_1_n
P2
pci_arb_req_2_n
P1
pci_arb_gnt_1_n
pci_arb_gnt_2_n
62
NS9750B-A1 Datasheet
03/2006
PCI timing
PCI burst write from NS9750B-A1 timing
pci_clk_in
P1
frame_n
P4
P1
P5
addr
ad[31:0]
data0
data1
data2
data3
data4
data5
data6
data7
P1
cbe_n[3:0]
cmd
byte enables
P1
irdy_n
P2
P3
P2
P3
trdy_n
devsel_n
Note:
The functional timing for trdy_n and devsel_n shows the fastest possible response from the target.
PCI burst read from NS9750B-A1 timing
pci_clk_in
P1
frame_n
P4
ad[31:0]
P1
P5
P2
addr
data0
P3
data1
data2
data3
data4
data5
data6
data7
P1
cbe_n[3:0]
cmd
byte enables
P1
irdy_n
P2
P3
trdy_n
P2
P3
devsel_n
Note:
The functional timing for trdy_n, devsel_n, and the read data on ad[31:0] shows the fastest
possible response from the target.
www.digi.com
63
PCI timing
PCI burst write to NS9750B-A1 timing
pci_clk_in
P2
P3
frame_n
P2
P3
addr
ad[31:0]
data0
data1
data2
data3
data4
data5
data6
data7
P2
cbe_n[3:0]
P3
cmd
byte enables
P2
P3
irdy_n
P1
trdy_n
P1
3x pci_clk_in
devsel_n
PCI burst read to NS9750B-A1 timing
pci_clk_in
P2
P3
frame_n
P2
ad[31:0]
P4
P1
addr
P5
data0
data1
data2
data3
data4
P2
cbe_n[3:0]
data5
data6
data7
P3
cmd
byte enables
P2
P3
irdy_n
P1
trdy_n
P1
3x pci_clk_in
devsel_n
Note:
The functional timing for valid read data on ad[31:0] is just an example. The actual response time
will depend on when the PCI bridge gets access to the AHB bus internal to NS9750B-A1.
pci_clk_out timing
P6
P7
pci_clk_out
pci_clk_in timing
P8
P9
P10
pci_clk_in
64
NS9750B-A1 Datasheet
03/2006
I2C timing
I 2 C timing
I2C AC characteristics are measured with 10pF, unless otherwise noted.
Table 32 describes the values shown in the I2C timing diagram.
Standard mode
Max
Fast mode
Parm
Description
Min
Min
Max
Unit
C1
iic_sda to iic_scl START hold time
4.0
0.6
μs
C2
iic_scl low period
4.7
1.3
μs
C3
iic_scl high period
4.7
1.3
μs
C4
iic_scl to iic_sda DATA hold time
0
0
μs
C5
iic_sda to iic_scl DATA setup time
250
100
ns
C6
iic_scl to iic_sda START setup time
4.7
0.6
μs
C7
iic_scl to iic_sda STOP setup time
4.0
0.6
μs
Table 32: I2C timing parameters
C4
C6
C7
iic_sda
C1
C2
C5
C3
iic_scl
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65
LCD timing
LCD timing
LCD AC characteristics are measured with 10pF, unless otherwise noted.
Table 33 describes the values shown in the LCD timing diagrams.
Parameter
Description
Register
Value
Units
L1
Horizontal front porch blanking
LCDTiming0
HFP+1
CLCP periods
L2
Horizontal sync width
LCDTiming0
HSW+1
CLCP periods
L3
Horizontal period
N/A
L1+L2+L15+L4
CLCP periods
L4
Horizontal backporch
LCDTiming0
HBP+1
CLCP periods
L5
TFT active line
LCDTiming0
16*(PPL+1)
(see note 3)
CLCP periods
L6
LCD panel clock frequency
LCDTiming1
For BCD=0:
CLCDCLK/(PCD+2)
For BCD=1:
CLCDCLK (see note 1)
MHz
L7
TFT vertical sync width
LCDTiming1
VSW+1
H lines
L8
TFT vertical lines/frame
N/A
L7+L9+L10+L11
H lines
L9
TFT vertical back porch
LCDTiming1
VBP
H lines
L10
TFT vertical front porch
LCDTiming1
VFP
H lines
L11
Active lines/frame
LCDTiming1
LPP+1
H lines
L12
STN HSYNC inactive to VSYNC
active
LCDTiming0
HBP+1
CLCP periods
L13
STN vertical sync width
N/A
1
H lines
L14
STN vertical lines/frame
N/A
L11+L16
H lines
L15
STN active line
LCDTiming2
CPL+1 (see note 4)
CLCP periods
L16
STN vertical blanking
LCDTiming1
VSW+VFP+VBP+1
H lines
L17
STN CLCP inactive to HSYNC active
LCDTiming0
HFP+1.5
CLCP periods
L18
CLCP to data/control
(see notes 7 and 8)
-1.0 (min)
+1.5 (max)
ns
L19
CLCP high (see notes 8, 9)
50%±0.5ns
ns
L20
CLCP low (see notes 8, 9)
50%±0.5ns
ns
L21
TFT VSYNC active to HSYNC active
(see note 8)
-0.1ns (min)
+0.1ns (max)
ns
L22
TFT VSYNC active to HSYNC inactive LCDTiming0
HSW
CLCP periods
Table 33: LCD timing parameters
66
NS9750B-A1 Datasheet
03/2006
LCD timing
Parameter
Description
Register
Value
Units
L23
STN VSYNC active to HSYNC
inactive
LCDTiming0
STN color:
14+HSW+HFP
STN Mono8:
6+HSW+HFP
STN Mono4:
10+HSW+HFP
CLCP periods
L24
STN HSYNC inactive to VSYNC
inactive
LCDTiming0
HBP+1
CLCP periods
L25
STN VSYNC inactive to HSYNC
active
LCDTiming0
STN color: HFP+13
STN Mono8: HFP+15
STN Mono4: HFP+9
CLCP periods
L26
CLCP period
12.5 ns (min)
ns
Table 33: LCD timing parameters
Notes:
1
CLCDCLK is selected from 5 possible sources:
— lcdclk/2 (lcdclk is an external oscillator)
— AHB clock
— AHB clock/2
— AHB clock/4
— AHB clock/8
See the LCD chapter in the NS9750B-A1 Hardware Reference for acceptable clock frequencies for the
different display configurations.
2
The polarity of CLLP, CLFP, CLCP, and CLAC can be inverted using control fields in the LCDTiming1 register.
3
The CPL field in the LCDTiming2 register must also be programmed to T5-1 (see the LCD chapter in the
NS9750B-A1 Hardware Reference).
4
The PPL field in the LCDTiming0 register must also be programmed correctly (see the LCD chapter in the
NS9750B-A1 Hardware Reference).
5
These data widths are supported:
— 4-bit mono STN single panel
— 8-bit mono STN single panel
— 8-bit color STN single panel
— 4-bit mono STN dual panel (8 bits to LCD panel)
— 8-bit mono STN dual panel (16 bits to LCD panel)
— 8-bit color STN dual panel (16 bits to LCD panel)
— 24-bit TFT
— 18-bit TFT
6
See the LCD chapter in the NS9750B-A1 Hardware Reference for definitions of these bit fields.
7
Note that data is sampled by the LCD panel on the falling edge of the CLCP in “LCD output timing” on
page 69. If the polarity of CLCP is inverted, this parameter is relative to CLCP falling.
8
Cload = 10pf on all outputs.
9
CLCP high and low times specified as 50% of the clock period ±0.5ns.
10 Maximum allowable LCD panel clock frequency is 80 MHz.
www.digi.com
67
LCD timing
Horizontal timing for STN displays
L3
L1
L2
L4
L17
CLLP
L6
CLCP
L15
Valid Display Data
Blanking
CLD[7:0]
Blanking
Vertical timing for STN displays
L12
L14
L13
CLFP
CLLP
L15
CLD[7:0]
Blank Lines
L16
Valid Display Data
Blank Lines
Valid Display Data
Horizontal timing for TFT displays
L3
L1
L2
L4
CLLP
L6
CLCP
CLAC
CLD[23:0]
L5
Active Display Data
Blanking
Blanking
Vertical timing for TFT displays
L8
L7
L9
L10
CLFP
L11
CLLP
Blanking
Active Display Data
Blanking
CLAC
68
NS9750B-A1 Datasheet
03/2006
LCD timing
HSYNC vs VSYNC timing for STN displays
L12
L23
L25
CLFP
L24
CLLP
HSYNC vs VSYNC timing for TFT displays
L22
L21
CLFP
CLLP
LCD output timing
L26
L19
L20
CLCP
L18
CLD[23:0],CLLP,CLFP,CLLE,CLAC
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69
SPI timing
SPI timing
SPI AC characteristics are measured with 10pF, unless otherwise noted.
Table 34 describes the values shown in the SPI timing diagrams.
Parm
Description
Min
Max
Unit
Modes
Notes
SPI master parameters
SP0
SPI enable low setup to first SPI CLK out
rising
3*TBCLK-10
ns
0, 3
1, 3
SP1
SPI enable low setup to first SPI CLK out
falling
3*TBCLK-10
ns
1, 2
1, 3
SP3
SPI data in setup to SPI CLK out rising
30
ns
0, 3
SP4
SPI data in hold from SPI CLK out rising
0
ns
0, 3
SP5
SPI data in setup to SPI CLK out falling
30
ns
1, 2
SP6
SPI data in hold from SPI CLK out falling
0
ns
1, 2
SP7
SPI CLK out falling to SPI data out valid
10
ns
0, 3
6
SP8
SPI CLK out rising to SPI data out valid
10
ns
1, 2
6
SP9
SPI enable low hold from last SPI CLK out
falling
3*TBCLK-10
ns
0, 3
1, 3
SP10
SPI enable low hold from last SPI CLK out
rising
3*TBCLK-10
ns
1, 2
1, 3
SP11
SPI CLK out high time
SP13*45%
SP13*55%
ns
0, 1, 2, 3 4
SP12
SPI CLK out low time
SP13*45%
SP13*55%
ns
0, 1, 2, 3
SP13
SPI CLK out period
TBCLK*6
ns
0, 1, 2, 3 3
4
SPI slave parameters
SP14
SPI enable low setup to first SPI CLK in
rising
30
ns
0, 3
1
SP15
SPI enable low setup to first SPI CLK in
falling
30
ns
1, 2
1
SP16
SPI data in setup to SPI CLK in rising
0
ns
0, 3
SP17
SPI data in hold from SPI CLK in rising
60
ns
0, 3
SP18
SPI data in setup to SPI CLK in falling
0
ns
1, 2
SP19
SPI data in hold from SPI CLK in falling
60
ns
1, 2
SP20
SPI CLK in falling to SPI data out valid
20
70
ns
0, 3
6
SP21
SPI CLK in rising to SPI data out valid
20
70
ns
1, 2
6
SP22
SPI enable low hold from last SPI CLK in
falling
15
ns
0, 3
1
Table 34: SPI timing parameters
70
NS9750B-A1 Datasheet
03/2006
SPI timing
Parm
Description
Min
Max
SP23
SPI enable low hold from last SPI CLK in
rising
15
SP24
SPI CLK in high time
SP26*40%
SP25
SPI CLK in low time
SP26*40%
SP26
SPI CLK in period
TBCLK*10
Unit
Modes
Notes
ns
1, 2
1
SP26*60%
ns
0, 1, 2, 3 5
SP26*60%
ns
0, 1, 2, 3 5
ns
0, 1, 2, 3
Table 34: SPI timing parameters
Notes:
1
Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial Channel B/A/C/D Control
Register B (see the NS9750B-A1 Hardware Reference) is set to 1. Note that in SPI slave mode, only a
value of 0 (low enable) is valid; the SPI slave is fixed to an active low chip select.
2
SPI data order is reversed (that is, LSB last and MSB first) if the BITORDR bit in Serial Channel B/A/C/D
Control Register B (see the NS9750B-A1 Hardware Reference) is set to 0.
3
TBCLK is period of BBus clock.
4
±5% duty cycle skew.
5
±10% duty cycle skew.
6
Cload = 10pf for all outputs.
7
SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Channel B/A/C/D Control
Register A (see the NS9750B-A1 Hardware Reference).
SPI master mode 0 and 1: 2-byte transfer (see note 7)
SP0
SP3
SP11
SP12
SP13
S9
SPI CLK Out (Mode 0)
SP1
SP5
S10
SPI CLK Out (Mode 1)
SPI Enable
SP7
SPI Data Out
MSB
LSB
SP4
LSB
MSB
LSB
SP6
MSB
SPI Data In
SP8
MSB
LSB
SPI master mode 2 and 3: 2-byte transfer (see note 7)
SP0
SP3
S9
SPI CLK Out (Mode 2)
SP1
SP5
S10
SPI CLK Out (Mode 3)
SPI Enable
SP7
SPI Data Out
MSB
SP4
SPI Data In
MSB
SP8
LSB
MSB
LSB
LSB
MSB
LSB
SP6
www.digi.com
71
SPI timing
SPI slave mode 0 and 1: 2-byte transfer (see note 7)
SP14
SP16
SP24
SP25
SP26
S22
SPI CLK In (Mode 0)
SP15
SP18
S23
SPI CLK In (Mode 1)
SPI Enable
SP20
MSB
SPI Data Out
LSB
SP17
SPI Data In
SP21
MSB
LSB
SP19
MSB
LSB
MSB
LSB
SPI slave mode 2 and 3: 2-byte transfer (see note 7)
SP14
SP16
S22
SPI CLK In (Mode 2)
SP15
SP18
S23
SPI CLK In (Mode 3)
SPI Enable
SP20
SPI Data Out
MSB
SP17
SPI Data In
72
SP21
LSB
MSB
LSB
LSB
MSB
LSB
SP19
MSB
NS9750B-A1 Datasheet
03/2006
IEEE 1284 timing
IEEE 1284 timing
IEEE 1284 AC characteristics are measured with 10pF, unless otherwise noted.
Table 35 describes the values shown in the IEEE 1284 timing diagram.
Parameter
Description
Min
Max
Unit
Note
IE1
Busy-while-Strobe
0
500
ns
1
IE2
Busy high to nAck low
0
IE3
Busy high
1000
ns
2
IE4
nAck low
500
ns
3
IE5
nAck high to Busy low
500
ns
3
ns
Table 35: IEEE 1284 timing parameters
Notes:
1
The range is 0ns up to one time unit.
2
Two time units.
3
Three time units.
IEEE 1284 timing example
The IEEE 1284 timing is determined by the BBus clock and the Granularity Count register (GCR)
setting. In this example, the BBus clock is 50 MHz and the Granularity Count register is set to 25.
The basic time unit is 1/50 MHz x 25, which is 500ns.
Data[8:1]
nStrobe
IE3
IE1
IE5
Busy
IE2
IE4
nAck
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73
USB timing
USB timing
Table 36 and Table 37 describe the values shown in the USB timing diagrams.
Parameter
Description
Min
Max
Unit
Notes
U1
Rise time (10%–90%)
4
20
ns
1
U2
Fall time (10%–90%)
4
20
ns
1
U3
Differential rise and fall time matching
90
111.11
%
2, 5
U4
Driver output resistance
28
44
ohms
3
Table 36: USB full speed timing parameters
Parameter
Description
Min
Max
Unit
Notes
U1
Rise time (10%–90%)
75
300
ns
4
U2
Fall time (10%–90%)
75
300
ns
4
U3
Differential rise and fall time matching
80
125
%
2, 5
Table 37: USB low speed timing parameters
Notes:
1
Load shown in "USB full speed load."
2
U1/U2.
3
Includes resistance of 27 ohm ±2 ohm external series resistor.
4
Load shown in "USB low speed load."
5
Excluding the first transition from the idle state.
USB differential data timing
usb_dp
usb_dm
90%
10%
10%
U1
74
90%
U2
NS9750B-A1 Datasheet
03/2006
USB timing
USB full speed load
Full Speed Buffer
RS
Rs - external resistor
usb_dp
CL = 50pf
RS
usb_dm
CL = 50pf
USB low speed load
Low Speed Buffer
RS
Rs - external resistor
usb_dp
CL = 200pf to 600pf
VDD
RS
1.5K
usb_dm
CL = 200pf to 600pf
www.digi.com
75
Reset and hardware strapping timing
Reset and hardware strapping timing
Reset and hardware strapping AC characteristics are measured with 10pF, unless otherwise noted.
Table 38 describes the values shown in the reset and hardware strapping timing diagram.
Parameter
Description
Min
R1
reset_n minimum time
10
R2
reset_n to reset_done
Max
4
Unit
Notes
x1_sys_osc clock cycles
1
ms
Table 38: Reset and hardware strapping timing parameters
Note:
1
The hardware strapping pins are latched 5 clock cycles after reset_n is deasserted (goes high).
x1_sys_osc
R1
reset_n
R2
reset_done
R1: reset_n must be held low for a minimum of 10 x1_sys_osc clock cycles after power up.
R2: reset_done is asserted 4ms after reset_n is driven high.
76
NS9750B-A1 Datasheet
03/2006
JTAG timing
JTAG timing
JTAG AC characteristics are measured with 10pF, unless otherwise noted.
Table 39 describes the values shown in the JTAG timing diagram.
Parameter
Description
Min
Max
Unit
J1
tms (input) setup to tck rising
5
ns
J2
tms (input) hold to tck rising
2
ns
J3
tdi (input) setup to tck rising
5
ns
J4
tdi (input) hold to tck rising
2
ns
J5
tdo (output) to tck falling
2.5
10
ns
Table 39: JTAG timing parameters
tck
rtck_out
J1
J2
J3
J4
tms
tdi
J5
J5
tdo
trst_n
Notes:
1
Maximum tck rate is 10 MHz.
2
rtck_out is an asynchronous output, driven off of the CPU clock.
3
trst_n is an asynchronous input.
www.digi.com
77
Clock timing
Clock timing
Clock AC characteristics are measured with 10pF, unless otherwise noted.
The next three timing diagrams pertain to clock timing.
USB crystal/external oscillator timing
Table 40 describes the values shown in the USB crystal/external oscillator timing diagram.
Parameter
Description
Min
Max
Unit
Notes
UC1
x1_usb_osc cycle time
20.831
20.835
ns
1
UC2
x1_usb_osc high time
(UC1/2) x 0.4
(UC1/2) x 0.6
ns
UC3
x1_usb_osc low time
(UC1/2) x 0.4
(UC1/2) X 0.6
ns
Table 40: USB crystal/external oscillator timing parameters
Note:
1
If using a crystal, the tolerance must be ±100 ppm or better.
UC1
UC2
UC3
x1_usb_osc
LCD input clock
Table 41 describes the values shown for the LCD input clock timing diagram.
Parameter
Description
Min
Max
LC1
lcdclk cycle time
6.25
LC2
lcdclk high time
(LC1/2) x 0.4
(LC1/2) x 0.6
ns
LC3
lcdclk low time
(LC1/2) x 0.4
(LC1/2) x 0.6
ns
Table 41: LCD input clock timing parameters
Note:
1
The clock rate supplied on lcdclk is twice the actual LCD clock rate.
LC1
LC2
LC3
lcdclk
78
NS9750B-A1 Datasheet
03/2006
Unit
Notes
ns
1
Clock timing
System PLL reference clock timing
Table 42 describes the values shown in the system PLL reference clock timing diagram.
Parameter
Description
Min
Max
Unit
SC1
x1_sys_osc cycle time
25
50
ns
SC2
x1_sys_osc high time
(SC1/2) x 0.45
(SC1/2) x 0.55
ns
SC3
x1_sys_osc low time
(SC1/2) x 0.45
(SC1/2) x 0.55
ns
Table 42: System PLL reference clock timing parameters
SC1
SC2
SC3
x1_sys_osc
www.digi.com
79
Packaging
Packaging
A
The NS9750B-A1 dimensions and pinout are shown in the next two diagrams.
0.3
S
35.0
0.3
35.0
X4
0.2
Figure 7: NS9750B-A1 top view
80
NS9750B-A1 Datasheet
03/2006
S
B
Packaging
2.46 MAX
A
0.6 + 0.1
0.635
1.27
(1.625)
AF
AE
AD
1.27
AC
AB
AA
Y
W
V
U
T
B
R
P
N
M
L
K
//
0.35
0.635
J
H
G
S
F
E
D
C
B
A
0.25
S
1 2 3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
(1.625)
0.75 + 0.15
0.15 M
AB
S
Figure 8: NS9750B-A1 bottom and side view
www.digi.com
81
Packaging
Figure 9 shows the layout of the NS9750B-A1, for use in setting up the board.
AF AE AD AC AB AA
AF1
VSS
AE1
AD1
AC1
GPIO45 GPIO49 PHY_INTn
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
AB1
AA1
Y1
W1
V1
U1
T1
R1
P1
N1
M1
L1
K1
J1
H1
G1
F1
E1
D1
C1
B1
A1
COL
TXEN
TXD_2
RXER
RXD_0
RXD_3
(GND)
(GND)
BSTR_2
(GND)
(GND)
(NC4)
(GND)
(GND)
DQM_3
DQM_0
BLSn_2
VSS
VSS
VSS
DY_PWRn CKE_2
A
AF2
AE2
AD2
AC2
AB2
AA2
Y2
W2
V2
U2
T2
R2
P2
N2
M2
L2
K2
J2
H2
G2
F2
E2
D2
C2
B2
A2
(VDDS)
VSS
GPIO44
GPIO48
MDIO
CRS
TXD_0
TXD_3
RXDV
RXD_2
BSTR_0
(GND)
BSTR_3
(GND)
(GND)
(NC3)
(GND)
LCD_CLK
CKE_3
CKE_0
DQM_1
(GND)
SRSTn
VSS
VSS
VSS
AF3
AE3
AD3
AC3
AB3
AA3
Y3
W3
V3
U3
T3
R3
P3
N3
M3
L3
K3
J3
H3
G3
F3
E3
D3
C3
B3
A3
GPIO43
(GND)
VSS
USB_DP
GPIO46
MDC
TXER
TXD_1
TXCLK
RXD_1
RXCLK
(GND)
BSTR_4
BSTR_1
(NC5)
(NC2)
(GND)
TA_STB
CKE_1
DQM_2
VSS
VSS
VSS
VSS
AF4
AE4
AD4
AC4
AB4
AA4
Y4
W4
V4
U4
T4
R4
P4
N4
M4
L4
K4
J4
H4
G4
F4
E4
D4
C4
B4
A4
GPIO39
GPIO42
(VDDC)
VSS
VDDS
VDDS
VDDC
VDDC
VSS
VSS
VDDS
VDDS
VSS
VSS
VDDC
VDDC
VDDS
VDDS
BLSn_1
VSS
VSS
VSS
BLSn_0
CKO_3
USB_DM GPIO47
BLSn_3 SRST_EN
AF5
AE5
AD5
AC5
D5
C5
B5
A5
GPIO36
GPIO38
GPIO41
(GND)
VSS
CLK_IN
CASn
CKO_2
AF6
AE6
AD6
AC6
D6
C6
B6
A6
(GND)
GPIO35
GPIO37
GPIO40
RASn
ST_OEn
WEn
DCSn_2
AF7
AE7
AD7
AC7
D7
C7
B7
A7
GPIO34
VDDS
AF8
AE8
AD8
AC8
GPIO29
GPIO32
GPIO31
GPIO33
VSS
(NC1)
NS9750B-A1, 388 BGA
VDDS
Top View, Balls Facing Down
DCSn_3 SYS_X2
C8
B8
A8
SYS_X1
DCSn_1
DCSn_0
D9
C9
B9
A9
SCSn_3
SCSn_2
CKO_1
D10
C10
B10
A10
VDDC
SCSn_1
SCSn_0
CKO_0
D11
C11
B11
A11
VSS
VDDC
A27
A26
A25
AE9
AD9
GPIO28
GPIO30
VSS
AF10
AE10
AD10
AC10
AC9
GPIO24
GPIO25
GPIO26
VDDC
AF11
AE11
AD11
AC11
T11
R11
P11
N11
M11
L11
GPIO21
GPIO22
GPIO23
VDDC
VSS
VSS
VSS
VSS
VSS
V1.3
AF12
AE12
AD12
AC12
T12
R12
P12
N12
M12
L12
D12
C12
B12
A12
GPIO17
GPIO18
GPIO19
GPIO20
VSS
VSS
VSS
VSS
VSS
VSS
A24
A23
A22
A21
AF13
AE13
AD13
AC13
T13
R13
P13
M13
L13
D13
C13
B13
A13
GPIO14
GPIO15
GPIO16
VDDS
VSS
VSS
VSS
VSS
VSS
VSS
VDDS
A20
A19
A18
AF14
AE14
AD14
AC14
T14
R14
P14
N14
M14
L14
D14
C14
B14
A14
GPIO13
GPIO12
GPIO11
VDDS
VSS
VSS
VSS
VSS
VSS
VSS
VDDS
A15
A16
A17
N13
AF15
AE15
AD15
AC15
T15
R15
P15
N15
M15
L15
D15
C15
B15
A15
GPIO10
GPIO9
GPIO8
I2C_SCL
VSS
VSS
VSS
VSS
VSS
VSS
A11
A12
A13
A14
C16
B16
A16
AF16
AE16
AC16
T16
R16
P16
N16
M16
L16
D16
I2C_SDA
GPIO7
GPIO6
VDDC
VSS
VSS
VSS
VSS
VSS
VSS
VDDC
A8
A9
A10
AF17
AE17
AD17
AC17
D17
C17
B17
A17
GPIO5
GPIO4
GPIO3
VDDC
AF18
AE18
AD18
AC18
GPIO2
GPIO1
TDI
TMS
AF19
AE19
AD19
AC19
AD16
VDDC SPLL_AG SPLL_AV
VDDS = I/O = 3.3V
VDDC = CORE = 1.5V
GPIO0
TDO
RTCK
VSS
AF20
AE20
AD20
AC20
TRSTn
TCK
BISTENn
VDDS
AF21
AE21
AD21
AC21
NC2
RST_DONE
PLLTSTn SCANENn
VSS = GROUND RETURN
( ) = Reserved
= HW Strap Option
D18
C18
B18
VSS
A5
SPLL_DV
D19
C19
B19
A19
VSS
A2
A4
A6
D20
C20
B20
A20
VDDS
D31
A1
A3
D21
C21
B21
A21
D23
D28
D30
A0
AE22
AD22
AC22
D22
C22
B22
A22
NC3
INTDn
REQn_3
D18
D22
D27
D29
D23
C23
B23
A23
E23
AF23
AE23
AD23
Y23
W23
V23
U23
T23
R23
P23
N23
L23
K23
J23
H23
G23
RSC_IN
INTCn
GNTn_2
VSS
VDDS
VDDS
VDDC
VDDC
VSS
VSS
VDDS
VDDS
VSS
VSS
VDDC
VDDC
VDDS
VDDS
D10
D14
VSS
D19
D24
D26
AF24
AE24
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
P24
N24
M24
L24
K24
J24
H24
G24
F24
E24
D24
C24
B24
A24
INTBn
GNTn_3
VSS
GNTn_1
PCI_CKI
AD27
AD24
AD23
AD20
AD16
IRDYn
STOPn
PAR
AD12
AD9
AD7
AD4
AD0
D1
D4
D7
D11
D15
VSS
D20
D25
AF25
AE25
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
P25
N25
M25
L25
K25
J25
H25
G25
F25
E25
D25
C25
B25
A25
INTAn
VSS
REQn_1
AD31
AD28
AD25
IDSEL
AD21
AD18
CBEn_2
TRDYn
PERRn
CBEn_1
AD13
AD10
CBEn_0
AD5
AD2
RESETn
D2
D5
D8
D12
D16
VSS
D21
AF26
AE26
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
VSS
PCI_RSTn
AD30
AD29
AD26
CBEn_3
AD22
AD19
AD17
FRAMEn
AB23
AA23
DEVSELn SERRn
M23
F23
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SPLL_DG
NC1
REQn_2 PCI_CKO
3
A7
A18
AF22
AC23
2
USB_X2
D8
VSS
USB_X1
AF9
GPIO27
1
P26
N26
M26
L26
K26
J26
H26
G26
F26
E26
D26
C26
B26
A26
AD15
AD14
AD11
AD8
AD6
AD3
AD1
D0
D3
D6
D9
D13
D17
VSS
19
20
21
22
23
24
25
26
Figure 9: NS9750B-A1 BGA layout
For information about hardware strapping options, see Table 1, “Configuration pins— Bootstrap
initialization,” on page 5.
82
NS9750B-A1 Datasheet
03/2006
Product specifications
Product specifications
These tables provide additional information about the NS9750B-A1.
ROHS substance
PPM level
Lead
0
Mercury
0
Cadmium
0
Hexavalent Chromium
0
Polybrominated biphenyls
0
Polybrominated diphenyl ethers
0
Table 43: RoHS specifications
Component
Weight [mg]
Material
CAS no.
Name
Weight [mg]
Weight [%]
Chip
27.037
7440-21-3
Si
27.0370
0.61
Frame
1841.616
223769-10-6
Epoxy resin
865.5600
19.71
7440-50-8
Cu
736.6500
16.77
7440-02-0
Ni
9.2100
0.21
7440-57-5
Au
1.8400
0.04
Other
228.3560
5.20
Bonding wire
6.990
7440-57-5
Au
6.9900
0.16
Ag paste
3.400
7440-22-4
Ag
2.6200
0.06
Epoxy, other
0.7800
0.02
Silica (SiO2)
1747.3570
39.79
Epoxy, other
86.4100
1.97
Phenol Resin
86.4100
1.97
Epoxy resin
Solder ball
Total weight
1920.177
592.400
60676-86-0
CAS no.
Name
7440-31-5
Sn
571.6700
13.02
7440-22-4
Ag
17.7700
0.40
7440-50-8
Cu
2.9600
0.07
4391.620
www.digi.com
83
P/N: 91001324_B
Release date: March 2006
© Digi International Inc. 2005-2006 All rights reserved.
Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a Digi
International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of
Digi International, Inc. in the United States and other countries worldwide. All other trademarks
are the property of their respective owners.
Information in this document is subject to change without notice and does not represent a
commitment on the part of Digi International.
Digi provides this document “as is,” without warranty of any kind, either expressed or implied,
including, but not limited to, the implied warranties of, fitness or merchantability for a particular
purpose. Digi may make improvements and/or changes in this manual or in the product(s) and/or
the program(s) described in this manual at any time.
This product could include technical inaccuracies or typographical errors. Changes are made
periodically to the information herein; these changes may be incorporated in new editions of the
publication.
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Minnetonka, MN 55343 U.S.A.
United States: +1 877 912-3444
Other locations: +1 952 912-3444
Fax: +1 952 912-4960
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