MC9328MXSVF10 скачать даташит

MC9328MXSVF10 скачать даташит

Freescale Semiconductor

Data Sheet: Technical Data

MC9328MXS

Document Number: MC9328MXS

Rev. 3, 12/2006

MC9328MXS

Package Information

Plastic Package

Case 1304B-01

(MAPBGA–225)

Ordering Information

See Table 1 on page 3

1 Introduction

The i.MX Family of applications processors provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. The i.MX family specifically addresses the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities.

The MC9328MXS (i.MXS) processor features the advanced and power-efficient ARM920T™ core that operates at speeds up to 100 MHz. Integrated modules, which include a USB device and an LCD controller, support a suite of peripherals to enhance portable products. It is packaged in a 225-contact MAPBGA

package. Figure 1

shows the functional block diagram of the i.MXS processor.

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Signals and Connections . . . . . . . . . . . . . . . 4

3 Electrical Characteristics . . . . . . . . . . . . . . 16

4 Functional Description and Application

Information . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Pin-Out and Package Information . . . . . . . . 71

6 Product Documentation . . . . . . . . . . . . . . . . 73

Contact Information . . . . . . . . . . . . . . . Last Page

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

© Freescale Semiconductor, Inc., 2006. All rights reserved.

Introduction

2

Figure 1. i.MXS Functional Block Diagram

1.1

Features

To support a wide variety of applications, the processor offers a robust array of features, including the following:

• ARM920T™ Microprocessor Core

• AHB to IP Bus Interfaces (AIPIs)

• External Interface Module (EIM)

• SDRAM Controller (SDRAMC)

• DPLL Clock and Power Control Module

• Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)

• Serial Peripheral Interface (SPI)

• Two General-Purpose 32-bit Counters/Timers

• Watchdog Timer

• Real-Time Clock/Sampling Timer (RTC)

• LCD Controller (LCDC)

• Pulse-Width Modulation (PWM) Module

• Universal Serial Bus (USB) Device

• Direct Memory Access Controller (DMAC)

• Synchronous Serial Interface and an Inter-IC Sound (SSI/I

2

S) Module

• Inter-IC (I

2

C) Bus Module

• General-Purpose I/O (GPIO) Ports

• Bootstrap Mode

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Introduction

• Power Management Features

• Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O

• 225-contact MAPBGA Package

1.2

Target Applications

The i.MXS applications processor is designed to meet the needs of medical instrumentation, low-end

PDAs, point-of-sale terminals, security systems and other applications requiring a basic device based on

ARM technology with support for open operating systems. Like other members of the i.MX family, the i.MXS is designed for high performance and low-power to maximize battery life.

1.3

Ordering Information

Table 1

provides ordering information.

Table 1. i.MXS Ordering Information

Package Type

225-contact MAPBGA

Frequency

100 MHz

Temperature

0

O

C to 70

O

C

-40

O

C to 85

O

C

Solderball Type

Pb-free

Pb-free

Order Number

MC9328MXSVP10(R2)

MC9328MXSCVP10(R2)

1.4

Conventions

This document uses the following conventions:

• OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.

Logic level one

is a voltage that corresponds to Boolean true (1) state.

Logic level zero

is a voltage that corresponds to Boolean false (0) state.

• To set a bit or bits means to establish logic level one.

• To clear a bit or bits means to establish logic level zero.

• A signal is an electronic construct whose state conveys or changes in state convey information.

• A pin is an external physical connection. The same pin can be used to connect a number of signals.

Asserted

means that a discrete signal is in active logic state.

Active low signals change from logic level one to logic level zero.

Active high signals change from logic level zero to logic level one.

Negated

means that an asserted discrete signal changes logic state.

Active low signals change from logic level zero to logic level one.

Active high signals change from logic level one to logic level zero.

• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out.

• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

3

4

Signals and Connections

A[24:0]

D[31:0]

EB0

EB1

EB2

EB3

OE

CS [5:0]

2 Signals and Connections

Table 2

identifies and describes the i.MXS processor signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to.

Table 2. i.MXS Signal Descriptions

Signal Name

ECB

LBA

BCLK (burst clock)

RW

DTACK

BOOT [3:0]

SDBA [4:0]

SDIBA [3:0]

MA [11:10]

MA [9:0]

DQM [3:0]

CSD0

Function/Notes

External Bus/Chip-Select (EIM)

Address bus signals

Data bus signals

MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].

Byte Strobe—Active low external enable byte signal that controls D [23:16].

Byte Strobe—Active low external enable byte signal that controls D [15:8].

LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].

Memory Output Enable—Active low output enables external data bus.

Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the

Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.

Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence.

Active low signal sent by a flash device causing the external burst device to latch the starting burst address.

Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM.

DTACK signal—The external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed.

Bootstrap

System Boot Mode Select—The operational system boot mode of the i.MXS processor upon system reset is determined by the settings of these pins.

SDRAM Controller

SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles.

SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.

SDRAM address signals

SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on

SDRAM cycles.

SDRAM data enable

SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register.

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Signal Name

CSD1

RAS

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

RESET_SF

EXTAL16M

XTAL16M

EXTAL32K

XTAL32K

CLKO

RESET_IN

RESET_OUT

POR

TRST

TDO

TDI

TCK

TMS

DMA_REQ

BIG_ENDIAN

Signals and Connections

Table 2. i.MXS Signal Descriptions (Continued)

Function/Notes

SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as boot chip-select by properly configuring BOOT [3:0] input pins.

SDRAM Row Address Select signal

SDRAM Column Address Select signal

SDRAM Write Enable signal

SDRAM Clock Enable 0

SDRAM Clock Enable 1

SDRAM Clock

Not Used

Clocks and Resets

Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut down.

Crystal output

32 kHz crystal input

32 kHz crystal output

Clock Out signal selected from internal clock signals.

Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset.

Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.

Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event.

JTAG

Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

Serial Output for test instructions and data. Changes on the falling edge of TCK.

Serial Input for test instructions and data. Sampled on the rising edge of TCK.

Test Clock to synchronize test logic and control register access through the JTAG port.

Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of

TCK.

DMA

DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.

Big Endian—Input signal that determines the configuration of the external chip-select space. If it is driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven logic-low at reset, the external chip-select space will be configured to little endian. This input must not change state after power-on reset negates or during chip operation.

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

5

Signals and Connections

Table 2. i.MXS Signal Descriptions (Continued)

Signal Name Function/Notes

ETM

ETMTRACESYNC

ETMTRACECLK

ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.

ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.

ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode.

ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].

ETMTRACEPKT [7:0] are selected in ETM mode.

LD [15:0]

FLM/VSYNC

LP/HSYNC

LSCLK

ACD/OE

CONTRAST

SPL_SPR

PS

CLS

REV

SPI1_MOSI

SPI1_MISO

SPI1_SS

SPI1_SCLK

SPI1_SPI_RDY

TIN

TMR2OUT

USBD_VMO

USBD_VPO

USBD_VM

USBD_VP

LCD Controller

LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.

Frame Sync or Vsync—This signal also serves as the clock signal output for the gate driver (dedicated signal SPS for Sharp panel HR-TFT).

Line pulse or H sync

Shift clock

Alternate crystal direction/output enable.

This signal is used to control the LCD bias voltage as contrast control.

Program horizontal scan direction (Sharp panel dedicated signal).

Control signal output for source driver (Sharp panel dedicated signal).

Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal).

Signal for common electrode driving signal preparation (Sharp panel dedicated signal).

SPI 1

Master Out/Slave In

Slave In/Master Out

Slave Select (Selectable polarity)

Serial Clock

Serial Data Ready

General Purpose Timers

Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers simultaneously.

Timer 2 Output

USB Device

USB Minus Output

USB Plus Output

USB Minus Input

USB Plus Input

6

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

UART2_RXD

UART2_TXD

UART2_RTS

UART2_CTS

UART2_DSR

UART2_RI

UART2_DCD

UART2_DTR

Signal Name

USBD_SUSPND

USBD_RCV

USBD_ROE

USBD_AFE

SSI_TXDAT

SSI_RXDAT

SSI_TXCLK

SSI_RXCLK

SSI_TXFS

SSI_RXFS

I2C_SCL

I2C_SDA

PWMO

TRISTATE

PA[14:3]

Signals and Connections

Table 2. i.MXS Signal Descriptions (Continued)

Function/Notes

USB Suspend Output

USB Receive Data

USB OE

USB Analog Front End Enable

UARTs – IrDA/Auto-Bauding

Receive Data

Transmit Data

Request to Send

Clear to Send

Receive Data

Transmit Data

Request to Send

Clear to Send

Data Set Ready

Ring Indicator

Data Carrier Detect

Data Terminal Ready

Serial Audio Port – SSI (configurable to I

2

S protocol)

Transmit Data

Receive Data

Transmit Serial Clock

Receive Serial Clock

Transmit Frame Sync

Receive Frame Sync

I

2

C

I

2

C Clock

I

2

C Data

PWM

PWM Output

Test Function

Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input with a 1 k ohm resistor to ground. (TRI-STATE

®

is a registered trademark of National Semiconductor.)

General Purpose Input/Output

Dedicated GPIO

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

7

8

Signals and Connections

Signal Name

PB[13:8]

NVDD

NVSS

AVDD

QVDD

QVSS

Table 2. i.MXS Signal Descriptions (Continued)

Function/Notes

Dedicated GPIO

Digital Supply for the I/O pins

Digital Ground for the I/O pins

Digital Supply Pins

Supply Pins – Analog Modules

Supply for analog blocks

Internal Power Supply

Power supply pins for silicon internal circuitry

Ground pins for silicon internal circuitry

2.1

I/O Pads Power Supply and Signal Multiplexing Scheme

This section describes detailed information about both the power supply for each I/O pin and its function multiplexing scheme. The user can reference information provided in

Table 6 on page 17 to configure the

power supply scheme for each device in the system (memory and external peripherals). The function

multiplexing information also shown in Table 6 allows the user to select the function of each pin by

configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions.

Table 3. MC9328MXS Signal Multiplexing Scheme

Primary Alternate

I/O Supply

Voltage

NVDD1

225

BGA

Ball

D2

Signal

A24

Dir

O

Pull-

Up

Signal Dir

ETMTRAC

ESYNC

O

GPIO

Mux

PA0

Pull

-Up

AIN

69K Reser ved

BIN AOUT Default

A24

NVDD1

NVDD1

C1

D1

D31

A23

I/O

O

69K

ETMTRAC

ECLK

O PA31 69K A23

NVDD1

NVDD1

E3

E2

D30

A22

I/O

O

69K

ETMPIPE

STAT2

O PA30 69K A22

NVDD1

NVDD1

E4

E1

D29

A21

I/O

O

69K

ETMPIPE

STAT1

O PA29 69K A21

NVDD1

NVDD1

F3

F1

D28

A20

I/O

O

69K

ETMPIPE

STAT0

O PA28 69K A20

NVDD1

NVDD1

F4

F2

D27

A19

I/O

O

69K

ETMTRAC

EPKT3

O PA27 69K A19

NVDD1 G3 D26 I/O 69K

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

I/O Supply

Voltage

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

Signals and Connections

R3

N5

R4

R2

N4

M4

P4

M3

P2

N3

P3

M2

N2

P1

R1

L3

L2

M1

N1

K4

K2

L4

L1

J3

K1

J4

J2

H3

H1

H5

J1

225

BGA

Ball

G2

G4

G1

H4

H2

Table 3. MC9328MXS Signal Multiplexing Scheme (Continued)

D11

EB0

D10

A3

EB1

D9

EB2

D13

A5

D12

A4

D15

A7

D14

A6

D17

A9

D16

A8

D19

A11

D18

A10

D21

A13

D20

A12

D23

A15

D22

A14

Signal

A18

D25

A17

D24

A16

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

I/O

O

Primary

Dir

O

I/O

O

I/O

O

Pull-

Up

Alternate

Signal

ETMTRAC

EPKT2

Dir

O

GPIO

Mux

Pull

-Up

PA26 69K

69K

ETMTRAC

EPKT1

O PA25 69K

69K

ETMTRAC

EPKT0

O PA24 69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

69K

AIN BIN AOUT Default

A18

A17

A16

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

9

Signals and Connections

I/O Supply

Voltage

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

N10

R12

N11

P11

K10

M10

P10

P9

N12

P12

R13

R14

Table 3. MC9328MXS Signal Multiplexing Scheme (Continued)

Primary Alternate

Signal

CS4

A0

CS3

D6

CS2

SDCLK

CS1

CS0

D5

ECB

A2

EB3

D8

OE

A1

CS5

D7

225

BGA

Ball

K3

R8

M8

N8

M7

R7

N7

P7

P8

L9

R5

P6

L7

R6

P5

M5

N6

Dir

O

O

O

O

O

O

O

I/O

I/O

I

O

O

O

I/O

O

O

I/O

Pull-

Up

69K

69K

69K

69K

Signal

CSD1

CSD0

ETMTRAC

EPKT7

Dir

GPIO

Mux

Pull

-Up

PA23 69K

PA22 69K

PA21 69K

PA20 69K

AIN BIN

R9

R10

D4

LBA

I/O

O

69K

ETMTRAC

EPKT6

PA19 69K

R11

M9

D3

BCLK

I/O 69K

ETMTRAC

EPKT5

PA18 69K

L8

N9

D2

PA17

I/O 69K

ETMTRAC

EPKT4

PA17 69K Reser ved

D1

RW

MA11

MA10

D0

DQM3

DQM2

DQM1

DQM0

RAS

CAS

SDWE

I/O

O

O

O

O

O

O

I/O

O

O

O

69K

69K

AOUT

DTACK

Default

PA23

PA22

A0

CSD1

CSD0

ECB

LBA

BCLK

PA17

10

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

I/O Supply

Voltage

NVDD1

NVDD1

NVDD1

NVDD1

AVDD1

QVDD2

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

AVDD1

Signals and Connections

Table 3. MC9328MXS Signal Multiplexing Scheme (Continued)

Alternate

225

BGA

Ball

Signal

Primary

Dir

Pull-

Up

M12

K11

J14

J15

J13

H15

J12

K12

J11

H14

H13

G14

H12

G13

J10

G15

N13

P13

P15

SDCKE0

SDCKE1

RESET_S

F

O

O

O

P14

R15

M13

N15

CLKO

AVDD1 Static

QVDD2

TRST

N14 TRISTATE

1

O

Static

I

I

M15

L14

L15

K15

M14

K14

L12

K13

EXTAL16

M

I

XTAL16M O

EXTAL32

K

I

XTAL32K O

RESET_I

N

2

I

RESET_O

UT

O

I

POR

2

BIG_ENDI

AN

3

I

I

BOOT3

3

BOOT2

3

BOOT1

3

I

I

BOOT0

3

I

TDO

4

TMS

O

TCK

TDI

I2C_SCL O

I2C_SDA I/O

I

I

I

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

I

I

I

I

I

I

69K

69K

69K

69K

69K

Signal Dir

GPIO

Mux

Pull

-Up

PA16 69K

PA15 69K

PA14 69K

PA13 69K

PA12 69K

PA11 69K

PA10 69K

PA9 69K

AIN BIN AOUT Default

PA16

PA15

PA14

PA13

PA12

PA11

PA10

PA9

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

11

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

Signals and Connections

I/O Supply

Voltage

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

NVDD2

B13

A13

D12

B12

C11

B15

B14

A15

A14

D13

E12

C13

C12

F13

F12

D15

C14

Table 3. MC9328MXS Signal Multiplexing Scheme (Continued)

225

BGA

Ball

Signal

Primary

Dir

F15

G12

F14

H11

E14

E15

G11

Reserved

Reserved

Reserved

Reserved

Reserved

I

I

I

I

I

Reserved O

PWMO O

E13 TIN I

D14 TMR2OUT O

Pull-

Up

Alternate

Signal Dir

GPIO

Mux

Pull

-Up

PA8

PA7

PA6

PA5

PA4

PA3

PA2

69K

69K

69K

PA1 69K

PD31 69K

69K

69K

69K

69K

AIN BIN AOUT

Reser ved

Reserved

D11

E11

C10

B11

LD15

LD14

LD13

LD12

LD11

LD10

LD9

LD8

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

FLM/VSY

NC

LP/HSYN

C

ACD/OE

CONTRA

ST

O

SPL_SPR O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

PD30 69K

PD29 69K

PD28 69K

PD27 69K

PD26 69K

PD25 69K

PD24 69K

PD23 69K

PD22 69K

PD21 69K

PD20 69K

PD19 69K

PD18 69K

PD17 69K

PD16 69K

PD15 69K

PD14 69K

PD13 69K

PD12 69K

PD11 69K

A12

F10

A11

PS

CLS

REV

O

O

O

UART2_D

SR

O

UART2_RI O

O UART2_D

CD

UART2_D

TR

I

PD10 69K Reser ved

PD9 69K

PD8

PD7

69K Reser ved

69K Reser ved

Reserved

Default

PD13

PD12

PD11

PD10

PD9

PD8

PD7

PA8

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PD31

PD22

PD21

PD20

PD19

PD18

PD17

PD16

PD15

PD14

PD30

PD29

PD28

PD27

PD26

PD25

PD24

PD23

12

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

I/O Supply

Voltage

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD4

NVDD2

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD3

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

Signals and Connections

Table 3. MC9328MXS Signal Multiplexing Scheme (Continued)

225

BGA

Ball

B10

D10

E10

B9

A10

A9

E8

B8

C9

E9

A8

C8

F9

B7

F8

A7

C7

D8

E7

F7

B6

C6

A6

D6

A5

Signal

Primary

Dir

SSI_TXFS I/O

SSI_TXDA

T

O

I SSI_RXD

AT

SSI_RXCL

K

I

SSI_RXFS I

UART2_R

XD

I

O UART2_T

XD

UART2_R

TS

I

UART2_C

TS

USBD_VM

O

O

O

USBD_VP

O

O

USBD_VM I

LSCLK

SPI1_MO

SI

SPI1_MIS

O

O

I/O

I/O

SPI1_SS I/O

SPI1_SCL

K

I/O

I/O SPI1_SPI

_RDY

UART1_R

XD

I

O UART1_T

XD

UART1_R

TS

UART1_C

TS

SSI_TXCL

K

I

O

I/O

USBD_VP I

USBD_SU

SPND

O

Pull-

Up

Alternate

Signal Dir

GPIO

Mux

Pull

-Up

PD6 69K

PC17 69K

PC16 69K

PC15 69K

PC14 69K

PC13 69K

PC12 69K

PC11 69K

PC10 69K

PC9

PC8

PC7

PC6

PC5

PC4

69K

69K

69K

69K

69K

69K

PC3 69K

PB31 69K

PB30 69K

PB29 69K

PB28 69K

PB27 69K

PB26 69K

PB25 69K

PB24 69K

PB23 69K

AIN BIN AOUT

DMA_REQ

Default

PD6

PC17

PC16

PC15

PC14

PC13

PC12

PC11

PC10

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PB31

PB30

PB29

PB28

PB27

PB26

PB25

PB24

PB23

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

13

Signals and Connections

I/O Supply

Voltage

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD4

NVDD1

NVDD1

QVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

NVDD1

Table 3. MC9328MXS Signal Multiplexing Scheme (Continued)

G5

K6

J5

H7

J8

E6

F5

J6

D5

G6

E5

H6

C5

D3

C2

L5

H8

K7

K5

J7

L5

G8

Reserved I/O

Reserved I/O

Reserved I/O

NVDD1 Static

NVSS Static

NVDD1 Static

NVSS Static

QVDD1 Static

QVSS Static

NVDD Static

NVSS Static

NVDD1 Static

NVSS Static

NVDD1 Static

NVSS Static

NVDD1 Static

NVSS Static

NVDD1 Static

NVSS Static

NVDD1 Static

NVSS Static

QVSS Static

A2

C3

A1

B2

B1

A3

C4

D4

B3

225

BGA

Ball

B5

A4

B4

Signal

Primary

Dir

USBD_RC

V

USBD_RO

E

USBD_AF

E

I/O

O

O

PB19

PB18

PB17

PB16

PB15

PB14

Reserved I/O

Reserved O

I

I

Reserved I/O

I/O

I/O

O

I

Pull-

Up

Alternate

Signal

Reserved

Reserved

Reserved

Dir

GPIO

Mux

Pull

-Up

PB22 69K

PB21

PB20

69K

69K

Reserved

Reserved

Reserved

69K

69K

PB13 69K

PB12 69K

69K

69K

69K

69K

PB11 69K

(pull down)

PB10 69K

PB9

PB8

69K

69K

AIN BIN AOUT Default

PB10

PB9

PB8

PB22

PB21

PB20

PB19

PB18

PB17

PB16

PB15

PB14

PB13

PB12

PB11

14

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Signals and Connections

Table 3. MC9328MXS Signal Multiplexing Scheme (Continued)

Primary Alternate GPIO

I/O Supply

Voltage

225

BGA

Ball

Signal Dir

Pull-

Up

Signal Dir

NVDD2

QVDD3

NVDD2

QVDD4

NVDD3

NVDD4

NVDD1

NVDD1

NVDD1

NVDD1

G7

F6

L6

M6

L13

D9

J9

K9

K8

L10

L11

M11

H10

G9

F11

G10

C15

H9

D7

NVDD2 Static

NVSS Static

QVDD3 Static

QVSS Static

NVDD2 Static

NVSS Static

QVDD4 Static

QVSS Static

NVDD3 Static

NVSS Static

NVSS Static

NVDD4 Static

NVDD1 Static

NVDD1 Static

NVDD1 Static

NVDD1 Static

NVSS Static

NVSS Static

NVSS Static

2

3

1

4

Pull down this input with 1K

Ω resistor to GND.

External circuit required to drive this input.

Tie this input high (to AVDD) or pull down with 1K

Ω resistor to GND.

Pull up this output with a resistor to NVDD2.

Mux

Pull

-Up

AIN BIN AOUT Default

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

15

Electrical Characteristics

3 Electrical Characteristics

This section contains the electrical specifications and timing diagrams for the i.MXS processor.

3.1

Maximum Ratings

Table 4

provides information on maximum ratings which are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits listed in Recommended Operating

Range Table 5 on page 17

or the DC Characteristics table.

Table 4. Maximum Ratings

Symbol Rating Minimum Maximum Unit

NV

DD

QV

DD

AV

DD

DC I/O Supply Voltage

DC Internal (core = 100 MHz) Supply Voltage

DC Analog Supply Voltage

-0.3

-0.3

-0.3

3.3

1.9

3.3

V

V

V

BTRFV

DD

VESD_HBM

VESD_MM

DC Bluetooth Supply Voltage

ESD immunity with HBM (human body model)

ESD immunity with MM (machine model)

-0.3

3.3

2000

100

V

V

V

ILatchup

Test

Latch-up immunity

Storage temperature

-55

200

150 mA

°C

Pmax Power Consumption

800

1

1300

2 mW

1

2

A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM

® core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.

A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the

ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS application at 100MHz, and where the whole image is running out of SDRAM. QVDD at 1.9V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.

3.2

Recommended Operating Range

Table 5

provides the recommended operating ranges for the supply voltages and temperatures. The i.MXS processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of

VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system.

Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins.

For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4 .

16

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Electrical Characteristics

Table 5. Recommended Operating Range

Symbol Rating

T

T

A

A

Operating temperature range

MC9328MXSVP10

Operating temperature range

MC9328MXSCVP10

NVDD I/O supply voltage (if using SPI, LCD, and USBd which are only 3 V interfaces)

NVDD I/O supply voltage (if not using the peripherals listed above)

QVDD Internal supply voltage (Core = 100 MHz)

AVDD Analog supply voltage

Minimum Maximum

0 70

-40

2.70

1.70

1.70

1.70

85

3.30

3.30

1.90

3.30

Unit

°C

°C

V

V

V

V

3.3

Power Sequence Requirements

For required power-up and power-down sequencing, please refer to the “Power-Up Sequence” section of application note AN2537 on the i.MX applications processor website.

3.4

DC Electrical Characteristics

Table 6

contains both maximum and minimum DC characteristics of the i.MXS processor.

Table 6. Maximum and Minimum DC Characteristics

Number or

Symbol

Iop

Sidd

1

Sidd

2

Sidd

3

Sidd

4

Parameter

Full running operating current at 1.8V for QVDD, 3.3V for

NVDD/AVDD (Core = 96 MHz, System = 96 MHz, driving

TFT display panel, and OS with MMU enabled memory system is running on external SDRAM).

Standby current

(Core = 100 MHz, QVDD = 1.8V, temp = 25

°

C)

Standby current

(Core = 100 MHz, QVDD = 1.8V, temp = 55

°

C)

Standby current

(Core = 100 MHz, QVDD = 1.9V, temp = 25

°

C)

Standby current

(Core = 100 MHz, QVDD = 1.9V, temp = 55

°

C)

Input high voltage V

IH

V

IL

V

OH

V

OL

I

IL

Input low voltage

Output high voltage (I

OH

= 2.0 mA)

Output low voltage (I

OL

= -2.5 mA)

Input low leakage current

(V

IN

= GND, no pull-up or pull-down)

Min

0.7V

DD

0.7V

DD

Typical

QVDD at

1.8V = 120mA;

NVDD+AVDD at

3.0V = 30mA

25

45

35

60

Max

Vdd+0.2

0.4

Vdd

0.4

±1

Unit

mA

μA

μA

μA

μA

V

V

V

V

μA

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

17

Functional Description and Application Information

Table 6. Maximum and Minimum DC Characteristics (Continued)

Number or

Symbol

I

IH

I

I

I

OH

OL

OZ

Parameter

Input high leakage current

(V

IN

= V

DD

, no pull-up or pull-down)

Output high current

(V

OH

= 0.8V

DD

, V

DD

= 1.8V)

Output low current

(V

OL

= 0.4V, V

DD

= 1.8V)

Output leakage current

(V out

= V

DD

, output is high impedance)

Input capacitance C i

C o

Output capacitance

Min

4.0

-4.0

Typical

±5

5

5

Max

±1

Unit

μA mA mA

μA pF pF

3.5

AC Electrical Characteristics

The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 100 MHz) with an operating supply voltage from V

DD min timing is measured at 30 pF loading.

to V

DD max

under an operating temperature from T

L

to T

H

. All

Table 7. Tristate Signal Timing

Pin Parameter

TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z

Minimum Maximum Unit

– 20.8

ns

Table 8. 32k/16M Oscillator Signal Timing

Parameter Minimum

EXTAL32k input jitter (peak to peak) –

EXTAL32k startup time

EXTAL16M input jitter (peak to peak)

1

EXTAL16M startup time

1

800

TBD

1

The 16 MHz oscillator is not recommended for use in new designs.

RMS

5

TBD

Maximum

20

TBD

Unit

ns ms

4 Functional Description and Application Information

This section provides the electrical information including and timing diagrams for the individual modules of the i.MXS.

18

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

4.1

Embedded Trace Macrocell

All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the

ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following:

• 32-bit data field

• 7-bit address field

• A read/write bit

The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit.

A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.

The timing diagram for the ETM9 is shown in Figure 2 . See Table 9

for the ETM9 timing parameters used

in Figure 2 .

2a

1

3a

2b

TRACECLK

3b

TRACECLK

(Half-Rate Clocking Mode)

Output Trace Port Valid Data

4a

Figure 2. Trace Port Timing Diagram

Valid Data

4b

3b

4a

4b

1

2a

2b

3a

Ref No.

Table 9. Trace Port Timing Diagram Parameter Table

Parameter

CLK frequency

Clock high time

Clock low time

Clock rise time

Clock fall time

Output hold time

Output setup time

1.8 ± 0.1 V

Minimum

0

1.3

3

2.28

3.42

Maximum

3

85

4

3.0 ± 0.3 V

Minimum

2

3

2

0

2

Maximum

3

100

3

Unit

MHz ns ns ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

19

Functional Description and Application Information

4.2

DPLL Timing Specifications

Parameters of the DPLL are given in Table 10

. In this table, T ref pre-divider and T dck

is the output double clock period.

is a reference clock period after the

Table 10. DPLL Specifications

Parameter Test Conditions

DPLL input clock freq range

Pre-divider output clock freq range

Vcc = 1.8V

Vcc = 1.8V

DPLL output clock freq range Vcc = 1.8V

Pre-divider factor (PD) –

Total multiplication factor (MF) Includes both integer and fractional parts

MF integer part –

MF numerator

MF denominator

Pre-multiplier lock-in time

Should be less than the denominator

Freq lock-in time after full reset

Freq lock-in time after partial reset

Phase lock-in time after full reset

Phase lock-in time after partial reset

Freq jitter (p-p)

FOL mode for non-integer MF

(does not include pre-multi lock-in time)

FOL mode for non-integer MF (does not include pre-multi lock-in time)

FPL mode and integer MF (does not include pre-multi lock-in time)

FPL mode and integer MF (does not include pre-multi lock-in time)

Phase jitter (p-p)

Power supply voltage

Power dissipation

Integer MF, FPL mode, Vcc=1.8V

FOL mode, integer MF, f dck

= 100 MHz, Vcc = 1.8V

Minimum Typical Maximum Unit

5 – 100 MHz

5

80

1

5

5

0

1

250

220

300

270

1.7

280

(56

μs)

250

(50

μs)

350

(70

μs)

320

(64

μs)

0.005

(0.01%)

1.0

(10%)

30

220

16

15

15

1022

1023

312.5

300

270

400

370

0.01

1.5

2.5

4

MHz

T ref

T ref

T ref

T ref

2•T dck ns

V mW

MHz

μ sec

4.3

Reset Module

The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and

Figure 4

.

NOTE

Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing.

20

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

POR

RESET_POR

RESET_DRAM

HRESET

RESET_OUT

CLK32

HCLK

90% AVDD

1

10% AVDD

2

Exact 300ms

3

7 cycles @ CLK32

4

14 cycles @ CLK32

Figure 3. Timing Relationship with POR

5

RESET_IN

HRESET

RESET_OUT

CLK32

HCLK

6

14 cycles @ CLK32

4

Figure 4. Timing Relationship with RESET_IN

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

21

Functional Description and Application Information

Table 11. Reset Module Timing Parameter Table

Ref

No.

Parameter

1.8 ± 0.1 V 3.0 ± 0.3 V

Unit

Min Max Min Max

1 Width of input POWER_ON_RESET note

1

300

– note

1

300

– –

2 Width of internal POWER_ON_RESET

(CLK32 at 32 kHz)

3 7K to 32K-cycle stretcher for SDRAM reset

300 300 ms

4 14K to 32K-cycle stretcher for internal system reset

HRESERT and output reset at pin RESET_OUT

5 Width of external hard-reset RESET_IN

7

14

7

14

7

14

7

14

Cycles of

CLK32

Cycles of

CLK32

4 – 4 – Cycles of

CLK32

6 4K to 32K-cycle qualifier 4 4 4 4 Cycles of

CLK32

1

POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals.

Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.

If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process.

4.4

External Interface Module

The External Interface Module (EIM) handles the interface to devices external to the i.MXS processor, including the generation of chip-selects for external peripherals and memory. The timing diagram for the

EIM is shown in

Figure 5

, and

Table 12

defines the parameters of signals.

22

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

(HCLK) Bus Clock

Address

Chip-select

1a

2a

1b

2b

3a 3b

Read (Write)

OE (rising edge)

4a 4b

5a

4c

5b

4d

OE (falling edge)

EB (rising edge)

5c 5d

EB (falling edge)

6a 6b

LBA (negated falling edge)

6a 6c

LBA (negated rising edge)

7a 7b

BCLK (burst clock) - rising edge

BCLK (burst clock) - falling edge

Read Data

Write Data (negated falling)

9a

7c

8a

7d

8b

9b

9a 9c

Write Data (negated rising)

DTACK_B

10a 10a

Figure 5. EIM Bus Timing Diagram

1a

1b

2a

2b

3a

3b

Ref No.

Table 12. EIM Bus Timing Parameter Table

Parameter

Clock fall to address valid

Clock fall to address invalid

Clock fall to chip-select valid

Clock fall to chip-select invalid

Clock fall to Read (Write) Valid

Clock fall to Read (Write) Invalid

1.8 ± 0.1 V 3.0 ± 0.3 V

Min Typical Max Min Typical Max

2.48

1.55

2.69

1.55

1.35

1.86

3.31

2.48

3.31

2.48

2.79

2.59

9.11

5.69

7.87

6.31

6.52

6.11

2.4

1.5

2.6

1.5

1.3

1.8

3.2

2.4

3.2

2.4

2.7

2.5

8.8

5.5

7.6

6.1

6.3

5.9

Unit

ns ns ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

23

Functional Description and Application Information

Table 12. EIM Bus Timing Parameter Table (Continued)

1.8 ± 0.1 V 3.0 ± 0.3 V

Ref No.

Parameter

Min Typical Max Min Typical Max

4a

4b

4c

4d

5a

5b

5c

5d

6a

6b

6c

7a

Clock

1

rise to Output Enable Valid

Clock

1

rise to Output Enable Invalid

Clock

1

fall to Output Enable Valid

Clock

1

fall to Output Enable Invalid

Clock

1

rise to Enable Bytes Valid

Clock

1

rise to Enable Bytes Invalid

Clock

1

fall to Enable Bytes Valid

Clock

1

fall to Enable Bytes Invalid

Clock

1

fall to Load Burst Address Valid

Clock

1

fall to Load Burst Address Invalid

Clock

1

rise to Load Burst Address Invalid

Clock

1

rise to Burst Clock rise

Clock

1 rise to Burst Clock fall

Clock

1

fall to Burst Clock rise

Clock

1

fall to Burst Clock fall

2.32

2.11

2.38

2.17

1.91

1.81

1.97

1.76

2.07

1.97

1.91

1.61

2.62

2.52

2.69

2.59

2.52

2.42

2.59

2.48

2.79

2.79

2.62

2.62

6.85

6.55

7.04

6.73

5.54

5.24

5.69

5.38

6.73

6.83

6.45

5.64

2.3

2.1

2.3

2.1

1.9

1.8

1.9

1.7

2.0

1.9

1.9

1.6

7b

7c

7d

8a

1.61

1.55

1.55

5.54

2.62

2.48

2.59

5.84

1.6

5.59

1.5

5.80

1.5

– 5.5

8b

9a

9b

9c

Read Data setup time

Read Data hold time

Clock

1

Clock

1

Clock

1

rise to Write Data Valid

fall to Write Data Invalid

rise to Write Data Invalid

0

1.81

1.45

1.63

2.72

2.48

6.85

1.8

5.69

10a DTACK setup time 2.52

– –

1

Clock refers to the system clock signal, HCLK, generated from the System DPLL

0

1.4

1.62

2.5

2.6

2.5

2.6

2.5

2.5

2.4

2.5

2.4

2.7

2.7

2.6

2.6

2.6

2.4

2.5

2.7

2.4

6.5

6.6

6.4

5.6

5.5

5.2

5.5

5.2

6.8

6.5

6.8

6.5

6.8

5.5

5.8

5.4

5.6

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

4.4.1

DTACK Signal Description

The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal function when the external DTACK signal is used for data acknowledgement.

4.4.2

DTACK Signal Timing

Figure 6

through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units

of measure for this figure are found in the associated tables.

24

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

4.4.2.1

WAIT Read Cycle without DMA

Address

2

CS5

EB

1 programmable min 0ns

9

8

3

5

OE

4

WAIT

7 6

DATABUS

(input to i.MXS)

10 11

Figure 6. WAIT Read Cycle without DMA

Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.0 ± 0.3 V

Number Characteristic Unit

Minimum Maximum

3

4

1

2

OE and EB assertion time

CS5 pulse width

OE negated to address inactive

Wait asserted after OE asserted

See note 2

3T

56.81

57.28

1020T

5

6

7

8

Wait asserted to OE negated

Data hold timing after OE negated

Data ready after wait asserted

OE negated to CS negated

OE negated after EB negated

2T+1.57

T-1.49

0

1.5T-0.68

3T+7.33

T

1.5T-0.06

9

10

Become low after CS5 asserted

0.06

0

0.18

1019T ns ns

11

Wait pulse width

1T 1020T ns

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when

EBC bit in CS5L register is clear.

3. Address becomes valid and CS asserts at the start of read access cycle.

4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. ns ns ns ns ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

25

Functional Description and Application Information

4.4.2.2

WAIT Read Cycle DMA Enabled

Address

2

CS5

EB

1 programmable min 0ns

10

4

9

3

6

OE

RW

(logic high)

WAIT

5

7

11

12

8

S

DATABUS

Figure 7. DTACK WAIT Read Cycle DMA Enabled

Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.0 ± 0.3 V

Number Characteristic Unit

7

8

5

6

3

4

1

2

9

10

11

OE and EB assertion time

CS pulse width

OE negated before CS5 is negated

Address inactived before CS negated

Wait asserted after CS5 asserted

Wait asserted to OE negated

Data hold timing after OE negated

Data ready after wait is asserted

CS deactive to next CS active

OE negate after EB negate

Wait becomes low after CS5 asserted

Minimum

See note 2

3T

1.5T-0.68

2T+1.57

T-1.49

T

0.06

0

Maximum

1.5T-0.06

0.05

1020T

3T+7.33

T

0.18

1019T ns ns ns ns ns ns ns ns ns ns ns

26

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)

3.0 ± 0.3 V

Number Characteristic Unit

Minimum Maximum

12 Wait pulse width 1T 1020T ns

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when

EBC bit in CS5L register is clear.

3. Address becomes valid and CS asserts at the start of read access cycle.

4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.

4.4.2.3

WAIT Write Cycle without DMA

5

Address

CS5

1

2

EB programmable min 0ns programmable min 0ns

3

10

4

7

RW

OE

(logic high)

WAIT

DATABUS from i.MXS

9

11

6

12

8

Figure 8. WAIT Write Cycle without DMA

Number

Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.0 ± 0.3 V

Characteristic

3

4

1

2

5

6

CS5 assertion time

EB assertion time

CS5 pulse width

RW negated before CS5 is negated

RW negated to Address inactive

Wait asserted after CS5 asserted

Minimum

See note 2

See note 2

3T

2.5T-3.63

64.22

Maximum

2.5T-1.16

1020T

Unit

ns ns ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

27

Functional Description and Application Information

Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)

3.0 ± 0.3 V

Number Characteristic Unit

Minimum Maximum

9

10

7

8

Wait asserted to RW negated

Data hold timing after RW negated

Data ready after CS5 is asserted

EB negated after CS5 is negated

T+2.66

2T+0.03

0.5T

2T+7.96

T

0.5T+0.5

11

12

Wait becomes low after CS5 asserted

Wait pulse width

0

1T

1019T

1020T

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.

3. Address becomes valid and RW asserts at the start of write access cycle.

4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. ns ns ns ns ns ns

4.4.2.4

WAIT Write Cycle DMA Enabled

Address

1

CS5

2

EB

RW

OE (logic high)

WAIT

S

DATABUS programmable min 0ns programmable min 0ns

3

6

7

4

9

12

13

Figure 9. WAIT Write Cycle DMA Enabled

8

5

11

10

28

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz

3.0 ± 0.3 V

Number Characteristic Unit

Minimum Maximum

7

8

5

6

3

4

1

2

CS5 assertion time

EB assertion time

CS5 pulse width

RW negated before CS5 is negated

Address inactived after CS negated

Wait asserted after CS5 asserted

Wait asserted to RW negated

Data hold timing after RW negated

See note 2

See note 2

3T

2.5T-3.63

T+2.66

2T+0.03

2.5T-1.16

0.09

1020T

2T+7.96

9

10

Data ready after CS5 is asserted

CS deactive to next CS active

T

T

– ns ns

11

12

EB negate after CS negate 0.5T

0

0.5T+0.5

1019T

13

Wait becomes low after CS5 asserted

Wait pulse width 1T 1020T

Note:

1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)

2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.

3. Address becomes valid and RW asserts at the start of write access cycle.

4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. ns ns ns ns ns ns ns ns ns ns

4.4.3

EIM External Bus Timing

The External Interface Module (EIM) is the interface to devices external to the i.MXS

, including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in

Figure 5 , and Table 12 defines the parameters of signals.

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

29

Functional Description and Application Information

hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready

BCLK (burst clock)

ADDR

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Seq/Nonseq

Read

V1

Last Valid Data

Last Valid Address

Read

V1

DATA

V1

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 10. WSC = 1, A.HALF/E.HALF

V1

30

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[0] htrans hwrite haddr hready hwdata weim_hrdata weim_hready

BCLK (burst clock)

ADDR

CS0

R/W

LBA

OE

EB

Nonseq

Write

V1

Last Valid Data

Last Valid Address

Write Data (V1)

Last Valid Data

Write

V1

Unknown

DATA

Last Valid Data Write Data (V1)

Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

31

Functional Description and Application Information

hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready

BCLK (burst clock)

ADDR

CS0

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Nonseq

Read

V1

Last Valid Data

Last Valid Addr Address V1

Read

V1 Word

Address V1 + 2

DATA

1/2 Half Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF

2/2 Half Word

32

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[0] htrans hwrite haddr

Nonseq

Write

V1 hready hwdata Last Valid Data weim_hrdata weim_hready

BCLK (burst clock)

ADDR

CS0

R/W

LBA

OE

EB

Last Valid Addr

Write Data (V1 Word)

Last Valid Data

Address V1

Write

Address V1 + 2

DATA 1/2 Half Word

Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF

2/2 Half Word

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

33

Functional Description and Application Information

hclk hsel_weim_cs[3] htrans

Nonseq hwrite

Read haddr

V1 hready weim_hrdata

Last Valid Data weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS[3]

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Address V1

Read

Address V1 + 2

V1 Word

DATA

1/2 Half Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF

2/2 Half Word

34

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[3] htrans Nonseq hwrite

Write haddr

V1 hready hwdata Last Valid

Data weim_hrdata weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS3

R/W

LBA

OE

EB

Write Data (V1 Word)

Last Valid Data

Address V1

Write

Address V1 + 2

DATA

Last Valid Data 1/2 Half Word 2/2 Half Word

Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

35

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq

Read hwrite haddr

V1 hready weim_hrdata

Last Valid Data weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Address V1

Read

Address V1 + 2

V1 Word weim_data_in

1/2 Half Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF

2/2 Half Word

36

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq hwrite haddr

Write

V1 hready hwdata

Last Valid

Data weim_hrdata weim_hready

BCLK (burst clock)

ADDR Last Valid Addr

CS2

R/W

LBA

OE

EB

Write Data (V1 Word)

Last Valid Data

Address V1

Write

Address V1 + 2

DATA Last Valid Data 1/2 Half Word

Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF

2/2 Half Word

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

37

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq hwrite haddr

Read

V1 hready weim_hrdata Last Valid Data weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Address V1

Read

Address V1 + 2

DATA

1/2 Half Word 2/2 Half Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF

V1 Word

38

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

hclk hsel_weim_cs[2] htrans

Nonseq hwrite haddr

Read

V1 hready weim_hrdata

Last Valid Data weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Address V1

Read

Functional Description and Application Information

Address V1 + 2

V1 Word

DATA

1/2 Half Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF

2/2 Half Word

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

39

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq hwrite haddr

Write

V1 hready hwdata

Last Valid

Data weim_hrdata weim_hready

BCLK (burst clock)

ADDR Last Valid Addr

CS2

R/W

LBA

OE

EB

Address V1

Write Data (V1 Word)

Last Valid Data

Write

Address V1 + 2

Unknown

DATA

Last Valid Data 1/2 Half Word 2/2 Half Word

Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF

40

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans Nonseq

Write hwrite haddr

V1 hready hwdata

Last Valid

Data weim_hrdata weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EB

Write Data (V1 Word)

Last Valid Data

Address V1

Write

Address V1 + 2

DATA

Last Valid Data 1/2 Half Word 2/2 Half Word

Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF

Unknown

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

41

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq

Read hwrite haddr V1 hready hwdata weim_hrdata weim_hready

Last Valid Data

Last Valid Data

Nonseq

Write

V8

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Read

Address V1

Write Data

Read Data

Address V8

Write

DATA Read Data

DATA

Last Valid Data Write Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF

42

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Read hclk hsel_weim_cs[2] htrans

Nonseq

Read hwrite haddr

V1 hready hwdata weim_hrdata

Last Valid Data

Last Valid Data

Nonseq

Write

V8

Idle weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Read

Address V1

Functional Description and Application Information

Write

Write Data

Read Data

Address V8

Write

DATA Read Data

DATA

Last Valid Data Write Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

43

Functional Description and Application Information

hclk hsel_weim_cs[4] htrans

Nonseq hwrite haddr

Write

V1 hready hwdata

Last Valid

Data weim_hrdata weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS

R/W

LBA

OE

EB

Address V1

Write Data (Word)

Last Valid Data

Write

Address V1 + 2

DATA

Last Valid Data Write Data (1/2 Half Word) Write Data (2/2 Half Word)

Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF

44

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

hclk hsel_weim_cs[4] htrans Nonseq

Read hwrite haddr

V1 hready hwdata weim_hrdata weim_hready

Last Valid Data

Last Valid Data

BCLK (burst clock)

ADDR Last Valid Addr

CS4

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Read

Address V1

Nonseq

Write

V8

Functional Description and Application Information

Write Data

Read Data

Address V8

Write

DATA

Read Data

DATA Last Valid Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF

Write Data

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

45

Functional Description and Application Information

hclk hsel_weim_cs[4] htrans hwrite haddr

Nonseq

Read

V1 hready weim_hrdata weim_hready

Last Valid Data

BCLK (burst clock)

ADDR

Last Valid

CS4

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Idle Seq

Read

V2

Read Data (V1)

Address V1

Read

CNC

Read Data (V2)

Address V2

DATA

Read Data

(V1)

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF

Read Data

(V2)

46

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[4] htrans

Nonseq hwrite haddr

Read

V1 hready hwdata weim_hrdata

Last Valid Data

Last Valid Data

Idle Nonseq

Write

V8 weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr Address V1

CS4

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Read

CNC

Write Data

Read Data

Address V8

Write

DATA

Read Data

DATA

Last Valid Data Write Data

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

47

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq hwrite

Read haddr

V1 hready weim_hrdata weim_hready

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Address V1

Nonse

Read

V5

Read

Address V5

Idle

ECB

DATA

V1 Word V2 Word V5 Word V6 Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF

48

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq hwrite

Read haddr

V1 hready weim_hrdata weim_hready

Last Valid Data

BCLK (burst clock)

ADDR

Last Valid Addr

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Seq

Read

V2

V1 Word

Seq

Read

V3

V2 Word

Address V1

Read

Seq

Read

V4

V3 Word

Idle

V4 Word

ECB

DATA V1 Word V2 Word V3 Word

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD

V4 Word

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

49

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans

Nonseq hwrite haddr

Read

V1 hready weim_hrdata

Last Valid Data weim_hready

BCLK (burst clock)

ADDR

Last Valid

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Address V1

Seq

Read

V2

V1 Word

Read

Address V2

Idle

V2 Word

ECB

DATA

V1 1/2 V1 2/2 V2 1/2

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF

V2 2/2

50

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans hwrite

Non seq

Read haddr

V1 hready weim_hrdata weim_hready

BCLK (burst clock)

ADDR

Last

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Last Valid Data

Address V1

Read

Seq

Read

V2

V1 Word

Idle

V2 Word

ECB

DATA

V1 1/2 V1 2/2 V2 1/2 V2 2/2

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

51

Functional Description and Application Information

hclk hsel_weim_cs[2] htrans hwrite

Non seq

Read haddr

V1 hready weim_hrdata weim_hready

BCLK (burst clock)

ADDR

Last

CS2

R/W

LBA

OE

EBx

1

(EBC

2

=0)

EBx

1

(EBC

2

=1)

Last Valid Data

Address V1

Read

Seq

Read

V2

V1 Word

Idle

V2 Word

ECB

DATA

V1 1/2 V1 2/2 V2 1/2 V2 2/2

Note 1: x = 0, 1, 2 or 3

Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register

Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF

52

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

4.4.4

Non-TFT Panel Timing

T1

VSYN

T1

T2

T3

XMAX

T4 T2

HSYN

SCLK

Ts

LD[15:0]

Figure 33. Non-TFT Panel Timing

Table 17. Non TFT Panel Timing Diagram

Symbol Parameter

Allowed Register

Minimum Value

1, 2

Actual Value Unit

T1 HSYN to VSYN delay

3

0 HWAIT2+2

Tpix

4

T2

T3

HSYN pulse width

VSYN to SCLK

0

HWIDTH+1

0

≤ T3 ≤ Ts

5

Tpix

T4 SCLK to HSYN 0 HWAIT1+1 Tpix

2

3

1

4

5

Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.

Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.

VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all these 3 signals are active high.

Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).

Ts is the shift clock period. Ts = Tpix * (panel data bus width).

4.5

SPI Timing Diagrams

To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI1 Sample Period Control Register (PERIODREG1) can also be programmed to a fixed data transfer rate. When the SPI module is configured as a slave, the user can configure the SPI1

Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers,

as well as to increment the data FIFO. Figure 34 through Figure 38

show the timing relationship of the master SPI using different triggering mechanisms.

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

53

Functional Description and Application Information

2

SS

1

SPIRDY

3

4

5

SCLK, MOSI, MISO

Figure 34. Master SPI Timing Diagram Using SPI_RDY Edge Trigger

SS

SPIRDY

SCLK, MOSI, MISO

Figure 35. Master SPI Timing Diagram Using SPI_RDY Level Trigger

SS (output)

SCLK, MOSI, MISO

Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger

SS (input)

SCLK, MOSI, MISO

Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT

SS (input)

6

7

SCLK, MOSI, MISO

Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge

54

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

Table 18. Timing Parameter Table for

Figure 34

through

Figure 38

3.0 ± 0.3 V

Ref No.

Parameter

Minimum Maximum

1

2

3

4

SPI_RDY to SS output low

SS output low to first SCLK edge

Last SCLK edge to SS output high

SS output high to SPI_RDY low

2T

1

3 • Tsclk

2

2 • Tsclk

0

5 SS output pulse width

Tsclk + WAIT

3

T

6 SS input low to first SCLK edge –

7 SS input pulse width T –

1

2

3

T = CSPI system clock period (PERCLK2).

Tsclk = Period of SCLK.

WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.

Unit

ns ns ns ns ns ns ns

8

SCLK

9 9

Figure 39. SPI SCLK Timing Diagram

Ref No.

8

9

Table 19. Timing Parameter Table for SPI SCLK

3.0 ± 0.3 V

Parameter

SCLK frequency

SCLK pulse width

Minimum

0

100

Maximum

10

Unit

MHz ns

4.6

LCD Controller

This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MXS

Reference Manual

.

LSCLK

1

LD[15:0]

Figure 40. SCLK to LD Timing Diagram

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

55

Functional Description and Application Information

Table 20. LCDC SCLK Timing Parameter Table

3.0 ± 0.3 V

Ref No.

1

Parameter

SCLK to LD valid

Minimum

Maximum

2

T1

Non-display

T3

T4

Display region

Unit

ns

VSYN

HSYN

OE

LD[15:0]

T2

Line Y Line 1 Line Y

T5

T6

XMAX

T7

HSYN

SCLK

OE

LD[15:0]

T8

(1,1)

(1,2)

(1,X)

VSYN

T9 T10

Figure 41. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing

Symbol

T1

Description

End of OE to beginning of VSYN

T2

T3

T4

T5

T6

T7

Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing

HSYN period

VSYN pulse width

End of VSYN to beginning of OE

HSYN pulse width

End of HSYN to beginning to T9

End of OE to beginning of HSYN

Minimum Corresponding Register Value

(VWAIT1·T2)+T5+T6+T7+T9 T5+T6

+T7+T9

XMAX+5

T2

1

1

2

1

XMAX+T5+T6+T7+T9+T10

VWIDTH·(T2)

VWAIT2·(T2)

HWIDTH+1

HWAIT2+1

HWAIT1+1

Unit

Ts

Ts

Ts

Ts

Ts

Ts

Ts

56

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)

Symbol Description Minimum Corresponding Register Value Unit

T8

T9

T9

SCLK to valid LD data

End of HSYN idle2 to VSYN edge

(for non-display region)

End of HSYN idle2 to VSYN edge

(for Display region)

VSYN to OE active (Sharp = 0) when VWAIT2 = 0

VSYN to OE active (Sharp = 1) when VWAIT2 = 0

-3

2

1

3

2

1 ns

Ts

Ts

T10

T10

1

2

1

2

Ts

Ts

Note:

• Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.

VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41 , all 3 signals

are active low.

• The polarity of SCLK and LD[15:0] can also be programmed.

• SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.

In

Figure 41

, SCLK is always active.

• For T9 non-display region, VSYN is non-active. It is used as an reference.

• XMAX is defined in pixels.

4.7

Pulse-Width Modulator

The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in

Figure 42

and the parameters are listed in

Table 22 .

1

2a

3b

System Clock

2b

4b

3a

4a

PWM Output

Figure 42. PWM Output Timing Diagram

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

57

Functional Description and Application Information

Table 22. PWM Output Timing Parameter Table

1.8 ± 0.1 V

Ref No.

Parameter

Minimum

1

2a

2b

3a

3b

4a

System CLK frequency

1

0

Clock high time

1

3.3

Clock low time

1

7.5

Clock fall time

1

Clock rise time

1

Output delay time

1

Output setup time

1

5.7

5.7

4b

1

C

L

of PWMO = 30 pF

Maximum

87

5

6.67

3.0 ± 0.3 V

Minimum

5

5

0

5/10

5/10

Maximum

100

5/10

5/10

Unit

MHz ns ns ns ns ns ns

4.8

SDRAM Controller

This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic random access memory) Controller.

58

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

1

SDCLK

2

3S

3

CS

3H

3S

RAS

3S

3H

CAS

3S

3H

3H

WE

4S

4H

ROW/BA

ADDR

COL/BA

8

5

DQ

Data

6

7

3S

DQM

3H

Note:

CKE is high during the read/write cycle.

Figure 43. SDRAM Read Cycle Timing Diagram

Ref

No.

Table 23. SDRAM Read Timing Parameter Table

1.8 ± 0.1 V

Parameter

1 SDRAM clock high-level width

2 SDRAM clock low-level width

3 SDRAM clock cycle time

3S CS, RAS, CAS, WE, DQM setup time

3H CS, RAS, CAS, WE, DQM hold time

4S Address setup time

4H Address hold time

5 SDRAM access time (CL = 3)

Minimum

2.28

3.42

2.28

2.67

6

11.4

3.42

Maximum

6.84

3.0 ± 0.3 V

Minimum

2

2

3

10

3

4

4

Maximum

6

Unit

ns ns ns ns ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

59

Functional Description and Application Information

Table 23. SDRAM Read Timing Parameter Table (Continued)

1.8 ± 0.1 V 3.0 ± 0.3 V

Ref

No.

Parameter

Minimum Maximum Minimum

5 SDRAM access time (CL = 2)

5 SDRAM access time (CL = 1)

6 Data out hold time

7 Data out high-impedance time (CL = 3)

2.85

6.84

22

6.84

2.5

7 Data out high-impedance time (CL = 2)

7 Data out high-impedance time (CL = 1)

6.84

22

8 Active to read/write command period (RC = 1) t

RCD

1 – t

RCD1

1 t

RCD

= SDRAM clock cycle time. This settings can be found in the MC9328MXS reference manual.

Maximum

6

22

6

22

6

Unit

ns ns ns ns ns ns ns

SDCLK

1

3

2

CS

RAS

6

CAS

WE

ADDR

DQ

4

/ BA

5

ROW/BA

7

8

COL/BA

DATA

9

DQM

Figure 44. SDRAM Write Cycle Timing Diagram

60

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

Table 24. SDRAM Write Timing Parameter Table

1.8 ± 0.1 V 3.0 ± 0.3 V

Ref No.

Parameter

Minimum Maximum Minimum Maximum

3

4

1

2

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

Address setup time

2.67

6

11.4

3.42

4

4

10

3

5

6

7

8

Address hold time

Precharge cycle period

1

Active to read/write command delay

Data setup time t

2.28

t

RP

2

RCD2

4.0

– t

2

RP2 t

RCD2

2

9 Data hold time 2.28

– 2 –

1

2

Precharge cycle timing is included in the write timing diagram.

t

RP

and t

RCD

= SDRAM clock cycle time. These settings can be found in the MC9328MXS reference manual.

Unit

ns ns ns ns ns ns ns ns ns

SDCLK

1 3 2

CS

RAS

6

CAS

7 7

WE

ADDR

4

BA

5

ROW/BA

DQ

DQM

Figure 45. SDRAM Refresh Timing Diagram

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

61

Functional Description and Application Information

Table 25. SDRAM Refresh Timing Parameter Table

1.8 ± 0.1 V 3.0 ± 0.3 V

Ref No.

Parameter

Minimum Maximum Minimum Maximum

3

4

1

2

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

Address setup time

2.67

6

11.4

3.42

4

4

10

3

5 Address hold time 2.28

– 2 –

6 Precharge cycle period t

RP

1 – t

RP1

7 Auto precharge command period t

RC1

– t

RC1

1 t

RP

and t

RC

= SDRAM clock cycle time. These settings can be found in the MC9328MXS reference manual.

Unit

ns ns ns ns ns ns ns

SDCLK

CS

RAS

CAS

WE

ADDR

DQ

DQM

CKE

BA

Figure 46. SDRAM Self-Refresh Cycle Timing Diagram

62

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

4.9

USB Device Port

Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up.

Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer.

USBD_AFE

(Output)

USBD_ROE

(Output)

1 t

ROE_VPO t

VMO_ROE

4 t

PERIOD

6 3 t

VPO_ROE

USBD_VPO

(Output)

USBD_VMO

(Output)

USBD_SUSPND

(Output)

USBD_RCV

(Input)

USBD_VP

(Input) t

ROE_VMO

2 t

FEOPT

5

USBD_VM

(Input)

Figure 47. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)

Ref

No.

Table 26. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)

3.0 ± 0.3 V

Parameter

1 t

ROE_VPO

; USBD_ROE active to USBD_VPO low

2 t

ROE_VMO

; USBD_ROE active to USBD_VMO high

3 t

VPO_ROE

; USBD_VPO high to USBD_ROE deactivated

4 t

VMO_ROE

; USBD_VMO low to USBD_ROE deactivated (includes SE0)

Minimum

83.14

81.55

83.54

248.90

Maximum

83.47

81.98

83.80

249.13

Unit

ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

63

Functional Description and Application Information

Ref

No.

Table 26. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX) (Continued)

5 t

FEOPT

; SE0 interval of EOP

6 t

PERIOD

; Data transfer rate

Parameter

3.0 ± 0.3 V

Minimum

160.00

11.97

Maximum

175.00

12.03

Unit

ns

Mb/s

USBD_AFE

(Output)

USBD_ROE

(Output)

USBD_VPO

(Output)

USBD_VMO

(Output)

USBD_SUSPND

(Output)

USBD_RCV

(Input) t

FEOPR

1

USBD_VP

(Input)

USBD_VM

(Input)

Figure 48. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)

Table 27. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)

Ref No.

1

Parameter

t

FEOPR

; Receiver SE0 interval of EOP

3.0 ± 0.3 V

Minimum

82

Maximum

Unit

ns

4.10

I

2

C Module

The I

2

C communication protocol consists of seven elements: START, Data Source/Recipient, Data

Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.

64

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

SDA

5

3

4

3

4

1

2

5

6

Ref No.

SCL

2

1

Figure 49. Definition of Bus Timing for I

2

C

Table 28. I

2

C Bus Timing Parameter Table

1.8 ± 0.1 V

Parameter

Hold time (repeated) START condition

Data hold time

Data setup time

HIGH period of the SCL clock

LOW period of the SCL clock

Setup time for STOP condition

Minimum

182

0

11.4

80

480

182.4

Maximum

171

6

3.0 ± 0.3 V

Minimum

160

0

10

120

320

160

Maximum

150

Unit

ns ns ns ns ns ns

4.11

Synchronous Serial Interface

The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals.

Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams

are shown in Figure 51 through

Figure 53

.

Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of

I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

65

Functional Description and Application Information

1

STCK Output

2

4

STFS (bl) Output

STFS (wl) Output

6

10

11

STXD Output

31

32

SRXD Input

Note: SRXD input in synchronous mode only.

Figure 50. SSI Transmitter Internal Clock Timing Diagram

12

8

1

SRCK Output

3 5

SRFS (bl) Output

SRFS (wl) Output

7

13

14

SRXD Input

Figure 51. SSI Receiver Internal Clock Timing Diagram

9

66

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

16

15

17

STCK Input

18 20

STFS (bl) Input

STFS (wl) Input

22

28

26 27

STXD Output

33

34

SRXD Input

Note: SRXD Input in Synchronous mode only

Figure 52. SSI Transmitter External Clock Timing Diagram

24

16

15

17

SRCK Input

19 21

SRFS (bl) Input

23

SRFS (wl) Input

30

29

SRXD Input

Figure 53. SSI Receiver External Clock Timing Diagram

25

Table 29. SSI (Port C Primary Function) Timing Parameter Table

3

4

1

2

5

Ref No.

1.8 ± 0.1 V 3.0 ± 0.3 V

Parameter

Minimum Maximum Minimum Maximum

Internal Clock Operation

1

(Port C Primary Function

2

)

STCK/SRCK clock period

1

95

STCK high to STFS (bl) high

3

1.5

SRCK high to SRFS (bl) high

3

-1.2

STCK high to STFS (bl) low

3

2.5

SRCK high to SRFS (bl) low

3

0.1

4.5

-1.7

4.3

-0.8

83.3

1.3

-1.1

2.2

0.1

3.9

-1.5

3.8

-0.8

Unit

ns ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

67

Functional Description and Application Information

Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued)

27a

27b

28

29

30

23

24

25

26

19

20

21

22

15

16

17

18

10

11a

11b

12

13

14

8

9

6

7

Ref No.

1.8 ± 0.1 V 3.0 ± 0.3 V

Parameter

Minimum Maximum Minimum Maximum

STCK high to STFS (wl) high

3

1.48

SRCK high to SRFS (wl) high

3

-1.1

STCK high to STFS (wl) low

3

2.51

SRCK high to SRFS (wl) low

3

0.1

4.45

-1.5

4.33

-0.8

1.3

-1.1

2.2

0.1

3.9

-1.5

3.8

-0.8

STCK high to STXD valid from high impedance

STCK high to STXD high

14.25

0.91

15.73

3.08

12.5

0.8

13.8

2.7

STCK high to STXD low

STCK high to STXD high impedance

SRXD setup time before SRCK low

SRXD hold time after SRCK low

0.57

12.88

21.1

0

3.19

13.57

0.5

11.3

18.5

0

2.8

11.9

External Clock Operation (Port C Primary Function

2

)

STCK/SRCK clock period

1

92.8

STCK/SRCK clock high period

STCK/SRCK clock low period

STCK high to STFS (bl) high

3

SRCK high to SRFS (bl) high

3

STCK high to STFS (bl) low

3

SRCK high to SRFS (bl) low

3

STCK high to STFS (wl) high

3

SRCK high to SRFS (wl) high

3

STCK high to STFS (wl) low

3

SRCK high to SRFS (wl) low

3

27.1

61.1

92.8

92.8

92.8

92.8

92.8

92.8

92.8

92.8

STCK high to STXD valid from high impedance

STCK high to STXD high

STCK high to STXD low

STCK high to STXD high impedance

SRXD setup time before SRCK low

SRXD hole time after SRCK low

18.01

8.98

9.12

18.47

1.14

0

28.16

18.13

18.24

28.5

Synchronous Internal Clock Operation (Port C Primary Function

2

)

7.0

8.0

16.2

1.0

0

0

0

0

15.8

0

0

0

0

81.4

40.7

40.7

0

15.9

16.0

25.0

81.4

81.4

81.4

24.7

81.4

81.4

81.4

81.4

81.4

31

32

SRXD setup before STCK falling

SRXD hold after STCK falling

15.4

0

13.5

0

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

68

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Functional Description and Application Information

Table 29. SSI (Port C Primary Function) Timing Parameter Table (Continued)

1.8 ± 0.1 V 3.0 ± 0.3 V

Ref No.

Parameter Unit

Minimum Maximum Minimum Maximum

Synchronous External Clock Operation (Port C Primary Function

2

)

33 SRXD setup before STCK falling 1.14

– 1.0

– ns

34 SRXD hold after STCK falling 0 – 0 – ns

1

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

2

There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.

3 bl = bit length; wl = word length.

Table 30. SSI (Port B Alternate Function) Timing Parameter Table

Ref

No.

Parameter

1.8 ± 0.1 V

Minimum Maximum

10

11a STCK high to STXD high

11b

12 STCK high to STXD high impedance

13

STCK high to STXD low

Internal Clock Operation

1

(Port B Alternate Function

2

)

1 STCK/SRCK clock period

1

95

2 STCK high to STFS (bl) high

3

1.7

3 SRCK high to SRFS (bl) high

3

-0.1

4 STCK high to STFS (bl) low

3

3.08

5 SRCK high to SRFS (bl) low

3

1.25

6 STCK high to STFS (wl) high

3

7 SRCK high to SRFS (wl) high

3

1.71

9 SRCK high to SRFS (wl) low

3

-0.1

8 STCK high to STFS (wl) low

3

3.08

1.25

STCK high to STXD valid from high impedance

SRXD setup time before SRCK low

14 SRXD hold time after SRCK low

14.93

1.25

2.51

12.43

20

0

4.8

1.0

5.24

2.28

4.79

1.0

5.24

2.28

16.19

3.42

3.99

14.59

83.3

1.5

-0.1

2.7

1.1

1.5

-0.1

2.7

1.1

13.1

1.1

2.2

10.9

17.5

0

3.0 ± 0.3 V

Minimum Maximum

2.0

14.2

3.0

3.5

12.8

2.0

4.2

1.0

4.6

4.2

1.0

4.6

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

69

Functional Description and Application Information

Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued)

Ref

No.

Parameter

1.8 ± 0.1 V 3.0 ± 0.3 V

Unit

Minimum Maximum Minimum Maximum

External Clock Operation (Port B Alternate Function

2

)

15 STCK/SRCK clock period

1

92.8

– 81.4

16 STCK/SRCK clock high period

17 STCK/SRCK clock low period

18 STCK high to STFS (bl) high

3

19 SRCK high to SRFS (bl) high

3

20 STCK high to STFS (bl) low

3

21 SRCK high to SRFS (bl) low

3

22 STCK high to STFS (wl) high

3

23 SRCK high to SRFS (wl) high

3

24 STCK high to STFS (wl) low

3

25 SRCK high to SRFS (wl) low

3

27.1

61.1

92.8

92.8

92.8

92.8

92.8

92.8

92.8

92.8

40.7

40.7

0

0

0

0

0

0

0

0

26 STCK high to STXD valid from high impedance

27a STCK high to STXD high

27b STCK high to STXD low

28 STCK high to STXD high impedance

29 SRXD setup time before SRCK low

30 SRXD hold time after SRCK low

18.9

9.23

10.60

17.90

1.14

0

29.07

20.75

21.32

29.75

1.0

0

16.6

8.1

9.3

15.7

Synchronous Internal Clock Operation (Port B Alternate Function

2

)

31 SRXD setup before STCK falling

32 SRXD hold after STCK falling

18.81

0

16.5

0

Synchronous External Clock Operation (Port B Alternate Function

2

)

– ns ns

33 SRXD setup before STCK falling 1.14

– 1.0

– ns

34 SRXD hold after STCK falling 0 – 0 – ns

1

2

3

All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on

FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.

bl = bit length; wl = word length.

18.2

18.7

26.1

81.4

81.4

81.4

25.5

81.4

81.4

81.4

81.4

81.4

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

70

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

K

A

B

C

D

E

F

G

H

J

5 Pin-Out and Package Information

Table 31

illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the

Signal Multiplexing Table 3 on page 8.

Table 31. i.MXS 225 MAPBGA Pin Assignments

1

PB13

PB11

D31

A23

A21

A20

A17

A15

A14

2

PB15

PB12

PB8

A24

A22

A19

A18

A16

A12

3

PB19

PB16

PB14

PB9

D30

D28

D26

D23

D21

4

USBD_

ROE

USBD_

AFE

PB18

PB17

D29

D27

D25

D24

D20

5

USBD_

SUSPND

6

USBD_VM

USBD_

RCV

PB10

USBD_

VMO

USBD_

VPO

NVDD1

USBD_

VP

7

SSI_

RXFS

SSI_

RXDAT

UART2_

RXD

QVDD4

NVDD1

NVDD1

QVSS

NVDD1

UART2_

RTS

UART2_

CTS

NVDD1 NVSS NVDD4

D22

NVDD1

NVSS

NVSS

NVSS

NVSS

8

SSI_

TXCLK

UART1_

TXD

SSI_

TXFS

UART2_

TXD

UART1_

RXD

SSI_

RXCLK

NVSS

9

SPI1_SPI_

RDY

10

SPI1_

SCLK

11

REV

SPI1_SS

UART1_

RTS

CONTRAST FLM/VSYNC

NVDD3

UART1_

CTS

SSI_

TXDAT

LSCLK

SPI1_

MOSI

SPI1_

MISO

CLS

SPL_

SPR

LP/HSYNC

ACD/OE

QVDD3

NVSS QVSS PWMO

NVSS

QVDD1

NVSS

NVSS

NVDD2

PA10

PA5

I2C_SCL

12

PS

LD0

LD8

LD1

LD10

LD14

PA7

PA12

TCK

13

LD2

LD3

LD9

LD11

TIN

LD15

14

LD4

LD6

LD12

TMR2OUT

PA4

PA6

15

LD5

LD7

NVDD2

LD13

PA3

PA8

A13 A11 CS2 D19 NVDD1 NVSS QVSS

N

P

L

M

A10

D16

A8

D14

A9

D15

A7

A5

D17

D13

D12

A4

D18

D10

EB0

A3

NVDD1

EB3

D9

A2

NVDD1

NVDD1

D8

A1

R

A6 D11 EB1 EB2 OE D7 A0

1 2 3 4 5 6

1

2

Burst Clock

This signal is not used and should be floated in an actual application.

7

CS5

CS4

CS3

D6

NVDD1

D2

CS1

CS0

D5

SDCLK

8

NVSS

ECB

BCLK

1

PA17

MA10

D4

9

D1

NVSS

RW

D0

MA11

LBA

10

BOOT2

NVSS

NVSS

DQM2

DQM1

D3

11

TDI

POR

BOOT3

DQM0

RAS

DQM3

12

A

B

C

D

E

F

PA11

PA14

PA13

I2C_SDA

PA9

TMS

TDO

BIG_

ENDIAN

QVSS

QVDD2

BOOT1

RESET_

OUT

BOOT0

XTAL32K

XTAL16M EXTAL32K

J

K

L

RESET_IN EXTAL16M

M

SDCKE0 TRISTATE

SDCKE1

CAS

13

CLKO

SDWE

14

TRST

N

RESET_SF

2

P

R

AVDD1

15

G

H

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MXS Product Family

Pin-Out and Package Information

5.1

MAPBGA 225 Package Dimensions

Figure 54

illustrates the 225 MAPBGA 13 mm × 13 mm package.

Case Outline 1304B

TOP VIEW

72

BOTTOM VIEW

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2.DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.

SIDE VIEW

3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER

BALLS.

5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE

OF PACKAGE

Figure 54. i.MXS 225 MAPBGA Mechanical Drawing

MC9328MXS Technical Data, Rev. 3

Freescale Semiconductor

Product Documentation

6 Product Documentation

6.1

Revision History

Table 32

provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes.

Table 32. i.MXS Data Sheet Revision History Rev. 3

Location

Table 2 on page 4

Signal Names and

Descriptions

Table 3 on page 8

Signal Multiplex Table i.MXS

Table 10 on page 20

Revision

• Added the DMA_REQ signal to table.

• Corrected signal name from USBD_OE to USBD_ROE

Added Signal Multiplex table from Reference Manual with the following changes:

• Corrected BGA pin assignments.

Changed first and second parameters descriptions:

From: Reference Clock freq range, To: DPLL input clock freq range

From: Double clock freq range, To: DPLL output freq range

6.2

Reference Documents

The following documents are required for a complete description of the MC9328MXS and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous i.MX processor products, the following documents are helpful when used in conjunction with this document.

ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)

ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)

ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)

EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)

MC9328MXS Product Brief (order number MC9328MXSP)

MC9328MXS Reference Manual (order number MC9328MXSRM)

The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.

Freescale Semiconductor

MC9328MXS Technical Data, Rev. 3

73

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

[email protected]

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130 [email protected]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French) [email protected]

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064, Japan

0120 191014 or +81 3 5437 9125 [email protected]

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080 [email protected]

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-521-6274 or 303-675-2140

Fax: 303-675-2150

[email protected]

Information in this document is provided solely to enable system and software implementers to use

Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts.

Freescale Semiconductor does not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use

Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ARM and the

ARM POWERED logo are the registered trademarks of ARM Limited. ARM9, ARM920T, and

ARM9TDMI are the trademarks of ARM Limited. All other product or service names are the property of their respective owners.

© Freescale Semiconductor, Inc. 2006. All rights reserved.

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative.

For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp.

Document Number:

MC9328MXS

Rev. 3

12/2006

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement

Table of contents