CY2545FC скачать даташит

CY2545FC скачать даташит
CY2545, CY2547
Quad PLL Programmable
Spread Spectrum Clock Generator
with Serial I2C Interface
Features
■
Four fully integrated phase locked loops (PLLs)
■
Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
■
■
Up to eight clock outputs with programmable drive strength
■
Glitch-free outputs while frequency switching
■
24-pin QFN package
■
Commercial and industrial temperature ranges
Benefits
Wide operating output frequency range
❐ 3 to 166 MHz
■
Multiple high performance PLLs allow synthesis of unrelated
frequencies
■
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■
Application specific programmable EMI reduction using Spread
Spectrum for clocks
■
Programmable PLLs for system frequency margin tests
■
Meets critical timing requirements in complex system designs
■
Suitability for PC, consumer, portable, and networking applications
2
■
Serial programmable over 2-wire I C interface
■
Programmable spread spectrum with center and down spread
option and Lexmark and Linear modulation profiles
■
VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V for CY2545
❐ 1.8 V for CY2547
■
Selectable output clock voltages independent of VDD supply:
❐ 2.5 V, 3.0 V, and 3.3 V for CY2545
❐ 1.8 V for CY2547
■
Power-down, output enable, or frequency select features
■
Low jitter, high accuracy outputs
■
Capable of zero PPM frequency synthesis error
■
Ability to synthesize nonstandard frequencies with Fractional-N
capability
■
Uninterrupted system operation during clock frequency switch
■
Application compatibility in standard and low power systems
Logic Block Diagram
CLKIN/RST
Crossbar
XIN/
EXCLKIN
XOUT
CLK1
Switch
Output
OSC
Bank
1
CLK2
PLL1
Dividers
CLK3
and
Drive
PLL2
MUX
and
Control
Logic
FS
Bank
2
CLK5
Strength
Control
CLK6
Bank
3
PLL3
(SS)
CLK4
CLK7
CLK8
SCL
SDA
PLL4
(SS)
I2C
PD#/OE
SSON
Cypress Semiconductor Corporation
Document #: 001-13196 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2011
[+] Feedback
CY2545, CY2547
Contents
Pinouts .............................................................................. 3
General Description ......................................................... 5
Four Configurable PLLs .............................................. 5
I2C Programming ........................................................ 5
Input Reference Clocks ............................................... 5
Multiple Power Supplies .............................................. 5
Output Bank Settings .................................................. 5
Output Source Selection ............................................. 5
Spread Spectrum Control ............................................ 5
Frequency Select ........................................................ 5
Glitch-Free Frequency Switch ..................................... 5
Device Reset Function ................................................ 5
PD#/OE Mode ............................................................. 6
Keep Alive Mode ......................................................... 6
Output Drive Strength .................................................. 6
Generic Configuration and Custom Frequency ........... 6
Serial I2C Programming Interface
Protocol and Timing ......................................................... 6
Device Address ........................................................... 6
Data Valid .................................................................... 6
Data Frame ................................................................. 6
Acknowledge Pulse ..................................................... 6
Write Operations ............................................................... 7
Writing Individual Bytes ............................................... 7
Writing Multiple Bytes .................................................. 7
Document #: 001-13196 Rev. *C
Read Operations ............................................................... 7
Current Address Read ................................................. 7
Random Read ............................................................. 7
Sequential Read .......................................................... 7
Serial I2C Programming Interface Timing ...................... 9
Serial I2C Programming Interface
Timing Specifications ...................................................... 9
Absolute Maximum Conditions ..................................... 10
Recommended Operating Conditions .......................... 10
DC Electrical Specifications .......................................... 11
Recommended Crystal Specification
for SMD Package ............................................................ 12
Test and Measurement Setup ........................................ 13
Voltage and Timing Definitions ..................................... 13
Ordering Information ...................................................... 14
Package Drawing and Dimensions ............................... 15
Reference Information ................................................... 16
Acronyms ................................................................. 16
Document Conventions ............................................. 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Page 2 of 17
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CY2545, CY2547
Pinouts
XIN/
EXCLKIN
XOUT
VDD
CLKIN/RST
CLK8
GND
Figure 1. Pin Diagram – CY2545 24-pin QFN
24
23
22
21
20
19
GND
1
18
GND
CLK1
2
17
CLK7
VDD_CLK_B1
3
16
VDD_CLK_B3
PD#OE
4
15
CLK6/SSON
DNU
5
14
VDD_CLK_B2
6
13
CLK5
9
10
SDA
CLK3/FS
11
12
GND
8
CLK4
7
SCL
24LD QFN
GND
CLK2
CY2545
Table 1. Pin Definition – CY2545 24-pin QFN (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
Name
I/O
Description
1
GND
Power
Power supply ground
2
CLK1
Output
Programmable clock output. Output voltage depends on Bank1 voltage
3
VDD_CLK_B1
Power
Power supply for Bank1 (CLK1, CLK2) output: 2.5 V/3.0 V/3.3 V
4
PD#/OE
Input
Multifunction programmable pin: Output enable or Power-down mode
5
DNU
DNU
Do not use this pin
6
CLK2
Output
Programmable clock output. Output voltage depends on Bank1 voltage
7
GND
Power
Power supply ground
8
SCL
Input
Serial data clock
9
SDA
Input/Output
Serial data input/output
10
CLK3/FS
Output/Input
Multifunction programmable pin: Programmable clock output or frequency
select input pin. Output voltage of CLK3 depends on Bank2 voltage
11
CLK4
Output
Programmable clock output. Output voltage depends on Bank2 voltage
12
GND
Power
Power supply ground
13
CLK5
Output
Programmable clock output. Output voltage depends on Bank2 voltage
14
VDD_CLK_B2
Power
Power supply for Bank2 (CLK3, CLK4, CLK5) output: 2.5 V/3.0 V/3.3 V
15
CLK6/SSON
Output/Input
Multifunction programmable pin: Programmable clock output or spread
spectrum ON/OFF control input pin. Output voltage of CLK6 depends on
Bank3 voltage
16
VDD_CLK_B3
Power
Power supply for Bank3 (CLK6, CLK7, CLK8) output: 2.5 V/3.0 V/3.3 V
17
CLK7
Output
Programmable clock output. Output voltage depends on Bank3 voltage
18
GND
Power
Power supply ground
19
GND
Power
Power supply ground
20
CLK8
Output
Programmable clock output. Output voltage depends on Bank3 voltage
21
CLKIN/RST
Input/Input
Multifunction programmable pin. High true reset input or 2.5 V/3.0 V/3.3 V
external reference clock input. The signal level of CLKIN input must track VDD
power supply on pin 22.
22
VDD
Power
Power supply for core and inputs: 2.5 V/3.0 V/3.3 V
Document #: 001-13196 Rev. *C
Page 3 of 17
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CY2545, CY2547
Table 1. Pin Definition – CY2545 24-pin QFN (VDD = 2.5 V, 3.0 V or 3.3 V Supply) (continued)
Pin Number
Name
I/O
Description
23
XOUT
Output
Crystal output
24
XIN/EXCLKIN
Input
Crystal input or 1.8 V external clock input
GND
22
CLK8
23
CLKIN/RST
XOUT
24
VDD
XIN/
EXCLKIN
Figure 2. Pin Diagram – CY2547 24-pin QFN
21
20
19
GND
1
18
GND
CLK1
2
17
CLK7
VDD_CLK_B1
3
16
VDD_CLK_B3
PD#OE
4
15
CLK6/SSON
VDD
5
14
VDD_CLK_B2
CLK2
6
13
CLK5
CY2547
SCL
SDA
10
11
12
GND
9
CLK4
8
CLK3/FS
7
GND
24LD QFN
Table 2. Pin Definition – CY2547 24-pin QFN (VDD = 1.8 V Supply)
Pin Number
Name
I/O
Description
1
GND
Power
Power supply ground
2
CLK1
Output
Programmable clock output. Output voltage depends on Bank1 voltage
3
VDD_CLK_B1
Power
Power supply for Bank1 (CLK1, CLK2) output: 1.8 V
4
PD#/OE
Input
Multifunction programmable pin: Output enable or Power-down mode
5
VDD
Power
Power supply for core and inputs: 1.8 V
6
CLK2
Output
Programmable output clock. Output voltage depends on Bank1 voltage
7
GND
Power
Power supply ground
8
SCL
Input
Serial data clock
9
SDA
Input/Output
Serial data input
10
CLK3/FS
Output/Input
Multifunction programmable pin: Programmable clock output or frequency
select input pin. Output voltage of CLK3 depends on VDD_CLK_B2 voltage
11
CLK4
Output
Programmable output clock. Output voltage depends on Bank2 voltage
12
GND
Power
Power supply ground
13
CLK5
Output
Programmable clock output. Output voltage depends on Bank2 voltage
14
VDD_CLK_B2
Power
Power supply for Bank2 (CLK3, CLK4, CLK5) output: 1.8 V
15
CLK6/SSON
Output/Input
Multifunction programmable pin: Programmable clock output or spread
spectrum ON/OFF control input pin. Output voltage of CLK6 depends on
VDD_CLK_B3 voltage
16
VDD_CLK_B3
Power
Power supply for Bank3 (CLK6, CLK7, CLK8) output: 1.8 V
17
CLK7
Output
Programmable clock output. Output voltage depends on Bank3 voltage
18
GND
Power
Power supply ground
19
GND
Power
Power supply ground
20
CLK8
Output
Programmable clock output. Output voltage depends on Bank3 voltage
Document #: 001-13196 Rev. *C
Page 4 of 17
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CY2545, CY2547
Table 2. Pin Definition – CY2547 24-pin QFN (VDD = 1.8 V Supply) (continued)
Pin Number
Name
I/O
Description
21
CLKIN/RST
Input/Input
Multifunction programmable pin: High true reset input or 1.8 V external low
voltage reference clock input
22
VDD
Power
Power supply for core and inputs: 1.8 V
23
XOUT
Output
Crystal output
24
XIN/EXCLKIN
Input
Crystal input or 1.8 V external clock input
General Description
Four Configurable PLLs
Output Source Selection
The CY2545 and CY2547 have four I2C programmable PLLs
available to generate output frequencies ranging from 3 to 166
MHz. The advantage of having four PLLs is that a single device
generates up to four independent frequencies from a single
crystal. Two sets of frequencies for each PLL can be
programmed. This enables in system frequency switching using
multifunction frequency select pin, FS.
These devices have eight clock outputs (CLK1 - 8). There are six
available clock sources for these outputs. These clock sources
are: XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output
clock source selection is done using four out of six crossbar
switch. Thus, any one of these six available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have up to four independent clock outputs.
I2C Programming
Spread Spectrum Control
The CY2545 and CY2547 have a serial I2C interface that
programs the configuration memory array to synthesize output
frequencies by programmable output divider, spread characteristics, drive strength, and crystal load capacitance. I2C can also
be used for in system control of these programmable features.
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and Spread Spectrum Clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Input Reference Clocks
The input to the CY2545 and CY2547 is either a crystal or a clock
signal. The input frequency range for crystals is 8 MHz to 48
MHz. There is provision for two reference clock inputs, CLKIN
and EXCLKIN with frequency range of 8 MHz to 166 MHz. For
both devices, when CLKIN signal at pin 21 is used as a reference
input, a valid signal at EXCLKIN (as specified in the AC and DC
Electrical Specification table), must be present for the devices to
operate properly.
Multiple Power Supplies
The CY2545 and CY2547 are designed to operate at internal
core supply voltage of 1.8 V. In the case of the high voltage part
(CY2545), an internal regulator is used to generate 1.8 V from
the 2.5 V/3.0 V/3.3 V VDD supply voltage at pin 22. For the low
voltage part (CY2547), this internal regulator is bypassed and 1.8
V at VDD pin 22 is directly used.
Frequency Select
The device can store two different PLL frequency configurations,
output source selection and output divider values for all eight
outputs in its nonvolatile memory location. There is a multifunction programmable pin, CLK3/FS which, if programmed as
frequency select input, can be used to select between these two
arbitrarily programmed settings.
Glitch-Free Frequency Switch
When the frequency select pin (FS) is used to switch frequency,
the outputs are glitch-free provided frequency is switched using
output dividers. This feature enables uninterrupted system
operation while clock frequency is switched.
Output Bank Settings
Device Reset Function
These devices have eight clock outputs grouped in three output
driver banks. The Bank 1, Bank 2, and Bank 3 correspond to
(CLK1, CLK2), (CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8),
respectively. Separate power supplies are used for each of these
banks and they can be any of 2.5 V, 3.0 V, or 3.3 V for CY2545
and 1.8 V for CY2547 giving user multiple choice of output clock
voltage levels.
There is a multifunction CLKIN/RST (pin 21) that can be
programmed to use for the device reset function. There are two
different programmable modes of operation for this device reset
function. First one (called POR like reset), when used brings the
device in the default register settings loosing all configuration
changes made through the I2C interface. The second (called
Clean Start), keeps the I2C programmed values while giving all
outputs a simultaneous clean start from its low pull-down state.
Document #: 001-13196 Rev. *C
Page 5 of 17
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CY2545, CY2547
PD#/OE Mode
PD#/OE (Pin 4) is programmable to operate as either
power-down (PD#) or output enable (OE) mode. PD# is a low
true input. If activated it shuts off the entire chip, resulting in
minimum device power consumption. Setting this signal high
brings the device into operational mode with default register
settings.
When this pin is programmed as output enable (OE), clock
outputs are enabled or disabled using OE pin. Individual clock
outputs can be programmed to be sensitive to this OE pin.
Keep Alive Mode
By activating the device in the keep alive mode, power-down
mode is changed to power saving mode. This disables all PLLs
and outputs, but preserves the contents of the volatile registers.
Thus, any configuration changes made through the I2C interface
are preserved. By deactivating the keep alive mode, I2C memory
is not preserved during power-down, but power consumption is
reduced relative to the keep alive mode.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 4 shows the typical rise
and fall times for different drive strength settings.
Table 3. Output Drive Strength
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Serial I2C Programming Interface Protocol
and Timing
To enhance the flexibility and function of the clock synthesizer, a
two signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, are individually enabled or disabled. The registers
associated with the Serial Data Interface initialize to their default
setting upon power-up and therefore, use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required.
The CY2545 and CY2547 use a 2-wire serial interface SDA and
SCL that operates up to 400 kbits/s in read or write mode. The
SDA and SCL timing and data transfer sequence is shown in
Figure 3. The basic write serial format is:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4.
Device Address
The device serial interface address is 69H. The device address
is combined with a read/write bit as the LSB and is sent after
each start bit.
Data Valid
Low
6.8
Data is valid when the clock is HIGH, and is only transitioned
when the clock is LOW, as illustrated in Figure 5.
Mid Low
3.4
Data Frame
Mid High
2.0
High
1.0
A start and stop sequence indicates every new data frame, as
illustrated in Figure 6.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY2545/CY2547 can be custom programmed to any
desired frequencies and listed features. For customer specific
programming and I2C programmable memory bitmap definitions,
please contact your local Cypress Field Application Engineer
(FAE) or sales representative.
Start Sequence - The start frame is indicated by SDA going LOW
when SCL is HIGH. Every time a start signal is supplied, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Stop Sequence - The stop frame is indicated by SDA going HIGH
when SCL is HIGH. A stop frame frees the bus to go to another
part on the same bus or to another random register address.
Acknowledge Pulse
During write mode the CY2545/CY2547 responds with an
acknowledge pulse after every eight bits. Do this by pulling the
SDA line LOW during the N × 9th clock cycle as illustrated in
Figure 7 (N = the number of bytes transmitted). During read
mode, the master generates the acknowledge pulse after
reading the data packet.
Document #: 001-13196 Rev. *C
Page 6 of 17
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CY2545, CY2547
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
read operation returns the value stored in location ‘n+1’. When
the CY2545/CY2547 receive the slave address with the R/W bit
set to a ‘1’, the CY2545/CY2547 issue an acknowledge and
transmit the 8-bit word. The master device does not
acknowledge the transfer, but generates a STOP condition,
which causes the CY2545/CY2547 to stop transmission.
Random Read
To write multiple bytes at a time, the master does not end the
write sequence with a STOP condition; instead, the master
sends multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, the same as
after the first byte, and accepts data until the STOP condition
responds to the acknowledge bit. When receiving multiple bytes,
the CY2545 and CY2547 internally increment the register
address.
Through random read operations, the master may access any
memory location. To perform this type of read operation, first the
word address must be set. This is done by sending the address
to the CY2545/CY2547 as part of a write operation. After sending
the word address, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next, the master reissues the
control byte with the R/W byte set to ‘1’. The CY2545/CY2547
then issue an acknowledge and transmit the 8-bit word. The
master device does not acknowledge the transfer, but generates
a STOP condition, which causes the CY2545/CY2547 to stop
transmission.
Read Operations
Sequential Read
Read operations are initiated the same way as write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmitting the first 8-bit data word. This
action increments the internal address pointer, and subsequently
output of the next 8-bit data word. By continuing to issue
acknowledges instead of STOP conditions, the master serially
reads the entire contents of the slave device memory. When the
internal address pointer points to the FFH register, after the next
increment, the pointer points to the 00H register.
Writing Multiple Bytes
Current Address Read
The CY2545 and CY2547 have an onboard address counter that
retains 1 more than the address of the last word access. If the
last word written or read was word ‘n’, then a current address
Document #: 001-13196 Rev. *C
Page 7 of 17
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CY2545, CY2547
Figure 3. Data Transfer Sequence on the Serial Bus
SCL
SDA
Address or
Acknowledge
Valid
START
Condition
STOP
Condition
Data may
be changed
Figure 4. Data Frame Architecture
SDA Write
Multiple
Contiguous
Registers
1 Bit
1 Bit Slave
R/W = 0 ACK
7-bit
Device
Address
1 Bit
Slave
ACK
8-bit
Register
Address
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+1)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+2)
1 Bit
Slave
ACK
8-bit
Register
Data
(FFH)
1 Bit
Slave
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
SDA Read
Current
Address
Read Start Signal
SDA Read
Multiple
Contiguous
Registers
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
ACK
R/W = 1
7-bit
Device
Address
1 Bit
Slave
ACK
1 Bit
Master
ACK
8-bit
Register
Data
Stop Signal
1 Bit
1 Bit Slave
ACK
R/W = 0
7-bit
Device
Address
1 Bit
Slave
ACK
8-bit
Register
Address
(XXH)
1 Bit
Master
ACK
7-bit
Device
Address
+R/W=1
1 Bit
Master
ACK
8-bit
Register
Data
(XXH)
1 Bit
Master
ACK
8-bit
Register
Data
(XXH+1)
8-bit
Register
Data
(FFH)
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
Repeated
Start bit
Figure 5. Data Valid and Data Transition Periods
Data Valid
Transition
to next Bit
SDA
tDH
tSU
CLKHIGH
VIH
SCL
Document #: 001-13196 Rev. *C
VIL
CLKLOW
Page 8 of 17
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CY2545, CY2547
Serial I2C Programming Interface Timing
Figure 6. .Start and Stop Frame
SDA
Transition
to next Bit
START
SCL
STOP
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDA
+
START
SCL
DA6
DA5 DA0
+
R/W
ACK
RA7
RA6 RA1
+
RA0
ACK
+
+
D7
D6
D1
D0
ACK
STOP
+
Serial I2C Programming Interface Timing Specifications
Parameter
fSCL
Description
Frequency of SCL
Min
Max
Unit
–
400
kHz
Start mode time from SDA LOW to SCL LOW
0.6
–
μs
CLKLOW
SCL LOW period
1.3
–
μs
CLKHIGH
SCL HIGH period
0.6
–
μs
tSU
Data transition to SCL HIGH
250
–
ns
tDH
Data hold (SCL LOW to data transition)
0
–
ns
Rise time of SCL and SDA
–
300
ns
Fall time of SCL and SDA
–
300
ns
Stop mode time from SCL HIGH to SDA HIGH
0.6
–
μs
Stop mode to start mode
1.3
–
μs
Document #: 001-13196 Rev. *C
Page 9 of 17
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CY2545, CY2547
Absolute Maximum Conditions
Min
Max
Unit
VDD
Parameter
Supply voltage for CY2545
Description
Condition
–0.5
4.5
V
VDD
Supply voltage for CY2547
–0.5
2.6
V
VDD_CLK_BX
Output bank supply voltage
–0.5
4.5
V
VIN
Input voltage for CY2545
Relative to VSS
–0.5
VDD + 0.5
V
VIN
Input voltage for CY2547
Relative to VSS
–0.5
2.2
V
+150
°C
TS
Temperature and storage
Nonfunctional
–65
ESDHBM
ESD protection (human body model)
JEDEC EIA/JESD22-A114-E
2000
UL-94
Flammability rating
V-0 at1/8 in.
MSL
Moisture sensitivity level
V
10
ppm
3
Recommended Operating Conditions
Min
Typ
Max
Unit
VDD
Parameter
VDD operating voltage for CY2545
Description
2.25
–
3.60
V
VDD
VDD operating voltage for CY2547
1.65
1.8
1.95
V
VDD_CLK_BX
Output driver voltage for bank 1, 2 and 3
1.43
–
3.60
V
TAC
Commercial ambient temperature
TAI
Industrial ambient temperature
CLOAD
Maximum load capacitance
tPU
Power-up time for all VDD to reach minimum specified voltage
(power ramps must be monotonic)
Document #: 001-13196 Rev. *C
0
–
+70
°C
–40
–
+85
°C
–
–
15
pF
0.05
–
500
ms
Page 10 of 17
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CY2545, CY2547
DC Electrical Specifications
Parameter
VOL
Description
Output low voltage
Conditions
IOL = 2 mA, drive strength = [00]
Min
Typ
Max
Unit
–
–
0.4
V
VDD_CLK_BX
– 0.4
–
–
V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH
Output high voltage
IOH = –2 mA, drive strength = [00]
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VOLSD
Output low voltage, SDA
–
–
0.4
V
VIL1
Input low voltage of PD#/OE, RST,
FS, and SSON
–
–
0.2 × VDD
V
VIL2
Input low voltage of CLKIN for
CY2545
–
–
0.1 × VDD
V
VIL3
Input low voltage of EXCLKIN for
CY2545
–
–
0.18
V
VIL4
Input low voltage of CLKIN,
EXCLKIN for CY2547
–
–
0.1 × VDD
V
VIH1
Input high voltage of PD#/OE,
RST, FS, and SSON
0.8 × VDD
–
–
V
VIH2
Input high voltage of CLKIN for
CY2545
0.9 × VDD
–
–
V
VIH3
Input high voltage of EXCLKIN for
CY2545
1.62
–
2.2
V
VIH4
Input high voltage of CLKIN,
EXCLKIN for CY2547
0.9 × VDD
–
–
V
IILPD
Input low current of RST and
PD#/OE
VIL = 0 V
–
–
10
µA
IIHPD
Input high current of RST and
PD#/OE
VIH = VDD
–
–
10
µA
IILSR
Input low current of SSON and FS VIL = 0 V (Internal pull-down = 160 k typ)
–
–
10
µA
IIHSR
14
–
36
µA
RDN
Input high current of SSON and FS VIH = VDD (Internal pull-down = 160 k typ)
Pull-down resistor of (CLK1-CLK8)
when off, CLK6/SSON and
CLK3/FS
100
160
250
kΩ
IDD[1, 2]
Supply current for CY2547
PD# = high, no load
–
20
–
mA
Supply current for CY2545
PD# = high, no load
–
22
–
mA
[1]
IOL = 4 mA
I2C
IDDS
Standby current
PD# = low, no load, with
keep alive mode
circuit not in
–
3
–
µA
IPD[1]
Power-down current
PD# = low, no load, with I2C circuit in keep
alive mode
–
–
1
mA
CIN[1]
Input capacitance
SSON, RST, PD#/OE or FS inputs
–
7
pF
Notes
1. Guaranteed by design but not 100% tested.
2. Configuration dependent.
Document #: 001-13196 Rev. *C
Page 11 of 17
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CY2545, CY2547
AC Electrical Specifications
Parameter
Description
FIN (crystal)
Crystal frequency, XIN
FIN (clock)
Input clock frequency
Conditions
Min
Typ
Max
Unit
8
–
48
MHz
Clock inputs CLKIN or EXCLKIN
8
–
166
MHz
FCLK
Output clock frequency
3
–
166
MHz
DC1
Output duty cycle, all clocks
except ref out
Duty cycle is defined in Figure 9; t1/t2, measured 50%
of VDD
45
50
55
%
DC2
Ref out clock duty cycle
Ref In Min 45%, Max 55%
40
–
60
%
[3]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as shown
in Figure 10, CLOAD = 15 pF, Drive strength [00]
–
6.8
–
ns
TRF2[3]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as shown
in Figure 10, CLOAD = 15 pF, Drive strength [01]
–
3.4
–
ns
TRF3[3]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as shown
in Figure 10, CLOAD = 15 pF, Drive strength [10]
–
2.0
–
ns
TRF4[3]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as shown
in Figure 10, CLOAD = 15 pF, Drive strength [11]
–
1.0
–
ns
TCCJ[3, 4]
Cycle-to-cycle jitter max (Pk-Pk)
Configuration dependent. See Table 4
–
150
–
ps
PLL lock time
Measured from 90% of the applied power supply level
–
1
3
ms
TRF1
[3]
TLOCK
Table 4. Configuration Example for C-C Jitter
Ref. Freq.
(MHz)
CLK1 Output
Freq.
(MHz)
C-C Jitter
Typ (ps)
14.3181
8.0
19.2
74.25
CLK2 Output
CLK3 Output
Freq.
(MHz)
C-C Jitter
Typ (ps)
Freq.
(MHz)
134
166
103
99
166
94
CLK4 Output
C-C Jitter
Typ (ps)
Freq.
(MHz)
48
92
74.25
81
8
91
27
110
CLK5 Output
C-C Jitter
Typ (ps)
27
48
67
27
109
166
103
74.25
97
48
48
93
27
123
166
137
166
138
Freq.
(MHz)
C-C Jitter
Typ (ps)
Not used
48
75
Not used
8
103
Recommended Crystal Specification for SMD Package
Parameter
Fmin
Description
Minimum frequency
Range 1
8
Range 2 Range 3
14
Unit
28
MHz
Fmax
Maximum frequency
14
28
48
MHz
R1
Motional resistance (ESR)
135
50
30
Ω
C0
Shunt capacitance
4
4
2
pF
CL
Parallel load capacitance
18
14
12
pF
DL(max)
Maximum crystal drive level
300
300
300
µW
Recommended Crystal Specification for Thru-Hole Package
Parameter
Description
Range 1
Range 2 Range 3
Unit
Fmin
Minimum frequency
8
14
24
MHz
Fmax
Maximum frequency
14
24
32
MHz
R1
Motional resistance (ESR)
90
50
30
Ω
C0
Shunt capacitance
7
7
7
pF
CL
Parallel load capacitance
DL(max)
Maximum crystal drive level
18
12
12
pF
1000
1000
1000
µW
Notes
3. Guaranteed by design but not 100% tested.
4. Configuration dependent.
Document #: 001-13196 Rev. *C
Page 12 of 17
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CY2545, CY2547
Test and Measurement Setup
Figure 8. Test and Measurement Setup
V DD
0.1 μF
Outputs
C LOAD
DUT
GND
Voltage and Timing Definitions
Figure 9. Duty Cycle Definition
t1
t2
VDD_CLK_BX
50% of V
Clock
Output
DD_CLK_BX
0V
Figure 10. Rise Time = TRF, Fall Time = TRF
TRF
TRF
V DD_CLK_BX
80% of V
Clock
Output
Document #: 001-13196 Rev. *C
20% of V
DD_CLK_BX
DD_CLK_BX
0V
Page 13 of 17
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CY2545, CY2547
Ordering Information
All product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations
table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for
more information.
Possible Configurations
Part Number[5]
Type
VDD(V)
Production Flow
Pb-free
CY2545Cxxx
24-pin QFN
Supply voltage: 2.5 V, 3.0 V or 3.3 V
Commercial, 0 °C to 70 °C
CY2545CxxxT
24-pin QFN tape and reel Supply voltage: 2.5 V, 3.0 V or 3.3 V
Commercial, 0 °C to 70 °C
CY2547Cxxx
24-pin QFN
Supply voltage: 1.8 V
Commercial, 0 °C to 70 °C
CY2547CxxxT
24-pin QFN tape and reel Supply voltage: 1.8 V
Commercial, 0 °C to 70 °C
CY2545Ixxx
24-pin QFN
Industrial, –40 °C to 85 °C
Supply voltage: 2.5 V, 3.0 V or 3.3 V
CY2545IxxxT
24-pin QFN tape and reel Supply voltage: 2.5 V, 3.0 V or 3.3 V
Industrial, –40 °C to 85 °C
CY2547Ixxx
24-pin QFN
Supply voltage: 1.8 V
Industrial, –40 °C to 85 °C
CY2547IxxxT
24-pin QFN tape and reel Supply voltage: 1.8 V
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY
2545/7
C
xxx
T
Tape and reel
Three digit numeric custom
configuration code
Temperature range:
C = Commercial, I = Industrial
Base part number
Company Code: CY = Cypress
Note
5. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document #: 001-13196 Rev. *C
Page 14 of 17
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CY2545, CY2547
Package Drawing and Dimensions
Figure 11. 24-pin QFN 4 × 4 mm (subcon punch type package with 2.49 × 2.49 EPAD) LF24A/LY24A
51-85203 *B
Document #: 001-13196 Rev. *C
Page 15 of 17
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CY2545, CY2547
Reference Information
Acronyms
Document Conventions
Table 5. Acronyms Used in this Document
Units of Measure
Acronym
PLL
Description
Table 6. Units of Measure
Symbol
phase-locked loop
Unit of Measure
I C
inter integrated circuit
°C
degree Celsius
QFN
quad flat no leads
kHz
kilohertz
JEDEC EIA
Joint Electron Device Engineering Council
Electronic Industries Alliance
MHz
megahertz
μA
microampere
ESD
electrostatic discharge
μs
microsecond
ESR
equivalent series resistance
μW
microwatt
mA
milliampere
ms
millisecond
ns
nanosecond
W
ohm
2
Document #: 001-13196 Rev. *C
ppm
parts per million
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 16 of 17
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CY2545, CY2547
Document History Page
Document Title: CY2545 CY2547 Quad PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface
Document Number: 001-13196
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
870780
RGL/AESA
See ECN
New Datasheet
*A
1504843
RGL/AESA
See ECN
Changed I2C Tsu specification from 100 ns to 250 ns
Changed ESD spec from MIL-STD to JEDEC
Combined VDD operating condition spec for CY2545 to a single VDD spec
Changed name from VDD_CORE to VDD
*B
2899681
CXQ
03/26/2010
Updated Ordering Information
Updated Package Diagram
*C
3302754
CXQ
07/05/2011
Updated template and style to meet current Cypress standards.
Included table of contents.
Added ordering code definitions, acronyms and units of measure.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-13196 Rev. *C
Revised July 5, 2011
Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
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