HD61602R скачать даташит

HD61602R скачать даташит
HD61602/HD61603
(Segment Type LCD Driver)
Description
The HD61602 and the HD61603 are liquid crystal display driver LSIs with a TTL and CMOS compatible
interface. Each of the LSIs can be connected to various microprocessors.
The HD61602 incorporates the power supply circuit for the liquid crystal display driver. Using the
software-controlled liquid crystal driving method, several types of liquid crystals can be connected
according to the applications.
The HD61603 is a liquid crystal display driver LSI only for static drive and has 64 segment outputs that
can display 8 digits per chip.
Features
• Wide-range operating voltage
 Operates in a wide range of supply voltage: 2.2V to 5.5V
 Compatible with TTL interface at 4.5V to 5.5V
• Low current consumption
 Can run from a battery power supply (100 µA max. at 5 V)
 Standby input enables standby operation at lower current consumption (5 µA max. on 5V)
• Internal power supply circuit for liquid crystal display driver (HD61602)
 Internal power supply circuit for liquid crystal display driver facilitates the connection to a
microprocessor system
1230
HD61602/HD61603
Ordering Information
Type No.
Package
HD61602R
80-pin plastic QFP (FP-80)
HD61602RH
80-pin plastic QFP (FP-80A)
HD61603R
80-pin plastic QFP (FP-80)
Versatile Segment Driving Capacity
Type No.
Driving
HD61602
Static
HD61603
Display
Method Segments
51
Example of Use
Frame Freq. (Hz)
at fOSC = 100 kHz
8 segments × 6 digits + 3 marks
33
1/2 bias
1/2 duty 102
8 segments × 12 digits + 6 marks
65
1/3 bias
1/3 duty 153
9 segments × 17 digits
208
1/4 duty 204
8 segments × 25 digits + 4 marks
223
8 segments × 8 digits
33
Static
64
Package
80-pin plastic
QFP (FP-80,
FP-80A,
TFP-80)
80-pin plastic QFP
(FP-80)
1231
HD61602/HD61603
Pin Arrangement
20
45
21
44
22
43
23
42
24
41
65
66
45
21
44
22
43
23
42
24
41
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
READY
VDD
OSC1
OSC2
SYNC
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
79
67
46
20
44
18
43
19
42
20
41
COM0
COM1
COM2
COM3
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
40
45
17
39
46
16
38
47
15
37
48
14
36
49
13
35
50
12
34
51
11
33
52
10
32
53
9
31
54
8
30
55
7
29
56
6
28
57
5
27
4
26
58
25
59
3
24
60
2
23
1
22
68
47
19
COM2
COM3
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
80
69
48
18
(FP-80)
21
70
49
17
HD61602RH
(FP-80A)
(Top view)
1232
71
50
16
(FP-80)
CS
WE
RE
SB
D7
D6
D5
D4
VSS
D3
D2
D1
D0
VREF1
VREF2
VC2
VC1
V1
V2
V3
72
73
74
75
76
77
78
51
15
40
46
52
14
39
19
53
13
38
47
54
12
37
18
55
11
36
48
56
10
35
17
57
9
34
49
58
8
33
16
59
7
32
50
60
6
31
51
15
5
30
14
61
29
52
62
4
28
13
63
3
27
53
64
2
26
12
1
25
54
VDD
READY
CS
WE
RE
SB
D3
D2
D1
D0
VSS
V3
COM0
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
40
11
39
55
38
10
37
56
36
9
35
57
34
58
8
33
59
7
32
60
6
31
5
30
61
29
4
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
79
80
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
62
28
63
3
27
64
2
26
1
25
VDD
READY
CS
WE
RE
SB
D7
D6
D5
D4
VSS
D3
D2
D1
D0
VREF1
VREF2
VC2
VC2
V1
V2
V3
COM0
COM1
OSC1
OSC2
SYNC
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
HD61603R
OSC1
OSC2
SYNC
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
HD61602R
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
HD61602/HD61603
Block Diagram
HD61602
SYNC
LCD driving
timing
generator
OSC
READY
CS
WE
RE
D0–D7
Data
controller
RAM write
timing generator
Data latch
8 bits × 2
Parallel/serial
converter
Common output
(4 lines)
Segment
driver
Segment output
(51 lines)
Common
driver
Common output
Segment
driver
Segment output
(64 lines)
Address
decoder
SB
Mode
setting
latch
Display
data RAM
Common
driver
Operation
mode
LCD driving
voltage generator
V1
V2
V3
Driving voltage
selection
To VDD
HD61603
SYNC
OSC
READY
CS
WE
RE
D0–D3
LCD driving
timing
generator
Data
controller
RAM write
timing generator
Data latch
4 bits × 4
Parallel/serial
converter
SB
Mode
setting
latch
Display
data RAM
Address
decoder
V3
1233
HD61602/HD61603
Terminal Functions
HD61602 Terminal Functions
Terminal
Name
No. of
Lines
Input/Output
VDD
1
Power supply
READY
1
NMOS open
drain output
MCU
While data is being set in the display data RAM
and mode setting latch in the LSI after data
transfer, low is output from the READY terminal
to inhibit the next data input.
There are two modes: one in which low is output
only when both of &6 and 5( are low, and the
other in which low is output regardless of &6 and
5(.
&6
1
Input
MCU
Chip select input. Data can be written only when
this terminal is low.
:(
1
Input
MCU
Write enable input. Input data of D0 to D7 is
latched at the rising edge of :(.
5(
1
Input
MCU
Resets the input data byte counter. After both
&6 and 5(are low, the first data is recognized
as the 1st byte data.
SB
1
Input
MCU
High level input stops LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.
MCU
Data input terminal for 8-bit × 2-byte data.
Connected to Function
Positive power supply.
D0–D7
8
Input
VSS
1
Power supply
VREF1
1
Output
External R
Reference voltage output. Generates LCD
driving voltage.
VREF2
1
Input
External R
Divides the reference voltage of VREF1 with
external R to determine LCD driving voltage.
VREF2 ≈ V1.
VC1, VC2
2
Output
External C
Connection terminals for boosting C of LCD
driving voltage generator. An external C is
connected between VC1 and VC2.
V1, V2, V3
3
Output (Input) External C
LCD driving voltage outputs. An external C is
connected to each terminal.
COM0–COM3 4
Output
LCD
LCD common (backplate) driving output.
SEG0–SEG50 51
Output
LCD
LCD segment driving output.
SYNC
1
Input
MCU
Synchronous input for 2 or more chips
applications. LCD driver timing circuit is reset by
high input. LCD is off.
OSC1
OSC2
2
Input
Output
External R
Attach external R to these terminals for
oscillation. An external clock (100 kHz) can be
input to OSC1.
Negative power supply.
Note: Logic polarity is positive. 1 = high = active.
1234
HD61602/HD61603
HD61603 Terminal Functions
Terminal
Name
No. of
Lines
Input/Output Connected to Function
VDD
1
Power supply
READY
1
NMOS open
drain output
MCU
While data is being set in the display data RAM
and mode setting latch in the LSI after data
transfer, low is output from the READY terminal
to inhibit the next data input.
There are two modes: one in which low is output
only when both of &6 and 5( are low, and the
other in which low is output regardless of &6 and
5(.
&6
1
Input
MCU
Chip select input. Data can be written only when
this terminal is low.
:(
1
Input
MCU
Write enable input. Input data of D0 to D3 is
latched at the rising edge of :(.
5(
1
Input
MCU
Resets the input data byte counter. After both of
and 5( are low, the first data is recognized
as the 1st byte data.
Positive power supply.
&6
SB
1
Input
MCU
High level input stops the LSI operations.
1. Stops oscillation and clock input.
2. Stops LCD driver.
3. Stops writing data into display RAM.
D0–D3
4
Input
MCU
Data input terminal from where 4-bit × 4 data are
input.
VSS
1
Power supply
V3
1
Input
Power supply Power supply input for LCD drive. Voltage
between VDD and V3 is used as driving voltage.
COM0
1
Output
LCD
LCD common (backplate) driving output.
SEG0–SEG63 64
Output
LCD
LCD segment driving output.
SYNC
1
Input
MCU
Synchronous input for 2 or more chips
applications. LCD driver timing circuit is reset by
high input. LCD is off.
OSC1
OSC2
2
Input
Output
External R
Attach external R to these terminals for
oscillation.
An external clock (100 kHz) can be input to
OSC1.
Negative power supply.
Note: Logic polarity is positive. 1 = high = active.
1235
HD61602/HD61603
Display RAM
HD61602 Display RAM
The HD61602 has an internal display RAM shown in Figure 1. Display data is stored in the RAM, or is
read according to the LCD driving timing to display on the LCD. One bit of the RAM corresponds to 1
segment of the LCD. Note that some bits of the RAM cannot be displayed depending on LCD driving
mode.
4 bits
Common address
(COM0–COM3)
Display RAM
51 bits
Segment address (SEG0–SEG50)
Figure 1 Display RAM
1236
HD61602/HD61603
Reading Data from Display RAM: A display RAM segment address corresponds to a segment output.
The data at segment address SEGn is output to segment output SEGn terminal.
A common address corresponds to the output timing of a common output and a segment output. The same
common address data is simultaneously read. The data of display RAM is reproduced on the LCD panel.
When a 7-segment type LCD driver is connected, for example, the correspondence between the display
RAM and the display pattern in each mode is as follows:
1. Static drive
In the static drive, only the column of COM0 of display RAM is output. COM1 to COM3 are not
displayed (Figure 2).
2. 1/2 duty cycle drive
In the 1/2 duty cycle drive, the columns of COM0 and COM1 of display RAM are output in time
sharing. The columns of COM2 and COM3 are not displayed (Figure 3).
LCD connection
a
Display RAM
f
b
COM3
g
e
COM2
c
COM0
d
COM0
SEG12
SEG13
SEG14
SEG15
SEG11
SEG10
SEG9
DP
SEG8
COM1
f
e
d
c
DP
g
b
a
SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
Figure 2 Example of Correspondence between LCD Connection and Display RAM
(Static Drive, HD61602)
LCD connection
a
Display RAM
f
b
g
e
COM3
COM1
COM2
COM0
COM1
a
g
c
b
COM0
f
e
d
DP
SEG4
SEG5
SEG6
SEG7
c
SEG7
DP
SEG6
SEG5
SEG4
d
SEG8
SEG9
Figure 3 Example of Correspondence between LCD Connection and Display RAM
(1/2 Duty Cycle, HD61602)
1237
HD61602/HD61603
3. 1/3 duty cycle drive
In the 1/3 duty cycle drive, the columns of COM0 to COM2 are output in time sharing. No column of
COM3 is displayed.
“Y” cannot be rewritten by display data (input on an 8-segment basis). Please use bit manipulation to
turn on/off the display of “Y” (Figure 4).
4. 1/4 duty cycle drive
In the 1/4 duty cycle drive, all the columns of COM0 to COM3 are displayed (Figure 5).
LCD connection
Display RAM
a
Y
COM3
b
f
COM2
COM2
c
g
e
a
b
COM1
COM1
f
g
c
COM0
COM0
e
d
DP
SEG3
SEG4
SEG5
SEG5
DP
SEG4
SEG3
d
Y
SEG6
Figure 4 Example of Correspondence between LCD Connection and Display RAM
(1/3 Duty Cycle, HD61602)
LCD connection
f
b
g
c
e
COM3
f
a
COM2
g
b
COM1
COM1
e
c
COM0
COM0
d
DP
SEG2
SEG3
COM2
DP
SEG3
SEG2
d
Display RAM
COM3
a
SEG4
Figure 5 Example of Correspondence between LCD Connection and Display RAM
(1/4 Duty Cycle, HD61602)
1238
HD61602/HD61603
Writing Data into Display RAM: Data is written into the display RAM in the following five methods:
1. Bit manipulation
Data is written into any bit of RAM on a bit basis.
2. Static display mode
8-bit data is written on a digit basis according to the 7-segment type LCD pattern of static drive.
3. 1/2 duty cycle display mode
8-bit data is written on a digit basis according to the 7-segment type LCD pattern of 1/2 duty cycle
drive.
4. 1/3 duty cycle display mode
8-bit data is written on a digit basis according to the 7-segment type LCD pattern of 1/3 duty cycle
drive.
5. 1/4 duty cycle display mode
8-bit data is written on a digit basis according to the 7-segment type LCD pattern of 1/4 duty cycle
drive.
The RAM area and the allocation of the segment data for 1-digit display depend on the driving methods
as described in “Reading Data from Display RAM”.
8-bit data is written on a digit basis corresponding to the above duty cycle driving methods. The digits are
allocated as shown Figure 8 (allocation of digits). As the data can be transferred on a digit basis from a
microprocessor, transfer efficiency is improved by allocating the LCD pattern according to the allocation
of each bit data of the digit in the data RAM.
Figure 6 shows the digit address (displayed as Adn) to specify the store address of the transferred 8-bit
data on a digit basis.
Figure 7 shows the correspondence between each segment in an Adn and the 8-bit input data.
When data is transferred on a digit basis 8-bit display data and digit address should be specified as
described above.
However, when the digit address is Ad6 for static, Ad12 for 1/2 duty cycle, or Ad25 for 1/4 duty cycle,
display RAM does not have enough bits for the data.
Thus the extra bits of the input 8-bit data are ignored.
In bit manipulation, any one bit of display RAM can be written. When data is transferred on a bit basis,
1-bit display data, a segment address (6 bits) and a common address (2 bits) should be specified.
1239
HD61602/HD61603
(1) Static
(2) 1/2 duty cycle
display
COM0COM1 COM2
(3) 1/3 duty cycle
display
COM0COM1 COM2
(4) 1/4 duty cycle
display
COM0COM1 COM2 COM3
SEG0
COM0COM1 COM2 COM3
SEG0
SEG0
SEG0
SEG1
SEG1
SEG2
SEG2
SEG2
SEG2
SEG3 Ad0
SEG4
SEG3
SEG3
SEG3
SEG5
SEG5
SEG6
SEG6
SEG6
SEG7
SEG7
SEG7
SEG8
SEG8
SEG8
SEG8
SEG9
SEG9
SEG9
SEG9
SEG10
SEG10
SEG10
SEG11 Ad1
SEG12
SEG11
SEG11
SEG12
SEG12
SEG13
SEG13
SEG13
SEG14
SEG14
SEG14
SEG14
SEG15
SEG15
SEG15
SEG15
SEG16
SEG16
SEG17 Ad2
SEG17
SEG18
SEG18
SEG4
..
.
SEG50 Ad6
SEG50
Ad0
SEG1
Ad0
Ad1
SEG4
Ad2
Ad3
..
.
Ad12
Ad2
SEG5
SEG6
Ad2
Ad3
SEG7
Ad3
Ad4
SEG10
Ad5
SEG11
SEG12
Ad4
Ad6
SEG13
Ad5
SEG16
Ad4
Ad1
SEG4
SEG5
Ad1
Ad0
SEG1
Ad7
SEG16
SEG17
Ad8
SEG17
SEG18
Ad6
..
.
SEG18
..
.
Ad24
SEG50
Ad16
SEG50
Ad25
Figure 6 Allocation of Digit (HD61602)
(1) Static display
(2) 1/2 duty display
COM0
SEG0 Bit
7
COM0 COM1
SEG4n Bit
7
SEG8n+1
6
SEG4n+1
5
SEG8n+2
5
SEG4n+2
SEG8n+3
4
SEG8n+4
3
SEG8n+5
2
SEG8n+6
1
SEG8n+7
Bit
0
(3) 1/3 duty display
SEG4n+3
COM0 COM1 COM2
SEG3n Bit
7
6
6
4
SEG3n+1
5
4
3
3
2
SEG3n+2
2
1
Bit
0
1
Bit
0
(4) 1/4 duty display
COM0 COM1 COM2 COM3
SEG2n Bit
7
SEG2n+1
3
6
2
5
4
1
Bit
0
Figure 7 Bit Assignment in an Adn (HD61602)
1240
HD61602/HD61603
HD61603 Display RAM
The HD61603 has an internal display RAM as shown in Figure 8. Display data is stored in the RAM and
output to the segment output terminal.
Reading Data from Display RAM: Each bit of the display RAM corresponds to an LCD segment. The
data at segment address SEGn is output to segment output SEGn terminal. Figure 9 shows an example of
the correspondence between the display RAM bit and the display pattern when a 7-segment type LCD is
connected.
Writing Data into Display RAM: Data is written into the display RAM in the following two methods:
1. Bit manipulation
Data is written into any bit of RAM on a bit basis.
2. Static display mode
8-bit data is written on a digit basis according to the 7-segment type LCD pattern of static drive.
1 bit
(COM0)
Display RAM
64 bits
Segment address (SEG0–SEG63)
Figure 8 Display RAM (HD61603)
LCD connection
Display RAM
a
f
b
COM0
f
e
d
c
DP
g
b
a
SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
g
SEG11
SEG10
SEG9
COM0
DP
d
SEG8
c
SEG12
SEG13
SEG14
SEG15
e
Figure 9 Example of Correspondence between Display RAM Bit and Display Pattern (HD61603)
1241
HD61602/HD61603
The 8-bit data is written on a digit basis into the digit address (displayed as Adn) shown in Figure 10.
When data is transferred from a microprocessor, four 4-bit data are needed to specify the digit address
and an 8-bit display data. Figure 11 shows the correspondence between each segment in an Adn and the
transferred 8-bit data.
In bit manipulation, any one bit of display RAM can be written. When data is transferred on a bit basis,
1-bit display data and a segment address (6 bits) should be specified.
COM0
SEG0
SEG1
SEG2
SEG3 Ad0
SEG4
SEG5
SEG45
SEG6
SEG46
SEG7
SEG47
SEG8
SEG48
SEG9
SEG49
SEG10
SEG50
SEG11 Ad1 SEG51 Ad6
SEG12
SEG52
SEG13
SEG53
SEG14
SEG54
SEG15
SEG55
SEG16
SEG56
SEG17
SEG57
SEG18
SEG58
SEG19 Ad2 SEG59 Ad7
SEG20
SEG60
SEG21
SEG61
SEG22
SEG62
SEG23
SEG63
SEG24
Figure 10 Allocation of Digits (HD61603)
1242
HD61602/HD61603
COM0
SEG8n
Bit
7
SEG8n+1
6
SEG8n+2
5
SEG8n+3
4
SEG8n+4
3
SEG8n+5
2
SEG8n+6
1
SEG8n+7
Bit
0
Figure 11 Bit Assignment in an Adn (HD61603)
1243
HD61602/HD61603
Operating Modes
HD61602 Operating Modes
The HD61602 has the following operating modes:
1. LCD drive mode
Determines the LCD driving method.
a. Static drive mode
LCD is driven statically.
b. 1/2 duty cycle drive mode
LCD is driven at 1/2 duty cycle and 1/2 bias.
c. 1/3 duty cycle drive mode
LCD is driven at 1/3 duty cycle and 1/3 bias.
d. 1/4 duty cycle drive mode
LCD is driven at 1/4 duty cycle and 1/3 bias.
2. Data display mode
Determines how to write display data into the data RAM.
a. Static display mode
8-bit data is written into the display RAM according to the digit in static drive.
b. 1/2 duty cycle display mode
8-bit data is written into the display RAM according to the digit in 1/2 duty cycle drive.
c. 1/3 duty cycle display mode
8-bit data is written into the display RAM according to the digit in 1/3 duty cycle drive.
d. 1/4 duty cycle display mode
8-bit data is written into the display RAM according to the digit in 1/4 duty cycle drive.
3. READY output mode
Determines the READY output timing.
After a data set is transferred, the data is processed internally. The next data cannot be acknowledged
during the processing period. The READY output reports the period to the MPU. The timing when the
READY is output can be selected from the following two modes:
a. READY is mode always available (Figure 12).
b. READY is mode available by &6 and 5((Figure 13).
4. LCD OFF mode
In this mode, the HD61602 stops driving LCD and turns it off.
5. External driving voltage mode
A mode for using external driving voltage (V1, V2, and V3).
The above 5 modes are specified by mode setting data. The modes are independent of each other and can
be used in any combination. Bit manipulation is independent of data display mode and can be used
regardless of it.
1244
HD61602/HD61603
CS
WE
READY
Data transfer
period
Input inhibit
period
Next data
transfer
Figure 12 READY Output Timing (When It Is Always Available)
CS
WE
RE
READY
Data transfer
period
Input inhibit
period
Next data
transfer
Figure 13 READY Output Timing (When It Is Made Available by &6 and 5()
1245
HD61602/HD61603
HD61603 Operating Modes
The HD61603 has the following modes:
1. READY output mode
Determines the READY output timing.
After a data set is transferred, the data is processed internally. The next data cannot be acknowledged
during the processing period. The READY output reports the period to the MPU. The timing when
READY is output can be selected from the following two modes:
a. READY is always available (Figure 14).
b. READY is mode available by &6 and 5( (Figure 15).
2. LCD OFF mode
In this mode, the HD61603 stops driving the LCD and turns it off.
CS
WE
READY
Data transfer
period
Input inhibit
period
Next data
transfer
Figure 14 READY Output Timing (When It Is Always Available)
CS
WE
RE
READY
Data transfer
period
Input inhibit
period
Next data
transfer
Figure 15 READY Output Timing (When It Is Made Available by &6 and 5()
1246
HD61602/HD61603
Input Data Formats
HD61602 Input Data Formats
Input data is composed of 8 bits × 2. Input them as 2-byte data after READY output changes from low to
high or low pulse is entered into 5( terminal.
1. Display data (updates display on an 8-segment basis)
1st byte
0
0
✕
7
6
5
6
5
Display address
(digit address Adn)
4
3
2
1
0
2
1
0
2nd byte
Display data
7
4
3
a. Display address
Digit address Adn in accordance with display mode
b. Display data
Pattern data that is written into the display RAM according to display mode and the address
2. Bit manipulation data (updates display on a segment basis)
1st byte
0
1
Display
data
✕
✕
✕
7
6
5
4
3
2
5
4
COM
address
1
0
2nd byte
✕
✕
7
6
SEG address
3
2
1
0
a. Display data
Data that is written into 1 bit of the specified display RAM.
b. COM address
Common address of display RAM
c. SEG address
Segment address of display RAM
1247
HD61602/HD61603
3. Mode setting data
External power
supply
1st byte
READY
bit
1
0
✕
0
7
6
5
4
3
2
✕
✕
✕
✕
✕
OFF/ON
bit
7
6
5
4
3
2
Drive mode
bits
1
0
2nd byte
Display
mode bits
1
0
a. Display mode bits
00:
Static display mode
01:
1/2 duty cycle display mode
10:
1/3 duty cycle display mode
11:
1/4 duty cycle display mode
b. OFF/ON bit
1:
LCD off (set to 1 when SYNC is entered)
0:
LCD on
c. Drive mode bits
00:
Static drive
01:
1/2 duty cycle drive
10:
1/3 duty cycle drive
11:
1/4 duty cycle drive
d. READY bit
0:
READY bus mode; READY outputs 0 only while CS and RE are 0. (reset to 0 when
SYNC is entered)
1:
READY port mode; READY outputs 0 regardless of CS and RE.
e. External power supply bit
0:
Driving voltage is generated internally.
1:
Driving voltage is supplied externally. (Set to 1 when SYNC is entered.)
4. 1-byte instruction
1st byte
1
1
✕
✕
✕
✕
✕
✕
7
6
5
4
3
2
1
0
The first data (first byte) is ignored when bit 6 and bit 7 in the byte are 1.
1248
HD61602/HD61603
HD61603 Input Data Formats
Input data is composed of 4 bits × 4. Input them as four 4-bit data after READY output changes from low
to high or low pulse is entered into 5( terminal.
1. Display data (updates display on an 8-segment basis)
1st byte
2nd byte
0
0
✕
✕
✕
3
2
1
0
3
3rd byte
Bit 7
3
Display address
(digit address Adn)
2
1
0
4th byte
Display data
6
5
2
1
4
0
Bit 3
3
Display data
2
1
2
1
0
0
a. Display address
Digit address Adn shown in Figure 10.
b. Display data
Pattern data that is written into the display RAM as shown in Figure 11.
2. Bit manipulation data (updates display on a segment basis)
1st byte
2nd byte
0
1
Display
data
3
2
1
✕
✕
✕
0
0
0
3
2
1
0
3rd byte
4th byte
✕
✕
3
2
SEG address
Bit 5
1
4
0
Bit 3
3
SEG address
2
1
2
1
0
0
a. Display data
Data that is written into 1 bit of the specified display RAM.
b. SEG address
Segment address of display RAM (segment output)
1249
HD61602/HD61603
3. Mode setting data
1st byte
2nd byte
1
0
✕
0
✕
READY
bit
✕
✕
3
2
1
0
3
2
1
0
3rd byte
4th byte
✕
✕
✕
✕
✕
OFF/ON
bit
0
0
3
2
1
0
3
2
1
0
a. OFF/ON bit
1:
LCD off (set to 1 when SYNC is entered.)
0:
LCD on
b. READY bits
0:
READY bus mode; READY outputs 0 only while &6 and 5( are 0. (reset to 0 when
SYNC is entered.)
1:
READY port mode; READY outputs 0 regardless of &6 and 5(.
4. 1-byte instruction
1st byte
1
1
✕
✕
3
2
1
0
The first data (4 bits) is ignored when bit 3 and 2 in the data are 1.
1250
HD61602/HD61603
How to Input Data
How to Input HD61602 Data
Input data is composed of 8 bits × 2. Take care that the data transfer is not interrupted, because the first
8-bit data is distinguished from the second one by the sequence only.
If data transfer is interrupted, or at power on, the following two methods can be used to reset the count of
the number of bytes (count of the first and second bytes):
1. Set &6 and 5( inputs low (no display data changes).
2. Input 2 or more “1-byte instruction” data in which bit 7 and 6 are 1 (display data may change).
The data input method via data input terminals (&6, :(, D0 to D7) is similar to that of static RAM such
as HM6116. An access of the LSI can be made through the same bus line as ROM and RAM. When
output ports of a microprocessor are used for an access, refer to the timing specifications and Figure 16.
Power on
CS
WE
RE
READY
*6
*6
*4
*5
*1
*5
*3
*5
*2
SYNC
SB
D0–D7
1st
2nd
Mode setting data
1st
2nd
Mode setting data
1st
2nd
Display data
Notes: 1. READY output is indefinite during 12 clocks after the oscillation start at power on (clock:
OSC2 clock).
2. High pulse should be applied to SYNC terminal when using two or more chips
synchronously.
3. In the mode in which READY is always available, READY output is in definite while SYNC
is high.
4. Reset the byte counter after power on.
5. READY output period is within 3.5 clocks in the mode setting operation and bit
manipulation or within 10.5 clocks when the display data (8 bits) is updated.
6. Connect a pull-up resister if WE or RE may be floating.
7. It is not always necessary to follow this example.
Figure 16 Example of Data Transfer Sequence
1251
HD61602/HD61603
How to Input HD61603 Data
Input data is composed of 4 bits × 4. Take care that data transfer is not interrupted, because the first 4-bit
data to the fourth 4-bit data are distinguished from each other by the sequence only.
If data transfer is interrupted, or at power on, the following two methods can be used to reset the count of
the number of data (count of the first 4-bit data to the fourth 4-bit data):
1. Set &6and 5( low.
2. Input 4 or more “1-byte instruction” data (4-bit data) in which bit 3 and 2 are 1 (display data may
change).
The data input method via data input terminals (&6, :(, D0 to D3) is similar to that of static RAM such
as HM6116. An access of the LSI can be made through the same bus line as ROM and RAM. When
output ports of a microprocessor are used for an access, refer to the timing specifications and Figure 17.
Power on
CS
WE
RE
*6
*6
*4
READY
*5
*1
*3
*5
*5
*2
SYNC
SB
D0–D3
1st 2nd 3rd
4th
Mode setting data
1st 2nd 3rd 4th
Mode setting data
1st 2nd 3rd
4th
Display data
Notes: 1. READY output is indefinite during 12 clocks after the oscillation start at power on (clock:
OSC2 clock).
2. High pulse should be applied to SYNC terminal when using two or more chips
synchronously.
3. In the mode in which READY is always available, READY output is in definite while SYNC
is high.
4. Reset the 4-bit data counter after power on.
5. READY output period is within 3.5 clocks in the mode setting operation and bit
manipulation or within 10.5 clocks when the display data (8 bits) is updated.
6. Connect a pull-up resister if WE or RE may be floating.
7. It is not always necessary to follow this example.
Figure 17 Example of Data Transfer Sequence
1252
HD61602/HD61603
Notes on READY Output
Note that the READY output will be unsettled during 1.5 clocks (max) after inputting the first 2-byte data
for setting the mode after turning the power on. This is because the READY bit data of mode setting
latches and the mode of READY pin (READY bus or port mode) are unsettled until the completion of
mode setting.
There are two kinds of the READY output waveforms depending of the modes:
1. READY bus mode (READY bit = 0)
2. READY port mode (READY bit = 1)
However, if you input SYNC before mode setting, waveform will be determined; when you choose
READY bus mode, (1) a in Figure 18 will be output, and when you choose READY port mode, (2) a will
be output. The figures can be applied both to HD61602 and HD61603.
Power on
CE
WE
1st
D0–D7
2nd
READY output is unsettled.
Mode setting data
(2-byte data)
1.5 clocks (max)
Mode setting latch is unsettled.
Mode setting data are
latched.
Power on
WE
RE
a
b
READY
Note: CS = low
1.5 clocks (max)
(1) READY Bus Mode
Power on
WE
a
b
READY
Note: CS = low, RE = high
1.5 clocks (max)
3.5 clocks (max)
(2) READY Port Mode
Figure 18 READY Output According to Modes
1253
HD61602/HD61603
Standby Operation
Standby operation with low power consumption can be activated when pin SB is used. Normal operation
of the LSI is activated when pin SB is low level, and the LSI goes into the standby state when pin SB is
high level. The standby state of the LSI is as follows:
1. LCD driver is stopped (LCD is off).
2. Display data and operating mode are held.
3. The operation is suspended while display changes (while READY is outputting low.) In this case,
READY outputs high within 10.5 clocks or 3.5 clocks after release from the standby mode.
4. Oscillation is stopped.
When this mode is not used, connect pin SB to VSS.
Multichip Operation
When an LCD is driven with two or more chips, the driving timing of the LCD must be synchronized. In
this case, the chips are synchronized with each other by using SYNC input. If SYNC input is high, the
LCD driver timing circuit is reset. Apply high pulse to the SYNC input after the operating mode is set.
A high pulse to the SYNC input changes the mode setting data. (The OFF/ON bit is set and the READY
bit is reset. See 3. Mode Setting Data in “Input Data Formats”.) Transfer the mode setting data into the
LSI after every SYNC operation.
If a power on reset signal is applied to the SYNC pin, the LCD can be off-state when the power is turned
on.
When SYNC input is not used, connect pin SYNC to VSS.
When SB input is used, after standby mode is released, a high pulse must be applied to the SYNC input,
and mode setting data must be set again.
Restriction on Usage
Minimize the noise by inserting a noise by-pass capacitor (≥ 1 µF) between VDD and VSS pins. (Insert
one as near chip as possible.)
1254
HD61602/HD61603
Liquid Crystal Display Drive Voltage Circuit (HD61602)
What is LCD Voltage?
HD61602 drives liquid crystal display using four levels of voltages (Figure 19); VDD, V1, V2, and V3
(VDD is the highest and V3 is the lowest). The voltage between VDD and V3 is called VLCD and it is
necessary to apply the appropriate VLCD according to the liquid crystal display. V3 always needs to be
supplied regardless of the display duty ratio since it supplies the voltage to the LCD drive circuit of
HD61602.
VDD
∆V
∆V
∆V
VLCD
V1
V2
V3
Figure 19 LCD Output Waveform and Output Levels
1255
HD61602/HD61603
When Internal Drive Power Supply Is Used
When the internal drive power supply is used, attach C1–C4 for charge pump circuits and variable
resistance R1 for deciding display drive voltage to HD61602 as shown in Figure 20.
Internal voltage is available by setting external voltage switching bits of mode setting data 0.
Figure 21 shows voltage characteristics between VDD and VREF1. Voltage is divided at R1, and then
input into VREF2. Voltage between VDD and VREF2 is equivalent to ÆV in Figure 21, and so VLCD
can be changed by regulating the voltage.
VREF2 is usually regulated by variable resistance, but when replacing R1 with two nonvariable
resistances take VREF1 between max and min into consideration as shown in Figure 21.
Internal drive power supply is generated by using capacitance, and so large current cannot flow. When
large liquid crystal display panel is used, examine the external drive power supply.
C6
Power
1
C5
11
R1
16
17
r1
r2
18
19
C2
20
C3
21
C4
22
23–26
77
LCD
76
75
VDD
VSS
Vref1
Vref2
VC1
Regulator
Voltage follower
+
–
VC2
V1
V2
V3
2 × (V1 – VDD)
3 × (V1 – VDD)
COM
SEG0
HD61602
SEG1
SEG2
R1 = 1 MΩ variable
C1 = 0.3 µF
C2–C4 = 0.3 µF
C5 = 0.1 to 0.3 µF
C6 ≥ 1 µF
Figure 20 Example
1256
Charge
pump
circuit
HD61602/HD61603
When External Drive Power Supply Is Used
An external power supply can be used by setting external voltage switching bits of mode setting data to 1.
When a large liquid crystal display panel is used, in multichip designs, which need accurate liquid crystal
drive voltage, use the external power supply. See Figure 22.
R2–R5 is connected in series between VDD and VSS, and by these resistance ratio each voltage of ÆV
and VLCD is generated and then supplied to V1, V2, and V3. C2–C4 are smoothing capacitors.
When regulating brightness, change the resistance value by setting R5 variable resistance.
VDD–VSS (V)
VDD–Vref1 (V)
2
3
4
5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
6
Min
Typ
Max
Figure 21 Voltage Characteristics between VDD and Vref1
Positive
power
supply
VDD
VSS
C6
R2
NC
NC
C4
Positive
power
supply
VREF1
VREF2
VC1
VC2
V1
V2
V3
VDD
VSS
C6
R2
C2
NC
NC
Positive
power
supply
VREF1
VREF2
VC1
VC2
V1
R2
C2
R3
VDD
VSS
C6
NC
NC
C3
R3
C4
R4
V2
R5
V2
C3
V3
SB
SB
(1) Static Drive
V3
Tr
(2) 1/2 Duty Cycle Drive
C6 ≥ 1 µF
R5
R5
Tr
VREF1
VREF2
VC1
VC2
V1
SB
Tr
(3) 1/3 and 1/4 Duty Cycle Drive
Notes: 1. When standby mode is used, a transistor is required.
2. R2–R5 should be some kΩ–some tens of kΩ, and C2–C4 should be 0.1 µF–0.3 µF.
Figure 22 Example when External Drive Voltage Is Used
1257
HD61602/HD61603
Liquid Crystal Display Drive Voltage (HD61603)
As shown in Figure 23, apply LCD drive voltage from the external power supply.
Oscillation Circuit
When Internal Oscillation Circuit Is Used
When the internal oscillation circuit is used, attach an external resister ROSC as shown in Figure 24. (Insert
ROSC as near chip as possible, and make the OSC1 side shorter.)
When External Clock Is Used
When an external clock of 100 kHz with CMOS level is provided, pin OSC1 can be used for the input
pin. In this case, open pin OSC2.
C6
Positive power
supply
1
VDD
11 VSS
R1
12
V3
R2
SB
Tr
C6 ≥ 1 µF
Note: When standby mode is used, a transistor is required.
Figure 23 Example of Drive Voltage Generator
ROSC
80
79
OSC1 OSC2
ROSC
HD14049UB
80
79
etc.
OSC1 OSC2
NC
80
79
OSC1 OSC2
Multichip operation
Figure 24 Example of Oscillation Circuit
1258
HD61602/HD61603
HD74LS138
+5 V
A13
A14
A15
A
B
C
Address bus
D7–
D0
G
Data bus
Y
D0
E
+5 V
VCC
VSS
HD6809
HD61602
VC1 COM0
to
VC2 COM3 SEG0
CS
HD14049UB
+5 V
VDD
READY
SB
VSS
V1
V2
SYNC
OSC2
VREF1
VREF2
WE
RE
CS
D0–D7
OSC1
VDD
READY
SB
VSS
+5 V
SYNC
WE
R/W
RE
+5 V
BA
D0–D7 OSC1OSC2
VREF1
VREF2
HD61602
V1
V2
VC1
V3
SEG50
VC2
V3
SEG1
SEG50
+5 V
4
CPU
Liquid crystal
Figure 25 Example (1)
HD74LS138
+5 V
A13
A14
A15
A
B
C
Address bus
D3–
D0
Data bus
G
Y
D0
E
VCC
VSS
SEG63
SEG0
OSC2
D0–D3
OSC1
VDD
READY
SB
VSS
SYNC
CS
+5 V
WE
RE
OSC2
HD14049UB
V3
HD61603
COM0 SEG0
HD6809
D0–D3
OSC1
SYNC
VDD
READY
SB
VSS
CS
WE
R/W
RE
+5 V
BA
V3
HD61603
SEG63
+5 V
CPU
Liquid crystal
Figure 26 Example (2)
1259
HD61602/HD61603
Absolute Maximum Ratings
Item
Symbol
Limit
Unit
Power supply voltage*
VDD, V1, V2, V3
–0.3 to +7.0
V
Terminal voltage*
VT
–0.3 to VDD +0.3
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
* Value referenced to VSS = 0V.
Note: If LSIs are used above absolute maximum ratings, they may be permanently destroyed. Using
them within electrical characteristics limits is strongly recommended for normal operation. Use
beyond these conditions will cause malfunction and poor reliability.
Recommended Operating Conditions
Limit
Item
Symbol
Min
Typ
Max
Unit
Power supply voltage
VDD
2.2
—
5.5
V
V1, V2, V3
0
—
VDD
V
Terminal voltage*
VT
0
—
VDD
V
Operating temperature
Topr
–20
—
75
°C
* Value referenced to VSS = 0V.
1260
HD61602/HD61603
Electrical Characteristics
DC Characteristics (1) (VSS = 0V, VDD = 4.5 to 5.5V, Ta = –20 to +75°C, unless otherwise noted)
Limit
Item
Max
Unit
0.8 VDD —
VDD
V
VIH2
2.0
—
VDD
V
OSC1
VIL1
0
—
0.2 VDD V
Others
VIL2
0
—
0.8
V
Output leakage
current
READY
IOH
—
—
5
µA
V0 = VDD
Output low voltage
READY
VOL
—
—
0.4
V
IOL = 0.4 mA
Input leakage
current*1
Input terminal
IIL1
–1.0
—
1.0
µA
VIN = 0–VDD
V1
IIL2
–20
—
20
µA
VIN = VDD–V3
V2, V3
IIL3
–5.0
—
5.0
µA
COM0–COM3
Vd1
—
—
0.3
V
±Id = 3 µA for each
COM, V3 = VDD–3V
SEG0–SEG50
Vd2
—
—
0.6
V
±Id = 3 µA for each
SEG, V3 = VDD–3V
IDD
—
—
100
µA
During display*
ROSC = 360 kΩ
IDD
—
—
5
µA
At standby
VTR
—
—
0.4
V
VREF2 = VDD–1 V,
C1–C4 = 0.3 µF,
RL = 3 MΩ
Input high voltage
Input low voltage
LCD driver voltage
drop
Symbol
Min
OSC1
VIH1
Others
Power supply
current
Internal driving
voltage drop
V1, V2, V3
Typ
Test Condition
2
Notes: 1. V1, V2: apply only to HD61602.
2. Except the transfer operation of display data and bit data.
1261
HD61602/HD61603
DC Characteristics (2) (VSS = 0V, VDD = 2.2 to 3.8V, Ta = –20 to +75°C, unless otherwise noted)
Limit
Item
Symbol
Min
Input high voltage
VIH
Input low voltage
Typ
Max
Unit
0.8 VDD —
VDD
V
VIL
0
—
0.1 VDD V
Output leakage
current
READY
IOH
—
—
5
Output low voltage
READY
VOL
—
—
0.1 VDD V
IOL = 0.04 mA
Input leakage
current*1
Input terminal
IIL1
–1.0
0
1.0
µA
VIN = 0–VDD
V1
IIL2
–20
—
20
µA
VIN = VDD–V3
V2, V3
IIL3
–5.0
—
5.0
µA
COM0–COM3
Vd1
—
—
0.3
V
±Id = 3 µA for each
COM, V3 = VDD–3V
SEG0–SEG50
Vd2
—
—
0.6
V
±Id = 3 µA for each
SEG, V3 = VDD–3V
ISS
—
—
50
µA
During display*
ROSC = 330 kΩ
ISS
—
—
5
µA
At standby
VTR
—
—
0.4
V
VREF2 = VDD–1V,
C1–C4 = 0.3 µF,
RL = 3 MΩ,
VDD = 3–3.8 V
LCD driver voltage
drop
Power supply
current
Internal driving
voltage drop
V1, V2, V3
Notes: 1. V1, V2: apply only to HD61602.
2. Except the transfer operation of display data and bit data.
1262
µA
Test Condition
VIN = VDD
2
HD61602/HD61603
AC Characteristics (1) (VSS = 0V, VDD = 4.5 to 5.5V, Ta = –20 to +75°C, unless otherwise noted)
Limit
Item
Symbol Min
Typ
Max
Unit
Test Condition
OSC2
fosc
70
100
130
kHz
Rosc = 360 kΩ
External clock frequency OSC1
fosc
70
100
130
kHz
External clock duty
Duty
40
50
60
%
tS
400
—
—
ns
tH
10
—
—
ns
tWH
300
—
—
ns
tWL
400
—
—
ns
tWR
400
—
—
ns
tDL
—
—
1.0
µs
tEN
400
—
—
ns
tOP1
9.5
—
10.5
Clock For display data
transfer
tOP2
2.5
—
3.5
Clock For bit and mode
data transfer
tr, tf
—
—
25
ns
Oscillation frequency
OSC1
I/O signal timing
Input signal rise time and fall time
Figure 31
1263
HD61602/HD61603
AC Characteristics (2) (VSS = 0V, VDD = 2.2 to 3.8V, Ta = –20 to +75°C, unless otherwise noted)
Limit
Item
Symbol
Min
Typ
Max
Unit
Test Condition
OSC2
fosc
70
100
130
kHz
Rosc = 330 kΩ
External clock frequency OSC1
fosc
70
100
130
kHz
External clock duty
Duty
40
50
60
%
tS
1.5
—
—
µs
tH
1.0
—
—
µs
tWH
1.5
—
—
µs
tWL
1.5
—
—
µs
tDL
—
—
2.0
µs
tWR
1.5
—
—
µs
tEN
2.0
—
—
µs
tOP1
9.5
—
10.5
Clock For display data
transfer
tOP2
2.5
—
3.5
Clock For bit and mode
data transfer
tr, tf
—
—
25
ns
Oscillation frequency
OSC1
I/O signal timing
(VDD = 3.0–3.8 V)
Input signal rise time and fall time
1264
Figure 32
HD61602/HD61603
CS
VIL
tWH
WE
VIH
VIL
VIL
VIH
tWH
VIH
VIH
VIL
D0–D7
VIL
tS
tH
Figure 27 Write Timing (5( Is Fixed at High Level, and SYNC at Low Level)
WE
VIH
VIL
tEN
tEN
VIH
RE
VIL
tWR
READY
VOL
VIH
VIL
tDL
VOH
tDL
Figure 28 Reset/Read Timing (&6 and SYNC Are Fixed at Low Level)
WE
VIH
VIL
tEN
tDL
READY
VOH
VOL
tOP1, tOP2
Figure 29 READY Timing (When the READY Output Is Always Available)
1265
HD61602/HD61603
READY
VOH
VOH
tEN
SYNC
tWH
VIH
VIL
Within
1 clock
VIH
Figure 30 SYNC Timing
VDD
47 kΩ
Measurement
terminal
(READY)
30 pF
10 kΩ
120 kΩ
1S2074H
VSS
Figure 31 Bus Timing Load Circuit (LS-TTL Load)
VDD
470 kΩ
Measurement
terminal
(READY)
30 pF
VSS
Figure 32 Bus Timing Load Circuit (CMOS Load)
1266
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