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INTEGRATED CIRCUITS

DATA SHEET

TEA1211HN

High efficiency auto-up/down

DC/DC converter

Preliminary specification

Supersedes data of 2003 Aug 06

2003 Oct 13

Philips Semiconductors

High efficiency auto-up/down

DC/DC converter

CONTENTS

3

4

1

2

5

6

7

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.12.1

7.12.2

7.12.3

7.1

7.2

7.2.1

7.2.2

7.2.3

7.3

7.4

7.5

7.12.4

7.13

7.13.1

7.13.2

7.13.3

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

Introduction

Control mechanism

PWM

PFM

Switching sequence

Adjustable output voltage

Start-up

Under voltage lockout

Shut-down

Power switches

Synchronous rectification

PWM-only mode

External synchronisation

Current limiter

I

2

C-bus serial interface

Characteristics of the I

2

C-bus

START and STOP conditions

Bit transfer

Acknowledge

I

2

C-bus protocol

Addressing

Data

Write Cycle

Preliminary specification

TEA1211HN

14

15

16

17

8

9

10

11

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

12

13

13.1

13.2

13.3

13.4

13.5

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

APPLICATION INFORMATION

Typical Li-Ion, 2- or 3-cell application with

I

2

C-bus programming

Component selection

Inductor

Capacitors

Schottky diodes

Feedback resistors

Current Limiter

PACKAGE OUTLINE

SOLDERING

Introduction to soldering surface mount packages

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for wave and reflow soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I

2

C COMPONENTS

2003 Oct 13 2

Philips Semiconductors


DC/DC converter


TEA1211HN

1 FEATURES

•

I

2

C-bus programmable output voltage range of

1.5 V to 5.5 V

•

Single inductor topology

•

High efficiency up to 94 % over wide load range

•

Wide input range; functional from 2.55 V up to 5.5 V

•

1.7 A maximum input and output current

•

•

•

•

•

•

2

Low quiescent power consumption

600 kHz switching frequency

•

Four integrated very low R

DS(on)

power MOSFETs

•

Synchronizable to external clock

•

Externally adjustable current limit for protection and efficient battery use in case of dynamic loads

Under voltage lockout

PWM-only option

Shut-down current less than 1

32-pin small body HVQFN package.

APPLICATIONS

µ

A

•

Stable output voltage from Lithium-Ion batteries

•

Variable voltage source for PAs (Power Amplifiers) in cellular phones

•

Wireless handsets

•

Hand-held instruments

•

Portable computers.

3 GENERAL DESCRIPTION

The TEA1211HN is a fully integrated auto-up/down

DC/DC converter circuit with I

2

C-bus interface. Efficient, compact and dynamic power conversion is achieved using a digitally controlled pulse width and frequency modulation like control concept, four integrated low R

DS(on)

power switches with low parasitic capacitances and fully synchronous rectification.

The combination of auto-up/down DC/DC conversion, high efficiency and low switching noise makes the TEA1211HN well suited to supply a power amplifier in a cellular phone.

The output voltage can be I

2

C-bus programmed to the exact voltage needed to achieve a certain output power level with optimal system efficiency, thus enlarging battery lifetime.

The TEA1211HN operates at 600 kHz switching frequency which enables the use of small size external components.

The switching frequency can be locked to an external high frequency clock. Deadlock is prevented by an on-chip under voltage lockout circuit. An adjustable current limit enables efficient battery use even at high dynamic loads.

Optionally, the device can be kept in pulse width modulation mode regardless of the load applied.

4 ORDERING INFORMATION

TYPE

NUMBER

TEA1211HN

PACKAGE

NAME DESCRIPTION

HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5

×

5

×

0.85 mm

VERSION

SOT617-3

2003 Oct 13 3



DC/DC converter


TEA1211HN

5 BLOCK DIAGRAM

n.c.

handbook, full pagewidth

2, 31, 32

6, 8, 17, 19

TEA1211HN

IN

P-type power FET

P-down

LXA

1, 3, 4,

10, 11

LXB

14, 15, 21, 22, 24

P-type power FET

P-up

23, 25, 26

OUT

INTERNAL

SUPPLY sense FET

N-down

N-type power FETs

N-up

TEMPERATURE

PROTECTION

DIGITAL

CONTROLLER

13 MHz

OSCILLATOR

Window comparator

CLOCK

SELECTOR I

2

C-BUS INTERFACE

Current limit comparator

29 28

SYNC/PWM SHDWN

12

SCL

13

SDA

30

ILIM

5, 7, 9, 16, 18, 20

GND

Fig.1 Block diagram.

BANDGAP

REFERENCE

27

FB

MDB001

6 PINNING

SYMBOL

LXA

IN

LXA

LXA

GND n.c.

GND n.c.

GND

LXA

LXA

SCL

SDA

LXB

LXB

GND

PIN DESCRIPTION

1

2

3 inductor connection 1 input voltage inductor connection 1

6

7

4

5 inductor connection 1 ground not connected ground

8

9 not connected ground

10 inductor connection 1


12 serial clock input line I

2

C-bus

13 serial data input/output line

I

2

C-bus



16 ground

2003 Oct 13 4

SYMBOL

n.c.

GND n.c.

GND

LXB

LXB

OUT

LXB

OUT

OUT

FB

SHDWN

SYNC/PWM

ILIM

IN

IN

PIN DESCRIPTION

17 not connected

18 ground

19 not connected

20 ground



23 output voltage


25 output voltage

26 output voltage

27 feedback input

28 shut-down input

29 synchronization clock input,

PWM-only input

30 current limit resistor connection

31 input voltage

32 input voltage



DC/DC converter handbook, halfpage n.c.

8

GND

7 n.c.

6

GND 5

LXA 4

LXA 3

IN 2

LXA 1

TEA1211HN

17 n.c.

18

GND

19 n.c.

20 GND

21 LXB

22 LXB

23 OUT

24 LXB

MDB002


TEA1211HN

This diagram is a bottom side view.

Pin 1 is indicated with a dot on the top side of the package.

For mechanical details of HVQFN32 package, see Chapter 12.

Fig.2 Pin configuration.

7 FUNCTIONAL DESCRIPTION

7.1

Introduction

The TEA1211HN is able to operate in Pulse Frequency

Modulation (PFM) or discontinuous conduction mode as well as in Pulse Width Modulation (PWM) or continuous conduction mode. All switching actions are completely determined by a digital control circuit which uses the output voltage level as control input. This digital approach enables the use of a new pulse width and frequency modulation scheme, which ensures optimum power efficiency over the complete range of operation of the converter.

7.2

Control mechanism

Depending on load current I load

and V

IN

to V

OUT

ratio, the controller chooses a mode of operation. When high output power is requested, the device will operate in PWM

(continuous conduction) mode, which is a 2-phase cycle in up- as well as in down mode. For small load currents the controller will switch over to PFM (discontinuous mode), which is either a 3- or 4-phase cycle depending on the input to output ratio, see Fig.3.

handbook, halfpage

Icoil

0

Fig.3

VIN

>

VOUT down mode

VIN

=

VOUT stationary mode

PWM

PFM

VIN

<

VOUT up mode

MDB003

Waveform of coil current as function of I and V

IN

to V

OUT

ratio.

load

2003 Oct 13 5



DC/DC converter


TEA1211HN

7.2.1

PWM

PWM results in minimum AC currents in the circuit components and hence optimum efficiency, cost and

EMC. In this mode the output voltage is allowed to vary between two predefined voltage levels. When the output voltage stays within this so called window, switching continues in a fixed pattern. When the output voltage reaches one of the window borders, the digital controller immediately reacts by adjusting the duty cycle and inserting a current step in such a way that the output voltage stays within the window with higher or lower current capability. This approach enables very fast reaction to load variations.

Figure 4 shows the TEA1211HN’s response to a sudden load increase in case of up conversion. The upper trace shows the output voltage. The ripple on top of the DC level is a result of the current in the output capacitor, which changes in sign twice per cycle, multiplied by the capacitor’s internal Equivalent Series Resistance (ESR).

After each ramp-down of the inductor current, or when the

ESR effect increases the output voltage, the TEA1211HN determines what to do in the next cycle. As soon as more load current is taken from the output the output voltage starts to decay. When the output voltage becomes lower than the low limit of the window, corrective action is taken by a ramp-up of the inductor current during a much longer time. As a result, the DC current level is increased and normal PWM control can continue. The output voltage

(including ESR effect) is again within the predefined window.

Figure 5 depicts the spread of the output voltage window.

The absolute value is most dependent on spread, while the actual window size is not affected. For one specific device, the output voltage will not vary more than 2 % typically.

7.2.2

PFM

In low output power situations, TEA1211HN will switch over to PFM mode operation in case PWM-only mode is not activated. In this mode charge is transferred from battery to output in single pulses with a wait phase in between. Regulation information from earlier PWM mode operation is used. This results in optimum inductor peak current levels in PFM mode, which are slightly larger than the inductor ripple current in PWM mode. As a result, the transition between PFM and PWM mode is optimal under all circumstances. In PFM mode, the TEA1211HN regulates the output voltage to the limits shown in Fig.5.

Depending on the V

IN

to V

OUT

ratio the TEA1211HN decides for a 3- or 4-phase cycle, where the last phase is the wait phase. When the input voltage almost equals the output voltage, one of the slopes of a 3-phase cycle becomes weak. Then the charge, or the integral of its pulse, is near to zero and no charge is transferred. In this region the 4-phase cycle is used, (see Fig.3).

load increase start corrective action handbook, full pagewidth

VOUT high window limit low window limit time

Iload time

Fig.4 Response to load increase in up-mode.

MDB004

2003 Oct 13 6



DC/DC converter


TEA1211HN handbook, full pagewidth

VOUT (typ.)

2%

Vh

Vl maximum positive spread of VFB

Vh

2%

+

4%

Vl upper specification limit typical situation

−

4%

Vh

2%

Vl maximum negative spread of VFB lower specification limit

MDB005

V h

= High window limit

V l

= Low window limit

Fig.5 Spread of location of output voltage window.

7.2.3

S

WITCHING SEQUENCE

Refer to Figures 1 and 3. In up-mode the cycle starts by making P-down and N-up conducting in the first phase.

The second phase N-up opens and P-up starts conducting. In down-mode the cycle starts with in the first phase P-up and P-down conducting. The second phase

P-down opens and N-down starts conducting. In PFM these two phases are followed by a third or wait phase that opens all switches except for N-down, which is closed to prevent the coil from floating.

The stationary mode or 4-phase cycle, which only occurs in PFM, starts with in the first phase P-down and N-up conducting. In the second phase P-down and P-up conduct forming a short-cut from battery to output capacitor. In the third phase P-up and N-down conduct.

The fourth or wait-phase again opens all switches except for N-down which is closed to prevent the coil from floating.

7.4

Start-up

If the input voltage exceeds the start voltage, the

TEA1211HN starts ramping up the voltage at the output capacitor. Ramping stops when the target level, set by the external resistors, is reached.

7.5

Under voltage lockout

As a result of too high load or disconnection of the input power source, the input voltage can drop too low to guarantee normal regulation. In that case, the device switches to a shut-down mode stopping the switching completely. Start-up is possible by crossing the start-up level again.

7.6

Shut-down

When pin SHDWN is made HIGH, the converter disables all switches except for N-down (see Fig.1) and power consumption is reduced to a few

µ

A. N-down is kept conducting to prevent the coil from floating.

7.3

Adjustable output voltage

The output voltage of the TEA1211HN can be set to a fixed value by means of an external resistive divider. After start-up through this divider, dynamic control of the output voltage is made possible by use of an I

2

C-bus. The output voltage can be programmed from 1.5 V to 5.5 V in

40 steps of 0.1 V each. In case of Power Amplifiers (PAs) for example the output voltage of the TEA1211HN can be adjusted to the output power to be transmitted by the PA, in order to obtain maximum system efficiency.

7.7

Power switches

The power switches in the IC are two N-type and two

P-type MOSFETs, having a typical pin-to-pin resistance of

85 m

Ω

. The maximum continuous input/output current in the switches is 1.7 A at 70

°

C ambient temperature.

2003 Oct 13 7



DC/DC converter


TEA1211HN

7.8

Synchronous rectification

For optimal efficiency over the whole load range, synchronous rectifiers inside the TEA1211HN ensure that in PFM mode during the phase where the coil current is decreasing, all inductor current will flow through the low ohmic power MOSFETs. Special circuitry is included which detects that the inductor current reaches zero.

Following this detection, the digital controller switches off the power MOSFET and proceeds regulation. Negative currents are thus prevented.

7.9

PWM-only mode

When pin SYNC/PWM is HIGH, the TEA1211HN will use

PWM regulation independent of the load applied. As a result, the switching frequency does not vary over the whole load range.

7.10

External synchronisation

If a high frequency clock is applied to pin SYNC/PWM, the switching frequency in PWM mode will be exactly that frequency divided by 22. PFM mode is not possible if an external clock is applied. The quiescent current of the device increases when an external clock is applied.

In case no external synchronisation is necessary and the

PWM-only option is not used, pin SYNC/PWM must be connected to ground.

7.11

Current limiter

If the peak input current of the TEA1211HN exceeds its limit in PWM mode, current ramping is stopped immediately, and the next switching phase is entered. The current limitation protects the IC against overload conditions, inductor saturation, etc. The current limit level is user defined by the external resistor which must be connected between pin ILIM and pin GND.

7.12

I

2

C-bus serial interface

The serial interface of the TEA1211HN is the I

2

C-bus.

A detailed description of the I

2

C-bus specification, including applications, is given in the brochure: “The

I

2

C-bus and how to use it”, order no. 9398 393 40011.

7.12.1

C

HARACTERISTICS OF THE

I

2

C-

BUS

The I

2

C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a

Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor (for best efficiency it is advised to use the input voltage of the convertor). Data transfer may be initiated only when the bus is not busy. In bus configurations with

ICs on different supply voltages, the pull-up resistors shall be connected to the highest supply voltage. The I

2

C-bus supports incremental addressing. This enables the system controller to read or write multiple registers in only one

I

2

C-bus action. The TEA1211HN supports the I

2

C-bus up to 400 kbit/s.

The I

2

C-bus system configuration is shown in Fig.6.

A device generating a message is a transmitter, a device receiving a message is a receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The TEA1211HN is a slave only device.

SCL

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

MDB006

Fig.6 I

2

C-bus system configuration.

2003 Oct 13 8



DC/DC converter


TEA1211HN

7.12.2

START

AND

STOP

CONDITIONS

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Fig.7).


SDA

SCL

S

START condition

SDA

SCL

P

STOP condition

MDB007

Fig.7 START and STOP conditions on the I

2

C-bus.

7.12.3

B

IT TRANSFER

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.8).


SDA

SCL data line stable; data valid change of data allowed

Fig.8 Bit transfer on the I

2

C-bus.

MDB008

7.12.4

A

CKNOWLEDGE

The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited.

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the receiver generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter (see Fig.9).

The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered).

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

2003 Oct 13 9



DC/DC converter



DATA OUTPUT

BY SLAVE

TRANSMITTER

DATA OUTPUT

BY SLAVE

RECEIVER

SCL FROM

MASTER

TRANSMITTER

S

START condition

1 2 not acknowledge acknowledge

8 9 clock pulse for acknowledgement

MDB009

Fig.9 Acknowledge on the I

2

C-bus.

7.12.5

I

2

C-

BUS PROTOCOL

7.12.5.1

Addressing

Before any data is transmitted on the I

2

C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The (slave) address of the TEA1211HN is

0001 0000 (10h). The subaddress (or word address) is 0000 0000 (00h).

The TEA1211HN acts as a slave receiver only. Therefore the clock signal SCL is only an input signal. The data signal

SDA is a bidirectional line, enabling the TEA1211HN to send an acknowledge.

7.12.5.2

Data

The data consists of one byte, addressing the 40 voltage steps as explained in Tables 1 and 2.

Table 1

Data byte

SUBADDRESS

00h

BIT 7

0

BIT 6

0

BIT 5

CVLVL5

BIT 4

CVLVL4

BIT 3

CVLVL3

BIT 2

CVLVL2

BIT 2

CVLVL1

BIT 0

CVLVL0

Table 2

Translation data byte to voltage level

SUBADDRESS

00h

NAME

CVLVL

SIZE

(BIT)

6

STEP NUMBER

MIN.

0

MAX.

40

MIN. (V)

1.5

STEP

(V)

0.1

MAX. (V)

5.5

2003 Oct 13 10



DC/DC converter


TEA1211HN

7.12.5.3

Write Cycle

The I

2

C-bus configuration for the different TEA1211HN write cycles is shown in Fig.10. The word address is an eight bit value that defines which register is to be accessed next.


S

acknowledgement from slave

SLAVE ADDRESS

R/W

0 A acknowledgement

WORD ADDRESS from slave

A DATA acknowledgement from slave

A

P

n bytes auto increment memory word address

MDB010

S = START condition.

P = STOP condition.

Fig.10 Master transmits to slave receiver (write mode).

8 LIMITING VALUES

V

P

T j

T

V n tot

SYMBOL

T amb stg esd

PARAMETER

voltage on any pin with respect to GND total internal power dissipation junction temperature ambient temperature storage temperature electrostatic discharge voltage pins LXA

CONDITIONS

shut-down mode operational mode

MIN.

−

0.5

−

0.5

−

−

40

−

40

−

40 all other pins note 1 note 2

JEDEC Class II; note 1

JEDEC Class II; note 2

−

−

−

−

Notes

1. Human Body Model: equivalent to discharging a 100 pF capacitor via a 1.5 k

Ω

resistor.

2. Machine Model: equivalent to discharging a 200 pF capacitor via a 0.75

µ

H series inductor.

MAX.

+6.0

+5.5

1000

+150

+85

+125

±

800

±

200

±

2000

±

200

V

V

V

V

UNIT

V

V mW

°

C

°

C

°

C

9 THERMAL CHARACTERISTICS

SYMBOL

R th(j-a)

PARAMETER

thermal resistance from junction to ambient

CONDITIONS

mounted on dedicated PCB in free air

VALUE

35

UNIT

K/W

2003 Oct 13 11



DC/DC converter


TEA1211HN

10 CHARACTERISTICS

T amb

=

−

40 to +85

°

C; all voltages with respect to ground; positive currents flow into the IC; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN.

TYP.

MAX.

UNIT

Voltage levels

V

V

OUT

IN(start) output voltage start voltage V

OUT

I load

= 3.5 V;

< 100 mA

V

V

V

V

IN

IN(uvlo)

FB

OUT(wdw) input voltage under voltage lockout level feedback voltage level output voltage window as percentage of V

OUT

PWM mode

Current levels

I

I q

I shdwn

∆

I lim max quiescent current current in shut-down mode current limit deviation maximum continuous input/output current

Power MOSFETs; note 2

R

DS(on)(N)

R

DS(on)(P)

R

DS(on)(P-up)

I no load lim

= 1 A; note 1

T amb

< 70

°

C pin-to-pin resistance NFETs V

IN

= 3.5 V pin-to-pin resistance PFETs V

IN

= 3.5 V pin-to-pin resistance P-up

FET between pins LXB and

OUT

V

OUT

= 1.5 V f f

Timing

sw sync switching frequency synchronization input frequency

PWM mode

Digital levels: pins SYNC/PWM, SHDWN, SCL and SDA

V

V

IL

IH

Temperature

LOW-level input voltage

HIGH-level input voltage note 3

T amb

T max ambient temperature internal cut-off temperature

1.50

2.45

V

−

1.20

1.5

−

−

−

30

−

−

−

−

450

4.5

0

−

IN(start)

0.6

×

V

40

120

IN

−

2.55

−

V

IN(start)

−

0.15

−

1.25

2.0

100

< 1

−

−

65

65

100

600

13

−

−

+25

135

5.50

2.65

5.50

1.30

3.0

−

2

+30

1.7

85

85

135

750

20

0.4

V

IN

+85

150

V

V

V

V

V

%

µ

A

µ

A

%

A m

V

+ 0.3

V

Ω m

Ω m

Ω kHz

MHz

°

°

C

C

Notes

1. Current limit level is defined by the external R lim

resistor, see Chapter 11.

2. Measured at T amb

= 25

°

C.

3. To avoid additional supply current, it is advised to use HIGH levels not lower than V

IN

−

0.5 V.

2003 Oct 13 12



DC/DC converter

11 APPLICATION INFORMATION

11.1

Typical Li-Ion, 2- or 3-cell application with I

2

C-bus programming



VIN =

2.55 to 5.5 V battery

L1

10

µ

H

D1 D2

LXA LXB

IN

2

1

31

32

3 4 10 11

TEA1211HN

14 15 21 22 24

26

25

23

OUT

VOUT = 3.3 V

R1

120 k

Ω

COUT

100

µ

F

CIN

100

µ

F

27

FB

12 13 29 28

ILIM

30 5 7 9 16 18 20

GND

SCL SYNC/

PWM

Rlim

1 k

Ω

SDA SHDWN

R2

75 k

Ω

MDB011

The combination of the feedback resistors R1 and R2 in parallel should be approximately 50 k

Ω

.

D1 and D2 are Schottky diodes

The battery can be a one cell Li-Ion, two cell Alkaline or three cell NiCd/NiMH/Alkaline.

If the I

2

C-bus interface is used for programming the output voltage, the SCL and SDA lines must be connected to a positive supply via pull-up resistors

(see Section 7.12.1). If the I

2

C-bus interface is not used, connect pins SCL and SDA to ground.

Note the V

IH

-level (see Chapter 10).

Pins should never be left open-circuit.

No external clock is applied.

Fig.11 The TEA1211HN in a typical auto-up/down converter application.

2003 Oct 13 13



DC/DC converter


TEA1211HN

MDB013

100 handbook, full pagewidth

(1)

η

(

%

)

(2)

(3)

80

(4)

(5)

60

40

20

0

1

V

OUT

= 3.3 V.

L1 = 10

µ

H, TDK SLF7032 series.

(1) V

IN

= 2.7 V.

(2) V

IN

= 3.3 V.

(3) V

IN

= 3.6 V.

(4) V

IN

= 4.2 V

(5) V

IN

= 4.5 V.

10 100

Fig.12 Efficiency as a function of load current.

Iload (mA)

1000

2003 Oct 13 14



DC/DC converter


TEA1211HN

(4)

(5)

MDB012

100 handbook, full pagewidth

(1)

η

(

%

)

(2)

(3)

80

60

40

20

0

2.50

V

OUT

= 3.3 V.

L1 = 10

µ

H, TDK SLF7032 series.

(1) I

OUT

= 1000 mA.

(2) I

OUT

= 500 mA.

(3) I

OUT

= 100 mA.

(4) I

OUT

= 10 mA.

(5) I

OUT

= 1 mA.

3.00

3.50

Fig.13 Efficiency as a function of input voltage.

4.00

VIN (V)

4.50

2003 Oct 13 15



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TEA1211HN

11.2

Component selection

11.2.1

I

NDUCTOR

The inductor should have a low Equivalent Series Resistance (ESR) to reduce losses and the inductor must be able to handle the peak currents without saturating.

Table 3

Inductor selection information

COMPONENT

L1

L1

6.8

µ

H

10

µ

H

VALUE TYPE

DO3316-682

SLF7032T-100M1R4

Coilcraft

TDK

SUPPLIER

11.2.2

C

APACITORS

For the output capacitor the ESR is critical. The output voltage ripple is determined by the product of the current through the output capacitor and its ESR. The lower the ESR, the smaller the ripple. However, an ESR less than 80 m

Ω could result in unstable operation.

Table 4

Input and output capacitor selection information

C

IN

COMPONENT

, C

OUT

VALUE

100

µ

F/10 V

TYPE

TPS-series

594D-series

AVX

SUPPLIER

Vishay/Sprague

If the I

2

C-bus interface is used to program the output voltage, use a larger input capacitor to prevent the under voltage lockout level being triggered by large current peaks drawn from this capacitor.

Table 5

Input capacitor selection information, when I

2

C-bus is used

C

IN

(I

2

COMPONENT

C-bus used)

VALUE

220 to 470

µ

F/10 V

TYPE

TPS-series

594D-series

AVX

SUPPLIER

Vishay/Sprague

11.2.3

S

CHOTTKY DIODES

The Schottky diodes provide a lower voltage drop during the break-before-make time of the internal power FETs. It is advised to use Schottky diodes with fast recovery times.

Table 6

Schottky selection information

COMPONENT

D1, D2 PRLL5819

TYPE

Philips

SUPPLIER

2003 Oct 13 16



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11.2.4

F

EEDBACK RESISTORS

The fixed output voltage can be set with the feedback resistors R1 and R2 (see Fig.11). Even in case I

2

C-bus is used for programming the output voltage, these external resistors are required for start-up. The ratio of the resistors can be calculated by:

R1

-------

R2

=

V

-------------

1

V ref

–

, with V ref

= V

FB

(see Chapter 10).

The two resistors in parallel should have a value of approximately 50 k

Ω

:

R1

+

R2

≈

1

----------------

50 k

Ω

11.2.5

C

URRENT

L

IMITER

The maximum input peak current can be set by the current limiter as follows:

R lim

=

I

IN(peak)(max)

Ω

Remark. The output current is not limited: in down conversion, the output current will be higher than the input current, but the maximum continuous output current is not allowed to exceed 1.7 A (RMS) at 70

°

C.

Table 7

Resistor selection information

R1, R2

R lim

COMPONENT VALUE

V

OUT

dependent

I lim

dependent

SMD

SMD

TYPE

1 %

1 %

TOLERANCE

2003 Oct 13 17



DC/DC converter

12 PACKAGE OUTLINE

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

D

B

A terminal 1 index area

E

A

A1


TEA1211HN

SOT617-3

c detail X

L

8

9

e e1

1/2

e b

16

17

e v

M w

M

C

C

A B y1 C

C y

Eh

1/2

e e2 terminal 1 index area

1

32 25

24

Dh

0

Eh

3.75

3.45

2.5

scale

DIMENSIONS (mm are the original dimensions)

UNIT

A

(1) max.

A1 b c

D

(1)

Dh

mm

1

0.05

0.00

0.30

0.18

0.2

5.1

4.9

3.75

3.45

E

(1)

5.1

4.9

e

0.5

e1

3.5

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE

VERSION

SOT617-3

IEC

- - -

REFERENCES

JEDEC JEITA

MO-220 - - -

e2

3.5

L

0.5

0.3

5 mm

v

0.1

w y y1

0.05

0.05

0.1

EUROPEAN

PROJECTION

X

ISSUE DATE

02-04-18

02-10-22

2003 Oct 13 18



DC/DC converter


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13 SOLDERING

13.1

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is recommended.

13.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from

215 to 270

°

C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:

• below 220

°

C (SnPb process) or below 245

°

C (Pb-free process)

– for all BGA and SSOP-T packages

– for packages with a thickness

≥

2.5 mm

– for packages with a thickness < 2.5 mm and a volume

≥

350 mm

3

so called thick/large packages.

• below 235

°

C (SnPb process) or below 260

°

C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm

3

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3

Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

•

Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

•

For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•

For packages with leads on four sides, the footprint must be placed at a 45

° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from

3 to 4 seconds at 250

°

C or 265

°

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

13.4

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300

°

C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between

270 and 320

°

C.

2003 Oct 13 19



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13.5

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

(1)

BGA, LBGA, LFBGA, SQFP, SSOP-T

(3)

, TFBGA, VFBGA

DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, HVQFN, HVSON, SMS

PLCC

(5)

, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO, VSSOP

PMFP

(8) not suitable not suitable

SOLDERING METHOD

WAVE

(4)

REFLOW

(2) suitable suitable suitable suitable not recommended

(5)(6) suitable not recommended

(7) suitable not suitable not suitable

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217

°

C

±

10

°

C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45

°

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Hot bar or manual soldering is suitable for PMFP packages.

2003 Oct 13 20



DC/DC converter


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14 DATA SHEET STATUS

I

LEVEL

II

III

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.

Product data Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

15 DEFINITIONS

Short-form specification



The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition



Limiting values given are in accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may affect device reliability.

Application information



Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

16 DISCLAIMERS

Life support applications



These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes



Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

2003 Oct 13 21



DC/DC converter

17 PURCHASE OF PHILIPS I

2

C COMPONENTS


TEA1211HN

Purchase of Philips I

2

C components conveys a license under the Philips’ I

2

C patent to use the components in the I

2

C system provided the system conforms to the I

2

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2003 Oct 13 22

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: [email protected].

© Koninklijke Philips Electronics N.V. 2003 SCA75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R54/02/pp

23

Date of release:

2003 Oct 13

Document order number: 9397 750 12174

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Philips Semiconductors – a worldwide company

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