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TECHNICAL DATA
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MC68HC05F32
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MC68HC05F32/D
HC05
MC68HC05F32
MC68HC705F32
TECHNICAL
DATA
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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
PARALLEL INPUT/OUTPUT PORTS
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CORE TIMER
16-BIT PROGRAMABLE TIMER
DTMF/MELODY GENERATOR
LIQUID CRYSTAL DISPLAY DRIVER MODULE
A/D CONVERTER
SERIAL PERIPHERAL INTERFACE
SERIAL COMMUNICATIONS INTERFACE
PULSE WIDTH MODULATOR
32 KHZ CLOCK SYSTEM
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
MC68HC705F32
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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
PARALLEL INPUT/OUTPUT PORTS
CORE TIMER
16-BIT PROGRAMMABLE TIMER
DTMF/MELODY GENERATOR
LIQUID CRYSTAL DISPLAY DRIVER MODULE
A/D CONVERTER
SERIAL PERIPHERAL INTERFACE
SERIAL COMMUNICATIONS INTERFACE
PULSE WIDTH MODULATOR
32 KHZ CLOCK SYSTEM
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
MC68HC705F32
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MC68HC05F32
MC68HC705F32
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High-density complementary
metal oxide semiconductor
(HCMOS) microcontroller unit
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Conventions
Where abbreviations are used in the text, an explanation can be found in the
glossary, at the back of this manual. Register and bit mnemonics are defined in the
paragraphs describing them.
An overbar is used to designate an active-low signal, eg: RESET.
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SECTION 1
INTRODUCTION
SECTION 2
MODES OF OPERATION AND PIN DESCRIPTIONS
SECTION 3
MEMORY AND REGISTERS
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
SECTION 5
CORE TIMER
SECTION 6
16-BIT PROGRAMMABLE TIMER
SECTION 7
DTMF/MELODY GENERATOR
SECTION 8
LIQUID CRYSTAL DISPLAY DRIVER MODULE
SECTION 9
A/D CONVERTER
SECTION 10 SERIAL PERIPHERAL INTERFACE
SECTION 11 SERIAL COMMUNICATIONS INTERFACE
SECTION 12 PULSE WIDTH MODULATOR
SECTION 13 32 KHZ CLOCK SYSTEM
SECTION 14 RESETS AND INTERRUPTS
SECTION 15 CPU CORE AND INSTRUCTION SET
SECTION 16 ELECTRICAL SPECIFICATIONS
SECTION 17 MECHANICAL DATA
SECTION 18 ORDERING INFORMATION
SECTION 19 APPENDICES
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TABLE OF CONTENTS
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Paragraph
Number
TITLE
Page
Number
1
INTRODUCTION
1.1
1.2
Features................................................................................................................... 1–2
Mask options for the MC68HC05F32 ...................................................................... 1–2
2
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
Single-chip mode ..................................................................................................... 2–1
Low power modes.................................................................................................... 2–1
STOP mode ....................................................................................................... 2–1
WAIT mode ........................................................................................................ 2–2
Data retention mode .......................................................................................... 2–2
System options register (SOR) ................................................................................ 2–4
Pin descriptions ....................................................................................................... 2–5
VDD and VSS .................................................................................................... 2–5
IRQ .................................................................................................................... 2–5
RESET ............................................................................................................... 2–5
PA7–PA0/keyboard interrupt, PB7–PB0............................................................. 2–5
PC7/SS, PC6/SCK, PC5/MOSI, PC4/MISO, PC3/TDO, PC2/RDI, PC1/TCAP4,
PC0/TCAP3 ....................................................................................................... 2–6
2.4.6
PD7–PD0/AN7–AN0 .......................................................................................... 2–6
2.4.7
VRH ................................................................................................................... 2–6
2.4.8
AVDD ................................................................................................................. 2–6
2.4.9
AVSS.................................................................................................................. 2–6
2.4.10
PE7/PWM3, PE6/PWM2, PE5/PWM1, PE4/REFRESH, PE3/TCMP2, PE2/TCAP2,
PE1/TCMP1, PE0/TCAP1.................................................................................. 2–6
2.4.11
BP3–BP0 ........................................................................................................... 2–7
2.4.12
VLCD ................................................................................................................. 2–7
2.4.13
Ports F, G, H, I, J/FP39–FP0.............................................................................. 2–7
2.4.14
TNO and TNX .................................................................................................... 2–7
2.4.15
OSC1 and OSC2 ............................................................................................... 2–7
2.4.16
OSC3 and OSC4 ............................................................................................... 2–7
2.4.16.1
Crystal .......................................................................................................... 2–8
TPG
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Paragraph
Number
TITLE
Page
Number
2.4.16.2
External clock................................................................................................2–8
2.5
Alternative pin descriptions for the 80-pin QFP package .......................................2–10
2.5.1
PC5, PC4, PC0/TACP3.....................................................................................2–10
2.5.2
PD7–PD0..........................................................................................................2–10
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3
MEMORY AND REGISTERS
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
Registers ..................................................................................................................3–1
RAM .........................................................................................................................3–5
ROM .........................................................................................................................3–5
Bootloader ROM.......................................................................................................3–6
EEPROM ..................................................................................................................3–6
EEPROM programming register .........................................................................3–6
Programming and erasing procedures................................................................3–8
Sample EEPROM programming sequence ........................................................3–8
4
PARALLEL INPUT/OUTPUT PORTS
4.1
Input/output programming ........................................................................................4–1
4.2
Port A........................................................................................................................4–2
4.2.1
Keyboard interrupt ..............................................................................................4–2
4.2.1.1
Key control register (KCR) ............................................................................4–3
4.3
Port B........................................................................................................................4–4
4.4
Port C .......................................................................................................................4–5
4.5
Port D .......................................................................................................................4–5
4.6
Port E........................................................................................................................4–6
4.7
Ports F, G, H, I and J ................................................................................................4–6
4.8
Port registers ............................................................................................................4–7
4.8.1
Port data registers (Ports A, B, C, D, E, F, G, H, I and J) ....................................4–7
4.8.2
Data direction registers (DDRA, DDRB, DDRC, DDRD and DDRE) ..................4–7
4.8.3
Port control registers...........................................................................................4–8
5
CORE TIMER
5.1
5.2
5.2.1
5.2.2
5.3
5.4
5.5
Real time interrupts (RTI) .........................................................................................5–2
Core timer registers ..................................................................................................5–3
Core timer control and status register (CTCSR).................................................5–3
Core timer counter register (CTCR)....................................................................5–4
Computer operating properly (COP) watchdog timer ...............................................5–5
Core timer during WAIT ............................................................................................5–5
Core timer during STOP ...........................................................................................5–5
TPG
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Paragraph
Number
TITLE
Page
Number
6
16-BIT PROGRAMMABLE TIMER
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6.1
6.1.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.5
6.6
6.7
Counter .................................................................................................................... 6–1
Counter register and alternate counter register ................................................. 6–3
Timer control and status .......................................................................................... 6–4
Timer control registers 1 and 2 (TCR1 and TCR2) ............................................ 6–4
Timer status register (TSR)................................................................................ 6–7
Input capture............................................................................................................ 6–9
Input capture register 1 (ICR1) .......................................................................... 6–9
Input capture register 2 (ICR2) ........................................................................ 6–10
Output compare ..................................................................................................... 6–11
Output compare register 1 (OCR1).................................................................. 6–11
Output compare register 2 (OCR2).................................................................. 6–12
Timer during STOP mode...................................................................................... 6–13
Timer during WAIT mode....................................................................................... 6–13
Timer state diagrams ............................................................................................. 6–13
7
DTMF/MELODY GENERATOR
7.1
7.1.1
7.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
Introduction .............................................................................................................. 7–1
Features ............................................................................................................. 7–1
Functional description.............................................................................................. 7–2
DMG registers ......................................................................................................... 7–4
Row and column frequency control registers ..................................................... 7–4
Tone control register (TNCR) ............................................................................. 7–4
Operation of the DMG.............................................................................................. 7–7
DMG during WAIT mode.......................................................................................... 7–8
DMG during STOP mode......................................................................................... 7–8
8
LIQUID CRYSTAL DISPLAY DRIVER MODULE
8.1
8.2
8.3
8.4
8.5
8.6
LCD RAM ................................................................................................................ 8–2
LCD operation.......................................................................................................... 8–3
Timing signals and LCD voltage waveforms............................................................ 8–4
LCD control register (LCD) ..................................................................................... 8–9
LCD during WAIT mode......................................................................................... 8–10
LCD during STOP mode........................................................................................ 8–10
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MOTOROLA
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Paragraph
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TITLE
Page
Number
9
A/D CONVERTER
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9.1
9.2
9.2.1
9.2.2
9.3
9.4
9.5
A/D converter operation............................................................................................9–1
A/D registers.............................................................................................................9–3
A/D status/control register (ADSCR) ..................................................................9–3
A/D result data register (ADDATA) ......................................................................9–5
A/D converter during WAIT mode.............................................................................9–5
A/D converter during STOP mode............................................................................9–5
A/D analog input .......................................................................................................9–5
10
SERIAL PERIPHERAL INTERFACE
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.3
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
Overview and features............................................................................................10–1
SPI signal descriptions ...........................................................................................10–2
Master in slave out (MISO) ...............................................................................10–2
Master out slave in (MOSI) ...............................................................................10–2
Serial clock (SCK).............................................................................................10–2
Slave select (SS) ..............................................................................................10–4
Functional description ............................................................................................10–4
SPI registers ...........................................................................................................10–6
Control register (SPCR)....................................................................................10–6
Status register (SPSR) .....................................................................................10–8
SPI data I/O register (SPDAT) ..........................................................................10–9
SPI during WAIT mode ...........................................................................................10–9
SPI during STOP mode ..........................................................................................10–9
11
SERIAL COMMUNICATIONS INTERFACE
11.1 SCI two-wire system features.................................................................................11–1
11.2 SCI receiver features ..............................................................................................11–3
11.3 SCI transmitter features..........................................................................................11–3
11.4 External connections ..............................................................................................11–3
11.5 Functional description ............................................................................................11–4
11.6 Data format.............................................................................................................11–5
11.7 Receiver wake-up operation ...................................................................................11–5
11.7.1
Idle line wake-up ...............................................................................................11–6
11.7.2
Address mark wake-up .....................................................................................11–6
11.8 Receive data in (RDI) .............................................................................................11–6
11.9 Start bit detection ...................................................................................................11–7
11.10 Transmit data out (TDO) .........................................................................................11–8
11.11 SCI registers...........................................................................................................11–9
11.11.1 Serial communications data register (SCDAT)..................................................11–9
MOTOROLA
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TITLE
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Number
11.11.2 Serial communications control register 1 (SCCR1) ......................................... 11–9
11.11.3 Serial communications control register 2 (SCCR2) ....................................... 11–11
11.11.4 Serial communications status register (SCSR).............................................. 11–12
11.11.5 Baud rate register (BAUD) ............................................................................. 11–14
11.12 Baud rate selection .............................................................................................. 11–16
11.13 SCI during STOP mode ....................................................................................... 11–16
11.14 SCI during WAIT mode ........................................................................................ 11–16
12
PULSE WIDTH MODULATOR
12.1
12.2
12.3
12.3.1
12.3.2
12.4
12.5
12.6
PWM introduction .................................................................................................. 12–1
Functional description............................................................................................ 12–2
Registers ............................................................................................................... 12–2
PWM control (PWMCR) ................................................................................... 12–3
PWM data registers (PWMD)........................................................................... 12–4
PWM during WAIT mode ....................................................................................... 12–4
PWM during STOP mode ...................................................................................... 12–5
PWM during reset.................................................................................................. 12–5
13
32 KHZ CLOCK SYSTEM
13.1 32 kHz clock system .............................................................................................. 13–1
13.1.1
Custom periodic interrupt control/status register (CPICSR) ............................ 13–1
13.1.1.1
Refresh clock.............................................................................................. 13–2
13.2 Operation during STOP mode ............................................................................... 13–2
13.3 Operation during WAIT mode ................................................................................ 13–2
14
RESETS AND INTERRUPTS
14.1 Resets ................................................................................................................... 14–1
14.1.1
Power-on reset ................................................................................................. 14–1
14.1.2
RESET pin ....................................................................................................... 14–1
14.1.3
Illegal address reset......................................................................................... 14–1
14.1.4
Computer operating properly (COP) reset ....................................................... 14–2
14.1.5
Low voltage reset ............................................................................................. 14–2
14.2 Interrupts ............................................................................................................... 14–3
14.2.1
Interrupt priorities ............................................................................................. 14–4
14.2.2
Non-maskable software interrupt (SWI) ........................................................... 14–4
14.2.3
Maskable hardware interrupts.......................................................................... 14–4
14.2.3.1
Real time and core timer (CTIMER) interrupts ........................................... 14–4
14.2.3.2
Programmable 16-bit timer interrupt........................................................... 14–6
MC68HC05F32
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Paragraph
Number
14.2.3.3
14.2.3.4
14.2.3.5
14.2.3.6
14.2.3.7
14.2.4
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TITLE
Page
Number
Keyboard interrupt.......................................................................................14–7
Low voltage interrupt...................................................................................14–7
Serial peripheral interface (SPI) interrupt....................................................14–7
Serial communications interface (SCI) interrupt..........................................14–7
Custom periodic interrupt (CPI) ..................................................................14–8
Hardware controlled interrupt sequence...........................................................14–8
15
CPU CORE AND INSTRUCTION SET
15.1 Registers ................................................................................................................15–1
15.1.1
Accumulator (A) ................................................................................................15–1
15.1.2
Index register (X) ..............................................................................................15–2
15.1.3
Program counter (PC).......................................................................................15–2
15.1.4
Stack pointer (SP).............................................................................................15–2
15.1.5
Condition code register (CCR)..........................................................................15–2
15.2 Instruction set .........................................................................................................15–3
15.2.1
Register/memory Instructions ...........................................................................15–4
15.2.2
Branch instructions ...........................................................................................15–4
15.2.3
Bit manipulation instructions .............................................................................15–4
15.2.4
Read/modify/write instructions..........................................................................15–4
15.2.5
Control instructions ...........................................................................................15–4
15.2.6
Tables................................................................................................................15–5
15.3 Addressing modes..................................................................................................15–5
15.3.1
Inherent.............................................................................................................15–6
15.3.2
Immediate .........................................................................................................15–6
15.3.3
Direct ................................................................................................................15–7
15.3.4
Extended.........................................................................................................15–12
15.3.5
Indexed, no offset ...........................................................................................15–12
15.3.6
Indexed, 8-bit offset ........................................................................................15–12
15.3.7
Indexed, 16-bit offset ......................................................................................15–12
15.3.8
Relative ...........................................................................................................15–13
15.3.9
Bit set/clear .....................................................................................................15–13
15.3.10 Bit test and branch..........................................................................................15–13
16
ELECTRICAL SPECIFICATIONS
16.1
16.2
16.3
16.4
16.5
16.6
16.7
Maximum ratings ....................................................................................................16–1
Thermal characteristics and power considerations ................................................16–2
DC electrical characteristics ...................................................................................16–3
Control timing .........................................................................................................16–5
DC levels for low voltage RESET and LVI ..............................................................16–7
Electrical specifications for DTMF/melody generator .............................................16–7
EEPROM additional information.............................................................................16–8
MOTOROLA
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Paragraph
Number
16.8
16.9
TITLE
Page
Number
PWM timing ........................................................................................................... 16–8
A/D converter characteristics................................................................................. 16–9
17
MECHANICAL DATA
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17.1
17.2
17.3
17.4
100-pin QFP pinout for the MC68HC05F32 .......................................................... 17–1
100-pin QFP mechanical dimensions .................................................................... 17–2
80-pin QFP pinout for the MC68HC05F32 ............................................................ 17–3
80-pin QFP mechanical dimensions ...................................................................... 17–4
18
ORDERING INFORMATION
18.1
18.2
18.3
EPROMs................................................................................................................ 18–2
Verification media .................................................................................................. 18–2
ROM verification units(RVU).................................................................................. 18–2
A
MC68HC705F32
A.1
Features................................................................................................................... A–1
A.2
Pin descriptions ....................................................................................................... A–3
A.2.1
IRQ/VPP ............................................................................................................ A–3
A.3
Memory and registers.............................................................................................. A–3
A.3.1
Registers............................................................................................................ A–3
A.3.2
EPROM ............................................................................................................. A–8
A.3.2.1
EPROM programming register (PROG) ....................................................... A–8
A.3.2.2
EPROM programming operation .................................................................. A–8
A.4
Electrical specifications ........................................................................................... A–9
A.4.1
EPROM characteristics ...................................................................................... A–9
A.4.2
DC levels for low voltage reset and LVI .............................................................. A–9
A.5
Mechanical data .................................................................................................... A–10
A.5.1
100-pin QFP pinout for the MC68HC705F32................................................... A–10
A.5.2
80-pin QFP pinout for the MC68HC705F32..................................................... A–11
GLOSSARY
INDEX
MC68HC05F32
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LIST OF FIGURES
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Figure
Number
1-1
2-1
2-2
3-1
4-1
4-2
5-1
6-1
6-2
6-3
6-4
6-5
7-1
8-1
8-2
8-3
8-4
8-5
8-6
9-1
9-2
10-1
10-2
10-3
11-1
11-2
11-3
11-4
11-5
11-6
11-7
12-1
12-2
TITLE
Page
Number
MC68HC05F32 block diagram ...........................................................................1–3
STOP and WAIT flowcharts ................................................................................2–3
Oscillator connections ........................................................................................2–9
Memory map of the MC68HC05F32 ..................................................................3–2
Structure of port with keyboard interrupt ............................................................4–3
Standard I/O port structure.................................................................................4–4
Core timer block diagram....................................................................................5–1
16-bit programmable timer block diagram ..........................................................6–2
Timer state timing diagram for reset .................................................................6–14
Timer state timing diagram for input capture ....................................................6–14
Timer state timing diagram for output compare ................................................6–15
Timer state timing diagram for timer overflow...................................................6–15
DTMF/melody generator (DMG) block diagram..................................................7–3
LCD system block diagram.................................................................................8–1
Voltage level selection ........................................................................................8–4
LCD waveform with 2 backplanes, 1/2 bias ........................................................8–5
LCD waveform with 2 backplanes, 1/3 bias ........................................................8–6
LCD waveform with 3 backplanes ......................................................................8–7
LCD waveform with 4 backplanes ......................................................................8–8
A/D converter block diagram ..............................................................................9–2
Electrical model of an A/D input pin....................................................................9–6
Data clock timing diagram ................................................................................10–3
Serial peripheral interface block diagram .........................................................10–5
Serial peripheral interface master–slave interconnection .................................10–6
Serial communications interface block diagram ...............................................11–2
SCI and port C..................................................................................................11–3
Data format.......................................................................................................11–5
SCI sampling technique used on all bits...........................................................11–6
SCI examples of start bit sampling technique ..................................................11–7
Artificial start following a framing error .............................................................11–8
SCI start bit following a break...........................................................................11–8
PWM block diagram..........................................................................................12–1
PWM output waveforms (POL = 1, active high)................................................12–2
TPG
MC68HC05F32
LIST OF FIGURES
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Figure
Number
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12-3
14-1
15-1
15-2
17-1
17-2
17-3
17-4
A-1
A-2
18-1
18-2
TITLE
Page
Number
PWM waveforms (POL = 0, active low) ............................................................ 12–3
Interrupt flowchart ............................................................................................ 14–5
Programming model ......................................................................................... 15–1
Stacking order .................................................................................................. 15–2
100-pin QFP pinout for the MC68HC05F32 ..................................................... 17–1
100-pin QFP mechanical dimensions............................................................... 17–2
80-pin QFP pinout for the MC68HC05F32 ....................................................... 17–3
80-pin QFP mechanical dimensions................................................................. 17–4
MC68HC705F32 block diagram .........................................................................A–2
Memory map of the MC68HC705F32 ................................................................A–4
100-pin QFP pinout for the MC68HC705F32 ...................................................A–10
80-pin QFP pinout for the MC68HC705F32 .....................................................A–11
MOTOROLA
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LIST OF FIGURES
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LIST OF TABLES
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Table
Number
1-1
3-1
3-2
4-1
5-1
5-2
7-1
7-2
7-3
7-4
8-1
8-2
8-3
8-4
9-1
9-2
10-1
11-1
11-2
11-3
12-1
13-1
14-1
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
16-1
16-2
TITLE
Page
Number
Data sheet appendices.......................................................................................1–1
Register outline...................................................................................................3–3
Erase modes ......................................................................................................3–7
I/O pin states ......................................................................................................4–5
Example RTI periods ..........................................................................................5–4
Minimum COP reset times..................................................................................5–5
Bit description for DTMF generation...................................................................7–5
Bit description for melody generator...................................................................7–6
Mode of operation for DMG ................................................................................7–6
Effect of tone generation on DMG ......................................................................7–7
LCD RAM organization.......................................................................................8–2
LCD controller operating modes.........................................................................8–3
Frequency selection............................................................................................8–9
Multiplex ratio/backplane selection ...................................................................8–10
A/D clock selection .............................................................................................9–3
A/D channel assignment.....................................................................................9–4
SPI rate selection .............................................................................................10–8
Method of receiver wake-up ...........................................................................11–10
First prescaler stage .......................................................................................11–15
Second prescaler stage..................................................................................11–15
PWM clock rate ................................................................................................12–4
Refresh clock (32.768 kHz crystal)...................................................................13–2
Vector address for interrupts and reset.............................................................14–6
MUL instruction.................................................................................................15–5
Register/memory instructions...........................................................................15–6
Branch instructions ...........................................................................................15–7
Bit manipulation instructions.............................................................................15–7
Read/modify/write instructions .........................................................................15–8
Control instructions...........................................................................................15–8
Instruction set ...................................................................................................15–9
M68HC05 opcode map...................................................................................15–11
Maximum ratings ..............................................................................................16–1
Package thermal characteristics.......................................................................16–2
TPG
MC68HC05F32
LIST OF TABLES
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Table
Number
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16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
18-1
A-1
A-2
A-3
TITLE
Page
Number
DC electrical characteristics (VDD = 5.0 V)...................................................... 16–3
DC electrical characteristics (VDD = 2.7 V)...................................................... 16–4
Control timing (VDD = 5V) ................................................................................ 16–5
Control timing (VDD = 2.7V).............................................................................. 16–6
DC levels for low voltage reset and LVI ............................................................ 16–7
Sine wave tones at TNO................................................................................... 16–7
Square wave tones at TNO .............................................................................. 16–7
TONEX at TNX output ...................................................................................... 16–8
EEPROM additional information....................................................................... 16–8
PWM timing ...................................................................................................... 16–8
A/D converter characteristics ........................................................................... 16–9
MC order numbers ........................................................................................... 18–1
Register outline ..................................................................................................A–5
EPROM characteristics ......................................................................................A–9
DC levels for low voltage reset and LVI ..............................................................A–9
MOTOROLA
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LIST OF TABLES
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1
1
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INTRODUCTION
The MC68HC05F32 is a member of the M68HC05 family of HCMOS microcomputers. Its memory
configuration comprises 32K bytes of ROM, 920 bytes of RAM and 256 bytes of EEPROM. The
on-board features of this device make it particularly suitable for use in highly integrated telephone
handsets; the timer and DTMF generator allow for both pulse and tone dialling and, in addition to
telephone set-up parameters and features such as last number redial, the EEPROM can typically store
up to 12 telephone numbers of 20 digits, even after power has been removed from the circuit. Other
features of the device include the keyboard interrupt facility, which allows a direct interface to a
telephone keypad, the LCD circuit, which can drive up to 160 segments of an LCD display, and the A/D
converter which could be used, for example, as a volume control for a telephone in hands-free mode.
A high level of integration has been achieved on the MC68HC05F32 and careful attention has been
paid to its low-power and low-voltage performance, a major consideration in many telecommunications
applications.
The MC68HC05F32 is very well suited to automotive applications; with its 8 analog inputs and many
general I/O lines, it is especially useful in applications such as car dashboards. Also, the voltage levels
of the LCD driver can be varied using external resistors, and the timer system is capable of driving two
stepper motors (e.g. speedometer and odometer), as well as controlling a real time clock. The SCI
subsystem is ideal for interfacing to diagnostic equipment, for example, and the on-board EEPROM
can be used to store data such as mileage or calibration information.
This data sheet is structured such that devices similar to the MC68HC05F32 are described in a set of
appendices.
Table 1-1 Data sheet appendices
Device
MC68HC705F32
Appendix
Differences from MC68HC05F32
A
32256 bytes EPROM; 496 bytes boot ROM
TPG
MC68HC05F32
INTRODUCTION
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1
1.1
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Features
•
Fully static design featuring the industry-standard M68HC05 CPU core
•
32512 bytes of user ROM, plus 16 bytes for vectors
•
240 bytes of bootloader ROM
•
920 bytes of RAM plus 20 bytes of LCD RAM
•
256 bytes of user EEPROM
•
DTMF/melody generator
•
16-bit programmable timer with four input captures and four output compares (the outputs of
two of the output compares are used internally and do not have external connections)
•
15 stage multipurpose core timer with timer overflow, real time interrupt and COP watchdog
•
LCD driver with 4 backplanes and 40 frontplanes
•
8-channel, 8-bit analog-to-digital (A/D) converter
•
Power saving STOP and WAIT modes
•
I/O lines
–
100 QFP configuration – total of 80 I/O pins configured as:
16 dedicated bidirectional I/O
64 shared with peripherals
–
80 QFP configuration – total of 69 I/O pins configured as:
16 dedicated bidirectional I/O
53 shared with peripherals
•
Keyboard interrupt facility on eight of the I/O lines, with high or low voltage level interrupt
triggers
•
Hardware interrupt with edge or edge-and-level sensitive interrupt trigger
•
SCI and SPI subsystems
•
On-chip oscillators
•
Three PWM channels
•
Two selectable bus frequencies
•
32kHz independent clock system
•
Power-on and power-off resets; low voltage detection circuitry (EEPROM)
•
Available in 100-pin QFP and 80-pin QFP
Note:
The 80-pin version is only a bond option. Pins PE4, PD7–PD0, PC4, PC5 are shared
with module functions which cannot work on the 80-pin package. These modules and
their corresponding pin functions should not be enabled.
TPG
MOTOROLA
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1
1.2
Mask options for the MC68HC05F32
TCAP3
TCAP4
TDO
RDI
MISO
MOSI
SCK
SS
256 bytes user EEPROM
SCI
920 bytes RAM
SPI
20 bytes LCD RAM
OSC1
OSC2
Oscillator and divider
OSC3
OSC4
32 kHz independent clock
system, oscillator and divider
2
VDD
VSS
REFRESH
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
8-channel
A/D
converter
Core timer
2
Periodic interrupt
IRQ
RESET
COP watchdog
M68HC05 CPU
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
AVDD
VRH
VRL/AVSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
TNO
TNX
DTMF/ melody generator
FP39
FP38
FP37
FP36
FP35
FP34
FP33
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
FP19
FP18
FP17
FP16
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Port H
Port G
Port F
Port I
Port J
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
LCD driver
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
VLCD
BP3
BP2
BP1
BP0
Timer
Port E
16 bytes for vectors
TCMP2
TCAP2
TCMP1
TCAP1
Port C
Keyboard interrupt
240 bytes bootstrap ROM
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Port D
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PWM3
PWM2
PWM1
PWM
32512 bytes user ROM
Port B
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A
There are three mask options available on the MC68HC05F32: STOP instruction (enable/disable),
COP watchdog timer (enable/disable) and low voltage reset (LVR – enable/disable). These options
are programmed during fabrication and must be specified by the customer at the time of ordering.
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Note: When not being used to output the LCD frontplanes, port G and port F pins are input only,
while port H, port I and port J pins are output only.
Figure 1-1 MC68HC05F32 block diagram
TPG
MC68HC05F32
INTRODUCTION
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2
2
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MODES OF OPERATION AND PIN
DESCRIPTIONS
The normal operating mode of the MC68HC05F32 is single chip mode. There is also a bootloader
mode, primarily for factory test purposes. In addition to these modes, there are three low power
modes which may be entered and exited at will from user mode: STOP, WAIT and data retention.
2.1
Single-chip mode
This is the normal user operating mode, in which the device functions as a self-contained
microcomputer unit, with all on-board peripherals and I/O ports available to the user. All address
and data activity occurs within the MCU.
2.2
Low power modes
2.2.1
STOP mode
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog
timer) operation, 16-bit timers, SPI, SCI, PWM and A/D converter.
During STOP mode, the core timer interrupt flags (CTOF and RTIF) and interrupt enable bits
(TOFE and RTIE) in the CTCSR as well as the 16-bit timer flags in register TSR and interrupt
enable bits in register TCR are cleared by internal hardware. The I-bit in the CCR is cleared to
enable external interrupts. All other registers, the remaining bits in the CTCSR, and memory
contents remain unaltered. All input/output lines remain unchanged. The processor can be
brought out of STOP mode only by an interrupt (IRQ, Keyboard, LVI or CPI from the 32 kHz clock
system) if enabled or RESET (external reset or low voltage reset – LVR). See Figure 2-1.
The STOP instruction can be disables by a mask option. When disabled, the STOP instruction is
executed as a NOP.
TPG
MC68HC05F32
MODES OF OPERATION AND PIN DESCRIPTIONS
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2
2.2.2
WAIT mode
The WAIT instruction places the MCU in a low power consumption mode, though it consumes
more power than in STOP mode. All CPU action is suspended, but the Core timer, the first 16-bit
timer (TCAP1, 2 and TCMP1, 2), the DMG and the LCD remain active. If bit 7 (WTLCDO) of the
LCD control register, $1E, is reset, the SPI, the SCI, the second 16-bit timer (TCAP3, 4 and
TCMP3, 4) and the A/D converter, also remain active in WAIT mode. If, however, WTLCDO is set
they are turned off.
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An interrupt from the core timer, 16-bit timers, SPI, SCI, IRQ, keyboard, LVI, OR CPI from the 32
kHz clock system, if enabled, will cause the MCU to exit the WAIT mode. An external reset, or LVR,
causes the MCU to exit the wait mode.
During WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory
and input/output lines remain in their previous state. See Figure 2-1.
2.2.3
Data retention mode
The contents of the RAM and CPU registers are retained at supply voltages as low as 2.0Vdc.
This is called the data retention mode, in which data is maintained but the device is not guaranteed
to operate. If the voltage drops below VROFF the low voltage reset circuit generates a reset.
For lowest power consumption in data retention mode the device should be put into STOP mode
before reducing the supply voltage, to ensure that all the clocks are stopped. If the device is not
in STOP mode then it is recommended that RESET be held low whilst the power supply is outwith
the normal operating range, to ensure that processing is suspended in an orderly manner.
Recovery from data retention mode, after the power supply has been restored, is by an external
interrupt, or by pulling the RESET line high.
TPG
MOTOROLA
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MODES OF OPERATION AND PIN DESCRIPTIONS
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MC68HC05F32
22
05F32Book Page 3 Tuesday, June 8, 1999 7:55 am
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2
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STOP
WAIT
Stop oscillator
and all clocks;
clear I-mask
Oscillator active;
stop processing;
clear I-mask
RESET
?
RESET
?
No
No
Yes
No
Yes
Any
interrupt
?
Any
interrupt
?
Yes
No
Yes
Turn on oscillator;
wait tPORL for
stabilization
Restart
processor
clocks
Fetch
interrupt or RESET
vector
Fetch
interrupt or RESET
vector
Figure 2-1 STOP and WAIT flowcharts
TPG
MC68HC05F32
MODES OF OPERATION AND PIN DESCRIPTIONS
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2-3
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05F32Book Page 4 Tuesday, June 8, 1999 7:55 am
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2
2.3
System options register (SOR)
The MC68HC05F32 MCU contains a System Option Register which is located at address $4D.
This register is used to control the LVI and the clock system.
System options register (SOR)
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Address
bit 7
bit 6
bit 5
$004D
LVIF
LVIE
LVION
bit 4
SC
bit 3
bit 2
bit 1
bit 0
State
on reset
IRQ KEYMUXKEYCLR PUEN 0000 0000
LVIF, LVIE, LVION — Low voltage interrupt bits
The LVIF flag is set by the low voltage detection circuit, if the LVI is enabled and power supply VDD
falls below Vlvi.
The low voltage interrupt must be enabled by first setting bit LVION Low Voltage Interrupt On and
after that setting bit LVIE Low Voltage Interrupt Enable. After power on reset the LVI circuit is
disabled.
SC — System clock option
After power on reset the internal bus frequency is f=3.58Mhz/2. If the bit SC System Clock is set
the system speed is reduced to f=3.58Mhz/4, with the exception of the DTMF generator (Oscillator
Frequency 3.58Mhz).
IRQ — Interrupt sensitivity
IRQ edge or level sensitivity
1 (set)
–
0 (clear) –
IRQ input edge and level sensitive
IRQ input edge sensitive
KEYMUX — Multiplex bit for access of interrupt flag
The KEYMUX bit switches between the port A data register and the interrupt status register
IRSTATE, that both have the address $0000. If KEYMUX is cleared normal read and write access
to port A is possible. If KEYMUX is set, a read or write operation at address $0000 accesses the
8 interrupt status flags.
KEYCLR — Keyboard interrupt clear
The keyboard wake-up interrupt status flag (Bit 7, $1B) is cleared by writing a “1” to bit KEYCLR.
A read access to this bit always returns “0”.
PUEN — PORTC pull-up enable
After power on reset the pull-up resistors in port C are disabled. If bit PUEN is set, the pull-up
resistors in port C are enabled. Writing a “0” to PUEN disables the pull-up function.
TPG
MOTOROLA
2-4
MODES OF OPERATION AND PIN DESCRIPTIONS
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2.4
Pin descriptions
2.4.1
VDD and VSS
2
Power is supplied to the microcomputer via these two pins. VDD is the positive supply pin and VSS is
the ground pin.
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It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These
short rise and fall times place very high short-duration current demands on the power supply. To
prevent noise problems, special care must be taken to provide good power supply bypassing at
the MCU. Bypass capacitors should have good high-frequency characteristics and be as close to
the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are
loaded.
2.4.2
IRQ
This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the
IRQ bit in the SOR register, to be one of two options: either edge and level sensitive or edge
sensitive only.
The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.
2.4.3
RESET
This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin forces the device
to a known start-up state. An external RC-circuit can be connected to this pin to generate a
power-on reset (POR) if required. In this case, the time constant must be great enough (at least
100ms) to allow the oscillator circuit to stabilise. This input has an internal Schmitt trigger to
improve noise immunity. When a low voltage reset condition occurs internally, the RESET pin
provides an active-low open drain output signal that may be used to reset external hardware.
Other internal reset conditions are not visible at the RESET pin.
2.4.4
PA7–PA0/keyboard interrupt, PB7–PB0
These 16 I/O lines comprise the two 8-bit ports A and B. The state of any pin is software
programmable, and on reset, the port pins are configured as inputs, with internal pull-up resistors.
The eight I/O lines of port A are shared with the keyboard interrupt function.
TPG
MC68HC05F32
MODES OF OPERATION AND PIN DESCRIPTIONS
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MOTOROLA
2-5
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2
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2.4.5
PC7/SS, PC6/SCK, PC5/MOSI, PC4/MISO, PC3/TDO,
PC2/RDI, PC1/TCAP4, PC0/TCAP3
These eight I/O lines comprise the 8-bit port C, and are shared with other functions to give added
flexibility. During reset, these lines are configured as inputs. Port pins PC0 and PC1 are shared
with the input timer capture TCAP3 and TCAP4. Pins PC2 and PC3 are connected to the SCI
system (RDI, TDO), if the SCI is enabled. The remaining four pins, PC7–PC4, are connected to
the SPI system (SS, SCK, MOSI, MISO), if the SPI is enabled. All eight lines have internal
programmable pull-ups. If the PUEN bit in the system options register is cleared, the pull-ups are
disabled after reset. Setting the PUEN bit enables all the pull-up resistors in port C.
2.4.6
PD7–PD0/AN7–AN0
The eight I/O lines of port D are configured as inputs during power-on or reset. As all port D output
are open-drain, an external pull-up resistor is needed when a pin is being used as an output.
These port lines, PD7–PD0, are shared with the A/D converter, and are connected to it when the
corresponding port D control register bit is set to 1.
2.4.7
VRH
The VRH pin is the positive reference voltage for the A/D converter.
2.4.8
AVDD
AVDD is the positive supply voltage for the A/D converter.
2.4.9
AVSS
AVSS is the negative supply voltage and the negative reference voltage for the A/D converter.
2.4.10
PE7/PWM3, PE6/PWM2, PE5/PWM1, PE4/REFRESH,
PE3/TCMP2, PE2/TCAP2, PE1/TCMP1, PE0/TCAP1
The pins PE7–PE0 comprise port E, providing eight I/O lines when the port E control bits are set
to 0. As these pins are open-drain, an external pull-up resistor is needed when a pin is being used
as an output. These pins also share functions. When the corresponding port E register control bit
is set to 1, pins PE3–PE0 are connected to the timer system (TCMP2, TCAP2, TCMP1, TCAP1),
pin PE4 becomes REFRESH, and pins PE7–PE5 are connected to the PWM (PWM3–PWM1).
TPG
MOTOROLA
2-6
MODES OF OPERATION AND PIN DESCRIPTIONS
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Freescale Semiconductor, Inc.
2.4.11
BP3–BP0
The LCD driver subsystem has a maximum of four backplanes and forty frontplanes configured
under software control. The pins BP3–BP0 provide the backplane drive signals and the forty
output lines FP39–FP0 provide the frontplane drive signals for the LCD unit. The forty frontplane
lines are shared with ports F, G, H, I and J.
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2.4.12
2
VLCD
The analogue part of the LCD controller can be supplied with an external voltage, VLCD, using the
VLCD pin. The value of VLCD may not exceed the positive power supply voltage VDD. When the
INTVLCD bit in the LCD control register is set to 1, an internal voltage generator (approx. 3V, if
VDD>3V) is activated as the source of the analogue LCD supply voltage.
2.4.13
Ports F, G, H, I, J/FP39–FP0
These five ports are shared with the frontplanes FP39–FP0. The default setting of the register
control bits is 0, setting all the pins in ports F and G input only, and all the pins in ports H, I and J
output only. The port J outputs are all open-drain. When a register control bit is set to 1, the
corresponding pin is connected to the LCD frontplane driver.
2.4.14
TNO and TNX
The TNO output provides dual tone DTMF or melody under program control. TNO is an open-drain
output, and therefore requires an external pull-up resistor. The TNX output provides pacifier tones
under program control.
2.4.15
OSC1 and OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal or external clock signal
connected to these pins supplies the oscillator clock. The oscillator frequency of 3.579 MHz
provides the time base for the real-time clock and the DTMF/melody generator.
2.4.16
OSC3 and OSC4
These pins provide control input for an independent on-chip oscillator circuit. A 32 kHz crystal
connected across these pins, or an external clock signal connected to OSC3 provides the
TPG
MC68HC05F32
MODES OF OPERATION AND PIN DESCRIPTIONS
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2-7
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05F32Book Page 8 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
2
separate clock. The oscillator frequency (fOSC=32 kHz) provides the time base for the divider, the
real time custom periodic interrupt (CPI) and the clock system output (REFRESH).
2.4.16.1
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Crystal
The circuit shown in Figure 2-2(a) is recommended when using either a crystal or a ceramic
resonator. Figure 2-2(d) provides the recommended capacitance and feedback resistance values.
The internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal
resonator in the frequency range specified for fOSC (see Section 16.4). Use of an external CMOS
oscillator is recommended when crystals outside the specified ranges are to be used. The crystal
and associated components should be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. The manufacturer of the particular crystal being
considered should be consulted for specific information.
2.4.16.2
External clock
An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as
shown in Figure 2-2(c). The tOXOV specification (see Section 16.4) does not apply when using an
external clock input. The equivalent specification of the external clock source should be used in
lieu of tOXOV.
TPG
MOTOROLA
2-8
MODES OF OPERATION AND PIN DESCRIPTIONS
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Freescale Semiconductor, Inc.
2
L
C1
RS
OSC1
OSC2
MCU
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Freescale Semiconductor, Inc.
C0
OSC1
OSC2
RP
(b) Crystal equivalent circuit
C OSC1
C OSC2
MCU
(a) Crystal resonator
oscillator connections
OSC1
OSC2
External
clock
NC
(c) External clock source connections
R S (max)
C0
C1
C OSC1
C OSC2
RP
Q
Crystal
2MHz 4MHz
400
75
5
7
8
12
15 – 40 15 – 30
15 – 30 15 – 25
10
10
30 000 40 000
Unit
Ω
pF
nF
pF
pF
MΩ
—
(d) Crystal resonator parameters
Figure 2-2 Oscillator connections
MC68HC05F32
MODES OF OPERATION AND PIN DESCRIPTIONS
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2
2.5
Alternative pin descriptions for the 80-pin QFP package
There is also an 80-pin version of the MC68HC05F32. As it has fewer pins and fewer modules,
some of the pin descriptions vary. The reduction of the I/O count means that there is no longer a
port H and that port C has only three pins available for use, one of which is shared with the timer
(TCAP3). Port D’s pins were shared with the A/D converter, but this can no longer be used.
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2.5.1
PC5, PC4, PC0/TACP3
The three I/O lines of port C are configured as inputs during reset and each one has an internal
pull-up resistor. Pin PC0 is shared with one of the timer’s input captures (TCAP3).
2.5.2
PD7–PD0
All eight port D lines are configured as inputs during reset. These pins are open drain outputs
which means that each one requires an external pull-up resistor when it is used as an output.
MOTOROLA
2-10
MODES OF OPERATION AND PIN DESCRIPTIONS
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3
3
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MEMORY AND REGISTERS
The MC68HC05F32 has a 64K byte memory map consisting of registers (for I/O, control and
status), user RAM, user ROM, EEPROM, bootloader ROM and reset and interrupt vectors as
shown in Figure 3-1.
3.1
Registers
All the I/O, control and status registers of the MC68HC05F32 are contained within the first 80 byte
block of the memory map, as detailed in Table 3-1.
MC68HC05F32
MEMORY AND REGISTERS
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3-1
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Freescale Semiconductor, Inc.
MC68HC05F32
3
$0000
I/O
(80 bytes)
$0050
Unused
$0054
LCD RAM (20 bytes)
$0068
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RAM
(920 bytes)
Stack
$0400
EEPROM
(256 bytes)
$0500
Unused
$8000
User ROM
(32256 bytes)
$FF00
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
Port D data (PORTD)
Port A DDR (DDRA)
Port B DDR (DDRB)
Port C DDR (DDRC)
Port D DDR (DDRD)
Ctimer control/status (CTCSR)
Ctimer counter (CTCR)
Port E data (PORTE)
Port E DDR (DDRE)
Port E control (PECR)
Row freq. control (FCR)
Column freq. control (FCC)
Tone control (TNCR)
Port F data (PORTF)
Port F control (PFCR)
Port G data (PORTG)
Port G control (PGCR)
Port H data (PORTH) (1)
Port H control (PHCR)(1)
Port I data (PORTI)
Port I control (PICR)
Port J data (PORTJ)
Port J control (PJCR)
Port D control (PDCR)
Key control (KCR)
EEPROM prog. (EEPROG)
$1E LCD control (LCD)
Bootloader ROM
(496 bytes)
$FFF0
User vectors
(16 bytes)
$FFFF
$20
$21
$22
$23
$24
$25
$26
$27
Capture 1 high (ICR1H)
Capture 1 low (ICR1L)
Compare 1 high (OCR1H)
Compare 1 low (OCR1L)
Capture 2 high (ICR2H)
Capture 2 low (ICR2L)
Compare 2 high (OCR2H)
Compare 2 low (OCR2L)
$28
$29
$2A
$2B
$2C
$2D
$2E
Counter 1 high (CNTH/1)
Counter 1 low (CNTL/1)
Alt. counter high 1 (ACNTH/1)
Alt. counter low 1 (ACNTL/1)
Timer 1 control 1 (TCR1/1)
Timer 1 control 2 (TCR2/1)
Timer 1 status (TSR/1)
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
$3C
$3D
$3E
Capture 3 high (ICR3H)
Capture 3 low (ICR3L)
Compare 3 high (OCR3H)
Compare 3 low (OCR3L)
Capture 4 high (ICR4H)
Capture 4 low (ICR4L)
Compare 4 high (OCR4H)
Compare 4 low (OCR4L)
Counter 2 high (CNTH/2)
Counter 2 low (CNTL/2)
Alt. counter high 2 (ACNTH/2)
Alt. counter low 2 (ACNTL/2)
Timer 2 control 1 (TCR1/2)(1)
Timer 2 control 2 (TCR2/2)(1)
Timer 2 status (TSR/2)(1)
$40
$41
$42
$43
$44
$45
$46
$47
$48
$49
$4A
$4B
$4C
$4D
$4E
$4F
PWM control (PWMCR)
PWM data 1 (PWMD1)
PWM data 2 (PWMD2)
PWM data 3 (PWMD3)
SPI control (SPCR) (1)
SPI status (SPSR) (1)
SPI data I/O (SPDAT) (1)
SCI data (SCDAT) (1)
SCI control 1 (SCCR1) (1)
SCI control 2 (SCCR2) (1)
SCI status (SCSR) (1)
SCI baud rate (BAUD) (1)
CPI control/status (CPICSR)
System options (SOR)
A/D data (ADDATA) (1)
A/D status/control (ADSCR) (1)
(1) Not applicable to 80-pin package.
– reserved
Figure 3-1 Memory map of the MC68HC05F32
MOTOROLA
3-2
MEMORY AND REGISTERS
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Freescale Semiconductor, Inc.
Table 3-1 Register outline
Register Name
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Address bit 7
bit 5
bit 4
PA6
PA5
PA4
bit 3
bit 1
Key interrupt status (KISR)
$0000
Port B data (PORTB)
$0001
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
undefined
Port C data (PORTC)
$0002
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
undefined
Port D data (PORTD)
$0003
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
undefined
Port A data direction (DDRA)
$0004
0000 0000
Port B data direction (DDRB)
$0005
0000 0000
Port C data direction (DDRC)
$0006
0000 0000
Port D data direction ((DDRD)
$0007
0000 0000
$0008
$0009
Port E data (PORTE)
$000A
Port E data direction (DDRE)
$000B
Port E control (PECR)
$000C
DTMF row freq. control (FCR)
$000D
TOF
RTIF
PE7
PE6
0
0
MS0
PF7
PF6
Port G data (PORTG)
$0012
$0013
Port H data (PORTH)
$0014
$0015
Port I data (PORTI)
$0016
$0017
Port J data (PORTJ)
$0018
Port J control (PJCR)
$0019
Port D control (PDCR)
$001A
Key control (KCR)
$001B
EEPROM prog. (EEPROG)
LCD control (LCD)
$001C
RT1
RT0
0000 0011
PE4
PE3
PE2
PE1
PE0
undefined
0
0000 0000
0
FCR4 FCR3 FCR2 FCR1 FCR0 undefined
0
FCC4 FCC3 FCC2 FCC1 FCC0 undefined
TGER TGEC TNOE
PF5
PF4
PF3
0
0
0
0000 0000
PF2
PF1
PF0
undefined
PG6
PG5
PG4
PG3
PG2
PG1
PG0
undefined
PH6
PH5
PH4
PH3
PH2
PH1
PH0
0000 0000
0000 0000
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
0000 0000
0000 0000
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
0000 0000
0000 0000
0000 0000
KF
0
KIE
CPEN
EDG5 EDG4 EDG3 EDG2 EDG1 EDG0 0000 0000
0
ER1
ER0 LATCH EERC EEPGM 0000 0000
$001E WTLCDO FSEL1 FSEL0 I NTVLCD FDISP MUX4 MUX3 EXTVON 0000 0000
Capture 1 high (ICR1H)
$0020
Capture 1 low (ICR1L)
$0021
MC68HC05F32
RTOF RRTIF
0000 0000
PH7
Port I control (PICR)
RTIE
3
0000 0000
PG7
Port H control (PHCR)
PE5
0
MS1
Port G control (PGCR)
TOFE
0
0
$000E
$0011
undefined
0000 0000
$000F
$0010
PA0
0000 0000
DTMF tone control (TNCR)
Port F data (PORTF)
PA1
0000 0000
DTMF column freq. control (FCC)
Port F control (PFCR)
PA2
State
on reset
bit 0
$0000
Core timer counter (CTCR)
PA3
bit 2
Port A data (PORTA)
Core timer control/status (CTCSR)
PA7
bit 6
(bit 15)
MEMORY AND REGISTERS
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(bit 8)
undefined
undefined
MOTOROLA
3-3
31
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Freescale Semiconductor, Inc.
Table 3-1 Register outline
Register Name
3
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bit 0
State
on reset
(bit 15)
(bit 8)
undefined
(bit 15)
(bit 8)
(bit 15)
(bit 8)
(bit 15)
(bit 8) 1111 1111
$002A (bit 15)
(bit 8) 1111 1111
Address bit 7
Compare 1 high (OCR1H)
$0022
Compare 1 low (OCR1L)
$0023
Capture 2 high (ICR2H)
$0024
bit 5
bit 4
bit 3
bit 2
bit 1
undefined
Capture 2 low (ICR2L)
$0025
Compare 2 high (OCR2H)
$0026
Compare 2 low (OCR2L)
$0027
Counter 1 high (CNTH/1)
$0028
Counter 1 low (CNTL/1)
bit 6
undefined
undefind
undefined
$0029
Alternate counter 1 high (ACNTH/1)
1111 1100
Alternate counter 1 low (ACNTL/1)
$002B
Timer1 control 1 (TCR1/1)
$002C
Timer1 control 2 (TCR2/1)
$002D
0
0
OCI2E
Timer1 status (TSR/1)
$002E
IC1F
IC2F
OC1F
Capture 3 high (ICR3H)
$0030
(bit 15)
(bit 8)
(bit 15)
(bit 8)
Capture 3 low (ICR3L)
$0031
Compare 3 high (OCR3H)
$0032
Compare 3 low (OCR3L)
$0033
Capture 4 high (ICR4H)
$0034
Capture 4 low (ICR4L)
$0035
$0036
Compare 4 low (OCR4L)
$0037
Counter 1 high (CNTH/1)
$0038
Counter 1 low (CNTL/1)
1111 1100
ICI1E
ICI2E OCI1E TOIE CO1E IEDG1 IEDG2 OLVL1 0000 0uu0
0
CO2E
0
0
TOF TCAP1 TCAP2 OC2F
OLVL2 0000 0000
0
uuuu uuu0
undefined
undefined
undefined
undefined
Compare 4 high (OCR4H)
(bit 15)
undefined
(bit 15)
undefined
undefined
undefined
(bit 15)
(bit 8) 1111 1111
$003A (bit 15)
(bit 8) 1111 1111
$0039
Alternate counter 2 high (ACNTH/1)
undefined
1111 1100
Alternate counter 2 low (ACNTL/1)
$003B
Timer2 control 1 (TCR1/2)
$003C
Timer2 control 2 (TCR2/2)
$003D
0
0
OCI4E
Timer2 status (TSR/2)
$003E
IC3F
IC4F
OC3F
PWM control (PWMCR)
$0040
PWM data 1 (PWMD1)
$0041
1000 0000
PWM data 2 (PWMD2)
$0042
1000 0000
PWM data 3 (PWMD3)
$0043
SPI control (SPCR)
$0044
MOTOROLA
3-4
1111 1100
ICI3E
0000 0uu0
ICI4E OCI3E TOIE CO3E IEDG3 IEDG4
0
CO4E
0
0
0000 0000
TOF TCAP3 TCAP4 OC4F
0
POL3 POL2 POL1
RA0
RA1
uuuu uuu0
0001 1100
1000 0000
SPIE
SPE
DOD MSTR CPOL CPHA SPR1 SPR0 0000 01uu
MEMORY AND REGISTERS
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Table 3-1 Register outline
Register Name
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Address bit 7
bit 6
SPIF WCOL
bit 5
0
bit 4
MODF
bit 3
bit 2
bit 1
bit 0
0
0
0
0
State
on reset
SPI status (SPSR)
$0045
SPI data I/O (SPDAT)
$0046
undefined
SCI data (SCDAT)
$0047
undefined
SCI control 1 (SCCR1)
$0048
R8
T8
0
M
WAKE
0
0
0
uu00 0000
SCI control 2 (SCCR2)
$0049
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0000 0000
SCI status (SCSR)
$004A
TDRE
TC
RDRF
IDLE
OR
0
1100 0000
SCI baud rate (BAUD)
$004B
TCLR
0
FE
3
SCP1 SCP0 RCKB SCR2 SCR1 SCR0 0000 0uuu
CPI control status (CPICSR)
$004C
0
CPIF
0
CPIE
0
System options (SOR)
$004D
LVIF
LVIE
LVION
SC
IRQ
A/D data (ADDATA)
$004E
0
CH3
A/D status/control (ADSCR)
NF
0000 0000
0
RFQ1 RFQ0 0000 0000
KEYMUX KEYCLRPUEN 0000 0000
undefined
$004F COCO ADRC ADON
CH2
CH1
CH0
0000 0000
u = undefined
3.2
RAM
The user RAM consists of 920 bytes of memory, from $0068 to $03FF. This is shared with a
64 byte stack area. The stack begins at $00FF, and may extend down to $00C0.
Note:
3.3
Using the stack area for data storage or temporary work locations requires care to
prevent the data from being overwritten due to stacking from an interrupt or subroutine
call.
ROM
The user ROM occupies 32512 bytes of memory, from $8000 to $FEFF. In addition, there are 16
bytes of user vectors, from $FFF0 to $FFFF. The Bootloader ROM is located from $FF00 to $FFEF.
Note:
For compatibility, unused bits (shaded) should always be cleared, when writing to them.
MC68HC05F32
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3.4
3
Bootloader ROM
The MC68HC05F32 has 224 bytes of bootloader ROM plus 16 bytes of bootloader vectors, from
$FF00 to $FFEF. These are included primarily for factory test purposes.
3.5
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EEPROM
256 bytes of user EEPROM reside at addresses $0400 to $04FF.
Programming or erasing the EEPROM can be done by the user on a single byte basis; erasing
may also be performed on a block or bulk basis. All programming or erasing is accomplished by
manipulating the programming register (EEPROG), located at address $001C.
Note:
The erased state of an EEPROM byte is ‘$FF’. This means that a write forces zeros to
the bits specified, whilst bits defined as ones are unchanged by a write operation.
Caution: There is a restriction on the use of indexed addressing for EEPROM read operations.
When the base address of an indexed read of an EEPROM location is within the
EEPROM address range ($0400 to $04FF), the read may not be successful.
e.g. LDA (BASE ADDRESS), X – may not give the correct result when the base
address is in the range $0400 to $04FF. However if the base address is outwith the
EEPROM address range, the read operation will be successful. This restriction applies
to all operations capable of using indexed addressing.
3.5.1
EEPROM programming register
Address
EEPROM programming (EEPROG) $001C
bit 7
0
bit 6
CPEN
bit 5
0
bit 4
ER1
bit 3
bit 2
bit 1
bit 0
State
on reset
ER0 LATCH EERC EEPGM 0000 0000
CPEN — Charge pump enable
1 (set)
–
Charge pump enabled.
0 (clear) –
Charge pump disabled.
When set, CPEN enables the charge pump which produces the internal programming voltage.
This bit should be set at the same time as the LATCH bit. The programming voltage will not be
available until EEPGM is set. The charge pump should be disabled when not in use. CPEN is
readable and writable and is cleared by reset.
MOTOROLA
3-6
MEMORY AND REGISTERS
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ER1, ER0 — Erase select bits
ER1 and ER0 are used to select either single byte programming or one of three erase modes:
byte, block, or bulk. Table 3-2 shows the mode selected for each bit configuration. These bits are
readable and writable and are cleared by reset.
3
Table 3-2 Erase modes
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ER1
0
0
1
1
ER0
0
1
0
1
Mode
Program
Byte erase
Block erase
Bulk erase
–
In byte erase mode, only the selected byte is erased.
–
In block erase mode, a 32-byte block of EEPROM is erased. The EEPROM
memory space is divided into four 64-byte blocks ($0400 – $043F, $0440 –
$047F, $0480 – $04BF and $04C0 – $04FF) and performing a block erase
on any address within a block will erase the entire block.
–
In bulk erase mode, the entire 256 bytes of EEPROM are erased.
LATCH — EEPROM latch bit
1 (set)
–
0 (clear) –
EEPROM address and data buses are configured for programming.
EEPROM address and data buses are configured for normal
operation.
When set, the LATCH bit configures the EEPROM address and data buses for programming. In
addition, writes to the EEPROM array cause the address and data buses to be latched. This bit is
readable and writable, but reads from the EEPROM array are inhibited if the LATCH bit is set and
a write to the EEPROM space has taken place. When this bit is clear, address and data buses are
configured for normal operation. Reset clears this bit.
EERC — EEPROM RC oscillator control
1 (set)
–
0 (clear) –
Use internal RC oscillator for EEPROM.
Use CPU clock for EEPROM.
When this bit is set, the EEPROM memory array uses the internal RC oscillator instead of the CPU
clock. After setting the EERC bit, the user should wait a time tRCON to allow the RC oscillator to
stabilize. This bit is readable and writable and should be set by the user when the internal bus
frequency falls below 1.5MHz. Reset clears this bit.
MC68HC05F32
MEMORY AND REGISTERS
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EEPGM — EEPROM programming power enable
1 (set)
3
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–
0 (clear) –
Programming power connected to the EEPROM array.
Programming power switched off.
EEPGM must be set to enable the EEPGM function. When set, EEPGM turns on the charge pump
and enables the programming (or erasing) power to the EEPROM array. When clear, this power is
switched off. This will enable pulsing of the programming voltage to be controlled internally. This
bit can be read at any time, but can only be written to if LATCH = 1, i.e. if LATCH is not set, then
EEPGM cannot be set. Reset clears this bit.
3.5.2
Programming and erasing procedures
To program a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 0, write data to the
desired address and then set EEPGM for a time tEPGM.
There are three possibilities for erasing data from the EEPROM array, depending on how much
data is affected.
•
To erase a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = 0 and ER0 = 1, write data to
the desired address and then set EEPGM for a time tEBYTE.
•
To erase a block of EEPROM, set LATCH = CPEN = 1, set ER1 = 1 and ER0 = 0, write data
to any address in the block and then set EEPGM for a time tEBLOCK.
•
To bulk erase the EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 1, write data to any
address in the array and then set EEPGM for a time tEBULK.
To terminate the programming or erase sequence, clear EEPGM, wait for a time tFPV to allow the
programming voltage to fall, and then clear LATCH and CPEN to release the buses. Following
each erase or programming sequence, clear all programming control bits.
3.5.3
Sample EEPROM programming sequence
The following program is an example of the EEPROM programming sequence, using the timer to
implement the required delay and assuming a 1 MHz bus frequency.
MOTOROLA
3-8
MEMORY AND REGISTERS
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TCSR
EQU
TCNT
EQU
TOF
EQU
PROG
EQU
CPEN
EQU
ER1
EQU
ER0
EQU
LATCH EQU
EERC
EQU
EEPGM EQU
EESTARTEQU
SUMPIN EQU
$0008
$0009
7
$001C
6
4
3
2
1
0
$0400
$FF
TIMER CONTROL AND STATUS REGISTER
TIMER COUNTER REGISTER
TOF BIT OF TCSR
EEPROM PROGRAM REGISTER
CHARGE PUMP ENABLE BIT
ERASE SELECT BIT 1
ERASE SELECT BIT 0
LATCH BIT
RC/OSC SELECTOR BIT
EEPROM PROGRAM BIT
START ADDRESS OF EEPROM
DUMMY DATA
ORG
START
EQU
BSET
BSR
BSET
BSET
BCLR
BCLR
$0680
*
EERC, PROG
DELAY
CPEN, PROG
LATCH, PROG
ER1, PROG
ER0, PROG
SELECT RC OSCILLATOR
RC OSCILLATOR STABILIZATION
TURN ON CHARGE PUMP
ENABLE LATCH BIT
SELECT PROGRAM (NOT ERASE)
SELECT PROGRAM (NOT ERASE)
LDA
STA
BSET
JSR
BCLR
#SUMPIN
EESTART
EEPGM, PROG
DELAY
EEPGM, PROG
JSR
BCLR
BCLR
CMP
BNE
CLC
DELAY
LATCH, PROG
CPEN, PROG
EESTART
OUT1
OUT
RTS
OUT1
SEC
RTS
3
GET DATA
ENABLE PROGRAMMING POWER
WAIT FOR PROGRAMMING TIME
CLEAR EEPGM
WAIT FOR PROG VOLTAGE TO FALL
CLEAR LATCH
DISABLE CHARGE PUMP
VERIFY
CLEAR CARRY BIT IF NO ERROR
FLAG AN ERROR
*THIS ROUTINE GIVES A 15MS (+/-1MS) DELAY AT 1 MHZ BUS. THE SAME DELAY
* ROUTINE IS USED IN THIS EXAMPLE FOR SIMPLICITY, USING THE LONGEST DELAY
* TIME. USERS WILL WANT TO WRITE SHORTER DELAY ROUTINES FOR APPLICATIONS
*IN WHICH SPEED IS IMPORTANT.
DELAY
TIMLP
EQU
LDX
BCLR
BRCLR
DECX
BNE
RTS
MC68HC05F32
*
#15
TOF, TCSR
TOF, TCSR
COUNT OF 15
CLEAR TOF
WAIT FOR TOF FLAG
TIMLP
COUNT DOWN TO 0
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3
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THIS PAGE LEFT BLANK INTENTIONALLY
MOTOROLA
3-10
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4
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4
PARALLEL INPUT/OUTPUT PORTS
The MC68HC05F32 has a total of 80 I/O lines, arranged as ten 8-bit ports. The I/O lines are
individually programmable as either input or output, under the software control of the data
direction registers. Port A can also be configured to respond to keyboard interrupts.
To avoid glitches on the output pins, data should be written to the I/O port data register before
writing ones to the corresponding data direction register bits to set the pins in output mode.
4.1
Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The
direction of each pin is determined by the state of the corresponding bit in the port data direction
register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output
if its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding
DDR bit is cleared.
At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data
direction registers can be written to or read by the MCU. During the programmed output state, a
read of the data register actually reads the value of the output data latch and not the I/O pin. The
operation of the standard port hardware is shown schematically in Figure 4-2.
This is further summarized in Table 4-1, which shows the effect of reading from, or writing to an
I/O pin in various circumstances. Note that the read/write signal shown is internal and not available
to the user.
TPG
MC68HC05F32
PARALLEL INPUT/OUTPUT PORTS
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4.2
Port A
Port A is an 8-bit bidirectional port which is equipped with a keyboard interrupt. All eight lines have
internal pull-up resistors, which are required when the port is in input mode. On reset, this port is
configured as a standard I/O port comprising a data register and a data direction register.
4
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Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all ports pins to input mode. Writing a 1 to any DDR bit sets the corresponding port pin
to output mode. As every pin configured as an input contributes to the keyboard interrupt, it is
possible to disable a single pin by configuring it as an output.
4.2.1
Keyboard interrupt
Provided that the interrupt mask bit of the condition code register is cleared, the keyboard interrupt
facility is enabled by setting the keyboard interrupt bit (KIE) in the key control register.
On detection of a high-to-low transition, the interrupt inputs PA6 and PA7 are triggered. The trigger
edges of the interrupt lines, PA0–PA5, can be programmed using the EDG0–EDG5 bits in the key
control register. If one of these bits is cleared, after reset the corresponding interrupt is falling-edge
sensitive. If, however, one of them is set, after reset the corresponding interrupt is rising-edge
sensitive. The internal pull-up resistors of input lines, PA7–PA0, are disabled, if rising-edge
sensitivity is selected.
When a correct transition is detected, on any of this port’s pins, a keyboard interrupt request is
generated, and the corresponding interrupt status flag of the interrupt status register, IRSTATE, is
set. The interrupt status register is an 8-bit register which has the same address as PORTA,
$0000. This register can be read if the KEYMUX bit in the system option register is set. If KIE is
set, a keyboard interrupt is generated and the keyboard status flag, KF, is set by generating the
logical OR of the eight interrupt state register outputs.
The 8 interrupt state register flags can be reset in three ways:
1) Completely, if the chip is reset.
2) Completely, if a 1 is written to KEYCLR, in the system option register.
3) Individually, if a 1 is written to the corresponding bit position of the interrupt
state register ($00 with KEYMUX = 1, in the system option register).
TPG
MOTOROLA
4-2
PARALLEL INPUT/OUTPUT PORTS
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KIE
Bit 6, $1B
KEYMUX and
read PTAIO
EDG0
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4
Internal data bit 0
Bit 0, $1B
VDD
Q
D
KF and
keyboard
interrupt
request
Interrupt
state 0
C
R
8
DDR0
IRST1 – IRST8
Bit 0, $04
Figure 4-1 Structure of port with keyboard interrupt
4.2.1.1
Key control register (KCR)
This register contains eight bits, two of which are used to control the keyboard interrupt facility, the
others determine the keyboard interrupt edges.
Key control register (KCR)
Address
bit 7
bit 6
$001B
KF
KIE
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
EDG5 EDG4 EDG3 EDG2 EDG1 EDG0 0000 0000
KF — Keyboard interrupt status flag
1 (set)
–
0 (clear) –
A valid transition has occurred on one of the port pins.
No valid transition has occurred on any of the port pins.
This bit is set when a valid transition is detected on any of the port A pins; a keyboard interrupt
request will be generated, if keyboard interrupts are enabled (only if KIE is set). The KF flag is
cleared by resetting the IRSTATE register, or by setting KEYCLR = 1 in the system option register.
TPG
MC68HC05F32
PARALLEL INPUT/OUTPUT PORTS
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KIE — keyboard interrupt enable
1 (set)
–
Keyboard interrupt enabled.
0 (clear) –
Keyboard interrupt disabled.
An interrupt can only be generated if KIE and KF are both set and the I-bit in the CCR is clear.
EDG5–EDG0 — trigger edge control
1 (set)
–
0 (clear) –
Sets the corresponding interrupt line to rising-edge sensitive.
Sets the corresponding interrupt line falling-edge sensitive.
The trigger edges of the interrupt lines PA5–PA0 are programmable with the EDG5–EDG0 bits in
the key control register.
4.3
Port B
This port is a standard M68HC05 bidirectional I/O port, comprising a data register and a data
direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode. The port B lines have internal pull-up resistors.
M68HC05 inter nal connections
4
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Data direction
register bit
DDRn
Latched data
register bit
DATA
Output
buffer
O/P
data
buffer
I/O
pin
Output 

Input
buffer
Input 

DDRn
1
1
0
0
DATA
0
1
0
1
I/O
0
1
tristate
tristate
Figure 4-2 Standard I/O port structure
TPG
MOTOROLA
4-4
PARALLEL INPUT/OUTPUT PORTS
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Table 4-1 I/O pin states
R/W
0
0
1
1
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4.4
DDRn
0
1
0
1
Action of MCU write to/read of data bit
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch, and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in output mode. The output data latch is read.
4
Port C
Port C is an 8-bit bidirectional port, which is shared with the SPI subsystem, the SCI subsystem
and the timer system. If the SPI system is enabled, pins PC4–PC7 are connected to the functions
MISO, MOSI, SCK and SS, respectively. It the SCI system is enabled, pins PC2 and PC3 are
connected to RDI and TDO. PC0 and PC1 are connected to TCAP3 and TCAP4 in the timer
system. (These lines must be set to input, by resetting the DDR, to enable the correct TCAP
function).
Reset does not affect the data register, but it clears the data direction register, returning the ports
to inputs. Writing a 1 to a DDR bit, sets the corresponding port bit to output mode. All eight lines
have internal pull-ups, which can be programmed using the PUEN bit in the system option register
(SOR). The internal pull-ups are disabled after reset and when PUEN = 0, but are enabled by
writing a 1 to PUEN.
4.5
Port D
Port D is an 8-bit bidirectional port, which is shared with the A/D converter. A pin becomes
connected to the A/D converter, when its corresponding bit in the control register is set to 1.
Reset does not affect the data register, but it clears the data direction register and the control
register. The default setting of the register control bits is 0, making the pins general purpose I/O
lines. The direction of the pins is then determined by their corresponding bits in DDR (0 - input, 1
- output). Write access to DDR or the I/O register is blocked to reduce digital noise. Read access
to DDR or the I/O register returns 0. Port D has open-drain outputs, it therefore requires external
pull-up resistors for each pin when they are used as outputs.
Note:
The maximum leakage current for I/O ports is 10µA. Thus, a high resistance from an
analog source can limit the accuracy of the A/D converter. The analog source should
therefore be less than 1 kΩ.
TPG
MC68HC05F32
PARALLEL INPUT/OUTPUT PORTS
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4.6
4
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Port E
Port E is an 8-bit bidirectional port which is shared with the timer system, the independent 32 kHz
clock system and the PWM. When the corresponding bit in the port E control register is set to 1,
the pins PE1 and PE3 are connected to TCMP1 and TCMP2 of the timer system, PE4 is
connected to the independent clock system, it becomes REFRESH, and PE5 – PE7 become
PWM1 – PWM3 of the PWM system. Pins PE0 and PE2 are always connected to the timer system
(TCAP1 and TCAP2). These two lines must be set to input by resetting the DDR to enable correct
TCAP function.
Reset does not affect the data register, but it clears the data direction register and the control
register. The default setting of the register control bits is 0, making the pins general purpose I/O
lines. The direction of the pins is then determined by their corresponding bits in DDR (0 – input, 1
– output). Port E has open-drain outputs, it therefore requires external pull-up resistors for each
pin when they are used as outputs.
Note:
As the voltage at port D or port E is driven above VDD, the protection device will begin
to conduct and tend to clamp the input voltage to protect the input buffer. The voltage
at which this condition will occur varies significantly, from lot to lot, and over the
temperature range. At room temperature, the pin typically does not draw any current
until approximately 18V.
4.7
Ports F, G, H, I and J
These five ports are shared with the frontplanes FP39 – FP0. The default setting of the port control
bits, during reset, is 0, setting the pins in port F and port G to input only, and the pins in ports H,
I and J, to output only. At power on or reset, the output only port data registers are cleared, so that
these pins are driving logical 0. When the corresponding port control register bit is set to a 1, the
pin is connected to the LCD frontplane driver. All port J outputs are open-drain.
TPG
MOTOROLA
4-6
PARALLEL INPUT/OUTPUT PORTS
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4.8
Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.8.1
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4
Port data registers (Ports A, B, C, D, E, F, G, H, I and J)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data (PORTA)
$0000
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
undefined
Port B data (PORTB)
$0001
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
undefined
Port C data (PORTC)
$0002
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
undefined
Port D data (PORTD)
$0003
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
undefined
Port E data (PORTE)
$000A
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
undefined
Port F data (PORTF)
$0010
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
undefined
Port G data (PORTG)
$0012
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
undefined
Port H data (PORTH)
$0014
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
0000 0000
Port I data (PORTI)
$0016
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
Port J data (PORTJ)
$0018
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
0000 0000
0000 0000
Each bit of port A – port E can be configured as input or output via the corresponding data
direction bit in the port data direction register (DDRx).
Reset does not affect the state of the port A – port G data registers. However, port H, port I and
port J data registers are reset to 0.
4.8.2
Data direction registers (DDRA, DDRB, DDRC, DDRD and
DDRE)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data direction (DDRA)
$0004
0000 0000
Port B data direction (DDRB)
$0005
0000 0000
Port C data direction (DDRC)
$0006
0000 0000
Port D data direction (DDRD)
$0007
0000 0000
Port E data direction (DDRE)
$000B
0000 0000
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all port pins as inputs.
TPG
MC68HC05F32
PARALLEL INPUT/OUTPUT PORTS
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4.8.3
Port control registers
Address
4
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Port D control (PDCR)
Port E control (PECR)
Port F control (PFCR)
Port G control (PGCR)
Port H control (PHCR)
Port I control (PICR)
Port J control (PJCR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
$001A
$000C
$0011
$0013
$0015
$0017
$0019
bit 0
State on
reset$
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Writing a 1 to any bit configures the corresponding port pin as a special function port (timer, A/D,
LCD, PWM, refresh clock). However, clearing any bit to 0, configures the corresponding port pin
in port D and port E as general purpose I/O, port F and port G as input, and port H, port I and port
J as output.
TPG
MOTOROLA
4-8
PARALLEL INPUT/OUTPUT PORTS
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5
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CORE TIMER
5
The MC68HC05F32 has a 15-stage ripple counter called the core timer (CTIMER). Features of
this timer are: timer overflow, power-on reset (POR), real time interrupt (RTI) with four selectable
interrupt rates and a computer operating properly (COP) watchdog timer.
Internal bus
8
Internal processor clock
fOP
$09 CTCR
(Core timer counter)
fOP / 22
8
fOP
(÷ 4)
/ 210
7-bit counter
Overflow
detect
circuit
fOP / 217
fOP / 214
COP
clear
RTI select circuit
$08 CTCSR
(Core timer control and status)
8
TOF
RTIF TOFE
RTIE
RTOF RRTIF
RT1
RT0
COP watchdog
timer
(÷ 8)
Interrupt circuit
To
reset
logic
To interrupt logic
Figure 5-1 Core timer block diagram
TPG
MC68HC05F32
CORE TIMER
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5
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As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a fixed
prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be
read by the CPU at any time, by accessing the CTIMER counter register (CTCR) at address $09.
A timer overflow function is implemented on the last stage of this counter, giving a possible
interrupt at the rate of fOP/1024. (The POR signal (tPORL) is also derived from this register, at
fOP/4064.) The counter register circuit is followed by four more stages, with the resulting clock
(fOP/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages
with a 1-of-4 selector. The output of the RTI circuit is further divided by 8 to drive the COP
watchdog timer circuit. The RTI rate selector bits, and the RTI and CTIMER overflow enable bits
and flags, are located in the CTIMER control and status register (CTCSR) at location $08.
CTOF (core timer overflow flag) is a clearable, read-only status bit and is set when the 8-bit ripple
counter rolls over from $FF to $00. A CPU interrupt request will be generated if CTOFE is set.
Clearing the CTOF is done by writing a ‘0’ to it. Writing a ‘1’ to CTOF has no effect on the bit’s value.
Reset clears CTOF.
When CTOFE (core timer overflow enable) is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears CTOFE.
The core timer counter register (CTCR) is a read-only register that contains the current value of
the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP/4 and can
be used for various functions including a software input capture. Extended time periods can be
attained using the CTIMER overflow function to increment a temporary RAM storage location
thereby simulating a 16-bit (or more) counter.
The power-on cycle clears the entire counter chain and begins clocking the counter. After tPORL
cycles, the power-on reset circuit is released, which again clears the counter chain and allows the
device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up
from zero and normal device operation will begin. When RESET is asserted at any time during
operation (other than POR), the counter chain will be cleared.
5.1
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. The clock
frequency that drives the RTI circuit is fOP/214 (or fOP/16384), with three additional divider stages,
giving a maximum interrupt period of 4 seconds at a bus frequency (fOP) of 32kHz. Register details
are given in Section 5.2.
TPG
MOTOROLA
5-2
CORE TIMER
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5.2
Core timer registers
5.2.1
Core timer control and status register (CTCSR)
Core timer control/status (CTCSR)
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Address
bit 7
$0008
CTOF
bit 6
bit 5
bit 4
RTIF CTOFE RTIE
bit 3
bit 2
RTOF RRTIF
bit 1
RT1
bit 0
RT0
State
on reset
0000 0011
5
CTOF — Core timer overflow
1 (set)
–
0 (clear) –
Core timer overflow has occurred.
No core timer overflow interrupt has been generated.
CTOF is a read-only status bit and is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOFE is set. When set, CTOF may be cleared by
writing a ‘1’ to RTOF.
RTIF — Real time interrupt flag
1 (set)
–
0 (clear) –
A real time interrupt has occurred.
No real time interrupt has been generated.
RTIF is a read-only status bit and is set when the output of the chosen stage becomes active; an
interrupt request will be generated if RTIE is set. When set, the bit may be cleared by writing a ‘1’
to RRTIF. Reset also clears this bit.
CTOFE — Core timer overflow enable
1 (set)
–
Core timer overflow interrupt is enabled.
0 (clear) –
Core timer overflow interrupt is disabled.
Setting this bit enables the core timer overflow Interrupt. A CPU interrupt request will then be
generated whenever the CTOF bit becomes set and the I-bit in the CCR is clear. Clearing this bit
disables the core timer overflow interrupt capability.
RTIE — Real time interrupt enable
1 (set)
–
Real time interrupt is enabled.
0 (clear) –
Real time interrupt is disabled.
Setting this bit enables the real time interrupt. A CPU interrupt request will then be generated
whenever the RTIF bit becomes set and the I-bit in the CCR is clear. Clearing this bit disables the
real time interrupt capability.
TPG
MC68HC05F32
CORE TIMER
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RT1, RT0 — Real time interrupt rate select
5
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These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0
and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to alter
them if necessary. The COP reset times are also determined by these two bits. Care should be
taken when altering RT0 and RT1 if a timeout is imminent, or the timeout period is uncertain. If the
selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed
or an additional one could be generated. To avoid problems, the COP should be cleared before
changing the RTI taps. See Table 5-1 for some example RTI periods.
Table 5-1 Example RTI periods
RT1 RT0
0
0
1
1
5.2.2
0
1
0
1
RTI Rates at fOP Frequency Specified
Division
16.384 kHz 447 kHz
895 kHz 1.789 MHz
ratio
14
2
1s
36.7 ms
18.35 ms
9.17 ms
2 15
2s
73.4 ms
36.7 ms
18.35 ms
2 16
4s
146.8 ms
73.4 ms
36.7 ms
2 17
8s
293.6 ms
146.8 ms
73.4 ms
Core timer counter register (CTCR)
Address
Core timer counter (CTCR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
$0009
bit 0
State
on reset
0000 0000
The core timer counter register is a read-only register, which contains the current value of the 8-bit
ripple counter at the beginning of the timer chain. Reset clears this register.
TPG
MOTOROLA
5-4
CORE TIMER
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5.3
Computer operating properly (COP) watchdog timer
The COP watchdog timer function is implemented by taking the output of the RTI circuit and further
dividing it by eight, as shown in Figure 5-1. Note that the minimum COP timeout period is seven
times the RTI period. This is because the COP will be cleared asynchronously with respect to the
value in the core timer counter register/RTI divider, hence the actual COP timeout period will vary
between 7x and 8x the RTI period. The minimum COP reset rates are shown in Table 5-2.
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The COP function is a mask option, enabled or disabled during device manufacture.
If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched.
A COP timeout is prevented by writing a ‘0’ to bit 0 of address $FFF0. When the COP is cleared,
only the final divide-by-eight stage is cleared (see Figure 5-1).
5
Table 5-2 Minimum COP reset times
RT1
0
0
1
1
5.4
RT0
0
1
0
1
Minimum COP reset at f OP frequency specified
16.384 kHz 447 kHz
895 kHz
1.789 MHz
f OP
7s
256.9 ms 128.45 ms
64.19 ms
7 x RTI rate
14 s
513.8 ms
256.9 ms
128.45 ms
7 x RTI rate
28 s
1.03 s
513.8 s
256.9 ms
7 x RTI rate
56 s
2.06 s
1.03 s
513.8 ms
7 x RTI rate
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the timer remains active. If the CTIMER interrupts
are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (tPORL). The timer is then cleared and operation resumes.
TPG
MC68HC05F32
CORE TIMER
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THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
5-6
CORE TIMER
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6
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16-BIT PROGRAMMABLE TIMER
The MC68HC05F32 has two programmable 16-bit timers (TIMER1 and TIMER2), each with two
channels. The output compare function in TIMER2 has no external output, and is therefore used
for generating precision time intervals and interrupts only. The external connections are the only
differences between the two timers. The internal operation is identical (each timer has its own set
of registers), therefore only a complete description of TIMER1 is given.
6
The timer consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler,
plus the input capture/output compare circuitry. The timer can be used for many purposes including
measuring pulse length of two input signals and generating two output signals. Pulse lengths for
both input and output signals can vary from several microseconds to many seconds. The timer is
also capable of generating periodic interrupts or indicating passage of an arbitrary multiple of four
CPU cycles. A block diagram is shown in Figure 6-1, and timing diagrams are shown in Figure 6-2,
Figure 6-3, Figure 6-4 and Figure 6-5.
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers. These registers contain the high and low byte of that functional segment. Accessing
the low byte of a specific timer function allows full control of that function; however, an access of
the high byte inhibits that specific timer function until the low byte is also accessed.
The 16-bit programmable timer is monitored and controlled by a group of fifteen registers, full
details of which are contained in this section.
Note:
6.1
A problem may arise if an interrupt occurs in the time between the high and low bytes
being accessed. To prevent this, the I-bit in the condition code register (CCR) should be
set while manipulating both the high and low byte register of a specific timer function,
ensuring that an interrupt does not occur.
Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2µs if the internal bus clock is 2 MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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Internal bus
8
Internal
processor
clock
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High
byte
Low
byte
Output
compare
register 1
6
High
byte
$0022
$0023
8-bit
buffer
High
byte
Low
byte
Output
compare
register 2
$0026
$0027
÷4
Low
byte
16-bit
$0028
free-running
$0029
counter
COP watchdog
counter input
Counter
alternate
register
High
byte
Low
byte
High
byte
Low
byte
Input capture $0024
register 2 $0025
Input capture $0020
register 1 $0021
$002A
$002B
Internal timer bus
Output
compare
circuit 1
Overflow
detect
circuit
Output
compare
circuit 2
Edge
detect
circuit 1
Edge
detect
circuit 2
TCAP2
pin
TCAP1
pin
D
CLK
TCMP2
Q
pin
C
D
CLK
Q
TCMP1
pin
C
IC1F
IC2F OC1F TOF
TSR $002E
OC2F
OC2IE CO2E OLVL2
TCR2 $002D
IC1IE IC2IE OC1IE TOIE CO1E IEDG1 IEDG2 OLVL1
TCR1 $002C
RESET
Interrupt circuit
Input capture
interrupt vector
$7FF4, 5
Output compare
interrupt vector
$7FF4, 5
Input capture Output compare
interrupt vector interrupt vector
$7FF4, 5
$7FF4, 5
Overflow interrupt
vector
$7FF4, 5
Figure 6-1 16-bit programmable timer block diagram
TPG
MOTOROLA
6-2
16-BIT PROGRAMMABLE TIMER
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6.1.1
Counter register and alternate counter register
Address
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bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer counter high (CNTH)
$0028
1111 1111
Timer counter low (CNTL)
$0029
1111 1100
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Alternate counter high (ACNTH)
$002A
1111 1111
Alternate counter low (ACNTL)
$002B
1111 1100
The double-byte, free-running counter can be read from either of two locations, $0028 – $0029
(counter register) or $002A – $002B (counter alternate register). A read from only the less
significant byte (LSB) of the free-running counter ($0029 or $002B) receives the count value at the
time of the read. If a read of the free-running counter or alternate counter register first addresses
the more significant byte (MSB) ($0028 or $002A), the LSB is transferred to a buffer. This buffer
value remains fixed after the first MSB read, even if the user reads the MSB several times. This
buffer is accessed when reading the free-running counter or alternate counter register LSB and
thus completes a read sequence of the total counter value. In reading either the free-running
counter or alternate counter register, if the MSB is read, the LSB must also be read to complete
the sequence. If the timer overflow flag (TOF) is set when the counter register LSB is read then a
read of the timer status register (TSR) will clear the flag.
6
The counter alternate register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when
the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the flags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($0028 or $002A), then the reset counter operation
terminates the access sequence.
Caution: This operation may affect the function of the watchdog system (see Section 5.3).
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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6.2
Timer control and status
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
6.2.1
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6
Timer control registers 1 and 2 (TCR1 and TCR2)
The two timer control registers TCR1 and TCR2 ($002C and $002D) are used to enable the input
captures (IC1IE and IC2IE), output compares (OC1IE and OC2E), and timer overflow (TOIE)
functions as well as enabling the compare outputs (CO1E and CO2E), selecting input edge
sensitivity (IEDG1 and IEDG2) and levels of output polarity (OLVL1 and OLVL2).
Timer control 1 (TCR1)
Timer control 2 (TCR2)
Address
bit 7
bit 6
$002C
IC1IE
Address
bit 7
bit 6
$002D
0
0
bit 5
bit 4
IC2IE OC1IE TOIE
bit 5
OC2IE
bit 4
0
bit 3
bit 2
bit 1
bit 0
State
on reset
CO1E IEDG1 IEDG2 OLVL1 0000 0uu0
bit 3
CO2E
bit 2
0
bit 1
0
bit 0
State
on reset
OLVL2 0000 0000
TPG
MOTOROLA
6-4
16-BIT PROGRAMMABLE TIMER
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IC1IE — Input capture 1 interrupt enable
If this bit is set, a timer interrupt is enabled whenever the IC1F status flag (in the timer status
register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
IC2IE — Input capture 2 interrupt enable
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If this bit is set, a timer interrupt is enabled whenever the IC2F status flag (in the timer status
register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
6
OC1IE — Output compare 1 interrupt enable
If this bit is set, a timer interrupt is enabled whenever the OC1F status flag (in the timer status
register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
TOIE — Timer overflow interrupt enable
If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status
register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
CO1E — Timer compare 1 output enable
If this bit is set, the output from timer output compare 1 is enabled.
1 (set)
–
Output compare 1 enabled.
0 (clear) –
Output compare 1 disabled.
IEDG1 — Input edge 1
When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the input capture register 1. When clear, a negative-going edge
triggers the transfer.
1 (set)
–
0 (clear) –
TCAP1 is positive-going edge sensitive.
TCAP1 is negative-going edge sensitive.
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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IEDG2 — Input edge 2
When IEDG2 is set, a positive-going edge on the TCAP2 pin will trigger a transfer of the
free-running counter value to the input capture register 2. When clear, a negative-going edge
triggers the transfer.
1 (set)
–
0 (clear) –
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6
TCAP2 is positive-going edge sensitive.
TCAP2 is negative-going edge sensitive.
OLVL1 — Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set)
–
0 (clear) –
A high output level will appear on the TCMP1 pin.
A low output level will appear on the TCMP1 pin.
OC2IE — Output compare 2 interrupt enable
If this bit is set, a timer interrupt is enabled whenever the OC2F status flag (in the timer status
register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
CO2E — Timer compare 2 output enable
If this bit is set, the output from timer output compare 2 is enabled.
1 (set)
–
Output compare 2 enabled.
0 (clear) –
Output compare 2 disabled.
OLVL2 — Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set)
–
0 (clear) –
A high output level will appear on the TCMP2 pin.
A low output level will appear on the TCMP2 pin.
TPG
MOTOROLA
6-6
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6.2.2
Timer status register (TSR)
The timer status register ($002E) contains the status bits corresponding to the timer interrupt
conditions – IC1F, IC2F, OC1F, TOF, TCAP1, TCAP2 and OC2F.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
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Address
bit 7
bit 6
bit 5
$002E
IC1F
IC2F
OC1F
Timer status (TSR)
bit 4
bit 3
bit 2
bit 1
TOF TCAP1 TCAP2 OC2F
bit 0
0
State
on reset
Undefined
6
IC1F — Input capture 1 flag
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if IC1IE is set. IC1F is cleared by reading
the TSR and then the input capture 1 low register ($0021).
1 (set)
–
0 (clear) –
A valid input capture has occurred.
No input capture has occurred.
IC2F — Input capture 2 flag
This bit is set when the selected polarity of edge is detected by the input capture edge detector 2
at TCAP2; an input capture interrupt will be generated if IC2IE is set. IC2F is cleared by reading
the TSR and then the input capture 2 low register ($0025).
1 (set)
–
0 (clear) –
A valid input capture has occurred.
No input capture has occurred.
OC1F — Output compare 1 flag
This bit is set when the output compare register 1 contents match those of the free-running
counter; an output compare interrupt will be generated if OC1IE is set. OC1F is cleared by reading
the TSR and then the output compare 1 low register ($0023).
1 (set)
–
0 (clear) –
A valid output compare has occurred.
No output compare has occurred.
TOF — Timer overflow status flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($0029).
1 (set)
–
0 (clear) –
Timer overflow has occurred.
No timer overflow has occurred.
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
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6
1
The timer status register is read or written when TOF is set, and
2
The LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
TCAP1 — Timer capture 1 status flag
This bit reflects the status of the timer capture 1 input.
TCAP2 — Timer capture 2 status flag
This bit reflects the status of the timer capture 2 input.
OC2F — Output compare 2 flag
This bit is set when the output compare register 2 contents match those of the free-running
counter; an output compare interrupt will be generated if OC2IE is set. OC2F is cleared by reading
the TSR and then the output compare 2 low register ($0027).
1 (set)
–
0 (clear) –
A valid output compare has occurred.
No output compare has occurred.
TPG
MOTOROLA
6-8
16-BIT PROGRAMMABLE TIMER
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6.3
Input capture
‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free
running counter. In this way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).
There are two input capture interrupt enable bits (IC1IE and IC2IE).
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6.3.1
Input capture register 1 (ICR1)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture 1 high (ICR1H)
$0020
Undefined
Input capture 1 low (ICR1L)
$0021
Undefined
6
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 1 senses
a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the
input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag IC1F in TSR is set.
An interrupt can also accompany an input capture 1 provided the IC1IE bit in TCR1 is set. The 8
most significant bits are stored in the input capture register 1 high at $0020, the 8 least significant
bits in the input capture register 1 low at $0021.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 1 on each valid signal transition whether the input capture 1 flag (IC1F) is set or
clear. The input capture register 1 always contains the free-running counter value that corresponds
to the most recent input capture 1. After a read of the input capture register 1 MSB ($0020), the
counter transfer is inhibited until the LSB ($0021) is also read. This characteristic causes the time
used in the input capture software routine and its interaction with the main program to determine
the minimum pulse period. A read of the input capture register 1 LSB ($0021) does not inhibit the
free-running counter transfer since the two actions occur on opposite edges of the internal bus
clock.
Reset does not affect the contents of the input capture register 1, except when exiting STOP mode
(see Section 6.5).
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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6.3.2
Input capture register 2 (ICR2)
Address
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6
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture 2 high (ICR2H)
$0024
Undefined
Input capture 2 low (ICR2L)
$0025
Undefined
The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 2 senses
a valid transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag IC2F in
TSR is set. An interrupt can also accompany an input capture 2 provided the IC2IE bit in TCR1 is
set. The 8 most significant bits are stored in the input capture 2 high register at $0024, the 8 least
significant bits in the input capture 2 low register at $0025.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 2 on each valid signal transition whether the input capture 2 flag (IC2F) is set or
clear. The input capture register 2 always contains the free-running counter value that corresponds
to the most recent input capture 2. After a read of the input capture register 2 MSB ($0024), the
counter transfer is inhibited until the LSB ($0025) is also read. This characteristic causes the time
used in the input capture software routine and its interaction with the main program to determine
the minimum pulse period. A read of the input capture register 2 LSB ($0024) does not inhibit the
free-running counter transfer since the two actions occur on opposite edges of the internal bus
clock.
Reset does not affect the contents of the input capture register 2, except when exiting STOP mode
(see Section 6.5).
TPG
MOTOROLA
6-10
16-BIT PROGRAMMABLE TIMER
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6.4
Output compare
‘Output compare’ is a technique which may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
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There are two output compare interrupt enable bits (OC1IE and OC2IE).
6.4.1
Output compare register 1 (OCR1)
Address
bit 7
bit 6
bit 5
bit 4
6
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare 1 high (OCR1H)
$0022
Undefined
Output compare 1 low (OCR1L)
$0023
Undefined
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $0022 (MSB)
and $0023 (LSB). The contents of the output compare register 1 are compared with the contents
of the free-running counter continually and, if a match is found, the corresponding output compare
flag (OC1F) in the timer status register is set. If the timer compare output enable bit (CO1E) is set,
the output level (OLVL1) is transferred to pin TCMP1. The output compare register 1 values and
the output level bit should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt can also accompany a successful output compare provided the
corresponding interrupt enable bit (OC1IE) is set. (The free-running counter is updated every four
internal bus clock cycles.)
After a processor write cycle to the output compare register 1 containing the MSB ($0022), the
output compare function is inhibited until the LSB ($0023) is also written. The user must write both
bytes (locations) if the MSB is written first. A write made only to the LSB ($0023) will not inhibit the
compare 1 function. The processor can write to either byte of the output compare register 1 without
affecting the other byte. The output level (OLVL1) bit is clocked to the output level register and
hence to the TCMP1 pin whether the output compare flag 1 (OC1F) is set or clear. The minimum
time required to update the output compare register 1 is a function of the program rather than the
internal hardware. Because the output compare flag 1 and the output compare register 1 are not
defined at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
–
Write to output compare 1 high to inhibit further compares;
–
Read the timer status register to clear OC1F (if set);
–
Write to output compare 1 low to enable the output compare 1 function.
The purpose of this procedure is to prevent the OC1F bit from being set between the time it is read
and the write to the corresponding output compare register.
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
6.4.2
Output compare register 2 (OCR2)
Address
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6
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare 2 high (OCR2H)
$0026
Undefined
Output compare 2 low (OCR2L)
$0027
Undefined
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $0026 (MSB)
and $0027 (LSB). The contents of the output compare register 2 are compared with the contents
of the free-running counter continually and, if a match is found, the corresponding output compare
flag (OC2F) in the timer status register is set. If the timer compare 2 output enable bit (CO2E) is
set, the output level (OLVL2) is transferred to pin TCMP2. The output compare register 2 values
and the output level bit should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt can also accompany a successful output compare provided the
corresponding interrupt enable bit (OC2IE) is set. (The free-running counter is updated every four
internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($0026), the
output compare function is inhibited until the LSB ($0027) is also written. The user must write both
bytes (locations) if the MSB is written first. A write made only to the LSB ($0027) will not inhibit the
compare 2 function. The processor can write to either byte of the output compare register 2 without
affecting the other byte. The output level (OLVL2) bit is clocked to the output level register and
hence to the TCMP2 pin whether the output compare 2 flag (OC2F) is set or clear. The minimum
time required to update the output compare register 2 is a function of the program rather than the
internal hardware. Because the output compare 2 flag and the output compare register 2 are not
defined at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
–
Write to output compare 2 high to inhibit further compares;
–
Read the timer status register to clear OC2F (if set);
–
Write to output compare 2 low to enable the output compare 2 function.
The purpose of this procedure is to prevent the OC2F bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
TPG
MOTOROLA
6-12
16-BIT PROGRAMMABLE TIMER
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6.5
Timer during STOP mode
When the MCU enters STOP mode, the timer counter stops counting and remains at that particular
count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or
external reset, the counter is forced to $FFFC but if it is exited by external interrupt (IRQ) then the
counter resumes from its stopped value.
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Another feature of the programmable timer is that if at least one valid input capture edge occurs at
one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is
armed. This action does not wake the MCU or set any timer flags, but when the MCU does wake-up
there will be an active input capture flag (and data) from that first valid edge which occurred during
STOP mode.
If STOP mode is exited by an external reset then no such input capture flag or data action takes
place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.
6.6
6
Timer during WAIT mode
During WAIT mode, the CPU clock halts but timer1 keeps running. Timer2 is disabled, if bit 7
(WTLCDO) of the LCD control register is set, however, if it is cleared, timer2 remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit WAIT mode.
6.7
Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following figures. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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Internal
processor clock
Internal
reset
16-bit
counter
6
$FFFC
$FFFD
$FFFE
$FFFF
External reset
or end of POR
Note:
The counter and timer control registers are the only ones affected by power-on or external reset.
Figure 6-2 Timer state timing diagram for reset
Internal
processor clock
Internal
timer clocks
 T00
 T01
 T10

 T11
16-bit
counter
$F124
$F125
$F126
}
}
Input
edge
$F123
}
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Internal
timer clocks
 T00
 T01
 T10

 T11
}
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Internal
capture latch
Input capture
register
$????
$F124
Input capture
flag
Note:
If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then
the input capture flag will be set during the next T11 state.
Figure 6-3 Timer state timing diagram for input capture
TPG
MOTOROLA
6-14
16-BIT PROGRAMMABLE TIMER
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Internal
processor clock
Internal
timer clocks
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 T00
 T01
 T10

 T11
16-bit
counter
$F456
$F457
$F458
$F459
(Note 1)
Output compare
register
CPU writes $F457
(Note 2)
Output compare
flag and TCMP1,2
1
2
6
(Note 1)
Compare register
latch
Note:
$F457
The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.
The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this example).
Figure 6-4 Timer state timing diagram for output compare
Internal
processor clock
Internal
timer clocks
 T00
 T01
 T10

 T11
16-bit
counter
$FFFF
$0000
$0001
$0002
Timer overflow
flag
Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by
a read of the timer status register during the internal processor clock high time, followed by a read of the
counter low register.
Figure 6-5 Timer state timing diagram for timer overflow
TPG
MC68HC05F32
16-BIT PROGRAMMABLE TIMER
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6
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
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7
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DTMF/MELODY GENERATOR
7.1
Introduction
The DTMF/melody generator (DMG) is a multi-functional tone generator built into the
MC68HC05F32 MCU which supports DTMF dialling, melody-on-hold and pacifier tone functions.
7.1.1
7
Features
•
4 row and 4 column frequencies for DTMF dialling
•
24 row and 24 column frequencies for dual tone melody
•
28 frequencies for pacifier tone to acknowledge button pressed for pulse dialling
•
Power saving mechanism for output disable condition
•
3.579MHz/2 operation
•
6-bit D/A converter and 28 time steps for sine wave generation
•
Sine wave or square wave selectable output for melody (or DTMF)
•
Single or dual tone capability for melody (or DTMF)
TPG
MC68HC05F32
DTMF/MELODY GENERATOR
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7.2
Functional description
As shown in Figure 7-1, the DMG consists of 2 tone generation paths (the column and row paths).
One path generates the row tone and the other the column tone, whose frequencies are
determined by the values in the frequency control registers FCR and FCC respectively. The tones
allowed at the TNO output are single/dual sine/square wave tones of DTMF and melody
frequencies, whereas at the TNX output, only single square wave tones are allowed. The method
of tone generation for the two paths is almost the same, and is described as follows.
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7
To generate a sine wave tone with programmable frequency in a path, the internal clock (i.e. the
3.58MHz/2) is first divided by a frequency divider according to a number on the register (FCR or
FCC). The output of the divider is a periodic pulse train whose frequency is the sampling rate of
the desired ‘staircase sine wave’. This pulse train, in turn, clocks a divide-by-28 binary counter
(PLA scanner) whose 28 decoded outputs scan sequentially 28 memory locations of a 28x6 sine
wave generator (PLA) in 28 time steps (M). The six resulting digital sine wave bits are then fed
separately to a 6-bit resistor ladder to produce a current signal.
The method for generating a square wave tone in a path is similar to that of a sine wave tone
except that only the most significant bit of a sine wave PLA is fed to the 6-bit resistor ladder to
produce a current signal (the other 5 least significant bits are masked by the sine/square wave
select). Using this method, a square wave tone can be produced which has exactly the same
frequency and phase as a sine wave tone, and uses the same frequency control register value.
After obtaining the current signals from the row and column paths, the row current signal is first
attenuated by 2dB. It is then summed with the column current signal, and is finally fed to an active
7 KHz low pass filter to reduce harmonic distortion (note that square wave tones are also passed
through this filter). The resulting DTMF or melody signal is output through the TNO pin which is
normally connected to a speech circuit.
The generator provides not only DTMF and melody but also a square wave pacifier tone (ToneX).
This signal is also extracted from the most significant bit of the sine wave PLA of the row path, but
is not passed through the filter. The ToneX signal is output through the TNX pin which is normally
connected to a loudspeaker.
TPG
MOTOROLA
7-2
DTMF/MELODY GENERATOR
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3.58 MHz/2
msb
Row
frequency
divider
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PLA
scanner
6
Sine wave
PLA
28 x 6 bit
Sine/square
wave
select
TNX
MUX
lsb
6-bit
resistor
ladder
5
Current summer
+
active low pass
filter
FCR register
FCC register
Data
validator
TGER
MS1
TGEC
MS0
TNO
7
+
TNOE
Tristate
control
5
STOP
Row
frequency
divider
PLA
scanner
Sine wave
PLA
28 x 6 bit
6
Sine/square
wave
select
6
6-bit
resistor
ladder
High group
pre-emphasis
Figure 7-1 DTMF/melody generator (DMG) block diagram
TPG
MC68HC05F32
DTMF/MELODY GENERATOR
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7.3
DMG registers
The DMG has two registers (row frequency control register and column frequency control register)
for row and column frequency selection respectively, and one register (tone control register) for
tone output control and mode selection.
7.3.1
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Row and column frequency control registers
Row frequency control
register (FCR)
7
Column frequency control
register (FCC)
Address
bit 7
bit 6
bit 5
$000D
0
0
0
Address
bit 7
bit 6
bit 5
$000E
0
0
0
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
FCR4 FCR3 FCR2 FCR1 FCR0 undefined
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
FCC4 FCC3 FCC2 FCC1 FCC0 undefined
FCR4–FCR0 and FCC4–FCC0 control the frequency of the tone signals on the row and the
column paths respectively. The row and column paths are not exactly identical owing to the
presence of the high group pre-emphasis in the column path. In order to avoid the entry of the row
DTMF tone values to the column, and vice versa, the above cases are treated as illegal. The data
validator will disable all outputs when an illegal value is detected. The bit description for DTMF and
melody tone generation are shown in Table 7-1 and Table 7-2 respectively. It is the user’s
responsibility to ensure good programming practice by initialising all registers to contain legal
values for the desired function.
7.3.2
Tone control register (TNCR)
This register controls the internal configuration and tone output timing of the DTMF/melody
generator.
Tone control register
(TNCR)
Address
bit 7
bit 6
$000F
MS1
MS0
bit 5
bit 4
bit 3
TGER TGEC TNOE
bit 2
0
bit 1
0
bit 0
0
State
on reset
0000 0000
MS1, MS0 — Melody select for operation
The MS0 and MS1 bits control the mode of operation of the DTMF/melody generator. There are
sine wave, square wave 1, square wave 2 and square wave 3 modes. They are specified as shown
in Table 7-3.
TPG
MOTOROLA
7-4
DTMF/MELODY GENERATOR
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When square wave 2 or square wave 3 mode is selected, the TNX pin is activated. The idle state
for TNX is a logic high. The final state of the TNX pin is still dependent on the values of TGER,
TGEC (see Table 7-4), FCR and FCC bits (when illegal values are input).
The state of the TNO pin depends on the value of the TNOE bit. After a RESET, the TNOE is
cleared and the TNO pin is tristate. When TNOE is set, the TNO output is activated. If the TGER
and TGEC bits are held low and TNOE is set, the dc offset of VDD/2 appears at TNO pin. In STOP
mode, the TNX pin is high and the TNO pin is tristate.
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When both MS1 and MS0 are set (square wave 3), the generator can generate both single tone
melody at the column path, and ToneX at the row path simultaneously.
TGER — Tone generator enable row path
1 (set)
–
Row path on
0 (clear) –
Row path off
7
TGEC — Tone generator enable column path
1 (set)
–
Column path on
0 (clear) –
Column path off
TNOE — Tone output enable
1 (set)
–
TNO on
0 (clear) –
TNO off
Table 7-1 Bit description for DTMF generation
FCR
register
FCC
register
$00
$01
$02
$03
$10
$11
$12
$13
Tone
fR1
fR2
fR3
fR4
fC1
fC2
fC3
fC4
Standard
frequency
(Hz)
697.0
770.0
852.0
941.0
1209.0
1336.0
1477.0
1633.0
Tone output Frequency
frequency (Hz) deviation
694.8
770.1
854.2
940.0
1206.0
1331.7
1486.5
1639.0
–0.32
0.02
0.03
–0.11
–0.244
–0.324
0.645
0.367
Note: The legal values in the FCR register column are illegal to the FCC register,
and vice versa. An input of illegal values to these registers will produce a
high at TNX output and VDD /2 at TNO output (TNOE = 1)
TPG
MC68HC05F32
DTMF/MELODY GENERATOR
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Freescale Semiconductor, Inc.
.
Table 7-2 Bit description for melody generator
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7
FCR/FCC
register
Tone
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
D#5
E5
F5
F#5
G5
G#5
A5
A#5
B5
C6
C#6
D6
D#6
E6
F6
F#6
G6
G#6
A6
A#6
B6
C7
C#7
D7
Standard Tone output Frequency
frequency frequency deviation
(Hz)
(Hz)
(%)
622.3
620.6
–0.28
659.3
659.0
–0.05
698.5
694.8
–0.53
740.0
743.3
0.44
784.0
779.5
–0.57
830.6
830.1
–0.06
880.0
875.6
–0.50
932.0
926.4
–0.64
987.8
983.4
–0.45
1046.5
1047.9
0.13
1108.7
1102.1
–0.60
1174.7
1183.7
0.77
1244.5
1253.3
0.71
1318.5
1331.7
1.00
1396.9
1389.6
–0.52
1480.0
1486.5
0.44
1568.0
1559.0
–0.57
1661.2
1682.1
1.26
1760.0
1775.6
0.89
1864.7
1880.0
0.82
1975.5
1997.5
1.11
2093.0
2062.0
–1.49
2217.5
2204.2
–0.60
2349.3
2367.4
0.771
Table 7-3 Mode of operation for DMG
MS1
MS0
Mode
TNX output
0
0
sine wave
high
0
1
square wave 1
high
1
0
square wave 2
row frequency
1
1
square wave 3
row frequency
TNO output
sine wave row and
column frequency
square wave row and
column frequency
square wave row and
column frequency
square wave column
frequency
TPG
MOTOROLA
7-6
DTMF/MELODY GENERATOR
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TGER, TGEC — Tone generation enable for row and column paths
When both bits are held low, the DMG is disabled by forcing the two frequency counters and the
two PLA scanning counters to their reset states. The DMG should then consume zero dynamic
power, if the TNOE bit is also cleared.
When a TGE bit for a path is held high (provided that the value in the frequency control register
for that path is legal), the generator is enabled. All the counters associated with that path are then
run from their reset states.
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The reset state of a frequency counter defines the time=0 state of the time step, whereas at their
reset state, the PLA scanning counters, scanning the memory location, contain the dc values of
the staircase sine wave.
In DTMF dialling, the row and column tone values are first entered to the FCR and FCC registers.
The TGER and TGEC bits are then set or reset simultaneously to achieve dual tone multiple
frequency. Similarly, in melody generation, one path is chosen as the high part, and the other as
the low part. The TGER and TGEC bits are then set and reset according to the rhythm required by
the musical piece. One can exhibit only single tone melody by disabling either TGER or TGEC
permanently. The DTMF column and row frequency tones can also be output separately for testing
by enabling just the one path.
7
Table 7-4 Effect of tone generation on DMG
TGER
0
0
1
1
7.4
TGEC Row Path
0
1
0
1
off
off
active
active
Column
Path
off
active
off
active
Operation of the DMG
The DMG is recommended to be operated using the following procedures:
To operate melody generation, the choice of sine wave or square wave output mode is totally up
to the user’s taste. The sine wave melody has a sound like a flute, whereas the square wave
melody possesses much richer harmonics. The required tones are selected through the FCR and
FCC registers. The selected tone is output when the corresponding TGER or TGEC bit and TNOE
bit are set. The FCR register should contain the value representing the tone output frequency and
the FCC register should contain a value of $03 or greater to ensure the output is not blocked by
the data validator.
TPG
MC68HC05F32
DTMF/MELODY GENERATOR
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7.5
DMG during WAIT mode
The DMG is still active during the WAIT mode.
7.6
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DMG during STOP mode
In STOP mode the oscillator is stopped causing the DMG to cease function.
7
TPG
MOTOROLA
7-8
DTMF/MELODY GENERATOR
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8
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LIQUID CRYSTAL DISPLAY DRIVER MODULE
The LCD driver module on the MC68HC05F32 supports 40 frontplanes and 4 backplanes,
allowing a maximum of 160 LCD segments. Each segment is controlled by a corresponding bit in
the LCD RAM. The mode of operation is determined by the values set in the LCD control register
at $1E.
After reset and on leaving standby, the drivers are configured in the default duplex mode, 1/2 bias
with 2 backplanes. At power-up or after reset, the ON/OFF control bits for the internal and external
VLCD voltage (INTVLCD and EXTVON) are cleared, disabling the LCD drivers. Figure 8-1 shows
a block diagram of the LCD system. At power-up or after reset the LCD port’s control bits are
cleared, which disables the LCD frontplane drivers.
Internal data bus
Internal address bus
8
8
13
LCD
RAM
Backplane
driver
Segment
driver
Voltage
generator
Internal
signals
BP3
BP2
BP1
BP0
Control
logic
FP17
V LCD
FP0
Figure 8-1 LCD system block diagram
TPG
MC68HC05F32
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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8.1
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8
LCD RAM
Data to be displayed on the LCD must be written into the LCD RAM. The LCD RAM is comprised
of 20 bytes of RAM (in the MC68HC05F32’s memory map) at $0054 – $0067. The 160 bits in the
LCD RAM correspond to the 160 segments that can be driven by the frontplane/backplane drivers.
Table 8-1 shows how the LCD RAM is organized. Writing a ‘1’ to a given location will result in the
corresponding display segment being activated when the EXTVON or INTVLCD bit is set. The
LCD RAM is a dual port RAM that interfaces with the internal address and data buses of the MCU.
It is possible to read from LCD RAM locations for scrolling purposes.
Table 8-1 LCD RAM organization
LCD RAM
Data
Address
bit 7
bit 6
$54
FP1-BP3
FP1-BP2
bit 5
$55
FP3-BP3
FP3-BP2
FP3-BP1
FP3-BP0
FP2-BP3
FP2-BP2
FP2-BP1
FP2-BP0
$56
FP5-BP3
FP5-BP2
FP5-BP1
FP5-BP0
FP4-BP3
FP4-BP2
FP4-BP1
FP4-BP0
$57
FP7-BP3
FP7-BP2
FP7-BP1
FP7-BP0
FP6-BP3
FP6-BP2
FP6-BP1
FP6-BP0
$58
FP9-BP3
FP9-BP2
FP9-BP1
FP9-BP0
FP8-BP3
FP8-BP2
FP8-BP1
FP8-BP0
$59
FP11-BP3
FP11-BP2
FP11-BP1
FP11-BP0
FP10-BP3
FP10-BP2
FP10-BP1
FP10-BP0
$5A
FP13-BP3
FP13-BP2
FP13-BP1
FP13-BP0
FP12-BP3
FP12-BP2
FP12-BP1
FP12-BP0
FP1-BP1
bit 4
bit 3
bit 2
FP1-BP0
FP0-BP3
FP0-BP2
bit 1
FP0-BP1
bit 0
FP0-BP0
$5B
FP15-BP3
FP15-BP2
FP15-BP1
FP15-BP0
FP14-BP3
FP14-BP2
FP14-BP1
FP14-BP0
$5C
FP17-BP3
FP17-BP2
FP17-BP1
FP17-BP0
FP16-BP3
FP16-BP2
FP16-BP1
FP16-BP0
$5D
FP19-BP3
FP19-BP2
FP19-BP1
FP19-BP0
FP18-BP3
FP18-BP2
FP18-BP1
FP18-BP0
$5E
FP21-BP3
FP21-BP2
FP21-BP1
FP21-BP0
FP20-BP3
FP20-BP2
FP20-BP1
FP20-BP0
$5F
FP23-BP3
FP23-BP2
FP23-BP1
FP23-BP0
FP22-BP3
FP22-BP2
$60
FP25-BP3
FP25-BP2
FP25-BP1
FP25-BP0
FP24-BP3
FP24-BP2
FP24-BP1
FP24-BP0
$61
FP27-BP3
FP27-BP2
FP27-BP1
FP27-BP0
FP26-BP3
FP26-BP2
FP26-BP1
FP26-BP0
$62
FP29-BP3
FP29-BP2
FP29-BP1
FP29-BP0
FP28-BP3
FP28-BP2
FP28-BP1
FP28-BP0
$63
FP31-BP3
FP31-BP2
FP31-BP1
FP31-BP0
FP30-BP3
FP30-BP2
FP30-BP1
FP30-BP0
$64
FP33-BP3
FP33-BP2
FP33-BP1
FP33-BP0
FP32-BP3
FP32-BP2
FP32-BP1
FP32-BP0
$65
FP35-BP3
FP35-BP2
FP35-BP1
FP35-BP0
FP34-BP3
FP34-BP2
FP34-BP1
FP34-BP0
$66
FP37-BP3
FP37-BP2
FP37-BP1
FP37-BP0
FP36-BP3
FP36-BP2
FP36-BP1
FP36-BP0
$67
FP39-BP3
FP39-BP2
FP39-BP1
FP39-BP0
FP38-BP3
FP38-BP2
FP38-BP1
FP38-BP0
FP22-BP1
FP22-BP0
TPG
MOTOROLA
8-2
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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8.2
LCD operation
The LCD driver module can operate in four modes providing different multiplex ratios and number
of backplanes as follows:
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•
1/2 bias, 2 backplanes
•
1/3 bias, 2 backplanes
•
1/3 bias, 3 backplanes
•
1/4 bias, 4 backplanes
The operating mode is selected at power on using the multiplex ratio bits (MUX3 and MUX4) in
the LCD control register as shown in Table 8-4.
It is recommended that the EXTVON and INTVLCD bits in the LCD register are not set (display is
disabled) until the multiplex rate is selected. The voltage levels required for the different multiplex
rates are generated internally by a resistive divider chain between VLCD and VSS.
The 2-way multiplex with 1/3 bias and the three and four-way multiplex options require four voltage
levels, whereas the two-way multiplex with 1/2 bias needs only three levels. Resistors R1, R2 and
R3 are valued at 20kΩ ±40%. Figure 8-2 shows the resistive divider chain network that is used to
produce the various LCD waveforms outlined in Section 8.3.
8
The LCD drivers can operate with an external VLCD supply when EXTVON = 1, or with an internally
generated LCD voltage when INTVLCD = 1. The EXTVON option is useful when a display with
particular thresholds is being used. The LCD controller is enabled if the EXTVON bit or the
INTVLCD bit is set. Table 8-2 shows the different modes of operation depending on the bits
EXTVON and INTVLCD of the LCD control register.
Table 8-2 LCD controller operating modes
EXTVON INTVLCD
0
0
1
1
0
1
0
1
LCD
Internal voltage
controller
generator
off
off
on
on
on
off
on
on
Resistor chain
connected with
—
internal VLCD
VLCD pin
both (for test)
Note:
The external voltage VLCD may not exceed the positive power supply voltage, VDD.
Note:
If both bits INTVLCD and EXTVON are set, an externally applied voltage source can
cause damage to the LCD drivers.
.
TPG
MC68HC05F32
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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8-3
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Freescale Semiconductor, Inc.
VLCD
int. gen. VLCD
EXTVON
INTVLCD
V LCD
R3
V2
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R2
2 BP, 1/2 Bias
V1
R1
VSS
8
Figure 8-2 Voltage level selection
8.3
Timing signals and LCD voltage waveforms
The LCD timing signals are all derived from the main system clock. The frame rate will be fOSC/216,
therefore, if fOSC = 3.579 MHz, the frame rate will be 54.6 Hz for two and four-way multiplexing and
72.8 Hz for three-way multiplexing (see Table 8-4). An extra divide-by-two stage can be included
in the LCD clock generator by setting FDISP in the LCD register. This will result in the frame rate
being halved. For example, when three-way multiplexing is used, a frame rate of 36.4 Hz instead
of 72.8 Hz can be obtained. See Section 8.4.
Figure 8-3 to Figure 8-6 show the backplane waveforms and some examples of frontplane
waveforms for each of the operating modes.
The backplane waveforms are continuous and repetitive (every frame); they are fixed within each
operating mode and are not affected by the data in the LCD RAM.
The frontplane waveforms are dependent on the LCD segments to be driven as defined in the LCD
RAM. Each ‘on’ segment must have a differential driving voltage (BP–FP) applied to it once in each
frame; the LCD driver module hardware uses the data in the LCD RAM to construct the frontplane
waveform to meet this criterion.
TPG
MOTOROLA
8-4
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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V DD /VLCD
BP0
V2
V0
V DD /VLCD
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BP1
V2
V0
ON
OFF
V DD /VLCD
FPx, example 1
1 Frame
V2
V0
V DD /VLCD
FPx, example 2
8
V2
V0
V DD /VLCD
FPx, example 3
V2
V0
V DD /VLCD
FPx, example 4
V2
V0
Note:
In this mode V1=V2
Figure 8-3 LCD waveform with 2 backplanes, 1/2 bias
TPG
MC68HC05F32
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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V DD /VLCD
V2
BP0
V1
V0
V DD /VLCD
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8
V2
BP1
V1
ON
V0
OFF
1 Frame
FPx, example 1
V2
V1
V DD /VLCD
FPx, example 2
V2
V1
V0
V DD /VLCD
FPx, example 3
V2
V1
V0
V DD /VLCD
V2
FPx, example 4
V1
V0
Figure 8-4 LCD waveform with 2 backplanes, 1/3 bias
TPG
MOTOROLA
8-6
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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V DD /VLCD
V2
BP0
V1
V0
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V DD /VLCD
BP1
V2
V1
V0
V DD /VLCD
V2
BP2
ON
OFF
1 Frame
V1
8
V0
V DD /VLCD
V2
FPx, example 1
V1
V0
V DD /VLCD
V2
FPx, example 2
V1
V0
V DD /VLCD
V2
FPx, example 3
V1
V0
Figure 8-5 LCD waveform with 3 backplanes
TPG
MC68HC05F32
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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V DD /VLCD
V2
BP0
V1
V0
V DD /VLCD
V2
BP1
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ON
OFF
V1
V0
1 Frame
V DD /VLCD
V2
BP2
V1
V0
8
V DD /VLCD
V2
BP3
V1
V0
V DD /VLCD
FPx, example 1
V2
V1
V0
V DD /VLCD
V2
FPx, example 2
V1
V0
V DD /VLCD
V2
FPx, example 3
V1
V0
Figure 8-6 LCD waveform with 4 backplanes
TPG
MOTOROLA
8-8
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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8.4
LCD control register (LCD)
Address
LCD control register (LCD)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$001E WTLCDO FSEL1 FSEL0 INTVLCD FDISP MUX4 MUX3 EXTVON 0000 0000
WTLCDO — WAIT mode LCD only
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1 (set)
–
0 (clear) –
The SPI, the SCI, the second 16-bit timer and the A/D converter are
turned off in WAIT mode.
The SPI, the SCI, the second 16-bit timer and the A/D converter
remain active during WAIT mode.
If this bit is set, the SPI, the SCI, the second 16-bit timer and the A/D converter are turned off in
WAIT mode, reducing the power consumption, as only the core timer, the first 16-bit timer (timerA),
the DMG and the LCD controller remain active.
8
FSEL1, FSEL0 — LCD operation frequency
These bits select the LCD operation frequency according to Table 8-3. The frequency shown in the
right columns are calculated for an external frequency of 3.579 MHz.
Table 8-3 Frequency selection
FSEL1: FSEL0
00
10
01
11
Framefrequency Frame frequency
(2, 4 backplanes) (3 backplanes)
FOSC /216
4F OSC /(3X216 )
FOSC /215
4F OSC /(3X215 )
FOSC /214
4F OSC /(3X214 )
FOSC /29
4F OSC /(3X29)
Frequency for
2,4 backplanes
54.6 Hz
109.2 Hz
218.4 Hz
6990 Hz
Frequency for
3 backplanes
72.8 Hz
145.6 Hz
291.3 Hz
9320 Hz
INTVLCD — Internal voltage generator ON/OFF
1 (set)
–
0 (clear) –
The display is on and an internal voltage generator is activated.
The internal voltage generator is turned off.
When the INTVLCD bit is set, the display controller is on and an internal voltage generator is
activated and connected to the resistor chain (VLCD = 3V approx., if VDD > 3V). See Table 8-2.
TPG
MC68HC05F32
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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FDISP — Display frequency
1 (set)
–
0 (clear) –
Extra divide by two stage is included in the LCD clock generator
when this bit is set, giving a reduced frame rate.
Default frame rate is used.
For example, in the 3-way multiplexing mode, a frame rate of 36.8 Hz instead of 72.8 Hz can be
achieved.
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MUX4, MUX3 — Multiplex ratio
These two bits select the multiplex ratio to be 2, 3 or 4 backplanes. See Table 8-4.
Table 8-4 Multiplex ratio/backplane selection
MUX4
0
0
1
1
8
MUX3
0
1
0
1
Backplanes
2
3
4
2
Bias
1/2
1/3
1/3
1/3
Frequency
54.6 Hz
72.8 Hz
54.6 Hz
54.6 Hz
EXTVON — External LCD voltage ON/OFF
1 (set)
–
0 (clear) –
External LCD voltage is connected.
External LCD voltage is disconnected.
Clearing this bit disconnects the voltage generator resistor chain from the external VLCD. See
Table 8-2.
8.5
LCD during WAIT mode
The LCD drivers function normally during WAIT mode and will keep the display active if the
EXTVON bit or the INTVLCD bit is set.
8.6
LCD during STOP mode
During STOP mode the LCD controller is disabled. The driver outputs are discharged by the
resistor chain.
TPG
MOTOROLA
8-10
LIQUID CRYSTAL DISPLAY DRIVER MODULE
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9
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A/D CONVERTER
The analog to digital converter system consists of a 12-channel, multiplexed input to a successive
approximation A/D converter. Eight of the A/D input channels are connected to pins PD0–PD7 and
the particular input to be selected is determined by the setting/clearing of the CHx bits in the A/D
status/control register at $4F. A further four channels are available internally for test purposes. In
addition to the A/D status/control register (ADSCR) there is one 8-bit result data register at
address $4E.
The A/D converter is ratiometric and a dedicated pin, VREFH, is used to supply the upper
reference voltage level of each analog input. The lower voltage reference point, VREFL, is internally
connected to the AVSS pin. An input voltage equal to or greater than VRH converts to $FF (full
scale) with no overflow indication. For ratiometric conversions, the source of each analog input
should use VREFH as the supply voltage and be referenced to AVSS.
9
The A/D converter can operate from either the bus clock or an internal RC type oscillator. The
internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADRC)
and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is
too low to provide accurate results (see Section 9.2.1). When the A/D converter is not being used
it can be disconnected using the ADON bit in the ADSCR register, in order to save power (see
Section 9.2.1).
9.1
A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital-to-analog capacitor array, a
comparator and a successive approximation register (SAR). See Figure 9-1.
The A/D reference inputs is applied to a precision internal digital-to-analog converter. Control logic
drives this D/A converter and the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($4E), and
the conversion complete flag, COCO, is set in the A/D status/control register ($4F).
TPG
MC68HC05F32
A/D CONVERTER
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PD7/AN7
PD6/AN6
PD5/AN5
PD4/AN4
PD3/AN3
PD2/AN2
PD1/AN1
PD0/AN0
(VRH +V RL )/2
VRH
VRL = AVSS
8-bit capacitive DAC
with sample and hold
Analog MUX
(Channel assignment)
V RH
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Successive approximation
register and control
Result
A/D status/control register (ADSCR) $4F
CH0
CH1
CH2
CH3
0
ADON ADRC COCO
V RL = AV SS
9
A/D result register (ADDATA) $4E
Figure 9-1 A/D converter block diagram
Caution: Any write to the A/D status/control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared, thus the A/D is disabled.
TPG
MOTOROLA
9-2
A/D CONVERTER
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9.2
A/D registers
9.2.1
A/D status/control register (ADSCR)
Address
A/D status/control (ADSCR)
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bit 7
bit 6
bit 5
$004F COCO ADRC ADON
bit 4
0
bit 3
CH3
bit 2
CH2
bit 1
CH1
bit 0
CH0
State
on reset
0000 0000
COCO — Conversion complete flag
Each channel conversion takes 32 clock cycles at fOP, where fOP is equal to or greater than 1MHz.
1 (set)
–
COCO flag is set each time a conversion is complete, allowing the
new result to be read from the A/D result data register ($4E). The
converter then starts a new conversion.
0 (clear) –
COCO is cleared by reading the result data register or writing to the
status/control register.
Reset clears the COCO flag.
9
ADRC — A/D RC oscillator control
If the MCU bus frequency is less than 1MHz, an internal RC oscillator must be used for the A/D
conversion clock. This selection is made by setting the ADRC bit in ADSCR. The ADRC bit allows
the user to control the A/D RC oscillator.
1 (set)
–
The A/D RC oscillator is turned on and, if ADON is set, the A/D runs
from the internal RC oscillator clock (see Table 9-1).
0 (clear) –
The A/D RC oscillator is turned off and, if ADON is set, the A/D runs
from the CPU clock.
When the A/D RC oscillator is turned on, it takes a time tRCON to stabilize (see Table 16-5). During
this time A/D conversion results may be inaccurate.
Table 9-1 A/D clock selection
ADRC
ADON
0
0
1
1
0
1
0
1
RC
A/D
Comments
oscillator converter
OFF
OFF
A/D switched off.
OFF
ON
A/D using CPU clock.
ON
OFF
Allows the RC oscillator to stabilize.
ON
ON
A/D using RC oscillator clock.
TPG
MC68HC05F32
A/D CONVERTER
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When the internal RC oscillator is being used as the conversion clock, the following limitations
apply.
1) Due to the frequency tolerance of the RC oscillator and its asynchronism
with regard to the MCU bus clock, the conversion complete flag (COCO)
must be used to determine when a conversion sequence has been
completed.
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9
2) The conversion process runs at the nominal 1.5MHz rate but the conversion
results must be transferred to the MCU result registers synchronously with
the MCU bus clock in order that conversion time is limited to a maximum of
one channel per bus clock cycle.
3) If the system clock is running faster than the RC oscillator, the RC oscillator
should be switched off and the system clock used as the conversion clock.
ADON — A/D converter on
The ADON bit allows the user to enable/disable the A/D converter.
1 (set)
–
A/D converter is switched on.
0 (clear) –
A/D converter is switched off.
When the A/D converter is switched on, it takes a time tADON for the current sources to stabilize
(see Table 16-5). During this time A/D conversion results may be inaccurate.
Power-on or external reset will clear the ADON bit, thus disabling the A/D converter.
CH3 – CH0 — A/D channel selection
The CH3–CH0 bits allow the user to determine which channel of the A/D converter multiplexer is
selected (see Table 9-2).
Table 9-2 A/D channel assignment
CH3
0
0
0
0
0
0
0
0
1
1
1
1
CH2
0
0
0
0
1
1
1
1
1
1
1
1
CH1
0
0
1
1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
0
1
0
1
Channel
0
1
2
3
4
5
6
7
8
9
10
11
Signal
AD0/PD0
AD1/PD1
AD2/PD2
AD3/PD3
AD4/PD4
AD5/PD5
AD6/PD6
AD7/PD7
V REFH
(V REFH +V REFL )/2
V REFL
Factory test
TPG
MOTOROLA
9-4
A/D CONVERTER
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9.2.2
A/D result data register (ADDATA)
Address
A/D data register
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bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
$004E
bit 1
bit 0
State
on reset
Undefined
The A/D data register is a read-only register which is used to store the result of an A/D conversion.
The result is loaded into the register from the SAR and the conversion complete flag (COCO) in
the ADSCR register is set.
Caution: Performing a digital read of port D with levels other than VDD or VSS on the pins will
result in greater power dissipation during the read cycles.
9.3
A/D converter during WAIT mode
The A/D converter continues to operate normally during WAIT mode. To decrease power
consumption during WAIT, it is recommended that both the ADON and ADRC bits in the ADSTAT
register are cleared, if the A/D converter is not being used. If the A/D converter is being used and
the system clock frequency is above 1MHz, the ADRC bit should be cleared to disable the internal
RC oscillator.
9.4
9
A/D converter during STOP mode
In STOP mode the comparator and charge pump are turned off and the A/D converter ceases to
operate. Any pending conversion is aborted. When the clock begins oscillation upon leaving the
STOP mode, a finite amount of time passes before the A/D circuits stabilize enough to provide
conversions to the specified accuracy. Normally, the delays built into the MC68HC05F32 are
sufficient for this purpose, therefore no explicit delays need to be built into the software.
9.5
A/D analog input
The external analog voltage value to be processed by the A/D converter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
time switch, as shown in Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling,
the analog value is stored on the capacitor and held until the end of conversion. During this hold
time, the analog input is disconnected from the internal A/D system and the external voltage
source sees a high impedance input.
TPG
MC68HC05F32
A/D CONVERTER
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The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance
of 50 kΩ and a capacitance of at least 10pF. (It should be noted that these are typical values
measured at room temperature).
Input protection device
Analog
input
pin
(AD0–AD7)
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< 2pF
≥ 50kΩ
+ ∼20V
– ∼0.7V
10 µA
junction
leakage
≥ 10pF
DAC
capacitance
V REFL = AVSS
Note:
9
The analog switch is closed during the 12 cycle sample
time only.
Figure 9-2 Electrical model of an A/D input pin
TPG
MOTOROLA
9-6
A/D CONVERTER
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SERIAL PERIPHERAL INTERFACE
10.1
Overview and features
The SPI is a synchronous interface which allows several SPI microcontrollers or SPI-type
peripherals to be interconnected. In a serial peripheral interface, separate wires (signals) are
required for data and clock. In the SPI format, the clock is not included in the data stream and must
be furnished as a separate signal. The high-end SPI system may be configured either as a master
or as a slave.
Features,
10
•
Full-duplex, 3-wire synchronous transfers
•
Master or slave operation
•
Master bit frequency, fOP/2
•
Slave bit frequency, fOP
•
Four programmable master bit rates
•
Programmable clock polarity and phase
•
End-of-transmission interrupt flag
•
Write collision flag protection
•
Master-master mode fault protection
•
Easy interface to simple expansion parts (PLLs, D/As, latches, display drivers, etc.)
TPG
MC68HC05F32
SERIAL PERIPHERAL INTERFACE
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10.2
SPI signal descriptions
Four I/O pins located at port C (PC4 - PC7) are associated with the SPI data transfers. They are
the serial clock (SCK), the master in/slave out data line (MISO), the master out / slave in data line
(MOSI), and the active-low slave select (SS). When the SPI system is not utilized (SPE bit cleared
in the serial peripheral control register), the four pins (MISO, MOSI, SCK, and SS) are configured
as general-purpose I/O pins. The four SPI signals are discussed in the following paragraphs for
both master mode and slave mode of operation.
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10.2.1
Master in slave out (MISO)
The MISO line is configured as an input, in a master device, and as an output in a slave device. It
is one of the two lines that transfer serial data in one direction. The MISO line of a slave device is
placed in the high-impedance state if the slave is not selected.
10.2.2
Master out slave in (MOSI)
The MOSI line is configured as an output in a master device, and as an input in a slave device. It
is one of the two lines that transfer serial data in one direction.
10
10.2.3
Serial clock (SCK)
The serial clock is used to synchronize data movement both in and out of the device through its
MOSI and MISO lines. The master and slave devices are capable of exchanging a byte of
information during a sequence of eight clock cycles. Since SCK is generated by the master device,
this line becomes an input on a slave device.
As shown in Figure 10-1, four different timing relationships may be selected by control bits CPOL
and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must
operate with the same timing. The master device always places data on the MOSI line a half cycle
before the clock edge (SCK), in order for the slave device to latch the data.
Two bits (SPR0 and SPR1) in the SPI control register (SPCR) of the master device select the clock
rate. In a slave device, SPR0 and SPR1 have no effect on the operation of the SPI.
TPG
MOTOROLA
10-2
SERIAL PERIPHERAL INTERFACE
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SS
SS
SCK
(CPOL = 0, CPHA = 0)
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SCK
(CPOL = 0, CPHA = 1)
SCK
(CPOL = 1, CPHA = 0)
SCK
(CPOL = 1, CPHA = 1)
MISO/
MOSI
MSB
6
5
4
3
2
1
10
LSB
Internal strobe for data capture (DOD = 0)
Figure 10-1 Data clock timing diagram
TPG
MC68HC05F32
SERIAL PERIPHERAL INTERFACE
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10.2.4
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10
Slave select (SS)
The slave select (SS) input line is used to select a slave device. It must be in the active low state
prior to data transactions and must stay low for the duration of the transaction. The SS line on the
master must be tied high. If it goes low, a mode fault error flag (MODF) is set in the serial peripheral
status register (SPSR). When CPHA = 0, the shift clock is the logical OR of SS and SCK. In this
clock phase mode, SS must go high between successive characters in an SPI message. When
CPHA = 1, SS may be left low for several SPI characters. If there is only one SPI slave MCU, its
SS line may be tied to VSS, provided CPHA = 1 clock modes are used.
10.3
Functional description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master
device transmits data to a slave device via the MOSI line, the slave device responds by sending
data to the master device via the master’s MISO line. This implies full duplex transmission with
both data out and data in synchronized to the same clock signal. Thus, the byte transmitted is
replaced by the byte received, eliminating the need for separate transmitter-empty and
receiver-full status bits. A single status bit (SPIF) is used to signify that the I/O operation has been
completed.
The SPI is double buffered on read, but not on write. If a write is performed during data transfer,
the transfer is not interrupted, and the write will be unsuccessful. This condition will cause the write
collision status bit (WCOL) in the SPSR to be set. After a data byte is shifted, the SPIF flag in the
SPSR is set.
In master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the
SPCR, until data is written to the shift register. Eight clocks are then generated to shift the eight
bits of data, after which SCK goes idle again.
In slave mode, the slave start logic receives a logic low on the SS pin and a clock input at the SCK
pin, thus synchronizing the slave to the master. Data from the master is received serially via the
slave MOSI line and is loaded into the 8-bit shift register. The data is then transferred, in parallel,
from the 8-bit shift register to the read buffer. During a write cycle, data is written into the shift
register, then the slave waits for a clock train from the master to shift the data out on the slave’s
MISO line.
TPG
MOTOROLA
10-4
SERIAL PERIPHERAL INTERFACE
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MOSI/
PC5
Internal MCU clock
S
M
MISO/
PC4
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msb
M
S
8-bit shift register
Contro l
logic
SCK/
PC6
Divider
/2/4/16/32
lsb
Read data buffer
S
M
SS/
PC7
Clock logic
Select
SPI control
SPI
status
register
10
SPIF
WCOL
MODF
SPIE
SPE
DOD
MSTR CPOL CPHA SPR1 SPR0
SPI control register
SPI interrupt
request
Internal
data bus
Figure 10-2 Serial peripheral interface block diagram
TPG
MC68HC05F32
SERIAL PERIPHERAL INTERFACE
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Master
Slave
MISO
MISO
8-bit shift register
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10
8-bit shift register
MOSI
MOSI
SCK
SCK
SPI clock generator
V DD
SS
SS
Figure 10-3 Serial peripheral interface master–slave interconnection
10.4
SPI registers
There are three registers in the serial peripheral interface which provide control, status and data
storage functions. These registers are called: the serial peripheral control register (SPCR), the
serial peripheral status register (SPSR) and the serial peripheral data I/O register (SPDAT).
10.4.1
Control register (SPCR)
SPI control register (SPCR)
Address
bit 7
bit 6
$0044
SPIE
SPE
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
DOD MSTR CPOL CPHA SPR1 SPR0 0000 01uu
SPIE — SPI interrupt enable
1 (set)
–
SPI interrupts enabled.
0 (clear) –
SPI interrupts disabled.
When this bit is set to one, a hardware interrupt sequence is requested each time the SPIF or
MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I bit in the CC register
is set.
TPG
MOTOROLA
10-6
SERIAL PERIPHERAL INTERFACE
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SPE — SPI system enable
1 (set)
–
SPI system on.
0 (clear) –
SPI system off.
When the SPE bit is set, port C pins 4, 5, 6, and 7 are dedicated to the SPI function.
DOD — Direction of data
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This bit determines the direction of the data flow in or out of the serial shift register.
1 (set)
–
0 (clear) –
data is transferred LSB first.
data is transferred MSB first (default state).
MSTR — Master/slave mode select
1 (set)
–
0 (clear) –
master mode is selected.
slave mode is selected.
CPOL — Clock polarity
When the clock polarity bit is cleared and data is not being transferred, a steady state low value
is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle
high. This bit is also used in conjunction with the clock phase control bit to produce the desired
clock-data relationship between master and slave. See Figure 10-1.
10
CPHA — Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPOL bit can be thought of simply as inserting an inverter in series with
the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When
CPHA = 0, the shift clock is the logical OR of SCK and SS. As soon as SS goes low, the transaction
begins and the first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. Refer to Figure 10-1.
SPR1, SPR0 — SPI clock (SCK) rate select bits
If the device is a master, the two serial peripheral rate bits select one of four division ratios of the
E-clock to be used as SCK (See Table 10-1). These bits have no effect in slave mode.
TPG
MC68HC05F32
SERIAL PERIPHERAL INTERFACE
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Table 10-1 SPI rate selection
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10
10.4.2
SPR1
SPR0
0
0
1
1
0
1
0
1
E clock
divided by
2
4
16
32
Status register (SPSR)
Address
SPI status register (SPSR)
$0045
bit 7
bit 6
SPIF WCOL
bit 5
0
bit 4
MODF
bit 3
0
bit 2
0
bit 1
0
bit 0
0
State
on reset
0000 0000
SPIF — SPI interrupt request flag
The serial peripheral data transfer flag bit is set after the eighth SCK cycle in a data transfer and
it is cleared by reading the SPSR register (with SPIF set) followed by reading from or writing to the
SPI data register (SPDAT).
WCOL — Write collision
The write collision bit is used to indicate that a serial transfer was in progress when the MCU tried
to write new data into the SPDAT data register. The MCU write is disabled to avoid writing over the
data being transmitted. No interrupt is generated because the error status flag can be read upon
completion of the transfer that was in progress at the time of the error. This flag is automatically
cleared by a read of the SPSR (with WCOL set) followed by an access (read or write) to the SPDAT
register.
MODF — SPI mode error interrupt status flag
This flag is set if the SS signal goes to its active-low level while the SPI is configured as a master
(MSTR = 1). This condition is not permitted in normal operation. This flag is automatically cleared
by a read of the SPSR (with MODF set) followed by a write to the SPCR register.
TPG
MOTOROLA
10-8
SERIAL PERIPHERAL INTERFACE
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10.4.3
SPI data I/O register (SPDAT)
Address
SPI data/IO register (SPDAT)
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bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
$0046
bit 1
bit 0
State
on reset
uuuu uuuu
The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only
a write to this register will initiate transmission/reception of another byte, and this will only occur
in the master device. At the completion of transmitting a byte of data, the SPIF status bit is set in
both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first
SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer
is initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun
is lost. A write to the serial peripheral data I/O register is not buffered and places data directly into
the shift register for transmission.
10.5
SPI during WAIT mode
When the MCU enters wait mode, the CPU clock is halted. All CPU action is suspended; however,
the SPI system remains active. In fact an interrupt from the SPI causes the processor to exit the
wait mode.
10.6
10
SPI during STOP mode
When the MCU enters the stop mode, the internal oscillator is turned off, and the baud rate
generator which drives the SPI shuts down. This essentially stops all master mode SPI operation,
thus transfer is halted until the MCU exits the stop mode. If the stop mode is exited by a reset, then
the appropriate control/status bits are cleared and the SPI is disabled. If the device is in the slave
mode when the stop instruction is executed, the slave SPI will still operate. It can still accept data
and clock information in addition to transmitting its own data back to a master device.
At the end of a possible transmission with a slave SPI in the stop mode, no flags are set until the
MCU is “waked up” by an interrupt (IRQ, keyboard, LVI or CPI). Caution should be observed when
operating the SPI (as a slave) during the stop mode because none of the protection circuitry (write
collision, mode fault, etc.) is active.
TPG
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THIS PAGE LEFT BLANK INTENTIONALLY
10
TPG
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10-10
SERIAL PERIPHERAL INTERFACE
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11
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SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided with a standard
non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are
functionally independent and have their own baud rate generator; however they use the same
baud rate and data format.
The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data
bits, and one stop bit.
Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and
transmit data out (TDO).
‘Baud’ and ‘bit rate’ are used synonymously in the following description.
11.1
SCI two-wire system features
11
•
Standard NRZ (mark/space) format
•
Advanced error detection method with noise detection for noise duration of up to 1/16th bit time
•
Full-duplex operation (simultaneous transmit and receive)
•
32 software selectable baud rates
•
Software selectable word length (eight or nine bits)
•
Separate transmitter and receiver enable bits
•
Interrupt drive capability
•
Four separate enable bits for interrupt control
TPG
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Internal bus
SCI interrupt
+
$0047
(See note)
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Transmit
data register
$0047
(See note)
&
&
&
&
$0049
SCCR2
TIE
TCIE
RIE
ILIE
TE
RE
SBK
RWU
Transmit
data shift
register
TDO/
PC3
pin
+
7
6
5
4
3
2
1
0
Receive
data register
Receive
data shift
register
RDI/
PC2
pin
SCSR
$004A
7
TRDE
TE
6
TC
5
RDRF
3
4
IDLE
OR
2
NF
1
FE
Wake up
unit
7
SBK
Flag
control
Transmitter
control
Transmitter
clock
Receiver
control
Receiver
clock
Rate generator
11
TCLR
0
SCP1
SCP0 RCKB
SCR2
SCR1
SCR0
BAUD, $004B
7
R8
Note:
6
T8
5
4
M
3
WAKE
2
0
1
0
0
0
SCCR1
$0048
The serial communications data register (SCDAT) is controlled by
the internal R/W signal. It is the transmit data register when written
to and the receive data register when read.
Figure 11-1 Serial communications interface block diagram
TPG
MOTOROLA
11-2
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11.2
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SCI receiver features
•
Receiver wake-up function (idle line or address bit)
•
Idle line detection
•
Framing error detection
•
Noise detection
•
Overrun detection
•
Receiver data register full flag
11.3
SCI transmitter features
•
Transmit data register empty flag
•
Transmit complete flag
•
Send break
11.4
External connections
The external operation of the SCI block is routed through bits 2 and 3 of port C. Bits PC2 and PC3
are the receive and transmit pins for the SCI (RDI, TDO). Refer to Section 4 for a full description
of port C.
11
SCI
TCLR
0
SCP1
SCP0 RCKB
SCCR2, $0049
7
6
SCR2
TDO
5
4
3
SCR1
SCR0
RDI
2
1
0
Port C
PC2/RDI
PC3/TDO
Figure 11-2 SCI and port C
TPG
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11.5
Functional description
A block diagram of the SCI is shown in Figure 11-1. Option bits in serial control register1 (SCCR1)
select the ‘wake-up’ method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides
control bits that individually enable the transmitter and receiver, enable system interrupts and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud
rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and
receiver (see Section 11.11.5).
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11
Data transmission is initiated by writing to the serial communications data register (SCDR).
Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data
shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The
transfer of data to the transmit data shift register is synchronized with the bit rate clock. All data is
transmitted least significant bit first. Upon completion of data transmission, the transmission
complete flag (TC) in the SCSR is set (provided no pending data, preamble or break is to be sent)
and an interrupt is generated (if the transmit complete interrupt is enabled). If the transmitter is
disabled, and the data, preamble or break (in the transmit data shift register) has been sent, the
TC bit will also be set. This will also generate an interrupt if the transmission complete interrupt
enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the character being
transmitted will be completed before the transmitter gives up control of the TDO pin.
When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error
flags in the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to
detect the end of a message or the preamble of a new message, or to resynchronize with the
transmitter. A valid character must be received before the idle line condition or the IDLE bit will not
be set and idle line interrupt will not be generated.
TPG
MOTOROLA
11-4
SERIAL COMMUNICATIONS INTERFACE
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11.6
Data format
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Receive data or transmit data is the serial data that is transferred to the internal data bus from the
receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The
non-return-to-zero (NRZ) data format shown in Figure 11-3 is used and must meet the following
criteria:
–
The idle line is brought to a logic one state prior to transmission/reception of
a character.
–
A start bit (logic zero) is used to indicate the start of a frame.
–
The data is transmitted and received least significant bit first.
–
A stop bit (logic one) is used to indicate the end of a frame. A frame consists
of a start bit, a character of eight or nine data bits, and a stop bit.
–
A break is defined as the transmission or reception of a low (logic zero) for at
least one complete frame time (10 zeros for 8-bit format, 11 zeros for 9-bit).
Control bit M selects
8 or 9 bit data



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Idle line
0
1
2
3
4
5
6
7
0
8
Start
Stop Start
Figure 11-3 Data format
11
11.7
Receiver wake-up operation
The receiver logic hardware also supports a receiver wake-up function which is intended for
systems having more than one receiver. With this function a transmitting device directs messages
to an individual receiver or group of receivers by passing addressing information as the initial
byte(s) of each message. The wake-up function allows receivers not addressed to remain in a
dormant state for the remainder of the unwanted message. This eliminates any further software
overhead to service the remaining characters of the unwanted message and thus improves system
performance.
The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2
register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE)
are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU
bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do
so. Normally RWU is set by software and is cleared automatically in hardware by one of the two
methods described below.
TPG
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11-5
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11.7.1
Idle line wake-up
In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle
is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems
using this type of wake-up must provide at least one character time of idle between messages to
wake up sleeping receivers, but must not allow any idle time between characters within a message.
11
11.7.2
Address mark wake-up
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether
it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wake-up would set the MSB of the first
character of each message and leave it clear for all other characters in the message. Idle periods
may be present within messages and no idle time is required between messages for this wake-up
method.
11.8
Receive data in (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus.
The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred
to as the RT rate in Figure 11-5.
The receiver clock generator is controlled by the baud rate register, as shown in Figure 11-1;
however, the SCI is synchronized by the start bit, independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three
times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start),
as shown in Figure 11-4. The value of the bit is determined by voting logic which takes the value
of the majority of the samples. A noise flag is set when all three samples on a valid start bit or data
bit or the stop bit do not agree .
Previous bit
Present bit
RDI
Samples
Next bit
<
<
<
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16RT 1RT
8RT 9RT 10RT
16RT 1RT
Figure 11-4 SCI sampling technique used on all bits
TPG
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11-6
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16X internal sampling clock
1RT 2RT 3RT 4RT
RT clock edges for all three examples
Idle
5RT 6RT
7RT 8RT
Start
RDI
1
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1
1
1
1
1
1
1
1
1
1
Start
qualifiers
0
0
Start
0
0
Start edge
verification samples
Noise
RDI
1
1
1
1
1
1
1
1
1
1
1
Noise
0
0
1
0
0
0
0
Start
RDI
1
1
1
1
1
0
1
1
1
1
1
0
Figure 11-5 SCI examples of start bit sampling technique
11.9
Start bit detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as
the start edge verification samples in Figure 11-5). If at least two of these three verification
samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to
be idle. A noise flag is set if one of the three verification samples detect a logic one, thus a valid
start bit could be assumed with a set noise flag present.
11
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in Figure 11-5) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see Figure 11-6); therefore,
the start bit will be accepted no sooner than it is anticipated.
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $00) produced the
framing error, the start bit will not be artificially induced and the receiver must actually detect a logic
one before the start bit can be recognised (see Figure 11-7).
TPG
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Data
Expected stop
Artificial edge
Data
RDI
Start bit
Data samples
a) Case 1: receive line low during artificial edge
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Data
Expected stop
Start edge
Data
RDI
Start bit
Data samples
b) Case 2: receive line high during expected start edge
Figure 11-6 Artificial start following a framing error
Expected stop
Detected as valid start edge
Break
Start bit
RDI
11













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Data samples
Start
qualifiers
Start edge
verification
samples
Figure 11-7 SCI start bit following a break
11.10
Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in Section 11.6 and shown in Figure 11-3. The transmitter
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock.
TPG
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11-8
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11.11
SCI registers
The SCI system is configured and controlled by five registers: SCDAT, SCCR1, SCCR2, SCSR,
and BAUD.
11.11.1
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Serial communications data register (SCDAT)
Address
SCI data (SCDAT)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0047
State
on reset
undefined
The SCDAT is controlled by the internal R/W signal and performs two functions in the SCI. It acts
as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it
is written. Figure 11-1 shows this register as two separate registers, RDR and TDR. The RDR
provides the interface from the receive shift register to the internal data bus and the TDR provides
the parallel interface from the internal data bus to the transmit shift register.
The receive data register is a read-only register containing the last byte of data received from the
shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status
register is set to indicate that a byte has been transferred from the input serial shift register to the
SCDAT. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as
shown in Figure 11-1. All data is received with the least significant bit first.
The transmit data register (TDR) is a write-only register containing the next byte of data to be
applied to the transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the SCDAT is transferred to the transmit shift register (after the current byte
in the shift register has been transmitted).
11
The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as
shown in Figure 11-1. All data is received with the least significant bit first.
11.11.2
Serial communications control register 1 (SCCR1)
SCI control 1 (SCCR1)
Address
bit 7
bit 6
bit 5
bit 4
$0048
R8
T8
0
M
bit 3
WAKE
bit 2
0
bit 1
0
bit 0
0
State
on reset
0000 0000
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character
format and the receiver wake-up feature.
TPG
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R8 — Receive data bit 8
This read-only bit is the ninth serial data bit received when the SCI system is configured for nine
data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 7–0) are transferred from the serial
receive shift register to the SCI receive data register.
T8 — Transmit data bit 8
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11
This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine
data bit operation (M = 1). When the eight low order bits (bits 7–0) of a transmit character are
transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred
to the ninth bit position of the shift register.
M — Mode (select character format)
The read/write M-bit controls the character length for both the transmitter and receiver at the same
time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity
bit (see Table 11-1).
1 (set)
–
Start bit, 9 data bits, 1 stop bit.
0 (clear) –
Start bit, 8 data bits, 1 stop bit.
Table 11-1 Method of receiver wake-up
WAKE
M
0
x
1
0
1
1
Method of receiver wake-up
Detection of an idle line allows the next data type received to cause the receive
data register to fill and produce an RDRF flag.
Detection of a received one in the eighth data bit allows an RDRF flag and
associated error flags.
Detection of a received one in the ninth data bit allows an RDRF flag and
associated error flags.
x = Don’t care
WAKE — Wake-up mode select
This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or
written to any time. See Table 11-1.
1 (set)
–
Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th
(if M = 0) or the 9th (if M = 1) bit received on the Rx line is set.
0 (clear) –
Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M =
0) or 12 (if M = 1) consecutive ‘1’s on the Rx line.
TPG
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11.11.3
Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
SCI control (SCCR2)
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Address
bit 7
bit 6
$0049
TIE
TCIE
bit 5
RIE
bit 4
ILIE
bit 3
TE
bit 2
RE
bit 1
RWU
bit 0
SBK
State
on reset
0000 0000
TIE — Transmit interrupt enable
1 (set)
–
TDRE interrupts enabled.
0 (clear) –
TDRE interrupts disabled.
TCIE — Transmit complete interrupt enable
1 (set)
–
TC interrupts enabled.
0 (clear) –
TC interrupts disabled.
RIE — Receiver interrupt enable
1 (set)
–
RDRF and OR interrupts enabled.
0 (clear) –
RDRF and OR interrupts disabled.
ILIE — Idle line interrupt enable
1 (set)
–
IDLE interrupts enabled.
0 (clear) –
IDLE interrupts disabled.
11
TE — Transmitter enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO line.
Depending on the state of control bit M (SCCR1), a preamble of 10 (M = 0) or 11 (M = 1)
consecutive ones is transmitted when software sets the TE bit from a cleared state.
After loading the last byte in the serial communications data register and receiving the TDRE flag,
the user should clear TE. Transmission of the last byte will then be completed before the transmitter
gives up control of the TDO pin. While the transmitter is active, PC3 is forced to be an output.
1 (set)
–
Transmitter enabled.
0 (clear) –
Transmitter disabled.
TPG
MC68HC05F32
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RE — Receiver enable
1 (set)
–
Receiver enabled.
0 (clear) –
Receiver disabled.
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,
OR, NF and FE) are inhibited. While the receiver is enabled, PC2 is forced to be an input.
RWU — Receiver wake-up
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11
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables
the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit
discussed above (in SCCR1). When the RWU bit is set, no status flags will be set. Flags which
were set previously will not be cleared when RWU is set.
If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is
set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the address
byte stored in the receiver data register.
SBK — Send break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros
and then reverts to idle sending data. If SBK remains set, the transmitter will continually send
whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the
transmitter sends at least one high bit to guarantee recognition of a valid start bit. If the transmitter
is currently empty and idle, setting and clearing SBK is likely to queue two character times of break
because the first break transfers almost immediately to the shift register and the second is then
queued into the parallel transmit buffer.
11.11.4
Serial communications status register (SCSR)
SCI status (SCSR)
Address
bit 7
$004A
TDRE
bit 6
TC
bit 5
RDRF
bit 4
IDLE
bit 3
OR
bit 2
NF
bit 1
FE
bit 0
0
State
on reset
1100 0000
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
TPG
MOTOROLA
11-12
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TDRE — Transmit data register empty flag
This bit is set when the contents of the transmit data register are transferred to the serial shift
register. New data will not be transmitted unless the SCSR register is read before writing to the
transmit data register to clear the TDRE flag.
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If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial
communications data register will overwrite the previous value. The TDRE bit is cleared by
accessing the serial communications status register (with TDRE set) followed by writing to the
serial communications data register.
TC — Transmit complete flag
This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data
in shift register, no preamble, no break). When TC is set the serial line will go idle (continuous
MARK). The TC bit is cleared by accessing the serial communications data register (with TC set)
followed by writing to the serial communications data register. It does not inhibit the transmitter
function in any way.
RDRF — Receive data register full flag
This bit is set when the contents of the receiver serial shift register are transferred to the receiver
data register.
If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as
appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications
status register is accessed (with RDRF set) followed by a read of the serial communications data
register.
IDLE — Idle line detected flag
11
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive ‘1’s). This bit will not be set by the idle line condition when the RWU bit is set. This
allows a receiver that is not in the wake-up mode to detect the end of a message, detect the
preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by
accessing the serial communications status register (with IDLE set) followed by a read of the serial
communications data register. Once cleared, IDLE will not be set again until after RDRF has been
set, (i.e. until after the line has been active and becomes idle again).
OR — Overrun error flag
This bit is set when a new byte is ready to be transferred from the receiver shift register to the
receiver data register and the receive data register is already full (RDRF bit is set). Data transfer
is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid in
this case, but additional data received during an overrun condition (including the byte causing the
overrun) will be lost.
The OR bit is cleared when the serial communications status register is accessed (with OR set)
followed by a read of the serial communications data register.
TPG
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NF — Noise error flag
This bit is set if there is noise on a ‘valid’ start bit, any of the data bits or on the stop bit. The NF bit
is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set until
the RDRF flag is set. Each data bit is sampled three times as described in Section 11.8.
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The NF bit represents the status of the byte in the serial communications data register. For the byte
being received (shifted in) there will be also a ‘working’ noise flag, the value of which will be
transferred to the NF bit when the serial data is loaded into the serial communications data
register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and can
be used to generate the interrupt.
The NF bit is cleared when the serial communications status register is accessed (with NF set)
followed by a read of the serial communications data register.
FE — Framing error flag
This bit is set when the word boundaries in the bit stream are not synchronized with the receiver
bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE
bit reflects the status of the byte in the receive data register and the transfer from the receive shift
register to the receive data register is inhibited by an overrun. The FE bit is set during the same
cycle as the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag
inhibits further transfer of data into the receive data register until it is cleared.
The FE bit is cleared when the serial communications status register is accessed (with FE set)
followed by a read of the serial communications data register.
11.11.5
Baud rate register (BAUD)
The baud rate register (BAUD) is used to set the bit rate for the SCI system. Normally this register
is written once, during initialization, to set the baud rate for SCI communications. Both the receiver
and the transmitter use the same baud rate which is derived from the MCU bus rate clock. A two
stage divider is used to develop custom baud rates from normal MCU crystal frequencies,
therefore it is not necessary to use special baud rate crystal frequencies.
SCI baud rate (BAUD)
Address
bit 7
$004B
TCLR
bit 6
0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SCP1 SCP0 RCKB SCR2 SCR1 SCR0 0000 0uuu
TCLR — Clear baud rate counters (test purposes only)
This bit is disabled and remains low in any mode other than test or bootstrap. Reset clears this bit.
While in test or bootstrap mode, setting this bit causes the baud rate counter chains to be reset.
The logic one state of this bit is transitory, reads always a return a logic zero. This control bit is only
intended for factory testing of the MCU
TPG
MOTOROLA
11-14
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SCP1, SCP0 — Serial prescaler select bits
These read/write bits determine the prescale factor by which the internal processor clock is divided
before it is applied to the transmitter and receiver rate control dividers. This common prescaled
output is used as the input to a divider that is controlled by the SCR0–SCR2 bits for the SCI
receiver and transmitter.
Table 11-2 First prescaler stage
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SCP1
SCP0
0
0
1
1
0
1
0
1
Prescaler
division ratio (PRS1)
1
3
4
13
SCR2, SCR1, SCR0 — SCI rate select bits
These three read/write bits select the baud rates for the transmitter and the receiver. The prescaler
output is divided by the factors shown in Table 11-3.
Table 11-3 Second prescaler stage
SCR2
SCR1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SCR0
0
1
0
1
0
1
0
1
Prescaler
division ratio (PRS2)
1
2
4
8
16
32
64
128
11
RCKB — SCI receive baud rate clock test
This bit is disabled and remains low in any mode other than test or bootstrap. Reset clears this bit.
While in test or bootstrap mode, this bit may be written but not read (reads always return a logic
zero). Setting this bit enables a baud rate counter test mode, where the exclusive-or of the receiver
clock (16 times the baud rate) is driven out of the PC3/TDO pin. This control bit is intended only
for factory testing of the MCU.
TPG
MC68HC05F32
SERIAL COMMUNICATIONS INTERFACE
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11.12
Baud rate selection
The flexibility of the baud rate generator allows many different baud rates to be selected,
depending on the CPU clock frequency. A particular baud rate may be generated by manipulating
the various prescaler and division ratio bits.
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The SCI baud rate can be calculated from the internal bus clock and the two prescaler factors,
PRS1 and PRS2. The first prescaler factor, PRS1, is selected with SCP0 and SCP1, as shown in
Table 11-2. The second prescaler factor, PRS2, is selected with SCR0, SCR1 and SCR2, as
shown in Table 11-3. The SCI baud rate B equals the internal bus clock E, divided by 16, divided
by PRS1, divided by PRS2 (B = E/16/PRS1/PRS2).
Note:
For the receiver, the internal clock frequency is 16 times higher than the selected baud
rate.
11.13
SCI during STOP mode
When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter
is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to operate.
If the STOP instruction is executed during a transmitter transfer, that transfer is halted. When STOP
mode is exited as a result of an external interrupt, that particular transmission resumes.
If the receiver is receiving data when the STOP instruction is executed, received data sampling is
stopped (baud generator stops) and the rest of the data is lost.
Warning: For the above reasons, all SCI transactions should be in the idle state when the STOP
instruction is executed.
11.14
SCI during WAIT mode
The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI
interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering
WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication
control register 2 at $0049. This action will result in a reduction of power consumption during WAIT
mode.
TPG
MOTOROLA
11-16
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PULSE WIDTH MODULATOR
12.1
PWM introduction
The pulse width modulator (PWM) system has three 8-bit channels (PWM1, PWM2, and PWM3).
The PWM has a programmable period of 256xT, where T can be E/2, E/4, and E/8 for an output
frequency of 4 KHz, 2KHz, and 1 KHz respectively with E = 2MHz. E is the internal bus frequency
fixed to half of the external oscillator frequency.
PWM control
register
($0040)
PWM 8-bit counter
0
0
0
POL3 POL2 POL1
RA1
RA0
PWM3 data ($0043)
PWM3/PE7
PWM2 data ($0042)
PWM2/PE6
PWM1 data ($0041)
PWM1PE5
Clock
12
E
Figure 12-1 PWM block diagram
TPG
MC68HC05F32
PULSE WIDTH MODULATOR
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12.2
Functional description
The PWM is capable of generating signals from 0% to 100% duty cycle. A $00 in the PWM data
register yields an ‘OFF’ output (0%), but an $FF yields a duty of 255/256. To achieve the 100%
duty (‘ON’ output), the polarity control bit is set to active low (POL = 0) for that channel (i.e. PWM0
and PWM1) while the data register has $00 in it.
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When not in use, the PWM system can be shut off to save power by clearing the clock rate select
bits RA0 and RA1 in the PWM control register (PWCR). The PWM starts conversion immediately
after programming bits RA0 and RA1 in the PWM control register. The PWM outputs are
connected to port E if the corresponding bit in the port E control register is set.
The PWM output can have an active high or an active low pulse under software control.
256 T
$00
$01
255 T
T
$50
176 T
$80
128 T
12
$FF
255 T
T
Figure 12-2 PWM output waveforms (POL = 1, active high)
12.3
Registers
There are three PWM data registers and a control register associated with the PWM system.
These registers can be written to and read at any time.
After reset the user should write to the data registers and to the polarity select bits prior to enabling
the PWM system (i.e. prior to setting RA1 and/or RA0 for PWM input clock rate). This will avoid an
erroneous duty cycle being driven.
TPG
MOTOROLA
12-2
PULSE WIDTH MODULATOR
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$00
256 T
$01
T
255 T
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$50
80 T
$80
128 T
$FF
255 T
T
Figure 12-3 PWM waveforms (POL = 0, active low)
12.3.1
PWM control (PWMCR)
PWM control (PWMCR)
Address
bit 7
bit 6
bit 5
$0040
0
0
0
bit 4
bit 3
bit 2
POL3 POL2 POL1
bit 1
RA1
bit 0
RA0
State
on reset
0001 1100
12
POL1 — PWM1 polarity
1 (set)
–
0 (clear) –
makes the PWM1 pulse active high
makes the PWM1 pulse active low
POL2 — PWM2 polarity
1 (set)
–
0 (clear) –
makes the PWM2 pulse active high
makes the PWM2 pulse active low
POL3 — PWM3 polarity
1 (set)
–
0 (clear) –
makes the PWM3 pulse active high
makes the PWM3 pulse active low
TPG
MC68HC05F32
PULSE WIDTH MODULATOR
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RA1, RA0 — PWM clock rate bits
These bits select the input clock rate and determine the period.
Note:
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12
The polarity bits and the PWM clock rate bits are not latched until the end of conversion.
They affect the PWM output immediately. For proper operation these control bits must
not be changed during conversion.
Table 12-1 PWM clock rate
RA1:RA0
00
01
10
11
12.3.2
PWM input clock
OFF
E/2
E/4
E/8
PWM data registers (PWMD)
The PWM system has three 8-bit data registers which hold the duty cycle for each PWM output.
PWM data1, PWM data2, and PWM data3 are the data registers located at $41-$43 respectively.
Note:
These registers are affected by RESET
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
PWM data1 (PWMD1)
$0041
1000 0000
PWM data2 (PWMD2)
$0042
1000 0000
PWM data3 (PWMD3)
$0043
1000 0000
12.4
PWM during WAIT mode
The PWM continues normal operation during WAIT mode. To decrease power consumption during
WAIT, it is recommended that the rate select bits in the PWM control register are cleared if the
PWM D/A converter is not used.
TPG
MOTOROLA
12-4
PULSE WIDTH MODULATOR
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12.5
PWM during STOP mode
In STOP mode the oscillator is stopped causing the PWM to cease operation. Any signal in
process is aborted in whatever phase the signal happens to be in.
12.6
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PWM during reset
Upon RESET the RA0 and RA1 bits in the PWM control register are cleared, the port E control
register is cleared, the data registers are written with $80 and the polarity bits are set. This in effect
disables the PWM system. The user should write to the data registers prior to enabling the PWM
system (i.e. prior to setting RA1 or RA0). This will avoid an erroneous duty cycle being driven.
12
TPG
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12
TPG
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PULSE WIDTH MODULATOR
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32 KHZ CLOCK SYSTEM
13.1
32 kHz clock system
The 32 kHz clock system is mostly independent from the rest of the MCU. WAIT mode and STOP
mode do not affect the work of the 32 kHz clock system. For the reason of power saving the
oscillator and the divider can be stopped if the oscillator input pin OSC3 is held on fixed potential.
The 32 kHz clock system is provided to generate a refresh signal at port E pin 4 and an custom
periodic interrupt (CPI) with a period of 0.5s. The refresh frequency and the periodic interrupt are
under the control of the custom periodic interrupt control/status register located at $4C.
13.1.1
Custom periodic interrupt control/status register (CPICSR)
The CPICSR contains the interrupt flag CPIF, the interrupt enable bit CPIE and refresh frequency
select bits RFQ1, RFQ0.
CPI control/status (CPICSR)
Address
bit 7
bit 6
$004C
0
CPIF
bit 5
0
bit 4
CPIE
bit 3
bit 2
0
0
bit 1
bit 0
State
on reset
RFQ1 RFQ0 0000 0000
13
CPIF — Custom periodic interrupt flag
CPIF is a clearable, read-only status bit and is set when the 14-bit counter changes from $3FFF
to $0000. A CPU interrupt request will be generated if CPIE is set. Clearing the CPIF is done by
writing a ‘0’ to it. Writing a ‘1’ to CPIF has no effect on the bit’s value. Reset clears CPIF.
CPIE — Custom periodic interrupt enable
When this bit is cleared, the CPI interrupts are disabled. When this bit is set, a CPU interrupt
request is generated when the CPIF bit is set. Reset clears this bit.
TPG
MC68HC05F32
32 KHZ CLOCK SYSTEM
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RFQ1–RFQ0 — Refresh frequency select
These two read/write bits select one of four taps from the 14-stage counter to provide a refresh
clock with a frequency according to Table 13-1. Reset clears these bits, selecting the highest
frequency.
Table 13-1 Refresh clock (32.768 kHz crystal)
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13
RFQ1
0
0
1
1
13.1.1.1
RFQ0
0
1
0
1
Refresh clock frequency
8.192 kHz (reset condition)
4.096 kHz
2.048 kHz
1.024 kHz
Refresh clock
If bit 4 in the control register of port E is set, the output of the 32 kHz clock system is connected
to the pin PE4/REFRESH. The refresh clock rate is under software control and is specified in
Table 13-1.
13.2
Operation during STOP mode
Stop mode does not affect the work of the 32 kHz clock system. If the CPI interrupt is enabled, a
custom periodic interrupt will cause the processor to wake up from the STOP mode.
13.3
Operation during WAIT mode
The CPU clock halts during the WAIT mode, but the 32 kHz clock system remains active. If the
CPI interrupt is enabled, a custom periodic interrupt will cause the processor to exit the WAIT
mode.
TPG
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13-2
32 KHZ CLOCK SYSTEM
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RESETS AND INTERRUPTS
14.1
Resets
The MC68HC05F32 can be reset in five ways: by the initial power-on reset function, by an active
low input to the RESET pin, by an on-chip low voltage reset, by an opcode fetch from an illegal
address, and by a COP watchdog timer reset. Any of these resets will cause the program to return
to its starting address, specified by the contents of memory locations $FFFE and $FFFF, and
cause the interrupt mask of the CCR to be set.
14.1.1
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high.
14.1.2
RESET pin
When the oscillator is running in a stable state, the MCU is reset when a logic zero is applied to
the RESET input for a minimum period of 1.5 machine cycles (tCYC). This pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. When the reset pin goes high, the
MCU will resume operation on the following cycle. The RESET pin is also an output device for the
internal low voltage reset.
14.1.3
14
Illegal address reset
When an opcode fetch occurs from an address which is not part of the RAM ($0068 – $03FF) or
of the ROM ($8000 – $FFFF) or EEPROM ($0400 – $04FF), the device is automatically reset.
TPG
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RESETS AND INTERRUPTS
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Note:
No RTS or RTI instruction should be placed at the end of a memory block since this
could result in an illegal address reset.
14.1.4
Computer operating properly (COP) reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specific time by a program reset sequence.
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If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode it was in when the COP timeout was generated.
The COP function is a mask option, enabled or disabled during device manufacture. See
Section 1.2.
Refer to Section 5.3 for more information on the COP watchdog timer.
14.1.5
Low voltage reset
The MCU contains a low voltage detection circuit which drives the external reset.
For a positive transition of supply voltage vDD, the low voltage reset occurs as long as VDD is below
the VRON level. In this case the external reset pin is pulled down. If the supply voltage drops off
above the VRON level, the reset is released. If the supply voltage falls off below the VROFF level, the
RESET pin is pulled down.
14
TPG
MOTOROLA
14-2
RESETS AND INTERRUPTS
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14.2
Interrupts
The MCU can be interrupted by nine different sources, eight maskable hardware interrupts and
one nonmaskable software interrupt:
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•
External signal on the IRQ pin; IRQ is mask selectable as edge or edge-and-level sensitive
•
Keyboard interrupt
•
Core timer interrupt
•
16-bit programmable timer interrupt
•
Low voltage interrupt (LVI) – EEPROM
•
Serial peripheral interface (SPI) interrupt
•
Serial communications interface (SCI) interrupt
•
32 kHz clock system interrupt
•
Software interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared providing the
corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed. Figure 14-1 shows the interrupt processing
flow.
Note:
Power-on or external reset clears all interrupt enable bits thus preventing interrupts
during the reset sequence.
14
TPG
MC68HC05F32
RESETS AND INTERRUPTS
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14.2.1
Interrupt priorities
Each potential interrupt source is assigned a priority which means that if more than one interrupt
is pending at the same time, the processor will service the one with the highest priority first. For
example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
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14
14.2.2
Non-maskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the
contents of memory locations $FFFC and $FFFD.
14.2.3
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur. IRQ is software selectable as either
edge or edge-and-level sensitive (bit 3 of the system option register).
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
14.2.3.1
Real time and core timer (CTIMER) interrupts
There are two different core timer interrupt flags that cause a CTIMER interrupt whenever an
interrupt is enabled and its flag becomes set, namely RTIF and CTOF. The interrupt flags and
enable bits are located in the CTIMER control and status register (CTCSR). These interrupts will
vector to the same interrupt service routine, whose start address is contained in memory locations
$FFF8 and $FFF9 (see Section 5.2.1 and Figure 5-1).
To make use of the real time interrupt the RTIE bit must first be set. The RTIF bit will then be set
after the specified number of counts.
To make use of the core timer overflow interrupt, the CTOFE bit must first be set. The CTOF bit will
then be set when the core timer counter register overflows from $FF to $00.
TPG
MOTOROLA
14-4
RESETS AND INTERRUPTS
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From
RESET
Yes
Is
I-bit set
?
No
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IRQ/Key
external interrupt
?
Yes
Clear relevant
interrupt request
latch
No
Core timer
or CPI interrupt
?
Yes
Stack:
PC, X, A, CC
No
Timer1, 2, 3, 4
interrupt
?
Yes
Set I-bit
Load PC from:
SWI:
IRQ/Key:
CTIMER:
CPI:
TIMER:
LVI:
SPI:
SCI:
No
LVI
interrupt
?
No
Yes
SPI
interrupt
Yes
?
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
Fetch next instruction
No
SCI
interrupt
Yes
SWI
instruction
?
No
?
No
Yes
RTI
instruction
?
Restore registers
from stack:
CC, A, X, PC
14
No
Execute
instruction
Figure 14-1 Interrupt flowchart
TPG
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RESETS AND INTERRUPTS
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Table 14-1 Vector address for interrupts and reset
Register Flag name
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14
—
—
—
CTCSR
CTCSR
CPICSR
TSR
TSR
TSR
TSR
TSR2
TSR2
TSR2
TSR2
TSR
TSR2
KEY
SOR
SPSR
SPSR
SCSR
SCSR
SCSR
SCSR
SCSR
14.2.3.2
—
—
—
CTOF
RTIF
CPIF
ICF1
OCF1
ICF2
OCF2
ICF3
OCF3
ICF4
OCF4
TOF
TOF
KSF
LVI
SPIF
MODF
TDRE
TC
RDRF
IDLE
OR
Interrupts
Reset
Software interrupt
External interrupt
Core timer overflow
Real time interrupt
Custom periodic interrupt
Timer input capture1
Timer output compare1
Timer input capture2
Timer output compare2
Timer input capture3
Timer output compare3
Timer input capture4
Timer output compare4
Timer1 overflow
Timer2 overflow
Keyboard interrupt
Low voltage interrupt
SPI request interrupt
SPI mode error
SCI transmit interrupt
SCI transmit complete
SCI receive interrupt
SCI idle line interrupt
SCI overrun error
CPU
Vector address
interrupt
RESET
$FFFE–$FFFF
SWI
$FFFC–$FFFD
IRQ
$FFFA–$FFFB
CTIMER
$FFF8–$FFF9
CTIMER
$FFF8–$FFF9
CPI
$FFF8–$FFF9
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
TIMER
$FFF6–$FFF7
KEYF
$FFFA–$FFFB
LVI
$FFF4–$FFF5
SPI
$FFF2–$FFF3
SPI
$FFF2–$FFF3
SCI
$FFF0–$FFF1
SCI
$FFF0–$FFF1
SCI
$FFF0–$FFF1
SCI
$FFF0–$FFF1
SCI
$FFF0–$FFF1
Programmable 16-bit timer interrupt
There are ten different timer interrupt flags that cause a timer interrupt whenever they are set and
enabled. The timer interrupt enable bits are located in the timer control register (TCR) and the timer
interrupt flags are located in the timer status registers (TSR1, TSR2). All three interrupts will vector
to the same service routine, whose start address is contained in memory locations $FFF6 and
$FFF7.
TPG
MOTOROLA
14-6
RESETS AND INTERRUPTS
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14.2.3.3
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Keyboard interrupt
When configured as input pins, all eight port A lines provide a wired-OR keyboard interrupt facility
and will generate an interrupt, provided that the keyboard interrupt enable bit (KIE) in the
keyboard/timer register (KEY/TIM) is set. The address of the interrupt service routine is specified
by the contents of memory locations $0FFA and $0FFB. Since this interrupt vector is shared with
the IRQ external interrupt function the interrupt service routine should check KSF to determine the
interrupt source. KSF should be cleared by software in the interrupt service routine. Care must be
taken to allow adequate time for switch debounce before clearing the flag.
14.2.3.4
Low voltage interrupt
There is a low voltage interrupt flag that causes an interrupt whenever it is set and enabled. The
low voltage interrupt enable bit and the interrupt flag are located in the system option register
(SOR). This interrupt will vector to the service routine, located at the address specified by the
contents of memory locations $FFF4 and $FFF5.
14.2.3.5
Serial peripheral interface (SPI) interrupt
An interrupt in the serial peripheral interface (SPI) occurs when one of the interrupt flag bits in the
SPI status register SPSR is set, provided the I-bit in the condition code register is clear and the
enable bit SPIE in the SPI control register is enabled. The SPI interrupt causes the program to
vector to memory location $FFF2 and $FFF3 which contains the starting address of the interrupt
service routine. Software in the SPI service routine must determine the priority and cause of the
SPI interrupt by examined the interrupt flag bits located in the SPI status register.
14.2.3.6
Serial communications interface (SCI) interrupt
There are five different interrupt flags (TDRE, TC, OR, RDRE, IDLE) that will cause an SCI
interrupt whenever they are set and enabled. These five interrupt flags are found in the five most
significant bits of the SCI status register SCSR. The actual processor interrupt is generated only if
the I-bit in the condition code register is clear and the enable bit in the serial communication control
register 2 (SCCR2) is enabled. The SCI interrupt causes the program counter to vector to the
address pointed to by memory locations $FFF0–$FFF1 which contain the start address of the
interrupt service routine. Software in the SCI interrupt service routine must determine the priority
and cause of the SCI interrupt by examining the interrupt flags and the status bits in the serial
communications status register SCSR.
14
TPG
MC68HC05F32
RESETS AND INTERRUPTS
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14.2.3.7
Custom periodic interrupt (CPI)
There is a timer interrupt flag that causes a CPI interrupt from the 32 kHz clock system whenever
set and enabled. The interrupt flag and enable bits are located in the CPI control and status
register (CPICSR). An interrupt will vector to the same interrupt service routine as the core timer
interrupts, located at the address specified by the contents of memory location $FFF8 and $FFF9.
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14.2.4
Hardware controlled interrupt sequence
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts.
However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in
Figure 2-1.
RESET: A reset condition causes the program to vector to its starting address, which is contained
in memory locations $FFFE (MSB) and $FFFF (LSB). The I-bit in the condition code register is
also set, to disable interrupts.
STOP: The STOP instruction causes the oscillator to be turned off and the processor to ‘sleep’ until
an external interrupt (IRQ), a low voltage interrupt (LVI), a custom periodic interrupt (CPI), or a
keyboard interrupt occurs, or the device is reset.
WAIT: The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt (IRQ), a
keyboard interrupt, a timer interrupt (core or 16-bit), or a CPI, SPI, SCI, LVI interrupt. There are no
special WAIT vectors for these interrupts.
14
TPG
MOTOROLA
14-8
RESETS AND INTERRUPTS
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15
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CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05F32.
15.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 15-1. The interrupt
stacking order is shown in Figure 15-2.
7
0
7
0
7
0
Accumulator
Index register
15
Program counter
15
7
0
0 0 0 0 0 0 0 0 1 1
7
0
1 1 1 H I N Z C
Stack pointer
Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
15
Figure 15-1 Programming model
15.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of
arithmetic calculations or data manipulations.
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Unstack
Stack
0
Condition code register
Accumulator
Index register
Program counter high
Program counter low
Interrupt
Increasing
memory
address
Return
7
Decreasing
memory
address
Figure 15-2 Stacking order
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15
15.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to
create an effective address. The index register may also be used as a temporary storage area.
15.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
15.1.4
Stack pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011. These
ten bits are appended to the six least significant register bits to produce an address within the
range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64
locations are exceeded, the stack pointer wraps around and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
15.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just
executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually
tested by a program, and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
TPG
MOTOROLA
15-2
CPU CORE AND INSTRUCTION SET
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Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3
and 4.
Interrupt (I)
When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
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Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation. This bit is also affected during bit test and branch instructions
and during shifts and rotates.
15.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as
follows:
–
Register/memory
–
Read/modify/write
–
Branch
–
Bit manipulation
–
Control
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
15
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the
index register and the low-order product is stored in the accumulator. A detailed definition of the
MUL instruction is shown in Table 15-1.
TPG
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15.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the
index register. The second operand is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register
operand. Refer to Table 15-2 for a complete list of register/memory instructions.
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15.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no
operation is performed. Branch instructions are two-byte instructions. Refer to Table 15-3.
15.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space
(page 0). All port data and data direction registers, timer and serial interface registers,
control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature
allows the software to test and branch on the state of any bit within these locations. The bit set, bit
clear, bit test and branch functions are all implemented with single instructions. For the test and
branch instructions, the value of the bit tested is also placed in the carry bit of the condition code
register. Refer to Table 15-4.
15.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register. The test for negative or zero (TST) instruction is
an exception to this sequence of reading, modifying and writing, since it does not modify the value.
Refer to Table 15-5 for a complete list of read/modify/write instructions.
15.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to Table 15-6 for a complete list of control instructions.
TPG
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15-4
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15.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see Table 15-7), and an opcode map for the instruction set of the
M68HC05 MCU family (see Table 15-8).
Table 15-1 MUL instruction
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Operation
Description
Condition
codes
Source
Form
15.3
X:A ← X*A
Multiplies the eight bits in the index register by the eight
bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
H : Cleared
I : Not affected
N : Not affected
Z : Not affected
C : Cleared
MUL
Addressing mode
Cycles
Bytes Opcode
Inherent
11
1
$42
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for
all situations. The various indexed addressing modes make it possible to locate data tables, code
conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are
single byte instructions; the longest instructions (three bytes) enable access to tables throughout
memory. Short absolute (direct) and long absolute (extended) addressing are also included. One
or two byte direct addressing instructions access all data bytes in most applications. Extended
addressing permits jump instructions to reach all memory locations.
The term ‘effective address’ (EA) is used in describing the various addressing modes. The
effective address is defined as the address from which the argument for an instruction is fetched
or stored. The ten addressing modes of the processor are described below. Parentheses are used
to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the
contents of the location pointed to by the PC (program counter). An arrow indicates ‘is replaced
by’ and a colon indicates concatenation of two bytes. For additional details and graphical
illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/
Microprocessor User's Manual or to the M68HC05 Applications Guide.
15
TPG
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Table 15-2 Register/memory instructions
Addressing modes
15
# Cycles
# Bytes
Opcode
Indexed
(16-bit
offset)
# Cycles
# Bytes
Opcode
# Bytes
Opcode
# Cycles
# Bytes
Opcode
Indexed
(8-bit
offset)
# Cycles
Indexed
(no
offset)
Extended
# Cycles
# Bytes
Direct
Opcode
# Cycles
# Bytes
Function
Opcode
Mnemonic
Immediate
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Load A from memory
LDA
A6
2
2
B6
2
3
C6
3
4
F6
1
3
E6
2
4
D6
3
5
Load X from memory
LDX
AE
2
2
BE
2
3
CE
3
4
FE
1
3
EE
2
4
DE
3
5
Store A in memory
STA
B7
2
4
C7
3
5
F7
1
4
E7
2
5
D7
3
6
Store X in memory
STX
BF
2
4
CF
3
5
FF
1
4
EF
2
5
DF
3
6
Add memory to A
ADD
AB
2
2
BB
2
3
CB
3
4
FB
1
3
EB
2
4
DB
3
Add memory and carry to A
ADC
A9
2
2
B9
2
3
C9
3
4
F9
1
3
E9
2
4
D9
3
5
Subtract memory
SUB
A0
2
2
B0
2
3
C0
3
4
F0
1
3
E0
2
4
D0
3
5
5
Subtract memory from A
with borrow
SBC
A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
D2
3
5
AND memory with A
AND
A4
2
2
B4
2
3
C4
3
4
F4
1
3
E4
2
4
D4
3
5
OR memory with A
ORA
AA
2
2
BA
2
3
CA
3
4
FA
1
3
EA
2
4
DA
3
5
Exclusive OR memory with A
EOR
A8
2
2
B8
2
3
C8
3
4
F8
1
3
E8
2
4
D8
3
5
Arithmetic compare A
with memory
CMP
A1
2
2
B1
2
3
C1
3
4
F1
1
3
E1
2
4
D1
3
5
Arithmetic compare X
with memory
CPX
A3
2
2
B3
2
3
C3
3
4
F3
1
3
E3
2
4
D3
3
5
Bit test memory with A
(logical compare)
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
D5
3
5
Jump unconditional
JMP
BC
2
2
CC
3
3
FC
1
2
EC
2
3
DC
3
4
Jump to subroutine
JSR
BD
2
5
CD
3
6
FD
1
5
ED
2
6
DD
3
7
15.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations specifying only the index register or accumulator, as well as
the control instruction, with no other arguments are included in this mode. These instructions are
one byte long.
15.3.2
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access constants that do not change during
program execution (e.g. a constant used to initialize a loop counter).
EA = PC+1; PC ← PC+2
TPG
MOTOROLA
15-6
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Freescale Semiconductor, Inc.
Table 15-3 Branch instructions
Function
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Branch always
Branch never
Branch if higher
Branch if lower or same
Branch if carry clear
(Branch if higher or same)
Branch if carry set
(Branch if lower)
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
Branch if minus
Branch if interrupt mask bit is clear
Branch if interrupt mask bit is set
Branch if interrupt line is low
Branch if interrupt line is high
Branch to subroutine
Mnemonic
BRA
BRN
BHI
BLS
BCC
(BHS)
BCS
(BLO)
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
BIH
BSR
Relative addressing mode
Opcode # Bytes # Cycles
20
2
3
21
2
3
22
2
3
23
2
3
24
2
3
24
2
3
25
2
3
25
2
3
26
2
3
27
2
3
28
2
3
29
2
3
2A
2
3
2B
2
3
2C
2
3
2D
2
3
2E
2
3
2F
2
3
AD
2
6
Table 15-4 Bit manipulation instructions
Function
Mnemonic
Branch if bit n is set
Branch if bit n is clear
Set bit n
Clear bit n
15.3.3
BRSET n (n=0–7)
BRCLR n (n=0–7)
BSET n (n=0–7)
BCLR n (n=0–7)
Addressing modes
Bit set/clear
Bit test and branch
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
2•n
3
5
01+2•n
3
5
10+2•n
2
5
11+2•n
2
5
15
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte
following the opcode byte. Direct addressing allows the user to directly address the lowest 256
bytes in memory with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
TPG
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Freescale Semiconductor, Inc.
Table 15-5 Read/modify/write instructions
Addressing modes
Increment
Decrement
Clear
Complement
Negate (two’s complement)
Rotate left through carry
Rotate right through carry
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
Multiply
1 3 5C
1 3 5A
1 3 5F
1 3 53
1 3 50
1 3 59
1 3 56
1 3 58
1 3 54
1 3 57
1 3 5D
1 11
1 3 3C
1 3 3A
1 3 3F
1 3 33
1 3 30
1 3 39
1 3 36
1 3 38
1 3 34
1 3 37
1 3 3D
2 5 7C
2 5 7A
2 5 7F
2 5 73
2 5 70
2 5 79
2 5 76
2 5 78
2 5 74
2 5 77
2 4 7D
1 5 6C
1 5 6A
1 5 6F
1 5 63
1 5 60
1 5 69
1 5 66
1 5 68
1 5 64
1 5 67
1 4 6D
# Cycles
# Bytes
Opcode
Indexed
(8-bit
offset)
# Cycles
# Bytes
# Cycles
# Bytes
Opcode
Indexed
(no
offset)
Direct
Opcode
# Cycles
# Bytes
Opcode
4C
4A
4F
43
40
49
46
48
44
47
4D
42
Inherent
(X)
# Cycles
INC
DEC
CLR
COM
NEG
ROL
ROR
LSL
LSR
ASR
TST
MUL
# Bytes
Opcode
Function
Mnemonic
Inherent
(A)
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
2 6
2 6
2 6
2 6
2 6
2 6
2 6
2 6
2 6
2 6
2 5
Table 15-6 Control instructions
Function
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-operation
Stop
Wait
15
Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
Inherent addressing mode
Opcode # Bytes # Cycles
97
1
2
9F
1
2
99
1
2
98
1
2
9B
1
2
9A
1
2
83
1
10
81
1
6
80
1
9
9C
1
2
9D
1
2
8E
1
2
8F
1
2
TPG
MOTOROLA
15-8
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Freescale Semiconductor, Inc.
Table 15-7 Instruction set
Mnemonic
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
INH
IMM
DIR
Addressing modes
EXT REL IX
IX1
IX2
BSC BTB
H
ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
CMP
Condition codes
I
N Z C
◊
•
◊
◊
◊
•
◊
◊
•
•
◊
◊
•
•
◊
◊
•
•
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0 1
•
•
◊
◊
◊
◊
•
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
◊
◊
•
•
0
•
•
◊
15
Condition code symbols
Address mode abbreviations
BSC Bit set/clear
IMM
Immediate
H
Half carry (from bit 3)
◊
Tested and set if true,
cleared otherwise
BTB Bit test & branch
IX
Indexed (no offset)
I
Interrupt mask
•
Not affected
DIR
IX1
Indexed, 1 byte offset
N
Negate (sign bit)
?
Load CCR from stack
EXT Extended
IX2
Indexed, 2 byte offset
Z
Zero
0
Cleared
INH
REL
Relative
C
Carry/borrow
1
Set
Direct
Inherent
Not implemented
TPG
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MOTOROLA
15-9
143
05F32Book Page 10 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
Table 15-7 Instruction set (Continued)
Mnemonic
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
15
INH
IMM
DIR
Addressing modes
EXT REL IX
IX1
IX2
BSC BTB
H
COM
CPX
DEC
EOR
INC
JMP
JSR
LDA
LDX
LSL
LSR
MUL
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT
Condition codes
I
N Z C
•
•
◊
◊ 1
•
•
◊
◊
◊
•
•
◊
◊
•
•
•
◊
◊
•
•
•
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
◊
◊
•
•
•
◊
◊
•
•
•
◊
◊
◊
•
•
0 ◊
◊
0
•
•
•
0
•
•
◊
◊
◊
•
•
•
•
•
•
•
◊
◊
•
•
•
◊
◊
◊
•
•
◊
◊
◊
•
•
•
•
•
? ? ? ? ?
•
•
•
•
•
•
•
◊
◊
◊
•
•
•
•
1
•
1
•
•
•
•
•
◊
◊
•
•
0
•
•
•
•
•
◊
◊
•
•
•
◊
◊
◊
•
1
•
•
•
•
•
•
•
•
•
•
◊
◊
•
•
•
•
•
•
•
0
•
•
•
Condition code symbols
Address mode abbreviations
BSC Bit set/clear
IMM
Immediate
H
Half carry (from bit 3)
◊
Tested and set if true,
cleared otherwise
BTB Bit test & branch
IX
Indexed (no offset)
I
Interrupt mask
•
Not affected
DIR
IX1
Indexed, 1 byte offset
N
Negate (sign bit)
?
Load CCR from stack
EXT Extended
IX2
Indexed, 2 byte offset
Z
Zero
0
Cleared
INH
REL
Relative
C
Carry/borrow
1
Set
Direct
Inherent
Not implemented
TPG
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0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BRCLR7
BRSET7
BRCLR6
BRSET6
BRCLR5
BRSET5
BRCLR4
BRSET4
BRCLR3
BRSET3
BRCLR2
BRSET2
BRCLR1
BRSET1
3
BRCLR0
BTB 2
5
BRSET0
3
5
BSC 2
BCLR7
BSC 2
5
BSET7
BSC 2
5
BCLR6
BSC 2
5
BSC 2
5
BSET6
BCLR5
BSC 2
5
BSC 2
5
BSET5
BCLR4
BSC 2
5
BSC 2
5
BSET4
BCLR3
BSC 2
5
BSC 2
5
BSET3
BCLR2
BSC 2
5
BSC 2
5
BSET2
BCLR1
BSC 2
5
BSC 2
5
BSET1
BCLR0
BSC 2
5
BSET0
5
BIH
BIL
BMS
BMC
BMI
REL 2
REL
3
REL 2
3
REL 2
3
REL
3
REL 2
3
REL 2
3
REL 2
3
REL 2
3
REL 2
3
REL
3
REL 2
3
REL 2
3
REL
3
REL
3
BHCS
BPL
3
REL 2
3
BHCC
BEQ
BNE
BCS
BCC
BLS
BHI
BRN
BRA
Branch
REL
2
0010
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BSC
BTB
DIR
EXT
INH
IMM
Bit set/clear
Bit test and branch
Direct
Extended
Inherent
Immediate
IX
IX1
IX2
REL
A
X
Abbreviations for address modes and register s
Low
High
Bit manipulation
BTB
BSC
0
1
0000
0001
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
DIR
3
0011
CLRA
TSTA
INCA
DECA
INH 1
3
INH 1
INH 1
3
3
INH 1
INH 1
3
INH 1
3
INH 1
3
ROLA
LSLA
ASRA
INH 1
3
3
INH 1
INH 1
3
RORA
LSRA
11
INH
3
COMA
MUL
INH 1
NEGA
3
CLRX
TSTX
INCX
DECX
INH 2
3
INH 2
INH 2
3
3
INH 2
INH 2
3
INH 2
3
INH 2
3
ROLX
LSLX
ASRX
INH 2
3
3
INH 2
INH 2
3
RORX
LSRX
3
INH 2
COMX
NEGX
3
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
Read/modify/write
INH
IX1
5
6
0101
0110
Indexed (no offset)
Indexed, 1 byte (8-bit) offset
Indexed, 2 byte (16-bit) offset
Relative
Accum ulator
Index register
DIR 1
5
DIR 1
DIR 1
4
5
DIR 1
DIR 1
5
DIR 1
5
DIR 1
5
DIR 1
5
5
DIR 1
DIR 1
5
5
1
DIR 1
5
INH
4
0100
IX1 1
6
IX1 1
IX1 1
5
6
IX1 1
IX1 1
6
IX1 1
6
IX1 1
6
IX1 1
6
6
IX1 1
IX1 1
6
6
IX1 1
6
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
IX
7
0111
1
WAIT
1
1
1
1
1
1
1
INH 1
INH
2
2
INH
10
INH
INH
6
STOP
SWI
RTS
RTI
9
TXA
NOP
RSP
SEI
CLI
SEC
CLC
TAX
INH
9
1001
Control
Not implemented
IX 1
5
IX
IX
4
5
IX
IX
5
IX
5
IX
5
IX
5
5
IX
IX 1
5
5
1
IX 1
5
INH
8
1000
2
INH
2
INH 2
INH
2
INH 2
2
INH 2
2
INH 2
2
INH 2
2
INH
2
2
2
2
2
2
2
2
2
LDX
BSR
ADD
ORA
ADC
EOR
LDA
BIT
AND
CPX
SBC
CMP
SUB
IMM
A
1010
2
6
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
3
Bytes
1
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
SUB
F
1111
EXT 3
EXT 3
5
EXT 3
4
EXT 3
6
EXT 3
3
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
5
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
4
IX
3
0
0000
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
IX2 2
4
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
6
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
5
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
IX1
E
1110
Address mode
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
Register/memor y
EXT
IX2
C
D
1100
1101
Cycles
DIR 3
DIR 3
4
DIR 3
3
DIR 3
5
DIR 3
2
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
4
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
Mnemonic
Legend
2
IMM 2
REL 2
2
2
IMM 2
IMM 2
2
IMM 2
2
IMM 2
2
2
IMM 2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
2
DIR
B
1011
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
High
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Low
Opcode in binary
Opcode in hexadecimal
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
IX1 1
3
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
5
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
4
IX
F
1111
Freescale Semiconductor, Inc.
05F32Book Page 11 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
Table 15-8 M68HC05 opcode map
15
TPG
MOTOROLA
15-11
145
05F32Book Page 12 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
15.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Motorola assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
15
EA = (PC+1):(PC+2); PC ← PC+3
Address bus high ← (PC+1); Address bus low ← (PC+2)
15.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
EA = X; PC ← PC+1
Address bus high ← 0; Address bus low ← X
15.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations. This addressing mode
is useful for selecting the mth element in an n element table.
EA = X+(PC+1); PC ← PC+2
Address bus high ← K; Address bus low ← X+(PC+1)
where K = the carry from the addition of X and (PC+1)
15.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola
assembler determines the shortest form of indexed addressing.
EA = X+[(PC+1):(PC+2)]; PC ← PC+3
Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)
where K = the carry from the addition of X and (PC+2)
TPG
MOTOROLA
15-12
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15.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the
contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only
if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of
relative addressing is from –126 to +129 from the opcode address. The programmer need not
calculate the offset when using the Motorola assembler, since it calculates the proper offset and
checks to see that it is within the span of the branch.
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EA = PC+2+(PC+1); PC ← EA if branch taken;
otherwise EA = PC ← PC+2
15.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte
following the opcode specifies the address of the byte in which the specified bit is to be set or
cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively
set or cleared with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
15.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The
address of the byte to be tested is in the single byte immediately following the opcode byte (EA1).
The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set
or cleared in the specified memory location. This single three-byte instruction allows the program
to branch based on the condition of any readable bit in the first 256 locations of memory. The span
of branch is from –125 to +130 from the opcode address. The state of the tested bit is also
transferred to the carry bit of the condition code register.
EA1 = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
EA2 = PC+3+(PC+2); PC ← EA2 if branch taken;
otherwise PC ← PC+3
15
TPG
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TPG
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16
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ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the
MC68HC05F32.
16.1
Maximum ratings
Table 16-1 Maximum ratings
Rating (1)
Supply voltage
Input voltage
Bootloader mode (IRQ pin
only)
Current drain per pin(2)
— excluding VDD and VSS
Operating temperature range
— standard
— extended
Storage temperature range
Symbol
V DD
VIN
Value
– 0.3 to + 0.7
V SS – 0.3 to VSS + 0.3
Unit
V
V
V IN
V SS – 0.3 to 2 x VDD + 0.3
V
I
25
mA
TA
T STG
TL to TH
0 to + 70
–40 to + 85
– 65 to + 150
°C
°C
(1) All voltages are with respect to VSS .
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given
in the Maximum Ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either VSS or VDD.
16
TPG
MC68HC05F32
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16.2
Thermal characteristics and power considerations
Table 16-2 Package thermal characteristics
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Characteristics
Thermal resistance
— 100-pin QFP package
— 80-pin QFP package
Symbol
Value
Unit
θJA
55
°C/W
The average chip junction temperature, TJ, in degrees Celsius can be obtained from the following
equation:
T J = T A + ( P D • θ JA )
where:
TA = Ambient Temperature (°C)
θJA = Package Thermal Resistance,
Junction-to-ambient (°C/W)
PD = PINT + PI/O (W)
PINT = Internal Chip Power = IDD • VDD (W)
PI/O = Power Dissipation on Input and Output pins (User determined)
An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = ---------------------T J + 273
Solving equations [1] and [2] for K gives:
K = P D • ( T A + 273 ) + θ JA • P D2
where K is a constant for a particular part. K can be determined by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained for any value of TA
by solving the above equations. The package thermal characteristics are shown in Table 16-2.
16
TPG
MOTOROLA
16-2
ELECTRICAL SPECIFICATIONS
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16.3
DC electrical characteristics
Table 16-3 DC electrical characteristics (VDD = 5.0 V)
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(VDD = 5.0VDC ± 10%, V SS = 0 VDC , TA = –40°C to +85°C, unless otherwise stated)
Characteristic
Symbol
Min.
Typ. (1) Max.
Output voltage
ILOAD = –10 µA
VOH
V DD – 0.1
—
—
ILOAD = +10 µA
VOL
—
—
0.1
Output high voltage (ILOAD = –0.8 mA)
VOH
V DD – 0.8
—
—
Ports (PA0–7, PB0–7, PC0–7, PH0–7, PI7–0)
Output low voltage (ILOAD = +1.6 mA)
Ports(PA0–7, PB0–7, PC4–7, PD4–7, PE4–7,
VOL
—
—
0.4
PH0–7, PI0–7, PJ0–7)
Input high voltage
V IH
0.7V DD
—
15.0
Ports (PD0–7, PE0–7)
Input high voltage
Ports (PA0–7, PB0–7, PC0–7, PF0–7, PG0–7)
V IH
0.7V DD
—
V DD
IRQ, RESET,OSC1, OSC3
Input low voltage
Ports (PA0–7, PB0–7, PC0–7, PF0–7, PG0–7)
V IL
—
—
0.2V DD
IRQ , RESET, OSC1, OSC3
Supply Current (2)
IDD
RUN
—
5
10
WAIT
—
0.6
1.2
STOP
—
—
80
I/O ports hi-Z leakage current
—
—
10
IOZ
Ports (PA0–7, PB0–7, PC0–7, PD0–7, PE0–7)
Input current
IIN
—
—
1
RESET, IRQ, OSC1
Capacitance
Ports (as input or output)
C OUT
—
—
12
RESET, IRQ
C IN
—
—
8
Input current low
IIL
– 30
– 90
– 170
Ports (PA0–7, PB0–7, PC0–7), RESET
LCD step down resistor
R LCDSD
—
20
—
Unit
V
V
V
V
V
V
V
mA
mA
µA
µA
µA
pF
pF
µA
kΩ
(1) Typical values are at midpoint of voltage range and at 25°C only.
(2) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the
transient switching currents inherent in CMOS designs. RUN and WAIT IDD : measured using an external
square-wave clock source (fOSC = 3.58 MHz); all inputs0.2V from rail; no DC loads; maximum load on outputs
50pF (20pF on OSC2). WAIT I DD : only the timer system active; current varies linearly with the OSC2
capacitance. STOP and WAIT I DD : all ports configured as inputs, VIL = 0.2 V, VIH = VDD – 0.2 V. STOP IDD :
measured with OSC1 = V SS .
16
TPG
MC68HC05F32
ELECTRICAL SPECIFICATIONS
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Freescale Semiconductor, Inc.
Table 16-4 DC electrical characteristics (VDD = 2.7 V)
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16
(VDD = 2.7VDC min, VSS = 0 VDC , TA = –40°C to +85°C, unless otherwise stated)
Characteristic
Symbol
Min.
Output voltage
ILOAD = –10 µA
VOH
V DD – 0.1
ILOAD = +10 µA
VOL
—
Output high voltage (ILOAD = –0.8 mA)
VOH
V DD – 0.3
Ports (PA0–7, PB0–7, PC0–7, PH0–7, PI7–0)
Output low voltage (ILOAD = +1.6 mA)
Ports(PA0–7, PB0–7, PC4–7, PD4–7, PE4–7,
VOL
—
PH0–7, PI0–7, PJ0–7)
Input high voltage
V IH
0.7V DD
Ports (PD0–7, PE0–7)
Input high voltage
Ports (PA0–7, PB0–7, PC0–7, PF0–7, PG0–7)
V IH
0.7V DD
IRQ, RESET,OSC1, OSC3
Input low voltage
Ports (PA0–7, PB0–7, PC0–7, PF0–7, PG0–7)
V IL
—
IRQ , RESET, OSC1, OSC3
Supply Current (2)
IDD
RUN
—
WAIT
—
STOP
—
I/O ports hi-Z leakage current
—
IOZ
Ports (PA0–7, PB0–7, PC0–7, PD0–7, PE0–7)
Input current
IIN
—
RESET, IRQ, OSC1
Capacitance
Ports (as input or output)
C OUT
—
RESET, IRQ
C IN
—
Input current low
IIL
–5
Ports (PA0–7, PB0–7, PC0–7), RESET
LCD step down resistor
R LCDSD
—
Typ. (1)
Max.
Unit
—
—
—
0.1
V
V
—
—
V
—
0.3
V
—
15.0
V
—
V DD
V
—
0.2V DD
V
1.8
0.2
—
3.0
1.0
40
mA
mA
µA
—
10
µA
—
1
µA
—
—
12
8
pF
pF
– 15
40
µA
20
—
kΩ
(1) Typical values are at midpoint of voltage range and at 25°C only.
(2) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the
transient switching currents inherent in CMOS designs. RUN and WAIT IDD : measured using an external
square-wave clock source (fOSC = 3.58 MHz); all inputs0.2V from rail; no DC loads; maximum load on outputs
50pF (20pF on OSC2). WAIT I DD : only the timer system active; current varies linearly with the OSC2
capacitance. STOP and WAIT I DD : all ports configured as inputs, VIL = 0.2 V, VIH = VDD – 0.2 V. STOP IDD :
measured with OSC1 = V SS .
TPG
MOTOROLA
16-4
ELECTRICAL SPECIFICATIONS
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16.4
Control timing
Table 16-5 Control timing (VDD = 5V)
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(VDD = 5.0 VDC ± 10%, V SS = 0 VDC , TA = TL to TH )
Characteristic
Symbol
Frequency of operation:
Crystal
fOSC
External clock
Internal operating frequency:
Crystal
fOP
External clock
Processor cycle time
tCYC
Stop recovery start-up time
tILCH
Crystal oscillator start-up time
t
OXOV
RESET pulse width
tRL
Interrupt pulse width low (edge-triggered)
t
ILIH
Interrupt pulse period
tILIL
OSC1 pulse width
t OH , tOL
RC oscillator stabilization time
t
RCON
A/D on current stabilization time
t
ADON
EEPROM byte programming time
t EPGM
EEPROM byte erase time
t EBYTE
EEPROM block erase time
t EBLOCK
EEPROM bulk erase time
t EBULK
EEPROM programming voltage fall time
t FPV
EEPROM minimum programming voltage
V CCMIN
Min.
Max.
Unit
—
DC
3.579
3.579
MHz
—
DC
550.0
—
—
1.5
250.0
1.789
1.789
—
20.0
20.0
—
—
—
—
5.0
100.0
15.0
15.0
100.0
300.0
10.0
MHz
(1)
100.0
—
—
—
—
—
—
—
2.7
ns
ms
ms
t CYC
ns
t CYC
ns
µs
µs
ms
ms
ms
ms
µs
V
(1) The minimum period T ILIL should not be less than the number of cycle times it takes to execute
the interrupt service routine plus 21 CYC
t .
16
TPG
MC68HC05F32
ELECTRICAL SPECIFICATIONS
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Freescale Semiconductor, Inc.
Table 16-6 Control timing (VDD = 2.7V)
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(VDD = 2.7 VDC min, VSS = 0 VDC , TA = TL to TH )
Characteristic
Frequency of operation:
Crystal
External clock
Internal operating frequency:
Crystal
External clock
Processor cycle time
Stop recovery start-up time
Crystal oscillator start-up time
RESET pulse width
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
OSC1 pulse width
RC oscillator stabilization time
A/D on current stabilization time
EEPROM byte programming time
EEPROM byte erase time
EEPROM block erase time
EEPROM bulk erase time
EEPROM programming voltage fall time
EEPROM minimum programming voltage
Symbol
Min.
Max.
Unit
fOSC
—
DC
3.579
3.579
MHz
fOP
—
DC
550.0
—
—
1.5
250.0
1.789
1.789
—
20.0
20.0
—
—
—
—
10.0
200.0
15.0
15.0
100.0
300.0
10.0
MHz
tCYC
tILCH
t
OXOV
tRL
t
ILIH
tILIL
t OH , tOL
t
RCON
t
ADON
t EPGM
t EBYTE
t EBLOCK
t EBULK
t FPV
V CCMIN
(1)
100.0
—
—
—
—
—
—
—
2.7
ns
ms
ms
t CYC
ns
t CYC
ns
µs
µs
ms
ms
ms
ms
µs
V
(1) The minimum period T ILIL should not be less than the number of cycle times it takes to execute
the interrupt service routine plus 21 CYC
t .
16
TPG
MOTOROLA
16-6
ELECTRICAL SPECIFICATIONS
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16.5
DC levels for low voltage RESET and LVI
Table 16-7 DC levels for low voltage reset and LVI
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(TA = –40°C to +85°C, unless otherwise stated)
Characteristic
Symbol
Min.
Typ.
Power-on reset voltage
V RON
2.55
2.8
Power-off reset voltage
VROFF
2.45
2.7
Low voltage interrupt
VLVI
2.75
3.0
16.6
Max.
3.05
2.95
3.25
Unit
V
V
V
Electrical specifications for DTMF/melody generator
Table 16-8 Sine wave tones at TNO
Characteristic
Operating voltage
Tone output level:
Low group – row
High group – column
Frequency deviation (DTMF)
Frequency deviation (Melody)
Tone output DC level
High group pre-emphasis
Total harmonic distortion
Min.
2.7
Typ.
—
Max.
5.5
0.120
0.160
– 0.65
– 1.5
0.45
1
—
0.160
0.205
0.210
0.280
+ 0.65
+ 1.5
0.55
3
—
0.50
2.15
–25
Unit
V
V rms
V rms
%
%
Vdd
dB
dB
Table 16-9 Square wave tones at TNO
Characteristic
Operating voltage
Tone output level:
Low group – row
High group – column
Frequency deviation (Melody)
Tone output DC level (+ 1/2 Vp-p value)
Min.
2.7
Typ.
—
—
—
– 1.5
0.45
0.270
0.360
0.50
Max.
5.5
Unit
V
V p-p
V p-p
+ 1.5
0.55
%
Vdd
16
TPG
MC68HC05F32
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Table 16-10 TONEX at TNX output
Characteristic
Operating voltage
Tone output level (square wave)
Frequency deviation
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16.7
Min.
2.7
Typ.
—
VDD
– 1.5
Max.
5.5
+ 1.5
Unit
V
V p-p
%
EEPROM additional information
Table 16-11 EEPROM additional information
Temperature
0 °C – 85 °C
50 °C
25 °C
16.8
Read/write
cycles
10 000
35 000
100 000
Remarks
The value is regularly tested and monitored
This value is predicted from the tested ones
This value is predicted from the tested ones
PWM timing
Table 16-12 PWM timing
Characteristic
PWM rise time
PWM fall time
Symbol
t PWMR
tPWMF
Min.
15.0
15.0
Max.
35.0
35.0
Unit
ns
ns
16
MOTOROLA
16-8
ELECTRICAL SPECIFICATIONS
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16.9
A/D converter characteristics
Table 16-13 A/D converter characteristics
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(VDD = 5.0 VDC ± 10%, V SS = 0 VDC , TA = –40°C to +85°C, unless otherwise stated)
Characteristic
Parameter
Min.
Max.
Resolution
Number of bits resolved by the A/D
8
—
Maximum deviation from the best straight
Non-linearity
line through A/D transfer characteristics
—
±1/2
(AV SS =V RH = VDD, AVSS = VSS )
Quantization error
Uncertainty due to converter resolution
—
±1/2
Difference between the actual input
Absolute accuracy
voltage and the full scale equivalent of
—
±1
the binary output code for all errors
Conversion range
Analog input voltage range
AV SS §
V RH
V RH
Maximum analog reference voltage
AV SS
V DD + 0.1
AV SS
Analog supply voltage
VSS – 0.1
—
Total time to perform a single analog to
digital conversion
Conversion time
a. External clock
—
32
b. internal RC oscillator
—
32
Conversion result never decreases with
Monotinicity
an increase in input voltage and has no
GUARANTEED
missing codes
Zero input reading
Conversion result when VIN = AVSS
00
Full scale reading
Conversion result when VIN = VRH
—
FF
Analog input acquisition sampling
—
12
Sample acquisition time(1)
a. External clock
b. Internal RC oscillator
—
12
Sample/hold capacitance
Input leakage
AV DD
Input capacitance on AN0–AN7
Input leakage on AN0–AN7
Input leakage on VRH
Analog supply voltage
—
—
—
12
10
1
1.125V RH
Unit
bit
LSB
LSB
LSB
V
V
V
tCYC
µs
Hex
Hex
tCYC
µs
pF
µA
µA
V
(1) Source impedances greater than 10 kΩ will adversely affect internal RC charging time during input
sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R
source and input current.
(3) A/D accuracy may decrease as V RH is reduced below 4V.
16
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Freescale Semiconductor, Inc.
17
MECHANICAL DATA
100-pin QFP pinout for the MC68HC05F32
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VRH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
OSC1
OSC2
IRQ
VSS
VDD
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PH7/FP39
PH6/FP38
17.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PH1/FP33
PH0/FP32
PG7/FP31
PG6/FP30
PG5/FP29
PG4/FP28
PG3/FP27
PG2/FP26
PG1/FP25
PG0/FP24
PH5/FP37
PH4/FP36
PH3/FP35
PH2/FP34
PF7/FP23
PF6/FP22
PF5/FP21
PF4/FP20
PF3/FP19
PF2/FP18
PF1/FP17
PF0/FP16
PI7/FP15
PI6/FP14
PI5/FP13
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AVDD
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
AVSS
PE0/TCAP1
PE1/TCMP1
PE2/TCAP2
PE3/TCMP2
PE4/REFRESH
PE5/PWM1
PE6/PWM2
PE7/PWM3
PC0/TCAP3
PC1/TCAP4
PC2/RDI
PC3/TDO
PC4/MISO
VDD
VSS
PC5/MOSI
PC6/SCK
PC7/SS
OSC3
OSC4
TNX
TNO
VLCD
BP0
BP1
BP2
BP3
PJ0/FP0
PJ1/FP1
PJ2/FP2
PJ3/FP3
PJ4/FP4
PJ5/FP5
PJ6/FP6
PJ7/FP7
PI0/FP8
PI1/FP9
PI2/FP10
PI3/FP11
PI4/FP12
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
17
Figure 17-1 100-pin QFP pinout for the MC68HC05F32
TPG
MC68HC05F32
MECHANICAL DATA
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17-1
156
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Freescale Semiconductor, Inc.
17.2
100-pin QFP mechanical dimensions
4X
% 4X 25 TIPS
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
–L–
–M–
B V
3X VIEW Y
B1
V1
–N–
A1
S1
A
S
2X 02
C
%
–H–
–T–
!%$
$! %!# "# $
* ! %#! $! %#
%& $ !% % !%%! ! $ ! % (% % (# %
)%$ % "$% !* % % !%%!
! % "#% %&$ %! %# % %& $! $ $ ' %! %# %
$% " %
$! $ ! !% & !
"#!%#&$! !( "#!%#&$! $
"# $ $! $ !
& ! $% #
%# % %& $! !$ !% & #
"#!%#&$! # "#!%#&$! $
!% &$ % (% %! ) & $" %( "#!%#&$!
% !# "#!%#&$! θ
θ
θ
θ
$
$
$
$
$
#
$
$
$
$
#
#
$
$
$
$
$
#
$
$
$
$
#
#
2X 03
$% " VIEW AA
$
$%
W
F
Θ1
2XR
R1
G
J
C2
" K
E
C1
Z
"% AB
Θ
U
D
–X–
)
% $
$
AB
SECTION AB–AB
#!%%°!($
VIEW Y
VIEW AA
CASE 983-01
17
Figure 17-2 100-pin QFP mechanical dimensions
TPG
MOTOROLA
17-2
MECHANICAL DATA
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Freescale Semiconductor, Inc.
80-pin QFP pinout for the MC68HC05F32
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PA6
PA5
PA4
PA3
PA2
PA1
PA0
OSC1
OSC2
IRQ
VSS
VDD
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
17.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PB0
PG7/FP31
PG6/FP30
PG5/FP29
PG4/FP28
PG3/FP27
PG2/FP26
PG1/FP25
PG0/FP24
PF7/FP23
PF6/FP22
PF5/FP21
PF4/FP20
PF3/FP19
PF2/FP18
PF1/FP17
PF0/FP16
PI7/FP15
PI6/FP14
PI5/FP13
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PA7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE0/TCAP1
PE1/TCMP1
PE2/TCAP2
PE3/TCMP2
PE4
PE5/PWM1
PE6/PWM2
PE7/PWM3
PC0/TCAP3
PC4
VDD
PC5
TNX
TNO
BP0
BP1
BP2
BP3
PJ0/FP0
PJ1/FP1
PJ2/FP2
PJ3/FP3
PJ4/FP4
PJ5/FP5
PJ6/FP6
PJ7/FP7
PI0/FP8
PI1/FP9
PI2/FP10
PI3/FP11
PI4/FP12
Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.
Figure 17-3 80-pin QFP pinout for the MC68HC05F32
Note:
The 80-pin version is only a bond option. Pins PE4, PD7–PD0, PC4, PC5 are shared
with module functions which cannot work on the 80-pin package. These modules and
their corresponding pin functions should not be enabled.
17
TPG
MC68HC05F32
MECHANICAL DATA
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17-3
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Freescale Semiconductor, Inc.
80-pin QFP mechanical dimensions
L
Case No. 841B - 01
80 QFP
60
B
41
61
17
-B-
L
B
Detail “A”
V
0.20 M H A – B S D S
-A-
P
B
40
0.20 M C A – B S D S
0.05 A – B
17.4
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
- A, B, D Detail “A”
F
21
N
J
80
1
-D-
20
Base
metal
D
A
Section B–B
0.20 M C A – B S D S
0.20 M C A – B S D S
0.05 A – B
S
U
T
0.20 M H A – B S D S
Detail “C”
R
M
Q
C
E
Datum
-H- plane
-CH
Seating
plane
G
K
W
M
X
Detail “C”
Dim.
A
B
C
D
E
F
G
H
J
K
L
Min.
Max.
13.90
14.10
13.90
14.10
2.15
2.45
0.22
0.38
2.00
2.40
0.22
0.33
0.65 BSC
—
0.250
0.130
0.230
0.65
0.95
12.35 REF
Notes
1. Datum plane –H– is located at bottom of lead and is coincident with
the lead where the lead exits the plastic body at the bottom of the
parting line.
2. Datums A–B and –D to be determined at datum plane –H–.
3. Dimensions S and V to be determined at seating plane –C–.
4. Dimensions A and B do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side. Dimensions A and B do
include mould mismatch and are determined at datum plane –H–.
5. Dimension D does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 total in excess of the D dimension
at maximum material condition. Dambar cannot be located on the
lower radius or the foot.
6. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
7. All dimensions in mm.
Dim.
M
N
Q
R
S
T
U
V
W
X
Min.
Max.
5°
10 °
0.130
0.170
0°
7°
0.13
0.30
16.95
17.45
0.13
—
0°
—
16.95
17.45
0.35
0.45
1.6 REF
Figure 17-4 80-pin QFP mechanical dimensions
TPG
MOTOROLA
17-4
MECHANICAL DATA
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Freescale Semiconductor, Inc.
18
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Freescale Semiconductor, Inc.
ORDERING INFORMATION
This section describes the information needed to order the MC68HC05F32.
To initiate a ROM pattern for the MCU, it is necessary to first contact your local field service office,
local sales person or Motorola representative. Please note that you will need to supply details such
as: mask option selections; temperature range; oscillator frequency; package type; electrical test
requirements; and device marking details so that an order can be processed, and a customer
specific part number allocated. Refer to Table 18-1 for appropriate part numbers.
Table 18-1 MC order numbers
Device title
MC68HC05F32
MC68HC705F32
MC68HC05F32
MC68HC705F32
Package type
100-pin QFP
80-pin QFP
100-pin QFP
80-pin QFP
100-pin QFP
80-pin QFP
100-pin QFP
80-pin QFP
Temperature
0 to 70 °C
0 to 70 °C
–40 to 85 °C
–40 to 85 °C
Part number
MC68HC05F32PU
MC68HC05F32FU
MC68HC705F32PU
MC68HC705F32FU
MC68HC05F32CPU
MC68HC05F32CFU
MC68HC705F32CPU
MC68HC705F32CFU
18
TPG
MC68HC05F32
ORDERING INFORMATION
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18-1
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Freescale Semiconductor, Inc.
18.1
EPROMs
For the MC68HC05F32, a 64K byte EPROM programmed with the customer’s software (positive
logic for address and data) should be submitted for pattern generation. All unused bytes should
be programmed to $00.
The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.
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Freescale Semiconductor, Inc.
18.2
Verification media
All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and returned with a listing verification form.
The listing should be thoroughly checked and the verification form completed, signed and returned
to Motorola. The signed verification form constitutes the contractual agreement for creation of the
custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from
the data file used to create the custom mask, to aid in the verification process.
18.3
ROM verification units(RVU)
Ten MCUs containing the customer’s ROM pattern will be provided for program verification. These
units will have been made using the custom mask but are for ROM verification only. For
expediency, they are usually unmarked and are tested only at room temperature (25°C) and at
5 Volts. These RVUs are included in the mask charge and are not production parts. They are
neither backed nor guaranteed by Motorola Quality Assurance.
18
TPG
MOTOROLA
18-2
ORDERING INFORMATION
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Freescale Semiconductor, Inc.
a
t
a
d
y
Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.
Aar
n
MC68HC705F32
i
m
i
l
e
r
P
The MC68HC705F32 is a device very similar to the MC68HC05F32 but has 32256 bytes of user
EPROM with 496 bytes of bootloader ROM. It does have the same amount of RAM, LCD RAM,
EEPROM, I/O, and user vectors. It also has the same on-board peripherals as the
MC68HC05F32.
There is also an 80-pin version of the MC68HC705F32, this has a reduced I/O count and reduced
functionality. It has no 32 kHz clock system, SPI, SCI or A/D converter. The timer has three input
captures (no TCAP4) and the LCD driver only has 32 frontplanes.
Note:
A.1
ta
a
d
The 80-pin version is only a bond option. Pins PE4, PD7–PD0, PC4, PC5 are shared
with module functions which cannot work on the 80-pin package. These modules and
their corresponding pin functions should not be enabled.
y
r
a
n
i
m
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e
Pr
Features
•
32256 bytes of user EPROM plus 16 bytes of user vectors
•
496 bytes of bootloader ROM
y
r
a
ta
a
d
n
i
m
i
l
e
Pr
TPG
MC68HC05F32
MC68HC705F32
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A-1
A
162
05F32Book Page 2 Tuesday, June 8, 1999 7:55 am
i
l
e
Pr
IC3
IC4
TDO
RDI
MISO
MOSI
SCK
SS
SCI 3
920 bytes RAM
SPI 3
20 bytes LCD RAM
OC2
IC2
OC1
IC1
Port E
Timer
PWM3
PWM2
PWM1
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Port C2
Keyboard interrupt
ar
16 bytes for vectors
n
i
m
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
Oscillator and divider
32 kHz independent clock
system, oscillator and divider3
OSC3
OSC4
2
2
REFRESH
Periodic interrupt
COP watchdog
y
r
a
M68HC05 CPU
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
8-channel
A/D
converter3
Core timer
IRQ/VPP
RESET
ta
a
d
TNO
TNX
DTMF/ melody generator
n
i
m
AVDD
VRH
VRL/AVSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
FP39
FP38
FP37
FP36
FP35
FP34
FP33
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
FP19
FP18
FP17
FP16
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Port H1, 2
Port G1
Port F1
Port I1
Port J1
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
LCD driver4
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
VLCD
BP3
BP2
BP1
BP0
yd
496 bytes bootloader ROM
256 bytes user EEPROM
OSC1
OSC2
VDD
VSS
ata
PWM
32256 bytes user EPROM
Port D
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port B
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
i
l
e
Pr
ta
a
d
1. When not being used to output the LCD frontplanes, port G and port F are input only, while port H, port I and port J are output only.
2. In the 80-pin package there is no port H and only pins PC0, PC4 and PC5 are available on port C.
3. These modules are not available in the 80-pin package.
4. In the 80-pin package there are only 32 frontplanes.
y
r
a
n
i
m
Figure A-1 MC68HC705F32 block diagram
i
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Pr
A
TPG
MOTOROLA
A-2
MC68HC705F32
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A.2
Pin descriptions
A.2.1
IRQ/VPP
a
t
a
d
y
r
a
in
As for the MC68HC05F32, this is an input-only pin for external interrupt sources. It also serves as
the EPROM programming voltage input pin (VPP) on the MC68HC705F32.
Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.
A.3
m
i
l
re
Memory and registers
P
The MC68HC705F32 has a 64K byte memory map consisting of registers (for I/O, control and
status), user RAM, user ROM, EEPROM, bootloader ROM and reset and interrupt vectors as
shown in Figure A-2.
A.3.1
Registers
ta
a
d
All the I/O, control and status registers of the MC68HC705F32 are contained within the first 80
byte block of the memory map, as detailed in Table A-1.
y
r
a
n
i
m
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e
Pr
y
r
a
ta
a
d
n
i
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Pr
TPG
MC68HC05F32
MC68HC705F32
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A-3
A
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Freescale Semiconductor, Inc.
MC68HC705F32
$0000
I/O
(80 bytes)
$0050
Unused
$0054
LCD RAM (20 bytes)
RAM
(920 bytes)
i
l
e
Pr
Stack
$0400
EEPROM
(256 bytes)
$0500
Unused
$8000
User EPROM
(32256 bytes)
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
Port D data (PORTD)
Port A DDR (DDRA)
Port B DDR (DDRB)
Port C DDR (DDRC)
Port D DDR (DDRD)
Ctimer control/status (CTCSR)
Ctimer counter (CTCR)
Port E data (PORTE)
Port E DDR (DDRE)
Port E control (PECR)
Row freq. control (FCR)
Column freq. control (FCC)
Tone control (TNCR)
Port F data (PORTF)
Port F control (PFCR)
Port G data (PORTG)
Port G control (PGCR)
Port H data (PORTH) (1)
Port H control (PHCR)(1)
Port I data (PORTI)
Port I control (PICR)
Port J data (PORTJ)
Port J control (PJCR)
Port D control (PDCR)
Key control (KCR)
EEPROM prog. (EEPROG)
EPROM prog. (PROG)
LCD control (LCD)
$20
$21
$22
$23
$24
$25
$26
$27
Capture 1 high (ICR1H)
Capture 1 low (ICR1L)
Compare 1 high (OCR1H)
Compare 1 low (OCR1L)
Capture 2 high (ICR2H)
Capture 2 low (ICR2L)
Compare 2 high (OCR2H)
Compare 2 low (OCR2L)
y
r
a
y
r
a
Bootloader ROM
(496 bytes)
$FFF0
User vectors
(16 bytes)
$FFFF
y
r
a
n
i
m
$28
$29
$2A
$2B
$2C
$2D
$2E
Counter 1 high (CNTH/1)
Counter 1 low (CNTL/1)
Alt. counter high 1 (ACNTH/1)
Alt. counter low 1 (ACNTL/1)
Timer 1 control 1 (TCR1/1)
Timer 1 control 2 (TCR2/1)
Timer 1 status (TSR/1)
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
$3C
$3D
$3E
Capture 3 high (ICR3H)
Capture 3 low (ICR3L)
Compare 3 high (OCR3H)
Compare 3 low (OCR3L)
Capture 4 high (ICR4H)
Capture 4 low (ICR4L)
Compare 4 high (OCR4H)
Compare 4 low (OCR4L)
Counter 2 high (CNTH/2)
Counter 2 low (CNTL/2)
Alt. counter high 2 (ACNTH/2)
Alt. counter low 2 (ACNTL/2)
Timer 2 control 1 (TCR1/2)(1)
Timer 2 control 2 (TCR2/2)(1)
Timer 2 status (TSR/2)(1)
$40
$41
$42
$43
$44
$45
$46
$47
$48
$49
$4A
$4B
$4C
$4D
$4E
$4F
PWM control (PWMCR)
PWM data 1 (PWMD1)
PWM data 2 (PWMD2)
PWM data 3 (PWMD3)
SPI control (SPCR) (1)
SPI status (SPSR) (1)
SPI data I/O (SPDAT) (1)
SCI data (SCDAT) (1)
SCI control 1 (SCCR1) (1)
SCI control 2 (SCCR2) (1)
SCI status (SCSR) (1)
SCI baud rate (BAUD) (1)
CPI control/status (CPICSR)
System options (SOR)
A/D data (ADDATA) (1)
A/D status/control (ADSCR) (1)
ta
a
d
n
i
m
i
l
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Pr
$FF00
ta
a
d
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
n
i
m
$0068
Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.
ta
a
d
(1) Not applicable to 80-pin package.
i
l
e
Pr
Figure A-2 Memory map of the MC68HC705F32
A
TPG
MOTOROLA
A-4
MC68HC705F32
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Table A-1 Register outline
Register Name
Address bit 7
Port A data (PORTA)
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$0000
PA7
Key interrupt status (KISR)
$0000
Port B data (PORTB)
$0001
PB7
Port C data (PORTC)
$0002
PC7
Port A data direction (DDRA)
Port B data direction (DDRB)
$0003
PD7
$0004
P
Port C data direction (DDRC)
Port D data direction ((DDRD)
bit 5
bit 4
PA6
PA5
PA4
a
t
a
bit 3
bit 2
d
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r
a
in
m
i
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re
Port D data (PORTD)
bit 6
PA3
bit 1
State
on reset
bit 0
PA2
PA1
PA0
undefined
0000 0000
PB6
PB5
PB4
PB3
PB2
PB1
PB0
undefined
PC6
PC5
PC4
PC3
PC2
PC1
PC0
undefined
PD6
PD5
PD4
PD3
PD2
PD1
PD0
undefined
0000 0000
$0005
0000 0000
$0006
0000 0000
$0007
0000 0000
Core timer control/status (CTCSR)
$0008
Core timer counter (CTCR)
$0009
Port E data (PORTE)
$000A
Port E data direction (DDRE)
$000B
TOF
RTIF
PE7
PE6
Port E control (PECR)
$000C
$000D
0
0
DTMF column freq. control (FCC)
$000E
0
0
DTMF tone control (TNCR)
$000F
MS1
MS0
Port F data (PORTF)
$0010
PF7
PF6
Port G data (PORTG)
$0012
Port G control (PGCR)
$0013
Port H data (PORTH)
$0014
Port H control (PHCR)
$0015
Port I data (PORTI)
$0016
Port I control (PICR)
$0017
Port J data (PORTJ)
$0018
Port J control (PJCR)
$0019
Port D control (PDCR)
$001A
Key control (KCR)
$001B
PE5
RTOF RRTIF
RT1
RT0
0000 0011
PG7
PG6
PE4
PE3
PE2
PE1
ata
PE0
0000 0000
0
d
y
ar
undefined
0
0000 0000
0
FCR4 FCR3 FCR2 FCR1 FCR0 undefined
0
FCC4 FCC3 FCC2 FCC1 FCC0 undefined
n
i
m
i
l
e
Pr
$0011
RTIE
0000 0000
DTMF row freq. control (FCR)
Port F control (PFCR)
TOFE
TGER TGEC TNOE
PF5
PF4
PF3
0
0
0
0000 0000
PF2
PF1
PF0
undefined
0000 0000
PG5
PG4
PG3
PG2
PG1
PG0
undefined
0000 0000
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
0000 0000
0000 0000
PI7
PI6
PJ7
PJ6
PI5
PJ5
PI4
PJ4
KIE
PI1
ata
PJ3
PJ2
PJ1
PI0
0000 0000
0000 0000
PJ0
0000 0000
0000 0000
0000 0000
EDG5 EDG4 EDG3 EDG2 EDG1 EDG0 0000 0000
EEPROM prog. (EEPROG)
$001C
0
CPEN
0
ER1
EPROM prog. (PROG)
$001D
0
0
0
TS1
m
i
l
re
PI2
yd
r
a
in
KF
PI3
ER0 LATCH EERC EEPGM 0000 0000
TS0 ELATCH
0
EPGM 0000 0000
$001E WTLCDO FSEL1 FSEL0 I NTVLCD FDISP MUX4 MUX3 EXTVON 0000 0000
LCD control (LCD)
P
Capture 1 high (ICR1H)
Capture 1 low (ICR1L)
$0020
(bit 15)
$0021
(bit 8)
undefined
undefined
TPG
MC68HC05F32
MC68HC705F32
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A-5
A
166
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Freescale Semiconductor, Inc.
Table A-1 Register outline
Register Name
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
A
Address bit 7
Compare 1 high (OCR1H)
$0022
Compare 1 low (OCR1L)
$0023
Capture 2 high (ICR2H)
$0024
Capture 2 low (ICR2L)
$0025
Compare 2 high (OCR2H)
$0026
bit 6
bit 5
(bit 15)
y
r
a
(bit 15)
$0027
Counter 1 high (CNTH/1)
$0028
Counter 1 low (CNTL/1)
$0029
Alternate counter 1 high (ACNTH/1)
bit 2
bit 1
bit 0
State
on reset
(bit 8)
undefined
undefined
(bit 8)
undefined
(bit 8)
undefind
undefined
(bit 8) 1111 1111
$002A (bit 15)
(bit 8) 1111 1111
1111 1100
$002B
Timer1 control 1 (TCR1/1)
$002C
Timer1 control 2 (TCR2/1)
$002D
0
0
OCI2E
Timer1 status (TSR/1)
$002E
IC1F
IC2F
OC1F
Capture 3 high (ICR3H)
$0030
(bit 15)
Capture 3 low (ICR3L)
$0031
Compare 3 high (OCR3H)
$0032
Compare 3 low (OCR3L)
$0033
1111 1100
ICI1E
ICI2E OCI1E TOIE CO1E IEDG1 IEDG2 OLVL1 0000 0uu0
$0034
Capture 4 low (ICR4L)
$0035
Compare 4 high (OCR4H)
$0036
Compare 4 low (OCR4L)
$0037
Counter 1 high (CNTH/1)
$0038
0
CO2E
0
0
ata
TOF TCAP1 TCAP2 OC2F
yd
ar
n
i
m
(bit 15)
i
l
e
Pr
Capture 4 high (ICR4H)
OLVL2 0000 0000
0
uuuu uuu0
(bit 8)
undefined
undefined
(bit 8)
undefined
undefined
(bit 15)
undefined
(bit 15)
undefined
undefined
undefined
(bit 15)
(bit 8) 1111 1111
$003A (bit 15)
(bit 8) 1111 1111
$0039
Alternate counter 2 high (ACNTH/1)
undefined
(bit 15)
Alternate counter 1 low (ACNTL/1)
Counter 1 low (CNTL/1)
ta
a
d
bit 3
n
i
m
(bit 15)
i
l
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Pr
Compare 2 low (OCR2L)
bit 4
1111 1100
Alternate counter 2 low (ACNTL/1)
$003B
Timer2 control 1 (TCR1/2)
$003C
Timer2 control 2 (TCR2/2)
$003D
0
Timer2 status (TSR/2)
$003E
IC3F
PWM control (PWMCR)
$0040
PWM data 1 (PWMD1)
$0041
ICI3E
0
OCI4E
IC4F
OC3F
r
a
in
m
i
l
e
Pr
PWM data 2 (PWMD2)
$0042
PWM data 3 (PWMD3)
$0043
SPI control (SPCR)
$0044
SPIE
yd
ata
1111 1100
0000 0uu0
ICI4E OCI3E TOIE CO3E IEDG3 IEDG4
SPE
0
CO4E
0
0
0000 0000
TOF TCAP3 TCAP4 OC4F
0
POL3 POL2 POL1
RA0
RA1
uuuu uuu0
0001 1100
1000 0000
1000 0000
1000 0000
DOD MSTR CPOL CPHA SPR1 SPR0 0000 01uu
TPG
MOTOROLA
A-6
MC68HC705F32
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Freescale Semiconductor, Inc.
Table A-1 Register outline
Register Name
Address bit 7
SPI status (SPSR)
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
$0045
SPI data I/O (SPDAT)
$0046
SCI data (SCDAT)
$0047
SCI control 1 (SCCR1)
$0048
SCI status (SCSR)
P
CPI control status (CPICSR)
System options (SOR)
A/D data (ADDATA)
bit 5
SPIF WCOL
$0049
TIE
$004A
TDRE
$004B
TCLR
0
bit 4
bit 1
bit 0
d
y
0
0
0
MODF
bit 3
a
t
a
bit 2
r
a
in
R8
m
i
l
re
SCI control 2 (SCCR2)
SCI baud rate (BAUD)
bit 6
0
0000 0000
undefined
undefined
T8
0
M
WAKE
0
0
0
uu00 0000
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0000 0000
TC
RDRF
IDLE
OR
0
1100 0000
0
NF
FE
SCP1 SCP0 RCKB SCR2 SCR1 SCR0 0000 0uuu
$004C
0
CPIF
0
CPIE
0
$004D
LVIF
LVIE
LVION
SC
IRQ
0
CH3
0
RFQ1 RFQ0 0000 0000
KEYMUX KEYCLRPUEN 0000 0000
$004E
A/D status/control (ADSCR)
State
on reset
undefined
$004F COCO ADRC ADON
y
r
a
CH2
CH1
ta
a
d
CH0
0000 0000
u = undefined
n
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ta
a
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TPG
MC68HC05F32
MC68HC705F32
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MOTOROLA
A-7
A
168
05F32Book Page 8 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
A.3.2
EPROM
ta
a
d
The MC68HC705F32 has 32256 bytes of EPROM located from $8000 to $FDFF, plus 16 bytes of
user vectors from $FFF0 to $FFFF. Up to 16 bytes of EPROM can be programmed simultaneously
by correctly manipulating the bits in the EPROM programming register.
A.3.2.1
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
y
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EPROM programming register (PROG)
i
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Address
EPROM programming (PROG)
$001D
bit 7
bit 6
bit 5
bit 4
0
0
0
0
bit 3
0
bit 2
ELATCH
bit 1
0
bit 0
State
on reset
EPGM 0000 0000
EPGM — EPROM program control
1 (set)
–
0 (clear) –
Programming power connected to the EPROM array.
Programming power disconnected from the EPROM array.
ta
a
d
ELATCH and EPGM cannot be set on the same write operation. EPGM can only be set if ELATCH
is set. EPGM is automatically cleared when ELATCH is cleared.
y
r
a
ELATCH — EPROM latch control
1 (set)
–
EPROM address and data buses configured for programming.
0 (clear) –
EPROM address and data buses configured for normal reads
n
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Pr
ELATCH causes address and data buses to be latched when a write to EPROM is carried out. The
EPROM cannot be read if ELATCH = 1. This bit should not be set unless a programming voltage
is applied to the VPP pin.
A.3.2.2
EPROM programming operation
ta
a
d
The following steps should be taken to program a byte of EPROM:
1) Apply the programming voltage VPP to the IRQ pin.
2) Set the ELATCH bit.
y
r
a
3) Write to the EPROM address.
4) Set the EPGM bit for a time tEPGM to apply the programming voltage.
5) Clear the ELATCH bit.
i
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Pr
n
i
m
If the address bytes A15–A4 do not change, i.e. all bytes are located within the same 16 byte
address block, then multibyte programming is permitted. The multibyte programming facility allows
up to 16 bytes of data to be written to the desired addresses after the ELATCH bit has been set.
A
TPG
MOTOROLA
A-8
MC68HC705F32
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05F32Book Page 9 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
A.4
Electrical specifications
a
t
a
This section gives the electrical specifications for the MC68HC705F32, the EPROM version of the
MC68HC05F32. Contained in this section is the information specific to the MC68HC705F32 which
differs from that detailed in Section 16.
d
y
A.4.1
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
r
a
in
EPROM characteristics
m
i
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re
Table A-2 EPROM characteristics
P
Characteristic
EPROM programming voltage rate
EPROM programming voltage
EPROM programming time
A.4.2
Symbol
V PP
V PP
t EPGM
Value
V SS - 0.3 to +17 + 0.5
typ. 17.0
min. 4.0
Unit
V
V
ms
ta
a
d
DC levels for low voltage reset and LVI
y
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Table A-3 DC levels for low voltage reset and LVI
n
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r
(TA = 0C to 60°C, unless otherwise stated)
Characteristic
Symbol
Min.
Power-on reset voltage
V RON
2.55
Power-off reset voltage
VROFF
2.45
Low voltage interrupt
VLVI
2.75
P
Typ.
2.8
2.7
3.0
y
r
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Max.
3.05
2.95
3.25
Unit
V
V
V
ta
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Pr
TPG
MC68HC05F32
MC68HC705F32
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A-9
A
170
05F32Book Page 10 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
A.5
Mechanical data
A.5.1
100-pin QFP pinout for the MC68HC705F32
y
r
a
ta
a
d
VRH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
OSC1
OSC2
IRQ/VPP
VSS
VDD
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PH7/FP39
PH6/FP38
n
i
m
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
i
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e
Pr
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
y
r
a
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
ta
a
d
n
i
m
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Pr
PH1/FP33
PH0/FP32
PG7/FP31
PG6/FP30
PG5/FP29
PG4/FP28
PG3/FP27
PG2/FP26
PG1/FP25
PG0/FP24
PH5/FP37
PH4/FP36
PH3/FP35
PH2/FP34
PF7/FP23
PF6/FP22
PF5/FP21
PF4/FP20
PF3/FP19
PF2/FP18
PF1/FP17
PF0/FP16
PI7/FP15
PI6/FP14
PI5/FP13
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AVDD
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
AVSS
PE0/TCAP1
PE1/TCMP1
PE2/TCAP2
PE3/TCMP2
PE4/REFRESH
PE5/PWM1
PE6/PWM2
PE7/PWM3
PC0/TCAP3
PC1/TCAP4
PC2/RDI
PC3/TDO
PC4/MISO
VDD
VSS
PC5/MOSI
PC6/SCK
PC7/SS
OSC3
OSC4
TNX
TNO
VLCD
BP0
BP1
BP2
BP3
PJ0/FP0
PJ1/FP1
PJ2/FP2
PJ3/FP3
PJ4/FP4
PJ5/FP5
PJ6/FP6
PJ7/FP7
PI0/FP8
PI1/FP9
PI2/FP10
PI3/FP11
PI4/FP12
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
ta
a
d
Figure 18-1 100-pin QFP pinout for the MC68HC705F32
For package dimensions, refer to Section 17.2.
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Pr
A
MOTOROLA
A-10
MC68HC705F32
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MC68HC05F32
05F32Book Page 11 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
A.5.2
80-pin QFP pinout for the MC68HC705F32
a
t
a
d
y
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PA6
PA5
PA4
PA3
PA2
PA1
PA0
OSC1
OSC2
IRQ/VPP
VSS
VDD
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
r
a
in
PA7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE0/TCAP1
PE1/TCMP1
PE2/TCAP2
PE3/TCMP2
PE4
PE5/PWM1
PE6/PWM2
PE7/PWM3
PC0/TCAP3
PC4
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
m
i
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re
P
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
y
r
a
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PB0
PG7/FP31
PG6/FP30
PG5/FP29
PG4/FP28
PG3/FP27
PG2/FP26
PG1/FP25
PG0/FP24
PF7/FP23
PF6/FP22
PF5/FP21
PF4/FP20
PF3/FP19
PF2/FP18
PF1/FP17
PF0/FP16
PI7/FP15
PI6/FP14
PI5/FP13
ta
a
d
PC5
TNX
TNO
BP0
BP1
BP2
BP3
PJ0/FP0
PJ1/FP1
PJ2/FP2
PJ3/FP3
PJ4/FP4
PJ5/FP5
PJ6/FP6
PJ7/FP7
PI0/FP8
PI1/FP9
PI2/FP10
PI3/FP11
PI4/FP12
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
n
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Pr
Figure 18-2 80-pin QFP pinout for the MC68HC705F32
Note:
ta
a
d
The 80-pin version is only a bond option. Pins PE4, PD7–PD0, PC4, PC5 are shared
with module functions which cannot work on the 80-pin package. These modules and
their corresponding pin functions should not be enabled.
y
r
a
n
i
m
For package dimensions, refer to Section 17.4.
i
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Pr
MC68HC05F32
MC68HC705F32
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MOTOROLA
A-11
A
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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THIS PAGE LEFT BLANK INTENTIONALLY
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A
MOTOROLA
A-12
MC68HC705F32
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Freescale Semiconductor, Inc.
GLOSSARY
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
This section contains abbreviations and specialist words used in this data
sheet and throughout the industry. Further information on many of the terms
may be gleaned from Motorola’s M68HC11 Reference Manual,
M68HC11RM/AD, or from a variety of standard electronics text books.
$xxxx
The digits following the ‘$’ are in hexadecimal format.
%xxxx
The digits following the ‘%’ are in binary format.
A/D, ADC
Analog-to-digital (converter).
Bootstrap mode
In this mode the device automatically loads its internal memory from an
external source on reset and then allows this program to be executed.
Byte
Eight bits.
CCR
Condition codes register; an integral part of the CPU.
CERQUAD
A ceramic package type, principally used for EPROM and high temperature
devices.
Clear
‘0’ — the logic zero state; the opposite of ‘set’.
CMOS
Complementary metal oxide semiconductor. A semiconductor technology
chosen for its low power consumption and good noise immunity.
COP
Computer operating properly. aka ‘watchdog’. This circuit is used to detect
device runaway and provide a means for restoring correct operation.
CPU
Central processing unit.
D/A, DAC
Digital-to-analog (converter).
EEPROM
Electrically erasable programmable read only memory. aka ‘EEROM’.
EPROM
Erasable programmable read only memory. This type of memory requires
exposure to ultra-violet wavelengths in order to erase previous data. aka
‘PROM’.
ESD
Electrostatic discharge.
Expanded mode
In this mode the internal address and data bus lines are connected to
external pins. This enables the device to be used in much more complex
systems, where there is a need for external memory for example.
TPG
MC68HC05F32
GLOSSARY
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
EVS
Evaluation system. One of the range of platforms provided by Motorola for
evaluation and emulation of their devices.
HCMOS
High-density complementary metal oxide semiconductor. A semiconductor
technology chosen for its low power consumption and good noise immunity.
I/O
Input/output; used to describe a bidirectional pin or function.
Input capture
(IC) This is a function provided by the timing system, whereby an external
event is ‘captured’ by storing the value of a counter at the instant the event
is detected.
Interrupt
This refers to an asynchronous external event and the handling of it by the
MCU. The external event is detected by the MCU and causes a
predetermined action to occur.
IRQ
Interrupt request. The overline indicates that this is an active-low signal
format.
K byte
A kilo-byte (of memory); 1024 bytes.
LCD
Liquid crystal display.
LSB
Least significant byte.
M68HC05
Motorola’s family of 8-bit MCUs.
MCU
Microcontroller unit.
MI BUS
Motorola interconnect bus. A single wire, medium speed serial
communications protocol.
MSB
Most significant byte.
Nibble
Half a byte; four bits.
NRZ
Non-return to zero.
Opcode
The opcode is a byte which identifies the particular instruction and operating
mode to the CPU. See also: prebyte, operand.
Operand
The operand is a byte containing information the CPU needs to execute a
particular instruction. There may be from 0 to 3 operands associated with an
opcode. See also: opcode, prebyte.
Output compare
(OC) This is a function provided by the timing system, whereby an external
event is generated when an internal counter value matches a predefined
value.
PLCC
Plastic leaded chip carrier package.
PLL
Phase-locked loop circuit. This provides a method of frequency
multiplication, to enable the use of a low frequency crystal in a high
frequency circuit.
Prebyte
This byte is sometimes required to qualify an opcode, in order to fully specify
a particular instruction. See also: opcode, operand.
TPG
MOTOROLA
xiv
GLOSSARY
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Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are
permanently connected to either ground or VDD.
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PWM
Pulse width modulation. This term is used to describe a technique where the
width of the high and low periods of a waveform is varied, usually to enable
a representation of an analog value.
QFP
Quad flat pack package.
RAM
Random access memory. Fast read and write, but contents are lost when
the power is removed.
RFI
Radio frequency interference.
RTI
Real-time interrupt.
ROM
Read-only memory. This type of memory is programmed during device
manufacture and cannot subsequently be altered.
RS-232C
A standard serial communications protocol.
SAR
Successive approximation register.
SCI
Serial communications interface.
Set
‘1’ — the logic one state; the opposite of ‘clear’.
Silicon glen
An area in the central belt of Scotland, so called because of the
concentration of semiconductor manufacturers and users found there.
Single chip mode
In this mode the device functions as a self contained unit, requiring only I/O
devices to complete a system.
SPI
Serial peripheral interface.
Test mode
This mode is intended for factory testing.
TTL
Transistor-transistor logic.
UART
Universal asynchronous receiver transmitter.
VCO
Voltage controlled oscillator.
Watchdog
see ‘COP’.
Wired-OR
A means of connecting outputs together such that the resulting composite
output state is the logical OR of the state of the individual outputs.
Word
Two bytes; 16 bits.
XIRQ
Non-maskable interrupt request. The overline indicates that this has an
active-low signal format.
TPG
MC68HC05F32
GLOSSARY
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MOTOROLA
xvi
GLOSSARY
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INDEX
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In this index numeric entries are placed first; page references in italics indicate that the reference
is to a figure.
100-pin QFP
MC68HC05F32 pinout 17–1
MC68HC705F32 pinout A–10
mechanical dimensions 17–2
32 kHz clock system
during STOP mode 13–2
during WAIT mode 13–2
refresh clock 13–2
80-pin QFP
MC68HC05F32 pinout 17–3
MC68HC705F32 pinout A–11
mechanical dimensions 17–4
A
A – accumulator 15–1
A/D converter
ADDATA 9–5
ADSCR 9–3
AN7–AN0 2–6
analog input 9–5
block diagram 9–2
channel selection 9–1 9–4
conversion 9–3
during STOP mode 9–5
during WAIT mode 9–5
operation 9–1
RC oscillator 9–3
stabilization 9–4
successive approximation (SAR) 9–1
ADDATA — A/D result data register 9–5
addressing modes 15–5 15–13
ADON bit in ADSCR 9–4
ADRC bit in ADSCR 9–3
ADSCR — A/D status/control register
ADON – A/D converter on bit 9–4
ADRC – A/D RC oscillator flag 9–3
CH2–CH0 – A/D channel selection bits 9–4
COCO – conversion complete flag 9–3
alternate counter register 6–3
AN7–AN0 2–6
AVDD 2–6
AVSS 2–6
,
–
B
BAUD — baud rate register 11–14
SCP1, SCP0 – serial prescaler select bits 11–15
SCT2, SCT1, SCT0 – SCI rate select bits 11–15
baud rate selection 11–16
bit set/clear addressing mode 15–13
bit test and branch addressing mode 15–13
block diagrams
A/D converter 9–2
core timer 5–1
LCD 8–1
MC68HC05F32 1–3
MC68HC705F32 A–2
programmable timer 6–2
PWM 12–1
SCI 11–2
SPI 10–5
BP3–PB0 2–7
C
C-bit in CCR 15–3
CCR – condition code register 15–2
CH2–CH0 bits in ADSCR 9–4
clocks – see oscillator clock
CO1E bit in TCR1 6–5
CO2E bit in TCR2 6–6
COCO bit in ADSCR 9–3
control timing 16–5
COP 14–2
COP watchdog timer 5–5
COP reset times 5–5
core timer
block diagram 5–1
CTCR — counter register 5–4
CTCSR — control/status register 5–3
during STOP mode 5–5
during WAIT mode 5–5
interrupts 5–2 14–4
counter
alternate counter register 6–3
,
TPG
MC68HC05F32
INDEX
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xvii
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counter register 6–3
programmable timer 6–1
CPEN-bit in EPROG 3–6
CPHA bit in SPCR 10–7
CPICSR
CPIE – custom periodic interrupt enable 13–1
CPIF – custom periodic interrupt flag 13–1
RFQ1, RFQ0 – refresh frequency select 13–2
CPICSR — custom periodic interrupt control/status register
13–1
CPIE bit in CPICSR 13–1
CPIF bit in CPICSR 13–1
CPOL 10–7
CPOL bit in SCCR1 11–11
CPOL bit in SPCR 10–7
CPU
A – accumulator 15–1
addressing modes 15–5 15–13
CCR – condition code register 15–2
instruction set 15–3 15–11
PC – program counter 15–2
programming model 15–1
SP – stack pointer 15–2
stacking order 15–2
X – index register 15–2
crystal 2–8
CTCR — core timer counter register 5–4
CTCSR — core timer control/status register
CTOF – core timer overflow 5–3
CTOFE– core timer overflow enable 5–3
RT1, RT0 real time interrupt rate select 5–4
RTIE – real time interrupt enable 5–3
RTIF – real time interrupt flag 5–3
–
–
D
data retention mode 2–2
DC characteristics 16–3
direct addressing mode 15–7
DMG registers
FCC — column frequency control register 7–4
FCR — row frequency control register 7–4
TNCR — tone control register 7–4
DOD bit in SPCR 10–7
DTMF/melody generator (DMG)
during STOP mode 7–8
during WAIT mode 7–8
features 7–1
operation 7–7
E
EDG0–EDG5 – trigger edge control 4–4
EEPGM-bit in EPROG 3–8
EEPROM 3–6
EPROG – EEPROM programing register 3–6
erase modes 3–7
MOTOROLA
xviii
erasing procedures 3–8
LATCH - latch bit 3–7
programming procedures 3–8
sample programming sequence 3–8
EERC-bit in EPROG 3–7
ELATCH bit in PROG A–8
electrical specifications
A/D converter 16–9
control timing (5V) 16–5
DC characteristics (5V) 16–3
DTMF/melody generator 16–7
EPROM characteristics A–9
maximum ratings 16–1
PWM timing 16–8
thermal characteristics 16–2
EPGM bit in PROG A–8
EPROG – EEPROM programing register 3–6
EPROM
multibyte programming A–8
PROG — EPROM programming register A–8
programming A–8
ER1, ER0 bits in EPROG 3–7
extended addressing mode 15–12
external clock 2–8
EXTVON bit in LCD 8–10
F
FCC — column frequency control register 7–4
FCR — row frequency control register 7–4
FDISP bit in LCD 8–10
FE bit in SCSR 11–14
features
MC68HC05F32 1–2
MC68HC705F32 A–1
flowcharts
interrupt 14–5
STOP and WAIT 2–3
FP39–FP0 2–7
frontplane pins 2–7
H
H-bit in CCR 15–3
I
I/O port structure 4–4
I/O ports
I/O port structure 4–4
port A 4–2
port B 4–4
port C 4–5
port D 4–5
port E 4–6
ports F, G, H, I, J 4–6
INDEX
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programming 4–1
I-bit in CCR 15–3
IC1F, IC2F bits in TSR 6–7
IC1IE bit in TCR 6–5
IC2IE bit in TCR1 6–5
ICR1 — input capture register 6–9
IDLE bit in SCSR 11–13
IEDG1 bit in TCR1 6–5
IEDG2 bit in TCR1 6–6
ILIE bit in SCCR2 11–11
illegal address reset 14–1
immediate addressing mode 15–6
indexed addressing modes 15–12
inherent addressing mode 15–6
input capture 6–9
instruction set 15–3 15–11
tables of instructions 15–5 15–11
interrupts 14–3
core timer 14–4
hardware 14–4
interrupt flowchart 14–5
keyboard 14–7
maskable 14–4
nonmaskable 14–4
priorities 14–4
programmable timer 14–6
real-time 5–2 14–4
software (SWI) 14–4
INTVLCD bit in LCD 8–9
IRQ 2–5
IRQ bit in SOR 2–4
–
–
,
K
key control register
EDG0–EDG5 – trigger edge control 4–4
KF – keyboard interrupt status flag 4–3
KIE – keyboard interrupt enable 4–4
keyboard interrupt 2–5 4–2 14–7
KEYCLR bit in SOR 2–4
KEYMUX bit in SOR 2–4
,
M
M bit in SCCR1 11–10
mask options 1–2
maximum ratings 16–1
MC68HC05F32
block diagram 1–3
features 1–2
mask options 1–2
MC68HC705F32
block diagram A–2
features A–1
memory
bootloader ROM 3–6
EEPROM 3–6
EPROM A–8
memory map 3–2 A–4
RAM 3–5
ROM 3–5
MISO 2–6
modes of operation
low power modes 2–1
single-chip 2–1
MODF bit in SPSR 10–8
MOSI 2–6
MSTR 10–7
MSTR bit in SPCR 10–7
MUX4, MUX3 bits in LCD 8–10
,
,
N
N-bit in CCR 15–3
NF bit in SCSR 11–14
L
LATCH-bit in EPROG 3–7
LCD
block diagram 8–1
during STOP mode 8–10
during WAIT mode 8–10
RAM 8–2
timing diagrams 8–4 8–8
timing signals 8–4
voltage level selection 8–4
LCD — LCD control register
EXTVON – external LCD voltage ON/OFF 8–10
FDISP – display frequency 8–10
INTVLCD - internal voltage generator ON/OFF 8–9
–
MC68HC05F32
MUX4, MUX3 – multiplex ratio 8–10
WTLCDO – WAIT mode LCD only 8–9
low power modes 2–1
data retention 2–2
RESET, STOP, WAIT – as interrupt sequence 14–8
STOP 2–1
WAIT 2–2
LVIF, LVIE, LVION bits in SOR 2–4
O
OC1IE bit in TCR1 6–5
OC2IE bit in TCR2 6–6
OCR1, OCR2 — output compare registers 6–11
OLVL1 bit in TCR1 6–6
OLVL2 bit in TCR2 6–6
OR bit in SCSR 11–13
OSC1, OSC2 pins 2–7
OSC3, OSC4 pins 2–7
oscillator clock
connections 2–9
crystal 2–8
INDEX
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MOTOROLA
xix
05F32Book Page xx Tuesday, June 8, 1999 7:55 am
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external clock 2–8
output compare 6–11
P
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PA7–PA0 2–5
packages
MC68HC05F32 100-pin QFP 17–1
MC68HC05F32 80-pin QFP 17–3
MC68HC705F32 100-pin QFP A–10
MC68HC705F32 80-pin QFP A–11
PB7–PB0 2–5
PC – program counter 15–2
PC7–PC0 2–6
PD7–PD0 2–6
PE7–PE0 2–6
pins
AN7–AN0 2–6
AVDD 2–6
AVSS 2–6
BP3–BP0 2–7
FP39–FP0 2–7
IRQ 2–5
keyboard interrupt 2–5
MISO 2–6
MOSI 2–6
OSC1, OSC2 2–7
OSC3, OSC4 2–7
PA7–PA0 2–5
PB7–PB0 2–5
PC7–PC0 2–6
PD7–PD0 2–6
PE7–PE0 2–6
ports F, G, H, I, J 2–7
PWM1 2–6
PWM2 2–6
PWM3 2–6
RDI 2–6 11–6
REFRESH 2–6
RESET 2–5 14–1
SCK 2–6
SS 2–6
TCAP1 2–6
TCAP2 2–6
TCAP3 2–6
TCAP4 2–6
TCMP1 2–6
TCMP2 2–6
TDO 2–6
TNO, TNX 2–7
VDD, VSS 2–5
VLCD 2–7
VRH 2–6
POL1 bit in the PWM control register 12–3
POL2 bit in the PWM control register 12–3
POL3 bit in the PWM control register 12–3
POR – see power-on reset
port A 4–2
keyboard interrupt 4–2
,
,
MOTOROLA
xx
port B 4–4
port C 4–5
port D 4–5
port E 4–6
port registers
data direction registers 4–7
port data registers 4–7
ports F, G, H, I, J 4–6
ports F, G, H, I, J pins 2–7
power-on reset 14–1
PROG — EPROM programming register A–8
ELATCH – EPROM latch control A–8
EPGM – EPROM program control A–8
programmable timer
block diagram 6–2
counter 6–1
during STOP mode 6–13
during WAIT mode 6–13
ICR1 6–9
interrupts 14–6
OCR1, OCR2 6–11
TCR1, TCR2 6–4
timing diagrams 6–13
TSR 6–7
programming
EEPROM 3–8
EPROM A–8
PUEN bit in SOR 2–4
PWM 12–4
block diagram 12–1
control register 12–3
during reset 12–5
during STOP mode 12–5
during WAIT mode 12–4
waveforms 12–2 12–3
PWM control register
POL1 – PWM1 polarity 12–3
POL2 – PWM2 polarity 12–3
POL3 – PWM3 polarity 12–3
PWM timing 16–8
PWM1 2–6
PWM2 2–6
PWM3 2–6
,
R
R8 bit in SCCR1 11–10
RC oscillator
stabilization 9–3
RDI 2–6
RDI – receive data in 11–6
RDRF bit in SCSR 11–13
RE bit in SCCR2 11–12
real-time interrupts 5–2 14–4
example RTI periods 5–4
receiver wake-up 11–5
REFRESH 2–6
register summary 3–3 A–5
relative addressing mode 15–13
,
,
INDEX
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RESET 2–5
resets 14–1
COP 14–2
illegal address 14–1
power-on reset 14–1
RESET pin 2–5 14–1
RFQ1, RFQ0 bits in CPICSR 13–2
RIE bit in SCCR2 11–11
RT1, RT0 bits in CTCSR 5–4
RTIE bit in CTCSR 5–3
RTIF bit in CTCSR 5–3
RWU bit in SCCR2 11–12
,
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S
SBK bit in SCCR2 11–12
SC bit in SOR 2–4
SCCR1 — serial communications control register 1 11–9
CPOL – clock polarity bit 11–11
M – mode (select character format) 11–10
R8 – receive data bit 8 11–10
T8 – transmit data bit 8 11–10
WAKE – wake-up mode select bit 11–10
SCCR2 — serial communications control register 2 11–11
ILIE – idle line interrupt enable 11–11
RE – receiver enable 11–12
RIE – receiver interrupt enable 11–11
RWU – receiver wake-up 11–12
SBK – send break 11–12
TCIE – transmit complete interrupt enable 11–11
TE – transmitter enable 11–11
TIE – transmit interrupt enable 11–11
SCDR — serial communications data register 11–9
SCI
baud rate selection 11–16
block diagram 11–2
data format 11–5
receiver wake-up 11–5
start bit detection 11–7
SCK 2–6
SCP1, SCP0 bits in BAUD 11–15
SCSR — serial communications status register 11–12
FE – framing error flag 11–14
IDLE – idle line detected flag 11–13
NF – noise error flag 11–14
OR – overrun error flag 11–13
RDRF – receive data register full flag 11–13
TC – transmit complete flag 11–13
TDRE – transmit data register empty flag 11–13
SCT2, SCT1, SCT0 bits in BAUD 11–15
SOR 2–4
IRQ — interrupt sensitivity 2–4
KEYCLR — keyboard interrupt clear 2–4
KEYMUX — multiplex bit for access of interrupt flag
2–4
LVIF, LVIE, LVION — low voltage interrupt bits 2–4
PUEN — PORTC pull-up enable 2–4
SC — system clock option 2–4
SP – stack pointer 15–2
MC68HC05F32
SPCR
CPHA – clock phase 10–7
CPOL – clock polarity 10–7
DOD – direction of data 10–7
MSTR – master/slave mode select 10–7
SPE – SPI system enable 10–7
SPIE – SPI interrupt enable 10–6
SPR1, SPR0 – SPI clock select bits 10–7
SPI 10–9
block diagram 10–5
during STOP mode 10–9
during WAIT mode 10–9
features 10–1
rate selection 10–8
registers 10–6
SPI registers
SPCR — SPI control register 10–6
SPDAT — SPI data I/O register 10–9
SPSR — SPI status register 10–8
SPI signal descriptions
master in slave out (MISO) 10–2
master out slave in (MOSI) 10–2
serial clock (SCK) 10–2
slave select (SS) 10–4
SPIE 10–6
SPSR
MODF – SPI mode error interrupt status flag 10–8
SPIF – SPI interrupt request flag 10–8
WCOL – write collision 10–8
SS 2–6
STOP mode 2–1
successive approximation (SAR) - see A/D converter
SWI – see interrupts
system options register 2–4
T
T8 bit in SCCR1 11–10
TC bit in SCSR 11–13
TCAP1 2–6
TCAP1, TCAP2 bits in TSR 6–8
TCAP2 2–6
TCAP3 2–6
TCAP4 2–6
TCIE bit in SCCR2 11–11
TCMP1 2–6
TCMP2 2–6
TCR1 — timer control register 1 6–4
CO1E – compare output enable bit 1 6–5
IC1IE – input capture interrupt enable 1 6–5
IC2IE – input capture interrupt enable 2 6–5
IEDG1 – input edge bit 1 6–5
IEDG2 – input edge bit 2 6–6
OC1IE – output compare interrupt enable 1 6–5
OLVL1 – output level bit 1 6–6
TOIE – timer overflow interrupt enable 6–5
TCR2 — timer control register 2 6–4
CO2E – compare output enable bit 2 6–6
OC2IE – output compare interrupt enable 2 6–6
INDEX
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MOTOROLA
xxi
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OLVL2 – output level bit 2 6–6
TDO 2–6
SCI transmit data out 11–8
TDRE bit in SCSR 11–13
TE bit in SCCR2 11–11
thermal characteristics 16–2
TIE bit in SCCR2 11–11
timing diagrams
programmable timer 6–13
TNCR — tone control register
MS1, MS0 – melody select for operation 7–4
TGEC – tone generator enable column path 7–5
TGER – tone generator enable row path 7–5
TNOE – tone output enable 7–5
TNO, TNX pins 2–7
TNOE bit in TNCR 7–5
TOF bit in TSR 6–7
TOIE bit in TCR1 6–5
TSR — timer status register 6–7
IC1F, IC2F – input capture flags 6–7
OC1F, OC2F – output compare flags 6–7
TACP1, TCAP2 – input capture status flags 6–8
TOF – timer overflow status flag 6–7
V
VDD 2–5
VLCD 2–7
VRH 2–6
VSS 2–5
W
WAIT mode 2–2
WAKE bit in SCCR1 11–10
watchdog timer 14–2
WCOL 10–8
WCOL bit in SPSR 10–8
WTLCDO bit in LCD 8–9
X
X – index register 15–2
Z
Z-bit in CCR 15–3
MOTOROLA
xxii
INDEX
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6.
SECTION 1
INTRODUCTION
SECTION 2
MODES OF OPERATION AND PIN DESCRIPTIONS
SECTION 3
MEMORY AND REGISTERS
SECTION 4
PARALLEL INPUT/OUTPUT PORTS
SECTION 5
CORE TIMER
SECTION 6
16-BIT PROGRAMMABLE TIMER
SECTION 7
DTMF/MELODY GENERATOR
SECTION 8
LIQUID CRYSTAL DISPLAY DRIVER MODULE
SECTION 9
A/D CONVERTER
SECTION 10 SERIAL PERIPHERAL INTERFACE
SECTION 11 SERIAL COMMUNICATIONS INTERFACE
SECTION 12 PULSE WIDTH MODULATOR
SECTION 13 32 KHZ CLOCK SYSTEM
SECTION 14 RESETS AND INTERRUPTS
SECTION 15 CPU CORE AND INSTRUCTION SET
SECTION 16 ELECTRICAL SPECIFICATIONS
SECTION 17 MECHANICAL DATA
SECTION 18 ORDERING INFORMATION
SECTION 19 APPENDICES
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8.
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9.
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12. How many years have you worked with microprocessors?
Less than 1 year
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13. Currently there is some discussion in the semiconductor industry regarding a move towards providing data sheets in electronic
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05F32Book Page 1 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
PARALLEL INPUT/OUTPUT PORTS
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
CORE TIMER
16-BIT PROGRAMMABLE TIMER
DTMF/MELODY GENERATOR
LIQUID CRYSTAL DISPLAY DRIVER MODULE
A/D CONVERTER
SERIAL PERIPHERAL INTERFACE
SERIAL COMMUNICATIONS INTERFACE
PULSE WIDTH MODULATOR
32 KHZ CLOCK SYSTEM
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
MC68HC705F32
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A
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
PARALLEL INPUT/OUTPUT PORTS
CORE TIMER
16-BIT PROGRAMMABLE TIMER
DTMF/MELODY GENERATOR
LIQUID CRYSTAL DISPLAY DRIVER MODULE
A/D CONVERTER
SERIAL PERIPHERAL INTERFACE
SERIAL COMMUNICATIONS INTERFACE
PULSE WIDTH MODULATOR
32 KHZ CLOCK SYSTEM
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
ORDERING INFORMATION
MC68HC705F32
For More Information On This Product,
Go to: www.freescale.com
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177
05F32Book Page 2 Tuesday, June 8, 1999 7:55 am
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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For More Information On This Product,
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05F32Book Page 3 Tuesday, June 8, 1999 7:55 am
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How to reach us:
Mfax™: [email protected] – TOUCHTONE (602) 244-6609
INTERNET: http://www.mot.com/SPS/
USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303-675-2140
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center,
3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road,
Tai Po, N.T., Hong Kong. 852-26629298
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