FDC37M817-MS скачать даташит

FDC37M817-MS скачать даташит

FDC37M81x

PC98/99 Compliant Enhanced Super I/O

Controller with Keyboard/Mouse Wake-Up

FEATURES

5 Volt Operation

PC98, PC99 Compliant

ISA Plug-and-Play Compatible Register Set

Intelligent Auto Power Management

- Shadowed Write-Only Registers

Floppy Disk Available on Parallel Port Pins

Enhanced Digital Data Separator

- 2 Mbps, 1 Mbps, 500 Kbps, 300

Kbps, 250 Kbps Data Rates

- Programmable Precompensation

- Programmable Wake-up Event

Modes

Interface

System Management Interrupt, Watchdog

Timer

2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk

Controller

- Software and Register Compatible with SMSC's Proprietary 82077AA

- 8042 Software Compatible

- 8 Bit Microcomputer

- 2k Bytes of Program ROM

- 256 Bytes of Data RAM

- Four Open Drain Outputs Dedicated

- Asynchronous Access to Two Data

- Supports One Floppy Drive

- Configurable Open Drain/Push-Pull

- Supports Interrupt and Polling Access

- 8 Bit Counter Timer

- Port 92 Support

- Fast Gate A20 and KRESET Outputs

- 8042 P12, P16 and P17 Outputs

- Supports Vertical Recording Format

- 16-Byte Data FIFO

- 100% IBM Compatibility

- Detects All Overrun and Underrun

Conditions

- Sophisticated Power Control Circuitry

(PCC) Including Multiple Powerdown

Modes for Reduced Power

Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- 480 Address, Up to 15 IRQ and

- Two Full Function Serial Ports

- High Speed NS16C550A Compatible

UARTs with Send/Receive 16-Byte

FIFOs

- Supports 230k and 460k Baud

Programmable Baud Rate Generator

- 480 Address and 15 IRQ Options

- IrDA 1.0, HP-SIR, ASK IR Support

Multi-Mode Parallel Port with ChiProtect

- Standard Mode IBM PC/XT PC/AT,

and PS/2 Compatible Bidirectional

Parallel Port

- Enhanced Parallel Port (EPP)

Compatible - EPP 1.7 and EPP 1.9

- IEEE 1284 Compliant Enhanced

- 480 Address, Up to 15 IRQ and

Three DMA Options

ISA Host Interface

- 16 Bit Address Qualification

- 8 Bit Data Bus

- IOCHRDY for ECP and IrCC

- Three 8 Bit DMA Channels

- Serial IRQ Interface Compatible with

Serialized IRQ Support for PCI Systems

- ChiProtect Circuitry for Protection

Against Damage Due to Printer Power-

On

100 Pin QFP Lead-free RoHS Compliant

Package

Order Number: FDC37M817-MS for 100 pin, QFP Lead-free RoHS Compliant Package

GENERAL DESCRIPTION

The FDC37M81x* with IrDA v1.0 support The FDC37M81x supports the ISA Plug-and-Play incorporates a keyboard interface, SMSC's true

CMOS 765B floppy disk controller, advanced digital data separator, two 16C550A compatible

UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, on-chip 12 mA AT bus drivers, one floppy direct drive support, and Intelligent Power Management including PME support. The true CMOS 765B

Standard (Version 1.0a) and provides the recommended functionality to support Windows

'95/’98. The I/O Address, DMA Channel and hardware IRQ of each logical device in the

FDC37M81x may be reprogrammed through the internal configuration registers. There are 480

I/O address location options, a Serialized IRQ interface, and three DMA channels. core provides 100% compatibility with IBM

PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection.

The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use.

Both on-chip UARTs are compatible with the

The FDC37M81x does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The FDC37M81x is software and register compatible with SMSC's proprietary 82077AA core.

NS16C550A. The parallel port is compatible with

IBM PC/AT architecture, as well as IEEE 1284

EPP and ECP. The FDC37M81x incorporates sophisticated power control circuitry (PCC) which includes support for keyboard, mouse, and modem ring wake-up events. The PCC supports multiple low power-down modes.

*The “x” in the part number is a designator that changes depending upon the particular BIOS used inside the specific chip. “2” denotes AMI Keyboard BIOS and “7” denotes Phoenix 42i Keyboard BIOS.

2

TABLE OF CONTENTS

FEATURES.............................................................................................................................................. 1

GENERAL DESCRIPTION ...................................................................................................................... 2

PIN CONFIGURATION............................................................................................................................ 5

DESCRIPTION OF PIN FUNCTIONS ..................................................................................................... 6

Buffer Type Descriptions ..................................................................................................................... 9

Description of Multifunction Pins ........................................................................................................10

REFERENCE DOCUMENTS..................................................................................................................10

POWER FUNCTIONALITY ....................................................................................................................12

VCC Power ........................................................................................................................................12

VTR Support ......................................................................................................................................12

Internal PWRGOOD...........................................................................................................................12

Trickle Power Functionality ................................................................................................................13

Maximum Current Values...................................................................................................................13

Power Management Events (PME/SCI) .............................................................................................13

FUNCTIONAL DESCRIPTION ...............................................................................................................14

Super I/O Registers............................................................................................................................14

Host Processor Interface....................................................................................................................14

FLOPPY DISK CONTROLLER ..............................................................................................................15

FDC Internal Registers.......................................................................................................................15

Command Set/Descriptions................................................................................................................38

Instruction Set ....................................................................................................................................41

SERIAL PORT (UART)...........................................................................................................................68

INFRARED INTERFACE ........................................................................................................................82

PARALLEL PORT ..................................................................................................................................83

IBM XT/AT Compatible, Bi-Directional And Epp Modes .......................................................................85

Extended Capabilities Parallel Port......................................................................................................91

PARALLEL PORT FLOPPY DISK CONTROLLER .............................................................................104

POWER MANAGEMENT .....................................................................................................................106

SERIAL IRQ .........................................................................................................................................112

GP INDEX REGISTERS .......................................................................................................................116

WATCH DOG TIMER ...........................................................................................................................118

8042 KEYBOARD CONTROLLER DESCRIPTION .............................................................................119

Latches On Keyboard And Mouse IRQs ..........................................................................................128

Keyboard and Mouse PME Generation............................................................................................129

3

SYSTEM MANAGEMENT INTERRUPT (SMI) .....................................................................................131

PME SUPPORT....................................................................................................................................132

CONFIGURATION................................................................................................................................133

OPERATIONAL DESCRIPTION ..........................................................................................................164

Maximum Guaranteed Ratings.........................................................................................................164

DC Electrical Characteristics............................................................................................................164

TIMING DIAGRAMS .............................................................................................................................169

4

PIN CONFIGURATION

DRVDEN0

DRVDEN1 nMTR0 nIO_PME nDS0

P17

VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWPRT nRDATA nDSKCHG

VTR

CLOCKI nCS/SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

18

19

20

21

22

23

12

13

14

15

16

17

24

25

26

27

28

29

30

6

7

8

9

10

11

3

4

5

1

2

FDC37M81x

100 PIN QFP

PE

SLCT nERROR nACK

VSS

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7 nINIT nSLCTIN

VCC

KBRST

A20M

IRTX2

IRRX2

VSS

KDAT

KCLK

MDAT

MCLK

IOCHRDY

TC

VCC

DRQ3/P12 nDACK3/P16

54

53

52

51

58

57

56

55

64

63

62

61

60

59

74

73

72

71

70

69

68

67

66

65

80

79

78

77

76

75

5

PIN

No./QFP NAME

DESCRIPTION OF PIN FUNCTIONS

TOTAL SYMBOL

PROCESSOR/HOST INTERFACE (36)

8 SD[0:7] 45:42,

40:37

System Data Bus

31:21 11-bit System Address Bus 11 SA[0:10]

20

55

46

32

48

50

52

47

49

51

4

6

19

62

53,65,

93

Chip Select/SA11 (Note 2)

I/O Channel Ready

ISA Reset Drive

1 nCS/SA11

1 AEN

1 IOCHRDY

1 RESET_DR

V

1 SER_IRQ

1 PCI_CLK PCI Clock for Serial IRQ

(33MHz/30MHz)

DMA Request 1

DMA Request 2

DMA Request 3/8042 P12

DMA Acknowledge 1

DMA Acknowledge 2

DMA Acknowledge 3/8042 P16

Power Management Event

8042 - P17 (Note 5)

1

1

DRQ1

DRQ2

1 DRQ3/P12

1

1

1 nDACK1 nDACK2 nDACK3/

P16

1 TC

1 nIOR

1 nIOW

1 nIO_PME

1 P17

14.318MHz Clock Input

CLOCKS (1)

1 CLOCKI

Infrared Tx (Note 4)

+5 Volt Supply Voltage

INFRARED INTERFACE (2)

1 IRRX

1

POWER PINS (8)

IRTX

VCC

BUFFER TYPE

PER FUNCTION

(NOTE 1)

IO12

I

I/I

I

OD12

IS

IO12

ICLK

O12

O12

O12/IO12

I

I

I/IO12

I

I

I

OD24

IO8

ICLK

I

O24PD

6

PIN

No./QFP

7,41,

60,76

18

16

11

10

5

3

NAME

DESCRIPTION OF PIN FUNCTIONS

TOTAL SYMBOL

+5 Volt Standby Supply Voltage

(Note 7)

Read Disk Data

Write Gate

Write Disk Data

Drive Select 0

Motor On 0

VTR

FDD INTERFACE (14)

1 nRDATA

1

1 nWGATE nWDATA

1 nHDSEL

1 nDIR

1 nSTEP

1 nDSKCHG

1

1 nDS0 nMTR0

1 nWRTPRT

1 nTRKO

13

1

2

84

85

87

88

89

86

91

90

95

96

98

BUFFER TYPE

PER FUNCTION

(NOTE 1)

IS

(O24/OD24)

(O24/OD24)

(O24/OD24)

(O24/OD24)

(O24/OD24)

IS

(O24/OD24)

(O24/OD24)

IS

IS

Drive Density Select 0

Drive Density Select 1

1

1

DRVDEN0

DRVDEN1

SERIAL PORT 1 INTERFACE (8)

Receive Serial Data 1 1 RXD1

Transmit Serial Data 1

Request to Send 1/System

Option (Note 6)

1 TXD1

1 nRTS1/

SYSOPT

(O24/OD24)

(O24/OD24)

I

O4

O4/I

Clear to Send 1

Data Terminal Ready 1

Data Set Ready 1

Data Carrier Detect 1

Ring Indicator 1

1

1

1

1

1 nCTS1 nDTR1 nDSR1 nDCD1 nRI1

SERIAL PORT 2 INTERFACE (8)

Receive Serial Data 2/Infrared

Rx

Transmit Serial Data 2/Infrared

Tx (Note 4)

Request to Send 2/Sys Addr 12

1 RXD2/IRRX

1 TXD2/IRTX

1 nRTS2/

SA12

I

O4

I

I

I

I/I

O24PD/

O4/I

7

PIN

No./QFP

99

DESCRIPTION OF PIN FUNCTIONS

NAME

Clear to Send 2/Sys Addr 13

TOTAL

1

SA13

SYMBOL

nCTS2/

BUFFER TYPE

PER FUNCTION

(NOTE 1)

I/I

100

97

Data Terminal Ready/Sys Addr

14

Data Set Ready 2/Sys Addr 15

1 nDTR2/

SA14

1 nDSR2/

SA15

94

92

Data Carrier Detect 2/8042 P12

Ring Indicator 2/8042 P16

1

1 nDCD2/P12 nRI2/P16

PARALLEL PORT INTERFACE (17)

75:68 Parallel Port Data Bus 8 PD[0:7]

O4/I

I/I

I/IO24

I/IO24

83 Auto Line Feed

1 nSLCTIN

1 nINIT

1 nALF

1 nSTROBE

IO24

OD24/O24

OD24/O24

OD24/O24

OD24/O24

1 BUSY

1 nACK

1 PE

1 SLCT

I

I

I

I

I 78 Error at Printer 1 nERROR

KEYBOARD/MOUSE INTERFACE (6)

1 KDAT

1 KCLK

1 MDAT

1 MCLK

IOD16

IOD16

IOD16

IOD16

1 KBDRST

(Note 3)

O4

1 A20M O4

Note: The "n" as the first letter of a signal name indicates an "Active Low" signal.

Note 1: Buffered types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis represent multiple buffer types for a single pin function.

Note 2: For 12 bit addressing, SA0:SA11 only, nCS should be tied to GND. For 16 bit external address qualification, address bits SA11:SA15 can be "ORed" together and applied to nCS. The nCS pin functions as SA11 in full 16 bit Internal Address Qualification Mode. CR24.6 controls the

FDC37M81x addressing modes.

Note 3: KBDRST is active low.

Note 4: The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of internal PWRGOOD.

8

Note 5: Requires external pull-up resistor.

Note 6: When SYSOPT function is used on nRTS1/SYSOPT pin, an external pulldown register is required to put the base I/O address for configuration at 0x3F0. An external pullup resistor is required to move the base I/O address for configuration to 0x370.

Note 7: VTR can be connected to VCC if no wakeup functionality is required.

Buffer Type Descriptions

I

IS

IOD16

IO24

IO4

O4

O24

OD24

IO8

Input, TTL compatible

Input with Schmitt trigger

Input/Output, 16mA sink

Input/Output, 24mA sink, 12mA source

Input/Output, 4mA sink, 2mA source

Output, 4mA sink, 2mA source

Output, 24mA sink, 12mA source

Output, Open Drain, 24mA sink

Input/Output, 8mA sink, 4mA source

ICLK

IO12

O12

OD12

O24PD

Input/Output, 12mA sink, 6mA source

Output, 12mA sink, 6mA source

Output, Open Drain, 12 mA sink

Output, 12mA sink, 6mA source with 30

μA pull-down

9

Description of Multifunction Pins

PIN

NO./QFP

51

52

92

94

95

ORIGINAL

FUNCTION

ALTERNATE

FUNCTION 1 DEFAULT NOTE

nDACK3 8042 nDACK3 1

DRQ3 8042 1 nRI2 8042 2 nDCD2 8042 nDCD2 2

96

97

98

99

100

RXD2 IRRX

TXD2 IRTX nDSR2 SA15 nRTS2 SA12 nCTS2 SA13 nDTR2 SA14

RXD2 3

TXD2 3 nDSR2 4 nRTS2 4 nCTS2 4 nDTR2 4

Note 1: Controlled by DMA3SEL(LD8:CRC0.1)

Note 2: Controlled by 8042COMSEL(LD8:CRC0.3)

Note 3: Controlled by IR Option Register( LD5:CRF1.6)

Note 4: Controlled by 16 bit Address Qualification (CR24.6)

For more information, refer to tables 63 through 73.

REFERENCE DOCUMENTS

1. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.

2. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.

3. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997.

10

SER_IRQ

PCI_CLK nIOR nIOW

AEN

SA[0:12] (nCS)

*

SA[13-15]

*

SD[O:7]

DRQ[1:3]

* nDACK[1:3]

*

TC

RESET_DRV

IOCHRDY nPME

SERIAL

IRQ

HOST

CPU

INTERFACE

V

TR

Vcc Vss

SMI PME WDT

DATA BUS

ADDRESS BUS

CONFIGURATION

REGISTERS

CONTROL BUS

MULTI-MODE

PARALLEL

PORT/FDC

MUX

16C550

COMPATIBLE

SERIAL

PORT 1

PD0-7

BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, nINIT, nALF

TXD1, nCTS1, nRTS1

RXD1 nDSR1, nDCD1, nRI1, nDTR1

CLOCK

WDATA

WCLOCK

SMSC

PROPRIETARY

82077

COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER

CORE

RCLOCK

RDATA

DIGITAL

DATA

SEPARATOR

WITH WRITE

PRECOM-

PENSATION

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

8042

GEN

CLOCKI

14MHz nINDEX nTRK0 nDSKCHG

DENSEL nDIR nSTEP nDS0 nMTR0

DRVDEN0 nWDATA nRDATA nWRPRT nWGATE nHDSEL

DRVDEN1 *

*

Denotes Multifunction Pins

FIGURE 1 - FDC37M81x BLOCK DIAGRAM

IRRX, IRTX

RXD2(IRRX) * nDSR2, nDCD2, nRI2, nDTR2

*

KCLK

KDATA

MCLK

MDATA

GATEA20, KRESET

P12

*

, P16

*

11

POWER FUNCTIONALITY

The FDC37M81x has two power planes: VCC and VTR.

VCC Power

must be at its full minimum potential at least 10

μs before V cc

begins a power-on cycle. When

V

TR

and V cc

are fully powered, the potential difference between the two supplies must not

The FDC37M81x is a 5 Volt part. The VCC supply is 5 Volts (nominal). See the Operational exceed 500mV.

Internal PWRGOOD

Description sections and the Maximum Current

Values subsection.

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in

V

TR

SUPPORT

The FDC37M81x requires a 25 mA max trickle the host interface as V cc

cycles on and off.

When the internal PWRGOOD signal is “1” supply (V

TR

) to provide sleep current for the programmable wake-up events in the PME interface when V

CC

is removed. If the

FDC37M81x is not intended to provide wake-up capabilities on standby current, V

TR

can be connected to V

CC

. V

TR

powers the PME configuration registers, and the PME interface.

The V

TR

pin generates a V

TR

Power-on-Reset signal to initialize these components.

(active), V cc

is > 3.7V, and the FDC37M81x host interface is active. When the internal

PWRGOOD signal is “0” (inactive), V cc

is

≤ 3.7V, and the FDC37M81x host interface is inactive; that is, ISA bus reads and writes will not be decoded.

The FDC37M81x device pins nIO_PME, KDAT,

MDAT, IRRX, nRI1, nRI2 and RXD2 are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive,

Note: If V

TR

is to be used for programmable wake-up events when V

CC

is removed, V

TR provided V

TR

is powered.

FDC37M81x PLL CONTROLS AND SELECTS

PLL

CONTROL

(CR24.1)

1

PME POWER

(CR22.7)

X

INTERNAL

PWRGOOD

X

DESCRIPTION

14 MHz PLL Powered Down

0 0 1 14MHz PLL Powered, Selected.

12

Trickle Power Functionality

When the FDC37M81x is running under VTR only, the PME wakeup events are active and (if enabled) able to assert and nIO_PME pin active low. The following lists the wakeup events.

UART1 Ring Indicator

UART2 Ring Indicator data

Maximum Current Values

Refer to the “Operational Description” section for the maximum current values.

The maximum VTR current, I

TR

, is given with all outputs open. The total maximum current for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by VTR.

The maximum VCC current, I

CC

, is given with all outputs open (not loaded).

Power Management Events (PME/SCI)

The FDC37M81x offers support for Power

Management Events (PMEs), also referred to as

System Control Interrupts (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 4.

See the “PME Support” section.

13

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

The address map, shown below in Table 1, shows

HOST PROCESSOR INTERFACE

The host processor communicates with the the addresses of the different blocks of the Super

I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via the configuration registers. Some

FDC37M81x through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA addresses are used to access more than one register. transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA.

Table 1 - Super I/O Block Addresses

ADDRESS BLOCK NAME

LOGICAL

DEVICE NOTES

Base+(0-5) and +(7) Floppy Disk 0

Base+(0-7)

Base1+(0-7)

Base+(0-3)

Base+(0-7)

Base+(0-3), +(400-402)

Base+(0-7), +(400-402)

60, 64

Serial Port Com 1

Serial Port Com 2

Parallel Port

SPP

EPP

ECP

ECP+EPP+SPP

KYBD

4

5 IrDA 1.0

3

7

Note 1: Refer to the configuration register descriptions for setting the base address

14

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drive. The FDC integrates the functions of the Formatter/Controller, Digital Data

Separator, Write Precompensation and Data Rate

Selection logic for an IBM XT/AT compatible FDC.

The true CMOS 765B core guarantees 100% IBM

FDC INTERNAL REGISTERS

The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table

2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC is compatible to the 82077AA using

SMSC's proprietary floppy disk controller core.

Table 2 - Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

SECONDARY

ADDRESS R/W REGISTER

3F0

3F1

3F2

3F3

3F4

3F4

3F5

3F6

3F7

3F7

370

371

372

373

374

374

375

376

377

377

R

R

R/W

R/W

R

W

R/W

R

W

Status Register A (SRA)

Status Register B (SRB)

Digital Output Register (DOR)

Tape Drive Register (TDR)

Main Status Register (MSR)

Data Rate Select Register (DSR)

Data (FIFO)

Reserved

Digital Input Register (DIR)

Configuration Control Register (CCR)

15

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the

PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

7 6 5 4 3 2 1 0

INT STEP nTRK0 HDSEL nINDX nWP DIR

PENDING

RESET

COND.

0 1 0 N/A 0 N/A

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected.

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

This function is not supported. This bit is always read as ‘1’.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy

Disk Interrupt output.

16

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

PENDING

DRQ STEP TRK0 nHDSEL INDX WP nDIR

F/F

RESET

COND.

BIT 0 nDIRECTION

Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 nHEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the

STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DRQ output pin.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy

Disk Interrupt output.

17

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 andModel 30 modes.

The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7 6 5 4 3 2 1 0

RESET

COND.

SEL0 TOGGLE

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

1 1 0 0 0 0 0 0

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Note: In the

FDC37M81x only one drive is available at the FDD interface.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the

DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

18

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

F/F F/F

WGATE

F/F nDS3 nDS2

RESET

COND.

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported in the

FDC37M81x.

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported in the

FDC37M81x.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the

DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the

DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input.

Note: This function is not supported in the

FDC37M81x.

19

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

7 6 5 4 3 2 1 0

RESET

COND.

EN3 EN2

MOT

EN1

MOT

EN0

DMAEN nRESE

T

DRIVE

SEL1

DRIVE

SEL0

0 0 0 0 0 0 0 0

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic

"1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode:

Writing this bit to logic "1" will enable the DRQ, nDACK, TC pins and interrupt functions. This bit being a logic "0" will disable the nDACK, TC inputs and interrupt functions, and hold the DRQ output in a high impedance state. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DRQ, nDACK, TC pins and interrupt functions are always enabled.

During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 6 MOTOR ENABLE 2

The MTR2 disk interface output is not supported in the FDC37M81x.

BIT 7 MOTOR ENABLE 3

The MTR3 disk interface output is not supported in the FDC37M81x.

Table 3 - Drive Activation Values

DRIVE

0

1

DOR VALUE

1CH

2DH

20

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

The Tape Drive Register (TDR) is included for

82077 software compatibility and allows the user to assign tape support to a particular drive during that drive automatically invokes tape support. The

TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 4 illustrates the Tape

Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. initialization. Any future references to

Table 4 - Tape Select Bits

TAPE SEL1

(TDR.1)

TAPE SEL0

(TDR.0)

DRIVE

SELECTED

0

0

1

1

0

1

0

1

None

1

2

3

REGISTER

Table 5 - Internal 2 Drive Decode - Normal

DIGITAL OUTPUT DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 5 Bit 4 Bit1 Bit 0

X 1 0 0 nDS1

1 nDS0

0 nMTR1 nBIT 5 nMTR0 nBIT 4

1

0

X

0

0

X

1

X

0

1

1

1 nBIT 5 nBIT 5 nBIT 4 nBIT 4

Table 6 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT

REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 5 Bit 4 Bit1 Bit 0

X 1 0 0 nDS1

0 nDS0

1 nMTR1 nBIT 4 nMTR0 nBIT 5

1

0

X

0

0

X

1

X

1

1

0

1 nBIT 4 nBIT 4 nBIT 5 nBIT 5

21

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Enhanced Floppy Mode 2 (OS2)

Register 3F3 for Enhanced Floppy Mode 2 operation.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Reserved Reserved Drive Type ID

DIGITAL OUTPUT REGISTER

Floppy Boot Drive

Table 7 - Drive Type ID tape sel1 tape sel0

REGISTER 3F3 - DRIVE TYPE ID

Bit 1

0

0

1

1

Bit 0

0

1

0

1

Bit 5

L0-CRF2 - B1

L0-CRF2 - B3

L0-CRF2 - B5

L0-CRF2 - B7

Bit 4

L0-CRF2 - B0

L0-CRF2 - B2

L0-CRF2 - B4

L0-CRF2 - B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

22

DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration

Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30.

Other applications can set the data rate in the

DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The

DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.

7 6 5 4 3 2 1 0

RESET

COND.

RESET DOWN

0 PRE-

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

0 0 0 0 0 0 1 0

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 9 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 through 4 PRECOMPENSATION

SELECT

These three bits select the value of write precompensation that will be applied to the

WDATA output signal. Table 11 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data mode after a software reset or access to the Data Register or

Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the

DOR RESET (DOR bit 2) except that this bit is self clearing.

Note: The DSR is Shadowed in the Floppy Data

Rate Select Shadow Register, LD8:CRC2[7:0]. separator circuits will be turned off. The controller will come out of manual low power.

23

Table 8 - Precompensation Delays

PRECOMP

432

PRECOMPENSATION

DELAY (nsec)

111

001

010

011

100

101

110

000

0.00

41.67

83.34

125.00

166.67

208.33

250.00

Default

0

20.8

41.7

62.5

83.3

104.2

125

Default

Default: See Table 12

*2Mbps data rate is only available if V

CC

= 5V.

24

DRIVE RATE

Table 9 - Data Rates

DATA RATE DATA RATE

DRT1 DRT0 SEL1 SEL0 MFM FM

DENSEL

DRATE(1)

1 0

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format

= Drive

Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.

Table 10 - DRVDEN Mapping

DT1 DT0 DRVDEN1 (1) DRVDEN0 (1) DRIVE TYPE

0 0 DRATE0 DENSEL 4/2/1 MB 3.5"

2/1 MB 5.25" FDDS

2/1.6/1 MB 3.5" (3-MODE)

1 0 DRATE0 DRATE1

0 1 DRATE0 nDENSEL

1 1 DRATE1 DRATE0

25

Table 11 - Default Precompensation Delays

*The 2Mbps data rate

DATA RATE

2 Mbps*

1 Mbps

500 Kbps

300 Kbps

250 Kbps

PRECOMPENSATION

DELAYS

20.8 ns

41.67 ns

125 ns

125 ns

125 ns is only available if V

CC

=

MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register and indicates the status of the disk controller. The

Main Status Register can be read at any

5V. time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer.

7 6 5 4 3 2 1 0

RQM DIO

NON

DMA

CMD

BUSY

Reserved Reserved

DRV1

BUSY

DRV0

BUSY

BIT 0 - 1 DRV x BUSY

These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates.

BIT 4 COMMAND BUSY

This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte.

BIT 5 NON-DMA

This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes.

BIT 6 DIO

Indicates the direction of a data transfer once a

RQM is set. A 1 indicates a read and a 0 indicates a write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to a

1. No access is permitted if set to a 0.

26

DATA REGISTER (FIFO)

aFIFO. The data is based upon the following formula:

Address 3F5 READ/WRITE

All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register.

Threshold # x 1

DATA RATE x 8 - 1.5

μs = DELAY

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings.

As the command execution phase is entered, the

The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be

FIFO is cleared of any data to ensure that invalid data is not transferred. changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error.

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to

Table 14 gives several examples of the delays with remove the remaining data so that the result phase may be entered.

Table 12 - FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT 2

Mbps* DATA RATE

1 x 4

μs - 1.5 μs = 2.5 μs

2 x 4

μs - 1.5 μs = 6.5 μs

8 x 4

μs - 1.5 μs = 30.5 μs

15 x 4

μs - 1.5 μs = 58.5 μs

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT 1

Mbps DATA RATE

1 x 8

μs - 1.5 μs = 6.5 μs

2 x 8

μs - 1.5 μs = 14.5 μs

8 x 8

μs - 1.5 μs = 62.5 μs

15 x 8

μs - 1.5 μs = 118.5 μs

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 x 16

μs - 1.5 μs = 14.5 μs

2 x 16

μs - 1.5 μs = 30.5 μs

8 x 16

μs - 1.5 μs = 126.5 μs

15 x 16

μs - 1.5 μs = 238.5 μs

*The 2 Mbps data rate is only available if V

CC

= 5V.

27

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC-AT Mode

7 6 5 4 3 2 1 0

RESET

COND.

CHG state

Tristate

Tristate

Tristate

Tristate

Tristate

Tristate

N/A N/A N/A N/A N/A N/A N/A N/A

BIT 0 - 6 UNDEFINED

The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register.

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk

Change Register (see Configuration Register

LD8:CRC1[1:0]).

PS/2 Mode

7 6 5 4 3 2 1 0

RESET

COND.

CHG SEL1 SEL0 nHIGH nDENS

N/A N/A N/A N/A N/A N/A N/A 1

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected.

BITS 1 - 2 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BITS 3 - 6 UNDEFINED

Always read as a logic "1"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk

Change Register (see Configuration Register

LD8:CRC1[1:0]).

28

Model 30 Mode

7 6 5 4 3 2 1 0

CHG SEL1 SEL0

RESET

COND.

BITS 0 - 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 NOPREC

This bit reflects the value of NOPREC bit set in the

CCR register.

BIT 3 DMAEN

This bit reflects the value of DMAEN bit set in the

DOR register bit 3.

BITS 4 - 6 UNDEFINED

Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk

Change Register (see Configuration Register

LD8:CRC1[1:0]).

29

CONFIGURATION CONTROL REGISTER (CCR)

Address 3F7 WRITE ONLY

PC/AT and PS/2 Modes

7 6 5 4 3 2 1 0

RESET

COND.

SEL1 SEL0

N/A N/A N/A N/A N/A N/A 1 0

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values.

PS/2 Model 30 Mode

BIT 2 - 7 RESERVED

Should be set to a logical "0"

7 6 5 4 3 2 1 0

RESET

COND.

SEL1 SEL0

N/A N/A N/A N/A N/A N/A 1 0

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values.

BIT 2 NO PRECOMPENSATION

This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset.

BIT 3 - 7 RESERVED

Should be set to a logical "0"

Table 12 shows the state of the DENSEL pin. The

DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets.

30

STATUS REGISTER ENCODING

During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed.

Table 13 - Status Register 0

BIT NO. SYMBOL NAME DESCRIPTION

7,6 IC Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error.

01 - Abnormal termination of command. Command execution was started, but was not successfully completed.

10 - Invalid command. The requested command could not be executed.

11 - Abnormal termination caused by Polling.

5 SE The FDC completed a Seek, Relative Seek or

Recalibrate command (used during a Sense Interrupt

Command).

4 EC Equipment

Check 1. 80 step pulses in the Recalibrate command.

2. The Relative Seek command caused the FDC to step outward beyond Track 0.

3

2 H

Unused. This bit is always "0".

Head Address The current head address.

31

Table 14 - Status Register 1

NAME DESCRIPTION BIT NO. SYMBOL

7 EN End

Cylinder

The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after

Read or Write Data command.

6

5 DE Data Error

Unused. This bit is always "0".

The FDC detected a CRC error in either the ID field or the data field of a sector.

4 OR Overrun/

Underrun service within the required time interval, resulting in data overrun or underrun.

3

2 ND No Data

Unused. This bit is always "0".

Any one of the following:

1. Read Data, Read Deleted Data command - the FDC did not find the specified sector.

2. Read ID command - the FDC cannot read the ID field without an error.

3. Read A Track command - the FDC cannot find the proper sector sequence.

1 NW Not Writeable WP pin became a "1" while the FDC is executing a Write

Data, Write Deleted Data, or Format A Track command.

0 MA Missing Any one of the following:

Address Mark 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the nINDEX pin twice.

2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track.

32

BIT NO.

7

SYMBOL

Table 15 - Status Register 2

NAME DESCRIPTION

Unused. This bit is always "0".

6

5

CM

DD

Control Mark Any one of the following:

1. Read Data command - the FDC encountered a deleted data address mark.

2. Read Deleted Data command - the FDC encountered a data address mark.

Data Error in

Data Field

The FDC detected a CRC error in the data field.

4 WC Wrong

Cylinder

The track address from the sector ID field is different from the track address maintained inside the FDC.

3 Unused. This bit is always "0".

2

1 BC

Unused. This bit is always "0".

Bad Cylinder The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format.

0 MD Missing The FDC cannot detect a data address mark or a deleted

Address Mark data address mark.

33

Table 16- Status Register 3

NAME DESCRIPTION BIT NO.

7

SYMBOL

6 WP Write

Protected

5

4 T0 Track 0

Unused. This bit is always "0".

Indicates the status of the WP pin.

Unused. This bit is always "1".

Indicates the status of the TRK0 pin.

3

2 HD

Unused. This bit is always "1".

Head Address Indicates the status of the HDSEL pin.

1,0 DS1,0 Drive Select Indicates the status of the DS1, DS0 pins.

RESET

There are three sources of system reset on the

FDC: the RESET_DRV pin of the FDC, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a

Power On Reset initializes the FDC. All resets take the FDC out of the power down state.

All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC.

On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.

RESET_DRV Pin (Hardware Reset)

The RESET_DRV pin is a global reset and clears all registers except those programmed by the

Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state.

DOR Reset vs. DSR Reset (Software Reset)

These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state.

MODES OF OPERATION

The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the Interface Mode bits in LD0-CRF0[3:2].

PC/AT mode

The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and TC and

DENSEL become active high signals.

34

PS/2 mode

This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the

DOR becomes a "don't care", (interrupt functions and DRQ are always enabled), TC and DENSEL become active low.

Model 30 mode

This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes (controls the interrupt and DMA functions), TC is active high and DENSEL is active low.

DMA TRANSFERS

DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid.

Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by the FDC based only on nDACK. This mode is only available when the

FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no

DMA operation is needed.

The FDC37M81x supports two DMA transfer modes for the FDC: Single Transfer and Burst

Transfer. In the case of the single transfer, the

DMA Req goes active at the start of the DMA cycle, and the DMA Req is deasserted after the nDACK. In the case of the burst transfer, the Req is held active until the last transfer (independent of nDACK). See timing diagrams for more information.

Burst mode is enabled via Bit[1] of CRF0 in

Logical Device 0. Setting Bit[1]=0 enables burst mode; the default is Bit[1]=1, for non-burst mode.

CONTROLLER PHASES

35

For simplicity, command handling in the FDC can be divided into three phases: Command,

Execution, and Result. Each phase is described in the following sections.

Command Phase

After a reset, the FDC enters the command phase and is ready to accept a command from the host.

For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 19 for the command set descriptions). These bytes of data must be transferred in the order prescribed.

Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register.

RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed.

The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition.

The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid

Command" condition.

Execution Phase

All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command.

After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or FDRQ depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value.

The following paragraphs detail the operation of the FIFO flow control. In these descriptions,

<threshold> is defined as the number of bytes available to the FDC when service is requested

from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.

A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system.

A high value of threshold (i.e. 12) is used with a

"sluggish" system by affording a long latency period after a service request, but results in more frequent service requests.

Non-DMA Mode - Transfers from the FIFO to the

Host

The interrupt and RQM bits in the Main Status

Register are activated when the FIFO contains

(16-<threshold>) bytes or the last bytes of a full sector have been placed in the FIFO. The interrupt can be used for interrupt-driven systems, and RQM can be used for polled systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the interrupt and RQM bit when the

FIFO becomes empty.

Non-DMA Mode - Transfers from the Host to the

FIFO

The interrupt and RQM bit in the Main Status

Register are activated upon entering the execution phase of data transfer commands. The host must respond to the request by writing data into the

FIFO. The interrupt and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has <threshold> bytes remaining in the FIFO. The interrupt will also be deactivated if

TC and nDACK both go inactive. The FDC enters the result phase after the last byte is taken by the

FDC from the FIFO (i.e. FIFO empty condition).

DMA Mode - Transfers from the FIFO to the Host

36

The FDC activates the DDRQ pin when the FIFO contains (16 - <threshold>) bytes, or the last byte of a full sector transfer has been placed in the

FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DDRQ pin when the FIFO becomes empty. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nDACK). A data underrun may occur if FDRQ is not removed in time to prevent an unwanted cycle.

DMA Mode - Transfers from the Host to the FIFO.

The FDC activates the FDRQ pin when entering the execution phase of the data transfer commands. The DMA controller must respond by activating the nDACK and nIOW pins and placing data in the FIFO. FDRQ remains active until the

FIFO becomes full. FDRQ is again set true when the FIFO has <threshold> bytes remaining in the

FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more data is required. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOW of the last byte, if no edge is present on nDACK). A data overrun may occur if FDRQ is not removed in time to prevent an unwanted cycle.

Data Transfer Termination

The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer.

If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete

the sector as if a hardware TC was received.

The only difference between these implicit functions and TC is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected.

Note that when the host is sending data to the

FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.

Result Phase

The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start.

RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to

"1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command.

37

COMMAND SET/DESCRIPTIONS

Commands can be written whenever the FDC is in interrupt is issued. The user sends a Sense the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an

Interrupt Status command which returns an invalid command error. Refer to Table 17 for explanations of the various symbols used. Table

18 lists the required parameters and the results associated with each command that the FDC is capable of performing.

Table 17 - Description of Command Symbols

SYMBOL NAME DESCRIPTION

D

D0, D1

Address

Data Pattern The pattern to be written in each sector data field during formatting.

Drive Select 0-

1

Designates which drives are perpendicular drives on the Perpendicular

Mode Command. A "1" indicates a perpendicular drive.

Control

DS0, DS1 Disk Drive

Select relative seek. If set to a 1, the head will step in toward the spindle.

DS1 DS0

0 1 Drive 1 (not implemented)

EC

Size bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX.

Enable Count When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track).

EFIFO Enable FIFO This active low bit when a 0, enables the FIFO. A "1" disables the

FIFO (default).

EIS Enable When set, a seek operation will be performed before executing any

Seek read or write command that requires the C parameter in the command phase. A "0" disables the implied seek.

EOT

GAP

GPL

H/HDS

End of Track The final sector number of the current track.

Alters Gap 2 length when using Perpendicular Mode.

Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the

VCO synchronization field).

Head Address Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field.

38

NAME

Table 17 - Description of Command Symbols

DESCRIPTION SYMBOL

Time initializing a read or write operation. Refer to the Specify command for actual delays.

LOCK

Time command) until the head is unloaded. Refer to the Specify command for actual delays.

Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a

"software Reset". (A reset caused by writing to the appropriate bits of either tha DSR or DOR)

MFM MFM/FM A one selects the double density (MFM) mode. A zero selects single

Selector density (FM) mode.

Selector

Code mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1.

With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive.

OW

Number

Mode Flag

Overwrite mode. In this mode, the host is interrupted for each data transfer.

When set to 0, the FDC operates in DMA mode, interfacing to a DMA controller by means of the DRQ and nDACK signals.

The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command.

39

Table 17 - Description of Command Symbols

SYMBOL NAME DESCRIPTION

PCN Present The current position of the head at the completion of Sense Interrupt

Cylinder

Number

Status command.

POLL Polling Disable When set, the internal polling routine is disabled. When clear, polling is enabled.

PRETRK Precompensati on Start Track

Number

R

Programmable from track 00 to FFH.

Sector Address The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written.

RCN Relative Relative cylinder offset from present cylinder as used by the Relative

Cylinder Seek command.

Number

SK

Sectors Per

Track

Skip Flag

ST0

ST1

ST2

ST3

WGATE

Interval

Status 0

Status 1

Status 2

Status 3

Write Gate command. The number of sectors per track to be verified during a

Verify command when EC is set.

When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read

Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands.

Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the

1 Mbit data rate. Refer to the SPECIFY command for actual delays.

Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution.

Alters timing of WE to allow for pre-erase loads in perpendicular drives.

40

INSTRUCTION SET

Table 18 - Instruction Set

PHASE

DATA BUS

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W MT SK 0 0 1 1 0

W C --------

W H --------

Sector ID information prior to

Command execution.

W R --------

W N --------

W

W

W

Execution

EOT -------

GPL -------

DTL -------

Result R ------- ST0 -------

Data transfer between the

FDD and system.

Status information after Command execution.

R ST1 -------

R ST2 -------

R C --------

R

R

R

H --------

R --------

N --------

Sector ID information after

Command execution.

41

READ DELETED DATA

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W MT SK 0 1 1 0 0

W C --------

W

W

H --------

R --------

Sector ID information prior to

Command execution.

W N --------

W EOT -------

W GPL -------

W DTL -------

Execution

Result R ------- ST0 -------

R ST1 -------

R ST2 -------

R C --------

R H --------

R R --------

R N --------

Data transfer between the

FDD and system.

Status information after Command execution.

Sector ID information after

Command execution.

42

PHASE

DATA BUS

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W MT 0 0 0 1 0 1

W C --------

W

W

H --------

R --------

Sector ID information prior to

Command execution.

W N --------

W EOT -------

W GPL -------

W DTL -------

Execution

Result R ------- ST0 -------

R

R

R

R

R

R

ST1 -------

ST2 -------

C --------

H --------

R --------

N --------

Data transfer between the

FDD and system.

Status information after Command execution.

Sector ID information after

Command execution.

43

WRITE DELETED DATA

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W MT

W C --------

Codes

W H --------

Sector ID information prior to Command execution.

W R --------

W N --------

W EOT -------

W GPL -------

W DTL -------

Execution

Result R

-------

ST0 -------

R ST1 -------

R ST2 -------

R C --------

R H --------

R R --------

R N --------

Data transfer between the FDD and system.

Status information after

Command execution.

Sector ID information after Command execution.

44

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W 0

W C --------

Codes

W H --------

Sector ID information prior to Command execution.

W R --------

W N --------

W

W

READ A TRACK

DATA BUS

EOT -------

GPL -------

W DTL -------

Execution

Result R

-------

R

ST0 -------

ST1 -------

R ST2 -------

R C --------

Data transfer between the FDD and system.

FDC reads all of cylinders' contents from index hole to EOT.

Status information after

Command execution.

Sector ID information after Command execution.

R H --------

R R --------

R N --------

45

VERIFY

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

Command W MFM SK

W C --------

REMARKS

W

Result R

-------

R

R

R

H --------

W R --------

W N --------

W EOT -------

W GPL -------

W DTL/SC ------

Execution

ST0 -------

ST1 -------

ST2 -------

C --------

Sector ID information prior to Command execution.

No data transfer takes place.

Status information after

Command execution.

Sector ID information after Command execution.

R H --------

R R --------

R N --------

VERSION

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W 0 0 0 1 0 0 0 0 Code

Result

46

FORMAT A TRACK

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W 0 Codes

W N -------- Bytes/Sector

W SC -------- Sectors/Cylinder

W 3

W Byte

Input Sector Parameters Execution for

Each Sector

Repeat:

W

--------

C --------

W H --------

W R --------

W N --------

Result R

-------

ST0 -------

FDC formats an entire cylinder

Status information after

Command execution

R ST1 -------

R ST2 -------

R Undefined ------

R Undefined ------

R Undefined ------

R Undefined ------

47

RECALIBRATE

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

Execution Head retracted to Track 0

Interrupt.

SENSE INTERRUPT STATUS

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

Command

Result R ------- ST0 -------

REMARKS

R PCN -------

SPECIFY

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

Status information at the end of each seek operation.

REMARKS

Command

---

HUT ---

W HLT ------ ND

48

SENSE DRIVE STATUS

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

Command

Result R

-------

ST3 -------

REMARKS

Status information about

FDD

SEEK

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

W NCN -------

Execution Head positioned over proper cylinder on diskette.

CONFIGURE

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W 0 Configure

Information

W

---

FIFOTHR ---

Execution W

---------

PRETRK ---------

49

PHASE

DATA BUS

R/W

D7 D6 D5 D4 D3 D2 D1 D0

Command W 1 0 0 1 1 1 1

W RCN -------

REMARKS

DUMPREG

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W 0 0 0 0 1 0 *Note:

Registers placed in

FIFO

Execution

Result R

------

PCN-Drive 0 -------

R ------ PCN-Drive 1 -------

R ------ PCN-Drive 2 -------

R ------ PCN-Drive 3 -------

---

HUT ---

R HLT ------- ND

R ------- SC/EOT -------

LOCK D2

R EFIFO

--

FIFOTHR --

R -------- PRETRK --------

50

PHASE

Command

Execution

DATA BUS

R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

W 0 0 0 1 0 1 0 Commands

Result R

R

R

R

R

R

R

--------

--------

--------

ST0 --------

ST1 --------

ST2 --------

--------

C --------

--------

H --------

--------

R --------

--------

N --------

The first correct ID information on the

Cylinder is stored in Data

Register

Status information after

Command execution.

51

PHASE

Command

R/W

D7 D6 D5

DATA BUS

D4 D3 D2 D1 D0

W 0 0 0 1 0 0 1

OW 0 D3 D2 D1 D0 GAP WGATE

REMARKS

PHASE

DATA BUS

R/W

D7 D6 D5 D4 D3 D2 D1 D0

Command W

-----

Invalid Codes -----

REMARKS

Invalid Command Codes

(NoOp - FDC goes into Standby State)

ST0 = 80H Result R ------- ST0 -------

LOCK

DATA BUS

PHASE R/W

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command

Result

W LOCK 0 0

R 0

1 0 1 0 0

0 0 LOCK 0 0 0 0

Codes

SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write.

Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).

DATA TRANSFER COMMANDS

52

All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte.

An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status

Register during the seek portion of the command.

If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed.

Read Data

A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO.

After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read

Operation". Upon receipt of TC, or an implied TC

(FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command.

N determines the number of bytes per sector (see

Table 19 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for

CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex,

DTL should be set to FF Hex and has no impact on the number of bytes transferred.

Table 19 - Sector Sizes

N

00

01

02

03

..

07

The amount of data which can be handled with a single command to the FDC depends upon MT

(multi-track) and N (number of bytes/sector).

SECTOR SIZE

128 bytes

256 bytes

512 bytes

1024 bytes

...

16 Kbytes

If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT

The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. byte. Refer to Table 20.

At the completion of the Read Data command, the head is not unloaded until after the Head Unload

Time Interval (specified in the Specify command) has elapsed. If the host issues another command

53

before the head unloads, then the head settling time may be saved between subsequent reads.

If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0

MT

1

0

1

0

1

0 to "01" indicating abnormal termination, sets the

ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data

Command.

After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status

Register 1 to "1", sets the DD bit in Status Register

2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 21 describes the effect of the SK bit on the Read

Data command execution and results. Except where noted in Table 21, the C or R value of the sector address is automatically incremented (see

Table 23).

N

2

3

3

1

1

2

Table 20 - Effects of MT and N Bits

MAXIMUM TRANSFER

CAPACITY

FINAL SECTOR READ

FROM DISK

256 x 26 = 6,656

256 x 52 = 13,312

512 x 15 = 7,680

512 x 30 = 15,360

1024 x 8 = 8,192

1024 x 16 = 16,384

26 at side 0 or 1

26 at side 1

15 at side 0 or 1

15 at side 1

8 at side 0 or 1

16 at side 1

54

1

1

0

0

SK BIT

VALUE

Table 21 - Skip Bit vs Read Data Command

DATA ADDRESS

MARK TYPE

ENCOUNTERED

RESULTS

READ? ST2 SET?

DESCRIPTION OF

RESULTS

Normal Data

Deleted Data

Normal Data

Deleted Data

Yes

Yes

Yes

No

No

Yes

No

Yes

Normal termination.

Address not incremented. Next sector not searched for.

Normal termination.

Normal termination. Sector not read

("skipped").

55

Read Deleted Data

This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a

Data Field.

Table 22 describes the effect of the SK bit on the

Read Deleted Data command execution and results.

Except where noted in Table 22, the C or R value of the sector address is automatically incremented

(see Table 23).

Table 22 - Skip Bit vs. Read Deleted Data Command

SK BIT

VALUE

DATA ADDRESS

MARK TYPE

ENCOUNTERED

RESULTS

READ? ST2 SET?

DESCRIPTION OF

RESULTS

0

1

0

1

Normal Data

Deleted Data

Normal Data

Deleted Data

Yes

Yes

No

Yes

Yes

No

Yes

No

Address not incremented. Next sector not searched for.

Normal termination.

Normal termination. Sector not read

("skipped").

Normal termination.

Read A Track

This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track.

Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command.

The FDC compares the ID information read from each sector with the specified value in the command and sets the

ND flag of Status Register 1 to a "1" if there is no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits

(bits D7 and D5 of the first command byte respectively) should always be set to "0".

This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin, then it sets the IC code in Status

Register 0 to "01" (abnormal termination), sets the

MA bit in Status Register 1 to "1", and terminates the command.

56

MT HEAD

Table 23 - Result Phase Table

FINAL SECTOR

TRANSFERRED TO

ID INFORMATION AT RESULT PHASE

HOST

0 0 Less than EOT

C

NC

H

NC

R

R + 1

N

NC

1

Equal to EOT

Less than EOT

Equal to EOT

1 0 Less than EOT

C + 1

NC

C + 1

NC

NC

NC

NC

NC

01

R + 1

01

R + 1

NC

NC

NC

NC

1

Equal to EOT

Less than EOT

NC

NC

LSB

NC

01

R + 1

NC

NC

Equal to EOT C + 1 LSB 01 NC

NC: No Change, the same value as the one at the beginning of command execution.

LSB: Least Significant Bit, the LSB of H is complemented.

Write Data

following items are the same. Please refer to the

Read Data Command for details:

After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field.

• Transfer

EN (End of Cylinder) bit

ND (No Data) bit

Head Load, Unload Time Interval

• ID information when the host terminates the command

• Definition of DTL when N = 0 and when N does not = 0

After writing data into the current sector, the FDC

Write Deleted Data computes the CRC value and writes it into the

CRC field at the end of the sector transfer. The

This command is almost the same as the Write

Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next

Data command except that a Deleted Data

Address Mark is written at the beginning of the data field. The FDC continues this "Multi-Sector

Write Operation". Upon receipt of a terminal count

Data Field instead of the normal Data Address

Mark. This command is typically used to mark a signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads bad sector containing an error on the floppy disk.

Verify the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID

The Verify command is used to verify the data fields, it sets the IC code in Status Register 0 to

"01" (abnormal termination), sets the DE bit of stored on a disk. This command acts exactly like a Read Data command except that no data is

Status Register 1 to "1", and terminates the Write

Data command.

The Write Data command operates in much the transferred to the host. Data is read from the disk and CRC is computed and checked against the same manner as the Read Data command. The previously-stored value.

57

Because data is not transferred to the host, TC cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when

the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0",

DTL/SC should be programmed to 0FFH. Refer to

Table 23 and Table 24 for information concerning the values of MT and EC versus SC and EOT value.

Definitions:

# Sectors Per Side = Number of formatted sectors per each side of the disk.

# Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1".

MT

0

0

0

EC

0

0

1

Table 24 - Verify Command Result Phase

SC/EOT VALUE TERMINATION RESULT

SC = DTL

EOT

≤ # Sectors Per Side

SC = DTL

EOT > # Sectors Per Side

SC

≤ # Sectors Remaining AND

EOT

≤ # Sectors Per Side

SC > # Sectors Remaining OR

EOT > # Sectors Per Side

Success Termination

Result Phase Valid

Unsuccessful Termination

Result Phase Invalid

Successful Termination

Result Phase Valid

Unsuccessful Termination

Result Phase Invalid

1

1

0

0

SC = DTL

EOT

≤ # Sectors Per Side

SC = DTL

EOT > # Sectors Per Side

SC

≤ # Sectors Remaining AND

EOT

≤ # Sectors Per Side

Successful Termination

Result Phase Valid

Unsuccessful Termination

Result Phase Invalid

Successful Termination

Result Phase Valid

1 1 SC > # Sectors Remaining OR

EOT > # Sectors Per Side

Unsuccessful Termination

Result Phase Invalid

Note: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on

Side 0, verifying will continue on Side 1 of the disk.

58

Format A Track

The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled

After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for

C, H, R, and N (cylinder, head, sector number and sector size respectively). the FDC encounters a pulse on the nINDEX pin again and it terminates the command.

Table 25 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics.

FORMAT FIELDS

SYSTEM 34 (DOUBLE DENSITY) FORMAT

GAP4a

80x

4E

GAP4a

40x

FF

GAP4a

80x

4E

SYNC

12x

00

IAM GAP1

50x

4E

SYNC

12x

00

3x 3x

C2 A1

IDAM

FE

C

Y

L

H

D

S

E

C

N

O

C

R

C

GAP2

22x

4E

SYNC

12x

00

DATA

AM

3x

A1

FB

F8

SYNC

6x

00

DATA

SYSTEM 3740 (SINGLE DENSITY) FORMAT

IAM GAP1

26x

FF

FC

SYNC

6x

IDAM C

Y

H

D

S

E

N

O

C

R

GAP2

11x

00 L C C FF

FE

SYNC

6x

DATA

AM

00

FB

F8

DATA

PERPENDICULAR FORMAT

SYNC

12x

00

IAM GAP1

50x

SYNC

12x

4E 00

3x 3x

C2 A1

IDAM C

Y

H

D

S

E

N

O

C

R

GAP2

41x

L C C 4E

FE

SYNC

12x

DATA

AM

00

3x

A1

FB

F8

DATA

C

R

C

GAP3 GAP 4b

C

R

C

GAP3 GAP 4b

C

R

C

GAP3 GAP 4b

59

5.25"

Drives

Table 25 - Typical Values for Formatting

FORMAT SECTOR SIZE N SC

FM

MFM

128

128

512

1024

2048

4096

...

256

256

512*

1024

2048

4096

...

01

01

02

03

04

05

...

00

00

02

03

04

05

...

12

10

09

04

02

01

12

10

08

04

02

01

GPL1

07

10

18

46

C8

C8

0A

20

2A

80

C8

C8

GPL2

09

19

30

87

FF

FF

0C

32

50

F0

FF

FF

3.5"

Drives

FM

MFM

128

256

512

256

512**

1024

0

1

2

1

2

3

0F

09

05

0F

09

05

07

0F

1B

0E

1B

35

1B

2A

3A

36

54

74

GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections.

GPL2 = suggested GPL value in Format A Track command.

*PC/AT values (typical)

**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.

NOTE: All values except sector size are in hex.

60

CONTROL COMMANDS

Control commands differ from the other commands in that no data transfer takes place.

Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt.

Read ID

The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01"

(abnormal termination), sets the MA bit in Status

Register 1 to "1", and terminates the command.

The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt

Status command. Otherwise, valuable interrupt status information will be lost.

Recalibrate

This command causes the read/write head within the FDC to retract to the track 0 position. The

FDC clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD.

As long as the nTRK0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register

0 is set to "1" and the command is terminated. If the nTRK0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than

80 tracks per side may require more than one

Recalibrate command to return the head back to physical Track 0.

The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of

61 the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another

Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once.

Upon power up, the software must issue a

Recalibrate command to properly initialize all drives and the controller.

Seek

The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference:

PCN < NCN: Direction signal to drive set to

PCN > NCN: Direction signal to drive set to

The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the

Specify command. After each step pulse is issued, NCN is compared against PCN, and when

NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once.

Note that if implied seek is not enabled, the read and write commands should be preceded by:

1) Seek command - Step to the proper track

2) Sense Interrupt Status command - Terminate the Seek command

3) Read ID - Verify head is on proper track

4) Issue Read/Write command.

The Seek command does not have a result phase.

Therefore, it is highly recommended that the

"1" (step in) and is

"0" (step out) and i

Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit

(Head Address) in ST0 will always return to a "0".

When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense

Interrupt Status command.

Sense Interrupt Status

An interrupt signal is generated by the FDC for one of the following reasons:

1. Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command

2. End of Seek, Relative Seek, or Recalibrate command

3. FDC requires a data transfer during the execution phase in the non-DMA mode

The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of

Status Register 0, identifies the cause of the interrupt.

Table 26 - Interrupt Identification

SE

0

1

1

IC

11

00

01

INTERRUPT DUE TO

Polling

Normal termination of Seek or Recalibrate command

Abnormal termination of

Seek or Recalibrate command

The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense

Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command.

62

Sense Drive Status

Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command

(Head Unload Time) defines the timefrom the end of the execution phase of one of the read/write commands to the head unload state. The SRT

(Step Rate Time) defines the time interval between phase. Status Register 3 contains the drive status information. adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT

(Head Load Time) defines the time between when

Specify

The Specify command sets the initial values for each of the three internal times. The HUT the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table

27. The values are the same for MFM and FM.

Table 27 - Drive Control Delays (ms)

HUT SRT

0

1

..

E

F

2M

64

4

..

56

60

1M 500K 300K 250K 2M

128

8

..

112

120

256

16

..

224

240

426

26.7

..

373

400

512

32

..

448

480

4

3.75

..

0.5

0.25

1M 500K 300K 250K

8

7.5

..

1

0.5

16

15

..

2

1

26.7

25

..

3.33

1.67

32

30

..

4

2

HLT

2M 1M 500K 300K 250K

00

01

02

..

7F

7F

64

0.5

1

..

63

63.5

128

1

2

..

126

127

256

2

4

..

252

254

426

3.3

6.7

..

420

423

512

4

8

.

504

508

The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are signaled by the FDRQ pin. Non-DMA mode uses the RQM bit and the interrupt to signal data transfers.

63

Configure

The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements.

Configure Default Values:

EIS - No Implied Seeks

EFIFO - FIFO Disabled

POLL - Polling Enabled

FIFOTHR - FIFO Threshold Set to 1 Byte

PRETRK - Pre-Compensation Set to Track 0

EIS - Enable Implied Seek. When set to "1", the

FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek.

EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-bybyte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1".

POLL - Disable polling of the drives. Defaults to

"0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired.

FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes.

PRETRK - Pre-Compensation Start Track

Number. Programmable from track 0 to 255.

Defaults to track 0. A "00" selects track 0; "FF" selects track 255.

Version

The Version command checks to see if the controller is an enhanced type or the older type

(765A). A value of 90 H is returned as the result byte.

64

Relative Seek

The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit.

DIR Head Step Direction Control

DIR

0

1

ACTION

Step Head Out

Step Head In

RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number.

The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks.

Relative Seeks cannot be overlapped with other

Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of

Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0.

As an example, assume that a floppy drive has

300 useable tracks. The host needs to read track

300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track

255. If a Relative Seek command is issued, the

FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the

FDC could position the head on using Relative

Seek will be 295 (D), the initial track + 255 (D).

The maximum count that the head can be moved with a single Relative Seek command is 255 (D).

The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain

39 (D). The resulting PCN value is thus (RCN +

PCN) mod 256. Functionally, the FDC starts

counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than

255. The FDC does not keep track that it is working in an "extended track area" (greater than

255). Any command issued will use the current

PCN value except for the Recalibrate command, which only looks for the TRACK0 signal.

Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the

"extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area.

To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary.

A Relative Seek can be used instead of the normal

Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command.

Perpendicular Mode

The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 28 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0).

Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select

Register. The user must ensure that these two data rates remain consistent.

The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers.

This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The Format Fields table illustrates the change in the Gap2 field size for the perpendicular format.

On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL

VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from

65

the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation.

For the Write Data case, the FDC activates Write

Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and

CRC. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0).

It should be noted that none of the alterations in

Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the

Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged.

The perpendicular mode command is enhanced to allow specific drives to be designated

Perpendicular recording drives. This enhancement allows data transfers between

Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values.

When both GAP and WGATE bits of the

PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0,

D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply:

1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate.

2. The write pre-compensation given to a perpendicular mode drive will be 0ns.

3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation.

Note: Bits D0-D3 can only be overwritten when

OW is programmed as a "1". If either GAP or WGATE is a "1" then D0-D3 are ignored.

Software and hardware resets have the following effect on the PERPENDICULAR MODE

COMMAND:

1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value.

2. "Hardware" resets will clear all bits (GAP,

WGATE and D0-D3) to "0", i.e all conventional mode.

66

WGATE GAP MODE

0

0

1

1

0

1

0

1

Conventional

Perpendicular

(500 Kbps)

Reserved

(Conventional)

Perpendicular

(1 Mbps)

LOCK

In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used.

The LOCK command defines whether the EFIFO,

FIFOTHR, and PRETRK parameters of the

CONFIGURE command can be RESET by the

DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values.

All "hardware" RESET from the RESET_DRV pin will set the LOCK bit to logic "0" and return the

EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte.

Table 28 - Effects of WGATE and GAP Bits

LENGTH OF

GAP2 FORMAT

FIELD

22 Bytes

22 Bytes

22 Bytes

41 Bytes

PORTION OF

GAP 2

WRITTEN BY

WRITE DATA

OPERATION

0 Bytes

19 Bytes

0 Bytes

38 Bytes

ENHANCED DUMPREG

The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands.

COMPATIBILITY

The FDC37M81x was designed with software compatibility in mind. It is a fully backwards- compatible solution with the older generation

765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a

PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.

67

SERIAL PORT (UART)

The FDC37M81x incorporates two full function

UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A.

The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the

Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a

UART is enabled by programming OUT2 of that

UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA 1.0, HP-SIR and ASK-IR modes of operation.

Note: The UARTs may be configured to share an interrupt. Refer to the Configuration section for more information.

REGISTER DESCRIPTION

Addressing of the accessible registers of the Serial

Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial

Port registers are located at sequentially increasing addresses above these base addresses. The FDC37M81x contains two serial ports, each of which contain a register set as described below.

Table 29 - Addressing the Serial Port

DLAB* A2 A1 A0 REGISTER NAME

*Note: DLAB is Bit 7 of the Line Control Register

68

The following section describes the operation of the registers.

RECEIVE BUFFER REGISTER (RB)

Address Offset = 0H, DLAB = 0, READ ONLY

This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.

TRANSMIT BUFFER REGISTER (TB)

Address Offset = 0H, DLAB = 0, WRITE ONLY

This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the

Transmit Buffer when the transmission of the previous byte is complete.

INTERRUPT ENABLE REGISTER (IER)

Address Offset = 1H, DLAB = 0, READ/WRITE

The lower four bits of this register control the enables of the five interrupt sources of the Serial

Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the FDC37M81x.

All other system functions operate in their normal manner, including the Line Status and MODEM

Status Registers. The contents of the Interrupt

Enable Register are described below.

Bit 0

This bit enables the Received Data Available

Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1".

Bit 1

This bit enables the Transmitter Holding Register

Empty Interrupt when set to logic "1".

Bit 2

This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and

Break. The Line Status Register must be read to determine the source.

Bit 3

This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state.

Bits 4 through 7

These bits are always logic "0".

FIFO CONTROL REGISTER (FCR)

Address Offset = 2H, DLAB = X, WRITE

This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note:

DMA is not supported. The UART1 and UART2

FCR’s are shadowed in the UART1 FIFO Control

Shadow Register (LD8:CRC3[7:0]) and UART2

FIFO Control Shadow Register (LD8:CRC4[7:0]).

Bit 0

Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed.

69

Bit 1

Setting this bit to a logic "1" clears all bytes in the

RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is selfclearing.

Bit 2

Setting this bit to a logic "1" clears all bytes in the

XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is selfclearing.

Bit 3

Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip.

Bit 4,5

Reserved

Bit 6,7

These bits are used to set the trigger level for the

RCVR FIFO interrupt.

INTERRUPT IDENTIFICATION REGISTER (IIR)

Address Offset = 2H, DLAB = X, READ

By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority:

1. Receiver Line Status (highest priority)

2. Received Data Ready

3. Transmitter Holding Register Empty

4. MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to

Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.

Bit 0

This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending.

Bits 1 and 2

These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table.

Bit 3

In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending.

Bits 4 and 5

These bits of the IIR are always logic "0".

Bits 6 and 7

These two bits are set when the FIFO CONTROL

Register bit 0 equals 1.

Bit 7 Bit 6

0 0

RCVR FIFO

Trigger Level (BYTES)

1

0 1 4

1 0

1 1

8

14

70

FIFO

MODE

ONLY

BIT 3

Table 30 - Interrupt Control

INTERRUPT

IDENTIFICATION

REGISTER

BIT 2 BIT 1 BIT 0

PRIORITY

LEVEL

0 0 0 1

INTERRUPT SET AND RESET FUNCTIONS

INTERRUPT

TYPE

- None

INTERRUPT

SOURCE

None

INTERRUPT

RESET

CONTROL

-

Status

Reading the Line

Status Register Parity Error,

Framing Error or

Break Interrupt

Available Available

Read Receiver

Buffer or the FIFO drops below the trigger level.

0 0 0

Timeout

Indication

No Characters

Have Been

Removed From or

Input to the RCVR

FIFO during the last 4 Char times and there is at least 1 char in it during this time

Reading the

Receiver Buffer

Register

0

Third Transmitter

Fourth

Holding

Register Empty

Transmitter

Holding Register

Empty

Reading the IIR

Register (if Source of Interrupt) or

Writing the

Transmitter

Holding Register

MODEM Status Clear to Send or

Data Set Ready or

Ring Indicator or

Data Carrier

Detect

Reading the

MODEM Status

Register

71

LINE CONTROL REGISTER (LCR)

Address Offset = 3H, DLAB = 0, READ/WRITE

This register contains the format information of the serial line. The bit definitions are:

Bits 0 and 1

These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows:

The Start, Stop and Parity bits are not included in the word length.

BIT 1 BIT 0 WORD LENGTH

0

0

1

1

0

1

0

1

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2

This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information.

BIT 2 WORD LENGTH

NUMBER OF

STOP BITS

0 -- 1

1.5

2

2

2

Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.

Bit 3

Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked

(receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed).

Bit 4

Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked.

Bit 5

Stick Parity bit. When bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4.

Bit 6

Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the

Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial

Port to alert a terminal in a communications system.

Bit 7

Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the

Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter

Holding Register, or the Interrupt Enable Register.

MODEM CONTROL REGISTER (MCR)

Address Offset = 4H, DLAB = X, READ/WRITE

This 8 bit register controls the interface with the

MODEM or data set (or device emulating a

MODEM). The contents of the MODEM control register are described below.

Bit 0

This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic

"0", the nDTR output is forced to a logic "1".

72

Bit 1

This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0.

Bit 2

This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU.

Bit 3

Output 2 (OUT2). This bit is used to enable an

UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled.

Bit 4

This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur:

1. The TXD is set to the Marking State(logic "1").

2. The receiver Serial Input (RXD) is disconnected.

3. The output of the Transmitter Shift Register is

"looped back" into the Receiver Shift Register input.

4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.

5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs

(nDSR, nCTS, RI, DCD).

6. The Modem Control output pins are forced inactive high.

7. Data that is transmitted is immediately received.

This feature allows the processor to verify the transmit and receive data paths of the Serial Port.

In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The

MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the

MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register.

73

Bits 5 through 7

These bits are permanently set to logic zero.

LINE STATUS REGISTER (LSR)

Address Offset = 5H, DLAB = X, READ/WRITE

Bit 0

Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the

FIFO.

Bit 1

Overrun Error (OE). Bit 1 indicates that data in the

Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In

FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line

Status Register is read.

Bit 2

Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the

Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the

FIFO.

Bit 3

Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit

3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies

to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'.

Bit 4

Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the

Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line

Status Register. In the FIFO mode this error is associated with the particular character in the

FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO.

When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic

"1" for at least 1/2 bit time.

Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled.

Bit 5

Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the

Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT

FIFO. Bit 5 is a read only bit.

Bit 6

Transmitter Empty (TEMT). Bit 6 is set to a logic

"1" whenever the Transmitter Holding Register

(THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty,

Bit 7

This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic

"1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO.

MODEM STATUS REGISTER (MSR)

Address Offset = 6H, DLAB = X, READ/WRITE

This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status

Register (MSR) provide change information.

These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status

Register is read.

Bit 0

Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read.

74

Bit 1

Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read.

Bit 2

Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic

"0" to logic "1".

Bit 3

Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.

Note: Whenever bit 0, 1, 2, or 3 is set to a logic

"1", a MODEM Status Interrupt is generated.

Bit 4

This bit is the complement of the Clear To Send

(nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR.

Bit 5

This bit is the complement of the Data Set Ready

(nDSR) input. If bit 4 of the MCR is set to logic

"1", this bit is equivalent to DTR in the MCR.

Bit 6

This bit is the complement of the Ring Indicator

(nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR.

Bit 7

This bit is the complement of the Data Carrier

Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR.

SCRATCHPAD REGISTER (SCR)

Address Offset =7H, DLAB =X, READ/WRITE

This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily.

PROGRAMMABLE BAUD RATE GENERATOR

(AND DIVISOR LATCHES DLH, DLL)

The Serial Port contains a programmable Baud

Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535.

75

The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than

38.4k, a 1.8432MHz frequency for 115.2k, a

3.6864MHz frequency for 230.4k and a

7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x the

Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator.

Upon loading either of the Divisor Latches, a 16 bit

Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a

50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count.

Table 31 shows the baud rates.

Effect Of The Reset on Register File

The Reset Function Table (Table 32) details the effect of the Reset input on each of the registers of the Serial Port.

FIFO INTERRUPT MODE OPERATION

When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows:

A. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level.

B. The IIR receive data available indication also occurs when the FIFO trigger level is reached.

It is cleared when the FIFO drops below the trigger level.

C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available

(IIR=04H) interrupt.

D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty.

When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:

A. A FIFO timeout interrupt occurs if all the following conditions exist:

- At least one character is in the FIFO.

- The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay).

- The most recent CPU read of the FIFO was longer than 4 continuous character times ago.

This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character.

B. Character times are calculated by using the

RCLK input for a clock signal (this makes the delay proportional to the baudrate).

C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO.

D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR

FIFO.

When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"),

XMIT interrupts occur as follows:

A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read.

B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs:

THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.

Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.

76

FIFO POLLED MODE OPERATION

With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled

Mode of operation. Since the RCVR and

- the same way as when in the interrupt mode, the IIR is not affected since EIR bit

2=0.

Bit 5 indicates when the XMIT FIFO is empty.

XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and

XMITTER status via the LSR. LSR definitions for

- Bit 6 indicates that both the XMIT FIFO and

- shift register are empty.

Bit 7 indicates whether there are any errors in the RCVR FIFO. the FIFO Polled Mode are as follows:

-

Bit 0=1 as long as there is one byte in the

RCVR FIFO.

There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode,

- Bits 1 to 4 specify which error(s) have occurred. Character error status is handled however, the RCVR and XMIT FIFOs are still fully capable of holding characters.

Table 31 - Baud Rates

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

1

HIGH

SPEED BIT

2

50 2304

75 1536

110 1047

134.5 857

150 768

300 384

600 192

1200 96

1800 64

2000 58

0.001

-

-

0.004

-

-

-

-

-

0.005

X

X

X

X

X

X

X

X

X

X

2400 48

3600 32

4800 24

7200 16

9600 12

19200 6

38400 3

57600 2

115200 1

230400 32770

-

-

-

-

-

-

0.030

0.16

0.16

0.16

460800 32769 0.16

Note

1

Note

2

: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

: The High Speed bit is located in the Device Configuration Space.

X

X

X

X

X

X

X

X

X

1

1

77

REGISTER/SIGNAL

Interrupt Enable Register

Interrupt Identification Reg.

FIFO Control

Line Control Reg.

MODEM Control Reg.

Line Status Reg.

MODEM Status Reg.

TXD1, TXD2

Table 32 - Reset Function

RESET CONTROL

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET STATE

All bits low

Bit 0 is high; Bits 1 - 7 low

All bits low

All bits low

All bits low

All bits low except 5, 6 high

Bits 0 - 3 low; Bits 4 - 7 input

High

INTRPT (RCVR errs) RESET/Read LSR

INTRPT (RCVR Data Ready) RESET/Read RBR

Low

Low

INTRPT (THRE) RESET/ReadIIR/Write THR Low

OUT2B RESET High

OUT1B RESET High

RCVR FIFO RESET/

FCR1*FCR0/_FCR0

All Bits Low

XMIT FIFO RESET/

FCR1*FCR0/_FCR0

All Bits Low

78

REGISTER

ADDRESS*

ADDR = 0

DLAB = 0

ADDR = 0

DLAB = 0

ADDR = 1

DLAB = 0

ADDR = 2

ADDR = 2

ADDR = 3

ADDR = 4

ADDR = 5

ADDR = 6

ADDR = 7

Table 33 - Register Summary for an Individual UART Channel

REGISTER NAME

REGISTER

SYMBOL BIT 0

Receive Buffer Register (Read Only) RBR

THR

Data Bit 0

(Note 1)

Data Bit 0 Transmitter Holding Register (Write

Only)

Interrupt Enable Register IER

Interrupt Ident. Register (Read Only)

FIFO Control Register (Write Only)

Line Control Register

MODEM Control Register

Line Status Register

MODEM Status Register

Scratch Register (Note 4)

IIR

FCR

(Note 7)

LCR

MCR

LSR

MSR

SCR

BIT 1

Data Bit 1

Data Bit 1

Enable

Received

Data

Available

Interrupt

(ERDAI)

Data

Terminal

Ready

(DTR)

Data Ready

(DR)

Delta Clear to Send

(DCTS)

Bit 0

Enable

Transmitter

Holding

Register

Empty

Interrupt

(ETHREI)

Interrupt ID

Bit

"0" if

Interrupt

Pending

FIFO Enable RCVR FIFO

Reset

Word Length

Select Bit 0

(WLS0)

Word Length

Select Bit 1

(WLS1)

Request to

Send (RTS)

Overrun

Error (OE)

Delta Data

Set Ready

(DDSR)

Bit 1

ADDR = 0

DLAB = 1

Divisor Latch (LS) DDL Bit 0 Bit 1

ADDR = 1

DLAB = 1

Divisor Latch (MS) DLM Bit 8 Bit 9

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.

79

BIT 2

Table 33 - Register Summary for an Individual UART Channel (continued)

BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

Data Bit 2

Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7

Data Bit 2

Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7

Enable

Receiver Line

Status

Interrupt

(ELSI)

Enable

MODEM

Status

Interrupt

(EMSI)

0 0 0 0

Interrupt ID Bit Interrupt ID Bit

(Note 5) Enabled

(Note 5)

Enabled

(Note 5)

XMIT FIFO

Reset

Number of

Stop Bits

(STB)

DMA Mode

Select (Note

6)

Parity Enable

(PEN)

Even Parity

Select (EPS)

Stick Parity

LSB

Set Break

MSB

Divisor Latch

Access Bit

(DLAB)

OUT1

(Note 3)

OUT2

(Note 3)

Parity Error

(PE)

Framing Error

(FE)

Break

Interrupt (BI)

Transmitter

Holding

Register

(THRE)

Transmitter

Empty (TEMT)

(Note 2)

Error in RCVR

FIFO (Note 5)

Trailing Edge

Ring Indicator

(TERI)

Bit 2

Delta Data

Carrier Detect

(DDCD)

Clear to Send

(CTS)

Data Set

Ready (DSR)

Ring Indicator

(RI)

Data Carrier

Detect (DCD)

Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Bit 2

Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Bit 10

Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

Note 3: This bit no longer has a pin associated with it.

Note 4: When operating in the XT mode, this register is not available.

Note 5: These bits are always zero in the non-FIFO mode.

Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.

Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register

(LD8:CRC3[7:0]) and UART2 FIFO Control Shadow Register (LD8:CRC4[7:0]).

80

NOTES ON SERIAL PORT OPERATION

FIFO MODE OPERATION:

GENERAL

The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.

TX AND RX FIFO OPERATION

The Tx portion of the UART transmits data through

TXD as soon as the CPU loads a byte into the Tx

FIFO. The UART will prevent loads to the Tx

FIFO if it currently holds 16 characters.

Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx.

The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt.

Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have the Tx FIFO empties after this condition, the Tx been loaded into the FIFO, concurrently. When interrupt will be activated without a one

character delay.

Rx support functions and operation are quite different from those described for the transmitter.

The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the

CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag.

Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs.

One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the

UART. To prevent the software from having to

check for this situation the chip incorporates a

timeout interrupt.

The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the

CPU nor the Rx shift register has accessed the Rx

FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it.

These FIFO related features allow optimization of

CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud).

81

INFRARED INTERFACE

The infrared interface provides a two-way wireless zero is signaled by sending a 500KHz waveform communications port using infrared as a transmission medium. Several IR implementations have been provided for the second UART in this chip (logical device 5), IrDA 1.0, and Amplitude

Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or optional

IRTX and IRRX pins. These can be selected through the configuration registers.

IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform.

The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform.

If the Half Duplex option is chosen, there is a timeout when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in

Logical Device 5. This register allows the time-out to be programmed to any value between 0 and

10msec in 100usec increments.

82

PARALLEL PORT

The FDC37M81x incorporates an IBM XT/AT The functionality of the Parallel Port is achieved compatible parallel port. This supports the optional PS/2 type bi-directional parallel port

(SPP), the Enhanced Parallel Port (EPP) and the

Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation.

The FDC37M81x also provides a mode for support of the floppy disk controller on the parallel port.

The parallel port also incorporates SMSC's

ChiProtect circuitry, which prevents possible damage to the parallel port due to printer powerup. through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below:

DATA PORT

STATUS PORT

CONTROL PORT

BASE ADDRESS + 00H

BASE ADDRESS + 01H

BASE ADDRESS + 02H

EPP ADDR PORT

EPP DATA PORT 0

EPP DATA PORT 1

EPP DATA PORT 2

BASE ADDRESS + 03H

BASE ADDRESS + 04H

BASE ADDRESS + 05H

BASE ADDRESS + 06H

BASE ADDRESS + 07H EPP DATA PORT 3

The bit map of these registers is:

D0 D1 D2 D3 D4 D5 D6 D7 Note

STATUS PORT TMOUT

CONTROL

PORT

0

AUTOFD

0 nERR SLCT PE nACK nBUSY

0

1

1

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 EPP ADDR

PORT

EPP DATA

PORT 0

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 EPP DATA

PORT 1

EPP DATA

PORT 2

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3

EPP DATA

PORT 3

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3

Note 1: These registers are available in all modes.

Note 2: These registers are only available in EPP mode.

Note 3: For EPP mode, IOCHRDY must be connected to the ISA bus.

83

HOST

CONNECTOR

PIN NUMBER

2-9

Table 34 - Parallel Port Connector

STANDARD EPP ECP

PD<0:7> PD<0:7> PD<0:7> nAckReverse(3)

HostAck(3) nPeriphRequest(3) nReverseRqst(3)

(1) = Compatible Mode

(3) = High Speed Mode

Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14,

1993. This document is available from Microsoft.

84

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL

AND EPP MODES

DATA PORT

ADDRESS OFFSET = 00H

The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus with the rising edge of the nIOW input. The contents of this register are buffered

(non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode,

PD0 - PD7 ports are buffered (not latched) and output to the host CPU.

STATUS PORT

ADDRESS OFFSET = 01H

The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of an nIOR read cycle. The bits of the Status Port are defined as follows:

BIT 0 TMOUT - TIME OUT

This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET.

Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect.

BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.

BIT 3 nERR - nERROR

The level on the nERROR input is read by the

CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic

1 means no error has been detected.

BIT 4 SLCT - PRINTER SELECTED STATUS

The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected.

BIT 5 PE - PAPER END

The level on the PE input is read by the CPU as bit

5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper.

BIT 6 nACK - nACKNOWLEDGE

The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data.

BIT 7 nBUSY - nBUSY

The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status

Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character.

A logic 1 means that it is ready to accept the next character.

CONTROL PORT

ADDRESS OFFSET = 02H

The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.

BIT 0 STROBE - STROBE

This bit is inverted and output onto the nSTROBE output.

BIT 1 AUTOFD - AUTOFEED

This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed.

85

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without inversion.

BIT 3 SLCTIN - PRINTER SELECT INPUT

This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected.

BIT 4 IRQE - INTERRUPT REQUEST ENABLE

The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled.

BIT 5 PCD - PARALLEL CONTROL DIRECTION

Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional,

EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read).

Bits 6 and 7 during a read are a low level, and cannot be written.

EPP ADDRESS PORT

ADDRESS OFFSET = 03H

The EPP Address Port is located at an offset of

'03H' from the base address. The address register is cleared at initialization by RESET.

During a WRITE operation, the contents of DB0-

DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports, the leading edge of nIOW causes an EPP ADDRESS WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle.

During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP

ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of

ADDRSTB latches the PData for the duration of the IOR cycle. This register is only available in

EPP mode.

EPP DATA PORT 0

ADDRESS OFFSET = 04H

The EPP Data Port 0 is located at an offset of

'04H' from the base address. The data register is cleared at initialization by RESET. During a

WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the PD0 -

PD7 ports, the leading edge of nIOW causes an

EPP DATA WRITE cycle to be performed, the trailing edge of IOW latches the data for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of IOR causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the IOR cycle. This register is only available in EPP mode.

EPP DATA PORT 1

ADDRESS OFFSET = 05H

The EPP Data Port 1 is located at an offset of

'05H' from the base address. Refer to EPP DATA

PORT 0 for a description of operation. This register is only available in EPP mode.

EPP DATA PORT 2

ADDRESS OFFSET = 06H

The EPP Data Port 2 is located at an offset of

'06H' from the base address. Refer to EPP DATA

PORT 0 for a description of operation. This register is only available in EPP mode.

EPP DATA PORT 3

ADDRESS OFFSET = 07H

The EPP Data Port 3 is located at an offset of

'07H' from the base address. Refer to EPP DATA

PORT 0 for a description of operation. This register is only available in EPP mode.

EPP 1.9 OPERATION

When the EPP mode is selected in the configuration register, the standard and bidirectional modes are also available. If no EPP

Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or

86

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the SPP

Control Port and direction is controlled by PCD of the Control port.

In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.

During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted.

Software Constraints

Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (ie a 04H or 05H should be written to the

Control port). If the user leaves PCD as a logic

"1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated.

EPP 1.9 Write

The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or

Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances:

1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high.

2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB,

87 nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.

Write Sequence of operation

1. The host selects an EPP register, places data on the SData bus and drives nIOW active.

2. The chip drives IOCHRDY inactive (low).

3. If WAIT is not asserted, the chip must wait until WAIT is asserted.

4. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.

5. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid.

6. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle.

7. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. b) The chip latches the data from the SData bus for the PData bus and asserts

(releases) IOCHRDY allowing the host to complete the write cycle.

8. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle.

9. Chip may modify nWRITE and nPDATA in preparation for the next cycle.

EPP 1.9 Read

The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances:

1 If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high.

2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.

Read Sequence of Operation

1. The host selects an EPP register and drives nIOR active.

2. The chip drives IOCHRDY inactive (low).

3. If WAIT is not asserted, the chip must wait until WAIT is asserted.

4. The chip tri-states the PData bus and deasserts nWRITE.

5. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid.

6. Peripheral drives PData bus valid.

7. Peripheral deasserts nWAIT, indicating that

PData is valid and the chip may begin the termination phase of the cycle.

8. a) The chip latches the data from the PData bus for the SData bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase. b) The chip drives the valid data onto the

SData bus and asserts (releases)

IOCHRDY allowing the host to complete the read cycle.

9. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the

PData bus is tri-stated.

10. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.

EPP 1.7 OPERATION

When the EPP 1.7 mode is selected in the configuration register, the standard and bidirectional modes are also available. If no EPP

Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the SPP

Control Port and direction is controlled by PCD of the Control port.

88

In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle (nIOR or nIOW asserted) to the end of the cycle nIOR or nIOW deasserted). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.

Software Constraints

Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and

EPP read.

EPP 1.7 Write

The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or

Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle.

This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high.

Write Sequence of Operation

1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE.

2. The host selects an EPP register, places data on the SData bus and drives nIOW active.

3. The chip places address or data on PData bus.

4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid.

5. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs.

6. When the host deasserts nIOW the chip deasserts nDATASTB or nADDRSTRB and latches the data from the SData bus for the

PData bus.

7. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

EPP 1.7 Read

The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle.

IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high.

Read Sequence of Operation

1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tristates the PData bus.

2. The host selects an EPP register and drives nIOR active.

3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid.

4. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs.

5. The Peripheral drives PData bus valid.

6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle.

7. When the host deasserts nIOR the chip deasserts nDATASTB or nADDRSTRB.

9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

89

EPP

SIGNAL

nWRITE

PD<0:7>

INTR

WAIT

DATASTB

RESET

EPP NAME

nWrite nWait nReset

Address/Data

Interrupt nData Strobe

Table 35 - EPP Pin Descriptions

TYPE EPP DESCRIPTION

O This signal is active low. It denotes a write operation.

I/O Bi-directional EPP byte wide address and data bus.

I This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP).

I This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer.

O This signal is active low. It is used to denote data read or write operation.

O This signal is active low. When driven active, the EPP device is reset to its initial operational mode.

O This signal is active low. It is used to denote address read or write operation.

I Same as SPP mode.

ADDRSTB nAddress

Strobe

PE Paper End

Same as SPP mode. nERR

Status

Error I Same as SPP mode.

Direction

O This output shows the direction of the data transfer on the parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress.

Note 1: SPP and EPP can use 1 common register.

Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle.

For correct EPP read cycles, PCD is required to be a low.

90

EXTENDED CAPABILITIES PARALLEL PORT

ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section.

• High performance half-duplex forward and reverse channel

• Interlocked handshake, for fast reliable transfer

• Optional single byte RLE compression for improved throughput (64:1)

Channel addressing for low-cost peripherals

Maintains link and data layer separation

Permits the use of active output drivers

Permits the use of adaptive signal timing

Vocabulary

The following terms are used in this document: assert: When a signal asserts it transitions to a

"true" state, when a signal deasserts it transitions to a "false" state. forward: Host to Peripheral communication. reverse: Peripheral to Host communication

Pword: A port word; equal in size to the width of the ISA interface. For this implementation,

PWord is always 8 bits.

1 A high level.

0 A low level.

These terms may be considered synonymous:

• PeriphClk,

• HostAck,

Busy

• nAckReverse,

Select nFault nInit

• ECPMode, nStrobe

Reference Document: IEEE 1284 Extended

Capabilities Port Protocol and ISA Interface

Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft.

The bit map of the Extended Parallel Port registers is:

D7 D6 D5 D4 D3 D2 D1 D0 Note ecpAFifo Addr/RLE Address or RLE field 2 cFifo ecpDFifo

Parallel Port Data FIFO

ECP Data FIFO

2

2

Parallel Port DMA

Note 1: These registers are available in all modes.

Note 2: All FIFOs use one common 16 byte FIFO.

Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration

Registers.

91

ISA IMPLEMENTATION STANDARD

This specification describes the standard ISA interface to the Extended Capabilities Port (ECP).

All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the

IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14,

1993. This document is available from Microsoft.

Description

The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any

"protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.

Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement.

The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed.

The port also supports run length encoded (RLE) decompression (required) in hardware.

Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the

RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional.

92

NAME TYPE

Table 36 - ECP Pin Descriptions

DESCRIPTION

nStrobe

PData 7:0 nAck

PeriphAck (Busy)

PError

(nAckReverse)

Select nAutoFd

(HostAck) nFault

(nPeriphRequest) nInit nSelectIn

O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy).

I/O Contains address or data or RLE data.

I Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse.

I This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction.

I Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest.

The host relies upon nAckReverse to determine when it is permitted to drive the data bus.

I Indicates printer on line.

O Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase.

I Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU.

O Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP

Mode and HostAck is low and nSelectIn is high.

O Always deasserted in ECP mode.

93

Register Definitions

The register definitions are based on the standard

IBM addresses for LPT. All of the standard printer ports are supported. The additional registers avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the attach to an upper bit decode of the standard LPT port definition to ecr. The table below lists these dependencies.

Operation of the devices in modes other that those specified is undefined.

Table 37 - ECP Register Definitions

NAME ADDRESS (Note 1) ECP MODES FUNCTION

data +000h R/W 000-001 Data Register ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA

+000h R/W

+001h R/W

+002h R/W

+400h R/W

+400h R/W

+400h R/W

+400h R

011

All

All

010

011

110

111

ECP FIFO (Address)

Status Register

Control Register

Parallel Port Data FIFO

ECP FIFO (DATA)

Test FIFO

Configuration Register A cnfgB +401h R/W 111 Configuration Register B ecr +402h R/W All Extended Control Register

Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers.

Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.

Table 38 - Mode Descriptions

MODE DESCRIPTION*

001 PS/2 Parallel Port mode

010 Parallel Port Data FIFO mode

011 ECP Parallel Port mode

100 EPP mode (If this option is enabled in the configuration registers)

101 Reserved

*Refer to ECR Register Description

DATA and ecpAFifo PORT

ADDRESS OFFSET = 00H

94

Modes 000 and 001 (Data Port)

The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the nIOW input. The contents of this register are buffered

(non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU.

Mode 011 (ECP FIFO - Address/RLE)

A data byte written to this address is placed in the

FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is ony defined for the forward direction

(direction is 0). Refer to the ECP Parallel Port

Forward Timing Diagram, located in the Timing

Diagrams section of this data sheet .

DEVICE STATUS REGISTER (dsr)

ADDRESS OFFSET = 01H

The Status Port is located at an offset of '01H' from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the

Printer Status Register these bits are a low level.

The bits of the Status Port are defined as follows:

BIT 3 nFault

The level on the nFault input is read by the CPU as bit 3 of the Device Status Register.

BIT 4 Select

The level on the Select input is read by the CPU as bit 4 of the Device Status Register.

BIT 5 PError

The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer

Status Register.

BIT 6 nAck

The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.

BIT 7 nBusy

The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status

Register.

95

DEVICE CONTROL REGISTER (dcr)

ADDRESS OFFSET = 02H

The Control Register is located at an offset of

'02H' from the base address. The Control

Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.

BIT 0 STROBE - STROBE

This bit is inverted and output onto the nSTROBE output.

BIT 1 AUTOFD - AUTOFEED

This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed.

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without inversion.

BIT 3 SELECTIN

This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected.

BIT 4 ackIntEn - INTERRUPT REQUEST

ENABLE

The interrupt request enable bit when set to a high

level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation,

Interrupts.

BIT 5 DIRECTION

If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read).

BITS 6 and 7 during a read are a low level, and cannot be written.

cFifo (Parallel Port Data FIFO)

ADDRESS OFFSET = 400h

Mode = 010

Bytes written or DMAed from the system to this

FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port

protocol. Transfers to the FIFO are byte aligned.

This mode is only defined for the forward direction.

ecpDFifo (ECP Data FIFO)

ADDRESS OFFSET = 400H

Mode = 011

Bytes written or DMAed from the system to this

FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the

FIFO are byte aligned.

Data bytes from the peripheral are read under automatic hardware handshake from ECP into this

FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.

tFifo (Test FIFO Mode)

ADDRESS OFFSET = 400H

Mode = 110

Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines.

The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again.

The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics.

The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits.

The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to

0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.

96

The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.

Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written.

cnfgA (Configuration Register A)

ADDRESS OFFSET = 400H

Mode = 111

This register is a read only register. When read,

10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte)

cnfgB (Configuration Register B)

ADDRESS OFFSET = 401H

Mode = 111

BIT 7 compress

This bit is read only. During a read it is a low level.

This means that this chip does not support hardware RLE compression. It does support hardware de-compression!

BIT 6 intrValue

Returns the value on the ISA IRq line to determine possible conflicts.

BITS [5:3] Parallel Port IRQ (read-only)

Refer to Table 39B.

BITS [2:0] Parallel Port DMA (read-only)

Refer to Table 39C.

ecr (Extended Control Register)

ADDRESS OFFSET = 402H

Mode = all

This register controls the extended ECP parallel port functions.

BITS 7,6,5

These bits are Read/Write and select the Mode.

BIT 4 nErrIntrEn

Read/Write (Valid only in ECP Mode)

1: Disables the interrupt generated on the asserting edge of nFault.

0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr.

BIT 3 dmaEn

Read/Write

1: Enables DMA (DMA starts when serviceIntr is

0).

0: Disables DMA unconditionally.

BIT 2 serviceIntr

Read/Write

1: Disables DMA and all of the service interrupts.

0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt. case dmaEn=1:

During DMA (this bit is set to a 1 when terminal count is reached). case dmaEn=0 direction=0:

This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the

FIFO. case dmaEn=0 direction=1:

This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.

BIT 1 full

Read only

1: The FIFO cannot accept another byte or the

FIFO is completely full.

0: The FIFO has at least 1 free byte.

BIT 0 empty

Read only

1: The FIFO is completely empty.

0: The FIFO contains at least 1 byte of data.

97

Table 39A - Extended Control Register

R/W MODE

000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode.

001: PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull).

010: Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the

FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).

011: ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups

(push-pull).

100: Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register L3-CRF0. All drivers have active pull-ups (push-pull).

101: Reserved

110: Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull).

111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and

0x401. All drivers have active pull-ups (push-pull).

Table 39B Table 39C

IRQ SELECTED

CONFIG REG B

BITS 5:3

15 110

DMA SELECTED

CONFIG REG B

BITS 2:0

3 011

14 101

11 100

10 011

2 010

1 001

9 010

7 001

5 111

All Others 000

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OPERATION

Mode Switching/Software Control

Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001).

Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase

(modes 011 or 010).

Setting the mode to 011 or 010 will cause the hardware to initiate data transfer.

If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or

001 it can only be switched into mode 000 or 001.

The direction can only be changed in mode 001.

Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above.

ECP Operation

Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000.

After negotiation, it is necessary to initialize some of the port bits. The following are required:

Set Direction = 0, enabling the drivers.

Set strobe = 0, causing the nStrobe signal to default to the deasserted state.

• Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.

Set mode = 011 (ECP Mode)

ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively.

Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction.

The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty.

ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000.

Termination from ECP Mode

Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction.

99

Command/Data

ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands.

When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low.

The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address.

When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low.

The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware.

Table 40 -

Forward Channel Commands (HostAck Low)

Reverse Channel Commands (PeripAck Low)

D7 D[6:0]

0

1

Run-Length Count (0-127) (mode

0011 0X00 only)

Channel Address (0-127)

Data Compression

The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.

Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the

RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the

100 subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided.

Pin Definition

The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes.

ISA Connections

The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary.

(The PWord value can be obtained by reading

Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals.

Interrupts

The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed

I/O if the number of bytes removed or added from/to the

FIFO does not cross the threshold.

The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert.

An interrupt is generated when:

1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC is received.

2. For Programmed I/O: direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. direction is 1 and there are readIntrThreshold or more bytes in the

FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO.

3. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from

1 to 0 and nFault is asserted.

4. When ackIntEn is 1 and the nAck signal transitions from a low to a high.

FIFO Operation

The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O

(non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel

Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or PDRQ depending on the selection of DMA or

Programmed I/O mode.

The following paragraphs detail the operation of the FIFO flow control. In these descriptions,

<threshold> ranges from 1 to 16. The parameter

FIFOTHR, which the user programs, is one less and ranges from 0 to 15.

A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests.

DMA TRANSFERS

DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by activating the PDRQ pin. The

DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for more than 32 DMA cycles in a row.

The FIFO is enabled directly by asserting nPDACK and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a TC.)

DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by

101

enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.

DMA Mode - Transfers from the FIFO to the

Host

(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.)

The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the

FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes inactive after nPDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as soon as there is one byte in the FIFO. If PDRQ goes inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and serviceIntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to prevent an unwanted cycle).

Programmed I/O Mode or Non-DMA Mode

The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O.

Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode.

Programmed I/O transfers are to the ecpDFifo at

400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0.

The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.

Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.

Programmed I/O - Transfers from the FIFO to

the Host

In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold =(16-<threshold>) data bytes in

FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The PINT pin can be used for interrupt-driven systems. The host must respond to the request by reading data from the FIFO.

This process is repeated until the last byte is transferred out of the FIFO. If at this time the

FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-

<threshold>) bytes may be read from the FIFO in a single burst.

102

Programmed I/O - Transfers from the Host to

the FIFO

In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the

FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read.

Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16-<threshold>) free bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request by writing data to the FIFO.

If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the

FIFO.

103

PARALLEL PORT FLOPPY DISK CONTROLLER

The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available.

2. Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1

There are two modes of operation, PPFD1 and

PPFD2. These modes can be selected in the

Parallel Port Mode Register, as defined in the

Parallel Port Mode Register, Logical Device 3, at

0xF1. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on the parallel port pins.

When the PPFDC is selected the following pins are set as follows:

SLCT = 0, nACK = 1, nERR = 1

The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive select register:

1. nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1.

2. If PPFDx is selected, then the parallel port

2. PDRQ: not ECP = high-Z, ECP & dmaEn = 0,

ECP & not dmaEn = high-Z

3. PINTR: not active, this is hi-Z or Low depending on settings.

Note: nPDACK, PDRQ and PINTR refer to the can not be used as a parallel port until

"Normal" mode is selected.

The FDC signals are muxed onto the Parallel Port pins as shown in Table 42. nDACK, DRQ and IRQ chosen for the parallel port.

The following parallel port pins are read as follows by a read of the parallel port register:

1. Data Register (read) = last Data Register

(write)

For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port must function independently of the state of the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the multiplexed FDD interface should function normally regardless of the Parallel Port Power control, CR22.3. Table

41 illustrates this functionality.

TABLE 41 - MODIFIED PARALLEL PORT FDD CONTROL

PARALLEL

PORT

POWER

PARALLEL PORT FDC

CONTROL

PARALLEL PORT

FDC STATE

PARALLEL PORT

STATE

CR22.3 LD3:CRF1.1 LD3:CRF1.0

1 0 0 OFF ON

0 0 0 OFF OFF

X 1 X ON OFF

X 1 (NOTE

1

)

NOTE

1

: The Parallel Port Control register reads as “Cable Not Connected” when the Parallel Port FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1.

104

CONNECTOR

PIN #

1

QFP

CHIP PIN #

83

Table 42 - FDC Parallel Port Pins

SPP MODE PIN DIRECTION FDC MODE

nSTROBE I/O (nDS0)

PIN DIRECTION

I/(O) Note1

7 73 - -

8 74 PD6 I/O (nMTR0) I/(O) Note1

9 75 - -

12 78 PE I nWDATA O

Note 1: These pins are outputs in mode PPFD2, inputs in mode PPFD1.

105

POWER MANAGEMENT

Power management capabilities are provided for the following logical devices: floppy disk, UART 1,

UART 2 and the parallel port. For each logical device, two types of power management are provided; direct powerdown and auto powerdown.

FDC Power Management

Direct power management is controlled by CR22.

Refer to CR22 for more information.

Auto Power Management is enabled by CR23-B0.

When set, this bit allows FDC to enter powerdown when all of the following conditions have been met:

1. The motor enable pins of register 3F2H are inactive (zero).

2. The part must be idle; MSR=80H and INT = 0

(INT may be high even if MSR = 80H due to polling interrupts).

3. The head unload timer must have expired.

4. The Auto powerdown timer (10msec) must have timed out.

An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met.

Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown.

DSR From Powerdown

If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective.

Wake Up From Auto Powerdown

If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers.

If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the

RESET_DRV pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part:

1. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part).

2. A read from the MSR register.

3. A read or write to the Data register.

Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied.

106

Register Behavior

Table 43 illustrates the AT and PS/2 (including

Model 30) configuration registers available and the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 43 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it.

Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens.

Accessing the part during powerdown may cause an increase in the power consumption by the part.

The part will revert back to its low power mode when the access has been completed.

Pin Behavior

The FDC37M81x is specifically designed for systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important.

The pins of the FDC37M81x can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part.

System Interface Pins

Table 44 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Input pins are "Disabled" to prevent them from causing currents internal to the FDC37M81x when they have indeterminate input values.

107

Table 43 - PC/AT and PS/2 Available Registers

AVAILABLE

BASE + ADDRESS PC-AT PS/2 (MODEL 30) ACCESS PERMITTED

Access to these registers DOES NOT wake up the part

00H ---- SRA

01H ---- SRB

02H DOR (1) DOR (1)

R

R

R/W

03H --- ---

04H DSR (1) DSR (1)

06H --- ---

07H DIR DIR

07H CCR CCR

Access to these registers wakes up the part

04H MSR MSR

---

W

---

R

W

R

05H Data Data R/W

Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part.

108

Table 44 - State of System Pins in Auto Powerdown

SYSTEM PINS STATE IN AUTO POWERDOWN

INPUT PINS nIOR Unchanged nIOW Unchanged

SA[0:9] Unchanged

SD[0:7] Unchanged

RESET_DRV Unchanged

DACKx Unchanged

TC Unchanged

OUTPUT PINS

SD[0:7] Unchanged

109

FDD Interface Pins

All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 45 depicts the state of the floppy disk drive interface pins in the powerdown state.

Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown

FDD PINS STATE IN AUTO POWERDOWN

INPUT PINS nRDATA Input nWPROT Input nTRK0 Input nINDEX Input nDSKCHG Input

OUTPUT PINS nMTR0 Tristated nDS0 Tristated nDIR Active nSTEP Active nWDATA Tristated nWGATE Tristated nHDSEL Active

DRVDEN[0:1] Active

110

UART Power Management

Direct power management is controlled by CR22.

Refer to CR22 for more information. Auto Power

Management is enabled by CR23-B4 and B5.

When set, these bits allow the following auto power management operations:

1. The transmitter enters auto powerdown when the transmit buffer and shift register are empty.

2. The receiver enters powerdown when the following conditions are all met:

A. Receive FIFO is empty

B. The receiver is waiting for a start bit.

Note: While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes.

Exit Auto Powerdown

The transmitter exits powerdown on a write to the

XMIT buffer. The receiver exits auto powerdown when RXDx changes state.

Parallel Port

Direct power management is controlled by CR22.

Refer to CR22 for more information.

Auto Power Management is enabled by CR23-B3.

When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used.

The EPP logic is in powerdown under any of the following conditions:

1. EPP is not enabled in the configuration registers.

2. EPP is not selected through ecr while in ECP mode.

The ECP logic is in powerdown under any of the following conditions:

1. ECP is not enabled in the configuration registers.

2 SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode.

Exit Auto Powerdown

The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers.

111

SERIAL IRQ

The FDC37M81x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.

Timing Diagrams for SER_IRQ Cycle

A) Start Frame timing with source sampled a low pulse on IRQ1

SL or

H

START FRAME

H

IRQ0 FRAME IRQ1 FRAME

R T S R T S R T

IRQ2 FRAME

S R T

PCI_CLK

SER_IRQ

START

1

Drive Source

IRQ

Host Controller None IRQ1 None

Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample

Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design.

B) Stop Frame Timing with Host using 17 SER_IRQ sampling period.

IRQ14 IRQ15

FRAME

S R T S

FRAME

R T

IOCHCK#

FRAME

S R T I

2

STOP FRAME

H R T

NEXT CYCLE

PCI_CLK

SER_IRQ

STOP

1

START

3

Driver

None IRQ15 None Host Controller

Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle

Note 1: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.

Note 2: There may be none, one or more Idle states during the Stop Frame.

Note 3: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turnaround clock of the Stop Frame.

112

SER_IRQ Cycle Control

There are two modes of operation for the

SER_IRQ Start Frame.

1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is

Idle between Stop and Start Frames. The

SER_IRQ is Active between Start and Stop

Frames. This mode of operation allows the

SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.

Once a Start Frame has been initiated the Host

Controller will take over driving the SER_IRQ low in the next clock and will continue driving the

SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the

Host Controller will drive the SER_IRQ back high for one clock, then tri-state.

Any SER_IRQ Device (i.e., The FDC37M81x) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start

Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ

Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle.

2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update

IRQ/Data line information. All other SER_IRQ agents become passive and may not initiate a

Start Frame. SER_IRQ will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ or the Host Controller can operate

SER_IRQ in a continuous mode by initiating a

Start Frame at the end of every Stop Frame.

An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ

bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle’s

mode.

SER_IRQ Data Frame

Once a Start Frame has been initiated, the

FDC37M81x will watch for the rising edge of the

Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and

Turn-around phase. During the Sample phase the FDC37M81x must drive the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high,

SER_IRQ must be left tri-stated. During the

Recovery phase the FDC37M81x must drive the

SERIRQ high, if and only if, it had driven the

SER_IRQ low during the previous Sample

Phase. During the Turn-around Phase the

FDC37M81x must tri-state the SERIRQ. The

FDC37M81x will drive the SER_IRQ line low at the appropriate sample point if its associated

IRQ/Data line is low, regardless of which device initiated the Start Frame.

The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 =

17th clock after the rising edge of the Start

Pulse).

113

SER_IRQ PERIOD

SER_IRQ Sampling Periods

SIGNAL SAMPLED # OF CLOCKS PAST START

1 Not 2

2 IRQ1 5

3 nSMI/IRQ2 8

4 IRQ3 11

5 IRQ4 14

6 IRQ5 17

7 IRQ6 20

8 IRQ7 23

9 IRQ8 26

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38

14 IRQ13 41

15 IRQ14 44

16 IRQ15 47

The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can also be used for the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the

SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2.

SER_IRQ Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5

(Ser Port 2), and 7 (KBD) shall have IRQ13 as a choice for their primary interrupt.

The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2.

114

Stop Cycle Control

Once all IRQ/Data Frames have completed the

Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host

Controller can initiate the Stop Frame. A Stop

Frame is indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is the Quiet mode; and any

SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ

Cycle’s sampled mode is the Continuos mode; and only the Host Controller may initiate a Start

Frame in the second clock or more after the rising edge of the Stop Frame’s pulse.

Latency

Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum

Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84

μS with a 25MHz

PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.

EOI/ISR Read Latency

Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated.

The recommended solution is to delay EOIs and

ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of order.

AC/DC Specification Issue

All SER_IRQ agents must drive / sample

SER_IRQ synchronously related to the rising edge of PCI bus clock. SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state.

Reset and Initialization

The SER_IRQ bus uses RESET_DRV as its reset signal. The SER_IRQ pin is tri-stated by all agents while RESET_DRV is active. With reset,

SER_IRQ Slaves are put into the (continuous)

IDLE mode. The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host

Controller’s responsibility to provide the default values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For

SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first.

This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes.

115

GP INDEX REGISTERS

The Watchdog Timer Control, SMI Enable and registers WDT_CTRL, SMI Enable and SMI Status

SMI Status Registers can be accessed by the host when the chip is in the normal run mode if CR03

Bit[7]=1. The host uses GP Index and Data register to access these registers. The Power on default GP Index and Data registers are 0xEA and

0xEB respectively. In configuration mode the GP

Index address may be programmed to reside on addresses 0xE0, 0xE2, 0xE4 or 0xEA. The GP

Registers.

To access these registers when in normal (run) mode, the host should perform an IOW of the

Register Index to the GP Index register (at 0xEX) to select the Register and then read or write the

Data register (at Index+1) to access the register.

Data address is automatically set to the Index address + 1. Upon exiting the configuration mode the new GP Index and Data registers are used to access

The WDT_CTRL, SMI Enable and SMI Status registers can also be accessed by the host when in the configuration state through Logical Device 8.

Table 46A - GP Index and Data Register

REGISTER ADDRESS (R/W) NORMAL (RUN) MODE

GP Index

GP Data

0xE0, E2, E4, EA 0x01-0x0F

Index address + 1 Access to Watchdog Timer

Control, SMI Enable and

SMI Status Registers (see

Table 46B)

116

Table 46B - Index and Data Register Normal (Run) Mode

INDEX NORMAL (RUN) MODE

0x01 Reserved

0x02 Reserved

0x03 Access to Watchdog Timer Control (L8 - CRF4)

0x04 Reserved

0x05 Reserved

0x06 Reserved

0x07 Reserved

0x08 Reserved

0x09 Reserved

0x0A Reserved

0x0B Reserved

0x0C Access to SMI Enable Register 1 (L8-CRB4)

0x0D

0x0E

0x0F

Access to SMI Enable Register 2 (L8-CRB5)

Access to SMI Status Register 1 (L8-CRB6)

Access to SMI Status Register 2 (L8-CRB7)

Note 1: These registers can also be accessed through the configuration registers at L8

- CRxx shown in the table above.

117

WATCH DOG TIMER

The FDC37M81x contains a Watch Dog Timer 0x201 (an external Joystick Port). The effect on

(WDT). The Watch Dog Time-out status bit may be mapped to an interrupt through the WDT_CFG

Configuration Register.

The FDC37M81x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are selected via bit[7] of the

WDT_TIMEOUT register (LD8:CRF1.7). The WDT time-out value is set through the WDT_VAL

Configuration register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Configuration

Register. Note: Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU.

There are three system events which can reset the

WDT, these are a Keyboard Interrupt, a Mouse

Interrupt, or I/O reads/writes to address the WDT for each of these system events may be individually enabled or disabled through bits in the

WDT_CFG configuration register. When a system event is enabled through the WDT_CFG register, the occurrence of that event will cause the WDT to reload the value stored in WDT_VAL and reset the

WDT time-out status bit if set. If all three system events are disabled the WDT will inevitably time out.

The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the

Time-out status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG

Configuration Register. When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status bit.

The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force

WD Time-out) Configuration Register. Writing a

"1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watch Dog

Status). Bit 2 of the WDT_CTRL is self-clearing.

118

8042 KEYBOARD CONTROLLER DESCRIPTION

The FDC37M81x is a Super I/O and Universal The Universal Keyboard Controller uses an 8042

Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Super I/O supports a Floppy

Disk Controller, two 16550 type serial ports one

ECP/EPP Parallel Port. microcontroller CPU core. This section concentrates on the FDC37M81x enhancements to the 8042. For general information about the

8042, refer to the "Hardware Description of the

8042" in the 8-Bit Embedded Controller Handbook.

8042A

P27

P10

P26

TST0

P23

TST1

P22

P11

LS05

Keyboard and Mouse Interface

KIRQ is the Keyboard IRQ

MIRQ is the Mouse IRQ

Port 21 is used to create a GATEA20 signal from the FDC37M81x.

KDAT

KCLK

MCLK

MDAT

119

KEYBOARD ISA INTERFACE

The FDC37M81x ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW register, and Output Data register. Table 47 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs. and the Status register, Input Data

Table 47 - ISA I/O Address Map

ISA ADDRESS nIOW nIOR BLOCK FUNCTION (NOTE 1)

0x60 0

1

1

0

KDATA

KDATA

Keyboard Data Write (C/D=0)

Keyboard Data Read

0x64 0 1 KDCTL Keyboard Command Write (C/D=1)

1 0 KDCTL Keyboard Status Read

Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data

Read.

120

Keyboard Data Write

This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set.

Keyboard Data Read

This is an 8 bit read only register. If enabled by

"ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or

AUXOBF1 must be cleared in software.

Keyboard Command Write

This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set.

Keyboard Status Read

This is an 8 bit read only register. Refer to the description of the Status Register for more information.

CPU-to-Host Communication

The FDC37M81x CPU can write to the Output

Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the

Status register. See Table 48.

8042 INSTRUCTION

Table 48 - Host Interface Flags

FLAG

OUT DBB Set OBF, and, if enabled, the KIRQ output signal goes high

Host-to-CPU Communication

The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register.

When bit 3 is "1", the CPU interprets the register contents as a command. When bit 3 is "0", the

CPU interprets the register contents as data.

During a host write operation, bit 3 is set to "1" if

SA2 = 1 or reset to "0" if SA2 = 0.

KIRQ

If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The

KIRQ signal can be connected to system interrupt to signify that the FDC37M81x CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.)

If "EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to

P24 forces KIRQ low; a high forces KIRQ high.

MIRQ

If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ.

The MIRQ signal can be connected to system interrupt to signify that the FDC37M81x CPU has read the DBB register.

If "EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces

MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support).

Gate A20

A general purpose P21 is used as a software controlled Gate A20 or user defined output.

EXTERNAL KEYBOARD AND MOUSE

INTERFACE

Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply

121

PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the

FDC37M81x provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse.

The FDC37M81x has four high-drive, open-drain output, bidirectional port pins that can be used for external serial interfaces, such as ISA external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10.

P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to

P11. NOTE: External pull-ups may be required.

KEYBOARD POWER MANAGEMENT

The keyboard provides support for two powersaving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power down mode the clock to the 8042 is stopped.

Soft Power Down Mode

This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master

CPU. If this mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the next instruction is executed.

If it is exited using RESET then a normal reset sequence is initiated and program execution starts from program memory location 0.

Hard Power Down Mode

This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell. When either RESET is driven active or a data byte is written to the

DBBIN register by a master CPU, this mode will be

122 exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above.

INTERRUPTS

The FDC37M81x provides the two 8042 interrupts.

IBF and the Timer/Counter Overflow.

MEMORY CONFIGURATIONS

The FDC37M81x provides 2K of on-chip ROM and

256 bytes of on-chip RAM.

Register Definitions

Host I/F Data Register

The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the

OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the

Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information.

Host I/F Status Register

The Status register is 8 bits wide. Table 49 shows the contents of the Status register.

Table 49 - Status Register

D7 D6 D5 D4 D3 D2 D1 D0

UD UD UD UD C/D UD IBF OBF

Status Register

This register is cleared on a reset. This register is read-only for the Host and read/write by the

FDC37M81x CPU.

UD Writable by FDC37M81x CPU. These bits are user-definable.

C/D (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2

= 0.

IBF (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the FDC37M81x CPU's nIBF (MIRQ) interrupt if enabled. When the FDC37M81x CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal.

Table 50 - Resets

OBF (Output Buffer Full) - This flag is set to whenever the FDC37M81x CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset.

EXTERNAL CLOCK SIGNAL

The FDC37M81x Keyboard Controller clock source is a 12 MHz clock generated from a 14.318

MHz clock. The reset pulse must last for at least

24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.

DEFAULT RESET CONDITIONS

The FDC37M81x has one source of reset: an external reset via the RESET_DRV pin. Refer to

Table 50 for the effect of each type of reset on the internal registers.

DESCRIPTION HARDWARE RESET (RESET_DRV)

Host I/F Data Reg

Host I/F Status Reg

N/A: Not Applicable

N/A

00H

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GATEA20 AND KEYBOARD RESET

The FDC37M81x provides two options for

GateA20 and Keyboard Reset: 8042 Software

Generated GateA20 and KRESET and Port 92

Fast GateA20 and KRESET.

PORT 92 FAST GATEA20 AND KEYBOARD

RESET

Port 92 Register

This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20

Register (Logical Device 7, 0xF0) set to 1.

This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.

Location 92h

Default Value 24h

Attribute Read/Write

Port 92 Register

Bit Function

7:6 Reserved. Returns 00 when read

5 Reserved. Returns a 1 when read

4

3

2

1

0

Reserved. Returns a 0 when read

Reserved. Returns a 0 when read

Reserved. Returns a 1 when read

ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.

Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address

Mode. This provides a faster means of reset than is provided by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of

500 ns. Before another nALT_RST pulse can be generated, this bit must be written back to a 0.

8042

P21 nGATEA20

ALT_A20

System nA20M

0 0 0

0 1 1

1 0 1

1 1 1

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Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92

Register causes this signal to pulse low for a minimum of 6µs, after a delay of a minimum of

14µs. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port

92 Register is set to 0).

If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92 Register and this pulse is

AND’ed with the pulse generated from the 8042.

This pulse is output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration.

6us

8042

P20

KRST

P92

KRST_GA20

Bit 2

Bit 0

Pulse

Gen

Note: When Port 92 is disabled, writes are ignored and reads return undefined values.

nALT_RST

6us

KRESET Generation

KBDRST

125

Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low.

ALT_A20 low drives nA20M to the CPU low, if

A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low.

8042 P12, P16 and P17 Functions

8042 functions P12, P16 and P17 are implemented as in a true 8042 part. Reference the 8042 spec for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within

20-30nsec. After 500nsec (six 8042 clocks), the port enable goes away and for P12, P16 the internal 90µA pull-up maintains the output signal as 1, and for P17 an external pull-up maintains the output signal as 1.

In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external pull-up can pull the pin high, and the pin can be shared i.e., P12 and nSMI can be externally tied together.

In 8042 mode, the pins cannot be programmed as input nor inverted through the GP configuration registers.

126

0ns 250ns 500ns

CLK

AEN nAEN

64=I/O Addr n64 nIOW nA

DD1 nDD1 nCNTL nIOW' nIOW+n64

AfterD1 nAfterD1

60=I/O Addr n60 nIOW+n60=B nAfterD1+B

D[1]

GA20

Gate A20 Turn-On Sequence Timing

When writing to the command and data port with hardware speedup, the IOW timing shown in the figure titled “IOW Timing for Port 92” in the Timing Diagrams Section is used. This setup time is only required to be met when using hardware speedup; the data must be valid a minimum of 0 nsec from the leading edge of the write and held throughout the entire write cycle.

127

Latches On Keyboard And Mouse IRQs

The implementation of the latches on the keyboard and mouse interrupts is shown below.

8042

KLATCH Bit

KINT

VCC

D Q

CLR

KINT new

RD 60

FIGURE 2 – KEYBOARD LATCH

128

8042

MLATCH Bit

MINT

VCC

D Q

CLR

RD 60

MINT new

FIGURE 3 – MOUSE LATCH

The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.

These bits are defined as follows:

Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched

MINT (default), 1=MINT is the latched 8042 MINT.

Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched

KINT (default), 1=KINT is the latched 8042 KINT.

See the Configuration section for description on these registers.

Keyboard and Mouse PME Generation

The FDC37M81x sets the associated PME Status bits when the following conditions occur:

Active Edge on Keyboard Data Signal (KDAT)

Active Edge on Mouse Data Signal (MDAT)

These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global PME_EN bit are set. Refer to the PME Support section for more details on the PME interface logic and refer to the Configuration section for details on the PME Status and Enable registers.

When using the keyboard and mouse for wakeup, it may be necessary to isolate the keyboard and mouse signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is due to the fact that the normal operation of the 8042 can prevent the system from

129

entering or exiting a sleep state or trigger false PME events. The FDC37M81x has “isolation” bits for the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but block the keyboard clock and data signals and the mouse clock and data signals from the 8042. These bits may be used when it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state.

See the SMSC Application Note titled “Using the Enhanced Keyboard and Mouse Wakeup Feature in

SMSC Super I/O Parts” for more information.

The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device 7,

Register 0xF0 (KRST_GA20) and are defined as follows:

Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal to the mouse wakeup (PME) logic.

1= Block mouse clock and data signals into 8042

0= Do not block mouse clock and data signals into 8042

Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal to the keyboard wakeup (PME) logic.

1= Block keyboard clock and data signals into 8042

0= Do not block keyboard clock and data signals into 8042

When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon exiting the sleep state. If either of the isolation bits is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this may produce undesired results.

It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go inactive (S1, S2).

130

SYSTEM MANAGEMENT INTERRUPT (SMI)

The FDC37M81x implements a group nSMI output pin. The System Management Interrupt is

SMI Enable Registers

a non-maskable interrupt with the highest priority level used for transparent power management.

The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip. The interrupts are enabled onto the group nSMI output via the SMI Enable

Registers 1 and 2. The nSMI output is then enabled onto the group nSMI output frame in the

Serial IRQ stream via bit[6] in the SMI Enable

Register 2.

The logic equation for the nSMI output is as follows: nSMI = (EN_PINT and IRQ_PINT) or

(EN_U2INT and IRQ_U2INT) or

(EN_U1INT and IRQ_U1INT) or

(EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and

IRQ_MINT) or (EN_KINT and

IRQ_KINT) or (EN_IRINT and

IRQ_IRINT)

REGISTERS

The following registers can be accessed when in configuration mode at Logical Device 8,

Registers B4-B7 and when not in configuration they can be accessed through the Index and

Data Register (refer to Table 46B).

SMI Enable Register 1

(Configuration Register B4, Logical Device 8)

This register is used to enable the different interrupt sources onto the group nSMI output.

SMI Enable Register 2

(Configuration Register B5, Logical Device 8)

This register is used to enable additional interrupt sources onto the group nSMI output. This register is also used to enable the group nSMI output frame onto the nSMI Serial IRQ stream and the routing of 8042 P12 internally to nSMI.

SMI Status Registers

SMI Status Register 1

(Configuration Register B6, Logical Device 8)

This register is used to read the status of the SMI input events. Note: The status bit gets set whether or not the interrupt is enabled onto the group SMI output.

SMI Status Register 2

(Configuration Register B7, Logical Device 8)

131

PME SUPPORT

The FDC37M81x offers support for ACPI power source has asserted the nIO_PME signal. The management events (PMEs). A power management event is requested by an ACPI function via the assertion of the nIO_PME signal.

In the FDC37M81x, only active transitions on the ring indicator inputs nRI1 and nRI2, active keyboard-data edges (high to low) and active mouse-data edges (high to low) can assert the nIO_PME signal. nIO_PME is an active low open-drain output. nIO_PME functionality is controlled by the configuration registers in logical device number eight. The PME Enable bit, PME_En,

LD8:CRC5.0, globally controls PME Wake-up events. When PME_En is inactive, the nIO_PME signal can not be asserted. When

PME_En is asserted, any wake source whose individual PME Wake Enable register bit,

LD8:CRC8, is asserted can cause nIO_PME to become asserted. The PME Wake Status register, LD8:CRC7, indicates which wake

PME Status bit, PME_Status, LD8:CRC6.0, is asserted by active transitions of PME Wake sources. PME_Status will become asserted independent of the state of the global PME enable, PME_En. Refer to the

CONFIGURATION section for further details.

The following pertains to the PME status bits for each event.

• The output of the status bit for each event is combined with the corresponding enable bit to set the PME status bit.

• The status bit for any pending events must be cleared in order to clear the PME_STS bit.

See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and mouse signals to generate a PME.

132

CONFIGURATION

The Configuration of the FDC37M81x is very configuration ports to initialize the logical devices flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The FDC37M81x is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the

FDC37M81x allows the BIOS to assign resources at POST. at POST. The INDEX and DATA ports are only valid when the FDC37M81x is in Configuration

Mode.

The SYSOPT pin is latched on the falling edge of the RESET_DRV or on Vcc Power On Reset to determine the configuration register's base address. The SYSOPT pin is used to select the

SYSTEM ELEMENTS

Primary Configuration Address Decoder

After a hard reset (RESET_DRV pin asserted) or

Vcc Power On Reset the FDC37M81x is in the

Run Mode with all logical devices disabled. The logical devices may be configured through two

CONFIG PORT's I/O address at power-up. Once powered up the configuration port base address can be changed through configuration registers

CR26 and CR27. The SYSOPT pin is a standard Configuration I/O Ports (INDEX and

DATA) by placing the FDC37M81x into

Configuration Mode. The BIOS uses these

PORT NAME

SYSOPT= 0

PULL-DOWN RESISTOR

(NOTE 1) hardware configuration pin which is shared

with the nRTS1 signal on pin 87. During reset this pin is a weak active low signal which sinks

30µA. Note: All I/O addresses are qualified with

AEN.

The INDEX and DATA ports are effective only when the chip is in the Configuration State.

SYSOPT= 1

10K PULL-UP

RESISTOR TYPE

CONFIG PORT (Note 2) 0x03F0 0x0370 Write

INDEX PORT (Note 2) 0x03F0 0x0370 Read/Write

DATA PORT

Note 1:

INDEX PORT + 1 Read/Write

If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use

Note 2: The configuration port base address can be relocated through CR26 and CR27.

Entering the Configuration State

The device enters the Configuration State when

Exiting the Configuration State

The device exits the Configuration State when the the following Config Key is successfully written to the CONFIG PORT.

Config Key = < 0x55 > following Config Key is successfully written to the

CONFIG PORT.

Config Key = < 0xAA>

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CONFIGURATION SEQUENCE

To program the configuration registers, the following sequence must be followed:

1. Enter Configuration Mode

2. Configure the Configuration Registers

3. Exit Configuration Mode.

Enter Configuration Mode

To place the chip into the Configuration State the

Config Key is sent to the chip's CONFIG PORT.

The config key consists of 0x55 written to the

CONFIG PORT. Once the configuration key is received correctly the chip enters into the

Configuration State (The auto Config ports are enabled).

Configuration Mode

The system sets the logical device information and activates desired logical devices through the

INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1.

The desired configuration registers are accessed in two steps: a. Write the index of the Logical Device Number

Configuration Register (i.e., 0x07) to the

INDEX PORT and then write the number of the desired logical device to the DATA PORT b. Write the address of the desired configuration register within the logical device to the INDEX

PORT and then write or read the configuration register through the DATA PORT.

Note: If accessing the Global Configuration

Registers, step (a) is not required.

Exit Configuration Mode

To exit the Configuration State the system writes

0xAA to the CONFIG PORT. The chip returns to the RUN State.

Note: Only two states are defined (Run and

Configuration). In the Run State the chip will always be ready to enter the Configuration State.

134

Programming Example

The following is an example of a configuration program in Intel 8086 assembly language.

;----------------------------.

; ENTER CONFIGURATION MODE |

;----------------------------'

MOV DX,3F0H

MOV AX,055H

OUT DX,AL

;----------------------------.

; CONFIGURE REGISTER CRE0, |

; LOGICAL DEVICE 8 |

;----------------------------'

MOV DX,3F0H

MOV AL,07H

OUT DX,AL ;Point to LD# Config Reg

MOV DX,3F1H

OUT DX,AL;Point to Logical Device 8

;

MOV DX,3F0H

MOV AL,E0H

OUT DX,AL ; Point to CRE0

MOV DX,3F1H

MOV AL,02H

OUT DX,AL ; Update CRE0

;-----------------------------.

; EXIT CONFIGURATION MODE |

;-----------------------------'

MOV DX,3F0H

MOV AX,0AAH

OUT DX,AL

135

Notes: 1. HARD RESET: RESET_DRV pin asserted

2. SOFT RESET: Bit 0 of Configuration Control register set to one

3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram)

Table 51 – FDC37M81x Configuration Registers Summary

INDEX TYPE

HARD

RESET

VCC

POR

SOFT

RESET

VTR

POR

CONFIGURATION REGISTER

GLOBAL CONFIGURATION REGISTERS

0x20

0x21

R

R

0x4D

Current Revision

Device ID - hard wired

Device Rev - hard wired

0x24 R/W 0x04 0x04

=0: 0xF0

Sysopt

=1: 0x70

=0: 0xF0

Sysopt

=1: 0x70

=0: 0x03

Sysopt

=1: 0x03

=0: 0x03

Sysopt

=1: 0x03

-

-

-

0x04 OSC

- Configuration Port Address Byte 0

- Configuration Port Address Byte 1

0x60,

0x61

LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)

R/W 0x03,

0xF0

0x03,

0xF0

0x03,

0xF0

0x03,

0xF0

Primary Base I/O Address

0xF1

0xF2

R/W

R/W

0x00

0xFF

0x00

0xFF

-

-

0x00 FDD Option Register

0xFF FDD Type Register

136

INDEX TYPE

HARD

RESET

VCC

POR

SOFT

RESET

VTR

POR

CONFIGURATION REGISTER

LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED)

LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED)

LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port)

0x60,

0x61

R/W 0x00, 0x00,

0x00 0x00

0x00,

0x00

0x00,

0x00

Primary Base I/O Address

0xF0

0xF1

0x60,

0x61

0xF0

0x60,

0x61

0x62,

0x63

0xF0

0xF1

0xF2

R/W

R/W

0x3C

0x00

0x3C

0x00

-

-

0x3C

0x00

Parallel Port Mode Register

Parallel Port Mode Register 2

LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1)

R/W 0x00,

0x00

0x00,

0x00

0x00,

0x00

0x00,

0x00

Primary Base I/O Address

R/W 0x00 0x00 - 0x00 Serial Port 1 Mode Register

LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2)

R/W 0x00,

0x00

R/W 0x00,

0x00

0x00,

0x00

0x00,

0x00

0x00,

0x00

0x00,

0x00

0x00,

0x00

0x00,

0x00

Primary Base I/O Address

Reserved

R/W

R/W

R/W

0x00

0x02

0x03

0x00

0x02

0x03

-

-

-

0x00 Serial Port 2 Mode Register

0x02 IR Options Register

0x03 IR Half Duplex Timeout

LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED)

LOGICAL DEVICE 7 CONFIGURATION REGISTERS (KEYBOARD)

0xF0

0xB4

0xB5

R/W 0x00 0x00 0x00 KRESET and GateA20 Select

LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O)

R/W

R/W

-

-

0x00

0x00

-

-

137

0x00 SMI Enable Register 1

0x00 SMI Enable Register 2

INDEX

0xB6

0xB7

0xC0

0xC1

0xC2

TYPE

R/W

R/W

R/W

R/W

R

HARD

RESET

-

-

0x02

0x01

-

VCC

POR

0x00

0x00

0x02

0x01

-

SOFT

RESET

-

-

-

-

-

VTR

POR

CONFIGURATION REGISTER

0x00 SMI Status Register 1

0x00 SMI Status Register 2

0x02 Pin Multiplex Controls

0x01 Force Disk Change

- Floppy Data Rate Select Shadow

0xC6 R/W-

CLEAR

0xC7 R/W-

CLEAR

0xC8 R/W

-

-

-

-

-

-

0x00 Register

0x00 Register

0x00 PME Wake Status Register

0x00 PME Wake Enable Register

0xF4 R/W

1

0x00

2

0x00 - WDT_CTRL

0xF6 :

FB

Note 1: This register contains some bits that are read or write only.

Note 2: Bit 0 is not cleared by HARD RESET.

Note 3: The Parallel Port interrupt defaults to ‘1’ when the Parallel Port activate bit is cleared. When the

Parallel Port is activated, PINT follows the nACK input.

138

Chip Level (Global) Control/Configuration

Registers[0x00-0x2F]

The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection.

All unimplemented registers and bits ignore writes and return zero when read.

The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode.

Table 52 - Chip Level Registers

REGISTER ADDRESS DESCRIPTION STATE

Chip (Global) Control Registers

Config Control

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

Index Address

Default = 0x03 on VCC POR, VTR

POR and HARD

RESET

0x01

0x02 W The hardware automatically clears this bit after the write, there is no need for software to clear the bits.

Bit 0 = 1: Soft Reset. Refer to the "Configuration

Registers" table for the soft reset value for each register.

0x03 R/W Bit[7]

= 1 Enable WDT_CTRL and SMI Enable and

SMI Status Register access when not in

= 0 configuration mode

Disable WDT_CTRL and SMI Enable and

SMI Status Register access when not in

Bits [6:2] configuration mode (Default)

Reserved - Writes are ignored, reads return 0.

Bits[1:0]

Sets GP index register address when in Run mode

(not in Configuration Mode).

= 11 0xEA (Default)

= 10 0xE4

= 01 0xE2

= 00 0xE0

0x04 - 0x06 Reserved - Writes are ignored, reads return 0.

C

Logical Device #

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

0x07 R/W A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note:

The Activate command operates only on the selected logical device.

C

139

Table 52 - Chip Level Registers

REGISTER ADDRESS DESCRIPTION

Card Level Reserved 0x08 - 0x1F Reserved - Writes are ignored, reads return 0.

Chip Level, SMSC Defined

Device ID

Hard wired

= 0x4D

Device Rev

Hard wired

= Current Revision

PowerControl

Default = 0x00. on VCC POR, VTR

POR, SOFT RESET and HARD RESET

Power Mgmt

Default = 0x00. on VCC POR, VTR

POR and HARD

RESET

0x21 R

0x22 R/W identification. Bits[7:0] = 0x4D when read.

A read only register which provides device revision information. Bits[7:0] = current revision when read.

Bit[0] FDC Power

Bit[1] Reserved

Bit[2] Reserved

Bit[3] Parallel Port Power

Bit[4] Serial Port 1 Power

Bit[5] Serial Port 2 Power

Bit[6] Reserved

Bit[7] Reserved

0x23 R/W Bit[0] FDC

Bit[1] Reserved

Bit[2] Reserved

Bit[3] Parallel Port

Bit[4] Serial Port 1

Bit[5] Serial Port 2

Bit[6:7] Reserved (read as 0)

= 0 Intelligent Pwr Mgmt off

= 1 Intelligent Pwr Mgmt on

STATE

C

C

C

C

140

Table 53 - Chip Level Registers

REGISTER ADDRESS

OSC

Default = 0x04, on

VCC POR, VTR

POR and HARD

RESET

0x24 R/W Bit[0] Reserved

Bit [1] PLL Control

DESCRIPTION

= 0 PLL is on (backward Compatible)

= 1 PLL is off

Bits[3:2] OSC

= 01 Osc is on, BRG clock is on.

= 10 Same as above (01) case.

= 00 Osc is on, BRG Clock Enabled.

= 11 Osc is off, BRG clock is disabled.

Bit [5:4] Reserved, set to zero

Bit [6] 16-Bit Address Qualification

= 0 12-Bit Address Qualification

= 1 16-Bit Address Qualification

Note: For normal operation, bit 6 should be set.

Bit[7] Reserved

0x25 Reserved - Writes are ignored, reads return 0. Chip Level

Vendor Defined

Configuration

Address Byte 0

Default

=0 x

F0 (Sysopt=0)

=0 x

70 (Sysopt=1) on VCC POR and

HARD RESET

Configuration

Address Byte 1

Default = 0x03 on VCC POR and

HARD RESET

Default = 0x00 on VCC POR and

Hard Reset

Chip Level

Vendor Defined

0x26

0x27

0x28

Bit[7:1] Configuration Address Bits [7:1]

Bit[0] = 0

See Note 1

Bit[7:0] Configuration Address Bits [15:8]

See Note 1

Bits[7:0] Reserved - Writes are ignored, reads return

0.

0x29 -0x2A Reserved - Writes are ignored, reads return 0.

STATE

C

C

C

141

Table 53 - Chip Level Registers

REGISTER ADDRESS

TEST 4

Default = 0x00, on

VCC POR and VTR

POR

TEST 5

Default = 0x00, on

VCC POR and

VTR POR

TEST 1

Default = 0x00, on

VCC POR and VTR

POR

0x2B R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.

0x2C R/W

DESCRIPTION

Bit[7] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results.

Bit[6] 8042 Reset:

1 = Put the 8042 into reset

0 = Take the 8042 out of reset

Bits[5:0] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results.

0x2D R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.

STATE

C

C

C

TEST 2

Default = 0x00, on

VCC POR and VTR

POR

0x2E R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.

C

TEST 3

Default = 0x00, on

VCC POR and VTR

POR

0x2F R/W Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.

C

Note 1: To allow the selection of the configuration address to a user defined location, these Configuration

Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address).

The configuration address is only reset to its default address upon a Hard Reset or Vcc POR.

Note: The default configuration address is either 3F0 or 370, as specified by the SYSOPT pin.

142

Logical Device Configuration/Control

each logical device and is selected with the Logical

Registers [0x30-0xFF]

Device # Register (0x07).

Used to access the registers that are assigned to each logical unit. This chip supports six logical units and has six sets of logical device registers.

The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT.

The six logical devices are Floppy, Parallel, Serial

1, Serial 2, Keyboard Controller, and Auxiliary_I/O.

The Logical Device registers are accessible only

A separate set (bank) of control and configuration registers exists for when the device is in the Configuration State. The logical register addresses are shown in the table below.

Table 54 - Logical Device Registers

LOGICAL DEVICE

REGISTER ADDRESS DESCRIPTION STATE

Activate (Note 1)

Default = 0x00 on VCC POR, VTR POR,

SOFT RESET and HARD

RESET

Logical Device Control

Memory Base Address

I/O Base Address

(Note 2)

(see Device Base I/O

Address Table)

Default = 0x00 on VCC POR, VTR POR,

SOFT RESET and HARD

RESET

(0x30) Bits[7:1] Reserved, set to zero.

Bit[0]

= 1 Activates the logical device currently selected through the Logical Device #

= 0 register.

Logical device currently selected is inactive

(0x31-0x37) Reserved - Writes are ignored, reads return 0.

(0x38-0x3f) Vendor Defined - Reserved - Writes are ignored, reads return 0.

(0x40-0x5F) Reserved - Writes are ignored, reads return 0.

(0x60-0x6F)

0x60,2,... = addr[15:8]

0x61,3,... = addr[7:0]

Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63.

Refer to Table 63 for the number of base address registers used by each device.

Unused registers will ignore writes and return zero when read.

C

C

C

C

C

143

Table 54 - Logical Device Registers

LOGICAL DEVICE

REGISTER

Interrupt Select

Defaults :

0x70 = 0x00 or 0X06

(Note 3) on VCC POR, VTR POR,

SOFT RESET and HARD

RESET

0x72 = 0x00, on VCC POR, VTR POR,

SOFT RESET and HARD

RESET

ADDRESS DESCRIPTION

(0x70,0x72) 0x70 is implemented for each logical device.

Refer to Interrupt Configuration Register description. Only the keyboard controller uses

Interrupt Select register 0x72. Unused register

(0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible).

STATE

C

DMA Channel Select

Default = 0x04 or 0X02

(Note 4) on VCC POR, VTR POR,

SOFT RESET and HARD

RESET

32-Bit Memory Space

Configuration

(0x71,0x73) Reserved - not implemented. These register locations ignore writes and return zero when read.

(0x74,0x75) Only 0x74 is implemented for FDC and Parallel port. 0x75 is not implemented and ignores writes and returns zero when read. Refer to

DMA Channel Configuration.

C

Logical Device

Logical Device

Configuration

(0x76-0xA8) Reserved - not implemented. These register locations ignore writes and return zero when read.

(0xA9-0xDF) Reserved - not implemented. These register locations ignore writes and return zero when read.

(0xE0-0xFE) Reserved - Vendor Defined (see SMSC defined Logical Device Configuration

Registers).

C

C

C

Note 1: A logical device will be active and powered up according to the following equation:

DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).

The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored.

144

Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical

Device I/O map, then read or write is not valid and is ignored.

Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.

Note 4: The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is

0x04.

Table 55 - I/O Base Address Configuration Register Description

LOGICAL

DEVICE

NUMBER

LOGICAL

DEVICE

REGISTER

INDEX

BASE I/O

RANGE

(NOTE 1)

FIXED

BASE OFFSETS

0x01 Reserved n/a

0x02 Reserved n/a

ON 8 BYTE BOUNDARIES n/a n/a

+1 : SRB

+2 : DOR

+3 : TDR

+4 : MSR/DSR

+5 : FIFO

+7 : DIR/CCR n/a n/a

Port

1

ON 4 BYTE BOUNDARIES

(EPP Not supported) or

[0x100:0x0FF8]

ON 8 BYTE BOUNDARIES

(all modes supported,

EPP is only available when the base address is on an 8byte boundary)

+1 : Status

+2 : Control

+3 : EPP Address

+4 : EPP Data 0

+5 : EPP Data 1

+6 : EPP Data 2

+7 : EPP Data 3

+400h : cfifo|ecpDfifo|tfifo |cnfgA

+401h : cnfgB

+402h : ecr

ON 8 BYTE BOUNDARIES

+1 : IER|MSB div

+2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LCR

+6 : MSR

+7 : SCR

2

ON 8 BYTE BOUNDARIES

+1 : IER|MSB div

+2 : IIR/FCR

+3 : LCR

+4 : MSR

+5 : LCR

+6 : MSR

+7 : SCR

145

Table 55 - I/O Base Address Configuration Register Description

LOGICAL

DEVICE

NUMBER

LOGICAL

DEVICE

REGISTER

INDEX

0x06 Reserved

BASE I/O

RANGE

(NOTE 1)

FIXED

BASE OFFSETS

0x07 KYBD n/a

Fixed Base Address: 60,64 n/a

+0 : Data Register

+4 : Command/Status Reg. n/a

0x09 Reserved n/a n/a n/a

Config.

Port

Config.

Port

0x26,0x27

(Note 2)

[0x0100:0x0FFE]

ON 2 BYTE BOUNDARIES

See Configuration Registers in

Table 51. Accessed through the

INDEX and DATA Ports located at the Configuration Port

Address and the Configuration

Port Address +1 respectively.

Note 1: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to ‘1’ and Address

Bits [A15:A12] must be ‘0’ for 16-bit address qualification.

Note 2: The Configuration Port is at either 0x03F0 or 0x0370 (for SYSOPT=0 or SYSOPT=1) at power up and can be relocated via the global configuration registers at 0x26 and 0x27.

146

Table 56 - Interrupt Select Configuration Register Description

DEFINITION STATE

Interrupt

Request Level

Select 0

Default = 0x00 or 0X06

(Note 1) on VCC POR,

VTR POR, SOFT

RESET and

HARD RESET

0x70 (R/W) Bits[3:0] selects which interrupt level is used for Interrupt 0.

0x00= no interrupt selected

0x03= IRQ3

0x04= IRQ4

0x05= IRQ5

0x06= IRQ6

0x07= IRQ7

0x08= IRQ8

0x09= IRQ9

0x0A= IRQ10

0x0B= IRQ11

0x0C= IRQ12

0x0D= IRQ13

0x0E= IRQ14

0x0F= IRQ15

Note: All interrupts are edge high (except ECP/EPP)

Note: nSMI is active low

C

Note: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND :

For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.

For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition

For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.

For the Serial Port logical device by setting any combination of bits D0-D3 in the IER

and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.

For the RTC by (refer to the RTC section of this spec).

For the KYBD logical device (refer to the KYBD controller section of this spec).

Note: IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.

Note: nSMI must be disabled to use IRQ2.

Note: All IRQ’s are available in Serial IRQ mode. Only IRQ[3:7] and IRQ[10:12] are available in

Parallel IRQ mode.

Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.

147

Table 57 - DMA Channel Select Configuration Register Description

DEFINITION STATE

DMA Channel

Select

Default = 0x04 or 0X02

(Note 1) on VCC POR,

VTR POR, SOFT

RESET and

HARD RESET

0x74 (R/W) Bits[2:0] select the DMA Channel.

0x00= Reserved

0x04-0x07= No DMA active

C

Note: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :

For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.

For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.

Note: DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.

Note 1: The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is

0x04.

148

b. a.

Note A. Logical Device IRQ and DMA Operation

1. IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the

IRQ and DACK disabled by the Configuration Registers (active bit or address not valid).

FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high impedance).

Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".

The FDC is in power down (disabled).

Serial Port 1 and 2:

Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is forced to a high impedance state - disabled.

I. ii.

SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is

ECP Mode:

(1) (DMA) dmaEn from ecr register. See table.

(2) IRQ - See table.

MODE

(FROM ECR REGISTER)

IRQ PIN

CONTROLLED BY

PDREQ PIN

CONTROLLED BY

000 PRINTER IRQE dmaEn

001 SPP IRQE dmaEn

010 FIFO (on) dmaEn

011 ECP (on) dmaEn

100 EPP IRQE dmaEn

101 RES IRQE dmaEn

110 TEST (on) dmaEn

111 CONFIG IRQE dmaEn d. Keyboard Controller: Refer to the KBD section of this spec.

149

SMSC Defined Logical Device Configuration Registers

The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the RESET_DRV signal. These registers are not affected by soft resets.

Table 58 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]

STATE

C FDD Mode Register

Default = 0x0E on VCC POR, VTR

POR and HARD

RESET

FDD Option Register

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

DEFINITION

0xF0 R/W Bit[0] Floppy Mode

= 0 Normal Floppy Mode (default)

= 1 Enhanced Floppy Mode 2 (OS2)

Bit[1] FDC DMA Mode

= 0 Burst Mode is enabled

= 1 Non-Burst Mode (default)

Bit[3:2] Interface Mode

= 11 AT Mode (default)

= 10 (Reserved)

= 01 PS/2

= 00 Model 30

Bit[4] Reserved

Bit[5] Reserved, set to zero

Bit[6] FDC Output Type Control

= 0

= 1

FDC outputs are OD24 open drain (default)

FDC outputs are O24 push-pull

Bit[7] FDC Output Control

= 0

= 1

FDC outputs active (default)

FDC outputs tri-stated

Note: Bits 6 & 7 do not affect the parallel port FDC pins.

0xF1 R/W

Bit[0] Forced Write Protect 0

= 0 Inactive (default)

= 1 FDD nWRTPRT input is forced active when the drive has been selected.

Bit[1] Reserved

Bits[3:2] Density Select

= 00 Normal (default)

= 01 Normal (reserved for users)

= 10 1 (forced to logic "1")

= 11 0 (forced to logic "0")

Bit[7:4] Reserved. nWRTPRT (to the FDC Core) = (nDS0 AND FORCE

WRTPRT) OR nWRTPRT (from the FDD Interface)

Note: Boot floppy is always drive 0.

Note: the Force Write Protect 0 bit also applies to the

Parallel Port FDC.

C

150

FDD0

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

FDD1

Table 58 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]

FDD Type Register

Default = 0xFF on VCC POR, VTR

POR and HARD

RESET

DEFINITION

0xF2 R/W Bits[1:0] Floppy Drive A Type

Bits[3:2] Floppy Drive B Type

Bits[5:4] Reserved (could be used to store Floppy Drive

C type)

Bits[7:6] Reserved (could be used to store Floppy Drive

D type)

Note: The FDC37M81x supports two floppy drives

0xF3 R Reserved, Read as 0 (read only)

0xF4 R/W Bits[1:0] Drive Type Select: DT1, DT0

Bits[2] Read as 0 (read only)

Bits[4:3] Data Rate Table Select: DRT1, DRT0

Bits[5] Read as 0 (read only)

Bits[6] Precompensation Disable PTS

=0 Use Precompensation

=1 No Precompensation

Bits[7] Read as 0 (read only)

0xF5 R/W Refer to definition and default for 0xF4

STATE

C

C

C

C

151

PP Mode Register

Default = 0x3C on VCC POR, VTR

POR and HARD

RESET

PP Mode Register 2

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

Table 59 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03]

DEFINITION

0xF0 R/W Bits[2:0] Parallel Port Mode

= 100 Printer Mode (default)

= 000 Standard and Bi-directional (SPP) Mode

= 001 EPP-1.9 and SPP Mode

= 101 EPP-1.7 and SPP Mode

= 010 ECP Mode

= 011 ECP and EPP-1.9 Mode

= 111 ECP and EPP-1.7 Mode

Bit[6:3] ECP FIFO Threshold

0111b (default)

Bit[7] PP Interupt Type

Not valid when the parallel port is in the Printer

Mode (100) or the Standard & Bi-directional Mode

(000).

= 1

= 0

Pulsed Low, released to high-Z.

IRQ follows nACK when parallel port in EPP

Mode or [Printer,SPP, EPP] under ECP.

IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode.

0xF1 R/W

Bits[1:0] PPFDC - muxed PP/FDC control

= 00 Normal Parallel Port Mode

= 01 PPFD1: Drive 0 is on the FDC pins

Drive 1 is on the Parallel port pins

= 10 PPFD2: Drive 0 is on the Parallel port pins

Drive 1 is on the Parallel port pins

Bits[7:2] Reserved. Set to zero.

STATE

C

152

Table 60 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]

DEFINITION STATE

Serial Port 1

Mode Register

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

0xF0 R/W Bit[0] MIDI Mode

= 0

= 1

MIDI support disabled (default)

MIDI support enabled

Bit[1] High Speed

= 0 High Speed Disabled(default)

= 1 High Speed Enabled

Bit[6:2] Reserved, set to zero

Bit[7]: Share IRQ

=0 UARTS use different IRQs

=1 UARTS share a common IRQ

See Note 1 below.

C

Note 1: To properly share and IRQ,

1. Configure UART1 (or UART2) to use the desired IRQ pin.

2. Configure UART2 (or UART1) to use No IRQ selected.

3. Set the share IRQ bit.

Note: If both UARTs are configured to use different IRQ pins and the share IRQ bit is set, then both of the UART IRQ pins will assert when either UART generates an interrupt.

UART Interrupt Operation Table

Table 61 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]

Serial Port 2

Mode Register

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

0xF0 R/W

DEFINITION

Bit[0] MIDI Mode

= 0

= 1

MIDI support disabled (default)

MIDI support enabled

Bit[1] High Speed

= 0 High Speed disabled(default)

= 1 High Speed enabled

Bit[7:2] Reserved, set to zero

STATE

C

153

Table 61 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]

IR Option Register

Default = 0x02 on VCC POR, VTR

POR and HARD

RESET

IR Half Duplex

Timeout

Default = 0x03 on VCC POR, VTR

POR and HARD

RESET

0xF1 R/W

DEFINITION

Bit[0] Receive Polarity

= 0 Active High (Default)

= 1 Active Low

Bit[1] Transmit Polarity

= 0 Active High

= 1 Active Low (Default)

Bit[2] Duplex Select

= 0

= 1

Full Duplex (Default)

Half Duplex

Bits[5:3] IR Mode

= 000 Standard COM Functionality (Default)

= 001 IrDA

= 010 ASK-IR

= 011 Reserved

= 1xx Reserved

Bit[6] IR Location Mux

= 0

= 1

Use Serial port TX2 and RX2 (Default)

Use alternate IRRX (pin 61) and IRTX (pin

62)

Bit[7] Reserved, write 0.

STATE

C

These bits set the half duplex time-out for the IR port.

This value is 0 to 10msec in 100usec increments.

0= blank during transmit/receive

1= blank during transmit/receive + 100usec

. . .

154

Table 62 - KYBD, Logical Device 7 [Logical Device Number = 0x07]

DEFINITION

KRST_GA20

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

0xF0

R/W

KRESET and GateA20 Select

Bit[7] Polarity Select for P12

= 0 P12 active low (default)

= 1 P12 active high

Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect MDAT signal to mouse wakeup (PME) logic.

1=block mouse clock and data signals into 8042

0= do not block mouse clock and data signals into

8042

Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect KDAT signal to keyboard wakeup (PME) logic.

1=block keyboard clock and data signals into 8042

0= do not block keyboard clock and data signals into

8042

Bit[4] MLATCH

= 0 MINT is the 8042 MINT ANDed with Latched

MINT (default)

= 1 MINT is the latched 8042 MINT

Bit[3] KLATCH

= 0 KINT is the 8042 KINT ANDed with Latched

KINT (default)

= 1 KINT is the latched 8042 KINT

Bit[2] Port 92 Select

= 0 Port 92 Disabled

= 1 Port 92 Enabled

Bit[1] Reserved

Bit[0] Reserved

0xFF

STATE

Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]

155

SMI Enable Register

1

Default = 0x00 on VCC POR and

VTR POR

SMI Enable Register

2

Default = 0x00 on VCC POR and

VTR POR

Bit 1 is set to ‘1’ on

VCC POR, VTR

POR, HARD

RESET and SOFT

RESET

SMI Status Register

1

Default = 0x00 on VCC POR and

VTR POR

0xB4 R/W

DEFINITION

This register is used to enable the different interrupt sources onto the group nSMI output.

1=Enable

0=Disable

Bit[0] Reserved

Bit[1] EN_PINT

Bit[2] EN_U2INT

Bit[3] EN_U1INT

Bit[4] EN_FINT

Bit[5] Reserved

Bit[6] Reserved

Bit[7] EN_WDT

0xB5 R/W This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto the nSMI frame in the Serial IRQ stream..

Unless otherwise noted,

1=Enable

0=Disable

Bit[0] EN_MINT

Bit[1] EN_KINT

Bit[2] EN_IRINT

Bit[3] Reserved

Bit[4] EN_P12: Enable 8042 P1.2 to route internally to nSMI. 0=Do not route to nSMI, 1=Enable routing to nSMI.

Bit[5] Reserved

Bit[6] EN_SMI_S: Enables nSMI Interrupt onto

Serial IRQ.

Bit[7] Reserved

0xB6 R/W This register is used to read the status of the SMI inputs.

The following bits must be cleared at their source.

Bit[0] Reserved

Bit[1] PINT (Parallel Port Interrupt)

The Parallel Port interrupt defaults to ‘1’ when the

Parallel Port activate bit is cleared. When the Parallel

Port is activated, PINT follows the nACK input.

Bit[2] U2INT (UART 2 Interrupt)

Bit[3] U1INT (UART 1 Interrupt)

Bit[4] FINT (Floppy Disk Controller Interrupt)

Bit[5] Reserved

Bit[6] Reserved

Bit[7] WDT (Watch Dog Timer)

SMI Status Register 0xB7 R/W This register is used to read the status of the SMI

156

STATE

C

C

C

C

Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]

DEFINITION

2

Default = 0x00 on VCC POR and

VTR POR inputs.

Bit[0] MINT: Mouse Interrupt. Cleared at source.

Bit[1] KINT: Keyboard Interrupt. Cleared at source.

Bit[2] IRINT: This bit is set by a transition on the IR pin

(RDX2 or IRRX as selected in CR L5-F1-B6 i.e., after the MUX). Cleared by a read of this register.

Bit[3] Reserved

Bit[4] P12: 8042 P1.2. Cleared at source

Bit[7:5] Reserved

0xB8 R/W Bits[7:0] Reserved Default = 0x00 on VTR POR

Pin Multiplex

Controls

Default = 0x02 on

VCC POR, VTR

POR and HARD

RESET

0xC0 Bit[0] Reserved

Bit[1] DMA 3 Select

Bit[2] Reserved

Bit[3] 8042 Select

Bit[4] Reserved

Bit[5:7] Reserved

Force Disk Change

Default = 0x01 on

VCC POR

0xC1

(R/W)

Floppy Data Rate

Select Shadow

UART1 FIFO

Control Shadow

UART2 FIFO

Control Shadow

0xC2

(R)

0xC3

(R)

0xC4

(R)

Bit[0] Force Change 0

0 = Inactive

1 = Active

Bit[7:1] Reserved

Force Change[0] can be written to 1 but is not clearable by software.

Force Change 0 is cleared on nSTEP and nDS0

DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND

Force Change 0) OR nDSKCHG

Bit[0] Data Rate Select 0

Bit[1] Data Rate Select 1

Bit[2] PRECOMP 0

Bit[3] PRECOMP 1

Bit[4] PRECOMP 2

Bit[5] Reserved

Bit[6] Power Down

Bit[7] Soft Reset

Bit[0] FIFO Enable

Bit[1] RCVR FIFO Reset

Bit[2] XMIT FIFO Reset

Bit[3] DMA Mode Select

Bit[5:4] Reserved

Bit[6] RCVR Trigger (LSB)

Bit[7] RCVR Trigger (MSB)

Bit[0] FIFO Enable

Bit[1] RCVR FIFO Reset

Bit[2] XMIT FIFO Reset

157

STATE

C

C,R

C

C

C

PME Control

Default = 0x00 on

VTR POR

PME Status

Default = 0x00 on

VTR POR

PME Wake Status

Default = 0x00 on

VTR POR

PME Wake Enable

Default = 0x00 on

V

TR

POR

Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]

DEFINITION

0xC5

(R/W)

0xC6

(R/w Clear)

0xC7

(R/w Clear)

0xC8

(R/W)

Bit[3] DMA Mode Select

Bit[5:4] Reserved

Bit[6] RCVR Trigger (LSB)

Bit[7] RCVR Trigger (MSB)

Bit[0] PME_En

= 0 nIO_PME signal assertion is disabled (default)

= 1 Enables FDC37M81x to assert nIO_PME signal

Bit[7:1] Reserved

PME_En is not affected by VCC POR, SOFT RESET or HARD RESET

Bit[0] PME_Status

= 0 (default)

= 1 Set when FDC37M81x would normally assert the

PCI nIO_PME signal, independent of the state of the PME_En bit.

Bit[7:1] Reserved

PME_Status is not affected by Vcc POR, SOFT

RESET or HARD RESET.

Writing a “1” to PME_Status will clear it and cause the

FDC37M81x to stop asserting nIO_PME, in enabled.

Writing a “0” to PME_Status has no effect.

This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit.

If the wake source has asserted a wake event, the associated PME Wake Status bit will be a “1”.

Bit[0] Reserved

Bit[1] RI2

Bit[2] RI1

Bit[3] KBD

Bit[4] MOUSE

Bit[7:5] Reserved

The PME Wake Status register is not affected by VCC

POR, SOFT RESET or HARD RESET.

Writing a “1” to Bit[4:0] will clear it. Writing a “0” to any bit in PME Wake Status Register has no effect.

This register is used to enable individual FDC37M81x

PME wake sources onto the nIO_PME wake bus.

When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event and the PME_En bit is “1”, the source will assert the PCI nIO_PME signal.

When the PME Wake Enable register bit for a wake source is inactive (“0”), the PME Wake Status register will indicate the state of the wake source but will not assert the PCI nIO_PME signal.

158

STATE

Table 63 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]

DEFINITION

Bit[0] Reserved

Bit[1] RI2

Bit[2] RI1

Bit[3] KBD

Bit[4] MOUSE

Bit[7:5] Reserved

The PME Wake Enable register is not affected by Vcc

POR, SOFT RESET or HARD RESET.

STATE

159

PIN

NAME

Table 64 - nRTS MUXING

MUX CONTROL

16 BIT ADDRESS

QUAL. (CR24.6)

SELECTED FUNCTION nRTS2 0

1

STATE OF

UNCONNECTED

SA12

INPUTS

0

PIN

NAME

Table 65 - nCTS2 MUXING

MUX CONTROL

16 BIT ADDRESS

QUAL. (CR24.6)

SELECTED FUNCTION nCTS2 0 nCTS2

1 SA13 0

Table 66 - nDTR2 MUXING

STATE OF

UNCONNECTED

INPUTS

PIN

MUX CONTROL

16 BIT ADDRESS

STATE OF

UNCONNECTED

NAME

QUAL. (CR24.6)

SELECTED FUNCTION INPUTS nDTR2 0 nDTR2

1 SA14 0

PIN

NAME

Table 67 - nDSR2 MUXING

MUX CONTROL

16 BIT ADDRESS

QUAL. (CR24.6) SELECTED FUNCTION

STATE OF

UNCONNECTED

INPUTS nDSR2 0 nDSR2

1 SA15 0

PIN

NAME

Table 68 - nDCD2 MUXING

MUX CONTROL

8042COMSEL.

(LD8:CRC0.3)

SELECTED FUNCTION nDCD2 0

1

STATE OF

UNCONNECTED

P12

INPUTS

-

PIN

NAME

Table 69 - nRI2 MUXING

MUX CONTROL

8042COMSEL.

(LD8:CRC0.3) SELECTED FUNCTION

STATE OF

UNCONNECTED

INPUTS nRI2 0 nR12

1 P16 -

160

PIN NAME

Table 70 - DRQ3 MUXING

MUX CONTROL

DMA3SEL

(LD8:CRC0.1) SELECTED FUNCTION

STATE OF

UNCONNECTED

INPUTS

0 P12 -

PIN NAME

Table 71 - nDACK3 MUXING

MUX CONTROL

DMA3SEL

(LD8:CRC0.1) SELECTED FUNCTION

STATE OF

UNCONNECTED

INPUTS

0 P16 -

161

WDT_TIME_OUT

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

WDT_VAL

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

WDT_CFG

Default = 0x00 on VCC POR, VTR

POR and HARD

RESET

Table 72 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]

0xF1

DEFINITION

Bit[0] Reserved

Bit[1] Reserved

Bits[6:2] Reserved, = 00000

Bit[7] WDT Time-out Value Units Select

= 0 Minutes (default)

= 1 Seconds

0xF2

0xF3

Watch-dog Timer Time-out Value

Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of Reg 0xF1, LD 8.

0x00 Time out disabled

0x01 Time-out = 1 minute (second)

.........

0xFF Time-out = 255 minutes (seconds)

Watch-dog timer Configuration

Bit[0] Joy-stick Enable

=1 WDT is reset upon an I/O read or write of the

=0

Game Port

WDT is not affected by I/O reads or writes to the Game Port.

Bit[1] Keyboard Enable

=1

=0

WDT is reset upon a Keyboard interrupt.

WDT is not affected by Keyboard interrupts.

Bit[2] Mouse Enable

=1

=0

WDT is reset upon a Mouse interrupt.

WDT is not affected by Mouse interrupts.

Bit[3] Reserved

Bits[7:4] WDT Interrupt Mapping

1111 = IRQ15

.........

0011 = IRQ3

0010 = Invalid

0001 = IRQ1

0000 = Disable

STATE

C

C

C

162

WDT_CTRL

Default = 0x00 on

VCC POR, VTR

POR and HARD

RESET

Table 72 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]

0xF4

DEFINITION

Watch-dog timer Control

Bit[0] Watch-dog Status Bit, R/W

=1 WD timeout occurred

=0 WD timer counting

Bit[1] Reserved

Bit[2] Force Timeout, W

=1 Forces WD timeout event; this bit is selfclearing

Bit[3] P20 Force Timeout Enable, R/W

= 1 Allows rising edge of P20, from the Keyboard

Controller, to force the WD timeout event. A

WD timeout event may still be forced by setting the Force Timeout Bit, bit 2.

P20 activity does not generate the WD timeout = 0 event.

Note: The P20 signal will remain high for a minimum of

1us and can remain high indefinitely. Therefore, when

P20 forced timeouts are enabled, a self-clearing edgedetect circuit is used to generate a signal which is

ORed with the signal generated by the Force Timeout

Bit.

Bit[7:4] Reserved. Set to 0

STATE

C

163

OPERATIONAL DESCRIPTION

MAXIMUM GUARANTEED RATINGS

Operating Temperature Range.....................................................................................................0

o

Storage Temperature Range ..................................................................................................... -55 o

C to +70 o

to +150 o

C

C

Lead Temperature Range........................................................................... Refer to JEDEC Spec. J-STD-020

Positive Voltage on any pin, with respect to Ground ...........................................................................V

cc

+0.3V

Negative Voltage on any pin, with respect to Ground............................................................................... -0.3V

Maximum V cc

............................................................................................................................................... +7V

Note: Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied.

Note: When powering this device from laboratory or system power supplies, it is important that the

Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

DC ELECTRICAL CHARACTERISTICS

(T

A

= 0

°C - 70°C, V cc

, V

TR

= +5 V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS

I Type Input Buffer

Low Input Level

High Input Level 2.0

0.8 V

V

TTL Levels

IS Type Input Buffer

Low Input Level

High Input Level

Schmitt Trigger Hysteresis

ICLK Input Buffer

Low Input Level

High Input Level

Input Leakage

(All I and IS buffers)

Low Input Leakage

High Input Leakage

V

ILI

V

IHI

V

ILIS

V

IHIS

V

HYS

V

ILCK

V

IHCK

I

IL

I

IH

-10

-10

2.2

2.2

250

+10

+10

0.8

0.4

V

V mV

μA

μA

V

V

Schmitt Trigger

Schmitt Trigger

V

IN

= 0

V

IN

= V

CC

164

PARAMETER

O4 Type Buffer

Low Output Level

High Output Level

Output Leakage

IO8 Type Buffer

Low Output Level

High Output Level

Output Leakage

O8SR Type Buffer

Low Output Level

High Output Level

Output Leakage

Rise Time

Fall Time

O24 Type Buffer

Low Output Level

High Output Level

Output Leakage

IO12 Type Buffer

Low Output Level

High Output Level

Output Leakage

SYMBOL MIN TYP MAX UNITS COMMENTS

V

OL

V

OH

I

OL

V

OL

V

OH

I

OL

T

RT

T

FL

V

OL

V

OH

I

OL

V

OL

V

OH

I

OL

V

OL

V

OH

I

OL

2.4

-10

2.4

-10

2.4

-10

2.4

-10

5

5

2.4

-10

0.4

+10

0.4

+10

0.4

+10

0.4

+10

0.4

+10

V

V

μA

V

V

μA ns ns

V

V

μA

V

V

μA

V

V

μA

I

OL

= 4 mA

I

OH

= -2 mA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 8 mA

I

OH

= -4 mA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 8 mA

I

OH

= -8 mA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 24 mA

I

OH

= -12 mA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 12 mA

I

OH

= -6 mA

V

IN

= 0 to V

CC

(Note 1)

165

PARAMETER

O12 Type Buffer

Low Output Level

High Output Level

Output Leakage

O24PD Type Buffer

Low Output Level

High Output Level

Output Leakage

O16SR Type Buffer

Low Output Level

High Output Level

Output Leakage

Rise Time

Fall Time

OD16P Type Buffer

Low Output Level

Output Leakage

OD24 Type Buffer

Low Output Level

Output Leakage

OD48 Type Buffer

Low Output Level

Output Leakage

SYMBOL MIN TYP MAX UNITS COMMENTS

V

OL

V

OH

I

OL

T

RT

T

FL

V

OL

I

OL

V

OL

V

OH

I

OL

V

OL

V

OH

I

OL

2.4

-10

2.4

-10

5

5

2.4

-10

-10

0.4

+10

0.4

+10

0.4

+10

0.4

+10

V

V

μA ns ns

V

μA

V

V

μA

V

V

μA

I

OL

= 12 mA

I

OH

= -6 mA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 24 mA

I

OH

= -12 mA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 16 mA

I

OH

= -16 mA

V

IN

= 0 to V

CC

(Note 1)

V

OL

I

OL

V

OL

I

OL

0.4

+10

0.4

+10

V

μA

V

μA

I

OL

= 16 mA

I

OH

= 90

μA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 24 mA

V

IN

= 0 to V

CC

(Note 1)

I

OL

= 48 mA

V

IN

= 0 to V

CC

(Note 1)

166

PARAMETER

ChiProtect

(SLCT, PE, BUSY, nACK, nERROR)

OD12 Type Buffer

Low Output Level

Output Leakage

SYMBOL MIN TYP MAX UNITS COMMENTS

I

IL

± 10

μA

V

CC

= 0V

V

IN

= 6V Max

V

I

OL

OL

-10

0.4

+10

V

μA

I

OL

= 12 mA

V

IN

= 0 to V

CC

(Note 1)

V

CC

= 0V

V

IN

= 6V Max

Backdrive

(nSTROBE, nAUTOFD, nINIT, nSLCTIN)

Backdrive

(PD0-PD7)

V

CC

Supply Current Active

(Note 4)

I

I

I

IL

IL

CCI

15

± 10

± 10

30

μA

μA mA

V

V

CC

IN

= 0V

= 6V Max

All Outputs Open

Trickle Supply Voltage V

TR

V

CC min

-.5V

5

V

CC max

V V

CC

must not be greater than .5V above V

TR

V

TR

Supply Current Active

(Note 4)

I

TRI

6

10 mA All outputs open

Note 1: All output leakage’s are measured with the current pins in high impedance.

Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state.

Note 3: KBCLK, KBDATA, MCLK, MDATA contain 90

μA min pull-ups.

Note 4: Please contact SMSC for the latest value.

Note 5: The minimum value given for V

TR

applies when V

CC

is active. When V

CC

is 0V, the minimum V

TR is 0V.

167

CAPACITANCE T

A

= 25

°C; fc = 1MHz; V

CC

= 5V

Clock Input Capacitance

Input Capacitance

Output Capacitance

C

IN

C

IN

C

OUT

LIMITS TEST

All pins except pin under test tied to AC

168

TIMING DIAGRAMS

For the Timing Diagrams shown, the following capacitive loads are used on outputs.

NAME

CAPACITANCE

TOTAL (pF)

SD[7:0] 50

PD[7:0] 240

DRQx 50 nDIR 240 nSTEP 240 nDS0-1 240 nMTR0-1 50 nWDATA 240 nRTSx 50 nDTRx 50 nINIT 50 nSTROBE 240 nALF 240 nSLCTIN 50

IOCHRDY 240

TXD1 50

TXD2 50

KDAT 240

KCLK 240

MDAT 240

MCLK 240

SER_IRQ 50

169

t3

SAx t4

SD<7:0> t1 t2 t5 nIOW

FIGURE 4 - IOW TIMING FOR PORT 92

IOW Timing

NAME DESCRIPTION MIN UNITS

t1 SAx Valid to nIOW Asserted t2 SDATA Valid to nIOW Asserted

40

0 ns ns t3 nIOW Asserted to SAx Invalid t4 nIOW Deasserted to DATA Invalid

10

0 ns ns t5 nIOW Deasserted to nIOW or nIOR Asserted 100 ns

170

V c c

A l l H o s t

A c c e s s e s t 1 t 2 t 3

FIGURE 5 - POWER-UP TIMING

t1 t2

Vcc Slew from 4.5V to 0V

Vcc Slew from 0V to 4.5V

300

100 t3 All Host Accesses After Powerup (Note 1) 125

Note 1: Internal write-protection period after Vcc passes 4.5 volts on power-up

500

μs

μs

μs

171

AEN

SA[x], nCS nIOW

SD[x] t1 t3 t2

DATA VALID t4

FIGURE 6 - ISA WRITE

t7 t5 t6 t1 t2 t3 t4 t5 t6 t7

SA[x], nCS and AEN valid to nIOW asserted nIOW asserted to nIOW deasserted nIOW asserted to SA[x], nCS invalid

SD[x] Valid to nIOW deasserted

SD[x] Hold from nIOW deasserted nIOW deasserted to nIOW asserted nIOW deasserted to AEN invalid

10

80

10

45

25

10

0 ns ns ns ns ns ns ns

172

AEN

SA[x], nCS nIOR

SD[x]

PD[x], nERROR, PE,

SLCT, nACK, BUSY nIOR/nIOW t1 t7 t4 t3 t2

DATA VALID t8

FIGURE 7 - ISA READ

ISA READ TIMING

t1 SA[x], nCS and AEN valid to nIOR asserted t2 nIOR asserted to nIOR deasserted t3 nIOR asserted to SA[x], nCS invalid t4 nIOR asserted to Data Valid t5 Data Hold/float from nIOR deasserted t7 Parallel Port setup to nIOR asserted t8 nIOR asserted after nIOW deasserted t8 nIOR/nIOR, nIOW/nIOW transfers from/to ECP FIFO t9 nIOW deasserted to AEN invalid t9 t5 t6

10

50 ns ns

80

150

10

10

50 ns ns

10 25 ns

25 ns

20 ns ns ns ns

173

KCLK/

MCLK

KDAT/

MDAT

t1

CLK

1 t3

Start Bit

t2 t6

t4

CLK

2

Bit 0

CLK

9

Bit 7

CLK

10

Parity Bit

CLK t5

11

Stop Bit

FIGURE 8 - KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING

t1 Time from DATA transition to falling edge of CLOCK

(Receive) t2 Time from rising edge of CLOCK to DATA transition

(Receive) t3 Duration of CLOCK inactive (Receive/Send) t4 Duration of CLOCK active (Receive/Send) t5 Time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (Receive) t6 Time from inactive to active CLOCK transition, used to time when the auxiliary device samples DATA (Send)

30

30

50

50

µsec

µsec

174

t1 t2 t2

CLOCKI

FIGURE 9A - INPUT CLOCK TIMING

NAME DESCRIPTION MIN UNITS

t1 t2

Clock Cycle Time for 14.318MHz (Note)

Clock High Time/Low Time for 14.318MHz

Clock Rise Time/Fall Time (not shown)

20

69.84

35

5 ns ns ns

P C I_ C L K t5 t1 t3 t4 t2

FIGURE 9B – PCI CLOCK TIMING

NAME DESCRIPTION MIN UNITS

t1 Period 30 33.3 nsec

12 nsec

12 nsec

3 nsec

3 nsec

FIGURE 9C - RESET TIMING

t1

n R E S E T _ D R V t1 nRESET_DRV width (Note) 1.5

μs

Note: The RESET width is dependent upon the processor clock. The RESET must be active while the clock is running and stable.

175

AEN

FDRQ,

PDRQ

nDACK[x] nIOR or nIOW

SD<7:0>

TC t15 t14 t1 t6 t5 t11 t3 t16 t2 t7 t4 t8 t12 t10 t9

DATA VALID

t13

FIGURE 10A - DMA TIMING (SINGLE TRANSFER MODE)

t1 t2 t3 nDACK Delay Time from FDRQ High

DRQ Reset Delay from nIOR or nIOW

FDRQ Reset Delay from nDACK Low t5 t6 t7 t8 nIOR Delay from FDRQ High nIOW Delay from FDRQ High

SData Access Time from nIOR Low

SData Set Up Time to nIOW High t9 SData to Float Delay from nIOR High t10 SData Hold Time from nIOW High t11 nDACK Set Up to nIOW/nIOR Low t12 nDACK Hold after nIOW/nIOR High t13 TC Pulse Width t14 AEN Set Up to nIOR/nIOW t15 AEN Hold from nDACK t16 TC Active to PDRQ Inactive

Note: FDRQ is the DMA request for the FDC.

PDRQ is the DMA request for the Parallel Port.

5

10

60

40

10

0

150

0

0

40

10

10

100

100 ns ns

100 ns ns ns ns

100

60 ns ns ns ns ns ns ns ns ns ns

176

AEN t15 t3 t16 t2

FDRQ,

PDRQ

nDACK[x] nIOR or nIOW

SD<7:0>

TC t1 t14 t6 t5 t11 t4

DATA VALID

t12 t7 t13 t8 t10 t9

DATA VALID

FIGURE 10B - DMA TIMING (BURST TRANSFER MODE)

t1 t2 t3 t5 t6 t7 t8 t9 t10 t11 t12 nDACK Delay Time from FDRQ High

DRQ Reset Delay from nIOR or nIOW

FDRQ Reset Delay from nDACK Low nIOR Delay from FDRQ High nIOW Delay from FDRQ High

SData Access Time from nIOR Low

SData Set Up Time to nIOW High

SData to Float Delay from nIOR High

SData Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold after nIOW/nIOR High

0

150

0

0

40

10

10

5

10 t13 TC Pulse Width t14 AEN Set Up to nIOR/nIOW

60

40 t15 AEN Hold from nDACK t16 TC Active to PDRQ Inactive

10

Note: FDRQ is the DMA request for the FDC.

PDRQ is the DMA request for the Parallel Port.

60

100

100 ns ns

100 ns ns

100 ns ns ns ns ns ns ns ns ns ns ns ns

177

nDIR t4 t1 t2 nSTEP t5 nDS0-3 t6 nINDEX t7 nRDATA t8 nWDATA nIOW nDS0-1, nMTR0-1 t9

FIGURE 11 - DISK DRIVE TIMING (AT MODE ONLY)

t1 t2 t3 t4 t5 t6 nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width t7 t8 nRDATA Active Time Low nWDATA Write Data Width Low t9 nDS0-1, MTRO-1 from End of nIOW

*X specifies one MCLK period and Y specifies one WCLK period.

MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz)

WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz)

4

24

96

132

20

2

40

.5

25 t9

X*

X*

X*

X*

X*

X* ns

Y* ns

178

nIOW t1 nRTSx, nDTRx

FIGURE 12A - SERIAL PORT TIMING

NAME DESCRIPTION MIN UNITS

t1 nRTSx, nDTRx Delay from nIOW 200 ns

Data

Start t1

Data (5-8 Bits)

Parity

Stop (1-2 Bits)

TXD1, 2

FIGURE 12B – SERIAL PORT DATA

NAME DESCRIPTION MIN UNITS

t1 Serial Port Data Bit Time tBR1 nsec

Note 1: tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud

Rates have percentage errors indicated in the “Baud Rate” table in the “Serial Port” section.

PCI_CLK t1 t2

SER_IRQ

FIGURE 12C – SETUP AND HOLD TIME

NAME DESCRIPTION MIN UNITS

t1 t2

SER_IRQ Setup Time to PCI_CLK Rising

SER_IRQ Hold Time to PCI_CLK Rising

7

0 nsec nsec

179

PD<7:0> nIOW nINIT, nSTROBE, nALF, SLCTIN t2 t1

FIGURE 13 - PARALLEL PORT TIMING

t1 PD0-7, nINIT, nSTROBE, nALF Delay from nIOW t2 PD0 - PD7 Delay from IOW Active

100

100 ns ns

180

SA<10:0>

SD<7:0> nIOW

IOCHRDY nWRITE

PD<7:0> nDATASTB nADDRSTB nWAIT t17 t8 t13 t20 t1 t10 t14 t16 t3 t11 t4 t12 t18 t9 t19 t2 t5 t15 t6 t7

FIGURE 14 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

181

TABLE 73 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING

t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWRITE to Command Asserted t4 nWAIT Deasserted to Command Deasserted

(Note 1) t5 nWAIT Asserted to PDATA Invalid (Note 1)

0

60

5

50

185

35 ns ns ns t7 Command Deasserted to nWAIT Asserted t8 SDATA Valid to nIOW Asserted t9 nIOW Deasserted to SDATA Invalid t10 nIOW Asserted to IOCHRDY Asserted t11 nWAIT Deasserted to IOCHRDY Deasserted

(Note 1)

0 ns

10 12 s

0 ns

10

0

0 24 ns ns ns t12 IOCHRDY Deasserted to nIOW Deasserted t13 nIOW Asserted to nWRITE Asserted t14 nWAIT Asserted to Command Asserted (Note 1) t15 Command Asserted to nWAIT Deasserted t16 PDATA Valid to Command Asserted t17 Ax Valid to nIOW Asserted t18 nIOW Asserted to Ax Invalid

10

0

60

0

10

40

10

70

210

10 t19 nIOW Deasserted to nIOW or nIOR Asserted t20 nWAIT Asserted to nWRITE Asserted (Note 1)

40

60 185 ns ns

Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. ns ns ns s ns ns ns

182

t20

A0-A10

IOR

SD<7:0>

IOCHRDY

PDIR nWRITE

PD<7:0> t19 t8 t24 t23 t9 t21 t2 t25 t28 t26 t1 t14

DATASTB

ADDRSTB nWAIT t15 t5 t13

PData bus driven by peripheral

t4 t7 t18 t10 t11 t3 t12 t22 t6

FIGURE 15 - EPP 1.9 DATA OR ADDRESS READ CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

t27 t17 t16

183

TABLE 74 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS

NAME DESCRIPTION MIN UNITS

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

PDATA Hi-Z to Command Asserted nIOR Asserted to PDATA Hi-Z nWAIT Deasserted to Command Deasserted

(Note 1)

Command Deasserted to PDATA Hi-Z

Command Asserted to PDATA Valid

PDATA Hi-Z to nWAIT Deasserted

PDATA Valid to nWAIT Deasserted

0

0

0

0

0

0

0

0

30

50

24 ns ns t20 t21 t22 t23 t24 t25 t16 t17 t18 t19 t11 t12 t13 t14 t26 t27 nIOR Asserted to IOCHRDY Asserted nWRITE Deasserted to nIOR Asserted (Note 2) nWAIT Deasserted to IOCHRDY Deasserted

(Note 1)

IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA Hi-Z (Hold Time)

PDATA Valid to SDATA Valid nWAIT Asserted to Command Asserted nWAIT Deasserted to PDATA Driven (Note 1) nWAIT Deasserted to nWRITE Modified (Notes 1,2)

SDATA Valid to IOCHRDY Deasserted (Note 3)

Ax Valid to nIOR Asserted nIOR Deasserted to Ax Invalid nWAIT Asserted to nWRITE Deasserted nIOR Deasserted to nIOW or nIOR Asserted nWAIT Asserted to PDIR Set (Note 1)

PDATA Hi-Z to PDIR Set nWAIT Asserted to PDATA Hi-Z (Note 1)

PDIR Set to Command nWAIT Deasserted to PDIR Low (Note 1)

60

0

40

10

0

40

0

0

0

40

75 ns ns ns

0 195 ns

10 12

μs

60 190 ns

60

0

60

0

60 t28 nWRITE Deasserted to Command 1

Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.

Note 2: When not executing a write cycle, EPP nWRITE is inactive high.

Note 3: 85 is true only if t7 = 0.

190

85

10

185

185

180

20

180 ns ns ns ns ns ns ns ns ns ns ns ns ns ns

μs ns ns ns

184

A0-A10

SD<7:0> nIOW

IOCHRDY nWRITE

PD<7:0> nDATAST nADDRSTB nWAIT

PDIR t17 t8 t13 t1 t10 t20 t16 t3 t6 t18 t9 t11 t12 t19 t2 t5 t4 t21

FIGURE 16 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

185

TABLE 75 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE PARAMETERS

NAME DESCRIPTION MIN UNITS

t1 nIOW Asserted to PDATA Valid t2 Command Deasserted to nWRITE Change

0

0

50

40 ns ns t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted (Note 2)

5 35

50 ns ns t5 Command Deasserted to PDATA Invalid t8 t9 t10 t11 t12 t13

SDATA Valid to nIOW Asserted nIOW Deasserted to DATA Invalid nIOW Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted

IOCHRDY Deasserted to nIOW Deasserted nIOW Asserted to nWRITE Asserted

50 ns

10 12

μs

10 ns

0

0 24 ns ns

10

0

40

50 ns ns ns t16 PDATA Valid to Command Asserted t17 t18

Ax Valid to nIOW Asserted nIOW Deasserted to Ax Invalid

10

40

10

100

35

45 ns ns

μs ns t19 nIOW Deasserted to nIOW or nIOR Asserted t20 nWAIT Asserted to IOCHRDY Deasserted ns t21 Command Deasserted to nWAIT Deasserted 0 ns

Note 1: nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an

EPP Write.

Note 2: The number is only valid if nWAIT is active when IOW goes active.

186

t20

A0-A10 nIOR t19

SD<7:0>

IOCHRDY nWRITE

PD<7:0> nDATASTB nADDRSTB nWAIT

PDIR t23 t8 t3 t5 t15 t13 t10 t11 t2 t12 t4 t22 t21

FIGURE 17 - EPP 1.7 DATA OR ADDRESS READ CYCLE

SEE TIMING PARAMETERS ON NEXT PAGE

187

TABLE 76 - EPP 1.7 DATA OR ADDRESS READ CYCLE PARAMETERS

NAME DESCRIPTION MIN UNITS

t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted 0

50

40 ns ns t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid

0

0 ns ns t8 t10 t11 t12 t13 nIOR Asserted to IOCHRDY Asserted nWAIT Deasserted to IOCHRDY Deasserted

IOCHRDY Deasserted to nIOR Deasserted nIOR Deasserted to SDATA High-Z (Hold Time)

PDATA Valid to SDATA Valid

0

0

24

50

40

40 ns

10 12

μs

40 ns

10 ns ns ns ns ns t19 Ax Valid to nIOR Asserted t20 nIOR Deasserted to Ax Invalid t21 Command Deasserted to nWAIT Deasserted t22 nIOR Deasserted to nIOW or nIOR Asserted

0

40 ns ns t23 nIOR Asserted to Command Asserted 55 ns

Note: WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP

Read.

188

ECP PARALLEL PORT TIMING

Parallel Port FIFO (Mode 101)

The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direc-

Reverse-Idle Phase

The peripheral has no data to send and keeps tion using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to Figure 19.

ECP Parallel Port Timing

The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase.

Forward-Idle

When the host has no data to send it keeps

HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low.

Forward Data Transfer Phase

The interface transfers data and commands from the host to the peripheral using an interlocked

PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest.

The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward

Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of

HostClk. The peripheral then sets PeriphAck

(Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets

PeriphAck (Busy) low, completing the transfer.

This sequence is shown in Figure 19.

The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe).

PeriphClk high. The host is idle and keeps

HostAck low.

Reverse Data Transfer Phase

The interface transfers data and commands from the peripheral to the host using an interlocked

HostAck and PeriphClk.

The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets

HostAck (nALF) low. The peripheral then sets

PeriphClk (nACK) low when it has data to send.

The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck

(nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck

(nALF) low, completing the transfer. This sequence is shown in Figure 20.

Output Drivers

To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck,

PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified in

then IEEE 1284 Extended Capabilities Port

Protocol and ISA Interface Standard, Rev. 1.14,

July 14, 1993, available from Microsoft. The dynamic driver

189

change must be implemented properly to prevent glitching the outputs.

PD<7:0> nSTROBE

BUSY t1 t2 t4

FIGURE 18 - PARALLEL PORT FIFO TIMING

t3 t6 t5

NAME DESCRIPTION MIN UNITS

t1 PDATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 PDATA Hold from nSTROBE Inactive (Note 1) t4 nSTROBE Active to BUSY Active

600

600

450

500 ns ns ns ns t5 BUSY Inactive to nSTROBE Active 680 ns t6 BUSY Inactive to PDATA Invalid (Note 1) 80 ns

Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely.

190

t3

nALF t4

PD<7:0> t2 t1 t7 t8 nSTROBE t6 t5 t6

BUSY

FIGURE 19 - ECP PARALLEL PORT FORWARD TIMING

NAME DESCRIPTION MIN UNITS

t1 t2 nALF Valid to nSTROBE Asserted

PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed

(Notes 1,2)

0

0

60

60 ns ns t4 BUSY Deasserted to PDATA Changed (Notes 1,2) t5 nSTROBE Deasserted to Busy Asserted t6 nSTROBE Deasserted to Busy Deasserted t7 BUSY Deasserted to nSTROBE Asserted (Notes 1,2)

80

0

0

80

180

200 ns ns ns ns t8 BUSY Asserted to nSTROBE Deasserted (Note 2) 80 180 ns

Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out.

Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.

191

t2

PD<7:0> t1 t5 t6 nACK t4 t3 t4

nALF

FIGURE 20 - ECP PARALLEL PORT REVERSE TIMING

NAME DESCRIPTION MIN UNITS

t1 PDATA Valid to nACK Asserted t2 nALF Deasserted to PDATA Changed t3 nACK Asserted to nALF Deasserted

(Notes 1,2)

0

0 ns ns t4 nACK Deasserted to nALF Asserted (Note 2) t5 nALF Asserted to nACK Asserted

80

0

200 ns ns t6 nALF Deasserted to nACK Deasserted 0 ns

Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low.

Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.

192

DATA

0 t2 t1

IRRX n IRRX

1 0 t2 t1

1 0 0 1 1 0 1 1 t1 t1 t1 t2 t2 t1 t1 t1 t1 t2 t2 t2 t2 t2

Parameter

Pulse Width at 115kbaud

Pulse Width at 57.6kbaud

Pulse Width at 38.4kbaud

Pulse Width at 19.2kbaud

Pulse Width at 9.6kbaud

Pulse Width at 4.8kbaud

Pulse Width at 2.4kbaud

Bit Time at 115kbaud

Bit Time at 57.6kbaud

Bit Time at 38.4kbaud

Bit Time at 19.2kbaud

Bit Time at 9.6kbaud

Bit Time at 4.8kbaud

Bit Time at 2.4kbaud

min

1.4

1.4

1.4

1.4

1.4

1.4

1.4

typ

1.6

3.22

4.8

9.7

19.5

39

78

8.68

17.4

26

52

104

208

416

max

2.71

3.69

5.53

11.07

22.13

44.27

88.55

Notes:

1. Receive Pulse Detection Criteria: A received pulse is considered detected if the

received pulse is a minimum of 1.41µs.

2. IRRX: L5, CRF1 Bit 0 = 1

nIRRX: L5, CRF1 Bit 0 = 0 (default)

FIGURE 21 - IrDA RECEIVE TIMING

193

units

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

DATA

IRTX

n IRTX

0 t2 t1

1 t2

0 t1

Parameter

1 0 0

min

1

typ

1

0

max

1

units

t1 t1 t1 t1 t1 t1 t1 t2

Pulse Width at 115kbaud

Pulse Width at 57.6kbaud

Pulse Width at 38.4kbaud

Pulse Width at 19.2kbaud

Pulse Width at 9.6kbaud

Pulse Width at 4.8kbaud

Pulse Width at 2.4kbaud

Bit Time at 115kbaud

1.41

1.41

1.41

1.41

1.41

1.41

1.41

1.6

3.22

4.8

9.7

19.5

39

78

8.68

2.71

3.69

5.53

11.07

22.13

44.27

88.55

µs

µs

µs

µs

µs

µs

µs

µs t2 t2

Bit Time at 57.6kbaud

Bit Time at 38.4kbaud

17.4

26

µs

µs t2 Bit Time at 19.2kbaud

52 µs t2 t2 t2

Bit Time at 9.6kbaud

Bit Time at 4.8kbaud

Bit Time at 2.4kbaud

104

208

416

µs

µs

µs

Notes:

1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX

1

and 48SX.

2. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default)

nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high

FIGURE 22 - IrDA TRANSMIT TIMING

194

DATA

IRRX n IRRX

MIRRX nMIRRX t1 t2 t3 t4 t5 t6

0 t1

1 t2 t3 t4 t5 t6

0

Parameter

Modulated Output Bit Time

Off Bit Time

Modulated Output "On"

Modulated Output "Off"

Modulated Output "On"

Modulated Output "Off"

1 0 0

min

0.8

0.8

0.8

0.8

1

typ

1

1

1

1

1

max

1.2

1.2

1.2

1.2

0 1

units

Notes:

1. IRRX: L5, CRF1 Bit 0: 1 = RCV active low

nIRRX: L5, CRF1 Bit 0: 0 = RCV active high (default)

MIRRX, nMIRRX are the modulated outputs

FIGURE 23 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING

µs

µs

µs

µs

µs

µs

1

195

DATA

IRTX

n IRTX

MIRTX nMIRTX

0 t1

1 t2 t3 t4 t5 t6

0 1 0 0

Parameter min

t1 t2

Modulated Output Bit Time

Off Bit Time t3 t4 t5

Modulated Output "On"

Modulated Output "Off"

Modulated Output "On"

0.8

0.8

0.8

t6 Modulated Output "Off" 0.8

Notes:

1. IRTX: L5, CRF1 Bit 1: 1 = XMIT active low (default)

1 1

typ

1

1

1

1

0

max

1.2

1.2

1.2

1.2

1

nIRTX: L5, CRF1 Bit 1: 0 = XMIT active high

MIRTX, nMIRTX are the modulated outputs

FIGURE 24 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING units

µs

µs

µs

µs

µs

µs

1

196

D

D1

E E1 e

W

A A2

H

-C-

0.10

H

L

L1 e

0

W

TD(1)

TE(1)

TD(2)

TE(2)

DIM

A

A1

A2

D

D1

E

E1

A1

M IN M AX

2.80

0.1

2.57

23.4

3.15

0.45

2.87

24.15

19.9

17.4

13.9

0.1

20.1

18.15

14.1

0.2

0.65

0.95

1.8

0.65 BSC

2.6

12°

.2

.4

21.8

15.8

22.2

16.2

22.21

16.27

22.76

16.82

TD/TE

M IN M AX

.110

.004

.101

.921

.124

.018

.113

.951

.783

.685

.547

.004

.791

.715

.555

.008

.026

.071

.037

.102

.0256 BSC

12°

.008

.016

.858

.622

.874

.638

.874

.641

.896

.662

0

L

L1

Notes :

1) Coplanarity is 0.100m m (.004") m ax im um .

2) Toleranc e on the position of the leads is

0.200m m (.008") m axim um .

3) Pack age body dim ens ions D1 and E1 do not inc lude the m old protrus ion. M axim um m old protrus ion is 0.25m m (.010").

4) Dim ensions TD and TE are im portant for tes ting by robotic handler. Only abov e c om binations of (1) or (2) are acc eptable.

5) Controlling dim ens ion: m illim eter. Dim ens ions in inc hes for referenc e only and not nec es s arily ac c urate.

FIGURE 25 - 100 PIN QFP PACKAGE OUTLINE

197

80 Arkay Drive, Hauppauge, NY 11788 (631) 435-6000, FAX (631) 273-3123

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Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications.

Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of

Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer.

Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST

INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE

OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR

CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF

THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT

LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE

FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

FDC37M81x Rev. 02-17-09

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