M9328MX21ADSE

Application Development System

User’s Manual

Document Number: UMS-21100

Rev. A

07/2006

Chapter 1 General Information

1.1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2

M9328MX21ADSE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.3

System and User Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.4

M9328MX21ADSE Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.5

ADS Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2 Configuration and Operation

2.3.4

2.3.5

2.3.6

2.3.7

2.3.8

2.3.9

2.3.10

2.3.11

2.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2

Configuring Board Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2.1

2.2.2

Peripheral Selection Switch (S1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Mode/User Switch (S2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.3

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3.1

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3.2

2.3.3

On-Board Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

USB On-The-Go Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

UART and IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Ethernet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Touchscreen ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

CD Quality CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Keypad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Memory Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Audio Indicator (Buzzer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.3.12

LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.4

Using The Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.5

Add-On Module Connections and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.5.1

Using the TFT LCD Display Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.5.2

2.5.3

2.5.4

2.5.5

2.5.6

2.5.7

Using the Keypad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Using a NAND Flash Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Using a SD/MMC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Using Image Sensor Daughter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Using the PCMCIA Daughter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Using the TV Encoder Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Chapter 3 Support Information

3.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2

CPU to Base Board Connectors PX1, PX2, PY1, and PY2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.3

CPU to Option Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.4

UART/RS-232 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.4.1

3.4.2

3.4.3

UART1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

UART4 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

External UART Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

1

3.5

Multi-ICE Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.6

Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.7

USB OTG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.8

NAND Flash Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

3.9

External Keypad Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

3.10

LCD Panel Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

3.11

TV Encoder Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

3.12

SD/MMC Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

3.13

Extension and Image Sensor Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

3.14

Disposal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

2

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

About This Book

This manual explains how to connect and operate the M9328MX21ADS i.MX21 Application

Development System.

Audience

The audience for this manual is handheld communication device designers. It is assumed that users are engineers or technicians with experience using development systems.

Organization

The manual consists of three chapters.

• Chapter 1 General Information introduces the user to the features and capabilities of the ADS.

• Chapter 2 Configuration and Operation contains configuration information, connection descriptions, and other operational information that may be useful during the development process.

• Chapter 3 Support Information contains connector pin assignments, connector signal descriptions, and other useful information about the ADS.

Revision History

The following table summarizes changes to this document since the previous release (Rev. A).

Revision History

Location Revision

Conventions

Units and measures in this manual conform to the International System of Units (SI) as defined by

National Institute of Standards and Technology Special Publication 811.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

P-1

Definitions, Acronyms, and Abbreviations

ICE

I/O

IrDA

JTAG

LCD

LED

MB

MCU

The following acronyms and abbreviations are used in this manual. This list does not include signal, register, and software mnemonics.

ADS

CD

Application Development System

Compact Disk

CMOS

CODEC

CPU

DCE

Complementary Metal Oxide Semiconductor

Code/Decode

Central Processing Unit

Data Communications Equipment

DIN

DIP

DTE

DUART

I

2

C

Deutsches Institut für Normung

Dual In-line Package

Data Terminal Equipment

Dual Universal Asynchronous Receiver/Transmitter

Inter-Integrated Circuit

In-Circuit Emulator

Input/Output

Infrared Data Association

MMC

NAND

OTG

PC

PCMCIA

SD

SDRAM

SI

SSI

TFT

UART

USB

VDC

Joint Test Access Group

Liquid Crystal Display

Light Emitting Diode

Megabyte

Microcontroller Unit

Multi-media Card

Negative AND

On the Go

Personal Computer

Personal Computer Memory Card International Association

SanDisk (Smart Media)

Synchronous Dynamic Random Access Memory

System International (international system of units and measures)

Synchronous Serial Interface

Thin Film Transistor

Universal Asynchronous Receiver/Transmitter

Universal Serial Bus

Volts Direct Current

M9328MX21ADSE User’s Manual, Rev. A

P-2 Freescale Semiconductor

Chapter 1 General Information

1.1

Description

The M9328MX21ADSE helps you develop applications for the i.MX21 MCU.

The ADS has 19 connectors and sockets that support application software, target board debugging, and optional circuit cards. A separate LCD display panel and a separate keypad are supplied with the ADS.

When you connect the LCD panel and keypad to the ADS Base board, they align with each other.

1.2

M9328MX21ADSE Features

ADS features include:

• i.MX21 Multimedia Application Processor

• Two clock-source crystals, 32.768 KHz and 26 MHz

• Power connector for +5.0-volts in from an external regulated power supply, an in-line fuse, and a power on/off switch.

• Voltage regulators that step down the 5.0 VDC input to Vcc (3.0 VDC), 2.5 VDC, 1.8 VDC and

1.5 VDC

• Multi-ICE debug support

• Two 8 MB

× 16-bit Burst Flash memory devices configured as one 32 MB, 32-bit device

• Two 16 MB

× 16-bit SDRAM devices configured as one 64 MB, 32-bit device

• High speed expansion connectors for adding optional cards.

• Two-board system: modular CPU board plugs into Base board; Base board has connections for

LCD display panel and keypad

• Memory mapped expansion I/O

• Software readable board revisions

• Configuration and user definable DIP switches

• SD/MMC memory card connector

• Two RS-232 transceivers and DB9 connectors (one configured for DCE and one for DTE operation) supporting on-chip UART ports

• External UART with RS-232 transceiver and DB9 connector

• IrDA transceiver that conforms to Specification 1.4 of the Infrared Data Association

• USB OTG (On The Go) interface transceiver and USB mini AB connector

• Separate LCD panel assembly that connects to the Base board and interfaces directly with the ADS

• Touch panel controller for use with the LCD

• Separate keypad unit with 36 push button keys

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 1-1

General Information

• Separate CMOS Image Sensor Card

• Audio CODEC includes an 11.28 MHz crystal oscillator, a 3.5 mm audio input jack, a 3.5 mm microphone jack, and a 3.5 mm headphone jack

• Cirrus Logic CS8900A-CQ3Z Ethernet controller, with RJ-45 connector for connecting to a system hub

• Two 32

× 3-pin DIN expansion connectors with most i.MX21 I/O signals

• Variable resistor for emulation of a battery voltage level

• NAND Flash card (Plugs into CPU Board)

• LED indicators for power, external bus activity, Ethernet activity, and two LEDs for user defined status indiction

• Universal power supply with 5.0-volt output @ 2.4 Amperes

• USB cable

• RS-232 serial cable

• Two RJ-45 Ethernet cables, network, and crossover

1.3

System and User Requirements

To use the ADS, you need:

• An IBM PC or compatible computer that has:

— A Windows

® 98, Windows ME™, Windows XP™, Windows 2000, or Windows NT® (version

4.0) operating system

— A parallel port and a Multi-ICE device (not included)

• A

+ 5 VDC power supply @ 2.4 A, with a 2 mm female (inside positive) power connector

(included)

CAUTION

Never supply more than +5.5-volts power to your M9328MX21ADSE.

Doing so can damage board components.

1.4

M9328MX21ADSE Diagram

Figure 1-1 shows the connectors and other major parts of the ADS Base board and CPU board.

1-2

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

General Information

+5V IN

P8

OFF

ON

SW1

P9

ETHERNET

P3

EXT UART DCE

F1

2A

BASE BOARD

LED6 LED5

5V PWR

VCC PWR

STAT2

STAT1

BUS ACT

SW2

RESET

BUZZER

P10

LINE IN

LED1

LED2

LED3

LED4

LED7

1

2

3

4

5

6

7

8

4

5

6

7

8

1

2

3

LINK ACT

S2

BOOT0

BOOT1

BOOT2

BOOT3

CLKMODE0

CLKMODE1

SW1 IRQ

SW2 READ

S1

UART1_ON

UART4_ON

IrDA_ON

NEXUS_EN

JTAG_CTRL

TONE_OUT

PEN_CS_B

PEN_IRQ_B

P11

MIC IN

P12

HEADPHONE

J7

ONE WIRE

PE3

EXP CON 2

P2

UART4 DTE

P1

UART1 DCE

ACT

SD2_D0

DTR

J3

NC

SD2_D1

DSR

NC

SD2_D2

J4

CD

J5

RI

NC

SD2_D3

J6

3

2

1

CPU BOARD

PX1/PY1

P20 MULTI-ICE

PM1

PM2

U5

CPU

PK1

U6

U8

J1 J3 J2

PK2

PX2/PY2

P4

USB OTG

U16 IrDA

P7

U7

U9

VR1

BATT EM

P13

P5

PE2

EXP CON 1

PE1

CSI

Figure 1-1. M9328MX21ADSE Application Development System

Important board components on the CPU card are:

• U5 — i.MX21 MCU

• PX1, PX2 — connections to the Base board (bottom side)

• PK1, PK2 — connections to option cards

• P20 — ARM Multi-ICE connector

• PM1 & PM2 — NAND Flash card connectors

• J1, J2, J3 — Power interruption jumpers for measuring CPU current consumption

Important board components on the Base board are:

• PY1, PY2 — connections to the CPU board

• P1 — RS-232 DB9 connector for the processor’s UART1, DCE pinout

• P2 — RS-232 DB9 connector for the processor’s UART4, DTE pinout

• P3 — RS-232 DB9 connector for the External UART, DCE pinout

• P4 — USB OTG connector

• P5 — Keypad module connector

• P6 — SD/MMC card connector

• P7 — LCD/touch panel connector

P6

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 1-3

General Information

• P8 — 5.0-volt input power connector

• P9 — RJ-45 Ethernet connectors

• P10 — Line In to audio CODEC

• P11 — Microphone In to audio CODEC

• P12 — Headphone Out to audio CODEC

• P13 — TV Encoder connector

• PE1 — Connector to an Image Sensor card

• PE2, PE3 — I/O Extension connectors

• S1 — Peripheral enable and JTAG select DIP switches

• S2 — Boot mode, clock mode, and user defined DIP switches

• SW1 — Power switch

• SW2 — Reset switch

• LED1 — 5 volt power LED (green)

• LED2 — 3 volt power LED (green)

• LED3 and LED4 — General-purpose LEDs (orange)

• LED5, LED6 — Ethernet activity LEDs (green, orange)

• LED7 — external bus activity LED (red)

• U16 — IrDA transceiver

• VR1 — emulate the battery voltage level

• J3, J4, J5 and J6 — Modem control enable jumpers for RS-232 DTE interface on P2

• J7 — One wire interface

1.5

ADS Specifications

Table 1-1 shows M9328MX21ADSE specifications.

Table 1-1. Specifications

Characteristic

Clock speed (SDRAM/FLASH)

Ports

Temperature:

operating

storage

Relative humidity

Power requirements

Dimensions

Specifications

CPU 266MHz, System 133MHz

10Base-T (RJ-45), RS-232 serial, USB OTG

0° to +50° C

-40° to +85° C

0 to 90% (noncondensing)

4.5V

—

5.5 VDC @ 2.4 A

7.15 x 9.45 in (18.2 x 24.1 cm)

1-4

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Configuration and Operation

Chapter 2 Configuration and Operation

2.1

Introduction

This section contains configuration information, connection descriptions, and other operational information that may be useful during the development process.

2.2

Configuring Board Components

Table 2-1 is a summary of configuration settings. The following paragraphs provide additional information

about configuring and using the ADS.

Table 2-1. Component Configuration Settings

Component

System Power Switch, SW1

Position

BOARD

EDGE

SW1

OFF ON

Effect

Move this switch to the ON position to enable the power source connected to P8 to power the system.

Factory setting is OFF.

System Reset Switch, SW2 Push to reset the M9328MX21ADSE.

SW2

Peripheral Selection Switch,

S1

S1

Mode Switch, S2

S2

S1

The UART1 and UART4 transceivers are forced enabled, the IrDA module is enabled by software, Nexus is disabled, ARM mode JTAG is selected, and the buzzer is connected to PWMO. The LCD touch panel signals are connected.

Factory setting is shown.

Subsection 2.2.1 explains other settings for this switch.

Configures 32-bit Burst Flash as the boot device and the Default clock bypass mode is selected.

Factory setting is shown

Subsection 2.2.2 explains other settings for this switch.

Power Headers

(on CPU card)

J1, VCC (3.0 V)

J2, 1.8 V

J3, 1.5 V

S2

1 2

1 2

Connects specified power signal.

Factory Setting

(Leave jumper installed during normal use.)

Connect ammeter across pins to measure processor current consumption from the specified power source.

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 2-1

Configuration and Operation

Component

Modem Control Enable

Jumpers

(on Base board)

J3, DTR

J4, DSR

J5, CD

J6, RI

Table 2-1. Component Configuration Settings (continued)

Position

1 2 3

1 2 3

Effect

The specified RS-232 control signal of P2 connects to the specified

I/O signal.

J3 - DTR (pin 4) is controlled by SD2_D0 (output)

J4 - DSR (pin 6) can be read on SD2_D1 (input)

J5 - CD (pin 1) can be read on SD2-D2 (input)

J6 - RI (pin 9) can be read on SD2-D3 (input)

The specified RS-232 control signal of P2 is not connected to any I/O signal and cannot be controlled or read.

J3 - DTR is forced active (positive), SD2_D0 is unused

J4 - DSR cannot be read, SD2_D1 is unused

J5 - CD cannot be read, SD2_D2 is unused

J6 - RI cannot be read, SD2_D3 is unused

2.2.1

Peripheral Selection Switch (S1)

S1 is a DIP switch that consists of eight slide switches. Seven of the switches enable and disable software control of the UART transceivers, the IrDA buffers, the Nexus buffer, the touch panel controls, and the buzzer. One switch selects JTAG operation mode.

Table 2-2 shows S1 functionality.

Table 2-2. S1 Switch Settings

Switch Name Setting Effect

S1-1, UART1_ON

S1-2, UART4_ON

S1-3, IrDA_ON

S1-4, NEXUS_EN

ON

OFF

ON

OFF

ON

OFF

ON

OFF

Forces the UART1 transceiver to be enabled.

UART1_EN_B bit controls the UART1 transceiver

Forces the UART4 transceiver to be enabled.

UART4_EN_B bit controls the UART4 transceiver

Forces the IrDA module buffers to be enabled.

IrDA_EN bit controls the IrDA buffers

Internal test only.

Set to OFF for debugging purposes.

S1-5, JTAG _CTRL

S1-6, TONE_OUT

ON

OFF

ON

OFF

Internal test only.

ARM Multi-ICE mode selected after TRST.

The buzzer is controlled by the PWMO output.

PWMO is disconnected from the buzzer circuit.

S1-7, PEN_CS_B

S1-8, PEN_IRQ_B

ON

OFF

ON

OFF

CSPI_SS0 controls the chip enable of the Touch controller.

Disables CSPI_SS0 control of the Touch controller chip enable.

UART3_CTS is connected to PENIRQ_B out of the Touch controller.

UART3_CTS is not connected to PENIRQ_B out of the Touch controller.*

*PENIRQ_B is not connected to anything.

Figure 2-1 shows an example configuration. The switches are set so that the UART1 transceiver and the

IrDA module are forced enabled; the UART4 transceiver can be enabled by software; and the NEXUS buffer and buzzer are disabled. In addition, ARM mode JTAG is selected and the LCD touch control signals are enabled.

M9328MX21ADSE User’s Manual, Rev. A

2-2 Freescale Semiconductor

Configuration and Operation

UART1_ON

UART4_ON

IrDA_ON

NEXUS_ON, (Set to OFF)

JTAG_CTRL, (Set to OFF)

TONE_OUT

PEN_CS_B

PEN_IRQ_B

S1

Figure 2-1. Switch S1

2.2.2

Mode/User Switch (S2)

S2 is a DIP switch that consists of eight slide switches. S2-1 to S2-4 configure boot mode and S2-5 and

S2-6 control the clock bypass modes. These switch settings take effect only on power up or after a reset.

S2 also provides two user definable switches (S2-7 and S2-8). S2-7 can be used to cause an interrupt when switched (SW1_IRQ through signal UART3_CTS).

Table 2-3 lists the settings for the boot-mode subswitches, S2-1 through S2-4.

.

Table 2-3. Boot Mode Switch Settings

Boot Mode, Device

Internal bootstrap ROM (USB/UART)

NAND, 8-bit, 2KB per page

NAND, 16-bit, 2KB per page

NAND, 16-bit, 512bytes per page

CS0, 16-bit, D[15:0]

CS0, 32-bit

NAND 8-bit, 512bytes per page

BOOT3

S2-4

ON

ON

ON

ON

ON

ON

ON

BOOT2

S2-3

ON

ON

ON

OFF

OFF

OFF

OFF

BOOT1

S2-2

ON

OFF

OFF

ON

ON

OFF

OFF

BOOT0

S2-1

ON/OFF

ON

OFF

ON

OFF

ON

OFF

Figure 2-2 shows an example configuration. S2-1 through S2-4 configure the system to boot from the 8-bit

NAND Flash. S2-5 and S2-6 are always set to OFF. S2-7 and S2-8 are set for user-defined functions.

BOOT0

BOOT1

BOOT2

BOOT3

CLKMODE0, (Set to OFF)

CLKMODE1, (Set to OFF)

SW1 IRQ

SW2 READ

S2

Figure 2-2. Switch S2

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

2-3

Configuration and Operation

2.3

Operation

This section describes how the system functions and how to use the boards.

2.3.1

Functional Block Diagram

Figure 2-3 shows the functional interconnections of the ADS in a block diagram format.

Base Board

Power Connector,

Power Switch & fuse

UART1,

UART2 &

IrDA

Ext.

UART

Ethernet port

USB series mini-AB connector

3V regulator, CPU

Reset signal

UART signals

UART controller

Addr /Data Bus

Ethernet controller

Addr /Data Bus

CPU Board

NAND Flash

Connector

NFC signals

Multi-ICE connector

SDRAM

Burst Flash i.MX21

USB OTG

Transceiver

USBOTG signals

LEDs & Buzzer

Boot mode,

UARTs, IrDA selection

1-wire Interface

Silicon & Board revision register

IO pins , PWM

S/W readable

DIP switches

Line In

Mic In

Speaker

Out

Audio

CODEC

OWIRE

Addr /Data bus

High Speed

Connectors

IO pins

Addr /Data bus

Transceiver

Touch screen controller

Battery Level

Measurement

Emulation

SSI

2.5V, 1.8V and

1.5V regulators

Base board connectors

Peripheral signals Peripheral signals CSI signals MMC/SD signals

KPP

Expansion

Connector 2

Expansion

Connector 1

Image sensor connector

MMC/SD connector

Keypad

Connector

White

LED driver

LCD Board

TFT LCD DC-

DC converter

LCD panel

(240x320 pixels) & Touch screen

Keypad Board

Figure 2-3. Functional Block Diagram of M9328MX21ADSE

2.3.2

On-Board Memory

Figure 2-4 and Figure 2-5 show the on-board memory interface. The M9328MX21ADSE is equipped with

8M x 32-bit Burst Flash and 16M x 32-bit SDRAM. The chip selects CS0 and CS2 (CSD0) are used for

Burst Flash and SDRAM chip selects, respectively.

2-4

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Configuration and Operation

V

CC

V

CC

V

CC

CS0

ECB

A2...A24

BCLK

OE

LBA

DQM3_EB3

FLASH_RST

D0.15

DQM1_EB1

D16..31

CS

WP

ACC

RDY

A0...A22

CLK

OE

AVD

WE

RESET

D0..15

WE

D0.15

Figure 2-4. Burst Flash Interface

V

CC

8MX16-Bit Burst Flash

8MX16-Bit Burst Flash

16MX16-Bit SDRAM

CS2

SDCKE0

SDCLK

RAS

CAS

WE

A2..A18

BA0

A19

A20

DQM1_EB1

DQM0_EB0

D0..15

CS

CKE

CLK

RAS

CAS

WE

A0..10

A11

BA0

BA1

LDQM

UDQM

D0..15

16MX16-Bit SDRAM

DQM3_EB3

DQM2_EB2

D16..31

LDQM

UDQM

D0..15

Figure 2-5. SDRAM Interface

2.3.3

Memory Map

Table 2-4 shows the memory map for external peripherals on the ADS board. Because the Burst Flash and

the Ethernet Controller do not take up the entire address space of the associated chip selects, software can access the same physical memory location at more than one range of addresses. For instance, SDRAM uses

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 2-5

Configuration and Operation

the entire 64 MB address space allowed for CSD0, but the Burst Flash occupies only 32 MB of the 64 MB space available to CS0, so it appears in two different ranges of addresses. CS1 covers 16 MB allowing many repetitions of the memory mapped peripherals.

Table 2-4. M9328MX21ADSE Memory Map

Peripheral Chip Select

SDRAM

Burst FLASH

Ethernet Controller

CSD0

CS0

CS1

External DUART

Read CPU and

Base board versions

CS1

CS1

CS1

Memory Mapped I/O

CS1

* For I/O operations only D15 - D0 are used

Address Range (HEX)

0xC000_0000 to 0xC3FF_FFFF

0xC800 0000 to 0xC9FF_FFFF

0xCC00 0000 to 0xCC00_000F*

0xCC20 0000 to 0xCC20_000F*

Read 0xCC40_0000*

D7-D0 = CPU, D15-D8 = Base board

Write to 0xCC80_0000* (Output)

Read 0xCC80_0000* (Input)

Act Mem Size

64 MB

32 MB

16 BYTES

16 BYTES

2 BYTES

2 BYTES

2 BYTES

2.3.4

USB On-The-Go Interface

The i.MX21 USB OTG Device Module interfaces with a Phillips ISP1301BS USB transceiver connected to P4, a mini AB USB connector. The interface can function as either a USB host or USB device. The interface includes a Maxim MAX3355EUD+ USB power supply chip which can provide power on the

USB bus in host mode. This power supply chip is enabled by the USB_PWR signal. For details on the

operation of the USB interface, refer to the i.MX21 data sheet. Figure 2-6 shows the USB interface

connection.

i.MX21

USB_PWR

ISP1301BS

P4

D-

D+

VBUS

ID

VBUS

IDIN

IDOUT

SHDN

MAX3355EUD+

Figure 2-6. USB OTG Interface

USB MINI AB

2.3.5

UART and IrDA

Figure 2-7 shows how to connect the UART and IrDA circuits.

M9328MX21ADSE User’s Manual, Rev. A

2-6

USB Device

Freescale Semiconductor

Configuration and Operation

i.MX21

UART1_TXD1

UART1_RXD1

UART1_RTS1

UART1_CTS1

RS232 Transceiver

EN

USBH1_TXDM

USBH1_RXDP

USBH1_RXDM

USBH1_RXDP

SD2_D1

SD2_D2

SD2_D3

SD2_D0

TXD4

RXD4

RTS

CTS

DSR*

CD*

RI*

DTR*

RS232 Transceiver

EN

UART3_TXD

UART3_RXD

* If enabled by jumper

Buffer

EN

EN

IrDA

P1

UART1

DCE

V

CC

GND

S1-1

Software Enable via MMIO Latch

P2

UART4

DTE

V

CC

GND

S1-2

Software Enable via MMIO Latch

V

CC

GND

S1-3

Software Enable via MMIO Latch

Figure 2-7. UARTs and IrDA Interface

2.3.6

Ethernet

The ADS is equipped with a Cirrus Logic CS8900A-CQ3Z Crystal LAN ISA Ethernet Controller that can interface with the i.MX21. The CS8900A-CQ3Z has 10BaseT transmit and receive filters and operates in

I/O mode. Figure 2-8 shows the Ethernet interface.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

2-7

Configuration and Operation

i.MX21

BA1..3

D0..15

CS_LAN

B_OE

B_RW

B_DQM3_EB3

UART3_RTS

V

CC

CS8900A-CQ3Z

SA8

SA9

SA0

SA4..7

SA10..19

SA1..3

D0..15

AEN

IOR

IOW

SBHE

INTRQ0

CHIPSEL

Isolation

Transformer

P9

RJ45 Connector

Figure 2-8. Ethernet Interface

2.3.7

Touchscreen ADC

The ADS is equipped with an Analog Devices AD7873BRQZ ADC. The ADC communicates with the touchscreen of the LCD on the Base board. Variable resistor VR1 on the Base board can be used to change the VBAT input voltage to the ADC. The i.MX21 communicates with the ADC via the CSPI1 interface.

Setting S1-7 to ON connects CSPI1_SS0 to the ADC chip select. Setting S1-8 to ON connects the ADC

interrupt out to UART3_CTS. Figure 2-9 shows the ADC interface.

V

CC i.MX21

S1

UART3_CTS

CSPI1_SS0

CSPI1_SCLK

CSPI1_MISO

CSPI1_MOSI

8

7

AD7873BRQZ

PENIRQ VREF

VBAT

CS

DCLK

DOUT

DIN

X+

Y+

X-

Y-

VR1

P7

LCD CONNECTOR

Figure 2-9. ADC Interface

M9328MX21ADSE User’s Manual, Rev. A

2-8 Freescale Semiconductor

Configuration and Operation

2.3.8

CD Quality CODEC

The ADS has a Wolfson WM8731SEDS 32-bit linear low power stereo CODEC with a built-in headphone driver (U24). The CODEC is controlled by the i.MX21, which sends the digital audio data via an SSI2 interface and control data via an I

2

C interface.

The CODEC has stereo line and mono microphone level audio inputs as well as stereo headphone outputs.

It features a mute function, programmable line level volume control, and a bias voltage output suitable for

an electret type microphone. Table 2-5 shows the CODEC connectors and describes their basic functions.

Table 2-5. Audio Connectors

Connector

P10

P11

P12

Descriptions

Stereo line in jack

Dynamic microphone input jack

Headphone jack for audio out

The WM8731SEDS data sheet is available at http://www.wolfsonmicro.com/

2.3.9

Keypad

The ADS includes an external keypad module that connects to the Base board. The keys provide tactile feedback. The i.MX21 keypad interface reads the pad via the KCOL[5:0] and KROW[5:0] signals. the interface has chording diodes to prevent ghost key presses. The keys are labeled with numeric, cursor control, soft key, and spare key functions, but the actual functionality is determined by user software. The default keypad can be replaced by a custom design. The UART2 signals that are multiplexed internally with the KCOL[7,6] and KROW[7,6] signals are brought out to keypad connector P5. This allows the use

of an 8x8 keypad matrix. Table 2-6 shows the key switch connections to the keypad signals by function

name (as labeled on the PCB) and the switch reference designators.

Table 2-6. Keypad Layout and Connections

KROW5

KROW4

KROW3

KROW2

KROW1

KROW0

KCOL5

APP1

SW1

APP2

SW7

DOWN

SW13

VOL UP

SW19

VOL DOWN

SW25

POWER

SW31

KCOL4

SEND

SW2

HOME

SW8

APP3

SW14

APP4

SW20

EXTRA 1

SW26

RECORD

SW32

KCOL3

KEY 1

SW3

LEFT

SW9

1 -

SW15

4 GHI

SW21

7 PQRS

SW27

*

SW33

KCOL2

UP

SW4

ACTION

SW10

2 ABC

SW16

5 JKL

SW22

8 TUV

SW28

0 +

SW34

KCOL1

KEY 2

SW5

RIGHT

SW11

3 DEF

SW17

6 MNO

SW23

9 WXYZ

SW29

#

SW35

KCOL0

END

SW6

BACK

SW12

EXTRA 2

SW18

EXTRA 3

SW24

EXTRA 4

SW30

EXTRA 5

SW36

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 2-9

Configuration and Operation

2.3.10

Memory Mapped I/O

The ADS uses Memory Mapped I/O to add I/O functions without using the I/O resources of the processor.

The following paragraphs describe the I/O functions.

2.3.10.1

Input I/O

A memory read of hex address 0xCC80_0000 inputs the state of the ADS signals connected to latches U5

and U7. Table 2-7 shows which signal is associated with each data bit.

Table 2-7. Input Buffer Signals

BIT

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

BIT 15

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Signal

SD_WP

SW_SEL

RESET_E_UART

RESET_BASE

CSI_CTL2

CSI_CTL1

CSI_CTL0

UART1_EN

UART4_EN

LCDON

IRDA_EN

IRDA_FIR_SEL

IRDA_MD0_B

IRDA_MD1

LED4_ON

LED3_ON

Description

Secure Data Write Protect

Software readable switch

External UART Reset

Ethernet controller Reset

Image Sensor control 2

Image Sensor control 1

Image Sensor control 0

UART1 transceiver enable

UART4 transceiver enable

LCD enable

IrDA transceiver enable

Reserved

IrDA SD/Mode (inverted)

Reserved

LED 4 control

LED 3 control

2-10

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Configuration and Operation

2.3.10.2

Output I/O

A memory write to hex address 0xCC80_0000 causes U5 and U7 to latch the logic state of the data bus.

Each latch output is associated with the data bus signal of the same number (Bit 0 is equal to DATA0, and

so on). All output bits are forced to logic 0 (low) on power up or reset. Table 2-8 shows the functions

associated with each data bit.

Table 2-8. Output Latch Functions

Bit Signal Description

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

TP6

TP7

RESET_E_UART*

RESET_BASE*

CSI_CTL2

CSI_CTL1

CSI_CTL0

Test point

Test point

External UART Reset (U17)

Ethernet controller Reset (U9)

Image Sensor control 2

Image Sensor control 1l

Image Sensor control 0

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

UART1_EN**

UART4_EN**

LCDON

IRDA_EN**

IRDA_FIR_SEL

IRDA_MD0_B

IRDA_MD1

LED4_ON

UART1 transceiver enable

UART4 transceiver enable

LCD enable

IrDA transceiver enable

Reserved

IrDA SD/Mode (inverted)

Reserved

LED 4 control, logic 1 turns on LED

BIT 15 LED3_ON LED 3 control, logic 1 turns on LED

* Toggle the pin from a logic 0 (low) to a logic 1 (high) and back to logic 0 to reset the selected peripheral.

** The associated x_ON switch (see Table 1-2) must be set OFF to allow the state of these bits to control the associated interface. Setting the bit to logic 1 (high) enables the interface and setting it to logic 0 (low) disables the interface.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

2-11

Configuration and Operation

2.3.11

Audio Indicator (Buzzer)

The ADS includes an audio indicator or buzzer, U23. When S1-6 is ON, the PWMO pin of the i.MX21 controls this function. This buzzer operates from 1 KHz to 10 KHz. The maximum sound level is reached when the frequency is 3 KHz and the duty cycle is 50%.

2.3.12

LED Indicators

Table 2-9 shows the ADS LED indicators and their associated functions.

Table 2-9. Function of LED Indicators

Reference # Color Name Function

LED1

LED2

LED3

Green

Green

Orange

5V PWR

VCC PWR

STAT 2

5 V power is ON

3 V power is ON

User status controlled by Output BIT 15*

LED4

LED5

LED6

LED7

Orange

Green

Orange

Red

STAT 1

ACTIVE

LINK

BUS ACT

User status controlled by Output BIT 14*

Blinking indicates LAN Activity

Link good or host controlled output

Blinking indicates external bus activity

* A logic high level at the controlling pin turns on the LED. A logic low turns it off.

2.4

Using The Board Connectors

Table 2-10 shows the ADS connectors and functions, as well as special instructions for using the

connectors. Figure 1-1 in Chapter 1 shows the connector locations and reference designators.

Connector

P1

P2

P3

P4

P5

P6

P7

P8

SD/MMC

LCD panel

Power

Table 2-10. M9328MX21ADSE Connectors

Function

UART1

UART4

External UART

USB OTG

Keypad module

Comments

RS-232 DCE interface to UART1 of the i.MX21

RS-232 DTE interface to UART4 of the i.MX21

RS-232 DCE interface to Port A of the ST16C2552 UART

USB On The Go mini AB connector

Connect the Keypad ribbon cable between this connector and the corresponding connector of the Keypad Module, J1.

Slide the MMC card into the connector until it snaps into place.

Connect LCD ribbon cable between this connector and the corresponding connector of the LCD display panel, J11.

Plug the 5-volt power-supply jack end into this connector.

M9328MX21ADSE User’s Manual, Rev. A

2-12 Freescale Semiconductor

Connector

P9

P10

P11

P12

P13

PE1

PE2, PE3

PY1, PY2

PX1, PX2

PK1, PK2

P20 (CPU)

PM1, PM2

(CPU)

Configuration and Operation

Table 2-10. M9328MX21ADSE Connectors (continued)

Function

Ethernet

Line In

Microphone In

Headphone

TV encoder

Image Sensor

Expansion

CPU

Base board

Option Cards

Multi-ICE

NAND Flash

Comments

Standard Ethernet connector. A cable for direct network and one for crossover connections (direct to a PC) have been provided.

Standard 3.5 mm connector for stereo audio input to the

WM8731SEDS CODEC

Standard 3.5 mm connector for a microphone. Use only dynamic microphones with a 200 to 600 ohms impedance.

Standard 3.5 mm connector for stereo audio. This is the amplified stereo output of the WM8731SEDS. Use headphones with a 16 to 32 ohms impedance.

This connector is used with P7 together to connect the TV encoder card.

Connect the image-sensor daughter board to this connector.

Standard 48 pin, three row, male DIN connectors. Can be connected to directly or cabled to a custom circuit board.

Connect the CPU module to these connectors.

Connect these to the Base board PY connectors.

Connect an appropriate Option Card to these connectors

Standard ARM Multi-ICE connector

Plug the NAND Flash module into this connector.

2.5

Add-On Module Connections and Usage

Figure 2-10 through Figure 2-12 show how to connect the ADS add-on modules. The following

paragraphs describe how to connect and use the add-on modules.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

2-13

Configuration and Operation

+5V IN

P8

OFF

ON

SW1

P9

ETHERNET

P3

EXT UART DCE

F1

2A

BASE BOARD

LED6 LED5

5V PWR

VCC PWR

STAT2

STAT1

BUS ACT

BUZZER

SW2

RESET

P10

LINE IN

LED1

LED2

LED3

LED4

LED7

7

8

5

6

1

2

3

4

7

8

5

6

1

2

3

4

LINK ACT

S2

BOOT0

BOOT1

BOOT2

BOOT3

CLKMODE0

CLKMODE1

SW1 IRQ

SW2 READ

S1

UART1_ON

UART4_ON

IrDA_ON

NEXUS_EN

JTAG_CTRL

TONE_OUT

PEN_CS_B

PEN_IRQ_B

P11

MIC IN

P12

HEADPHONE

J7

ONE WIRE

PN1

PN2

PE3

EXP CON 2

P2

UART4 DTE

P1

UART1 DCE

ACT

SD2_D0

DTR

NC

SD2_D1

DSR

NC

SD2_D2

CD

J3 J4 J5

RI

NC

SD2_D3

J6

3

2

1

CPU BOARD

PX1/PY1

P20 MULTI-ICE

PK1

P4

USB OTG

U16 IrDA

P7

VR1

BATT EM

P13

PM1

PM2

PE2

EXP CON 1

U5

CPU

U6

U8

J1 J3 J2

PK2

PX2/PY2

PE1

CSI

U7

U9

P5

P6

34 CONDUCTOR

RIBBON CABLE

20 CONDUCTOR

RIBBON CABLE

IMAGE SENSOR

SD/MMC

Card

Figure 2-10. Installation of the Main Boards

J11

VR1

TFT LCD PANEL

(240 x 320 dots)

LCD BOARD

P1

Vol Up

Send

Home

App1 App2

Key 1

KEYPAD

Up

Left Action

Down

Vol Down Extra 1

Power Record

1

4

7

*

2

5

8

0

Key 2

Right

End

Back

App3

3

6

App4

Extra 2

Extra 3

9

#

Extra 4

Extra 5

2-14

U9

PCMCIA DAUGHTER CARD

+5V IN

P8

F1

2A

OFF

ON

SW1

P9

ETHERNET

P3

EXT UART DCE

BASE BOARD

LED6 LED5

5V PWR

VCC PWR

STAT2

STAT1

BUS ACT

SW2

RESET

BUZZER

P10

LINE IN

LED1

LED2

LED3

LED4

LED7

7

8

5

6

3

4

1

2

3

4

1

2

5

6

7

8

LINK ACT

S2

BOOT0

BOOT1

BOOT2

BOOT3

CLKMODE0

CLKMODE1

SW1 IRQ

SW2 READ

S1

UART1_ON

UART4_ON

IrDA_ON

NEXUS_EN

JTAG_CTRL

TONE_OUT

PEN_CS_B

PEN_IRQ_B

P11

MIC IN

P12

HEADPHONE

J7

ONE WIRE

PE3

EXP CON 2

P2

UART4 DTE

P1

UART1 DCE

ACT

SD2_D0

DTR

NC

SD2_D1

DSR

NC

SD2_D2

CD

J3 J4 J5

RI

NC

SD2_D3

J6

3

2

1

CPU BOARD

PX1/PY1

P20

PE2

EXP CON 1

MULTI-ICE

PM1

PM2

U5

CPU

PK1

U6

U8

J1 J3 J2

PK2

PX2/PY2

PE1

CSI

P4

USB OTG

U16 IrDA

P7

U7

U9

VR1

BATT EM

PK1/PK3

Figure 2-11. Installation of the PCMCIA Daughter Card

P13

PK2/PK4

P5

S1

P6

P2

P1

S2

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Configuration and Operation

P1

+5V IN

P8

OFF

ON

SW1

P9

ETHERNET

P3

EXT UART DCE

F1

2A

BASE BOARD

LED6 LED5

5V PWR

VCC PWR

STAT2

STAT1

BUS ACT

SW2

RESET

BUZZER

P10

LINE IN

LED1

LED2

LED3

LED4

LED7

1

2

3

4

5

6

7

8

3

4

5

1

2

6

7

8

LINK ACT

S2

BOOT0

BOOT1

BOOT2

BOOT3

CLKMODE0

CLKMODE1

SW1 IRQ

SW2 READ

S1

UART1_ON

UART4_ON

IrDA_ON

NEXUS_EN

JTAG_CTRL

TONE_OUT

PEN_CS_B

PEN_IRQ_B

P11

MIC IN

P12

HEADPHONE

J7

ONE WIRE

PE3

EXP CON 2

P2

UART4 DTE

P1

UART1 DCE

ACT

SD2_D0

DTR

NC

SD2_D1

DSR

NC

SD2_D2

CD

J3 J4 J5

NC

SD2_D3

RI

J6

3

2

1

CPU BOARD

PX1/PY1

P20

PE2

MULTI-ICE

PM1

PM2

U5

CPU

PK1

U6

U8

J1 J3 J2

PK2

PX2/PY2

PE1

P4

USB OTG

U16 IrDA

P7

U7

U9

VR1

BATT EM

P13

P5

EXP CON 1 CSI

Figure 2-12. Installation of the TV Encoder Card

P6

P2

J2

J1

J3

2.5.1

Using the TFT LCD Display Panel

The ADS is equipped with a Sharp LQ035Q7DB02 touch control enabled TFT LCD display assembly. The

ADS documentation CD contains specifications for the TFT LCD component.

CAUTION

Make sure that the input power to the main board is disconnected or switched off before connecting the LCD module. Connecting the module with power applied can damage the LCD module and/or the main board.

To use the TFT LCD display, connect the 34 conductor ribbon cable supplied with the ADS from J11 on the LCD module to P7 on the Base board.

The potentiometer VR1, which is to the left of the LCD panel just below J11, controls flickering of the display screen. This control is set at the factory and normally does not require adjustment. However, if the

TFT LCD display flickers, you may adjust VR1 to stabilize the display. Use a suitable flat head or phillips head screwdriver. Because the adjustment is normally done with power applied, we recommend use of a plastic blade tool.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

2-15

Configuration and Operation

2.5.2

Using the Keypad

To use the keypad module, connect the 20 conductor ribbon cable supplied with the ADS from connector

P1 of the Keypad module to P5 of the M9328MX21ADSE Base board.

2.5.3

Using a NAND Flash Card

CAUTION

To avoid circuit damage, do not plug-in the NAND Flash card with power applied to the board.

To use the NAND Flash module supplied with the ADS, connect PN1 & PN2 of the NAND Flash module to PM1 & PM2 on the CPU board. Before installing the card, make sure that S1-4 (the NEXUS_ON switch) is OFF and that the PCMCIA Daughter Card is not installed. For details on the NAND Flash interface, refer to the specification document on the documentation CD.

2.5.4

Using a SD/MMC Card

Connector P6 on the Base board is a SD/MMC card holder. You must obtain a compatible card for use with this connector. Note the card power is connected to 3.0 V

2.5.5

Using Image Sensor Daughter Card

Connector PE1 is pre-configured to operate directly with the IM8012 image sensor daughter card supplied with the ADS. Communication with this card takes place through the I

2

C interface. For details on image sensor operation, refer to the data sheet on the documentation CD

CAUTION

To avoid circuit damage, do not plug-in the image sensor card with power applied to the board.

To install the image sensor card, plug its 48 position DIN connector into PE1 of the Base board. When the image sensor card is installed, the two boards are at a right angle to each other, with the image sensor facing away from the Base board.

2.5.6

Using the PCMCIA Daughter Card

CAUTION

Make sure that the input power to the Base board is disconnected when installing the PCMCIA daughter card.

To use the PCMCIA daughter card supplied with the ADS, install the card in the sockets PK1 and PK2 on the CPU board. Before installing the daughter card, make sure that S1-4 (the NEXUS_ON switch) is OFF and that there is no NAND Flash card installed at PM1 & PM2.

You must supply a compatible PCMCIA card for use with the PCMCIA daughter card.

M9328MX21ADSE User’s Manual, Rev. A

2-16 Freescale Semiconductor

Configuration and Operation

2.5.7

Using the TV Encoder Card

A TV encoder card is supplied with the ADS. The main component is a FS453LF (PC to TV Video Scan converter) from FOCUS Enhancements Semiconductor. For details on TV encoder operation, refer to its data sheet, available at http://www.focusinfo.com/

CAUTION

Make sure that input power is disconnected or switched off before the TV encoder card is installed. Connecting the card with power applied can damage the TV encoder card and the Base board.

This TV encoder cannot be used at the same time as the LCD display because they share connector P7 on the Base board. To use the TV encoder module, you must disconnect the LCD board from P7 on the Base board and install the TV encoder module in P7 and P13 of the Base board.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

2-17

Configuration and Operation

2-18

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Chapter 3 Support Information

3.1

Introduction

This section contains connector pin assignments, connector signal descriptions, and other useful information about the M9328MX21ADSE. Both the CPU and Base board connectors are described.

The tables in this section list signal names as they appear in the schematics for the boards. The figures usually refer to the same signal name, but may substitute a generally accepted standard name for that function. For example, all RS-232 transmitted data signals are referred to as TXD regardless of which

RS-232 connector is being illustrated. Also, the use of “_B” at the end of a signal name indicates that the active state of the signal is logic level zero or ground potential (active low).

3.2

CPU to Base Board Connectors PX1, PX2, PY1, and PY2

The PX1 and PX2 connectors located at the bottom side of the ADS CPU card connect this board to the

ADS Base board through connectors PY1 and PY2 located on the top side of the board. Figure 3-1 shows

the pin assignments for the PX1 and PY1 connectors. Table 3-1 provides signal descriptions for these

connectors. Figure 3-2 shows the pin assignments for the PX2 and PY2 connectors and Table 3-2 provides

signal descriptions for these connectors.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-1

Support Information

OE_ACD

FLM_VSYNC_SPS

1

3

SPL_SPR

VCC

5

7

CLS

9

LSCLK

11

LD16_R4

13

LD14_R2

15

LD12_R0

17

LD10_G4

19

LD8_G2

21

LD6_G0

23

LD4_B4

25

LD2_B2

27

LD0_B0

29

UART3_RXD

31

UART3_TXD

33

USBG_RXDP

35

USBG_RXDM

37

USBG_TXDP

39

USBG_TXDM

41

USBG_SDA

43

P5V

45

USBH1_TXDP

47

USBH1_TXDM

49

USBH1_RXDP

51

USBH1_RXDM

53

USB_BYP_B

55

P5V

57

TP22

59

CLK_26

61

UART1_RTS

63

UART1_RXD

65

UART2_RTS

67

UART2_RXD

69

BOOT3

71

BOOT1

73

PWM0

75

JTAG_CTRL

77

RESET_IN_B

79

POR_B

81

CLKMODE0

83

B_CS5_B

85

B_CS1_B

87

B_OE_B

89

B_NEXUSEVTI

91

B_A0

93

B_A2

95

B_D7

97

B_D6

99

B_D5

101

B_D4

103

B_D3

105

B_D2

107

B_D1

109

B_D0

111

B_A20

113

B_A22

115

B_A24

117

TP25

119

PX1

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

VCC

CONTRAST

LP_HSYNC

PS

REV

LD17_R5

LD15_R3

LD13_R1

LD11_G5

LD9_G3

LD7_G1

LD5_B5

LD3_B3

LD1_B1

VCC

UART3_RTS

UART3_CTS

USBG_OE_B

USBG_ON_B

USBG_FS

USBG_SCL

P5V

USBH1_FS

USB_OC_B

USBH1_OE_B

USBH_ON_B

USB_PWR

USBOTG_EN

B_DQM3_EB3_B

GND

VCC

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

64

UART1_CTS

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

UART1_TXD

UART2_CTS

UART2_TXD

BOOT2

BOOT0

TIN

TOUT

RESET_OUT_B

RTCK_GPIO

CLKMODE1

B_CS4_B

B_CS0_B

B_RW_B

NEXUS_EN_B

B_A1

96

B_A3

• •

98

B_D15

• •

100 B_D14

• •

102 B_D13

• •

104 B_D12

• •

106 B_D11

• •

108 B_D10

• •

• •

• •

• •

110 B_D9

112 B_D8

114 B_A21

116 B_A23

• •

118 B_A25

• •

120 GND

Figure 3-1. CPU to Base Board PX1/PY1 Connector Pin Assignments

M9328MX21ADSE User’s Manual, Rev. A

3-2 Freescale Semiconductor

Support Information

Pin(s)

25

26

27

28

29

31

21

22

23

24

17

18

19

20

13

14

15

16

9

10

11

12

6

8

4

5

1

2, 7,

30, 62

3

Signal

OE_ACD

Table 3-1. CPU to Base Board PX1/PY1 Connector Signals

Description

OUTPUT ENABLE / ALTERNATE CRYSTAL DIRECTION

VCC +3.0 VDC power

LD10_G4

LD9_G3

LD8_G2

LD7_G1

LD6_G0

LD5_B5

LD4_B4

LD3_B3

LD2_B2

LD1_B1

LD0_B0

UART3_RXD

FLM_VSYNC_SPS FIRST LINE MARKER / VERTICAL SYNCHRONIZATION

CONTRAST

SPL_SPR

LCD bias voltage used as contrast control

SAMPLING LEFT to RIGHT— Horizontal scan direction

LP_HSYNC

PS

CLS

REV

LINE PULSE / HORIZONTAL SYNCHRONIZATION

Control signal output for source driver (Sharp panel dedicated signal)

Start signal output for gate driver. Inverted version of PS (Sharp panel dedicated signal)

Signal for common electrode driving signal preparation (Sharp panel dedicated signal)

LSCLK

LD17_R5

LD16_R4

LD15_R3

LD14_R2

LD13_R1

LD12_R0

LD11_G5

LCD SHIFT CLOCK — Output to LCD

LCD DATA 17 / RED BIT 5 — Output data to LCO

LCD DATA 16 / RED BIT 4 — Output data to LCD

LCD DATA 15 / RED BIT 3 — Output data to LCD

LCD DATA 14 / RED BIT 2 — Output data to LCD

LCD DATA 13 / RED BIT 1 — Output data to LCD

LCD DATA 12 / RED BIT 0 — Output data to LCD

LCD DATA 11 / GREEN BIT 5 — Output data to LCD

LCD DATA 10 / GREEN BIT 4 — Output data to LCD

LCD DATA 9 / GREEN BIT 3 — Output data to LCD

LCD DATA 8 / GREEN BIT 2 — Output data to LCD

LCD DATA 7 / GREEN BIT 1 — Output data to LCD

LCD DATA 6 / GREEN BIT 0 — Output data to LCD

LCD DATA 5 / BLUE BIT 5 — Output data to LCD

LCD DATA 4 / BLUE BIT 4 — Output data to LCD

LCD DATA 3 / BLUE BIT 3 — Output data to LCD

LCD DATA 2 / BLUE BIT 2 — Output data to LCD

LCD DATA 1 / BLUE BIT 1 — Output data to LCD

LCD DATA 0 / BLUE BIT 0 — Output data to LCD

UART3 RECEIVED DATA — Serial input signal

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-3

Support Information

Pin(s)

58

59

60, 120

61

63

64

65

53

54

55

56

49

50

51

52

40

41

42

43

44, 45, 57

46

47

48

36

37

38

39

32

33

34

35

Table 3-1. CPU to Base Board PX1/PY1 Connector Signals (continued)

Signal Description

UART3_RTS

UART3_TXD

UART3_CTS

USBG_RXDP

USBG_OE_B

USBG_RXDM

USBG_ON_B

USBG_TXDP

USBG_FS

USBG_TXDM

USBG_SCL

USBG_SDA

P5V

USBH1_FS

USBH1_TXDP

USB_OC_B

UART3 REQUEST TO SEND — Active low input signal

UART3 TRANSMITTED DATA — Serial output signal

UART3 CLEAR TO SEND — Active low output signal

USB OTG RECEIVED DATA PLUS input

USB OTG OUTPUT ENABLE

USB OTG RECEIVED DATA MINUS input

USB OTG transceiver ON

USB OTG TRANSMITTED DATA PLUS output

USB OTG FULL SPEED

USB OTG TRANSMITTED DATA MINUS output

USB OTG SERIAL CLOCK

USB OTG SERIAL DATA

Swithched +5 VDC power

USB FULL SPEED

USB TRANSMITTED DATA PLUS output

USB OVER CURRENT input low.

USBH1_TXDM

USBH1_OE_B

USBH1_RXDP

USBH_ON_B

USBH1_RXDM

USB_PWR

USB_BYP_B

USBOTG_EN

USB TRANSMITTED DATA MINUS output

USB OUTPUT ENABLE

USB RECEIVED DATA PLUS input

USB transceiver ON

USB RECEIVED DATA MINUS input

USB POWER output.

USB BY PASS input active low

Not used

B_DQM3_EB3_B BUFFERED ENABLE BYTE 3 — D[7:0] for SDRAM, D[31:24] for other memory types

TP22 Test point

GND

CLK_26

GROUND

26 MHz clock from TV Encoder Card

UART1_RTS

UART1_CTS

UART1_RXD

UART1 REQUEST TO SEND — Active low input signal

UART1 CLEAR TO SEND — Active low output signal

UART1 RECEIVED DATA — Serial input signal

M9328MX21ADSE User’s Manual, Rev. A

3-4 Freescale Semiconductor

90

91

92

93

94

95

Pin(s)

78

79

80

81

74

75

76

77

70

71

72

73

66

67

68

69

86

87

88

82

83

84

85

89

Support Information

Table 3-1. CPU to Base Board PX1/PY1 Connector Signals (continued)

Signal Description

UART1_TXD

UART2_RTS

UART2_CTS

UART2_RXD

UART2_TXD

BOOT3

BOOT2

BOOT1

UART1 TRANSMITTED DATA — Serial output signal

UART2 REQUEST TO SEND — Active low input signal

UART2 CLEAR TO SEND — Active low output signal

UART2 RECEIVED DATA — Serial input signal

UART2 TRANSMITTED DATA — Serial output signal

BOOT location select input bit 3

BOOT location select input bit 2

BOOT location select input bit 1

BOOT0

PWM0

TIN

JTAG_CTRL

BOOT location select input bit 0

PULSE WIDTH MODULATOR OUTPUT

TIMER INPUT CAPTURE — Timer input

JTAG CONTROL — input to select between and ARM and normal JTAG operation

TOUT

RESET_IN_B

TIMER OUTPUT

RESET IN — Active low reset signal to the processor

RESET_OUT_B RESET OUT — Active low reset signal from the processor

POR_B POWER ON RESET

RTCK_GPIO

CLKMODE0

CLKMODE1

B_CS5_B

B_CS4_B

B_CS1_B

B_CS0_B

B_OE_B

B_RW_B

B_NEXUSEVTI

NEXUS_EN_B

B_A0

B_A1

B_A2

RETURN CLOCK — JTAG signal, can be general purpose I/O

CLOCK MODE BIT 0 — Selects PLL bypass modes

CLOCK MODE BIT 1 — Selects PLL bypass modes

BUFFERED CHIP SELECTS 5 — Chip select signal, active low output (Reserved)

BUFFERED CHIP SELECTS 4 — Chip select signal, active low output (Reserved)

BUFFERED CHIP SELECTS 1 — Chip select signal, active low output

BUFFERED CHIP SELECTS 0 — Chip select signal, active low output (Reserved)

BUFFERED OUTPUT ENABLE— Enables external devices to drive the data bus, active low output

BUFFERED READ/WRITE — A low indicates an external write operation, a high indicates a read operation type

Internal use only

Internal use only

BUFFERED ADDRESS 0— Buffered address output (Reserved)

BUFFERED ADDRESS 1— Buffered address output

BUFFERED ADDRESS 2 — Buffered address output

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-5

Pin(s)

108

109

110

111

104

105

106

107

100

101

102

103

96

97

98

99

116

117

118

119

112

113

114

115

Support Information

Table 3-1. CPU to Base Board PX1/PY1 Connector Signals (continued)

Signal

B_D12

B_D3

B_D11

B_D2

B_D10

B_D1

B_D9

B_D0

B_A3

B_D7

B_D15

B_D6

B_D14

B_D5

B_D13

B_D4

B_D8

B_A20

B_A21

B_A22

B_A23

B_A24

B_A25

TP25

Description

BUFFERED ADDRESS 3 — Buffered address output

BUFFERED DATA 7— Buffered bidirectional data bus bit

BUFFERED DATA 15 — Buffered bidirectional data bus bit

BUFFERED DATA 6 — Buffered bidirectional data bus bit

BUFFERED DATA 14 — Buffered bidirectional data bus bit

BUFFERED DATA 5— Buffered bidirectional data bus bit

BUFFERED DATA 13 — Buffered bidirectional data bus bit

BUFFERED DATA 4 — Buffered bidirectional data bus bit

BUFFERED DATA 12 — Buffered bidirectional data bus bit

BUFFERED DATA 3 — Buffered bidirectional data bus bit

BUFFERED DATA 11 — Buffered bidirectional data bus bit

BUFFERED DATA 2 — Buffered bidirectional data bus bit

BUFFERED DATA 10— Buffered bidirectional data bus bit

BUFFERED DATA 1 — Buffered bidirectional data bus bit

BUFFERED DATA 9— Buffered bidirectional data bus bit

BUFFERED DATA 0— Buffered bidirectional data bus bit

BUFFERED DATA 8— Buffered bidirectional data bus bit

BUFFERED ADDRESS 20 — Buffered address output (Reserved)

BUFFERED ADDRESS 21 — Buffered address output

BUFFERED ADDRESS 22 — Buffered address output

BUFFERED ADDRESS 23 — Buffered address output

BUFFERED ADDRESS 24 — Buffered address output (Reserved)

BUFFERED ADDRESS 25 — Buffered address output (Reserved)

Test point

3-6

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

VCC 61

CPU_BD_ID7 63

CPU_BD_ID6 65

CPU_BD_ID5 67

CPU_BD_ID4 69

KP_COL5 71

KP_COL4 73

KP_COL3 75

KP_COL2 77

KP_COL1 79

KP_COL0 81

B_DQM0_EB0_B 83

B_DQM2_EB2_B 85

B_A4 87

B_A6 89

B_A8 91

B_A10 93

B_A12 95

B_A14 97

B_A16 99

B_A18 101

B_D16 103

B_D18 105

B_D20 107

B_D22 109

B_D24 111

B_D26 113

B_D28 115

B_D30 117

RESET_SW 119

SD1_D3

SD1_D2

1

3

SD1_D1

SD1_D0

5

7

SD2_CLK 9

SD2_D3 11

SD2_D1 13

CSI_HSYNC 15

CSI_PIXCLK 17

CSI_D7 19

CSI_D5 21

CSI_D3 23

CSI_D1 25

I2C_CLK 27

SSI3_CLK 29

SSI3_RXD 31

SSI2_CLK 33

SSI2_RXD 35

SSI1_CLK 37

SSI1_RXD 39

SAP_CLK 41

SAP_FS 43

CSPI1_MOSI 45

CSPI1_SCLK 47

CSPI1_SS1 49

CSPI1_RDY 51

CSPI2_MOSI 53

CSPI2_SCLK 55

CSPI2_SS1 57

P5V 59

PX2

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

VCC

SD1_CMD

SD1_CLK

VCC

SD2_CMD

SD2_D2

SD2_D0

CSI_VSYNC

CSI_MCLK

CSI_D6

CSI_D4

CSI_D2

CSI_D0

IS2_DATA

SSI3_TXD

SSI3_FS

SSI2_TXD

SSI2_FS

SSI1_TXD

SSI1_FS

SAP_RXD

SAP_TXD

CSPI1_MISO

CSPI1_SS0

CSPI1_SS2

VCC

CSPI2_MISO

CSPI2_SS0

CSPI2_SS2

P5V

CPU_BD_ID0

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

• •

64 CPU_BD_ID1

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

CPU_BD_ID2

CPU_BD_ID3

VCC

KP_ROW5

KP_ROW4

KP_ROW3

KP_ROW2

KP_ROW1

KP_ROW0

B_DQM1_EB1_B

TP21

B_A5

B_A7

B_A9

B_A11

96 B_A13

• •

98 B_A15

• •

100 B_A17

• •

102 B_A19

• •

104 B_D17

• •

106 B_D19

• •

108 B_D21

• •

• •

• •

• •

110 B_D23

112 B_D25

114 B_D27

116 B_D29

• •

118 B_D31

• •

120 GND

Figure 3-2. CPU to Base Board PX2/PY2 Connector Pin Assignments

Support Information

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-7

Support Information

Pin(s)

22

21

23

24

17

18

19

20

25

26

27

28

13

14

15

16

9

10

11

12

1

2, 8,

52, 61, 70

3

6

7

4

5

29

SD1_D2

SD1_CMD

SD1_D1

SD1_CLK

SD1_D0

SD2_CLK

SD2_CMD

SD2_D3

SD2_D2

SD2_D1

SD2_D0

CSI_HSYNC

CSI_VSYNC

CSI_PIXCLK

CSI_MCLK

CSI_D7

CSI_D6

CSI_D5

CSI_D4

CSI_D3

CSI_D2

CSI_D1

CSI_D0

I2C_CLK

IS2_DATA

SSI3_CLK

Signal

SD1_D3

Table 3-2. CPU to Base Board PX2/PY2 Connector Signals

Description

SD/MMC DATA BIT 3 — Serial data bit to SD/MMC card, bidirectional

VCC +3.0 VDC power

SD/MMC DATA BIT 2 — Serial data bit to SD/MMC card, bidirectional

SD/MMC COMMAND — Serial command bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 1 — Serial data bit to SD/MMC card, bidirectional

SD/MMC CLOCK — Clock output to SD/MMC card

SD/MMC DATA BIT 0 — Serial data bit to SD/MMC card, bidirectional

SD/MMC CLOCK — Clock output to SD/MMC card

SD/MMC COMMAND — Serial command bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 3 — Serial data bit to SD/MMC card, bidirectional

SD/MMC COMMAND — Serial command bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 1 — Serial data bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 2 — Serial data bit to SD/MMC card, bidirectional

CMOS SENSOR INTERFACE HORIZONTAL SYNC— Control input

CMOS SENSOR INTERFACE VERTICAL SYNC — Control input

CMOS SENSOR INTERFACE PIXAL CLOCK — Data latch strobe

CMOS SENSOR INTERFACE MASTER CLOCK — Clock output to sensor card

CMOS SENSOR INTERFACE DATA 7— Image Sensor input data

CMOS SENSOR INTERFACE DATA 6— Image Sensor input data

CMOS SENSOR INTERFACE DATA 5— Image Sensor input data

CMOS SENSOR INTERFACE DATA 4— Image Sensor input data

CMOS SENSOR INTERFACE DATA 3— Image Sensor input data

CMOS SENSOR INTERFACE DATA 2— Image Sensor input data

CMOS SENSOR INTERFACE DATA 1— Image Sensor input data

CMOS SENSOR INTERFACE DATA 0— Image Sensor input data

I SQUARED C CLOCK — Serial clock, bidirectional

I SQUARED C DATA — Serial data, bidirectional

SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK — Bidirectional, output in master mode and input in slave mode

M9328MX21ADSE User’s Manual, Rev. A

3-8 Freescale Semiconductor

34

35

36

37

Pin(s)

30

31

32

33

42

43

53

54

55

56

57

58

59, 60

48

49

50

51

44

45

46

47

38

39

40

41

Support Information

SAP_TXD

CSPI1_MOSI

CSPI1_MISO

CSPI1_SCLK

CSPI1_SS0

CSPI1_SS1

CSPI1_SS2

CSPI1_RDY

CSPI2_MOSI

CSPI2_MISO

CSPI2_SCLK

CSPI2_SS0

CSPI2_SS1

CSPI2_SS2

P5V

Table 3-2. CPU to Base Board PX2/PY2 Connector Signals (continued)

Signal

SSI3_TXD

SSI3_RXD

SSI3_FS

SSI2_CLK

SSI2_TXD

SSI2_RXD

SSI2_FS

SSI1_CLK

SSI1_TXD

SSI1_RXD

SSI1_FS

SAP_CLK

SAP_RXD

SAP_FS

Description

SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA — Serial output signal

SYCHRONOUS SERIAL INTERFACE RECEIVED DATA — Serial input signal

SYCHRONOUS SERIAL INTERFACE FRAME SYNC

SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK — Bidirectional, output in master mode and input in slave mode

SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA — Serial output signal

SYCHRONOUS SERIAL INTERFACE RECEIVED DATA — Serial input signal

SYCHRONOUS SERIAL INTERFACE FRAME SYNC

SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK — Bidirectional, output in master mode and input in slave mode

SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA — Serial output signal

SYCHRONOUS SERIAL INTERFACE RECEIVED DATA — Serial input signal

SYCHRONOUS SERIAL INTERFACE FRAME SYNC

SYCHRONOUS AUDIO PORT CLOCK — Serial transmit clock, bidirectional, output in master mode, input in slave mode

SYCHRONOUS AUDIO PORT RECEIVED DATA — Serial data input

SYCHRONOUS AUDIO PORT FRAME SYNC — Bidirectional, output in master mode, input in slave mode

SYCHRONOUS AUDIO PORT TRANMITTED DATA — Serial data output

MASTER OUT / SLAVE IN — CSPI data signal (bidirectional)

MASTER IN / SLAVE OUT — CSPI data signal (bidirectional)

SERIAL CLOCK — Bidirectional

SLAVE SELECT 0 — CSPI signal (bidirectional)

SLAVE SELECT 1 — CSPI signal (bidirectional)

SLAVE SELECT 2 — CSPI signal (bidirectional)

READY — CSPI serial burst trigger, active low input

MASTER OUT / SLAVE IN — CSPI data signal (bidirectional)

MASTER IN / SLAVE OUT — CSPI data signal (bidirectional)

SERIAL CLOCK — Bidirectional

SLAVE SELECT 0 — CSPI signal (bidirectional)

SLAVE SELECT 1 — CSPI signal (bidirectional)

SLAVE SELECT 2 — CSPI signal (bidirectional)

Swithched +5 VDC power

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-9

Pin(s)

75

76

77

78

71

72

73

74

79

80

81

82

66

67

68

69

62

63

64

65

Support Information

83

84

85

86

87

88

89

90

91

Table 3-2. CPU to Base Board PX2/PY2 Connector Signals (continued)

Signal Description

CPU_BD_ID0 CPU BOARD ID 0 — Indicates the build revision of the CPU board

CPU_BD_ID7 CPU BOARD ID 1 — Indicates the build revision of the CPU board

CPU_BD_ID1 CPU BOARD ID 2 — Indicates the build revision of the CPU board

CPU_BD_ID6 CPU BOARD ID 3 — Indicates the build revision of the CPU board

CPU_BD_ID2 CPU BOARD ID 4 — Indicates the build revision of the CPU board

CPU_BD_ID5 CPU BOARD ID 5 — Indicates the build revision of the CPU board

CPU_BD_ID3 CPU BOARD ID 6 — Indicates the build revision of the CPU board

CPU_BD_ID4 CPU BOARD ID 7 — Indicates the build revision of the CPU board

KP_COL5

KP_ROW5

KP_COL4

KP_ROW4

KP_COL3

KP_ROW3

KP_COL2

KP_ROW2

KEYPAD COLUMN 5 — Bidirectional signal use to scan a keypad

KEYPAD ROW 5 — Bidirectional signal use to scan a keypad

KEYPAD COLUMN 4 — Bidirectional signal use to scan a keypad

KEYPAD ROW 4 — Bidirectional signal use to scan a keypad

KEYPAD COLUMN 3 — Bidirectional signal use to scan a keypad

KEYPAD ROW 3 — Bidirectional signal use to scan a keypad

KEYPAD COLUMN 2 — Bidirectional signal use to scan a keypad

KEYPAD ROW 2 — Bidirectional signal use to scan a keypad

KP_COL1

KP_ROW1

KP_COL0

KP_ROW0

KEYPAD COLUMN 1 — Bidirectional signal use to scan a keypad

KEYPAD ROW 1 — Bidirectional signal use to scan a keypad

KEYPAD COLUMN 0 — Bidirectional signal use to scan a keypad

KEYPAD ROW 0 — Bidirectional signal use to scan a keypad

B_DQM0_EB0_B

BUFFERED ENABLE BYTE 0 — D[31:24] for SDRAM, [D7:0] for other memory types

(Reserved)

B_DQM1_EB1_B

BUFFERED ENABLE BYTE 1 — D[23:16] for SDRAM, D[15:8] for other memory types

(Reserved)

B_DQM2_EB2_B

BUFFERED ENABLE BYTE 2 — D[15:8] for SDRAM, D[23:16] for other memory types

(Reserved)

TP21

B_A4

B_A5

B_A6

B_A7

B_A8

Test point

BUFFERED ADDRESS 4 — Buffered address output (Reserved)

BUFFERED ADDRESS 5 — Buffered address output (Reserved)

BUFFERED ADDRESS 6 — Buffered address output (Reserved)

BUFFERED ADDRESS 7 — Buffered address output (Reserved)

BUFFERED ADDRESS 8 — Buffered address output (Reserved)

M9328MX21ADSE User’s Manual, Rev. A

3-10 Freescale Semiconductor

Pin(s)

112

113

114

115

108

109

110

111

116

117

118

119

120

104

105

106

107

100

101

102

103

96

97

98

99

92

93

94

95

Table 3-2. CPU to Base Board PX2/PY2 Connector Signals (continued)

Signal

B_D21

B_D22

B_D23

B_D24

B_D25

B_D26

B_D27

B_D28

B_D29

B_D30

B_D31

RESET_SW

GND

B_A17

B_A18

B_A19

B_D16

B_D17

B_D18

B_D19

B_D20

B_A9

B_A10

B_A11

B_A12

B_A13

B_A14

B_A15

B_A16

Description

BUFFERED ADDRESS 9 — Buffered address output (Reserved)

BUFFERED ADDRESS 10 — Buffered address output (Reserved)

BUFFERED ADDRESS 11 — Buffered address output (Reserved)

BUFFERED ADDRESS 12 — Buffered address output (Reserved)

BUFFERED ADDRESS 13 — Buffered address output (Reserved)

BUFFERED ADDRESS 14 — Buffered address output (Reserved)

BUFFERED ADDRESS 15 — Buffered address output (Reserved)

BUFFERED ADDRESS 16 — Buffered address output (Reserved)

BUFFERED ADDRESS 17 — Buffered address output (Reserved)

BUFFERED ADDRESS 18 — Buffered address output (Reserved)

BUFFERED ADDRESS 19 — Buffered address output (Reserved)

BUFFERED DATA 16 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 17 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 18 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 19 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 20 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 21 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 22 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 23 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 24 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 25 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 26 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 27 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 28 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 29 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 30 — Buffered data (bidirectional) (Reserved)

BUFFERED DATA 31 — Buffered data (bidirectional) (Reserved)

RESET SWITCH Connected to the Reset switch on the Base board

GROUND

Support Information

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-11

Support Information

3.3

CPU to Option Card Connectors

The PK1 and PK2 connectors located at the top side of the ADS CPU card are used to connect the board to option cards. The option cards are designed to add new capabilities to the ADS. A number of option cards, such as the PCMCIA Adaptor Card, are available. You may want to develop your own add-on cards.

Figure 3-3 shows pin assignments for the PK1 connector and Table 3-3 provides signal descriptions for the

connector. Figure 3-4 shows pin assignments for the PK2 connector and Table 3-4 provides signal

descriptions for the connector.

PK1

VCC

PWMO

RESET_IN_B

1

3

5

RESET_OUT_B 7

• •

2 CS0_B

• •

4 TP13

• •

6 P2.5V

• •

8 NEXUSEVTI_GPIO

P2.5V

9

• •

10 SDCKE1

RW_B 11

• •

12 BCLK

CS5_B 13

• •

14 CLKO

CS3_B 15

• •

16 CS4_B

P1.8V

17

• •

18 CS1_B

A0 19

• •

20 A1

D7 21

• •

22 D8

D6 23

• •

24 D9

D5 25

• •

26 D10

D4 27

• •

28 D11

D3 29

• •

30 D12

D2 31

• •

32 D13

D1 33

• •

34 D14

D0 35

• •

36 D15

DQM1_EB1_B 37

• •

38 SDCLK

DQM0_EB0_B 39

• •

40 A18

SDCKE0 41

• •

42 A17

MA10 43

• •

44 A10

VCC 45

• •

46 A9

A16 47

• •

48 A7

A14 49

• •

50 A6

P1.8V

51

• •

52 A8

A15 53

• •

54 A11

A13 55

• •

56 P5V

A12 57

• •

58 OE_B

P5V 59

• •

60 ECB_B

Figure 3-3. CPU to Option Card PK1 Connector Pin Assignments

3-12

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Support Information

12

25

26

27

28

21

22

23

24

17, 51

18

19

20

13

14

15

16

29

30

31

Pin(s)

5

6, 9

7

8

1, 45

2

3

4

10

11

D5

D10

D4

D11

D7

D8

D6

D9

CS5_B

CLKO

CS3_B

CS4_B

P1.8v

CS1_B

A0

A1

D3

D12

D2

BCLK

Table 3-3. CPU to Option Card PK1 Connector Signals

Signal

VCC

CS0_B

PWMO PC_SPKOUT

TP13

RESET_IN_B

P2.5V

RESET_OUT_B

NEXUSEVTI_GPIO

SDCKE1

RW_B PC_WE

Description

+3.0 VDC power

CHIP SELECT 0 — Chip select signal, active low output

PCMCIA SPEAKER OUT — Digital audio output to drive a speaker*

Test point

RESET IN — Active low reset signal to the processor

+2.5 VDC power

RESET OUT — Active low reset signal from the processor

NEXUS EVENT IN — can be general purpose I/O

SDRAM CLOCK ENABLE 1 — Active high outputs to SDRAM

PCMCIA — Output signal used to latch memory write data*

BURST CLOCK — Output signal to external burst devices; synchronizes burst loading and incrementing

CHIP SELECT 5 — Chip select signal, active low output

CLOCK OUT — Clock out from the processor, NC if R44 not installed

CHIP SELECT 3 — Chip select signal, active low output

CHIP SELECT 4 — Chip select signal, active low output

+1.8 VDC power

CHIP SELECT 1 — Chip select signal, active low output

ADDRESS BIT 0 — Output line for addressing external devices.

ADDRESS BIT 1 — Output line for addressing external devices.

DATA BIT 7 — Bidirectional data bit from the processor

DATA BIT 8 — Bidirectional data bit from the processor

DATA BIT 6 — Bidirectional data bit from the processor

DATA BIT 9 — Bidirectional data bit from the processor

DATA BIT 5 — Bidirectional data bit from the processor

DATA BIT 10 — Bidirectional data bit from the processor

DATA BIT 4 — Bidirectional data bit from the processor

DATA BIT 11 — Bidirectional data bit from the processor

DATA BIT 3 — Bidirectional data bit from the processor

DATA BIT 12 — Bidirectional data bit from the processor

DATA BIT 2 — Bidirectional data bit from the processor

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-13

Support Information

Table 3-3. CPU to Option Card PK1 Connector Signals

Pin(s) Signal Description

44

46

47

48

40

41

42

43

36

37

38

39

32

33

34

35

D13

D1

D14

D0

D15

DQM1_EB1_B

SDCLK

DQM0_EB0_B

A18

SDCKE0

A17

MA10

A10

A9

A16

A7

DATA BIT 13 — Bidirectional data bit from the processor

DATA BIT 1 — Bidirectional data bit from the processor

DATA BIT 14 — Bidirectional data bit from the processor

DATA BIT 0 — Bidirectional data bit from the processor

DATA BIT 15 — Bidirectional data bit from the processor

ENABLE BYTE 1 — D23-D16 for SDRAM, D15-D8 for other memory types

SDRAM CLOCK — Main clock signal to SDRAM devices

ENABLE BYTE 0 — D31-D24 for SDRAM, D7-D0 for other memory types

ADDRESS BIT 18 — Output line for addressing external devices

SDRAM CLOCK ENABLE 0 — Active high outputs to SDRAM

ADDRESS BIT 17 — Output line for addressing external devices

MULTIPLEXED ADDRESS BIT 1O — Multiplexed address bit to SDRAM

ADDRESS BIT 10 — Output line for addressing external devices

ADDRESS BIT 9 — Output line for addressing external devices

ADDRESS BIT 16 — Output line for addressing external devices

ADDRESS BIT 7 — Output line for addressing external devices

54

55

56, 59

57

49

50

52

53

A14

A6

A8

A15

A11

A13

P5V

A12

ADDRESS BIT 14 — Output line for addressing external devices

ADDRESS BIT 6 — Output line for addressing external devices

ADDRESS BIT 8 — Output line for addressing external devices

ADDRESS BIT 15 — Output line for addressing external devices

ADDRESS BIT 11 — Output line for addressing external devices

ADDRESS BIT 13 — Output line for addressing external devices

Switched +5 VDC power

ADDRESS BIT 12 — Output line for addressing external devices

58

60

OE_B PC_IOWR

ECB_B

PCMCIA IO WRITE— Active low output for I/O writes*

END CURRENT BURST — Active low input signal asserted by external burst devices

* The signal name in italics is the function intended for operation with this connector. It is multiplexed inside the i.MX21 processor with the listed signal.

3-14

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

VCC 1

NFIO0 3

NFIO2 5

NFIO4 7

P2.5V

9

NFIO6 11

NFWE_B 13

NFALE 15

NFWP_B 17

NFRB 19

D23 21

D22 23

D21 25

D20 27

D19 29

D18 31

D17 33

D16 35

SDWE_B 37

A20 39

A19 41

A3 43

A4 45

A5 47

A2 49

A21 51

P1.8V

53

TP12 55

TP13 57

TP14 59

PK2

• •

• •

• •

• •

2

4

6

NFIO1

NFIO3

P2.5V

8 NFIO5

• •

10 NFIO7

• •

12 NFRE_B

• •

14 P1.8V

• •

16 NFCLE

• •

18 NFCE_B

• •

20 PC_PWRON

• •

22 D24

• •

24 D25

• •

26 D26

• •

28 D27

• •

30 D28

• •

32 D29

• •

34 D30

• •

36 D31

• •

38 RAS_B

• •

40 CAS_B

• •

42 CS2_B

• •

44 MA11

• •

46 DQM2_EB2_B

• •

48 DQM3_EB3_B

• •

50 A23

• •

52 A22

• •

54 LBA_B

• •

56 A24

• •

58 A25

• •

60 VCC

Figure 3-4. CPU to Option Card PK2 Connector Pin Assignments

Support Information

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-15

Support Information

Pin(s)

26

27

28

29

30

31

22

23

24

25

18

19

20

21

14, 53

15

16

17

10

11

12

13

5

6, 9

7

8

1, 60

2

3

4

3-16

Table 3-4. CPU to Option Card PK2 Connector Signals

Signal

NFCE_B PC_CE1

NFRB PC_RST

PC_PWRON

D23

D24

D22

D25

D21

D26

D20

D27

D19

D28

D18

VCC

NFIO1 PC_VS2

NFIO0 PC_BVD1

NFIO3 PC_WP

NFIO2 PC_VS1

P2.5V

NFIO4 PC_READY

NFIO5 PC_WAIT

NFIO7 PC_CD1

NFIO6 PC_CD2

NFRE_B PC_RW

NFWE_B PC_BVD2

P1.8V

NFALE PC_OE

NFCLE PC_POE

NFWP_B PC_CE2

Description

+3.0 VDC power

PCMCIA VOLTAGE SENSE 2 — Input signal to select card voltage*

PCMCIA BATTERY VOLTAGE DETECT 1 — Input signal to report battery status*

PCMCIA WRITE PROTECT — Input signal from the PCMCIA card*

PCMCIA VOLTAGE SENSE 1 input signal to select PCMCIA card voltage*

+ 2.5 VDC power

PCMCIA READY — Input signal to indicate the card is ready for access*

PCMCIA WAIT — Input signal to extend the current access*

PCMCIA CARD DETECT 1 — Input signal to indicate a card is inserted*

PCMCIA CARD DETECT 2 — Input signal to indicate a card is inserted*

PCMCIA READ/WRITE — Data direction control, active low to write*

PCMCIA BATTERY VOLTAGE DETECT 2 — Input signal to report battery status*

+1.8 VDC power

PCMCIA OUTPUT ENABLE — Output used to enable memory read data*

PCMCIA Buffer OUTPUT ENABLE — Output used tri-state control signals*

PCMCIA CARD ENABLE 2 — Output used to enable odd bytes*

PCMCIA CARD ENABLE 1 — Output used to enable even bytes*

PCMCIA RESET — Output to reset a card’s Configuration Option Register*

PCMCIA input to indicate card power is applied and stable

DATA BIT 23 — Bidirectional data bit from the processor

DATA BIT 24 — Bidirectional data bit from the processor

DATA BIT 22 — Bidirectional data bit from the processor

DATA BIT 25 — Bidirectional data bit from the processor

DATA BIT 21 — Bidirectional data bit from the processor

DATA BIT 26 — Bidirectional data bit from the processor

DATA BIT 20 — Bidirectional data bit from the processor

DATA BIT 27 — Bidirectional data bit from the processor

DATA BIT 19 — Bidirectional data bit from the processor

DATA BIT 28 — Bidirectional data bit from the processor

DATA BIT 18 — Bidirectional data bit from the processor

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Support Information

Table 3-4. CPU to Option Card PK2 Connector Signals (continued)

Pin(s) Signal Description

44

45

46

47

40

41

42

43

36

37

38

39

32

33

34

35

D29

D17

D30

D16

D31

SDWE_B

RAS_B

A20

CAS_B

A19

CS2_B

A3

MA11

A4

DQM2_EB2_B PC_REG

A5

DATA BIT 29 — Bidirectional data bit from the processor

DATA BIT 17 — Bidirectional data bit from the processor

DATA BIT 30 — Bidirectional data bit from the processor

DATA BIT 16 — Bidirectional data bit from the processor

DATA BIT 31 — Bidirectional data bit from the processor

SDRAM WRITE ENABLE — Write data strobe to SDRAM, active low

ROW ADDRESS STROBE — Clocks row address to SDRAM

ADDRESS BIT 20 — Output line for addressing external devices

COLUMN ADDRESS STROBE — clocks column address to SDRAM

ADDRESS BIT 19 — Output line for addressing external devices

CHIP SELECT 2 — Chip select signal, active low output

ADDRESS BIT 3 — Output line for addressing external devices

MULTIPLEXED ADDRESS BIT 11 — Multiplexed address bit to SDRAM

ADDRESS BIT 4 — Output line for addressing external devices

PCMCIA REGISTER SELECT — Output to select Attribute Memory*

ADDRESS BIT 5 — Output line for addressing external devices

48

49

50

51

52

54

55

56

57

DQM3_EB3_B PC_IORD PCMCIA I/O READ — Output signals to read I/O*

A2 ADDRESS BIT 2 — Output line for addressing external devices

A23

A21

A22

ADDRESS BIT 23 — Output line for addressing external devices

ADDRESS BIT 21 — Output line for addressing external devices

LBA_B

TP12

ADDRESS BIT 22 — Output line for addressing external devices

LOAD BURST ADDRESS — Active low signal asserted during burst mode accesses

Test point

A24

TP13

ADDRESS BIT 24 — Output line for addressing external devices

Test point

58

59

A25

TP14

ADDRESS BIT 25 — Output line for addressing external devices

Test point

*The signal name in italics is the function intended for operation with this connector. It is multiplexed inside the i.MX21 processor with the listed signal.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-17

Support Information

3.4

UART/RS-232 Connectors

This section describes the DB9 RS-232 serial interface connectors on the ADS. Each serial interface is controlled by a UART that is either inside the i.MX21 processor or part of an external device.

3.4.1

UART1 Connector

Connector P1 connects to the UART1 pins of the i.MX21 MCU. UART1 is the primary functionality of

the pins. This female DB9 connector is configured for RS-232 DCE operation. Figure 3-5 shows pin assignments and Table 3-5 provides signal descriptions for the connector.

5

G

ND

4

DT

R

3

RX

D

2

TX

D

1

CD

P1

RI

9 8 7 6

CT

S

RT

S

DS

R

Figure 3-5. Connector P1 (UART1) DCE Pin Assignments

Table 3-5. Connector P1 (UART1) DCE Signal Descriptions

Pin(s) Signal

7

8

5

6

9

3

4

1

2

Description

CD CARRIER DETECT — RS-232 output signal, pulled active positive

TXD TRANSMITTED DATA — RS-232 serial data output signal

RXD RECEIVED DATA — RS-232 serial data input signal

DTR DATA TERMINAL READY — RS-232 input signal, the logic level signal is available at TP8

GND GROUND

DSR DATA SET READY — RS-232 output signal, pulled active positive

RTS READY TO SEND — RS-232 input signal, active positive

CTS CLEAR TO SEND — RS-232 output signal, active positive

RI RING INDICATOR — RS-232 output signal, forced inactive negative

3-18

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Support Information

3.4.2

UART4 Connector

Connector P2 connects to the UART4 pins of the i.MX21 MCU. UART4 is the secondary functionality of

these pins. This male DB9 connector is configured for RS-232 DTE operation. Figure 3-6 shows pin assignments and Table 3-6 provides signal descriptions for the connector.

1

CD

2

RX

D

3

TX

D

4

DT

R

5

G

ND

P2

DS

6 7 8 9

R

RT

S

CT

S

RI

Figure 3-6. Connector P2 (UART4) DTE Pin Assignments

Table 3-6. Connector P2 (UART4) DTE Signal Descriptions

Pin Signal Description

1

2

3

CD CARRIER DETECT — RS-232 input signal, can be jumpered to SD2_D2 at J5 or ignored

RXD

TXD

RECEIVED DATA — RS-232 serial data input signal, connected to USBH1_TXDP when

UART4 is enable.

TRANSMITTED DATA — RS-232 serial data output signal, connected to USBH1_TXDM when UART4 is enabled

4 DTR

DATA TERMINAL READY — RS-232 output signal, can be jumpered to SD2_D0 or forced active positive at J3

5 GND GROUND

6 DSR

DATA SET READY — RS-232 input signal, can be jumpered to SD2_D1 at J4 or ignored, active positive

7

8

9

RTS

CTS

RI

READY TO SEND — RS-232 output signal, active positive, connected to USBH1_RXDM when UART4 is enabled

CLEAR TO SEND — RS-232 input signal, active positive, connected to USBH1_RXDP when UART4 is enabled

RING INDICATOR — RS-232 input signal, active positive, can be jumpered to SD2_D3 at

J6 or ignored

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-19

Support Information

3.4.3

External UART Connector

Connector P3 is connected to Port A of U17, an Exar ST16C255 DUART. This female DB9 connector is

configured for RS-232 Data Communications Equipment (DCE) operation. Figure 3-7 shows the pin assignments and Table 3-7 provides signal descriptions for the connector.

5

G

ND

4

DT

R

3

RX

D

2

TX

D

1

CD

P3

RI

9 8 7 6

CT

S

RT

S

DS

R

Figure 3-7. Connector P3 (EXT UART) DCE Pin Assignments

Table 3-7. Connector P3 (EXT UART) DCE Signal Descriptions

7

8

5

6

9

Pin(s) Signal

1

2

3

4

CD

TXD

Description

CARRIER DETECT — RS-232 output signal, pulled active positive

TRANSMITTED DATA — RS-232 serial data output signal

RXD RECEIVED DATA – RS-232 serial data input signal

DTR

DATA TERMINAL READY — RS-232 serial data input signal, the logic level signal is available at TP9

GND GROUND

DSR DATA SET READY — RS-232 output signal, pulled active positive

RTS READY TO SEND — RS-232 input signal, active positive,

CTS CLEAR TO SEND — RS-232 output signal, active positive,

RI RING INDICATOR — RS-232 output signal, forced inactive negative

3.5

Multi-ICE Connector

Connector P20 is the ADS Multi-ICE connector. Figure 3-8 shows pin assignments and Table 3-8 provides

signal descriptions for the connector.

P20

VCC 1

• •

TRST_B 3

• •

TDI 5

• •

TMS 7

• •

TCK 9

• •

RTCK 11

• •

TDO 13

• •

RESET_IN_B 15

• •

NC 17

• •

NC 19

• •

2 VCC

4 GND

6 GND

8 GND

10 GND

12 GND

14 GND

16 GND

18 GND

20 GND

Figure 3-8. Multi-ICE Connector P20 (on the CPU) Pin Assignments

M9328MX21ADSE User’s Manual, Rev. A

3-20 Freescale Semiconductor

Support Information

Table 3-8. Multi-ICE Connector P20 (on the CPU) Signal Descriptions

Pin(s)

1, 2

3

4, 6, 8, 10, 12,

14, 16, 18, 20

5

7

9

11

13

15

17, 19

Signal Description

VCC +3.0 VDC power

TRST_B TARGET RESET — Active low output signal that resets the target

GND GROUND

TDI

TMS

TEST DATA INPUT — Serial data output line, sampled on the rising edge of the TCK signal

TEST MODE SELECT – Output signal that sequences the target’s JTAG state machine, sampled on the rising edge of the TCK signal

TCK

RTCK

TDO

TEST CLOCK — Output timing signal, for synchronizing test logic and control register access

RETURN CLOCK

JTAG TEST DATA OUTPUT — Serial data input from the target

RESET_IN_B RESET IN — Active low reset signal to the processor

NC NO CONNECTION

3.6

Ethernet Connector

Connector P9 is the RJ-45 Ethernet connector for the ADS. Figure 3-9 shows pin numbering and Table 3-9

provides signal descriptions for the connector.

1

Figure 3-9. Ethernet Connector P9 Pin Numbers

Table 3-9. Ethernet Connector P9 Signal Descriptions

Pin(s) Signal Description

1

2

TPO+ DIFFERENTIAL OUTPUT PLUS

TPO- DIFFERENTIAL OUTPUT MINUS

3 TPI+ DIFFERENTIAL INPUT PLUS

4, 5, 7, 8 NC NO CONNECTION

6 TPIDIFFERENTIAL INPUT MINUS

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-21

Support Information

3.7

USB OTG Connector

Connector P4 is the USB OTG connector. Figure 3-10 shows pin assignments and Table 3-10 provides

signal descriptions for the connector.

1 2 3 4 5

Figure 3-10. USB Connector P4 Pin Assignments

Table 3-10. USB OTG Connector P4 Signal Descriptions

Pin(s) Signal

3

4

1

2

5

Description

VBUS VBUS

D-

D+

ID

USB DATA MINUS

USB DATA PLUS

ID

GND GROUND

3.8

NAND Flash Connector

PM1 and PM2 on the CPU board allow the ADS to interface with a NAND Flash module. Figure 3-12 and

Figure 3-12 show pin assignments. Table 3-12 and Table 3-12 provide signal descriptions for the

connectors.

PM1

P1.8V

TP26

P2.5V

1

3

5

• •

• •

• •

• •

2

4

6

NC

NFRB

NFRE_B

TP27

VCC

7

9

8 NFCE_B

• •

10 NFCLE

NC 11

• •

12 NFALE

NC 13

• •

14 NFWE_B

NC 15

• •

16 NFWP_B

GND 17

• •

18 GND

GND 19

• •

20 GND

Figure 3-11. NAND Flash Connector PM1 (on the CPU Board) Pin Assignments

3-22

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Table 3-11. NAND Flash Connector PM1 Signal Descriptions

Pin(s) Signal Description

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

P1.8V

NC

TP26

NFRB

+1.8 VDC power

Not Connect

Test point

NAND FLASH READY/BUSY

P2.5V

+ 2.5 VDC power

NFRE_B NAND FLASH READ ENABLE

TP27 Test point

NFCE_B NAND FLASH CHIP ENABLE

VCC

NFCLE

NC

NFALE

+3 VDC power

NAND FLASH COMMAND LATCH ENABLE

Not Connect

NAND FLASH ADDRESS LATCH ENABLE

NC Not Connect

NFWE_B NAND FLASH WRITE ENABLE

NC Not Connect

NFWP_B NAND FLASH WRITE PROTECT

17

18

19

20

GND

GND

GND

GND

GOUND

GOUND

GOUND

GOUND

23 NFIO4 NAND FLASH I/O BIT 4 — Bidirectional data transfer signal

24 A14 NFIO9 NAND FLASH I/O BIT 9 — Bidirectional data transfer signal*

25 NFIO5 NAND FLASH I/O BIT 5 — Bidirectional data transfer signal

26 A13 NFIO8 NAND FLASH I/O BIT 8 — Bidirectional data transfer signal*

27

28, 30

NFIO6

GND

NAND FLASH I/O BIT 6 — Bidirectional data transfer signal

GROUND

29 NFIO7 NAND FLASH I/O BIT 7 — Bidirectional data transfer signal

*The signal name in italics is the function intended for operation with this connector.

It is multiplexed in the i.MX21 processor with the listed signal.

NC 1

NFIO0 3

NFIO1 5

NFIO2 7

NFIO3 9

NFIO4 11

NFIO5 13

NFIO6 15

NFIO7 17

GND 19

PM2

• •

• •

• •

• •

2

4

6

NC

A25

A24

8 A23

• •

10 A22

• •

12 A21

• •

14 A15

• •

16 A14

• •

18 A13

• •

20 GND

Figure 3-12. NAND Flash Connector PM2 (on the CPU) Pin Assignments

Support Information

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-23

Support Information

Table 3-12. NAND Flash Connector PM2 Signal Descriptions

Pin(s) Signal Description

1

2

NC

NC

No Connect

No Connect

3 NFIO0 NAND FLASH I/O BIT 0 — Bidirectional data transfer signal

4 A25 NFIO15 NAND FLASH I/O BIT 15 — Bidirectional data transfer signal*

5 NFIO1 NAND FLASH I/O BIT 1— Bidirectional data transfer signal

6 A24 NFIO14 NAND FLASH I/O BIT 14 — Bidirectional data transfer signal*

7 NFIO2 NAND FLASH I/O BIT 2— Bidirectional data transfer signal

8 A23 NFIO13 NAND FLASH I/O BIT 13 — Bidirectional data transfer signal*

9 NFIO3 NAND FLASH I/O BIT 3— Bidirectional data transfer signal

10 A22 NFIO12 NAND FLASH I/O BIT 12 — Bidirectional data transfer signal*

11 NFIO4 NAND FLASH I/O BIT 4— Bidirectional data transfer signal

12 A21 NFIO11 NAND FLASH I/O BIT 11 — Bidirectional data transfer signal*

13 NFIO5 NAND FLASH I/O BIT 5— Bidirectional data transfer signal

14 A15 NFIO10 NAND FLASH I/O BIT 10 — Bidirectional data transfer signal*

15 NFIO6 NAND FLASH I/O BIT 6— Bidirectional data transfer signal

16 A14 NFIO9 NAND FLASH I/O BIT 9— Bidirectional data transfer signal*

17 NFIO7 NAND FLASH I/O BIT 7— Bidirectional data transfer signal

18 A13 NFIO8 NAND FLASH I/O BIT 8— Bidirectional data transfer signal*

19

20

GND

GND

GOUND

GOUND

*The signal name in italics is the function intended for operation with this connector.

It is multiplexed in the i.MX21 processor with the listed signal.

3-24

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Support Information

3.9

External Keypad Connector

Connector P5 is the ADS External Keypad connector. Figure 3-13 shows pin assignments and Table 3-13

provides signal descriptions for the connector.

P5

VCC 1

• •

UART2_RXD 3

• •

UART2_TXD 5

• •

KP_COL5 7

• •

KP_COL4 9

• •

KP_COL3 11

• •

KP_COL2 13

• •

KP_COL1 15

• •

KP_COL0 17

• •

NC 19

• •

2 NC

4 UART2_RTS

6 UART2_CTS

8 KP_ROW5

10 KP_ROW4

12 KP_ROW3

14 KP_ROW2

16 KP_ROW1

18 KP_ROW0

20 GND

Figure 3-13. External Keypad Connector P5 Pin Assignments

Table 3-13. External Keypad Connector P5 Signal Descriptions

Pin(s) Signal Description

13

14

15

16

9

10

11

12

1

2, 19

VCC

NC

+3 volt power

NO CONNECTION

3 UART2_RXD KEY_COL7 KEYPAD COLUMN 7 — Bidirectional signal used to scan a keypad

4 UART2_RTS KEY_ROW6 KEYPAD ROW 6 — Bidirectional signal used to scan a keypad

7

8

5 UART2_TXD KEY_COL6 KEYPAD COLUMN 6 — Bidirectional signal used to scan a keypad

6 UART2_CTS KEY_ROW7 KEYPAD ROW 7 — Bidirectional signal used to scan a keypad

KP_COL5

KP_ROW5

KEYPAD COLUMN 5 — Bidirectional signal used to scan a keypad

KEYPAD ROW 5 — Bidirectional signal used to scan a keypad

KP_COL4

KP_ROW4

KP_COL3

KP_ROW3

KP_COL2

KP_ROW2

KP_COL1

KP_ROW1

KEYPAD COLUMN 4 — Bidirectional signal used to scan a keypad

KEYPAD ROW 4 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 3 — Bidirectional signal used to scan a keypad

KEYPAD ROW 3 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 2 — Bidirectional signal used to scan a keypad

KEYPAD ROW 2 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 1 — Bidirectional signal used to scan a keypad

KEYPAD ROW 1 — Bidirectional signal used to scan a keypad

17

18

KP_COL0

KP_ROW0

KEYPAD COLUMN 0 — Bidirectional signal used to scan a keypad

KEYPAD ROW 0 — Bidirectional signal used to scan a keypad

20 GND GROUND

* The signal name in italics is the function intended for operation with this connector. It is multiplexed in the i.MX21 processor with the listed signal.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-25

Support Information

3.10

LCD Panel Connector

Connector P7 is the ADS LCD panel connector. Figure 3-14 shows pin assignments and Table 3-14

provides signal descriptions the connector.

P7

VCC 1

• •

OE_ACD 3

• •

LP_HYSYNC 5

• •

LD5_B5 7

• •

LD3_B3 9

• •

LD11_G5 11

• •

LD9_G3 13

• •

LD17_R5 15

• •

LD15_R3 17

• •

CONTRAST 19

• •

SPL_SPR 21

• •

PS 23

• •

LD1_B1 25

• •

LD7_G1 27

• •

LD13_R1 29

• •

TOP 31

• •

LEFT 33

• •

2 GND

4 FLM_VSYNC_SPS

6 LSCLK

8 LD4_B4

10 LD2_B2

12 LD10_G4

14 LD8_G2

16 LD16_R4

18 LD14_R2

20 LCDON

22 REV

24 CLS

26 LD0_B0

28 LD6_G0

30 LD12_R0

32 BOTTOM

34 RIGHT

Figure 3-14. LCD Panel Connector P7 Pin Assignments

Table 3-14. LCD Panel Connector P8 Signal Descriptions

Pin(s) Signal Description

13

14

15

16

17

9

10

11

12

7

8

5

6

1

2

VCC

GND

+3 volt power

GROUND

3 OE_ACD OUTPUT ENABLE / ALTERNATE CRYSTAL DIRECTION

4 FLM_VSYNC_SPS FIRST LINE MARKER / VERTICAL SYNCHRONIZATION

LP_HSYNC

LSCLK

LD5_B5

LD4_B4

LINE PULSE / HORIZONTAL SYNCHRONIZATION

LCD SHIFT CLOCK — Output to LCD

LCD DATA 5 / BLUE BIT 5 — Output data to LCD

LCD DATA 4 / BLUE BIT 4 — Output data to LCD

LD3_B3

LD2_B2

LD11_G5

LD10_G4

LD9_G3

LD8_G2

LD17_R5

LD16_R4

LD15_R3

LCD DATA 3 / BLUE BIT 3 — Output data to LCD

LCD DATA 2 / BLUE BIT 2 — Output data to LCD

LCD DATA 11 / GREEN BIT 5 — Output data to LCD

LCD DATA 10 / GREEN BIT 4 — Output data to LCD

LCD DATA 9 / GREEN BIT 3 — Output data to LCD

LCD DATA 8 / GREEN BIT 2 — Output data to LCD

LCD DATA 17 / RED BIT 5 — Output data to LCD

LCD DATA 16 / RED BIT 4 — Output data to LCD

LCD DATA 15 / RED BIT 3 — Output data to LCD

M9328MX21ADSE User’s Manual, Rev. A

3-26 Freescale Semiconductor

Pin(s)

18

19

20

21

22

23

24

29

30

31

32

25

26

27

28

33

34

Support Information

Signal

LD14_R2

CONTRAST

LCDON

SPL_SPR

REV

PS

CLS

LD1_B1

LD0_B0

LD7_G1

LD6_G0

LD13_R1

LD12_R0

TOP

BOTTOM

LEFT

RIGHT

Table 3-14. LCD Panel Connector P8 Signal Descriptions (continued)

Description

LCD DATA 14 / RED BIT 2 — Output data to LCD

LCD bias voltage used as contrast control

LCD enable — Active High, Enables the Sharp LCD

SAMPLING LEFT to RIGHT— Horizontal scan direction

Signal for common electrode driving signal preparation (Sharp panel dedicated signal)

Control signal output for source driver (Sharp panel dedicated signal)

Start signal output for gate driver. This signal is inverted version of PS (Sharp panel dedicated signal)

LCD DATA 1 / BLUE BIT 1 — Output data to LCD

LCD DATA 0 / BLUE BIT 0 — Output data to LCD

LCD DATA 7 / GREEN BIT 1 — Output data to LCD

LCD DATA 6 / GREEN BIT 0 — Output data to LCD

LCD DATA 13 / RED BIT 1 — Output data to LCD

LCD DATA 12 / RED BIT 0 — Output data to LCD

Negative pen-Y analog input

Positive pen-Y analog input

Negative pen-X analog input

Positive pen-X analog input

3.11

TV Encoder Connector

Connector P13 is the TV encoder connector. Figure 3-15 gives the pin assignments and Table 3-15 gives

the signal descriptions for this connector.

P13

VCC 1

• •

I2C_CLK 3

• •

I2C_DATA 5

• •

GND 7

• •

CLK_26M 9

• •

2 P5V

4 NC

6 NC

8 GND

10 GND

Figure 3-15. TV encoder Connector P13 Pin Assignments

Table 3-15. TV encoder Connector P13 Signal Descriptions

Pin(s)

1

2

3

4,6

5

7, 8, 10

9

Signal Description

VCC

P5V

+3 VDC power

+5 VDC power

I2C_CLK I SQUARED C CLOCK — Serial clock, bidirectional

NC NO CONNECTION

I2C_DATA I SQUARED C DATA — Serial data, bidirectional

GND GROUND

CLK_26M 26M Clock signal from TV encoder card

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-27

Support Information

3.12

SD/MMC Connector

Connector P6 is the ADS SD/MMC connector. Figure 3-16 gives the pin assignments and Table 3-16 gives

the signal descriptions for this connector.

11 10 8 7 6 5 4 3 2 1 9 13

Pin(s)

1

2

3, 6, 11

4

5

7

8

9

10

12

13, 14

12 14

Figure 3-16. SD/MMC Connector P6 Pin Assignments

Table 3-16. SD/MMC Connector P6 Signal Descriptions

Signal

SD1_DAT3

SD1_CMD

GND

VCC

SD1_CLK

SD1_DAT0

SD1_DAT1

SD1_DAT2

CSPI1_RDY

SD_WP

NC

Description

SD Card

MMC Card

1-Bit Mode 4-Bit Mode

Reserved

Not Used

Not Used

Not Used

Command / Response

GROUND

+3 VDC power

Clock

Data Line DAT0

Interrupt (IRQ)

ReadWait (RW)

Data Line DAT3

Data Line DAT1 or

Interrupt (IRQ)

Data Line DAT2 or

Read Wait (RW)

Card Detect, configured as GPIO, PB20

Write Protect Detect, connects to I/O input bit 0

No Connection

3.13

Extension and Image Sensor Connectors

Connectors PE1, PE2 and PE3 are 16 x 3-pin DIN type connectors. PE1 is a connector for the Image

Sensor module included with the ADS. PE2 and PE3 are Extension connectors that provide most of the

MC9328MX21 signals other than data bus, address bus, EIM control signals, and SDRAM control signals.

Figure 3-17 shows the pin numbering for the PE1, PE2, and PE3 connectors. Table 3-17 through

Table 3-19 provide signal descriptions. Table 3-17 covers PE1, Table 3-18 covers PE2 and Table 3-19

covers PE3.

M9328MX21ADSE User’s Manual, Rev. A

3-28 Freescale Semiconductor

Support Information

C

B

A

16 15 14 13 12 11 10

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

9

•

•

•

8

•

•

•

7

•

•

•

6

•

•

•

5

•

•

•

4

•

•

•

3

•

•

•

2

•

•

•

1

•

•

•

Figure 3-17. Connectors PE1, PE2, and PE3 Pin Numbering

Table 3-17. Image Sensor Connector PE1 Signal Description

Pin(s) Signal Description

A1,B1,C1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11-A15

A16,B16,C16

B2-B15

C2

C3

C8

C9

C10

C11

C4

C5

C6

C7

C12

C13-C15

GND

CSI_D0

CSI_D2

GROUND

CMOS SENSOR INTERFACE DATA 0— Image Sensor input data

CMOS SENSOR INTERFACE DATA 2— Image Sensor input data

CSI_D4

CSI_D6

CMOS SENSOR INTERFACE DATA 4— Image Sensor input data

CMOS SENSOR INTERFACE DATA 6— Image Sensor input data

CSI_PIXCLK CMOS SENSOR INTERFACE PIXAL CLOCK — Data latch strobe

CSI_VSYNC CMOS SENSOR INTERFACE VERTICAL SYNC — Control input

I2C_CLK I SQUARED C CLOCK — Serial clock, bidirectional

CSPI2_SS1 SLAVE SELECT 1 — CSPI signal (bidirectional)

CSPI2_SS2 SLAVE SELECT 2 — CSPI signal (bidirectional)

NC NO CONNECTION

VCC

NC

CSI_D1

CSI_D3

+3 VDC power

NO CONNECTION

CMOS SENSOR INTERFACE DATA 1— Image Sensor input data

CMOS SENSOR INTERFACE DATA 3— Image Sensor input data

CSI_D5

CSI_D7

CMOS SENSOR INTERFACE DATA 5— Image Sensor input data

CMOS SENSOR INTERFACE DATA 7— Image Sensor input data

CSI_HSYNC CMOS SENSOR INTERFACE HORIZONTAL SYNC— Control input

CSI_MCLK CMOS SENSOR INTERFACE MASTER CLOCK — Clock output to the sensor card

I2C_DAT

NC

I SQUARED C DATA — Serial data, bidirectional

NO CONNECTION

CSI_CTL0 CMOS SENSOR CONTORL 0 — Control output from MM I/O

CSI_CTL1 CMOS SENSOR CONTORL 1 — Control output from MM I/O

CSI_CTL2 CMOS SENSOR CONTORL 2 — Control output from MM I/O

NC NO CONNECTION

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor 3-29

Support Information

3-30

Pin(s)

B5

B6

B7

B8

B1

B2

B3

B4

B9

B10

B11

B12

B13

A13

A14

A15

A16

A9

A10

A11

A12

A5

A6

A7

A8

A1

A2

A3

A4

B14

Table 3-18. Extension Connector PE2 Signal Description

Signal Description

KP_ROW5

KP_ROW4

KP_ROW3

KP_ROW2

KP_ROW1

KP_ROW0

KP_COL5

KP_COL4

KP_COL3

KP_COL2

KP_COL1

KP_COL0

SAP_RXD

SD1_CLK

SD1_CMD

SD1_D3

SD1_D2

SD/MMC CLOCK — Clock output to SD/MMC card

SD/MMC COMMAND — Serial command bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 3 — Serial data bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 2 — Serial data bit to SD/MMC card, bidirectional

SD1_D1

SD1_D0

SD/MMC DATA BIT 1 — Serial data bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 0 — Serial data bit to SD/MMC card, bidirectional

UART1_RTS UART1 REQUEST TO SEND — Active low input signal

UART1_CTS UART1 CLEAR TO SEND — Active low output signal

UART1_RXD UART1 RECEIVED DATA — Serial input signal

UART1_TXD UART1 TRANSMITTED DATA — Serial output signal

UART3_RTS UART3 REQUEST TO SEND — Active low input signal

UART3_CTS UART3 CLEAR TO SEND — Active low output signal

UART3_RXD UART3 RECEIVED DATA — Serial input signal

UART3_TXD UART3 TRANSMITTED DATA — Serial output signal

UART2_RTS UART2 REQUEST TO SEND — Active low input signal

UART2_CTS UART2 CLEAR TO SEND — Active low output signal

SAP_FS

KEYPAD ROW 5 — Bidirectional signal used to scan a keypad

KEYPAD ROW 4 — Bidirectional signal used to scan a keypad

KEYPAD ROW 3 — Bidirectional signal used to scan a keypad

KEYPAD ROW 2 — Bidirectional signal used to scan a keypad

KEYPAD ROW 1 — Bidirectional signal used to scan a keypad

KEYPAD ROW 0 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 5 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 4 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 3 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 2 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 1 — Bidirectional signal used to scan a keypad

KEYPAD COLUMN 0 — Bidirectional signal used to scan a keypad

SYCHRONOUS AUDIO PORT RECEIVED DATA — serial data input

SYCHRONOUS AUDIO PORT FRAME SYNC — Bidirectional, output in master mode, input in slave mode

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

Support Information

Table 3-18. Extension Connector PE2 Signal Description (continued)

Pin(s) Signal Description

C3

C4

C5

C6

B15

B16

C1

C2

C7

C8

UART2_RXD

UART2_TXD

GND

CSPI1_MOSI

CSPI1_MISO

CSPI1_SCLK

CSPI1_SS0

CSPI1_SS1

UART2 RECEIVED DATA — Serial input signal

UART2 TRANSMITTED DATA — Serial output signal

GROUND

MASTER OUT / SLAVE IN — CSPI data signal (bidirectional)

MASTER IN / SLAVE OUT — CSPI data signal (bidirectional)

SERIAL CLOCK — Bidirectional

SLAVE SELECT 0 — CSPI signal (bidirectional)

SLAVE SELECT 1 — CSPI signal (bidirectional)

C9

CSPI1_SS2 SLAVE SELECT 2 — CSPI signal (bidirectional)

CSPI1_RDY READY — CSPI serial burst trigger, active low input

SSI1_CLK

SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK — Bidirectional, output in master mode and input in slave mode

C10

C11

C12

SSI1_TXD

SSI1_RXD

SSI1_FS

SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA — Serial output signal

SYCHRONOUS SERIAL INTERFACE RECEIVED DATA — Serial input signal

C13 SAP_CLK

SYCHRONOUS SERIAL INTERFACE FRAME SYNC

SYCHRONOUS AUDIO PORT CLOCK — Serial transmit clock, bidirectional, output in master mode, input in slave mode

SYCHRONOUS AUDIO PORT TRANMITTED DATA — Serial data output C14 SAP_TXD

C15 B_NEXUSEVTI BUFFERED NEXUS EVENT IN

C16 VCC + 3 VDC power

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-31

Support Information

Table 3-19. Extension Connector PE3 Signal Description

Pin(s) Signal Description

A5

A6

A7

A8

A1

A2

A3

A4

A9

CSPI2_MOSI MASTER OUT / SLAVE IN — CSPI data signal (bidirectional)

CSPI2_MISO MASTER IN / SLAVE OUT — CSPI data signal (bidirectional)

CSPI2_SCLK SERIAL CLOCK — Bidirectional

CSPI2_SS0 SLAVE SELECT 0 — CSPI signal (bidirectional)

CSPI2_SS1

CSPI2_SS2

I2C_CLK

I2C_DATA

SSI3_CLK

SLAVE SELECT 1 — CSPI signal (bidirectional)

SLAVE SELECT 2 — CSPI signal (bidirectional)

I SQUARED C CLOCK — Serial clock, bidirectional

I SQUARED C DATA — Serial data, bidirectional

SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK — Bidirectional, output in master mode and input in slave mode

A10

A11

A12

A13

A14

A15

A16

SSI3_TXD

SSI3_RXD

SSI3_FS

SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA — Serial output signal

SYCHRONOUS SERIAL INTERFACE RECEIVED DATA — Serial input signal

SSI2_CLK

SYCHRONOUS SERIAL INTERFACE FRAME SYNC

SYCHRONOUS SERIAL INTERFACE TRANSMITTER CLOCK — Bidirectional, output in master mode and input in slave mode

SYCHRONOUS SERIAL INTERFACE TRANSMITTED DATA — Serial output signal SSI2_TXD

SSI2_RXD

SSI2_FS

SYCHRONOUS SERIAL INTERFACE RECEIVED DATA — Serial input signal

SYCHRONOUS SERIAL INTERFACE FRAME SYNC

USBG_RXDP USB OTG RECEIVED DATA PLUS input

USBG_RXDM USB OTG RECEIVED DATA MINUS input

B1

B2

B3

B4

B5

B6

B7

B8

USBG_TXDP USB OTG TRANSMITTED DATA PLUS output

USBG_TXDM USB TRANSMITTED DATA MINUS output

USBG_OE_B

USBG_FS

USB OTG OUTPUT ENABLE

USB OTG FULL SPEED

USBG_ON_B USB OTG transceiver ON

USBG_SCL USB OTG SERIAL CLOCK

B9 USBG_SDA USB OTG SERIAL DATA

B10 USBH1_RXDM USB RECEIVED DATA MINUS input

B11 USBH1_RXDP USB RECEIVED DATA PLUS input.

B12 USBH1_TXDM USB TRANSMITTED DATA MINUS output

B13 USBH1_TXDP USB TRANSMITTED DATA PLUS output

M9328MX21ADSE User’s Manual, Rev. A

3-32 Freescale Semiconductor

Table 3-19. Extension Connector PE3 Signal Description (continued)

Pin(s) Signal Description

C2

C3

C4

C5

B14

B15

B16

C1

USBH1_FS USB FULL SPEED

USBH1_OE_B USB OUTPUT ENABLE

USBH_ON_B USB transceiver ON

GND GROUND

TIN

TOUT

SD2_CLK

SD2_CMD

TIMER INPUT CAPTURE — Timer input

TIMER OUTPUT COMPARE — Timer output

SD/MMC CLOCK — Clock output to SD/MMC card

SD/MMC COMMAND — Serial command bit to SD/MMC card, bidirectional

C6

C7

C8

C9

SD2_D3

SD2_D2

SD2_D1

SD2_D0

SD/MMC DATA BIT 3 — Serial data bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 2 — Serial data bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 1 — Serial data bit to SD/MMC card, bidirectional

SD/MMC DATA BIT 0 — Serial data bit to SD/MMC card, bidirectional

C10 PWMO PULSE WIDTH MODULATOR OUTPUT

C11 RESET_OUT_B RESET OUT — Active low reset signal from the processor

C12

C13

RTCK_GPIO

USB_OC_B

RETURN CLOCK — JTAG signal, can be general purpose I/O

USB OVER CURRENT input active low

C14

C15

C16

USB_PWR USB POWER

USB_BYP_B USB BY PASS input active low

VCC +3 VDC power

Support Information

3.14

Disposal Information

This symbol means this product may be subject to special disposal requirment.

For product disposal information, please refer to http://www.freescale.com/productdisposal.

Freescale Semiconductor

M9328MX21ADSE User’s Manual, Rev. A

3-33

Support Information

3-34

M9328MX21ADSE User’s Manual, Rev. A

Freescale Semiconductor

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

[email protected]

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130 [email protected]

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French) [email protected]

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

Japan

0120 191014 or +81 3 5437 9125 [email protected]

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080 [email protected]

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

[email protected]

UMS-21100

Rev A, 07/2006

Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale

Semiconductor was negligent regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners.

© Freescale Semiconductor, Inc. 2006. All rights reserved.