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KSZ8863MLL/FLL/RLL
Integrated 3-Port 10/100 Managed
Switch with PHYs
Rev. 1.4
General Description
The KSZ8863MLL/FLL/RLL are highly integrated 3-port switch on a chip ICs in industry’s smallest footprint. They are designed to enable a new generation of low port count, cost-sensitive and power efficient 10/100Mbps switch systems. Low power consumption, advanced power management and sophisticated QoS features
(e.g., IPv6 priority classification support) make these devices ideal for IPTV, IP-STB, VoIP, automotive and industrial applications.
The KSZ8863 family is designed to support the GREEN requirement in today’s switch systems. Advanced power management schemes include software power down, per port power down and the energy detect mode that shuts downs the transceiver when a port is idle.
The configurations provided by the KSZ8863 family enables the flexibility to meet requirements of different applications:
• KSZ8863MLL: Two 10/100BASE-T/TX transceivers and one MII interface.
• KSZ8863RLL: Two 10/100BASE-T/TX transceivers and one RMII interface.
• KSZ8863FLL: One 100BASE-FX, one
10/100BASE-T/TX transceivers and one MII interface.
The device is available in RoHS-compliant 48-pin LQFP package. Industrial-grade and Automotive-grade are also available.
KSZ8863MLL/FLL/RLL also offer a by-pass mode, which enables system-level power saving. In this mode, the processor connected to the switch through the MII interface can be shut down without impacting the normal switch operation.
The datasheets and supporting documents can be found at Micrel’s web site at: www.micrel.com
.
__________________________________________________________________________________________________________
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
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Micrel, Inc.
Features
• Advanced Switch Features
-
IEEE 802.1q VLAN support for up to 16 groups
(full-range of VLAN IDs)
-
VLAN ID tag/untag options, per port basis
-
IEEE 802.1p/q tag insertion or removal on a per port basis (egress)
-
Programmable rate limiting at the ingress and egress on a per port basis
-
Broadcast storm protection with % control
(global and per port basis)
-
IEEE 802.1d rapid spanning tree protocol support
-
tail tag mode (1 byte added before FCS) support at port3 to inform the processor which ingress port receives the packet and its priority
-
Bypass feature which Automatically sustains the switch function between Port1 and Port2 when
CPU (Port 3 interface) goes to the sleep mode
-
Self-address
-
Individual MAC address for port1 and port2
-
Support RMII interface and 50 MHz reference clock output
-
IGMP snooping (Ipv4) support for multicast packet Filtering
-
IPv4/IPv6 QoS support.
-
MAC filtering function to forward unknown unicast packets to specified port
• Comprehensive Configuration Register Access
-
Serial management interface (SMI) to all internal registers
-
MII management (MIIM) interface to PHY registers
-
High speed SPI and I registers
2
C Interface to all internal
-
I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode
-
Control registers configurable on the fly (portpriority, 802.1p/d/q, AN…)
• QoS/CoS Packet Prioritization Support
-
Per port, 802.1p and DiffServ-based
-
Re-mapping of 802.1p priority field per port basis Four priority levels
• Proven Integrated 3-Port 10/100 Ethernet Switch
-
3rd generation switch with three MACs and two
PHYs fully compliant with IEEE 802.3u standard
-
Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture
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KSZ8863MLL/FLL//RLL
-
Full duplex IEEE 802.3x flow control (PAUSE) with force mode option
-
Half-duplex back pressure flow control
-
HP Auto MDI-X for reliable detection of and correction for straight-through and crossover cables with disable and enable option
-
Micre
®
TDR-based cable diagnostics permit identification of faulty copper cabling
-
MII interface supports both MAC mode and PHY mode
-
Comprehensive LED Indicator support for link, activity, full/half duplex and 10/100 speed
-
HBM ESD Rating 4kV
• Switch Monitoring Features
-
Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII
-
MIB counters for fully compliant statistics gathering 34 MIB counters per port
-
Loopback modes for remote diagnostic of failure
• Low Power Dissipation
-
Full-chip hardware power-down (register configuration not saved)
-
Full-chip software power-down (register configuration not saved)
-
Energy-detect mode support
-
Dynamic clock tree shutdown feature
-
Per port based software power-save on PHY
(idle link detection, register configuration preserved)
-
Voltages: Single 3.3V supply with internal 1.8V
LDO for 3.3V VDDIO
-
Optional 3.3V, 2.5V and 1.8V for VDDIO
-
Transceiver power 3.3V for VDDA_3.3
• Industrial Temperature Range: –40
o
C to +85 o
C
• Available in 48-Pin LQFP, Lead-free package
Applications
• Typical
-
VoIP
-
Set-top/Game
-
Automotive
-
Industrial
-
IPTV
-
SOHO Gateway
-
Broadband Gateway / Firewall / VPN
-
Integrated DSL/Cable Modem
-
Wireless LAN access point + gateway
-
Standalone 10/100 switch
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Ordering Information
Part Number
KSZ8863MLL
KSZ8863MLLI
KSZ8863FLL
KSZ8863FLLI
KSZ8863RLL
KSZ8863RLLI
Revision History
Junction
Temperature Range
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
–40ºC to +85ºC
48-Pin LQFP
48-Pin LQFP
48-Pin LQFP
48-Pin LQFP
48-Pin LQFP
48-Pin LQFP
Pb-Free/Commercial
Pb-Free/Industrial
Pb-Free/Commercial
Pb-Free/Industrial
Pb-Free/Commercial
Pb-Free/Industrial
Revision Date Summary of Changes
1.0 07/10/08 release
1.1
09/23/09
Update the Electrical Characteristics.
Add LinkMD feature on Port 2.
Fix the typo on register 194
10/01/09 Modify pin 28(SMRXD31) description
Remove Turbo MII feature and its timing, add MDC/MDIO timing, update the descriptions of the by-pass mode, tag insertion, power management, pins, registers and so on. Update max rating, RMII timing and electrical characteristics.
Add the descriptions of the registers from register 175-186. Add a note for port register control 12, update the description for some registers, update reset timing diagram. junction thermal data and lead temperature.
KSZ8863MLL/FLL//RLL
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Contents
LinkMD
®
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2
I
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Absolute Maximum Ratings
(1)
Operating Ratings
(2)
Electrical Characteristics
(4)
I
2
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List of Figures
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List of Tables
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Pin Description and I/O Assignment
Pin Number Pin Name
1 RXM1
4
5
2
3
6
RXP1
TXM1
TXP1
VDDA_3.3
ISET
7 VDDA_1.8
8
9
RXM2
RXP2
10 AGND
11 TXM2
12
13
TXP2
NC
14 X1
Type
(1)
Description
I/O Physical receive or transmit signal (– differential)
I/O
I/O
I/O
P
O
P
I/O
I/O
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (– differential)
Physical transmit or receive signal (+ differential)
3.3V analog V
DD
Set physical transmit output current.
Pull-down this pin with a 11.8K 1% resistor to ground.
1.8V analog core power input from VDDCO (pin 42).
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
15 X2
16 SMTXEN3
17 SMTXD33/
EN_REFCLKO_3
18 SMTXD32
19
20
SMTXD31
SMTXD30
21 GND
22 VDDIO
I/O Physical transmit or receive signal (– differential)
I/O
NC
Physical transmit or receive signal (+ differential)
No Connection.
I 25 or 50MHz crystal/oscillator clock connections.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a
3.3V tolerant oscillator and X2 is a NC.
O
Note: Clock is +/- 50ppm for both crystal and oscillator, the clock should be applied to X1 pin before reset voltage goes high.
Ipu lpu
Ipu
Ipu
Ipu
Switch MII transmit enable
MLL/FLL: Switch MII transmit data bit 3
RLL: Strap option: RMII mode Clock selection
PU = Enable REFCLKO_3 output
PD = Disable REFCLKO_3 output
Switch MII transmit data bit 2
RLL: Strap option: X1 pin Clock selection (for Rev A3 and behind A3)
PU = 25MHz to X1 pin as clock source (default).
PD = 50MHz to X1 pin as clock source to provide/receive 50MHz RMII reference clock for RLL part.
Switch MII/RMII transmit data bit 1
Switch MII/RMII transmit data bit 0
23 SMTXC3/
REFCLKI_3
24 SMTXER3/
MII_LINK_3
P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
I/O MLL/FLL: Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII and RMII mode.
RLL: Reference clock input
Note: pull-down by resistor is needed if internal reference clock is used in
RLL by register 198 bit 3.
Ipd Switch port3 MII transmit error in MII mode
0= MII link indicator from host in MII PHY mode.
1= No link on port 3 MII PHY mode and enable By-pass mode.
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Pin Description and I/O Assignment (Continued)
Pin Number Pin Name
25 SMRXDV3
26 SMRXD33/
REFCLKO_3
27
28
29
30
SMRXD32
SMRXD31
SMRXD30
SMRXC3
Type
(1)
Description
lpu/O lpu/O
Ipu/O
Ipu/O lpu/O
Switch MII/RMII receive data valid
Strap option:
Force duplex mode (P1DPX)
PU = port 1 default to full duplex mode if P1ANEN = 1 and auto- negotiation fails. Force port 1 in full-duplex mode if P1ANEN = 0.
PD = port 1 default to half duplex mode if P1ANEN = 1 and auto- negotiation fails. Force port 1 in half duplex mode if P1ANEN = 0.
MLL/FLL: Switch MII receive data bit 3/
RLL: Ouput reference clock in RMII mode.
Strap option:
enable auto-negotiation on port 2 (P2ANEN)
PU = enable
PD = disable
Switch MII receive data bit 2
Strap option:
Force the speed on port 2 (P2SPD)
PU = force port 2 to 100BT if P2ANEN = 0
PD = force port 2 to 10BT if P2ANEN = 0
Switch MII/RMII receive data bit 1
Strap option:
Force duplex mode (P2DPX)
PU = port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in full duplex mode if P2ANEN = 0.
PD = Port 2 set to half duplex mode if P2ANEN = 1 and auto-negotiation fails.
Force port 2 in half duplex mode if P2ANEN = 0.
Switch MII/RMII receive data bit 0
Strap option:
Force flow control on port 2 (P2FFC)
PU = always enable (force) port 2 flow control feature.
PD = port 2 flow control feature enable is determined by auto- negotiation result.
I/O Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
31 GND
32 VDDC
33
34
SCOL3
SCRS3
35 INTRN
P
Ipu/O
Ipu/O
1.8V digital core power input from VDDCO (pin 42).
Switch MII collision detect
Switch MII carrier sense
36 SCL_MDC
37 SDA_MDIO Ipu/O
Active Low signal to host CPU to indicate an interrupt status bit is set when lost link. Refer to register 187 and 188.
SPI slave mode / I
2
C slave mode: clock input
I
2
C master mode: clock output
MIIM clock input
SPI slave mode: serial data input
I
2
C master/slave mode: serial data input/output
MIIM: data input/out
Note: an external pull-up is needed on this pin when it is in use.
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Pin Description and I/O Assignment (Continued)
Pin Number Pin Name
38 SPIQ
39 SPISN
40 VDDIO
Type
(1)
Description
lpd/O SPI slave mode: serial data output
Note: an external pull-up is needed on this pin when it is in use.
Strap option:
Force flow control on port 1 (P1FFC)
PU = always enable (force) port 1 flow control feature
PD = port 1 flow control feature enable is determined by auto negotiation result.
I SPI slave mode: chip select (active low)
When SPISN is high, the KSZ8863MLL/FLL/RLLis deselected and SPIQ is held in high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
Note: an external pull-up is needed on this pin when it is in use.
P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.
41 GND
42 VDDCO P 1.8V core power voltage output (internal 1.8V LDO regulator output), this
1.8V output pin provides power to both VDDA_1.8 and VDDC input pins.
Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not connect an external power supply to VDDCO pin. The ferrite bead is requested between analog and digital 1.8V core power.
43 P1LED1
Default: Speed (refer to register 195 bit[5:4])
Strap option:
Force the speed on port 1 (P1SPD)
PU = force port 1 to 100BT if P1ANEN = 0
PD = force port 1 to 10BT if P1ANEN = 0
44 P1LED0
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option:
enable auto-negotiation on port 1 (P1ANEN)
PU = enable (It is better to pull up in design)
PD = disable (default)
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Pin Description and I/O Assignment (Continued)
Type
(1)
Description Pin Number Pin Name
45 P2LED1
46 P2LED0
Strap option:
Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option
: Serial bus configuration
Serial bus configuration pins to select mode of access to
KSZ8863MLL/FLL/RLL internal registers.
[P2LED1, P2LED0] = [0, 0] — I
2
C master (EEPROM) mode
(If EEPROM is not detected, the KSZ8863MLL/FLL/RLL will be configured with the default values of its internal registers and the values of its strap-in pins.)
Interface Signals Type Description
SPIQ O Not used (tri-stated)
[P2LED1, P2LED0] = [0, 1] — I
2
C slave mode
The external I
2
C master will drive the SCL_MDC clock.
The KSZ8863MLL/FLL/RLL device addresses are:
1011_1111 <read>
1011_1110 <write>
Interface Signals Type Description
SPIQ O Not used (tri-stated)
[P2LED1, P2LED0] = [1, 0] — SPI slave mode
Interface Signals Type Description
SPIQ O SPI data out
47 RSTN
48 FXSD1
Notes:
1. Speed : Low (100BASE-TX), High (10BASE-T)
Full duplex : Low (full duplex), High (half duplex)
Act : Toggle (transmit / receive activity)
Link : Low (link), High (no link)
SDA_MDIO
SPISN
I
I
SPI data In
SPI chip select
[P2LED1, P2LED0] = [1, 1]
– SMI/MIIM-mode
In SMI mode, the KSZ8863MLL/FLL/RLL provides access to all its internal 8bit registers through its SCL_MDC and SDA_MDIO pins.
In MIIM mode, the KSZ8863MLL/FLL/RLL provides access to its 16-bit MIIM registers through its SDC_MDC and SDA_MDIO pins.
Ipu Hardware reset pin (active low)
I MLL/RLL: No connection or connect to analog ground by 1Kohm pull-down resistor.
FLL: Fiber signal detect
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2. P = Power supply.
Gnd = Ground.
I = Input.
Ipu/O = Input with internal pull-up during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Opu = Output w/ internal pull-up.
Opd = Output w/ internal pull-down.
KSZ8863MLL/FLL//RLL
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Pin Configuration
KSZ8863MLL/FLL//RLL
48-Pin LQFP
(Top View)
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Functional Description
The KSZ8863MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer
2 managed switch.
The KSZ8863MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host processor has complete control of the KSZ8863MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or
I
2
C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
On the media side, the KSZ8863MLL/FLL/RLL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external1% 11.8K
Ω resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8863MLL/FLL/RLL generates 125MHz, 62.5MHz, and 31.25MHz clocks for system timing. Internal clocks are generated from an external 25MHz or 50MHz crystal or oscillator. KSZ8863RLL can generates a 50MHz reference clock for the RMII interface
Scrambler/De-scrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming data stream using the same sequence as at the transmitter.
100BASE-FX Operation
100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is bypassed and auto MDI/MDI-X is disabled.
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100BASE-FX Signal Detection
In 100BASE-FX operation, FXSD (fiber signal detect), input pin 48, is usually connected to the fiber transceiver SD (signal detect) output pin. The fiber signal threshold can be selected by register 192 bit 6 for port 1 , When FXSD is less than the threshold, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD input pin is tied high to force 100BASE-FX mode.
100BASE-FX signal detection is summarized in the following table:
Register 192 bit 7 bit 6 (port 1)
1
0
Fiber Signal Threshold at FXSD
2.0V
1.2V
Table 1. FX Signal Threshold
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage swing to match the FXSD pin’s input voltage threshold.
100BASE-FX Far-End Fault
A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8863FLL detects a FEF when its FXSD input is below the Fiber Signal Threshold. When a FEF is detected, the
KSZ8863FLL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between frames.
By default, FEF is enabled. FEF can be disabled through register setting.
10BASE-T Transmit
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8863MLL/FLL/RLL decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8863MLL/FLL/RLL supports HP Auto
MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the
KSZ8863MLL/FLL/RLL device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers, or MIIM PHY registers.
The IEEE 802.3u standard MDI and MDI-X definitions are:
1
2
3
MDI
RJ-45 Pins
6
Signals
MDI-X
RJ-45 Pins Signals
TD+ 1 RD+
TD- 2 RD-
RD+ 3 TD+
RD- 6 TD-
Table 2. MDI/MDI-X Pin Definitions
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Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
Figure 1. Typical Straight Cable Connection
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Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
Receive Pair
Transmit Pair
1
2
3
4
5
6
7
8
Crossover
Cable
1
2
3
4
5
6
7
8
Receive Pair
Transmit Pair
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
Figure 2. Typical Crossover Cable Connection
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Auto-Negotiation
The KSZ8863MLL/FLL/RLL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In autonegotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not supported or the KSZ8863MLL/FLL/RLL link partner is forced to bypass auto-negotiation, the KSZ8863MLL/FLL/RLL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8863MLL/FLL/RLL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol.
The link up process is shown in the following flow diagram.
September 2011
Figure 3. Auto-Negotiation and Parallel Operation
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LinkMD
®
Cable Diagnostics
KSZ8863MLL/FLL/RLL supports the LinkMD
®
.
The LinkMD
®
feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches.
LinkMD
®
works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault. Internal circuitry displays the TDR information in a user-readable digital format.
Note: Cable diagnostics are only valid for copper connections and do not support fiber optic operation.
Access
LinkMD
®
is initiated by accessing the PHY special control/status registers {26, 42} and the LinkMD result registers {27, 43} for ports 1 and 2 respectively; and in conjunction with the port registers control 13 for ports 1and 2 respectively to disable
Auto MDI/MDIX.
Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD
®
access.
Usage
The following is a sample procedure for using LinkMD
®
with registers {42,43,45} on port 2.
1. Disable auto MDI/MDI-X by writing a ‘1’ to register 45, bit [2] to enable manual control over the differential pair used to transmit the LinkMD
®
pulse.
2. Start cable diagnostic test by writing a ‘1’ to register 42, bit [4]. This enable bit is self-clearing.
3. Wait (poll) for register 42, bit [4] to return a ‘0’, indicating cable diagnostic test is completed.
4. Read cable diagnostic test results in register 42, bits [6:5]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the KSZ8863MLL/FLL/RLL is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8863MLL/FLL/RLL to determine if the detected signal is a reflection of the signal generated or a signal from another source.
5. Get distance to fault by concatenating register 42, bit [0] and register 43, bits [7:0]; and multiplying the result by a constant of 0.4. The distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.4 x {(register 26, bit [0]),(register 27, bits [7:0])}
D (distance to cable fault) is expressed in meters.
Concatenated value of registers 42 and 43 is converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.
Functional Overview: Power Management
The KSZ8863MLL/FLL/RLL supports enhanced power management feature in low power state with energy detection to ensure low-power dissipation during device idle periods. There are five operation modes under the power management function which is controlled by two bits in Register 195 (0xC3) and one bit in Register 29 (0x1D),45(0x2D) as shown below:
Register 195 bit[1:0] = 00 Normal Operation Mode
Register 195 bit[1:0] = 01 Energy Detect Mode
Register 195 bit[1:0] = 10 Soft Power Down Mode
Register 195 bit[1:0] = 11 Power Saving Mode
Register 29,45 bit 3 =1 Port Based Power Down Mode
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Table 3 indicates all internal function blocks status under four different power management operation modes.
KSZ8863MLL/FLL/RLL
Function Blocks
Internal PLL Clock
Tx/Rx PHY
Power Management Operation Modes
Normal Mode Power Saving Mode
Enabled Enabled
Enabled
Energy Detect Mode
Disabled
Rx unused block disabled Energy detect at Rx
Soft Power Down Mode
Disabled
Disabled
Host Interface Enabled Enabled Disabled
Table 3. Internal Function Block Status
Disabled
Normal Operation Mode
This is the default setting bit[1:0]=00 in register 195 after the chip power-up or hardware reset . When
KSZ8863MLL/FLL/RLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU read or write.
During the normal operation mode, the host CPU can set the bit[1:0] in register 195 to transit the current normal operation mode to any one of the other three power management operation modes.
Energy Detect Mode
The energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8863MLL/FLL/RLL is not connected to an active link partner. In this mode, the device will save up to 87% of the power. If the cable is not plugged, the KSZ8863MLL/FLL/RLL can automatically enter to a low power state, a.k.a., the energy detect mode. In this mode, KSZ8863MLL/FLL/RLL will keep transmitting 120ns width pulses at 1 pulse/s rate.
Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8863MLL/FLL/RLL can automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
KSZ8863MLL/FLL/RLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode is entered by setting bit[1:0]=01 in register 195. When the KSZ8863MLL/FLL/RLL is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] Go-Sleep time in register 196, KSZ8863MLL/FLL/RLL will go into a low power state. When KSZ8863MLL/FLL/RLL is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable,
KSZ8863MLL/FLL/RLL will enter normal power state. When KSZ8863MLL/FLL/RLL is at normal power state, it is able to transmit or receive packet from the cable.
It will save about 87% of the power when MII interface is in PHY mode (Register 53 bit 7 =0), pin SMTXER3/MII_LINK_3 is connected to High, register 195 bit [1:0] =01, bit 2 =1(Disable PLL), not cables are connected.
Soft Power Down Mode
The soft power down mode is entered by setting bit[1:0]=10 in register 195. When KSZ8863MLL/FLL/RLL is in this mode, all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change. When the host set bit[1:0]=00 in register 195, this device will be back from current soft power down mode to normal operation mode.
Power Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit[1:0]=11 in register 195. When KSZ8863MLL/FLL/RLL is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8863MLL/FLL/RLL can automatically enabled the PHY power up to normal power state from power saving mode.
During this power saving mode, the host CPU can set bit[1:0] =0 in register 195 to transit the current power saving mode to any one of the other three power management operation modes.
Port based Power Down Mode
In addition, the KSZ8863MLL/FLL/RLL features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via port control register 29 or 45 bit 3, or MIIM PHY register. It will saves about 15mA per port.
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Functional Overview: MAC and Switch
Address Lookup
The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information.
The KSZ8863MLL/FLL/RLL is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.
Learning
The internal lookup engine updates its table with a new entry if the following conditions are met:
1. The received packet's Source Address (SA) does not exist in the lookup table.
2. The received packet is good; the packet has no receiving errors, and is of legal length.
The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted to make room for the new entry.
Migration
The internal lookup engine also monitors whether a station has moved. If a station has moved, it will update the table accordingly. Migration happens when the following conditions are met:
1. The received packet’s SA is in the table but the associated source port information is different.
2. The received packet is good; the packet has no receiving errors, and is of legal length.
The lookup engine will update the existing record in the table with the new source port information.
Aging
The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record from the table. The lookup engine constantly performs the aging process and will continuously remove aging records. The aging period is about 200 seconds. This feature can be enabled or disabled through register 3 (0x03) bit [2].
Forwarding
The KSZ8863MLL/FLL/RLL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as shown in Figure 5. The packet is sent to PTF2.
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Figure 4. Destination Address Lookup Flow Chart, Stage 1
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Figure 5. Destination Address Resolution Flow Chart, Stage 2
The KSZ8863MLL/FLL/RLL will not forward the following packets:
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors.
2. IEEE802.3x PAUSE frames
KSZ8863MLL/FLL/RLL intercepts these packets and performs full duplex flow control accordingly.
3. "Local" packets
Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local."
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Switching Engine
The KSZ8863MLL/FLL/RLL features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The switching engine has a 32kB internal frame buffer. This buffer pool is shared between all three ports. There are a total of 256 buffers available. Each buffer is sized at 128 bytes.
MAC Operation
The KSZ8863MLL/FLL/RLL strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
Back-Off Algorithm
The KSZ8863MLL/FLL/RLL implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and optional "aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending on the switch configuration for register 4 (0x04) bit [3].
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
Illegal Frames
The KSZ8863MLL/FLL/RLL discards frames less than 64 bytes, and can be programmed to accept frames up to1518 bytes, 1536 bytes or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since the
KSZ8863MLL/FLL/RLL supports VLAN tags, the maximum sizing is adjusted when these tags are present.
Full Duplex Flow Control
The KSZ8863MLL/FLL/RLL supports standard IEEE 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8863MLL/FLL/RLL receives a pause control frame, the KSZ8863MLL/FLL/RLL will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it is flow controlled), only flow control packets from the KSZ8863MLL/FLL/RLL are transmitted.
On the transmit side, the KSZ8863MLL/FLL/RLL has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues.
The KSZ8863MLL/FLL/RLL will flow control a port that has just received a packet if the destination port resource is busy.
The KSZ8863MLL/FLL/RLL issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE
802.3x standard. Once the resource is freed up, the KSZ8863MLL/FLL/RLL sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated.
The KSZ8863MLL/FLL/RLL flow controls all ports if the receive queue becomes full.
Half-Duplex Backpressure
A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation conditions are the same as full duplex flow control. If backpressure is required, the KSZ8863MLL/FLL/RLL sends preambles to defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the
KSZ8863MLL/FLL/RLL discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collisions and carrier sense is maintained to prevent packet reception.
To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following:
• Aggressive back-off (register 3 (0x03), bit [0])
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• No excessive collision drop (register 4 (0x04), bit [3])
Note: These bits are not set as defaults, as this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8863MLL/FLL/RLL has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8863MLL/FLL/RLL has the option to include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. The rate is based on a 67ms interval for 100BT and a 500ms interval for 10BT.
At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting is 0x63
(99 decimal). This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec × 67ms/interval × 1% = 99 frames/interval (approx.) = 0x63
Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8 bytes of preamble between two packets.
Port Individual MAC address and Source Port Filtering
The KSZ8863MLL/FLL/RLL provide individual MAC address for port 1 and port 2 respectively. They can be set at register
142-147 and 148-153. The packet will be filtered if its source address matches the MAC address of port 1 or port 2 when the register 21 and 37 bit 6 is set to 1 respectively. For example, the packet will be dropped after it completes the loop of a ring network.
MII Interface Operation
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common interface between physical layer and MAC layer devices. The MII provided by the KSZ8863MLL/FLL is connected to the device’s third MAC, the MII default is PHY mode and can set to MAC mode by the register 53 bit7. The interface contains two distinct groups of signals: one for transmission and the other for reception. The following table describes the signals used by the MII bus.
PHY-Mode Connections
MTXC
MCOL
MCRS
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
External MAC
Controller Signals
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
KSZ8863MLL/FLL
PHY Signals
SMTXD33
SMTXD32
SMTXD31
SMTXD30
SMRXDV3
(not used)
SMRXD33
SMRXD32
SMRXD31
SMRXD30
Pin
Descriptions
Transmit data bit 3
Transmit data bit 2
Transmit data bit 1
Transmit data bit 0
Receive data valid
Receive error
Receive data bit 3
Receive data bit 2
Receive data bit 1
Receive data bit 0
MAC-Mode Connections
External
PHY Signals
KSZ8863MLL/FLL
MAC Signals
MTXD3
MTXD2
MTXD1
MTXD0
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
SMRXD33
SMRXD32
SMRXD31
SMRXD30
SMTXEN3
SMTXER3
SMTXD33
SMTXD32
SMTXD31
SMTXD30
Table 4. MII Signals
The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate
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(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors.
For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
The KSZ8863MLL/FLL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the
KSZ8863MLL/FLL. So, for PHY mode operation, if the device interfacing with the KSZ8863MLL/FLL has an MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8863MLL/FLL has an
MTXER input pin, it also needs to be tied low.
The KSZ8863MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link status. If the host is power down, pin MII_LINK will go to high. In this case, no new ingress frames from port1 or port 2 will be sent out through port 3, and the frames for port 3 already in packet memory will be flushed out.
RMII Interface Operation
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
1. ports 10Mbps and 100Mbps data rates.
2. Uses a single 50 MHz clock reference (provided internally or externally).
3. Provides independent 2-bit wide (di-bit) transmit and receive data paths.
4. Contains two distinct groups of signals: one for transmission and the other for reception
When EN_REFCLKO_3 is high, KSZ8863RLL will output a 50MHz in REFCLKO_3. Register 198 bit[3] is used to select internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8863RLL will be provided by the KSZ8863RLL internally and the REFCLKI_3 pin is unconnected. For the external reference clock, the clock will provide to KSZ8863RLL via REFCLKI_3.
Note:
If the reference clock is not provided by the KSZ8863RLL, this 50MHz reference clock with an external divide by 2 device has to be used in X1 pin instead of the 25MHz crystal since the clock skew of these two clock sources will impact on the RMII timing before Rev.A3 part. The Rev A3 part can connect the external 50MHz reference clock to X1 pin and SMTXC3/REFCLKI_3 pins directly with strap pins of pin 17 SMTXD33/EN_REFCLKO_3 and pin 18 SMTXD32 to be pulled down.
Reg198 bit[3] Pin 17 SMTXD33
/EN_REFCLKO_3
Pin 18 SMTXD32
Internal pull-up
Clock Source Note
Internal pull-up
(For Rev A3)
0
0
0 (pull down by 1k) 0 (pull down by 1k) External 50MHz OSC input to SMTXC3
/REFCLKI_3 and X1 pin directly
1 0 (pull down by 1k) 50MHz on X1 pin is as clock source.
REFCLKO_3 Output Is
Feedback to REFCLKI_3 externally
EN_REFCLKO_3 = 0 to Disable
REFCLKO_3 for better
EMI
EN_REFCLKO_3 = 1 to Enable REFCLKO_3
EN_REFCLKO_3 = 1 to Enable REFCLKO_3
1 1 0 or 1 clock source.
REFCLKO_3 Output is connected to REFCLKI_3 externally
25MHz on X1 pin,
50MHz RMII Clock goes to SMTXC3/ REFCLKI_3 internally.
REFCLKI_3 is unconnected
EN_REFCLKO_3 = 1 to Enable REFCLKO_3
1 0
September 2011
Table 5. RMII Clock Setting
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The RMII provided by the KSZ8863RLL is connected to the device’s third MAC. It complies with the RMII Specification.
The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal description.
RMII
Signal Name
RXD1
RXD0
Direction
(with respect to the PHY)
Output
Output
Direction
(with respect to the MAC)
RMII
Signal Description
Synchronous 50 MHz clock reference for receive, transmit and control interface
Carrier sense/
Input
Receive data valid
Input
Input
Receive data bit 1
Receive data bit 0
KSZ8863RLL
RMII Signal (direction)
REFCLKI_3 (input)
SMRXDV3 (output)
SMRXD31 (output)
SMRXD30 (output)
TXD1
TXD0
Input
Input
Output
Output
Transmit data bit 1
Transmit data bit 0
Input
RX_ER Output
(not required)
Receive error
SMTXD31 (input)
SMTXD30 (input)
(not used)
--- --- ---
SMTXER3* (input)
* Connects to RX_ER signal of RMII PHY device
Table 6. RMII Signal Description
The KSZ8863RLL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from
RMII PHY devices, the SMTXER3 input signal of the KSZ8863RLL is connected to the RXER output signal of the RMII
PHY device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, tie MII signals, SMTXD3[3:2] and SMTXER3, to ground if they are not used.
The KSZ8863RLL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8863RLL devices to be connected back-to-back. The following table shows the KSZ8863RLL RMII pin connections with an external RMII
PHY and an external RMII MAC, such as another KSZ8863RLL device.
KSZ8863RLL
PHY-MAC Connections
External
PHY Signals
REF_CLK
TX_EN
TXD1
TXD0
CRS_DV
RXD1
RXD0
RX_ER
KSZ8863RLL
KSZ8863RLL
MAC Signals
Pin
Descriptions
MAC-MAC Connections
KSZ8863RLL
MAC Signals
External
MAC Signals
REFCLKI_3 Reference REFCLKI_3 REF_CLK
SMRXDV3
Carrier sense/
Receive data valid
SMRXDV3 CRS_DV
SMRXD31
SMRXD30
Receive data bit 1
Receive data bit 0
SMRXD31 RXD1
SMRXD30 RXD0
SMTXEN3 Transmit SMTXEN3 TX_EN
SMTXD31
SMTXD30
Transmit data bit 1
Transmit data bit 0
SMTXD31 TXD1
SMTXD30 TXD0
(not used) (not used)
Table 7. RMII Signal Connections
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MII Management (MIIM) Interface
The KSZ8863MLL/FLL/RLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8863MLL/FLL/RLL. An external device with MDC/MDIO capability is used to read the PHY status or configure the
PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification and refer to 802.3 section 22.3.4 for the timing.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8863MLL/FLL/RLL device.
• Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM registers
[29, 31].
The MIIM Interface can operate up to a maximum clock speed of 5MHz.
The following table depicts the MII Management Interface frame format.
Preamble Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA Data Bits [15:0] Idle
10
01
Table 8. MII Management Interface Frame Format
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Serial Management Interface (SMI)
The SMI is the KSZ8863MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8863MLL/FLL/RLL configuration registers. This interface allows an external device to completely monitor and control the states of the
KSZ8863MLL/FLL/RLL.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8863MLL/FLL/RLL device.
• Access to all KSZ8863MLL/FLL/RLL configuration registers. Register access includes the Global, Port and Advanced
Control Registers 0-198 (0x00 – 0xC6), and indirect access to the standard MIIM registers [0:5] and custom MIIM registers [29, 31].
The following table depicts the SMI frame format.
Preamble Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA Data Bits [15:0] Idle
Read 32 00
Write 32 00
Table 9. Serial Management Interface (SMI) Frame Format
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8873MLL/FLL/RLL registers 0-196 (0x00 – 0xC6), the following applies:
• PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} = bits
[7:0] of the 8-bit address.
• TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from output mode and the followed ‘0’ is the read response from device.
• TA bits [1:0] are set to ’10’ when write registers.
• Registers are 8 data bits wide.
For read operation, data bits [15:8] are read back as 0’s.
For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in this section.
Advanced Switch Functions
Bypass Mode
The KSZ8863MLL/FLL/RLL also offer a by-pass mode which enables system-level power saving. When the CPU
(connected to Port 3) enters a power saving mode of power down or sleeping mode, the CPU can control the pin 24
SMTXER3/MII_LINK_3 which can be tied high so that the KSZ8863MLL/FLL/RLL detect this change and automatically switches to the by-pass mode in which the switch function between Port1 and Port2 is sustained. In the by-pass mode, the packets with DA to port 3 will be dropped and by pass the internal buffer memory, make the buffer memory more efficiency for the data transfer between port 1 and port 2. Specially, the power saving get more in energy detect mode with the by-pass to be used.
IEEE 802.1Q VLAN Support
The KSZ8863MLL/FLL/RLL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8863MLL/FLL/RLL provides a 16-entries VLAN Table, which converts the 12-bits VLAN ID (VID) to the
4-bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine whether the VID is valid. If the VID is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved for further lookup. The FID + Destination Address (FID+DA) are used to determine the destination port. The FID + Source
Address (FID+SA) are used for address learning.
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DA found in Static MAC
Table?
No
No
Yes
Use FID flag? FID match?
Don’t care
Don’t care
0
Don’t care
Don’t care
Don’t care
KSZ8863MLL/FLL//RLL
DA+FID found in
Dynamic MAC
Table?
No
Action
Yes
Don’t care
Broadcast to the membership ports defined in the VLAN Table bits [18:16]
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Send to the destination port(s) defined in the
Static MAC Address Table bits [50:48]
Table 10. FID+DA Lookup in VLAN Mode
FID+SA found in Dynamic MAC Table?
No
Yes
Action
Learn and add FID+SA to the Dynamic MAC Address Table
Update time stamp
Table 11. FID+SA Lookup in VLAN Mode
Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the
KSZ8863MLL/FLL/RLL. These features can be set on a per port basis, and are defined in register 18, 34 and 50 for ports
1, 2 and 3, respectively.
QoS Priority Support
The KSZ8863MLL/FLL/RLL provides Quality of Service (QoS) for applications such as VoIP and video conferencing.
Offering four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the highest priority queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32 and 48 is used to enable split transmit queues for ports 1, 2 and 3, respectively. If a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four priority queues. This global option is set and explained in bit [3] of register 5.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received at the high priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. Bits [4:3] of registers 16, 32 and 48 are used to enable port-based priority for ports
1, 2 and 3, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8863MLL/FLL/RLL examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as specified by the registers 12 and 13. The “priority mapping” value is programmable.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
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Figure 6. 802.1p Priority Field Format
802.1p-based priority is enabled by bit [5] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively.
The KSZ8863MLL/FLL/RLL provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field
(TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion
is enabled by bit [2] of the port registers control 0 and the register 194 to select which source port (ingress port) PVID can be inserted on the egress port for ports 1, 2 and 3, respectively. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively and the source port VID has to be inserted at selected egress ports by bit[5:0] of register
194. The KSZ8863MLL/FLL/RLL will not add tags to already tagged packets.
Tag Removal
is enabled by bit [1] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8863MLL/FLL/RLL will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping
is a QoS feature that allows the KSZ8863MLL/FLL/RLL to set the “User Priority
Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine priority.
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. The following table shows the port setting and software actions taken for each of the five spanning tree states.
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Disable State
The port should not forward or receive any packets. Learning is disabled.
Blocking State
Only packets to the processor are forwarded. Learning is disabled.
Listening State
Only packets to and from the processor are forwarded.
Learning is disabled.
Learning State
Only packets to and from the processor are forwarded.
Learning is enabled.
Forwarding State
Packets are forwarded and received normally. Learning is enabled.
Port Setting
“transmit enable = 0, receive enable
= 0, learning disable =1”
Port Setting
“transmit enable = 0, receive enable
= 0, learning disable =1”
Port Setting
“transmit enable = 0, receive enable
= 0, learning disable =1”
Software Action
The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the “static MAC table” with “overriding bit” set) and the processor should discard those packets. Address learning is disabled on the port in this state.
Port Setting
“transmit enable = 0, receive enable
= 0, learning disable = 0”
Port Setting
“transmit enable = 1, receive enable = 1, learning disable = 0”
Software Action
The processor should not send any packets to the port(s) in this state. The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state.
Software Action
The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor.
The processor may send packets to the port(s) in this state. See “Tail
Tagging Mode” for details. Address learning is disabled on the port in this state.
Software Action
The processor should program the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor.
The processor may send packets to the port(s) in this state. See “Tail
Tagging Mode” for details. Address learning is enabled on the port in this state.
Software Action
The processor programs the “Static MAC table” with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. See “Tail Tagging Mode” for details.
Address learning is enabled on the port in this state.
Table 12. Spanning Tree States
Rapid Spanning Tree Support
There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP:
Discarding ports do not participate in the active topology and do not learn MAC addresses.
Discarding state: the state includs three states of the disable, blocking and listening of STP.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those packets. When disable the port’s learning capability (learning disable=’1’), set the register 2 bit 5 and bit 4 will flush rapidly the port related entries in the dynamic MAC table and static MAC table.
Note: processor is connected to port 3 via MII interface. Address learning is disabled on the port in this state.
Ports in Learning states learn MAC addresses, but do not forward user traffic.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is enabled on the port in this state.
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Ports in Forwarding states fully participate in both data forwarding and MAC learning.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the exception of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional information.
Tail Tagging Mode
The Tail Tag is only seen and used by the port 3 interface, which should be connected to a processor. It is an effective way to retrieve the ingress port information for spanning tree protocol IGMP snooping and other applications. The Bit 1 and bit 0 in the one byte tail tagging is used to indicate the source/destination port in port 3. Bit 3 and bit 2 are used for the priority setting of the ingress frame in port 3. Other bits are not used. The Tail Tag feature is enable by setting register 3 bit 6.
Ingress to Port 3 (Host -> KSZ8863MML)
Bit [1,0]
0,0
Figure 7. Tail Tag Frame Format
Destination Port
Normal (Address Look up)
1,1
Bit [3,2]
Port 1 and 2
Frame Priority
Egress from Port 3 (KSZ8863MML->Host)
Bit [0] Source Port
Figure 8. Tail Tag Rules
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IGMP Support
For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8863MLL/FLL/RLL provides two components:
IGMP Snooping
The KSZ8863MLL/FLL/RLL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2.
IGMP Send Back to the Subscribed Port
Once the host responds the received IGMP packet, the host should knows the original IGMP ingress port and send back the IGMP packet to this port only, otherwise this IGMP packet will be broadcasted to all port to downgrade the performance.
Enable the tail tag mode, the host will know the IGMP packet received port from tail tag bits [0] and can send back the response IGMP packet to this subscribed port by setting the bits [1,0] in the tail tag. Enable “Tail tag mode” by setting
Register 3 bit 6. The tail tag will be removed automatically when the IGMP packet is sent out from the subscribed port.
Port Mirroring Support
KSZ8863MLL/FLL/RLL supports “Port Mirroring” comprehensively as:
“receive only” mirror on a port
All the packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed to be “receive sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8863MLL/FLL/RLL forwards the packet to both port 2 and port 3. The KSZ8863MLL/FLL/RLL can optionally even forward “bad” received packets to the “sniffer port”.
“transmit only” mirror on a port
All the packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed to be
“transmit sniff” and port 3 is programmed to be the “sniffer port”. A packet received on port 2 is destined to port 1 after the internal lookup. The KSZ8863MLL/FLL/RLL forwards the packet to both port 1 and port 3.
“receive and transmit” mirror on two ports
All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND” feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed to be
“transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8863MLL/FLL/RLL forwards the packet to both port 2 and port 3.
Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer port”.
All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively.
Rate Limiting Support
The KSZ8863MLL/FLL/RLL provides a fine resolution hardware rate limiting from 64Kbps to 99Mbps. The rate step is
64Kbps when the rate range is from 64Kbps to 960Kbps and 1Mbps for 1Mbps to 100Mbps(100BT) or to 10Mbps(10BT)
(refer to Data Rate Limit Table). The rate limit is independently on the “receive side” and on the “transmit side” on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field
(from packet DA to FCS).
For ingress rate limiting, KSZ8863MLL/FLL/RLL provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. The KSZ8863MLL/FLL/RLL counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate.
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To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in the static table, it is also not learned in the dynamic MAC table. The KSZ8863MLL/FLL/RLL is then configured with the option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register 14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8863MLL/FLL/RLL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8863MLL/FLL/RLL is typically programmed using an EEPROM. If no EEPROM is present, the KSZ8863MLL/FLL/RLL is configured using its default register settings. Some default settings are configured via strapin pin options. The strap-in pins are indicated in the “Pin Description and I/O Assignment” table.
I
2
C Master Serial Bus Configuration
With an additional I
2
C (“2-wire”) EEPROM, the KSZ8863MLL/FLL/RLL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
For KSZ8863MLL/FLL/RLL I
2
C Master configuration, the EEPROM stores the configuration data for register 0 to register
120 (as defined in the KSZ8863MLL/FLL/RLL register map) with the exception of the “Read Only” status registers. After the de-assertion of reset, the KSZ8863MLL/FLL/RLL sequentially reads in the configuration data for all 121 registers, starting from register 0.
Figure 9. EEPROM Configuration Timing Diagram
The following is a sample procedure for programming the KSZ8863MLL/FLL/RLL with a pre-configured EEPROM:
1. Connect the KSZ8863MLL/FLL/RLL to the EEPROM by joining the SCL and SDA signals of the respective devices.
2. Enable C master mode by setting the KSZ8863MLL/FLL/RLL strap-in pins, P2LED[1:0] to “00”.
3. Check to ensure that the KSZ8863MLL/FLL/RLL reset signal input, RSTN, is properly connected to the external reset source at the board level.
4. Program the desired configuration data into the EEPROM.
5. Place the EEPROM on the board and power up the board.
6. Assert an active-low reset to the RSTN pin of the KSZ8863MLL/FLL/RLL. After reset is de-asserted, the
KSZ8863MLL/FLL/RLL begins reading the configuration data from the EEPROM. The KSZ8863MLL/FLL/RLL checks that the first byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues.
If not, EEPROM configuration access is denied and all other data sent from the EEPROM is ignored by the
KSZ8863MLL/FLL/RLL.
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I2C Slave Serial Bus Configuration
In managed mode, the KSZ8863MLL/FLL/RLL can be configured as an I
2
C slave device. In this mode, an I
2
C master device (external controller/CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly accessed via registers 121 to 131.
In I
2
C slave mode, the KSZ8863MLL/FLL/RLL operates like other I
2
C slave devices. Addressing the
KSZ8863MLL/FLL/RLL’s 8-bit registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of
I
2
C read/write operations and related timing information can be found in the AT24C02 Datasheet.
Two fixed 8-bit device addresses are used to address the KSZ8863MLL/FLL/RLL in I
2
C slave mode. One is for read; the other is for write. The addresses are as follow:
1011_1111 <read>
1011_1110 <write>
The following is a sample procedure for programming the KSZ8863MLL/FLL/RLL using the I
2
C slave serial bus:
1. Enable C slave mode by setting the KSZ8863MLL/FLL/RLL strap-in pins P2LED[1:0] to “01”.
2. Power up the board and assert reset to the KSZ8863MLL/FLL/RLL. Configure the desired register settings in the
KSZ8863MLL/FLL/RLL, using the I
2
C write operation.
3. Read back and verify the register settings in the KSZ8863MLL/FLL/RLL, using the I
2
C read operation.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down” can be programmed after the switch has been started.
SPI Slave Serial Bus Configuration
In managed mode, the KSZ8863MLL/FLL/RLL can be configured as a SPI slave device. In this mode, a SPI master device (external controller/CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers.
Programming access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are indirectly accessed via registers 121 to 131.
The KSZ8863MLL/FLL/RLL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write. SPI multiple read and multiple write are also supported by the KSZ8863MLL/FLL/RLL to expedite register read back and register configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8863MLL/FLL/RLL SPISN input pin (SPI
Slave Select signal) low after a byte (a register) is read. The KSZ8863MLL/FLL/RLL internal address counter increments automatically to the next byte (next register) after the read. The next byte at the next register address is shifted out onto the KSZ8863MLL/FLL/RLL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by deasserting the SPISN signal to the KSZ8863MLL/FLL/RLL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8863MLL/FLL/RLL SPISN input pin low after a byte (a register) is written. The KSZ8863MLL/FLL/RLL internal address counter increments automatically to the next byte (next register) after the write. The next byte that is sent from the master device to the KSZ8863MLL/FLL/RLL
SDA input pin is written to the next register address. SPI multiple write continues until the SPI master device terminates it by de-asserting the SPISN signal to the KSZ8863MLL/FLL/RLL.
For both SPI multiple read and multiple write, the KSZ8863MLL/FLL/RLL internal address counter wraps back to register address zero once the highest register address is reached. This feature allows all 198 KSZ8863MLL/FLL/RLL registers to be read, or written with a single SPI command from any initial register address.
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The KSZ8863MLL/FLL/RLL is capable of supporting a SPI bus.
The following is a sample procedure for programming the KSZ8863MLL/FLL/RLL using the SPI bus:
1. At the board level, connect the KSZ8863MLL/FLL/RLL pins as follows:
KSZ8863MLL/FLL/RLL Pin #
39 SPI Slave Select
36
37
SPISN
SCL
(SPIC)
SDA
(SPID)
SPI Clock
SPI Data
(Master output; Slave input)
Table 13. SPI Connections
2. Enable SPI slave mode by setting the KSZ8863MLL/FLL/RLL strap-in pins P2LED[1:0] to “10”.
3. Power up the board and assert reset to the KSZ8863MLL/FLL/RLL.
4. Configure the desired register settings in the KSZ8863MLL/FLL/RLL, using the SPI write or multiple write command.
5. Read back and verify the register settings in the KSZ8863MLL/FLL/RLL, using the SPI read or multiple read command.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down” can be programmed after the switch has been started.
The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of
SPIC.
Figure 10. SPI Write Data Cycle
SPIS_N
SPIC
SPID
SPIQ
X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
READ COMMAND READ ADDRESS READ DATA
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Figure 11. SPI Read Data Cycle
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Figure 12. SPI Multiple Write
Figure 13. SPI Multiple Read
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Loopback Support
The KSZ8863MLL/FLL/RLL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near-end
(Remote) Loopback.
Far-end Loopback
Far-end loopback is conducted between the KSZ8863MLL/FLL/RLL’s two PHY ports. The loopback is limited to few package a time for diagnosis purpose and can not support large traffic. The loopback path starts at the “Originating.” PHY port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating”
PHY port’s transmit outputs (TXP/TXM).
Bit [0] of registers 29 and 45 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 0, bit [14] can be used to enable far-end loopback.
The far-end loopback path is illustrated in the following figure.
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Figure 14. Far-End Loopback Path
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Near-end (Remote) Loopback
Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8863MLL/FLL/RLL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXPx/TXMx).
Bit [1] of registers 26 and 42 is used to enable near-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 31, bit [1] can be used to enable near-end loopback.
The near-end loopback paths are illustrated in the following figure.
Figure 15. Near-end (Remote) Loopback Path
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MII Management (MIIM) Registers
The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I
2
C, and SMI interfaces can also be used to access some of these registers. The latter three interfaces use a different mapping mechanism than the
MIIM interface.
The “PHYADs” by defaults are assigned “0x1” for PHY1 (port 1) and “0x2” for PHY2 (port 2). Additionally, these
“PHYADs” can be programmed to the PHY addresses specified in bits[7:3] of Register 15 (0x0F): Global Control 13.
The “REGAD” supported are 0x0-0x5, 0x1D and 0x1F.
Register Number
PHYAD = 0x1, REGAD = 0x0
PHYAD = 0x1, REGAD = 0x1
PHYAD = 0x1, REGAD = 0x2
PHYAD = 0x1, REGAD = 0x3
PHYAD = 0x1, REGAD = 0x4
PHYAD = 0x1, REGAD = 0x5
PHYAD = 0x1, 0x6 – 0x1C
PHYAD = 0x1, 0x1D
PHYAD = 0x1, 0x1E
PHYAD = 0x1, 0x1F
PHYAD = 0x2, REGAD = 0x0
PHYAD = 0x2, REGAD = 0x1
PHYAD = 0x2, REGAD = 0x2
PHYAD = 0x2, REGAD = 0x3
PHYAD = 0x2, REGAD = 0x4
PHYAD = 0x2, REGAD = 0x5
PHYAD = 0x2, 0x6 – 0x1C
PHYAD = 0x2, 0x1D
PHYAD = 0x2, 0x1E
PHYAD = 0x2, 0x1F
Description
PHY1 Basic Control Register
PHY1 Basic Status Register
PHY1 Physical Identifier I
PHY1 Physical Identifier II
PHY1 Auto-Negotiation Advertisement Register
PHY1 Auto-Negotiation Link Partner Ability Register
PHY1 Not supported
PHY1 Not supported
PHY1 Not supported
PHY1 Special Control/Status
PHY2 Basic Control Register
PHY2 Basic Status Register
PHY2 Physical Identifier I
PHY2 Physical Identifier II
PHY2 Auto-Negotiation Advertisement Register
PHY2 Auto-Negotiation Link Partner Ability Register
PHY2 Not supported
PHY2 LinkMD Control/Status
PHY2 Not supported
PHY2 Special Control/Status
September 2011 44 M9999-092111-1.4
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PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control
Bit Name
15
14
Soft reset
Loopback
RO NOT SUPPORTED
R/W = 1, Perform loopback, as indicated:
Port 1 Loopback (reg. 29, bit 0 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 1’s PHY
End: TXP2/TXM2 (port 2)
Port 2 Loopback (reg. 45, bit 0 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 2’s PHY
End: TXP1/TXM1 (port 1)
=0, Normal operation
=1, 100 Mbps
=0, 10 Mbps
12 AN R/W
=0, Auto-negotiation disabled
=1, Power down
=0, Normal operation
10 Isolate
9 Restart R/W
=0, Normal operation
8
7
Force full duplex
Collision test
R/W
RO
=1, Full duplex
=0, Half duplex
NOT SUPPORTED
6 Reserved
5 Hp_mdix
RO
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
4 Force R/W
=0, Normal operation (transmit on TXP / TXM pins)
2
1
Disable far-end fault
Disable transmit
R/W
R/W
=0, Enable auto MDI-X
=1, Disable far-end fault detection
=0, Normal operation
=1, Disable transmit
=0, Normal operation
=1, Disable LED
=0, Normal operation
KSZ8863MLL/FLL/RLL
0
0 Reg. 29, bit 0
Reg. 45, bit 0
0
0
0
1
Reg. 28, bit 6
Reg. 44, bit 6
Reg. 28, bit 7
Reg. 44, bit 7
0 Reg. 29, bit 3
Reg. 45, bit 3
0
0
0
0
0
Reg. 29, bit 5
Reg. 45, bit 5
Reg. 28, bit 5
Reg. 44, bit 5
0
0
1 Reg. 31, bit 7
Reg. 47, bit 7
0 Reg. 29, bit 1
Reg. 45, bit 1
Reg. 29, bit 2
Reg. 45, bit 2
Reg. 29, bit 4
Reg. 29, bit 6
Reg. 45, bit 6
Reg. 29, bit 7
Reg. 45, bit 7
September 2011 45 M9999-092111-1.4
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PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status
Bit Name
15
14
T4 capable
100 Full capable
13 100 Half capable
12
11
10 Full capable
10 Half capable
10-7 Reserved
6
Preamble suppressed
RO =0, Not 100 BASE-T4 capable
RO =1, 100BASE-TX full duplex capable
=0, Not capable of 100BASE-TX full duplex
RO =1, 100BASE-TX half duplex capable
=0, Not 100BASE-TX half duplex capable
RO =1, 10BASE-T full duplex capable
=0, Not 10BASE-T full duplex capable
RO =1, 10BASE-T half duplex capable
=0, Not 10BASE-T half duplex capable
RO
=0, Auto-negotiation not completed
=0, No far-end fault detected
1
0
=1, Auto-negotiation capable
=0, Not auto-negotiation capable
2 Link RO
=0, Link is down
Jabber test
Extended capable
RO NOT SUPPORTED
RO =0, Not extended register capable
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High
Bit Name
15-0 PHYID high RO High order PHYID bits
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low
Bit Name
15-0 PHYID low RO Low order PHYID bits
0
Default
0x0022
Default
0x1430
KSZ8863MLL/FLL/RLL
0000
0
0
0
1
0
0
0
Reg. 30, bit 6
Reg. 46, bit 6
Reg. 31, bit 0
Reg. 28, bit 7
Reg. 44, bit 7
Reg. 30, bit 5
Reg. 46, bit 5
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PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability
KSZ8863MLL/FLL/RLL
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability
Bit Name
15 Next page RO NOT SUPPORTED
14 Reserved RO
13 Remote fault RO NOT SUPPORTED
12-11 Reserved
10 Pause
RO
=1, Advertise pause ability
=0, Do not advertise pause ability
9 Reserved R/W
8 Adv 100 Full R/W =1, Advertise 100 full duplex ability
=0, Do not advertise 100 full duplex ability
7 Adv 100 Half
6
5
Adv 10 Full
Adv 10 Half
R/W =1, Advertise 100 half duplex ability
=0, Do not advertise 100 half duplex ability
R/W
=1, Advertise 10 full duplex ability
=0, Do not advertise 10 full duplex ability
R/W =1, Advertise 10 half duplex ability
=0, Do not advertise 10 half duplex ability
Default Reference
0
0
0
00
1 Reg. 28, bit 4
Reg. 44, bit 4
0
1 Reg. 28, bit 3
Reg. 44, bit 3
1
1
Reg. 28, bit 2
Reg. 44, bit 2
Reg. 28, bit 1
Reg. 44, bit 1
1 Reg. 28, bit 0
Reg. 44, bit 0
00001
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability
Bit Name
15
14
13
Next page
LP ACK
Remote fault
12-11 Reserved
10 Pause
9 Reserved RO
8 Adv 100 Full RO Link partner 100 full capability
7
6
5
Adv 100 Half
Adv 10 Full
Adv 10 Half
4-0 Reserved
RO NOT SUPPORTED
RO NOT SUPPORTED
RO NOT SUPPORTED
RO
RO Link partner pause capability
RO Link partner 100 half capability
RO Link partner 10 full capability
RO Link partner 10 half capability
RO
Default Reference
0
0
0
00
0 Reg. 30, bit 4
Reg. 46, bit 4
0
0 Reg. 30, bit 3
Reg. 46, bit 3
0 Reg. 30, bit 2
Reg. 46, bit 2
0
0
Reg. 30, bit 1
Reg. 46, bit 1
Reg. 30, bit 0
Reg. 46, bit 0
00000
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PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): Not support
KSZ8863MLL/FLL/RLL
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status
Bit Name R/W Description
15 Vct_enable R/W =1, Enable cable diagnostic. After VCT
(SC) test has completed, this bit will be selfcleared.
=0, Indicate cable diagnostic test (if enabled) has completed and the status information is valid for read.
14-13 Vct_result RO
12 Vct 10M Short RO
=00, Normal condition
=01, Open condition detected in cable
=10, Short condition detected in cable
=11, Cable diagnostic test has failed
=1, Less than 10 meter short
11-9 Reserved RO Reserved
8-0 Vct_fault_count RO Distance to the fault.
It’s approximately
0.4m*vct_fault_count[8:0]
Default Reference
0 Reg. 42, bit 4
00 Reg 42, bit[6:5]
0 Reg. 42, bit 7
000
{0, (0x00)} {(Reg. 42, bit 0),
(Reg. 43, bit[7:0])}
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status
Bit Name
15-6 Reserved
5 Polrvs
RO Reserved
0 = polarity is not reversed
0 = MDI-X
1 = Force link pass
0 = Normal Operation
2 Pwrsave R/W
1 = Disable power saving
1 Remote
Loopback
R/W 1 = Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s
PHY
End: TXP1/TXM1 (port 1)
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s
PHY
End: TXP2/TXM2 (port 2)
0 = Normal Operation
0 Reserved R/W
Do not change the default value.
Default Reference
{(0x00),00}
0 Reg. 31, bit 5
Reg. 47, bit 5
Note: This bit is only valid for 10BT
0
0
Reg. 30, bit 7
Reg. 46, bit 7
Reg. 26, bit 3
Reg. 42, bit 3
1
0
Reg. 26, bit 2
Reg. 42, bit 2
Reg. 26, bit 1
Reg. 42, bit 1
0
September 2011 48 M9999-092111-1.4
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Memory Map (8-bit Registers)
Global Registers
Register (Decimal) Register (Hex)
0-1
2-15
0x00-0x01
0x02-0x0F
Port Registers
Register (Decimal) Register (Hex)
16-29 0x10-0x1D
30-31
32-45
46-47
48-57
0x1E-0x1F
0x20-0x2D
0x2E-0x2F
0x30-0x39
Description
Chip ID Registers
Global Control Registers
Description
Port 1 Control Registers, including MII PHY Registers
Port 1 Status Registers, including MII PHY Registers
Port 2 Control Registers, including MII PHY Registers
Port 2 Status Registers, including MII PHY Registers
Port 3 Control Registers
63 0x3F Port 3 Status Register
Advanced Control Registers
Register (Decimal) Register (Hex)
96-111 0x60-0x6F
112-117 0x70-0x75
121-122
123-131
0x79-0x7A
0x7B-0x83
Description
TOS Priority Control Registers
Switch Engine’s MAC Address Registers
Indirect Access Control Registers
Indirect Data Registers
154-165
166
0x9A-0xA5
0xA6
Egress data rate limit
Device mode indicator
167-170 0xA7-0xAA Priority Packet Buffer Reserved
171-174 0xAB-0xAE PM Usage Flow Control Select Mode
175-186 0xAF-0xBA Split
187-188 0xBB-0xBC Link Change Interrupt register
189
192
194
195
0xBD
0xC0
0xC2
0xC3
Force Pause Off Iteration Limit Enable
Fiber Signal Threshold
Insert SRC PVID
Power Management and LED Mode
198 0xC6 Forward Invalid VID Frame and Host Mode
KSZ8863MLL/FLL/RLL
September 2011 49 M9999-092111-1.4
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Register Description
Global Registers (Registers 0 – 15)
Register 0 (0x00): Chip ID0
Bit Name
7-0 Family ID RO Chip family
Register 1 (0x01): Chip ID1 / Start Switch
Bit Name
7-4
3-1
0
Chip ID
Revision ID
Start Switch
RO 0x3 is assigned to M series. (73M)
RO Revision ID
RW =1, start the switch (default)
0=, stop the switch
Register 2 (0x02): Global Control 0
Bit Name
7 New Back-off
Enable
R/W New back-off algorithm designed for UNH
=1, Enable
=0, Disable
6 Reserved RO
5 Flush Dynamic
MAC Table
R/W =1, enable flush dynamic MAC table for spanning tree application
=disable
4 Flush Static
MAC Table
R/W =1, enable flush static MAC table for spanning tree application
=disable,
3 Pass Flow
Control Packet
R/W = 1, switch will pass 802.1x “flow control” packets
=0, switch will drop 802.1x “flow control” packets
2 Reserved R/W
Do not change the default value.
1 Reserved R/W
Do not change the default value.
0 Reserved RO
KSZ8863MLL/FLL/RLL
Default
0x88
Default
0x3
-
1
Default
0
0
0
0
0
0
0
0
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Register 3 (0x03): Global Control 1
Bit Name
7
Pass All
Frames
6 Port 3 Tail Tag
Mode Enable
5
4
3
IEEE 802.3x
Transmit
Direction Flow
Control Enable
IEEE 802.3x
Receive
Direction Flow
Control Enable
Frame Length
Field Check
R/W = 1, switch all packets including bad ones. Used solely for debugging purposes. Works in conjunction with sniffer mode only.
R/W =1, Enable port 3 tail tag mode.
=0, Disable.
R/W = 1, will enable transmit direction flow control feature.
= 0, will not enable transmit direction flow control feature. Switch will not generate any flow control (PAUSE) frame.
R/W = 1, will enable receive direction flow control feature.
= 0, will not enable receive direction flow control feature. Switch will not react to any flow control (PAUSE) frame it receives.
2
1
Aging Enable
R/W =1, will check frame length field in the IEEE packets. If the actual length does not match, the packet will be dropped (for Length/Type field < 1500).
=0, not check
R/W 1 = enable age function in the chip
0 = disable age function in the chip
R/W 1 = turn on fast age (800us)
0
Fast Age
Enable
Aggressive
Back-off
Enable
R/W 1 = enable more aggressive back off algorithm in half duplex mode to enhance performance. This is not an IEEE standard.
Register 4 (0x04): Global Control 2
Bit Name
7 Unicast
6
4
3
Port-VLAN
Mismatch
Discard
Multicast
Storm
Protection
Disable
R/W This feature is used with port-VLAN (described in reg. 17, reg. 33,
…)
= 1, all packets can not cross VLAN boundary
= 0, unicast packets (excluding unkown/multicast/ broadcast) can cross VLAN boundary
Note: Port mirroring is not supported if this bit is set to “0”.
R/W = 1, “Broadcast Storm Protection” does not include multicast packets. Only DA = FF-FF-FF-FF-FF-FF packets will be regulated.
= 0, “Broadcast Storm Protection” includes DA = FF-FF-FF-
FF-FF-FF and DA[40] = 1 packets.
Pressure = 1, carrier sense based backpressure is selected
Mode = 0, collision based backpressure is selected
Flow Control and Back
Pressure Fair
Mode
R/W = 1, fair mode is selected. In this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time.
= 0, in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be “fair” to the flow control port.
No Excessive
Collision Drop
R/W = 1, the switch will not drop packets when 16 or more collisions occur.
= 0, the switch will drop packets when 16 or more collisions occur.
KSZ8863MLL/FLL/RLL
Default
0
0
1
1
0
1
0
0
Default
1
1
1
1
0
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Bit Name
2 Huge Packet
Support
R/W = 1, will accept packet sizes up to 1916 bytes (inclusive). This bit setting will override setting from bit 1 of this register.
1 Legal
Maximum
Packet Size
Check Enable
R/W
= 0, the max packet size will be determined by bit 1 of this register.
= 0, will accept packet sizes up to 1536 bytes (inclusive).
= 1, 1522 bytes for tagged packets, 1518 bytes for untagged packets. Any packets larger than the specified value will be dropped.
0 Reserved R/W
Do not change the default value.
Register 5 (0x05): Global Control 3
Bit Name
7 802.1Q VLAN
Enable
6
5
IGMP Snoop
Enable on
Switch MII
Interface
Reserved
R/W = 1, 802.1Q VLAN mode is turned on. VLAN table needs to set up before the operation.
= 0, 802.1Q VLAN is disabled.
R/W =1, IGMP snoop is enabled. All IGMP packets will be forwarded to the Switch MII port.
=0, IGMP snoop is disabled.
4
3
2
1
0
Reserved
Weighted
Fair Queue
Enable
Reserved
Reserved
Sniff Mode
Select
RO Reserved
Do not change the default values.
RO Reserved
Do not change the default values.
R/W = 0, Priority method set by the registers 175-186 bit [7]=0 for port 1, port 2 and port 3.
= 1, Weighted Fair Queueing enabled. When all four queues have packets waiting to transmit, the bandwidth allocation is q3:q2:q1:q0
= 8:4:2:1.
If any queues are empty, the highest non-empty queue gets one more weighting. For example, if q2 is empty, q3:q2:q1:q0 becomes
(8+1):0:2:1.
RO Reserved
Do not change the default values.
RO Reserved
Do not change the default values.
R/W = 1, will do RX AND TX sniff (both source port and destination port need to match)
= 0, will do RX OR TX sniff (either source port or destination port needs to match). This is the mode used to implement RX only sniff.
KSZ8863MLL/FLL/RLL
Default
0
0
0
Default
0
0
0
0
0
0
0
0
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Register 6 (0x06): Global Control 4
Bit Name
7 Reserved
Reserved
Do not change the default values.
6 Switch MII Half
Duplex Mode
R/W = 1, enable MII interface half-duplex mode.
= 0, enable MII interface full-duplex mode.
5
4
Switch MII
Flow Control
Enable
Switch MII
10BT
R/W = 1, enable full duplex flow control on Switch MII interface.
= 0, disable full duplex flow control on Switch MII interface.
3
2-0
Null VID
Replacement
Broadcast
Storm
Protection
Rate
(1)
Bit [10:8]
R/W = 1, the switch interface is in 10Mbps mode
= 0, the switch interface is in 100Mbps mode
R/W = 1, will replace NULL VID with port VID (12 bits)
= 0, no replacement for NULL VID
R/W This register along with the next register determines how many “64 byte blocks” of packet data are allowed on an input port in a preset period. The period is 67ms for 100BT or 500ms for 10BT. The default is 1%.
Register 7 (0x07): Global Control 5
Bit Name
7-0 Broadcast
Storm
Protection
Rate
(1)
Bit [7:0]
R/W This register along with the previous register determines how many
“64 byte blocks” of packet data are allowed on an input port in a preset period. The period is 67ms for 100BT or 500ms for 10BT.
The default is 1%.
Note:
(1) 100BT Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63
KSZ8863MLL/FLL/RLL
Default
0
0
1
0
0
000
Default
0x63
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Register 8 (0x08): Global Control 6
Bit Name
7-0
Factory
Testing
RO Reserved
Do not change the default values.
Register 9 (0x09): Global Control 7
Bit Name
7-0 Factory
Testing
RO Reserved
Do not change the default values.
Register 10 (0x0A): Global Control 8
Bit Name
7-0 Factory
Testing
RO Reserved
Do not change the default values.
Register 11 (0x0B): Global Control 9
Bit Name
7-6 CPU interface
Clock
Selection
5-4
3-2
1
0
Reserved
Reserved
Reserved
Reserved
R/W =00, 31.25MHz supports SPI speed below 6MHz
=01, 62.5MHz supports SPI speed between 6MHz to 12.5MHz
=10, 125MHz supports SPI speed above 12.5MHz
Note: Lower clock speed will save more power consumption, It is better set to to 31.25MHz if SPI doesn’t request a high speed.
RO N/A Don’t change
RO N/A Don’t change
RO N/A Don’t change
RO N/A Don’t change
Register 12 (0x0C): Global Control 10
Bit Name R/W Description
7-6 Tag_0x3 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x3.
5-4 Tag_0x2 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x2.
3-2 Tag_0x1 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x1.
1-0 Tag_0x0 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x0.
Register 13 (0x0D): Global Control 11
Bit Name R/W
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x7.
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x6.
3-2 Tag_0x5 R/W priority when its IEEE 802.1p tag has a value of 0x5.
KSZ8863MLL/FLL/RLL
Default
0x00
Default
0x24
Default
0x35
Default
10
00
10
0
0
Default
01
01
00
00
Default
11
11
10
10 priority when its IEEE 802.1p tag has a value of 0x4.
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Register 14 (0x0E): Global Control 12
Bit Name R/W
7
Unknown
Packet
Default
Port
Enable
R/W Send packets with unknown destination MAC addresses to specified port(s) in bits [2:0] of this register.
0 = disable
1 = enable
6 Drive
Strength of I/O Pad
0: 8mA
Do not change the default values.
2-0
Do not change the default values.
Unknown
Packet
Default
Port
Do not change the default values.
R/W
Specify which port(s) to send packets with unknown destination MAC addresses. This feature is enabled by bit [7] of this register.
Bit 2 stands for port 3.
Bit 1 stands for port 2.
Bit 0 stands for port 1.
An ‘1’ includes a port.
An ‘0’ excludes a port.
Register 15 (0x0F): Global Control 13
Bit Name R/W
7-3 PHY
Address
R/W 00000 : N/A
00001 : Port 1 PHY address is 0x1
00010 : Port 1 PHY address is 0x2
…
11101 : Port 1 PHY address is 0x29
11110 : N/A
11111 : N/A
Note:
Port 2 PHY address = (Port 1 PHY address) + 1
Reserved
Do not change the default values.
KSZ8863MLL/FLL/RLL
Default
0
1
0
0
0
111
Default
00001
000
September 2011 55 M9999-092111-1.4
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Port Registers (Registers 16 – 95)
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated.
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0
Bit Name
7 Broadcast
Storm
Protection
Enable
6
5
4-3
DiffServ
Priority
Classification
Enable
802.1p
Priority
Classification
Enable
Port-based
Priority
Classification
R/W = 1, enable broadcast storm protection for ingress packets on port
= 0, disable broadcast storm protection
R/W = 1, enable DiffServ priority classification for ingress packets (IPv4) on port
= 0, disable DiffServ function
R/W = 1, enable 802.1p priority classification for ingress packets on port
= 0, disable 802.1p
R/W = 00, ingress packets on port will be classified as priority 0 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify.
= 01, ingress packets on port will be classified as priority 1 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify.
= 10, ingress packets on port will be classified as priority 2 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify.
= 11, ingress packets on port will be classified as priority 3 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify.
Note: “DiffServ”, “802.1p” and port priority can be enabled at the same time. The OR’ed result of 802.1p and DSCP overwrites the port priority.
Default
0
0
0
00
0
1
0
Tag
Removal
TXQ Split
Enable tags to packets without 802.1p/q tags when received. The switch will not add tags to packets already tagged. The tag inserted is the ingress port’s “port VID”.
= 0, disable tag insertion
R/W = 1, when packets are output on the port, the switch will remove
802.1p/q tags from packets with 802.1p/q tags when received. The switch will not modify packets received without tags.
= 0, disable tag removal
R/W = 1, split TXQ to 4 queue configuration. It cannot be enable at the same time with split 2 queue at register 18, 34,50 bit 7.
= 0, no split, treated as 1 queue configuration
0
0
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Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
Bit Name
6
5
4
Receive
Sniff
= 1, Port is designated as sniffer port and will transmit packets that are monitored.
= 0, Port is a normal port
R/W = 1, All packets received on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port”
= 0, no receive monitoring
Transmit
Sniff
R/W = 1, All packets transmitted on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port”
= 0, no transmit monitoring
Double Tag R/W = 1, All packets will be tagged with port default tag of ingress port regardless of the original packets are tagged or not
= 0, do not double tagged on all packets
KSZ8863MLL/FLL/RLL
Default
0
0
0
0
0
2-0
Ceiling
Port VLAN membership field” in the port default tag register, replace the packet’s “user priority field” with the “user priority field” in the port default tag register.
= 0, do not compare and replace the packet’s ‘user priority field”
R/W Define the port’s egress port VLAN membership. The port can only communicate within the membership. Bit 2 stands for port 3, bit 1 stands for port 2, bit 0 stands for port 1.
An ‘1’ includes a port in the membership.
An ‘0’ excludes a port from membership.
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Bit Name
7 Enable 2
Queue Split of Tx Queue
6
5
4
Ingress
VLAN
Filtering
Discard non
PVID
Packets
Force Flow
Control
It cannot be enable at the same time with split 4 queue at register 16,32 and 48 bit 0.
=0, Disable
R/W = 1, the switch will discard packets whose VID port membership in
VLAN table bits [18:16] does not include the ingress port.
= 0, no ingress VLAN filtering.
R/W = 1, the switch will discard packets whose VID does not match ingress port default VID.
= 0, no packets will be discarded
R/W = 1, will always enable full duplex flow control on the port, regardless of
AN result.
= 0, full duplex flow control is enabled based on AN result.
111
Default
0
0
0
Pin value during reset:
For port 1, SPIQ pin
(defult is PD)
For port 2, SMRXD30 pin
For port 3, this bit has no meaning. Flow
Control is set by Reg.
6, bit 5.
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Bit Name
3
2
Back
Pressure
Enable
Transmit
Enable
R/W = 1, enable port’s half duplex back pressure
= 0, disable port’s half duplex back pressure
1 Receive
0
Enable
Learning
Disable
R/W = 1, enable packet transmission on the port
= 0, disable packet transmission on the port
R/W = 1, enable packet reception on the port
= 0, disable packet reception on the port
R/W = 1, disable switch address learning capability
= 0, enable switch address learning
Note:
Bits [2:0] are used for spanning tree support.
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Bit Name
[15:8]
Tag R/W Port’s
7-5 : User priority bits
4 : CFI bit
3-0 : VID[11:8]
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Bit Name
Tag R/W Port’s
[7:0]
Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
Associated with the ingress untagged packets, and used for egress tagging.
Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
Bit Name
7 Port 3 MII mode
Selection
6
5
Self-address filtering enable
MACA1
(not for
0x35)
Self-address filtering enable
September 2011
R/W 1: Port 3 MII MAC mode
0: Port 3 MII PHY mode
Note: Bit 7 is reserved for port 1 and port 2
R/W =1, enable port 1 self-address filtering MACA1
=0, disable
R/W =1, enable port 2 Self-address filtering MACA2
=0, disable
58
KSZ8863MLL/FLL/RLL
Default
0
1
1
0
Default
0x00
Default
0x01
Default
0
0
0
M9999-092111-1.4
Micrel, Inc.
Bit Name
MACA2
(not for
0x35)
4
3-2
Drop Ingress
Tagged
Frame
Limit Mode
=0, Disable
1
0
Count IFG
Count Pre
R/W Ingress Limit Mode
These bits determine what kinds of frames are limited and counted against ingress rate limiting.
= 00, limit and count all frames
= 01, limit and count Broadcast, Multicast, and flooded unicast frames
= 10, limit and count Broadcast and Multicast frames only
= 11, limit and count Broadcast frames only
R/W Count IFG bytes
= 1, each frame’s minimum inter frame gap
(IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting calculations.
= 0, IFG bytes are not counted.
R/W Count Preamble bytes
= 1, each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations.
= 0, preamble bytes are not counted.
Register 22[6:0] (0x16): Port 1 Q0 ingress data rate limit
Register 38[6:0] (0x26): Port 2 Q0 ingress data rate limit
Register 54[6:0] (0x36): Port 3 Q0 ingress data rate limit
7
6-0
RMII
REFCLK
INVERT.
Q0 Ingress
Data Rate limit
R/W 1: Port 3 inverted refclk selected
0: Port 3 original refclk selected
Note: Bit 7 is reserved for port 1 and port 2
R/W Ingress data rate limit for priority 0 frames
Ingress traffic from this priority queue is shaped according to the ingress Data Rate Selected Table.
KSZ8863MLL/FLL/RLL
Default
0
00
0
0
Default
0
Note: Not Applied to
Reg.22 and 38(Port 1,
Port 2)
0
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Register 23[6:0] (0x17): Port 1 Q1 ingress data rate limit
Register 39[6:0] (0x27): Port 2 Q1 ingress data rate limit
Register 55[6:0] (0x37): Port 3 Q1 ingress data rate limit
Bit Name
7 Reserved R/W
Do not change the default values.
6-0 Q1 Ingress data Rate limit
R/W Ingress data rate limit for priority 1 frames
Ingress traffic from this priority queue is shaped according to the ingress Data Rate Selected Table.
Register 24[6:0] (0x18): Port 1 Q2 ingress data rate limit
Register 40[6:0] (0x28): Port 2 Q2 ingress data rate limit
Register 56[6:0] (0x38): Port 3 Q2 ingress data rate limit
Bit Name
7 Reserved R/W
Do not change the default values.
6-0 Q2 Ingress
Data Rate limit
R/W Ingress data rate limit for priority 2 frames
Ingress traffic from this priority queue is shaped according to ingress
Data Rate Selection Table.
Register 25[6:0] (0x19): Port 1 Q3 ingress data rate limit
KSZ8863MLL/FLL/RLL
Default
0
0
Default
0
0
Register 41[6:0] (0x29): Port 2 Q3 ingress data rate limit
Register 57[6:0] (0x39): Port 3 Q3 ingress data rate limit
Bit Name
7 Reserved RO
Do not change the default values.
6-0 Q3 Ingress
Data Rate limit
R/W Ingress data rate limit for priority 3 frames
Ingress traffic from this priority queue is shaped according to ingress
Data Rate Selection Table.
Default
0
0
Note:
Most of the contents in registers 26-31 and registers 42-47 for ports 1 and 2, respectively, can also be accessed with the MIIM PHY registers.
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Data Rate Limit for ingress or egress
64 Kbps
128 Kbps
192 Kbps
256 Kbps
320 Kbps
384 Kbps
448 Kbps
512 Kbps
576 Kbps
640 Kbps
704 Kbps
768 Kbps
832 Kbps
896 Kbps
960 Kbps
KSZ8863MLL/FLL/RLL
100BT
Register bit[6:0], Q=0..3
1 to 0x63 for the Rate
1Mbps to 99Mbps.
0 or 0x64 for the rate
100Mbps
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
Table 14. Data Rate Limit Table
10BT
Register bit[6:0], Q=0..3
1 to 0x09 for the rate
1Mbps to 9Mbps
0 or 0x0A for the rate
10Mbps
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Register 26 (0x1A): Port 1 PHY Special Control/Status
Register 42 (0x2A): Port 2 PHY Special Control/Status
Register 58 (0x3A): Reserved, not applied to port 3
Bit Name
7
6-5
Vct 10M Short
Vct_result
RO
RO
=1, Less than 10 meter short
=00, Normal condition
=01, Open condition detected in cable
=10, Short condition detected in cable
=11, Cable diagnostic test has failed
4 Vct_en
3 Force_lnk
(SC) this bit will be self-cleared.
=0, Indicate cable diagnostic test (if enabled) has completed and the status information is valid for read.
R/W =1, Force link pass
=0, Normal Operation
2
1
Do not change the default value.
Remote Loopback R/W =1, Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
=0, Normal Operation
KSZ8863MLL/FLL/RLL
Default
0
00
0
0
0
0
0
Distance to the fault.
It’s approximately 0.4m*vct_fault_count[8:0]
Register 27 (0x1B): Port 1 Not support
Register 43 (0x2B): Port 2 LinkMD Result
Register 59 (0x3B): Reserved, not applied to port 3
Bit Name
7-0 Vct_fault_count[7:
0]
RO
Bits[7:0] of VCT fault count
Distance to the fault.
It’s approximately 0.4m*Vct_fault_count[8:0]
Default
0x00
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Register 28 (0x1C): Port 1 Control 12
Register 44 (0x2C): Port 2 Control 12
Register 60 (0x3C): Reserved, not applied to port 3
Bit Name
7 Auto
Negotiation
Enable
R/W = 1, auto negotiation is on
= 0, disable auto negotiation; speed and duplex are determined by bits 6 and 5 of this register.
6 Force Speed R/W = 1, forced 100BT if AN is disabled (bit 7)
= 0, forced 10BT if AN is disabled (bit 7)
4
3
2
1
0
Advertise
100BT Full
Duplex
Capability
Advertise
100BT Half
Duplex
Capability
Advertise
10BT Full
Duplex
Capability
Advertise
10BT Half
Duplex
Capability
= 1, forced full duplex if (1) AN is disabled or (2) AN is enabled but failed.
= 0, forced half duplex if (1) AN is disabled or (2) AN is enabled but failed.
Note: This bit or strap pin should be set to ‘0’ for the correct duplex mode indication of LED and register status when the link-up is AN to force mode.
Advertise Flow
Control capability
R/W = 1, advertise flow control (pause) capability
= 0, suppress flow control (pause) capability from transmission to link partner
R/W = 1, advertise 100BT full duplex capability
= 0, suppress 100BT full duplex capability from transmission to link partner
R/W
R/W
R/W
= 1, advertise 100BT half duplex capability
= 0, suppress 100BT half duplex capability from transmission to link partner
= 1, advertise 10BT full duplex capability
= 0, suppress 10BT full duplex capability from transmission to link partner
= 1, advertise 10BT half duplex capability
= 0, suppress 10BT half duplex capability from transmission to link partner
Register 29 (0x1D): Port 1 Control 13
Register 45 (0x2D): Port 2 Control 13
Register 61 (0x3D): Reserved, not applied to port 3
Bit Name
6 Txdis
= 1, turn off all port’s LEDs (LEDx_1, LEDx_0, where “x” is the port number). These pins will be driven high if this bit is set to one.
= 0, normal operation
R/W = 1, disable the port’s transmitter
= 0, normal operation
KSZ8863MLL/FLL/RLL
Default
1
For port 1, P1LED0 pin value during reset.(default is PD)
For port 2, SMRXD33 pin value during reset
1
For port 1, P1LED1 pin value during reset.
For port 2, SMRXD32 pin value during reset.
1
For port 1, SMRXDV3 pin value during reset.
For port 2, SMRXD31 pin value during reset.
1
1
1
1
1
Default
0
0
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Bit Name
5
4
3
2
1
0
Restart AN
Disable Far- end Fault
Power Down
Disable Auto
MDI/MDI-X
Force MDI
Loopback
R/W = 1, restart auto-negotiation
= 0, normal operation
R/W = 1, disable far-end fault detection and pattern transmission.
= 0, enable far-end fault detection and pattern transmission
R/W = 1, power down
= 0, normal operation
R/W = 1, disable auto MDI/MDI-X function
= 0, enable auto MDI/MDI-X function
R/W If auto MDI/MDI-X is disabled,
= 1, force PHY into MDI mode (transmit on RXP/RXM pins)
= 0, force PHY into MDI-X mode (transmit on TXP/TXM pins)
R/W = 1, perform loopback, as indicated:
Port 1 Loopback (reg. 29, bit 0 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 1’s PHY
End: TXP2/TXM2 (port 2)
Port 2 Loopback (reg. 45, bit 0 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 2’s PHY
End: TXP1/TXM1 (port 1)
= 0, normal operation
Register 30 (0x1E): Port 1 Status 0
Register 46 (0x2E): Port 2 Status 0
Register 62 (0x3E): Reserved, not applied to port 3
Bit Name
7 MDI-X Status
6
5
4
AN Done
Link Good
RO = 1, MDI
= 0, MDI-X
RO = 1, auto-negotiation completed
= 0, auto-negotiation not completed
RO = 1, link good
= 0, link not good
RO = 1, link partner flow control (pause) capable
= 0, link partner not flow control (pause) capable
3
2
1
0
Partner Flow
Control
Capability
Partner 100BT
Full Duplex
Capability
Partner 100BT
Half Duplex
Capability
Partner 10BT
Full Duplex
Capability
Partner 10BT
RO = 1, link partner 100BT full duplex capable
= 0, link partner not 100BT full duplex capable
RO = 1, link partner 100BT half duplex capable
= 0, link partner not 100BT half duplex capable
RO = 1, link partner 10BT full duplex capable
= 0, link partner not 10BT full duplex capable
RO = 1, link partner 10BT half duplex capable
September 2011 64
KSZ8863MLL/FLL/RLL
Default
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
0
M9999-092111-1.4
Micrel, Inc.
Bit Name
Half Duplex
Capability
= 0, link partner not 10BT half duplex capable
Register 31 (0x1F): Port 1 Status 1
Register 47 (0x2F): Port 2 Status 1
Register 63 (0x3F): Port 3 Status 1
Bit Name
7 Hp_mdix R/W 1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
KSZ8863MLL/FLL/RLL
Default
6 Reserved RO
5 Polrvs
Do not change the default value.
RO 1 = polarity is reversed
0 = polarity is not reversed
4
3
2
1
0
Transmit Flow
Control Enable
Receive Flow
Control Enable
Operation
Speed
Operation
Duplex
Far-end Fault
RO 1 = transmit flow control feature is active
0 = transmit flow control feature is inactive
RO 1 = receive flow control feature is active
0 = receive flow control feature is inactive
RO 1 = link speed is 100Mbps
0 = link speed is 10Mbps
RO 1 = link duplex is full
0 = link duplex is half
RO = 1, Far-end fault status detected
= 0, no Far-end fault status detected
Register 67 (0x43): Reset
Bit Name
4 Software
Reset
R/W =1, Software reset
=0, Clear
Note: Software reset will reset all registers to the initial values of the power-on reset or warm reset (keep the strap values). compelete reset
=0, Clear
Note: PCS reset will reset the state machine and clock domain in PHY’s PCS layer.
Default
1
Note:
Only ports 1 and 2 are PHY ports.
This bit is not applicable to port 3
(MII).
0
0
Note:
This bit is not applicable to port 3 (MII).
This bit is only valid for 10BT
0
0
0
0
0
This bit is applicable to port 1 only.
Default
0
0
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Advanced Control Registers (Registers 96-198)
The IPv4/IPv6 TOS Priority Control Registers implement a fully decoded, 128-bit DSCP (Differentiated Services Code
Point) register set that is used to determine priority from the ToS (Type of Service) field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bits in the DSCP register to determine the priority.
Register 96 (0x60): TOS Priority Control Register 0
Bit Name
7-6 DSCP[7:6] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x03.
5-4 DSCP[5:4] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x02.
3-2 DSCP[3:2] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x01.
1-0 DSCP[1:0] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x00.
Register 97 (0x61): TOS Priority Control Register 1
Bit Name
Default
00
00
00
00
Default
00 bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x07.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x06.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x05.
1-0 DSCP[9:8] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x04.
Register 98 (0x62): TOS Priority Control Register 2
Bit Name
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0B.
00
00
00
Default
00
00 bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0A.
3-2 DSCP[19:18] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x09.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x08.
00
00
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Register 99 (0x63): TOS Priority Control Register 3
Bit Name
7-6 DSCP[31:30] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0F.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0E. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0D.
1-0 DSCP[25:24] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0C.
Register 100 (0x64): TOS Priority Control Register 4
Bit Name
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x13. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x12.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x11. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x10.
Register 101 (0x65): TOS Priority Control Register 5
Bit Name
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x17.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x16. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x15.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x14.
KSZ8863MLL/FLL/RLL
Default
00
00
00
00
Default
00
00
00
00
Default
00
00
00
00
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Register 102 (0x66): TOS Priority Control Register 6
Bit Name
7-6 DSCP[55:54] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1B.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1A. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x19.
1-0 DSCP[49:48] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x18.
Register 103 (0x67): TOS Priority Control Register 7
Bit Name
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1F. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1E.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1D. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1C.
Register 104 (0x68): TOS Priority Control Register 8
Bit Name
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x23.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x22. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x21.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x20.
KSZ8863MLL/FLL/RLL
Default
00
00
00
00
Default
00
00
00
00
Default
00
00
00
00
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Register 105 (0x69): TOS Priority Control Register 9
Bit Name
7-6 DSCP[79:78] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x27.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x26. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x25.
1-0 DSCP[73:72] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x24.
Register 106 (0x6A): TOS Priority Control Register 10
Bit Name
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2B. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2A.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x29. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x28.
Register 107 (0x6B): TOS Priority Control Register 11
Bit Name
7-6 DSCP[95:94] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2F.
5-4 DSCP[93:92] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2E.
3-2 DSCP[91:90] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2D.
1-0 DSCP[89:88] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2C.
KSZ8863MLL/FLL/RLL
Default
00
00
00
00
Default
00
00
00
00
Default
00
00
00
00
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Register 108 (0x6C): TOS Priority Control Register 12
Bit Name
7-6 DSCP[103:102] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x33.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x32. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x31.
1-0 DSCP[97:96] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x30.
Register 109 (0x6D): TOS Priority Control Register 13
Bit Name
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x37. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x36.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x35. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x34.
Register 110 (0x6E): TOS Priority Control Register 14
Bit Name
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x3B.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x3A. bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x39.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x38.
KSZ8863MLL/FLL/RLL
Default
00
00
00
00
Default
00
00
00
00
Default
00
00
00
00
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Register 111 (0x6F): TOS Priority Control Register 15
Bit Name
7-6 DSCP[127:126] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x3F.
The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x3E.
KSZ8863MLL/FLL/RLL
Default
00
00
00 bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x3D.
1-0 DSCP[121:120] R/W bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x3C.
00
Registers 112 to 117
Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address is used as the Source Address for the
MAC’s full duplex flow control (PAUSE) frame.
Register 112 (0x70): MAC Address Register 0
Bit Name
7-0 MACA[47:40] R/W
Register 113 (0x71): MAC Address Register 1
Bit Name
7-0 MACA[39:32] R/W
Register 114 (0x72): MAC Address Register 2
Bit Name
7-0 MACA[31:24] R/W
Register 115 (0x73): MAC Address Register 3
Bit Name
7-0 MACA[23:16] R/W
Register 116 (0x74): MAC Address Register 4
Bit Name
7-0 MACA[15:8] R/W
Register 117 (0x75): MAC Address Register 5
Bit Name
7-0 MACA[7:0] R/W
Default
0x00
Default
0x10
Default
0xA1
Default
0xFF
Default
0xFF
Default
0xFF
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Registers 118 to 120
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KSZ8863 and the external processor.
Register 118 (0x76): User Defined Register 1
Bit Name
7-0 UDR1 R/W
Register 119 (0x77): User Defined Register 2
Bit Name
7-0 UDR2 R/W
Default
0x00
Default
0x00
Register 120 (0x78): User Defined Register 3
Bit Name
7-0 UDR3 R/W
Default
0x00
Registers 121 to 131
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC address table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Bit Name
7-5 Reserved
4
3-2
Read High /
Write Low
Table Select
Do not change the default values.
R/W = 1, read cycle
= 0, write cycle
R/W 00 = static MAC address table selected
01 = VLAN table selected
10 = dynamic MAC address table selected
11 = MIB counter selected
R/W Bits [9:8] of indirect address 1-0 Indirect
Address High
Register 122 (0x7A): Indirect Access Control 1
Bit Name
7-0 Indirect
Address Low
R/W Bits [7:0] of indirect address
Note:
A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.
Register 123 (0x7B): Indirect Data Register 8
Bit Name
7
CPU Read
Status
6-3 Reserved
2-0 Indirect Data
[66:64]
RO
This bit is applicable only for dynamic MAC address table and MIB counter reads.
= 1, read is still in progress
= 0, read has completed
RO Reserved
RO Bits [66:64] of indirect data
Default
000
0
00
00
Default
0000_0000
Default
0
0000
000
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Register 124 (0x7C): Indirect Data Register 7
Bit Name
7-0
Indirect Data
[63:56]
R/W Bits [63:56] of indirect data
Register 125 (0x7D): Indirect Data Register 6
Bit Name
7-0 Indirect Data
[55:48]
R/W Bits [55:48] of indirect data
Register 126 (0x7E): Indirect Data Register 5
Bit Name
7-0 Indirect Data
[47:40]
R/W Bits [47:40] of indirect data
Register 127 (0x7F): Indirect Data Register 4
Bit Name
7-0 Indirect Data
[39:32]
R/W Bits [39:32] of indirect data
Register 128 (0x80): Indirect Data Register 3
Bit Name
7-0 Indirect Data
[31:24]
R/W Bits [31:24] of indirect data
Register 129 (0x81): Indirect Data Register 2
Bit Name
7-0 Indirect Data
[23:16]
R/W Bits [23:16] of indirect data
Register 130 (0x82): Indirect Data Register 1
Bit Name
7-0 Indirect Data
[15:8]
R/W Bits [15:8] of indirect data
Register 131 (0x83): Indirect Data Register 0
Bit Name
7-0 Indirect Data
[7:0]
R/W Bits [7:0] of indirect data
Register 147~142(0x93~0x8E): Station Address 1 MACA1
Register 153~148 (0x99~0x94): Station Address 2 MACA2
Bit Name
47-0 Station address
R/W 48-bit Station address MACA1 and MACA2.
Note: The station address is used for self MAC address filtering, see the port register control 5 bits [6,5] for detail.
KSZ8863MLL/FLL/RLL
Default
0000_0000
Default
0000_0000
Default
0000_0000
Default
0000_0000
Default
0000_0000
Default
0000_0000
Default
0000_0000
Default
0000_0000
Default
48’h0
Note:
the MSB bits[47-40] of the MAC is the register 147 and 153. The LSB bits[7-0] of
MAC is the register 142 and 148.
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Register 154[6:0] (0x9A): Port 1 Q0 Egress data rate limit
Register 158[6:0] (0x9E): Port 2 Q0 Egress data rate limit
Register 162[6:0] (0xA2): Port 3 Q0 Egress data rate limit
Bit Name
7
6-0
Egress Rate
Limit Flow
Control Enable
Q0 Egress
Data Rate limit
R/W 1: enable egress rate limit flow control.
0: disable
R/W Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped according to the Data Rate Limit Selected Table.
Register 155[6:0] (0x9B): Port 1 Q1 Egress data rate limit
Register 159[6:0] (0x9F): Port 2 Q1 Egress data rate limit
Register 163[6:0] (0xA3): Port 3 Q1 Egress data rate limit
Bit Name
7 Reserved R/W
Do not change the default values.
6-0 Q1 Egress data Rate limit
R/W Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped according to the Data Rate Limit Selected Table.
Register 156[6:0] (0x9C): Port 1 Q2 Egress data rate limit
Register 160[6:0] (0xA0): Port 2 Q2 Egress data rate limit
Register 164[6:0] (0xA4): Port 3 Q2 Egress data rate limit
Bit Name
7 Reserved R/W
Do not change the default values.
6-0 Q2 Egress
Data Rate limit
R/W Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped according to the Data Rate Limit Selected Table.
Register 157[6:0] (0x9D): Port 1 Q3 Egress data rate limit
Register 161[6:0] (0xA1): Port 2 Q3 Egress data rate limit
Register 165[6:0] (0xA5): Port 3 Q3 Egress data rate limit
Bit Name
7 Reserved R/W
Do not change the default values.
6-0 Q3 Egress
Data Rate limit
R/W Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped according to the Data Rate Limit Selected Table.
KSZ8863MLL/FLL/RLL
Default
0
0
Default
0
0
Default
0
0
Default
0
0
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Register 166 (0xA6): KSZ8863 mode indicator
Bit Name
7-0
KSZ8863
Mode Indicator
RO bit7: 1: 2 MII mode bit6: 1: 48P pkg of 2 PHY mode bit5: 1: Port 1 RMII 0: Port 1 MII bit4: 1: Port 3 RMII 0: Port 3 MII bit3: 1: Port 1 MAC MII 0: Port 1 PHY MII bit2: 1: Port 3 MAC MII 0: Port 3 PHY MII bit1: 1: Port 1 Copper 0: Port 1 Fiber bit0: 1: Port 2 Copper 0: Port 2 Fiber
Register 167 (0xA7): High Priority Packet Buffer Reserved for Q3
Bit Name
7-0 Reserved RO Reserved
Do not change the default values.
Register 168 (0xA8): High Priority Packet Buffer Reserved for Q2
Bit Name
7-0 Reserved RO Reserved
Do not change the default values.
Register 169 (0xA9): High Priority Packet Buffer Reserved for Q1
Bit Name
7-0 Reserved RO Reserved
Do not change the default values.
Register 170 (0xAA): High Priority Packet Buffer Reserved for Q0
Bit Name
7-0 Reserved RO Reserved
Do not change the default values.
Register 171 (0xAB): PM Usage Flow Control Select Mode 1
Bit Name
7 Reserved RO
Do not change the default values.
6 Reserved RO
Do not change the default values.
5-0 Reserved RO Reserved
Do not change the default values.
Register 172 (0xAC): PM Usage Flow Control Select Mode 2
Bit Name
7-6 Reserved
5-0 Reserved
RO Reserved
Do not change the default values.
RO Reserved
Do not change the default values.
September 2011 75
KSZ8863MLL/FLL/RLL
Default
0x03 MLL
0x13 RLL
0x01 FLL
Default
0x45
Default
0x35
Default
0x25
Default
0x15
Default
0
1
0x18
Default
0
0x10
M9999-092111-1.4
Micrel, Inc.
Register 173 (0xAD): PM Usage Flow Control Select Mode 3
Bit Name
7-6 Reserved
5-0 Reserved
RO Reserved
Do not change the default values.
RO Reserved
Do not change the default values.
Register 174 (0xAE): PM Usage Flow Control Select Mode 4
Bit Name
7-4 Reserved
3-0 Reserved
RO Reserved
Do not change the default values.
RO Reserved
Do not change the default values.
Register 175 (0xAF): TXQ Split for Q3 in Port 1
Bit Name
6:0 Reserved and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 176/177/178 bits[7]=1.
RO Reserved
Do not change the default values.
Register 176 (0xB0): TXQ Split for Q2 in Port 1
Bit Name
6:0 Reserved and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 175/177/178 bits[7]=1.
RO Reserved
Do not change the default values.
Register 177 (0xB1): TXQ Split for Q1 in Port 1
Bit Name
6:0 Reserved and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 175/176/178 bits[7]=1.
RO Reserved
Do not change the default values.
Register 178 (0xB2): TXQ Split for Q0 in Port 1
Bit Name
0 = enable straight priority with Reg 175/176/177 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 175/176/177 bits[7]=1.
6:0 Reserved RO Reserved
Do not change the default values.
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KSZ8863MLL/FLL/RLL
8
Default
1
4
Default
1
Default
00
0x08
Default
0
0x05
Default
1
2
Default
1
1
M9999-092111-1.4
Micrel, Inc.
Register 179 (0xB3): TXQ Split for Q3 in Port 2
Bit Name
0 = enable straight priority with Reg 180/181/182 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 180/181/182 bits[7]=1.
6:0 Reserved RO Reserved
Do not change the default values.
Register 180 (0xB4): TXQ Split for Q2 in Port 2
Bit Name
0 = enable straight priority with Reg 179/181/182 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 179/181/182 bits[7]=1.
6:0 Reserved RO Reserved
Do not change the default values.
Register 181 (0xB5): TXQ Split for Q1 in Port 2
Bit Name
0 = enable straight priority with Reg 179/180/182 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 179/180/182 bits[7]=1.
6:0 Reserved RO Reserved
Do not change the default values.
Register 182 (0xB6): TXQ Split for Q0 in Port 2
Bit Name
0 = enable straight priority with Reg 179/180/181 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 179/180/181 bits[7]=1.
6:0 Reserved RO Reserved
Do not change the default values.
Register 183 (0xB7): TXQ Split for Q3 Port 3
Bit Name
0 = enable straight priority with Reg 184/185/186 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 184/185/186 bits[7]=1.
6:0 Reserved RO Reserved
Do not change the default values.
Register 184 (0xB8): TXQ Split for Q2 Port 3
Bit Name
0 = enable straight priority with Reg 183/185/186 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
6:0 Reserved
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 183/185/186 bits[7]=1.
RO Reserved
September 2011 77
KSZ8863MLL/FLL/RLL
Default
1
2
Default
1
1
Default
1
8
Default
1
4
Default
1
8
Default
1
4
M9999-092111-1.4
Micrel, Inc.
Do not change the default values.
Register 185 (0xB9): TXQ Split for Q1 in Port 3
Bit Name
Select R/W and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 183/184/186 bits[7]=1.
6:0 Reserved RO Reserved
Do not change the default values.
Register 186 (0xBA): TXQ Split for Q0 in Port 3
Bit Name
6:0 Reserved and Reg 5 bit[3]=0 for higher priority first
1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 183/184/185 bits[7]=1.
RO Reserved
Do not change the default values.
Register 187 (0xBB): Interrupt enable register
Bit Name
7-0 Interrupt
Enable
Register
R/W Interrupt enable register corresponding to bits in Register
188
Note:
Set register 187 first and then set register 188 (W1C=
Write ‘1’ Clear) to wait the interrupt at pin 35 INTRN for the link to be changed.
Register 188 (0xBC): Link Change Interrupt
Bit Name
7 P1 or P2 Link
Change (LC)
Interrupt
R/W Set to 1 when P1 or P2 link changes in analog interface
(W1C).
6-3 Reserved
2
Do not change the default values.
R/W Set to 1 when P3 link changes in MII interface (W1C).
1
0
P3 Link
Change (LC)
Interrupt
P2 Link
Change (LC)
Interrupt
P1 MII Link
Change (LC)
Interrupt
R/W Set to 1 when P2 link changes in analog interface (W1C).
R/W Set to 1 when P1 link changes in analog interface or MII interface (W1C).
Register 189 (0xBD): Force Pause Off Iteration Limit Enable
Bit Name
7-0 Force Pause
Off Iteration
Limit Enable
R/W =1, Enable,It is 160ms before requesting to invalidate flow control.
=0, Disable
KSZ8863MLL/FLL/RLL
Default
1
2
Default
1
1
Default
0x00
Default
0
0
0
0
0
Default
0
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Register 192 (0xC0): Fiber Signal Threshold
Bit Name R/W
7 Port 2 Fiber
Signal
Threshold
R/W =1, Threshold is 2.0V
=0, Threshold is 1.2V
6 Port 1 Fiber
Signal
Threshold
R/W =1, Threshold is 2.0V
=0, Threshold is 1.2V
Do not change the default value.
Register 193 (0xC1): Internal 1.8V LDO Control
Bit Name R/W
6 Internal 1.8V
LDO Disable
Reserved
Do not change the default value.
R/W
=1, Disable internal 1.8V LDO
=0, Enable internal 1.8V LDO
5-0
Do not change the default value.
KSZ8863MLL/FLL/RLL
Default
0
0
0
Default
0
0
0
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Register 194 (0xC2): Insert SRC PVID
Bit Name
7-6
5
4
3
2
1
0
Insert SRC port 1 PVID at
Port 2
Insert SRC port 1 PVID at
Port 3
Insert SRC port 2 PVID at
Port 1
Insert SRC port 2 PVID at
Port 3
Insert SRC port 3 PVID at
Port 1
Insert SRC port 3 PVID at
Port 2
R/W
R/W
R/W
R/W
R/W
R/W
Do not change the default value.
1= insert SRC port 1 PVID for untagged frame at egress port 2
1= insert SRC port 1 PVID for untagged frame at egress port 3
1= insert SRC port 2 PVID for untagged frame at egress port 1
1= insert SRC port 2 PVID for untagged frame at egress port 3
1= insert SRC port 3 PVID for untagged frame at egress port 1
1= insert SRC port 3 PVID for untagged frame at egress port 2
Register 195 (0xC3): Power Management and LED Mode
Bit Name
7
6
5-4
3
2
CPU interface
Power Down
Switch Power
Down
R/W CPU interface clock tree power down enable.
1: Enable
0: Disable
Note: Power save a little bit when MII interface is used and the traffic is stopped in the power management with normal mode
R/W Switch clock tree power down enable.
1: Enable
0:Disable
LED Mode
Selection
Note: Power save a little bit when MII interface is used and the traffic is stopped in the power management with normal mode
R/W 00: LED0 -> Link/ACT, LED1-> Speed
01: LED0 -> Link, LED1 -> ACT
10: LED0 -> Link/ACT, LED1 -> Duplex
LED output mode
11: LED0 -> Link, LED1 -> Duplex
R/W =1, the internal stretched energy signal from the analog module will be negated and output to LED1 and the internal device ready signal will be negated and output to LED0.
=0, the LED1/LED0 pins will indicate the regular LED outputs.
(Note. This is for debugging purpose.)
PLL Off Enable R/W =1, PLL power down enable
=0, disable
Note: This bit is used in Energy Detect mode with pin 27
MII_LINK_3 pull-up in the by-pass mode for saving power
September 2011 80
00
0
0
0
0
0
0
KSZ8863MLL/FLL/RLL
Default
Default
0
0
00
0
0
M9999-092111-1.4
Micrel, Inc.
Bit Name
1-0 Power
Management
Mode
R/W Power management mode
00: Normal Mode
01: Energy Detection Mode
10: Software Power Down Mode
11: Power Saving Mode
Register 196(0xC4): Sleep Mode
Bit Name
This value is used to control the minimum period the no energy event has to be detected consecutively before the device enters the low power state when the ED mode is on.
The unit is 20 ms. The default go_sleep time is 1.6 seconds.
Register 198 (0xC6): Forward Invalid VID Frame and Host Mode
Bit Name
7 Reserved RO
6-4 Forward Invid
VID Frame
Do not change the default value.
R/W Forwarding ports for frame with invalid VID
3 P3 RMII Clock
Selection
0: External
2 P1 RMII Clock
Selection
0: External
1-0 Host Interface
Mode
R/W 00: I2C master mode
01: I2C slave mode
10: SPI slave mode
11: SMI mode
KSZ8863MLL/FLL/RLL
Default
00
Default
0x50
Default
0
3b’0
0
0
Strapped value of P2LED1,
P2LED0.
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Static MAC Address Table
The KSZ8863 supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, the KSZ8863 searches both tables to make a packet forwarding decision. In response to a Source Address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes.
The static DA look up result takes precedence over the dynamic DA look up result. If there is a DA match in both tables, the result from the static table is used. The entries in the static table will not be aged out by the KSZ8863.
The static table is accessed by a external processor via the SMI, SPI or I2C interfaces. The external processor performs all addition, modification and deletion of static MAC table entries.
57-54
53
FID
Use FID
R/W Filter VLAN ID – identifies one of the 16 active VLANs
R/W = 1, use (FID+MAC) for static table look ups
= 0, use MAC only for static table look ups
Default
0000
0
0
“receive enable=0” setting
= 0, no override
51 Valid R/W = 1, this entry is valid, the lookup result will be used
= 0, this entry is not valid
50-48 Forwarding
Ports
R/W These 3 bits control the forwarding port(s):
001, forward to port 1
010, forward to port 2
100, forward to port 3
011, forward to port 1 and port 2
110, forward to port 2 and port 3
101, forward to port 1 and port 3
111, broadcasting (excluding the port)
47-0 MAC Address R/W 48-bit MAC Address
0
000
0x0000_0000_000
0
Table 15. Format of Static MAC Table (8 Entries)
Examples:
1. Static Address Table Read (Read the 2 nd
Entry)
Write to reg. 121 (0x79) with 0x10
Write to reg. 122 (0x7A) with 0x01
Then,
Read reg. 124 (0x7C), static table bits [57:56]
Read reg. 125 (0x7D), static table bits [55:48]
Read reg. 126 (0x7E), static table bits [47:40]
Read reg. 127 (0x7F), static table bits [39:32]
Read reg. 128 (0x80), static table bits [31:24]
Read reg. 129 (0x81), static table bits [23:16]
Read reg. 130 (0x82), static table bits [15:8]
Read reg. 131 (0x83), static table bits [7:0]
// Read static table selected
// Trigger the read operation
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2. Static Address Table Write (Write the 8 th
Entry)
Write to reg. 124 (0x7C), static table bits [57:56]
Write to reg. 125 (0x7D), static table bits [55:48]
Write to reg. 126 (0x7E), static table bits [47:40]
Write to reg. 127 (0x7F), static table bits [39:32]
Write to reg. 128 (0x80), static table bits [31:24]
Write to reg. 129 (0x81), static table bits [23:16]
Write to reg. 130 (0x82), static table bits [15:8]
Write to reg. 131 (0x83), static table bits [7:0]
Write to reg. 121 (0x79) with 0x00
Write to reg. 122 (0x7A) with 0x07
// Write static table selected
// Trigger the write operation
KSZ8863MLL/FLL/RLL
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VLAN Table
The KSZ8863 uses the VLAN table to perform look ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID
(filter ID), VID (VLAN ID), and VLAN membership as described in the following table.
Bit Name R/W
19 Valid R/W = 1, entry is valid
= 0, entry is invalid
Default
1
111 a DA lookup fails (no match in both static and dynamic tables), the packet associated with this
VLAN will be forwarded to ports specified in this field. For example, 101 means port 3 and 1 are in this VLAN.
15-12 FID 0x0
11-0 VID represented by these four bit fields. FID is the mapped ID. If 802.1Q VLAN is enabled, the look up will be based on FID+DA and FID+SA.
R/W IEEE 802.1Q 12 bits VLAN ID 0x001
Table 16. Format of Static VLAN Table (16 Entries)
If 802.1Q VLAN mode is enabled, KSZ8863 will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null
VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place. If the VID is valid, the FID is retrieved. The FID+DA and
FID+SA lookups are performed. The FID+DA look up determines the forwarding ports. If FID+DA fails, the packet will be broadcast to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned.
Examples:
1. VLAN Table Read (read the 3 rd
entry)
Write to reg. 121 (0x79) with 0x14
Write to reg. 122 (0x7A) with 0x02
Then,
Read reg. 129 (0x81), VLAN table bits [19:16]
Read reg. 130 (0x82), VLAN table bits [15:8]
// Read VLAN table selected
// Trigger the read operation
Read reg. 131 (0x83), VLAN table bits [7:0]
2. VLAN Table Write (write the 7 th
entry)
Write to reg. 129 (0x81), VLAN table bits [19:16]
Write to reg. 130 (0x82), VLAN table bits [15:8]
Write to reg. 131 (0x83), VLAN table bits [7:0]
Write to reg. 121 (0x79) with 0x04
Write to reg. 122 (0x7A) with 0x06
// Write VLAN table selected
// Trigger the write operation
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Dynamic MAC Address Table
The KSZ8863 maintains the dynamic MAC address table. Read access is allowed only.
Bit Name
71 Data Not
Ready
70-67
66
65-56
55-54
53-52
Reserved
MAC Empty
No of Valid
Entries
Time Stamp
Source Port
RO = 1, entry is not ready, continue retrying until this bit is set to 0
= 0, entry is ready
RO Reserved
RO = 1, there is no valid entry in the table
= 0, there are valid entries in the table
RO Indicates how many valid entries in the table
0x3ff means 1K entries
0x001 means 2 entries
0x000 and bit 66 = 0 means 1 entry
0x000 and bit 66 = 1 means 0 entry
RO 2 bits counter for internal aging
RO The source port where FID+MAC is learned
00 : port 1
01 : port 2
10 : port 3
51-48 FID
47-0 MAC Address RO 48-bit MAC Address
Table 17. Format of Dynamic MAC Address Table (1K Entries)
KSZ8863MLL/FLL/RLL
Default
1
00_0000_0000
0x0
0x0000_0000_0000
Example:
Dynamic MAC Address Table Read (read the 1 st
entry and retrieve the MAC table size)
Write to reg. 121 (0x79) with 0x18
Write to reg. 122 (0x7A) with 0x00
// Read dynamic table selected
// Trigger the read operation
Then,
Read reg. 123 (0x7B), bit [7] dynamic table bits [66:64]
// if bit 7 = 1, restart (reread) from this register
Read reg. 124 (0x7C), dynamic table bits [63:56]
Read reg. 125 (0x7D), dynamic table bits [55:48]
Read reg. 126 (0x7E), dynamic table bits [47:40]
Read reg. 127 (0x7F), dynamic table bits [39:32]
Read reg. 128 (0x80), dynamic table bits [31:24]
Read reg. 129 (0x81), dynamic table bits [23:16]
Read reg. 130 (0x82), dynamic table bits [15:8]
Read reg. 131 (0x83), dynamic table bits [7:0]
00
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MIB (Management Information Base) Counters
The KSZ8863 provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.”
Bit Name
31 Overflow
Default
0
30
29-0
Count valid
Counter values
RO = 1, counter overflow
= 0, no counter overflow
RO = 1, counter value is valid
= 0, counter value is not valid
RO Counter value
0
0
Table 18. Format of “Per Port” MIB Counters
“Per Port” MIB counters are read using indirect memory access. The base address offsets and address ranges for all three ports are:
Port 1, base is 0x00 and range is (0x00-0x1f)
Port 2, base is 0x20 and range is (0x20-0x3f)
Port 3, base is 0x40 and range is (0x40-0x5f)
Port 1 MIB counters are read using the indirect memory offsets in the following table.
0x0
0x1
0x2
0x3
RxLoPriorityByte
RxHiPriorityByte
RxUndersizePkt
RxFragments
0x4 RxOversize
0x5 RxJabbers
Description
Rx lo-priority (default) octet count including bad packets
Rx hi-priority octet count including bad packets
Rx undersize packets w/ good CRC
Rx fragment packets w/ bad CRC, symbol errors or alignment errors
0x6 RxSymbolError
0x7 RxCRCError
Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes)
Rx packets longer than 1522 bytes w/ either CRC errors, alignment errors, or symbol errors
(depends on max packet size setting)
Rx packets w/ invalid data symbol and legal packet size.
Rx packets within (64,1522) bytes w/ an integral number of bytes and a bad CRC (upper limit depends on max packet size setting)
0x8 RxAlignmentError Rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC (upper limit depends on max packet size setting)
0x9 RxControl8808Pkts
0xA RxPausePkts
Number of MAC control frames received by a port with 88-08h in EtherType field
Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-
08h), DA, control opcode (00-01), data length (64B min), and a valid CRC
0xB RxBroadcast
0xC RxMulticast
0xD
0xE
0xF
RxUnicast
Rx64Octets
Rx65to127Octets
Rx good broadcast packets (not including error broadcast packets or valid multicast packets)
Rx good multicast packets (not including MAC control frames, error multicast packets or valid broadcast packets)
Rx good unicast packets
Total Rx packets (bad packets included) that were 64 octets in length
Total Rx packets (bad packets included) that are between 65 and 127 octets in length
0x10 Rx128to255Octets
0x11 Rx256to511Octets
Total Rx packets (bad packets included) that are between 128 and 255 octets in length
Total Rx packets (bad packets included) that are between 256 and 511 octets in length
0x12 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length
0x13 Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting)
0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets
0x15 TxHiPriorityByte Tx hi-priority good octet count, including PAUSE packets
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0x16 TxLateCollision
0x17
0x18
0x19
0x1A
TxPausePkts
TxBroadcastPkts
TxMulticastPkts
TxUnicastPkts
Description
The number of times a collision is detected later than 512 bit-times into the Tx of a packet
Number of PAUSE frames transmitted by a port
Tx good broadcast packets (not including error broadcast or valid multicast packets)
Tx good multicast packets (not including error multicast packets or valid broadcast packets)
Tx good unicast packets
0x1B TxDeferred
0x1C TxTotalCollision
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
Tx total collision, half duplex only
0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions
0x1E TxSingleCollision
0x1F TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision
Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets
Bit Name
30-16 Reserved N/A
15-0 Counter Value RO Counter Value
Table 20. Format of “All Port Dropped Packet” MIB Counters
Default
N/A
0
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“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters are shown in the following table:
0x100
0x101
0x102
0x103
0x104
0x105
Port1 TX Drop Packets
Port2 TX Drop Packets
Port3 TX Drop Packets
Port1 RX Drop Packets
Port2 RX Drop Packets
Port3 RX Drop Packets
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
Table 21. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets
Examples:
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c
Write to reg. 122 (0x7A) with 0x0e
Then
// Read MIB counters selected
// Trigger the read operation
Read reg. 128 (0x80), overflow bit [31] // If bit 31 = 1, there was a counter overflow valid bit [30] // If bit 30 = 0, restart (reread) from this register counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c // Read MIB counter selected
Write to reg. 122 (0x7A) with 0x2e
Then,
// Trigger the read operation
Read reg. 128 (0x80), overflow bit [31] // If bit 31 = 1, there was a counter overflow valid bit [30] // If bit 30 = 0, restart (reread) from this register counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Write to reg. 121 (0x79) with 0x1d // Read MIB counter selected
Write to reg. 122 (0x7A) with 0x00
Then
// Trigger the read operation
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Additional MIB Counter Information
“Per Port” MIB counters are designed as “read clear.” These counters will be cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or validity; therefore, the application must keep track of overflow and valid conditions.
To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are 160 registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.
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Absolute Maximum Ratings
(1)
Supply Voltage
VDDC) ................................. –0.5V to 2.4V
(VDDA_3.3V, VDDIO).............................. –0.5V to 4.0V
Input Voltage ................................................. –0.5V to 4.0V
Output Voltage .............................................. –0.5V to 4.0V
Lead Temperature (soldering, 10sec.)....................... 260°C
Storage Temperature (T s
) ..........................–55°C to 150°C
HBM ESD Rating .......................................................... 4KV
Electrical Characteristics
(4)
Operating Ratings
(2)
KSZ8863MLL/FLL/RLL
Supply Voltage
VDDC)............................1.690V to 1.890V
(VDDA_3.3) ............................................2.5V to 3.465V
(VDDIO) ................................................1.71V to 3.465V
Ambient Temperature (T
A
)
Commercial....................................................... 0°C to 70°C
Industrial................................................. –40°C to 85°C
Junction Temperature (T
J
) ......................................... 125°C
Junction Thermal Resistance
(3)
(
θ
JA
JC
) .................................................... 69.64°C/W
) ......................................................... 15°C/W
Current consumption is for the single 3.3V supply device only, and includes the 1.8V supply voltages (VDDA, VDDC) that are provided via power output pin 42(VDDCO).
Each PHY port’s transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V for 10BASE-T at fully traffic.
Symbol Parameter Condition Min Typ Max Units
I
100BASE-TX Operation (All Ports @ 100% Utilization)
ddxio
100BASE-TX
(analog core + digital core + transceiver + digital I/O)
V
DDA
_3.3, V
DDIO
= 3.3V
Core power is provided from the internal 1.8V
LDO with input voltage VDDIO
10BASE-T Operation (All Ports @ 100% Utilization)
I ddxio
10BASE-T
(analog core + digital core + transceiver + digital I/O)
V
DDA
_3.3, V
DDIO
= 3.3V
Core power is provided from the internal 1.8V
LDO with input voltage VDDIO
Power Management Mode
I dd3
Mode
I dd4
I dd5
Soft Power Down Mode
Energy Detect Mode
V
DDA
_3.3, V
DDIO
= 3.3V
Unplug Port 1 and Port 2
Set Register 195 bit[1,0] = [1,1]
V
DDA
_3.3, V
DDIO
= 3.3V
Set Register 195 bit[1,0] = [1,0]
V
DDA
_3.3, V
DDIO
= 3.3V
Unplug Port 1 and Port 2
Set Register 195 bit[7,0] = 0x05 with port 3
PHY mode and by-pass mode.
TTL Inputs (VDD_IO = 3.3V/2.5V/1.8V)
V
IH
Input High Voltage
V
IL
Input Low Voltage
114 mA
85 mA
96 mA
8 mA
16 mA
2.0/2.
0/1.3
-10
V
0.8/0.
6/0.3
10
V
µA I
IN
Input
TTL Outputs (VDD_IO = 3.3V/2.5V/1.8V)
V
OH
Output High Voltage
V
IN
= GND ~ VDD_IO
I
OH
= -8mA
V
OL
Output Low Voltage
I
OL
= 8mA
2.4/1.
9/1.5
V
0.4/0.
4/0.2
V
10 µA |I
OZ
| Output Tri-State Leakage
100BASE-TX Transmit (measured differentially after 1:1 transformer)
V
O
V
IMB
Peak Differential Output Voltage
Output Voltage Imbalance
100Ω termination across differential output
100Ω termination across differential output
0.95 1.05
2
V
%
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Electrical Characteristics
(4)
(Continued)
Symbol Parameter
T r
/T f
Rise/Fall Time Imbalance
Duty Cycle Distortion
Overshoot
Condition
Peak-to-peak
10BASE-T Receive
V
SQ
Squelch Threshold 5MHz square wave
10BASE-T Transmit (measured differentially after 1:1 transformer)
V
P
Peak Differential Output Voltage 100Ω termination across differential output
Peak-to-peak
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. No (HS) heat spreader in this package.
4. T
A
= 25°C. Specification for packaged product only.
KSZ8863MLL/FLL/RLL
Min Typ Max Units
3 5 ns
0 0.5
±0.5 ns ns
400
2.4 mV
V
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Timing Specifications
EEPROM Timing
KSZ8863MLL/FLL/RLL
Figure 16. EEPROM Interface Input Timing Diagram
Figure 17. EEPROM Interface Output Timing Diagram
t cyc1 t s1
Setup t h1
Hold t ov1
Output
Table 22. EEPROM Timing Parameters
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MII Timing
KSZ8863MLL/FLL/RLL
Figure 18. MAC Mode MII Timing – Data Received from MII
t
CYC3 t
S3 t
H3 t
OV3
September 2011
Figure 19. MAC Mode MII Timing – Data Transmitted to MII
10Base-T/100Base-TX
Clock Cycle
Set-Up Time
Hold Time
Output Valid
Table 23. MAC Mode MII Timing Parameters
2
7
4
400/40
11 16 ns ns ns ns
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MII Timing (Continued)
KSZ8863MLL/FLL/RLL
Figure 20. PHY Mode MII Timing – Data Received from MII
t
CYC4 t
S4 t
H4 t
OV4
Figure 21. PHY Mode MII Timing – Data Transmitted to MII
10BaseT/100BaseT
Clock Cycle
Set-Up Time
Hold Time
Output Valid
Table 24. PHY Mode MII Timing Parameters
10
0
18
400/40
19 ns ns ns ns
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RMII Timing
KSZ8863MLL/FLL/RLL
Figure 22. RMII Timing – Data Received from RMII
September 2011
Figure 23. RMII Timing – Data Transmitted to RMII
Table 25. RMII Timing Parameters
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I
2
C Slave Mode Timing
KSZ8863MLL/FLL/RLL
September 2011
Figure 24. I2C Input Timing
Figure 25. I2C Start Bit Timing
Figure 26. I2C Stop Bit Timing
Figure 27. I2C Output Timing
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I
2
C Slave Mode Timing (Continued)
KSZ8863MLL/FLL/RLL t
CYC
Clock t
S t
H t
TBS t
TBH
Start bit setup time
Start bit hold time
33
33 t
SBS t
SBH t
OV
Stop bit setup time
Stop bit hold time
2
33
Table 26. I2C Timing Parameters
Note:
Data is only allowed to change during SCL low time except start and stop bits. ns ns ns ns
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SPI Timing
KSZ8863MLL/FLL/RLL
Figure 28. SPI Input Timing
t t
Symbols Parameters Units
f
C t
CHSL t
SLCH t
CHSH
SPISN inactive hold time
SPISN active setup time
90
90 ns ns
SHCH t
SHSL t
DVCH t
CHDX
SPISN active old time
SPISN inactive setup time
SPISN deselect time
Data input setup time
Data input hold time
90
90
100
20
30 ns ns ns ns ns
CLCH t
CHCL t
DLDH t
DHDL
Clock rise time
Clock fall time
Data input rise time
Data input fall time
1
1
1
1 us us us us
Table 27. SPI Input Timing Parameters
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SPI Timing (Continued)
KSZ8863MLL/FLL/RLL
Figure 29. SPI Output Timing
Symbols Parameters Units
t f
C
Clock
CLQX t
CLQV t
CH t
CL t
QLQH t
QHQL t
SHQZ
SPIQ hold time
Clock low to SPIQ valid
Clock high time
Clock low time
SPIQ rise time
SPIQ fall time
SPIQ disable time
0
90
90
0
60
50
50
100 ns ns ns ns ns ns
Table 28. SPI Output Timing Parameters
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Auto-Negotiation Timing
KSZ8863MLL/FLL/RLL tBTB tPW tCTD tCTC
September 2011
Figure 30. Auto-Negotiation Timing
FLP burst to FLP burst 8 16 24 ms width ms
Clock/Data pulse width 100 ns
Clock pulse to Data pulse
Clock pulse to Clock pulse
Number of Clock/Data pulse per burst
55.5
111
64
128
69.5
139
µs
µs
17 33
Table 29. Auto-Negotiation Timing Parameters
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MDC/MDIO Timing
KSZ8863MLL/FLL/RLL
Figure 31. MDC/MDIO Timing
Timing Parameter Description Min Typ Max Unit
t
P
MDC t
1MD1 t
MD2 t
MD3
MDIO (PHY input) setup to rising edge of MDC
MDIO (PHY input) hold from rising edge of MDC
MDIO (PHY output) delay from rising edge of MDC
10
4
222 ns ns ns
Table 30. MDC/MDIO Timing Parameters
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Reset Timing
The KSZ8863MLL/FLL/RLL reset timing requirement is summarized in the following figure and table.
Figure 32. Reset Timing
t t
Symbols Parameters Units
sr
Stable supply voltages to reset High 10 ms cs t ch t rc tvr
Configuration setup time
Configuration hold time
Reset to strap-in pin output
3.3V rise time
50
50
50 ns ns us
100 us
Table 31. Reset Timing Parameters
After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on the managed interface (I2C slave, SPI slave, SMI, MIIM).
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Reset Circuit
power supply.
Figure 33. Recommended Reset Circuit
etc),. At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8863MLL/FLL/RLL device.
The RST_OUT_n from CPU/FPGA provides the warm reset after power up.
September 2011
Figure 34. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output
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Selection of Isolation Transformers
An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements.
The following table gives recommended transformer characteristics.
Turns ratio
Open-circuit inductance (min.)
Leakage inductance (max.)
Inter-winding capacitance (max.)
D.C. resistance (max.)
Insertion loss (max.)
HIPOT (min.)
1 CT : 1 CT
350
μH
0.4
μH
12pF
0.9
Ω
1.0dB
1500Vrms
Table 32. Transformer Selection Criteria
100mV, 100kHz, 8mA
1MHz (min.)
0MHz – 65MHz
Magnetic Manufacturer
Bel Fuse
Bel Fuse (MagJack)
Bel Fuse (MagJack)
Part Number
S558-5999-U7
SI-46001
SI-50170
Auto MDI-X
Yes
Yes
Yes
Number of Port
1
1
1
Pulse (low cost) H1260 Yes 1
1 TDK (Mag Jack) TLA-6T718
Table 33. Qualified Single Port Magnetics
Selection of Reference Crystal
Frequency tolerance (max)
Load capacitance (max)
Series resistance
Yes
±50
20
40
Table 34. Typical Reference Crystal Characteristics
ppm pF
Ω
September 2011 103 M9999-092111-1.4
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Package Information
KSZ8863MLL/FLL/RLL
Figure 35. 48-Pin LQFP (LQ)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2011 Micrel, Incorporated.
September 2011 104 M9999-092111-1.4
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