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PIC16F716
Data Sheet
8-bit Flash-based Microcontroller
with A/D Converter and
Enhanced Capture/Compare/PWM
 2003 Microchip Technology Inc.
Preliminary
DS41206A
Note the following details of the code protection feature on Microchip devices:
•
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•
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•
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•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Information contained in this publication regarding device
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS41206A-page ii
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
8-bit Flash-based Microcontroller with A/D Controller and
Enhanced Capture/Compare PWM
Microcontroller Core Features:
Low-Power Features:
• High-performance RISC CPU
• Only 35 single-word instructions to learn
- All single-cycle instructions except for
program branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Interrupt capability
(up to 7 internal/external interrupt sources)
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Standby Current:
- 100 nA @ 2.0V, typical
• Operating Current:
- 14 µA @ 32 kHz, 2.0V, typical
- 120 µA @ 1 MHz, 2.0V, typical
• Watchdog Timer Circuit:
- 1 µA @ 2.0V, typical
• Timer1 Oscillator Current:
- 3.0 µA @ 32 kHz, 2.0V, typical
Peripheral Features:
Special Microcontroller Features
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler
can be incremented during Sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Enhanced Capture, Compare, PWM module:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM maximum resolution is 10-bit
- Enhanced PWM:
- Single, Half-Bridge and Full-Bridge modes
- Digitally programmable dead-band delay
- Auto-shutdown/restart
• 8-bit multi-channel Analog-to-Digital converter
• 13 I/O pins with individual direction control
• Programmable weak pull-ups on PORTB
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Dual level Brown-out Reset circuitry
- 2.5 VBOR (Typical)
- 4.0 VBOR (Typical)
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options
• Fully static design
• In-Circuit Serial Programming (ICSP™)
CMOS Technology
• Wide operating voltage range:
- Industrial: 2.0V to 5.5V
- Extended: 3.0V to 5.5V
• High Sink/Source Current 25/25 mA
• Wide temperature range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Memory
Device
PIC16F716
Flash
Data
2048 x 14
128 x 8
 2003 Microchip Technology Inc.
I/O
8-bit A/D
(ch)
Timers 8/16
PWM
(outputs)
VDD Range
13
4
2/1
1/2/4
2.0V - 5.5V
Preliminary
DS41206A-page 1
PIC16F716
Pin Diagrams
18-pin PDIP, SOIC
1
2
3
4
5
6
7
8
9
PIC16F716
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
MCLR/VPP
VSS
RB0/INT/ECCPAS2
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1/P1A
18
17
16
15
14
13
12
11
10
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7/P1D
RB6/P1C
RB5/P1B
RB4/ECCPAS0
20
19
18
17
16
15
14
13
12
11
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7/P1D
RB6/P1C
RB5/P1B
RB4/ECCPAS0
20-pin SSOP
DS41206A-page 2
1
2
3
4
5
6
7
8
9
10
PIC16F716
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
MCLR/VPP
VSS
VSS
RB0/INT/ECCPAS2
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1/P1A
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization ................................................................................................................................................................... 7
3.0 I/O Ports ..................................................................................................................................................................................... 19
4.0 Timer0 Module ........................................................................................................................................................................... 27
5.0 Timer1 Module ........................................................................................................................................................................... 29
6.0 Timer2 Module ........................................................................................................................................................................... 31
7.0 Enhanced Capture/Compare/PWM (ECCP) Module.................................................................................................................. 33
8.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 49
9.0 Special Features of the CPU...................................................................................................................................................... 55
10.0 Instruction Set Summary ............................................................................................................................................................ 71
11.0 Development Support................................................................................................................................................................. 85
12.0 Electrical Characteristics ............................................................................................................................................................ 91
13.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 107
14.0 Packaging Information.............................................................................................................................................................. 109
Appendix A: Revision History............................................................................................................................................................. 113
Appendix B: Conversion Considerations ........................................................................................................................................... 113
Appendix C: Migration from Base-line to MID-RANGE Devices ........................................................................................................ 114
On-Line Support................................................................................................................................................................................. 115
Systems Information and Upgrade Hot Line ...................................................................................................................................... 115
Reader Response .............................................................................................................................................................................. 116
Index .................................................................................................................................................................................................. 117
Product Identification System ............................................................................................................................................................ 123
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Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 3
PIC16F716
NOTES:
DS41206A-page 4
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
1.0
DEVICE OVERVIEW
This document contains device specific information for
the PIC16F716. Additional information may be found in
the PICmicro® Mid-Range Reference Manual,
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site (www.microchip.com). The
Reference Manual should be considered a
complementary document to this data sheet, and is
highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
Figure 1-1 is the block diagram for the PIC16F716
device. The pinouts are listed in Table 1-1.
FIGURE 1-1:
PIC16F716 BLOCK DIAGRAM
13
Flash
2K x 14
Program
Memory
Program
Bus
8
Data Bus
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RAM
128 x 8
File
Registers
8 Level Stack
(13-bit)
14
RAM Addr(1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
Status reg
8
3
OSC1/CLKIN
Timing
Generation
OSC2/CLKOUT
Oscillator
Start-up Timer
Timer0
ALU
Power-on
Reset
8
Watchdog
Timer
Brown-out
Reset
MCLR
W reg
VDD, VSS
Timer1
Timer2
Enhanced CCP
(ECCP)
Note
1:
RB0/INT/ECCPAS2
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1/P1A
RB4/ECCPAS0
RB5/P1B
RB6/P1C
RB7/P1D
MUX
Power-up
Timer
Instruction
Decode and
Control
PORTA
A/D
Higher order bits are from the Status register.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 5
PIC16F716
TABLE 1-1:
PIC16F716 PINOUT DESCRIPTION
Name
Function
Input Type Output Type
Description
Master clear (Reset) input. This pin is an active low Reset to
the device.
MCLR/VPP
MCLR
VPP
P
—
Programming voltage input
OSC1/CLKIN
OSC1
XTAL
—
Oscillator crystal input
CLKIN
CMOS
—
External clock source input
CLKIN
ST
—
RC Oscillator mode
OSC2
XTAL
—
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
CLKOUT
—
CMOS
In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the
frequency of OSC1, and denotes the instruction cycle rate.
OSC2/CLKOUT
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RB0/INT/ECCPAS2
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1/P1A
RB4/ECCPAS0
ST
—
RA0
TTL
CMOS
AN0
AN
—
RA1
TTL
CMOS
AN1
AN
—
Bidirectional I/O
Analog Channel 0 input
Bidirectional I/O
Analog Channel 1 input
RA2
TTL
CMOS
AN2
AN
—
RA3
TTL
CMOS
AN3
AN
—
Analog Channel 3 input
VREF
AN
—
A/D reference voltage input
RA4
ST
OD
Bidirectional I/O. Open drain when configured as output.
T0CKI
ST
—
RB0
TTL
CMOS
Bidirectional I/O
Analog Channel 2 input
Bidirectional I/O
Timer0 external clock input
Bidirectional I/O. Programmable weak pull-up.
INT
ST
—
External Interrupt
ECCPAS2
ST
—
ECCP Auto-Shutdown pin
RB1
TTL
CMOS
Bidirectional I/O. Programmable weak pull-up.
T1OSO
—
XTAL
Timer1 oscillator output. Connects to crystal in Oscillator
mode.
T1CKI
ST
—
RB2
TTL
CMOS
Timer1 external clock input
T1OSI
XTAL
—
RB3
TTL
CMOS
CCP1
ST
CMOS
Capture1 input, Compare1 output, PWM1 output.
P1A
—
CMOS
PWM P1A output
RB4
TTL
CMOS
Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange.
Bidirectional I/O. Programmable weak pull-up.
Timer1 oscillator input. Connects to crystal in Oscillator mode.
Bidirectional I/O. Programmable weak pull-up.
ECCPAS0
ST
—
RB5/P1B
RB5
TTL
CMOS
Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange.
P1B
—
CMOS
PWM P1B output
RB6/P1C
RB6
TTL
CMOS
Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange. ST input when used as ICSP programming clock.
P1C
—
CMOS
PWM P1C output
RB7
TTL
CMOS
Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange. ST input when used as ICSP programming data.
PWM P1D output
RB7/P1D
ECCP Auto-Shutdown pin
P1D
—
CMOS
VSS
VSS
P
—
Ground reference for logic and I/O pins.
VDD
VDD
P
—
Positive supply for logic and I/O pins.
Legend:
I = Input
O = Output
P = Power
DS41206A-page 6
AN
= Analog input or output
TTL = TTL compatible input
XTAL = Crystal
OD
= Open drain
ST
= Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
2.0
MEMORY ORGANIZATION
2.2
There are two memory blocks in the PIC16F716
PICmicro® microcontroller device. Each block
(program memory and data memory) has its own bus
so that concurrent access can occur.
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 of the Status register are the bank select bits.
Additional information on device memory may be found
in the PICmicro® Mid-Range Reference Manual,
(DS33023).
2.1
Data Memory Organization
RP1:RP0(1)
(status<6:5>)
Bank
00
0
01
1
10
2(2)
11
3(2)
Program Memory Organization
The PIC16F716 has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. The
PIC16F716 has 2K x 14 words of program memory.
Accessing a location above the physically implemented
address will cause a wrap-around.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK OF
PIC16F716
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Note 1:
2:
Maintain Status bit 6 clear to ensure
upward compatibility with future products.
Not implemented
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers
are
General
Purpose
Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. The upper 16
bytes of GPR space and some “high use” Special
Function Registers in Bank 0 are mirrored in Bank 1 for
code reduction and quicker access.
13
Stack Level 1
User Memory
Space
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
07FFh
0800h
1FFFh
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 7
PIC16F716
2.2.1
GENERAL PURPOSE REGISTER
FILE
FIGURE 2-2:
The register file can be accessed either directly or
indirectly through the File Select Register FSR
(Section 2.5 “Indirect Addressing, INDF and FSR
Registers”).
REGISTER FILE MAP
File
Address
File
Address
00h
INDF(1)
INDF(1)
01h
TMR0
02h
PCL
PCL
82h
03h
STATUS
STATUS
83h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
80h
OPTION_REG 81h
07h
87h
08h
88h
89h
09h
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
0Ch
PIR1
PIE1
8Ch
0Eh
TMR1L
PCON
0Fh
TMR1H
8Fh
10h
T1CON
90h
11h
TMR2
12h
T2CON
8Dh
0Dh
8Eh
91h
PR2
92h
93h
13h
14h
94h
15h
CCPR1L
95h
16h
CCPR1H
96h
17h
CCP1CON
97h
18h
PWM1CON
98h
19h
ECCPAS
99h
1Ah
9Ah
1Bh
9Bh
1Ch
9Ch
1Dh
9Dh
9Eh
1Eh
ADRES
1Fh
ADCON0
ADCON1
9Fh
20h
General
Purpose
Registers
General
Purpose
Registers
32 Bytes
A0h
80 Bytes
C0h
6Fh
70h
7Fh
BFh
EFh
16 Bytes
Accesses
70-7Fh
Bank 0
Bank 1
F0h
FFh
Unimplemented data memory locations,
read as '0'.
Note 1:
DS41206A-page 8
Preliminary
Not a physical register.
 2003 Microchip Technology Inc.
PIC16F716
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANK 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
18
00h
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
27
02h
PCL(1)
Program Counter's (PC) Least Significant Byte
0000 0000
17
03h
STATUS(1)
04h
FSR
(1)
05h
PORTA(5,6)
06h
(5,6)
PORTB
07h-09h
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
0Ah
PCLATH(1,2)
0Bh
INTCON(1)
0Ch
PIR1
—
—
—(7)
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
Unimplemented
0001 1xxx
11
xxxx xxxx
18
--xx 0000
19
xxxx xxxx
21
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
17
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
13
—
ADIF
—
—
—
CCP1IF
TMR2IF
TMR1IF
-0-- 0000
15
0Dh
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
29
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
29
10h
T1CON
--00 0000
29
11h
TMR2
0000 0000
31
12h
T2CON
-000 0000
31
13h-14h
—
Unimplemented
—
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Timer2 module’s register
—
TOUTPS3
TOUTPS2 TOUTPS1 TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
Unimplemented
—
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx
34
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx
34
17h
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
33
18h
PWM1CON
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000
46
19h
ECCPAS
—(8)
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
00-0 0000
46
1Ah-1Dh
1Eh
1Fh
ADCON0
Legend:
Note
—
ADRES
1:
2:
3:
4:
5:
6:
7:
8:
ECCPASE ECCPAS2
Unimplemented
—
A/D Result Register
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—(7)
ADON
xxxx xxxx
49
0000 0000
49
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
These registers can be addressed from either bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
The IRP and RP1 bits are reserved. Always maintain these bits clear.
On any device Reset, these pins are configured as inputs.
This is the value that will be in the port output latch.
Reserved bits, do not use.
ECCPAS1 bit is not used on PIC16F716.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 9
PIC16F716
TABLE 2-2:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANK 1
Name
80h
INDF(1)
81h
OPTION_REG
82h
PCL(1)
83h
STATUS(1)
84h
FSR(1)
85h
TRISA
86h
TRISB
87h-89h
—
8Ah
PCLATH(1,2)
8Bh
INTCON(1)
8Ch
PIE1
8Dh
—
8Eh
PCON
8Fh-91h
92h
9Fh
Note
1:
2:
3:
4:
5:
6:
7:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
—(7)
PORTA Data Direction Register
PORTB Data Direction Register
Unimplemented
—
—
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
—
ADIE
—
—
—
CCP1IE
TMR2IE
Write Buffer for the upper 5 bits of the Program Counter
—
—
Unimplemented
—
0000 0000
18
1111 1111
12
0000 0000
17
0001 1xxx
11
xxxx xxxx
18
--11 1111
19
1111 1111
21
17
RBIF
0000 000x
13
TMR1IE
-0-- -000
14
—
—
—
—
—
POR
BOR
---- --qq
16
—
Timer2 Period Register
—
Page
---0 0000
Unimplemented
—
Value on:
POR, BOR
—
—
Unimplemented
ADCON1
Legend:
Bit 6
—
PR2
93h-9Eh
Bit 7
1111 1111
32, 36
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
50
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented,
read as ‘0’.
These registers can be addressed from either bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
The IRP and RP1 bits are reserved. Always maintain these bits clear.
On any device Reset, these pins are configured as inputs.
This is the value that will be in the port output latch.
Reserved bits, do not use.
DS41206A-page 10
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
2.2.2.1
Status Register
The Status register, shown in Register 2-1, contains the
arithmetic status of the ALU, the Reset status and the
bank select bits for data memory.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Status register because these instructions do not affect
the Z, C or DC bits from the Status register. For other
instructions, not affecting any Status bits, see the
“Instruction Set Summary.”
Note 1: The PIC16F716 does not use bits IRP
and RP1 (STATUS<7:6>). Maintain these
bits clear to ensure upward compatibility
with future products.
2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the Status register as
000u u1uu (where u = unchanged).
REGISTER 2-1:
STATUS REGISTER (ADDRESS: 03h, 83h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP(1)
RP1(1)
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)(1)
1 = Bank 2, 3 (100h – 1FFh)
0 = Bank 0, 1 (00h – FFh)
bit 6-5
RP1(1):RP0: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h – FFh)
00 = Bank 0 (00h – 7Fh)
Each bank is 128 bytes
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(2)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
Reserved, maintain clear
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41206A-page 11
PIC16F716
2.2.2.2
OPTION_REG Register
Note:
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single
assignable register known also as the prescaler), the
External INT Interrupt, TMR0 and the weak pull-ups on
PORTB.
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION_REG REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Weak Pull-up Enable bit
1 = PORTB weak pull-ups are disabled
0 = PORTB weak pull-ups are determined by alternate function or TRISBn bit value
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1 : 16
1:8
100
1 : 32
1 : 16
101
1 : 64
1 : 32
110
1 : 128
1 : 64
111
1 : 256
1 : 128
Legend:
DS41206A-page 12
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
PIC16F716
2.2.2.3
INTCON Register
Note:
The INTCON Register is a readable and writable
register which contains various enable and flag bits for
the TMR0 register overflow, RB Port change and
external RB0/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
INTCON REGISTER (ADDRESS: 0Bh, 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41206A-page 13
PIC16F716
2.2.2.4
PIE1 Register
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS: 8Ch)
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
ADIE
—
—
—
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-3
Unimplemented: Read as ‘0’
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
DS41206A-page 14
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
PIC16F716
2.2.2.5
PIR1 Register
Note:
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
PIR1 REGISTER (ADDRESS: 0Ch)
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
ADIF
—
—
—
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-3
Unimplemented: Read as ‘0’
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41206A-page 15
PIC16F716
2.2.2.6
PCON Register
Note:
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
These devices contain an additional bit to differentiate
a Brown-out Reset condition from a Power-on Reset
condition.
If the BOREN configuration bit is set, BOR
is ‘1’ on Power-on Reset and reset to ‘0’
when a Brown-out condition occurs. BOR
must then be set by the user and checked
on subsequent resets to see if it is clear,
indicating that another Brown-out has
occurred.
If the BOREN configuration bit is clear,
BOR is unknown on Power-on Reset.
REGISTER 2-6:
PCON REGISTER (ADDRESS: 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-q
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS41206A-page 16
Legend:
q = Depends on condition
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
PIC16F716
2.3
FIGURE 2-3:
PCL and PCLATH
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This
register is readable and writable. The high byte is
called the PCH register. This register contains the
PC<12:8> bits and is not directly readable or writable.
All updates to the PCH register go through the PCLATH
register.
2.3.1
Care should be exercised when modifying the PCL
register to jump into a look-up table or program branch
table (computed GOTO). With PCLATH set to the table
start address, if the table is greater than 255
instructions or if the lower 8 bits of the memory address
rolls over from 0xFF to 0x00 in the middle of the table,
then PCLATH must be incremented for each address
rollover that occurs between the table beginning and
the target address.
PROGRAM MEMORY PAGING
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper bit of the address is provided by
PCLATH<3>. When doing a CALL or GOTO instruction,
the user must ensure that the page select bit is
programmed so that the desired program memory
page is addressed. If a RETURN from a CALL instruction
(or interrupt) is executed, the entire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PCLATH<3> bit is not required for the RETURN
instructions (which POPs the address from the stack).
 2003 Microchip Technology Inc.
PCL
8 7
8
PCLATH<4:0>
5
0 Instruction with
PCL as
Destination
ALU
PCLATH
PCL
PCH
1110
0
8 7
GOTO, CALL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of PCLATH register. This allows the entire
contents of the program counter to be changed by first
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are then written to the PCL
register, all 13 bits of the program counter will change
to the values contained in the PCLATH register and
those being written to the PCL register.
2.3.2
PCH
12
12
MODIFYING PCL
LOADING OF PC IN
DIFFERENT SITUATIONS
PCLATH<4:3>
2
11
Opcode <10:0>
PCLATH
2.4
Stack
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space, and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed 8 times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Preliminary
DS41206A-page 17
PIC16F716
2.5
EXAMPLE 2-2:
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1:
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
NEXT
INDIRECT ADDRESSING
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear RAM & FSR
;inc pointer
;all done?
;no, clear next
CONTINUE
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
:
;yes, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-4. However, IRP is not used in the
PIC16F716.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although Status bits may be affected).
A simple program to clear RAM locations 20h – 2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1: RP0
6
Indirect Addressing
from opcode
0
IRP
(2)
bank select
bank select
location select
00
00h
01
80h
10
100h
FSR register
0
7Fh
Bank 0
FFh
17Fh
Bank 1
location select
11
180h
(3)
Data
Memory(1)
Note 1:
2:
3:
7
(2)
(3)
1FFh
Bank 2
Bank 3
For register file map detail see Figure 2-2.
Maintain clear for upward compatibility with future products.
Not implemented.
DS41206A-page 18
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
3.0
I/O PORTS
EXAMPLE 3-1:
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro® Mid-Range Reference Manual, (DS33023).
3.1
PORTA and the TRISA Register
PORTA is a 5-bit wide bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a High-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
BCF
CLRF
STATUS, RP0
PORTA
BSF
MOVLW
STATUS, RP0
0xEF
MOVWF
TRISA
BCF
STATUS, RP0
FIGURE 3-1:
DATA
BUS
D
BLOCK DIAGRAM OF
RA3:RA0
Q
VDD
CK
Q
P
Data Latch
D
WR
TRIS
CK
I/O pin
N
Q
VSS
Q
VSS
Analog
Input
mode
TRIS Latch
RD TRIS
On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
;
;Initialize PORTA by
;clearing output
;data latches
;Select Bank 1
;Value used to
;initialize data
;direction
;Set RA<3:0> as inputs
;RA<4> as outputs
;Return to Bank 0
VDD
WR
PORT
PORTA pins, RA3:0, are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register 1).
Note:
INITIALIZING PORTA
Q
TTL
Input
Buffer
D
EN
RD PORT
To A/D Converter
Note:
Setting RA3:0 to output while in Analog
mode will force pins to output contents of
data latch.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 19
PIC16F716
FIGURE 3-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data Latch
DATA
BUS
Q
D
WR
PORT
CK
RA4/T0CKI
Q
N
TRIS Latch
WR
TRIS
VSS
Q
D
CK
VSS
Schmitt
Trigger
Input
Buffer
Q
RD TRIS
Q
D
ENEN
RD PORT
TMR0 Clock Input
TABLE 3-1:
PORTA FUNCTIONS
Name
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Bit#
Buffer
bit 0
bit 1
bit 2
bit 3
bit 4
TTL
TTL
TTL
TTL
ST
Function
Input/output or analog input
Input/output or analog input
Input/output or analog input
Input/output or analog input or VREF
Input/output or external clock input for Timer0
Output is open drain type
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
Address
05h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
PORTA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
Resets
—
—(1)
RA4
RA2
RA1
RA0
--xx 0000
--uu uuuu
PORTA Data Direction Register
—
85h
TRISA
—
—
—(1)
9Fh
ADCON1
—
—
—
—
RA3
—
PCFG2 PCFG1 PCFG0
--11 1111
--11 1111
---- -000
---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
Note 1: Reserved bits, do not use.
DS41206A-page 20
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 3-2:
INITIALIZING PORTB
BCF
CLRF
STATUS, RP0
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
;select Bank 0
;Initialize PORTB by
;clearing output
;data latches
;Select Bank 1
;Value used to
;initialize data
;direction
;Set RB<3:0> as inputs
;RB<5:4> as outputs
;RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 3-3:
BLOCK DIAGRAM OF
RB0/INT/ECCPAS2 PIN
RBPU(1)
weak
P pull-up
Data Latch
D
Q
DATA
BUS
WR
PORT
Four of PORTB’s pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
1.
2.
Perform a read of PORTB to end the mismatch
condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
RB0/
INT/
ECCPAS2
CK
TRIS Latch
D
Q
WR
TRIS
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (such as BSF, BCF, XORWF) with
TRISB as the destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
VDD
VDD
PORTB pins RB7:RB0 are multiplexed with several
peripheral functions (Table 3-3).
VSS
CK
TTL
Input
Buffer
RD TRIS
Q
RD PORT
RB0/INT
D
EN
Schmitt Trigger
Buffer
RD PORT
ECCPAS2: ECCP Auto-shutdown input
Note
1:
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 21
PIC16F716
FIGURE 3-4:
BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
VDD
T1OSCEN
RBPU(1)
weak
P pull-up
VDD
DATA BUS
Data Latch
D
WR PORTB
CK
RB1/T1OSO/T1CKI
Q
Q
TRIS Latch
D
WR TRISB
CK
VSS
Q
Q
RD TRISB
T1OSCEN
TTL Buffer
Q
D
EN
RD PORTB
T1OSI (From RB2)
TMR1 oscillator
To Timer1 clock input
ST Buffer
Note
FIGURE 3-5:
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
BLOCK DIAGRAM OF RB2/T1OSI PIN
VDD
T1OSCEN
RBPU(1)
weak
P pull-up
VDD
Data Latch
DATA BUS
D
WR PORTB
CK
Q
RB2/T1OSI
Q
TRIS Latch
D
WR TRISB
CK
Q
VSS
Q
RD TRIS
T1OSCEN
TTL Buffer
Q
D
EN
RD PORTB
TMR1
Oscillator
T1OSO (To RB1)
Note
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS41206A-page 22
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 3-6:
BLOCK DIAGRAM OF RB3/CCP1/P1A PIN
VDD
RBPU(1)
[PWMA(P1A) / CCP1 Compare] Output Enable
[PWMA(P1A) / CCP1 Compare] Output
weak
P pull-up
VDD
1
RB3/CCP1/P1A
0
PWMA(P1A) Auto-shutdown tri-state
VSS
Data Latch
DATA BUS
D
WR PORTB
CK
Q
Q
TRIS Latch
D
WR TRISB
CK
Q
Q
RD TRIS
TTL Buffer
Q
D
EN
RD PORTB
Schmitt Trigger Buffer
CCP - Capture input
Note
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 3-7:
BLOCK DIAGRAM OF RB4/ECCPAS0 PIN
VDD
RBPU(1)
DATA BUS
WR PORTB
weak
P pull-up
Data Latch
D
Q
RB4/ECCPAS0
CK
TRIS Latch
D
Q
WR TRISB
VDD
VSS
TTL
Buffer
CK
ST
Buffer
RD TRIS
Q
Latch
D
EN
RD PORT
Q1
Set RBIF
From other
RB7:RB4 pins
Q
D
RD PORT
EN
ECCPAS0: ECCP Auto-Shutdown input
 2003 Microchip Technology Inc.
Preliminary
Q3
Note
1:
To enable weak pull-ups, set
the appropriate TRIS bit(s)
and clear the RBPU bit
(OPTION_REG<7>).
DS41206A-page 23
PIC16F716
FIGURE 3-8:
BLOCK DIAGRAM OF RB5/P1B PIN
VDD
RBPU(1)
PWMB(P1B) Enable
PWMB(P1B) Data out
PWMB(P1B) Auto-shutdown tri-state
Data Latch
DATA BUS
D
Q
WR PORTB
weak
P pull-up VDD
1
RB5/P1B
0
CK
TRIS Latch
D
Q
WR TRISB
CK
VSS
TTL
Buffer
Q
RD TRISB
Q
Latch
D
EN
RD PORTB
Q1
Set RBIF
Q
From other
RB7:RB4 pins
D
RD PORTB
Q3
EN
Note
FIGURE 3-9:
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
BLOCK DIAGRAM OF RB6/P1C PIN
VDD
RBPU(1)
PWMC(P1C) Enable
PWMC(P1C) Data out
PWMC(P1C) Auto-shutdown tri-state
Data Latch
DATA BUS
D
Q
WR PORTB
weak
P pull-up VDD
1
RB6/P1C
0
CK
TRIS Latch
D
Q
WR TRISB
CK
VSS
Q
ST
Buffer
RD TRISB
Q
TTL
Buffer
Latch
D
EN
RD PORTB
Q1
Set RBIF
From other
RB7:RB4 pins
Q
D
EN
RD PORTB
Q3
ICSPC - In circuit serial programming clock input
Note
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS41206A-page 24
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 3-10:
BLOCK DIAGRAM OF RB7/P1D PIN
VDD
RBPU(1)
PWMD(P1D) Enable
PWMD(P1D) Data out
PWMD(P1D) Auto-shutdown tri-state
Data Latch
DATA BUS
D
Q
WR PORTB
weak
P pull-up VDD
1
RB7/P1D
0
CK
TRIS Latch
D
Q
WR TRISB
CK
VSS
Q
ST
Buffer
RD TRISB
Q
Latch
D
EN
RD PORTB
TTL
Buffer
Q1
Set RBIF
Q
From other
RB7:RB4 pins
D
EN
Note
RD PORTB
Q3
ICSPD - In circuit serial programming data input
TABLE 3-3:
Name
1:
To enable weak pull-ups,
set the appropriate TRIS
bit(s) and clear the RBPU
bit (OPTION_REG<7>).
PORTB FUNCTIONS
Bit#
Buffer
bit 0
TTL/ST(1)
Function
Input/output pin or external interrupt input. Internal software
programmable weak pull-up. ECCP auto-shutdown input.
Input/output pin or Timer1 oscillator output, or Timer1 clock input. Internal
bit 1
TTL/ST(1)
software programmable weak pull-up. See Section 5.0 “Timer1 Module”
for detailed operation.
RB2/T1OSI
bit 2
TTL/XTAL
Input/output pin or Timer1 oscillator input. Internal software programmable
weak pull-up. See Section 5.0 “Timer1 Module” for detailed operation.
RB3/CCP1/
bit 3
TTL/ST(1)
Input/output pin or Capture1 input, or Compare1 output, or PWM A output.
P1A
Internal software programmable weak pull-up. See CCP1 section for
detailed operation.
bit 4
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
RB4/
weak pull-up. ECCP auto-shutdown input.
ECCPAS0
RB5/P1B
bit 5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. PWM B output.
Input/output pin (with interrupt-on-change). Internal software programmable
RB6/P1C
bit 6
TTL/ST(2)
weak pull-up. PWM C output. Serial programming clock.
(2)
Input/output pin (with interrupt-on-change). Internal software programmable
RB7/P1D
bit 7
TTL/ST
weak pull-up. PWM D output. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input, XTAL = Crystal Oscillator input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
RB0/INT/
ECCPAS2
RB1/T1OS0/
T1CKI
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 25
PIC16F716
TABLE 3-4:
Address
06h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
PORTB
86h
TRISB
81h
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
PORTB Data Direction Register
RBPU
INTEDG
T0CS
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS41206A-page 26
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
4.0
TIMER0 MODULE
4.2
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
Prescaler
8-bit timer/counter
Readable and writable
Internal or external clock select
Edge select for external clock
8-bit software programmable prescaler
Interrupt on overflow from FFh to 00h
Note:
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
4.1
There is only one prescaler available,
which is mutually exclusively shared
between the Timer0 module and Watchdog Timer. Thus, a prescaler assignment
for the Timer0 module means that there is
no prescaler for the Watchdog Timer and
vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Timer0 Operation
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the
increment is inhibited for the following two instruction
cycles. The user can work around this by writing an
adjusted value to the TMR0 register.
Setting bit PSA will assign the prescaler to the
Watchdog Timer (WDT). When the prescaler is
assigned to the WDT, prescale values of 1:1, 1:2, ...,
1:128 are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF
1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment on every rising or falling edge of pin RA4/
T0CKI. The incrementing edge is determined by the
Timer0
Source
Edge
Select
bit
T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the
rising edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
Additional information on external clock requirements
is available in the PICmicro® Mid-Range Reference
Manual, (DS33023).
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
PSOUT
8
1
1
RA4/T0CKI
pin
Programmable
Prescaler(2)
0
Sync with
Internal
clock
TMR0
PSOUT
(2 cycle delay)
T0SE(1)
3
T0CS(1)
Note
1:
2:
PS2, PS1, PS0(1)
PSA(1)
Set interrupt
flag bit T0IF
on overflow
T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 27
PIC16F716
4.2.1
SWITCHING PRESCALER
ASSIGNMENT
4.3
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt
service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
Sleep since the timer is shut off during Sleep.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
Note:
To avoid an unintended device Reset, a
specific instruction sequence (shown in
the PICmicro® Mid-Range Reference
Manual, DS33023) must be executed
when changing the prescaler assignment
from Timer0 to the WDT. This sequence
must be followed even if the WDT is
disabled.
FIGURE 4-2:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=FOSC/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
1
Watchdog
Timer
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
M
U
X
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-out
Note:
T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Name
01h
TMR0
0Bh,8Bh
INTCON
81h
OPTION_REG
85h
TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0IE
INTE
RBIE
T0IF
INTF
RBIF
T0CS
T0SE
PSA
PS2
PS1
PS0
—(1)
Bit 4
Timer0 module’s register
GIE
PEIE
RBPU INTEDG
—
—
PORTA Data Direction Register
Value on:
POR,
BOR
Value on all
other Resets
xxxx xxxx
uuuu uuuu
0000 000x
0000 000u
1111 1111
1111 1111
--11 1111
--11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1:
Reserved bits, do not use.
DS41206A-page 28
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
5.0
TIMER1 MODULE
5.1
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from ECCP module trigger
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 has a control register, shown in Register 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Figure 5-1 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
REGISTER 5-1:
Timer1 Operation
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB2/T1OSI and RB1/T1OSO/T1CKI pins
become inputs. That is, the TRISB<2:1> value is
ignored.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the ECCP module
(Section 7.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”).
T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
U-0
—
—
R/W-0
R/W-0
T1CKPS1 T1CKPS0
R/W-0
T1OSCEN
R/W-0
R/W-0
R/W-0
T1SYNC TMR1CS TMR1ON
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off(1)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB1/T1OSO/T1CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1:
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41206A-page 29
PIC16F716
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
clock input
0
TMR1
TMR1L
TMR1H
1
TMR1ON
on/off
T1SYNC
T1OSC
RB1/T1OSO/T1CKI
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
RB2/T1OSI
Note 1:
5.2
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS1:T1CKPS0
TMR1CS
Sleep input
When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator designed to operate
with a 32.768 kHz tuning fork crystal. It will continue to
run during Sleep.
5.4
Resetting Timer1 using an ECCP
Trigger Output
If the ECCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
The user must provide a software time delay to ensure
proper oscillator start-up.
Note 1: Circuit guidelines for the LP oscillator
(32 kHz), as shown in Section 9.2
“Oscillator Configurations”, also apply
to the Timer1 Oscillator.
Note:
The special event triggers from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
2: The Timer1 register pair, TMR1H and
TMR1L, in combination with the Timer1
overflow flag (TMR1IF) can be used as
the oscillator start-up stabilization timer.
Timer1 must be configured for either Timer or
Synchronized Counter mode to take advantage of this
feature. If Timer1 is running in Asynchronous Counter
mode, this Reset operation may not work.
Timer1 Interrupt
In the event that a write to Timer1 coincides with a
special event trigger from the ECCP, the write will take
precedence.
5.3
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
TABLE 5-1:
Address
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
0Bh,8Bh
INTCON
0Ch
PIR1
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
—
ADIF
—
—
—
CCP1IF
TMR2IF
TMR1IF
-0-- -000 -0-- -000
—
ADIE
—
—
—
CCP1IE
TMR2IE
TMR1IE
-0-- -000 -0-- -000
8Ch
PIE1
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
Legend:
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.
DS41206A-page 30
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
6.0
TIMER2 MODULE
Figure 6-1 is a simplified block diagram of the Timer2
module.
The Timer2 module timer has the following features:
•
•
•
•
•
•
Additional information on timer modules is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
Timer2 has a control register, shown in Register 6-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
REGISTER 6-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1
R/W-0
TOUTPS0
R/W-0
R/W-0
R/W-0
TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
0011 = 1:4 Postscale
0100 = 1:5 Postscale
0101 = 1:6 Postscale
0110 = 1:7 Postscale
0111 = 1:8 Postscale
1000 = 1:9 Postscale
1001 = 1:10 Postscale
1010 = 1:11 Postscale
1011 = 1:12 Postscale
1100 = 1:13 Postscale
1101 = 1:14 Postscale
1110 = 1:15 Postscale
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41206A-page 31
PIC16F716
6.1
Timer2 Operation
6.2
Timer2 can be used as the PWM time base for PWM
mode of the ECCP module.
Timer2 Interrupt
The Timer2 module has an 8-bit Period register (PR2).
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The TMR2 register is readable and writable, and is
cleared on any device Reset
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
FIGURE 6-1:
Sets flag
bit TMR2IF
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>).
TIMER2 BLOCK DIAGRAM
TMR2
output
Reset
The prescaler and postscaler counters are cleared
when any of the following occurs:
Postscaler
1:1 to 1:16
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset, or Brown-out Reset)
EQ
4
TMR2 reg
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
Comparator
PR2 reg
TMR2 is not cleared when T2CON is written.
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address
Name
Bit 7
0Bh, 8Bh
INTCON
0Ch
PIR1
8Ch
PIE1
11h
TMR2
12h
T2CON
92h
PR2
Legend:
Bit 2
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
INTF
RBIF
0000 000x
0000 000u
TMR2IF
TMR1IF
-0-- -000
-0-- -000
TMR1IE
-0-- -000
-0-- -000
0000 0000
0000 0000
-000 0000
-000 0000
1111 1111
1111 1111
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
GIE
PEIE
T0IE
INTE
RBIE
T0IF
—
ADIF
—
—
—
CCP1IF
—
ADIE
—
—
—
CCP1IE
TMR2IE
—
TOUTPS3
TOUTPS2
TOUTPS1
Timer2 module’s register
TOUTPS0
TMR2ON
Timer2 Period Register
T2CKPS1 T2CKPS0
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.
DS41206A-page 32
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
7.0
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
The CCP1CON register controls ECCP operation. All
the CCP1CON bits are readable and writable.
The ECCP (Enhanced Capture/Compare/PWM)
module contains a 16-bit register, which can operate
as:
Additional information on the ECCP module is available
in the PICmicro® Mid-Range Reference Manual,
(DS33023).
TABLE 7-1:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
ECCP MODE - TIMER
RESOURCE
ECCP Mode
Table 7-1 shows the timer resources of the ECCP
module modes.
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
Capture/Compare/PWM Register 1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte).
REGISTER 7-1:
CCP1CON REGISTER (ADDRESS: 17h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
bit 7-6
P1M1:P1M0: PWM Output Configuration bits
CCP1M<3:2> = 00, 01, 10
xx = P1A assigned as Capture/Compare I/O. P1B, P1C, P1D assigned as Port pins.
CCP1M<3:2> = 11
00 = Single output, P1A modulated. P1B, P1C, P1D assigned as Port pins.
01 = Quad output forward. P1D modulated, P1A active. P1B and P1C inactive.
10 = Dual output. P1A, P1B modulated with dead-time control. P1C, P1D assigned as port pins.
11 = Quad output reverse. P1B modulated, P1C active. P1A and P1D inactive.
bit 5-4
DC1B1:DC1B0: PWM Least Significant bits
Capture mode: Unused
Compare mode: Unused
PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found
in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (Reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (Reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set CCP1 output on match (CCP1IF bit is set)
1001 = Compare mode, clear CCP1 output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, TMR1 is reset, and an A/D conversion is
started if the A/D module is enabled. CCP1 pin is unaffected).
1100 = PWM mode. P1A, P1C active-high; P1B, P1D active-high.
1101 = PWM mode. P1A, P1C active-high; P1B, P1D active-low.
1110 = PWM mode. P1A, P1C active-low; P1B, P1D active-high.
1111 = PWM mode. P1A, P1C active-low; P1B, P1D active-low.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41206A-page 33
PIC16F716
7.1
7.1.4
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1/P1A. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit CCP1IF (PIR1<2>) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value will be lost.
Note:
Always reset the ECCP module
(CCP1M3:CCP1M0 = ‘0000’) between
changing from one capture mode to
another. This is necessary to reset the
internal capture counter.
FIGURE 7-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
1, 4, 16
RB3/CCP1/P1A
Pin
CCPR1H
and
edge detect
CCPR1L
TMR1L
CCP1CON<3:0>
Q’s
7.1.1
7.1.2
EXAMPLE 7-1:
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS
MOVWF CCP1CON
CHANGING BETWEEN
CAPTURE PRESCALERS
;Turn ECCP module off
;Load the W reg with
;the new prescaler
;mode value and ECCP ON
;Load CCP1CON with this
;value
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1/P1A pin is
either:
Driven High
Driven Low
Toggle output (high-to-low or low-to-high)
Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
CCP1 PIN CONFIGURATION
In Capture mode, the RB3/CCP1/P1A pin should be
configured as an input by setting the TRISB<3> bit.
Note:
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 7-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
•
•
•
•
Capture
Enable
TMR1H
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the ECCP module is
turned off, or the ECCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
7.2
Set flag bit CCP1IF
(PIR1<2>)
ECCP PRESCALER
If the RB3/CCP1/P1A is configured as an
output, a write to PORTB can cause a
capture condition.
Changing the ECCP mode to clear output on match
(CCP1M<3:0> = 1000) presets the CCP1 output latch
to the logic 1 level. Changing the ECCP mode to set
output on match (CCP1M<3:0> = 1001) presets the
CCP1 output latch to the logic 0 level.
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or
Synchronized Counter mode for the ECCP module to
use the capture feature. In Asynchronous Counter
mode, the capture operation may not work.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS41206A-page 34
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
7.2.1
CCP1 PIN CONFIGURATION
The user must configure the RB3/CCP1/P1A pin as the
CCP1 output by clearing the TRISB<3> bit.
Note:
7.2.2
Note:
Clearing the CCP1CON register will force
the RB3/CCP1/P1A compare output latch
to the default low level. This is not the
PORTB I/O data latch.
The special event trigger from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
FIGURE 7-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
TIMER1 MODE SELECTION
Special Event Trigger
Timer1 must be running in Timer mode or
Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
Set flag bit CCP1IF
(PIR1<2>)
RB3/CCP1/P1A
Pin
CCPR1H CCPR1L
Q
S
R
7.2.3
SOFTWARE INTERRUPT MODE
TRISB<3>
Output Enable
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is
generated (if enabled).
7.2.4
Note
1:
SPECIAL EVENT TRIGGER
Output
Logic
Comparator
match
TMR1H
CCP1CON<3:0>
Mode Select
TMR1L
Special event trigger will reset Timer1, but not set
interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/
DONE (ADCON0<2>) which starts an A/D
conversion.
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of the ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of the ECCP also starts
an A/D conversion (if the A/D module is enabled).
TABLE 7-2:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
GIE
PEIE
T0IE
INTE
RBIE
T0IF
—
ADIF
—
—
—
CCP1IF
Bit 0
Value on
POR,
BOR
INTF
RBIF
0000 000x
0000 000u
TMR2IF
TMR1IF
-0-- -000
-0-- -000
xxxx xxxx
uuuu uuuu
Bit 2
Bit 1
0Bh,8Bh
INTCON
0Ch
PIR1
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1register
10h
T1CON
15h
CCPR1L
16h
CCPR1H
17h
CCP1CON
86h
TRISB
8Ch
PIE1
Legend:
Value on
all other
Resets
xxxx xxxx
uuuu uuuu
--00 0000
--uu uuuu
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
1111 1111
1111 1111
-0-- -000
-0-- -000
—
P1M1
—
P1M0
T1CKPS1
DC1B1
T1CKPS0
DC1B0
T1OSCEN
CCP1M3
T1SYNC
CCP1M2
TMR1CS
CCP1M1
TMR1ON
CCP1M0
PORTB Data direction register
—
ADIE
—
—
—
CCP1IE
TMR2IE
TMR1IE
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 35
PIC16F716
7.3
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
pin an output.
Note:
A PWM output (Figure 7-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 7-4:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Period = PR2+1
Duty Cycle
Figure 7-3 shows a simplified block diagram of the
CCP module in PWM mode.
TMR2 = PR2
For a step-by-step procedure on how to setup the
ECCP module for PWM operation, see Section 7.3.3
“Set-Up for PWM Operation”.
FIGURE 7-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty cycle registers
PWM OUTPUT
TMR2 = Duty Cycle (CCPR1H)
TMR2 = PR2
7.3.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
CCP1CON<5:4>
CCPR1L
EQUATION 7-1:
PWM Period = [(PR2) + 1] • 4 • Tosc •
(TMR2 prescale value)
CCPR1H (Slave)
RB3/CCP1/P1A
R
Comparator
TMR2
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
S
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
TRISB<3>
Clear Timer,
CCP1 pin and
latch D.C.
PR2
1:
PWM frequency is defined as 1/[PWM period].
(Note 1)
Comparator
Note
Q
8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time base.
Note:
DS41206A-page 36
Preliminary
The Timer2 postscaler (see Section 6.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
 2003 Microchip Technology Inc.
PIC16F716
7.3.2
PWM DUTY CYCLE
EQUATION 7-3:
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
log
Max resolution =
Note:
If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
For an example PWM period and duty cycle
calculation, see the PICmicro® Mid-Range Reference
Manual, (DS33023).
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
7.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISB<3> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
2.
3.
When the CCPR1H and 2-bit latch match TMR2
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
4.
Maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation:
5.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 7-4:
Address
bits
log(2)
EQUATION 7-2:
TABLE 7-3:
OSC
( FFPWM
)
16
0xFF
10
4
0xFF
10
1
0xFF
10
1
0x3F
8
1
0x1F
7
1
0x17
6.6
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 1
Bit 0
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
—
—
CCP1IF
TMR2IF
TMR1IF
-0-- -000
-0-- -000
11h
TMR2
0000 0000
0000 0000
12h
T2CON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
0000 0000
0000 0000
86h
TRISB
1111 1111
1111 1111
8Ch
PIE1
-0-- -000
-0-- -000
92h
PR2
1111 1111
1111 1111
Legend:
Bit 2
Value on
POR,
BOR
Name
Timer2 module’s register
—
P1M1
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
PORB Data direction register
—
ADIE
—
—
—
Timer2 module’s period register
CCP1IE
TMR2IE
TMR1IE
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 37
PIC16F716
7.4
7.4.1
ENHANCED PWM MODE
PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allows
one of four configurations:
The Enhanced PWM mode provides additional PWM
output options for a broader range of control
applications. The module is an upwardly compatible
version of the standard CCP module and offers up to
four outputs, designated P1A through P1D. Users are
also able to select the polarity of the signal (either
active-high or active-low). The module’s Output mode
and polarity are configured by setting the P1M1:P1M0
and CCP1M3:CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
•
•
•
•
Single Output
Half-Bridge Output
Full-Bridge Output Forward mode
Full-Bridge Output Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 7.3 “PWM Mode”. The HalfBridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
Figure 7-5 shows a simplified block diagram of PWM
operation. All control registers are double buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Dead-band Delay, which is loaded at either
the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets, instead of
starting immediately. This means that enhanced PWM
waveforms do not exactly match the standard PWM
waveforms, but are instead offset by one full instruction
cycle (4 TOSC).
The general relationship of the outputs in all
configurations is summarized in Figure 7-6.
As before, the user must manually configure the
appropriate TRISB bits for output.
FIGURE 7-5:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
Duty Cycle Registers
CCP1M<3:0>
4
P1M<1:0>
2
CCPR1L
CCP1/P1A
RB3/CCP1/P1A
TRISB<3>
CCPR1H (Slave)
P1B
R
Comparator
Q
Output
Controller
RB5/P1B
TRISB<5>
RB6/P1C
P1C
(Note 1)
TMR2
TRISB<6>
S
P1D
Comparator
Clear Timer,
set CCP1 pin and
latch D.C.
PR2
Note
1:
RB7/P1D
TRISB<7>
PWM1CON
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
DS41206A-page 38
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 7-6:
PWM OUTPUT RELATIONSHIPS (P1A, P1B, P1C, P1D ACTIVE-HIGH STATE)
0
00
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
(Single Output)
P1A Modulated
Delay(1)
Delay(1)
P1A Modulated
10
(Half-Bridge)
P1B Modulated
P1A Active
01
P1B Inactive
(Full-Bridge,
Forward)
P1C Inactive
P1D Modulated
P1A Inactive
11
P1B Modulated
(Full-Bridge,
Reverse)
P1C Active
P1D Inactive
FIGURE 7-7:
PWM OUTPUT RELATIONSHIPS (P1A, P1B, P1C, P1D ACTIVE-LOW STATE)
0
00
(Single Output)
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
10
(Half-Bridge)
Delay(1)
Delay(1)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)
• Duty Cycle = TOSC * (CCPR1L<7:0> : CCP1CON<5:4>) * (TMR2 prescale value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 7.4.4 “Programmable Dead-Band
Delay”).
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 39
PIC16F716
FIGURE 7-8:
PWM OUTPUT RELATIONSHIPS (P1A, P1C ACTIVE-HIGH. P1B, P1D
ACTIVE-LOW)
0
CCP1CON
<7:6>
00
(Single Output)
PR2+1
Duty
Cycle
SIGNAL
Period
P1A Modulated
Delay(1)
Delay(1)
P1A Modulated
10
(Half-Bridge)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
DS41206A-page 40
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 7-9:
PWM OUTPUT RELATIONSHIPS (P1A, P1C ACTIVE-LOW. P1B, P1D
ACTIVE-HIGH)
0
00
(Single Output)
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
10
(Half-Bridge)
Delay(1)
Delay(1)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)
• Duty Cycle = TOSC * (CCPR1L<7:0> : CCP1CON<5:4>) * (TMR2 prescale value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 7.4.4 “Programmable Dead-Band
Delay”).
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 41
PIC16F716
7.4.2
HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the RB3/CCP1/P1A pin, while the
complementary PWM output signal is output on the
RB5/P1B pin (Figure 7-12). This mode can be used for
half-bridge applications, as shown in Figure 7-11 or for
full-bridge applications, where four power switches are
being modulated with two PWM signals.
In Half-Bridge Output mode, the programmable deadband delay can be used to prevent shoot-through
current in half-bridge power devices. The value of
PWM1CON bits PDC6:PDC0 sets the number of
instruction cycles before the output is driven active. If
the value is greater than the duty cycle, the
corresponding output remains inactive during the entire
cycle. See Section 7.4.4 “Programmable DeadBand Delay” for more details of the dead-band delay
operations.
Since the P1A and P1B outputs are multiplexed with
the PORTB<3> and PORTB<5> data latches, the
TRISB<3> and TRISB<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 7-10:
Period
Period
Duty Cycle
(2)
P1A
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-band Delay
Note 1:
2:
FIGURE 7-11:
HALF-BRIDGE PWM
OUTPUT
At this time, the TMR2 register is equal to the
PR2 register.
Output signals are shown as active-high.
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC16F716
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC16F716
FET
Driver
FET
Driver
P1A
FET
Driver
Load
FET
Driver
P1B
V-
DS41206A-page 42
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
7.4.3
FULL-BRIDGE MODE
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTB<3> and PORTB<5:7> data latches. The
TRISB<3> and TRISB<5:7> bits must be cleared to
make the P1A, P1B, P1C, and P1D pins output.
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin RB3/CCP1/P1A is
continuously active, and pin RB7/P1D is modulated. In
the Reverse mode, RB6/P1C pin is continuously active,
and RB5/P1B pin is modulated. These are illustrated in
Figure 7-6 through Figure 7-9.
FIGURE 7-12:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC16F716
FET
Driver
QC
QA
FET
Driver
P1A
Load
P1B
FET
Driver
P1C
FET
Driver
QD
QB
VP1D
7.4.3.1
Direction Change in Full-Bridge
Mode
Note:
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control the
Forward/Reverse direction. When the application
firmware changes this direction control bit, the module
will assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction. This
occurs in a time interval of (4•TOSC•(Timer2 Prescale
value)) before the next PWM period begins. The Timer2
prescaler will be either 1, 4 or 16, depending on the
value of the T2CKPSx bits (T2CON<1:0>). During the
interval from the switch of the unmodulated outputs to
the beginning of the next period, the modulated outputs
(P1B and P1D) remain inactive. This relationship is
shown in Figure 7-13.
 2003 Microchip Technology Inc.
Preliminary
In the Full-Bridge Output mode, the ECCP
module does not provide any dead-band
delay. In general, since only one output is
modulated at all times, dead-band delay is
not required. However, there is a situation
where a dead-band delay might be
required. This situation occurs when both
of the following conditions are true:
1. The direction of the PWM output
changes when the duty cycle of the
output is at or near 100%.
2. The turn off time of the power switch,
including the power device and driver
circuit, is greater than the turn on
time.
DS41206A-page 43
PIC16F716
Figure 7-14 shows an example where the PWM
direction changes from forward to reverse, at a near
100% duty cycle. At time t1, the output P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices QC and QD
(see Figure 7-12) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
FIGURE 7-13:
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1.
2.
Reduce PWM for a PWM period before changing
directions.
Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
PWM DIRECTION CHANGE
Period(1)
SIGNAL
Period
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
(Note 2)
P1D (Active-High)
DC
Note 1:
2:
The direction bit in the CCP1 Control Register (CCP1CON<7>) is written any time during the PWM cycle.
When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of
4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are
inactive at this time.
FIGURE 7-14:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
t1
Reverse Period
P1A
P1B
DC
P1C
P1D
DC
ton
External Switch C
toff
External Switch D
Potential
Shoot-Through
Current
Note 1:
2:
3:
t = toff - ton
All signals are shown as active-high.
ton is the turn-on delay of power switch QC and its driver.
toff is the turn-off delay of power switch QD and its driver.
DS41206A-page 44
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
7.4.4
PROGRAMMABLE DEAD-BAND
DELAY
7.4.5
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on,
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shootthrough current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shootthrough current from destroying the bridge power
switches. The delay occurs at the signal transition from
the non-active state to the active state. See Figure 7-10
for illustration. The lower seven bits of the PWM1CON
register (Register 7-2) sets the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
ENHANCED PWM
AUTO-SHUTDOWN
When the ECCP is programmed for any of the
enhanced PWM modes, the active output pins may be
configured
for
auto-shutdown.
Auto-shutdown
immediately places the enhanced PWM output pins
into a defined shutdown state when a shutdown event
occurs.
A shutdown event can be caused by a logic low level on
either or both of the RB0/INT/ECCPAS2 or RB4/
ECCPAS0 pins. The auto-shutdown feature can be
disabled by not selecting any auto-shutdown sources.
The auto-shutdown sources to be used are selected
using the ECCPAS2 and ECCPAS0 bits (ECCPAS<6>
and ECCPAS<4>).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
by
the
PSSAC1:PSSAC0
and
PSSBD1:PSSBD0 bits (ECCPAS<3:0>). Each pin pair
(P1A/P1C and P1B/P1D) may be set to drive high,
drive low, or be tri-stated (not driving). The ECCPASE
bit (ECCPAS<7>) is also set to hold the enhanced
PWM outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit must be cleared by firmware when the
cause of the shutdown clears. If automatic restarts are
enabled, the ECCPASE bit is automatically cleared
when the cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:
 2003 Microchip Technology Inc.
Preliminary
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
DS41206A-page 45
PIC16F716
REGISTER 7-2:
PWM1CON: PWM CONFIGURATION REGISTER (ADDRESS: 18h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
bit 7
bit 0
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically.
0 = Upon auto-shutdown, ECCPASE must be cleared in firmware to restart the PWM.
bit 6-0
PDC<6:0>: PWM Delay Count bits
Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should
transition active, and the actual time it transitions active.
Legend:
REGISTER 7-3:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
ECCPAS – ENHANCED CCP AUTO SHUT DOWN REGISTER (ADDRESS: 19h)
R/W-0
R/W-0
ECCPASE ECCPAS2
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred. Must be reset in firmware to re-enable ECCP if
PRSEN = 0
0 = ECCP outputs enabled, no shutdown event
bit 6
ECCPAS2: ECCP Auto-Shutdown bit 2
1 = RB0 (INT) pin low level (‘0’) causes shutdown
0 = RB0 (INT) pin has no effect on ECCP
bit 5
Unimplemented: Read as ‘0’
bit 4
ECCPAS0: ECCP Auto-Shutdown bit ‘0’
1 = RB4 pin low level (‘0’) causes shutdown
0 = RB4 pin has no effect on ECCP
bit 3-2
PSSAC<1:0>: Pin P1A and P1C Shutdown State Control
00 = Drive Pins P1A and P1C to ‘0’
01 = Drive Pins P1A and P1C to ‘1’
1x = Pins P1A and P1C tri-state
bit 1-0
PSSBD<1:0>: Pin P1B and P1D Shutdown State Control
00 = Drive Pins P1B and P1D to ‘0’
01 = Drive Pins P1B and P1D to ‘1’
1x = Pins P1B and P1D tri-state
Legend:
DS41206A-page 46
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
PIC16F716
7.4.5.1
Auto-Shutdown and Automatic
Restart
7.4.6
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
PWM1CON register (PWM1CON<7>).
In Shutdown mode with PRSEN = 1 (PWM1CON <7>)
(Figure 7-15), the ECCPASE bit will remain set for as
long as the cause of the shutdown continues. When the
shutdown condition clears, the ECCPASE bit is
cleared. If PRSEN = 0 (Figure 7-16), once a shutdown
condition occurs, the ECCPASE bit will remain set until
it is cleared by firmware. Once ECCPASE is cleared,
the enhanced PWM will resume at the beginning of the
next PWM period.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
The ECCPASE bit cannot be cleared as long as the
cause of the shutdown persists.
The Auto-shutdown mode can be forced by writing a '1'
to the ECCPASE bit.
FIGURE 7-15:
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The
external circuits must keep the power switch devices in
the off state, until the microcontroller drives the I/O pins
with the proper signal levels, or activates the PWM
output(s).
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity
configuration while the PWM pins are configured as
outputs is not recommended since it may result in
damage to the application circuits.
The P1A, P1B, P1C and P1D output latches may not
be in the proper states when the PWM module is
initialized. Enabling the PWM pins for output at the
same time as the ECCP module may cause damage to
the application circuit. The ECCP module must be
enabled in the proper Output mode and complete a full
PWM cycle before configuring the PWM pins as
outputs. The completion of a full PWM cycle is
indicated by the TMR2IF bit being set as the second
PWM period begins.
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
FIGURE 7-16:
Shutdown
Shutdown
Event Occurs Event Clears
PWM
Resumes
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
 2003 Microchip Technology Inc.
ECCPASE
Cleared by
Shutdown
Shutdown Firmware PWM
Event Occurs Event Clears
Resumes
Preliminary
DS41206A-page 47
PIC16F716
7.4.7
SETUP FOR PWM OPERATION
8.
Configure and start TMR2:
The following steps should be taken when configuring
the ECCP module for PWM operation:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
1.
• Set the TMR2 prescale value by loading the
T2CKPSx bits (T2CON<1:0>).
2.
3.
Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISB bits.
Set the PWM period by loading the PR2 register.
Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
9.
• Wait until TMR2 overflows (TMR2IF bit is set).
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRISB
bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
4.
5.
6.
Enable PWM outputs after a new PWM cycle
has started:
• Clear the ECCPASE bit (ECCPAS<7>).
See the previous section for additional details.
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
For Half-Bridge Output mode, set the deadband delay by loading PWM1CON<6:0> with
the appropriate value.
If auto-shutdown operation is required, load the
ECCPAS register.
7.4.8
EFFECTS OF A RESET
Both Power-on and subsequent Resets will force all
ports to Input mode and the ECCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard ECCP module.
• Select the auto-shutdown sources using the
ECCPAS<2> AND ECCPAS<0> bits.
• Select the shutdown states of the PWM output
pins
using
PSSAC1:PSSAC0
and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCPAS<7>).
7.
If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
TABLE 7-5:
Address
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Name
Bit 7
0Bh
INTCON
0Ch
PIR1
8Ch
PIE1
11h
TMR2
Timer2 Module Register
92h
PR2
Timer2 Module Period Register
12h
T2CON
Value on
POR, BOR
INT0IF
RBIF
0000 000x 0000 000u
TMR2IF
TMR1IF
-0-- -000 -0-- -000
TMR1IE
-0-- --00 -0-- --00
Bit 5
Bit 4
Bit 3
Bit 2
GIE
PEIE
TMR0IE
INT0IE
RBIE
TMR0IF
—
ADIF
—
—
—
CCP1IF
—
ADIE
—
—
—
CCP1IE
TMR2IE
—
TOUTPS3
Value on
all other
Resets
Bit 0
Bit 6
Bit 1
0000 0000 0000 0000
1111 1111 1111 1111
TOUTPS2
TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
16h
CCPR1H
Enhanced Capture/Compare/PWM Register1 High Byte
xxxx xxxx uuuu uuuu
15h
CCPR1L
Enhanced Capture/Compare/PWM Register1 Low Byte
17h
CCP1CON
19h
ECCPAS
18h
PWM1CON
Legend:
P1M1
P1M0
ECCPASE
PRSEN
xxxx xxxx uuuu uuuu
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 0000 0000 0000 0000
ECCPAS2
—
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0 00-0 0000 00-0 0000
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000 0000 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module in enhanced PWM mode.
DS41206A-page 48
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
8.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
Additional information on the A/D module is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
The Analog-to-Digital (A/D) Converter module has four
inputs.
The A/D module has three registers. These registers
are:
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to
Application Note AN546 for use of A/D Converter). The
output of the sample and hold is the input into the
converter, which generates the result via successive
approximation. The analog reference voltage is
software selectable to either the device’s positive
supply voltage (VDD) or the voltage level on the RA3/
AN3/VREF pin.
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
The ADCON0 register, shown in Register 8-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 8-2, configures the
functions of the port pins. The port pins can be
configured as analog inputs (RA3 can also be a voltage
reference) or as digital I/O.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
REGISTER 8-1:
ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 0
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (Clock derived from the internal ADC RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
1xx = reserved, do not use
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (Setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
Reserved: Maintain this bit as '0'
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41206A-page 49
PIC16F716
REGISTER 8-2:
ADCON1 REGISTER (ADDRESS: 9Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-3
Unimplemented: Read as '0'
bit 2-0
PCFG2:PCFG0: A/D Port Configuration Control bits
AN3
RA3
AN2
RA2
AN2
RA1
AN0
RA0
0x0
A
A
A
A
VDD
0x1
VREF
A
A
A
RA3
PCFG2:PCFG0
VREF
100
A
D
A
A
VDD
101
VREF
D
A
A
RA3
D
D
D
D
VDD
11x
Legend:
A = Analog input, D = Digital I/O
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
The ADRES register contains the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared and the A/D interrupt flag
bit ADIF is set. The block diagram of the A/D module is
shown in Figure 8-1.
The value that is in the ADRES register is not modified
for any Reset. The ADRES register will contain
unknown data after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 8.1
“A/D Acquisition Requirements”. After this
acquisition time has elapsed, the A/D conversion can
be started. The following steps should be followed for
doing an A/D conversion:
1.
2.
3.
4.
5.
Configure the A/D module:
- Configure analog pins/voltage reference/
and digital I/O (ADCON1)
- Select A/D input channel (ADCON0)
- Select A/D conversion clock (ADCON0)
- Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
- Clear ADIF bit
- Set ADIE bit
- Set GIE bit
Wait the required acquisition time.
Start conversion:
- Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
- Polling for the GO/DONE bit to be cleared
OR
6.
7.
DS41206A-page 50
x = Bit is unknown
Preliminary
- Waiting for the A/D interrupt
Read A/D Result register (ADRES), clear bit
ADIF if required.
For the next conversion, go to step 1 or step 2
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 8-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
VIN
011
(Input voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
000 or
010 or
100 or
110 or 111
VREF
(Reference
voltage)
001 or
011 or
101
PCFG2:PCFG0
8.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the
analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 10 kΩ. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
FIGURE 8-2:
To calculate the minimum acquisition time, TACQ, see
the PICmicro® Mid-Range Reference Manual,
(DS33023). This equation calculates the acquisition
time to within 1/2 LSb error. The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
accuracy.
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
ANALOG INPUT MODEL
VDD
Rs
ANx
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS
RSS
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend:
CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
 2003 Microchip Technology Inc.
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
Preliminary
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
DS41206A-page 51
PIC16F716
8.2
Selecting the A/D Conversion
Clock
8.3
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•
•
•
•
2 TOSC
8 TOSC
32 TOSC
Internal RC oscillator
The ADCON1 and TRISA registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 8-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 8-1:
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins
configured as digital inputs, will convert
an analog input. Analog levels on a
digitally configured input will not affect the
conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN3:AN0
pins), may cause the input buffer to
consume current that is out of the devices
specification.
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Operation
2 TOSC
8 TOSC
32 TOSC
RC
Legend:
Note 1:
2:
3:
4:
Configuring Analog Port Pins
Device Frequency
ADCS1:ADCS0
20 MHz
5 MHz
1.25 MHz
333.33 kHz
00
100 ns(2)
400 ns(2)
1.6 µs
6 µs
01
ns(2)
1.6 µs
6.4 µs
24 µs(3)
10
400
1.6 µs
6.4 µs
25.6
µs(3)
96 µs(3)
11
2-6 µs(1), (4)
2-6 µs(1), (4)
2-6 µs(1), (4)
2-6 µs(1)
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 4 µs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
Sleep operation only.
DS41206A-page 52
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
8.4
Note:
8.5
A/D Conversions
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Use of the ECCP Trigger
An A/D conversion can be started by the “special event
trigger” of the ECCP module. This requires that the
CCP1M3:CCP1M0
bits
(CCP1CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the GO/
DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 8-2:
Address
Name
SUMMARY OF A/D REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other Resets
05h
PORTA
—
—
—(1)
RA4
RA3
RA2
RA1
RA0
--xx 0000
--uu uuuu
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
—
—
CCP1IF
TMR2IF
TMR1IF
-0-- -000
-0-- -000
1Eh
ADRES
A/D Result Register
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
0000 0000
0000 0000
--11 1111
--11 1111
ADCS0
CHS2
CHS1
(1)
CHS0
GO/DONE
—(1)
ADON
85h
TRISA
—
—
8Ch
PIE1
—
ADIE
—
—
—
CCP1IE
TMR2IE
TMR1IE
-0-- -000
-0-- 0000
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
---- -000
Legend:
Note 1:
—
PORTA Data Direction Register
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for A/D conversion.
Reserved bit, do not use.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 53
PIC16F716
NOTES:
DS41206A-page 54
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
9.0
SPECIAL FEATURES OF THE
CPU
The PIC16F716 device has a host of features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These are:
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code protection
• ID locations
• In-Circuit Serial Programming™ (ICSP™)
9.1
Configuration Bits
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special configuration memory space (2000h – 3FFFh),
which can be accessed only during programming.
The PIC16F716 device has a Watchdog Timer, which
can be shut off only through configuration bits. It runs
off its own RC oscillator for added reliability. There are
two timers that offer necessary delays on power-up.
One is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is
stable. The other is the Power-up Timer (PWRT), which
provides a fixed delay on power-up only and is
designed to keep the part in Reset while the power
supply stabilizes. With these two timers on-chip, most
applications need no external Reset circuitry.
Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional information on special features is available
in the PICmicro® Mid-Range Reference Manual,
(DS33023).
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 55
PIC16F716
REGISTER 9-1:
CP
—
CONFIGURATION WORD
—
—
—
—
BORV
BOREN
—
—
PWRTE
WDTE
FOSC1 FOSC0
bit 13
bit 0
bit 13
CP: Flash Program Memory Code Protection bit
1 = Code protection off
0 = All program memory code protected
bit 12-8
Unimplemented: Read as ‘1’
bit 7
BORV: Brown-out Reset Voltage bit
1 = VBOR set to 4.0V
0 = VBOR set to 2.5V
bit 6
BOREN: Brown-out Reset Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 5-4
Unimplemented: Read as ‘1’
bit 3
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer (PWRTE).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = bit is set
‘0’ = bit is cleared
DS41206A-page 56
Preliminary
x = bit is unknown
 2003 Microchip Technology Inc.
PIC16F716
9.2
TABLE 9-1:
Oscillator Configurations
9.2.1
Ranges Tested:
OSCILLATOR TYPES
The PIC16F716 can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
LP - Low-power Crystal
XT - Crystal/Resonator
HS - High-speed Crystal/Resonator
RC - Resistor/Capacitor
9.2.2
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 9-1). The
PIC16F716 oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the
device can have an external clock source to drive the
OSC1/CLKIN pin (Figure 9-2).
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
C1(1)
OSC1
XTAL
RF(3)
Sleep
OSC2
RS(2)
C2(1)
Note 1:
2:
3:
Mode
XT
HS
Note 1:
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
FIGURE 9-1:
To
internal
logic
Freq
Osc Type
LP
XT
HS
Note 1:
OSC1 (C1)
OSC2 (C2)
455 kHz
68-100 pF
68-100 pF
2.0 MHz
15-68 pF
15-68 pF
4.0 MHz
10-68 pF
10-68 pF
8.0 MHz
15-68 pF
15-68 pF
16.0 MHz
10-22 pF
10-22 pF
These values are for design guidance
only. See notes at bottom of page.
TABLE 9-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
15-33 pF
32 kHz
15-33 pF
200 kHz
5-10 pF
5-10 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15-33 pF
15-33 pF
15-33 pF
4 MHz
15-33 pF
4 MHz
15-33 pF
15-33 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
These values are for design guidance only.
See notes at bottom of page.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
PIC16F716
See Table 9-1 and Table 9-2 for
recommended values of C1 and C2.
A series resistor (RS) may be required.
RF varies with the crystal chosen.
FIGURE 9-2:
CERAMIC RESONATORS
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: RS may be required to avoid overdriving
crystals with low drive level specification.
4: When using an external clock for the
OSC1 input, loading of the OSC2 pin
must be kept to a minimum by leaving the
OSC2 pin unconnected.
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
Clock from
ext. system
PIC16F716
Open
OSC2
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 57
PIC16F716
9.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 9-3 shows how the
R/C combination is connected to the PIC16F716.
FIGURE 9-3:
RC OSCILLATOR MODE
VDD
CEXT
Internal
clock
PIC16F716
VSS
FOSC/4
The PICmicro® microcontrollers have an MCLR noise
filter in the MCLR Reset path. The filter will detect and
ignore small pulses.
It should be noted that a WDT Reset does not drive the
MCLR pin low.
9.4
Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR,
just tie the MCLR pin directly (or through a resistor) to
VDD. This will eliminate external RC components
usually needed to create a Power-on Reset. A
maximum rise time for VDD is specified (parameter
D004). For a slow rise time, see Figure 9-4.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met. Brown-out Reset may be used to
meet the start-up conditions.
REXT
OSC1
A simplified block diagram of the On-chip Reset circuit
is shown in Figure 9-5.
OSC2/CLKOUT
FIGURE 9-4:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Recommended values:
3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
10 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
CEXT > 20 pF
9.3
VDD VDD
R
Reset
R1
MCLR
The PIC16F716 differentiates between various kinds of
Reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset (during normal operation)
WDT Wake-up (during Sleep)
Brown-out Reset (BOR)
C
Note 1:
2:
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brownout Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differently in different Reset situations as indicated in
Table 9-4. These bits are used in software to determine
the nature of the Reset. See Table 9-6 for a full
description of Reset states of all registers.
DS41206A-page 58
Preliminary
3:
PIC16F716
External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor quickly
when VDD powers down.
R < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR/VPP pin breakdown due
to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
 2003 Microchip Technology Inc.
PIC16F716
9.5
Power-up Timer (PWRT)
9.7
The Power-up Timer provides a fixed nominal time-out,
on power-up only, from the POR. The Power-up Timer
operates on an internal RC oscillator. The chip is kept
in Reset as long as the PWRT is active. The PWRT’s
time delay allows VDD to rise to an acceptable level.
The power-up timer enable configuration bit, PWRTE,
is provided to enable/disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See AC
parameters for details.
9.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized. See
AC parameters for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
Programmable Brown-Out Reset
(PBOR)
The PIC16F716 has on-chip Brown-out Reset circuitry.
A configuration bit, BOREN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset
circuitry.
The BORV configuration bit selects the programmable
Brown-out Reset threshold voltage (VBOR). When
BORV is 1, VBOR IS 4.0V. When BORV is 0, VBOR is
2.5V
A Brown-out Reset occurs when VDD falls below VBOR
for a time greater than parameter TBOR (see Table 12-4).
A Brown-out Reset is not guaranteed to occur if VDD falls
below VBOR for less than parameter TBOR.
On any Reset (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in Reset until VDD rises above
VBOR. The Power-up Timer will be invoked and will
keep the chip in Reset an additional 72 ms only if the
Power-up Timer enable bit in the configuration register
is set to 0 (PWRTE = 0).
If the Power-up Timer is enabled and VDD drops below
VBOR while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up
Timer will be re-initialized. Once VDD rises above VBOR,
the Power-up Timer will execute a 72 ms Reset. See
Figure 9-6.
For operations where the desired brown-out voltage is
other than 4.0V or 2.5V, an external brown-out circuit
must be used. Figure 9-8, Figure 9-9 and Figure 9-10
show examples of external Brown-out Protection
circuits.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 59
PIC16F716
FIGURE 9-5:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
Sleep
WDT
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
Chip_Reset
R
10-bit Ripple counter
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
PWRTE See Table 9-3 for time-out
situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
BROWN-OUT SITUATIONS (PWRTE = 0
FIGURE 9-6:
VDD
Internal
Reset
VBOR
72 ms
VDD
Internal
Reset
VBOR
<72 ms
72 ms
VDD
Internal
Reset
DS41206A-page 60
VBOR
72 ms
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 9-7:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
FIGURE 9-9:
VDD
VDD
33k
MCP809
Q1
10k
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
Vss
MCLR
bypass
capacitor
VDD
VDD
40k
RST
PIC16F716
MCLR
PIC16F716
Note 1: This circuit will activate Reset when VDD goes
below (Vz + 0.7V) where Vz = Zener voltage.
2: Internal Brown-out Reset circuitry should be
disabled when using this circuit.
FIGURE 9-8:
Note 1:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
This brown-out protection circuit employs
Microchip Technology’s MCP809
microcontroller supervisor. The MCP8XX and
MCP1XX families of supervisors provide
push-pull and open collector outputs with
both high and low active Reset pins. There
are 7 different trip point selections to
accommodate 5V and 3V systems.
VDD
R1
Q1
MCLR
R2
40k
PIC16F716
Note 1: This brown-out circuit is less expensive, albeit
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
R1
VDD x
= 0.7 V
R1 + R2
2: Internal Brown-out Reset should be disabled
when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 61
PIC16F716
9.8
Time-out Sequence
9.9
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-10,
Figure 9-11, and Figure 9-12 depict time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-12). This is useful for testing purposes or to
synchronize more than one PIC16F716 device
operating in parallel.
Table 9-5 shows the Reset conditions for some special
function registers, while Table 9-6 shows the Reset
conditions for all the registers.
TABLE 9-3:
Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON has two
bits.
Bit 0 is the Brown-out Reset Status bit, BOR. If the
BOREN configuration bit is set, BOR is ‘1’ on Power-on
Reset and reset to ‘0’ when a Brown-out condition
occurs. BOR must then be set by the user and checked
on subsequent resets to see if it is clear, indicating that
another Brown-out has occurred.
If the BOREN configuration bit is clear, BOR is
unknown on Power-on Reset.
Bit 1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
TIME-OUT IN VARIOUS SITUATIONS
Power-up or Brown-out
Oscillator Configuration
XT, HS, LP
Wake-up from Sleep
PWRTE = 0
PWRTE = 1
72 ms + 1024 TOSC
1024 TOSC
1024 TOSC
72 ms
—
—
RC
TABLE 9-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset (BOREN = 0)
0
1
1
1
Power-on Reset (BOREN = 1)
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during Sleep or interrupt wake-up from Sleep
DS41206A-page 62
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
TABLE 9-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
Status
Register
PCON
Register
Power-on Reset (BOREN = 0)
000h
0001 1xxx
---- --0x
Power-on Reset (BOREN = 1)
000h
0001 1xxx
---- --01
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during Sleep
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt wake-up from Sleep
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as ‘0’.
Note 1:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 63
PIC16F716
TABLE 9-6:
Register
W
INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16F716
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
N/A
N/A
N/A
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
0000h
0000h
PC + 1(2)
PCL
STATUS
0001 1xxx
000q quuu
(3)
uuuq quuu(3)
FSR
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(4), (5), (6)
--xx 0000
--xx 0000
--uu uuuu
PORTB(4), (5)
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
---0 0000
---0 0000
---u uuuu
INTCON
0000 -00x
0000 -00u
uuuu -uuu(1)
PIR1
-0-- -000
-0-- -000
-u-- -uuu(1)
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
--00 0000
--uu uuuu
--uu uuuu
TMR2
0000 0000
0000 0000
uuuu uuuu
T2CON
-000 0000
-000 0000
-uuu uuuu
CCPR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
0000 0000
0000 0000
uuuu uuuu
PWM1CON
0000 0000
0000 0000
uuuu uuuu
ECCPAS
00-0 0000
00-0 0000
u-uu uuuu
ADRES
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
0000 0000
0000 0000
uuuu uuuu
OPTION_REG
1111 1111
1111 1111
uuuu uuuu
TRISA
--11 1111
--11 1111
--uu uuuu
TRISB
1111 1111
1111 1111
uuuu uuuu
PIE1
-0-- -000
-0-- -000
-u-- -uuu
PCON
---- --qq
---- --uu
---- --uu
PR2
1111 1111
1111 1111
uuuu uuuu
ADCON1
---- -000
---- -000
---- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 9-5 for Reset value for specific condition.
4: On any device Reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
6: Output latches are unknown or unchanged. Analog inputs default to analog and read ‘0’.
DS41206A-page 64
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 9-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-11:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-12:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 65
PIC16F716
9.10
Interrupts
The peripheral interrupt flags are contained in the
special function registers, PIR1 and PIR2. The
corresponding interrupt enable bits are contained in
special function registers, PIE1 and PIE2, and the
peripheral interrupt enable bit is contained in special
function register, INTCON.
The PIC16F716 devices have up to 7 sources of
interrupt. The Interrupt Control Register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GIE bit.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables all un-masked interrupts when set, or disables
all interrupts when cleared. When bit GIE is enabled,
and an interrupt’s flag bit and mask bit are set, the
interrupt will vector immediately. Individual interrupts
can be disabled through their corresponding enable
bits in various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset and when an interrupt vector occurs.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
FIGURE 9-13:
INTERRUPT LOGIC
T0IF
T0IE
INTF
INTE
ADIF
ADIE
Wake-up (If in Sleep mode)
Interrupt to CPU
RBIF
RBIE
PEIE
CCP1IF
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
DS41206A-page 66
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
9.10.1
INT INTERRUPT
9.11
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake-up the processor from Sleep, if bit
INTE was set prior to going into Sleep. The status of
global interrupt enable bit GIE decides whether or not
the processor branches to the interrupt vector following
wake-up. See Section 9.13 “Power-down Mode
(Sleep)” for details on Sleep mode.
9.10.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0 “Timer0 Module”).
9.10.3
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, (i.e., W register and Status
register). This will have to be implemented in firmware.
Example 9-1 stores and restores the W, Status,
PCLATH and FSR registers. Context storage registers,
W_TEMP, STATUS_TEMP, PCLATH_TEMP and
FSR_TEMP, must be defined in Common RAM which
are those addresses between 70h-7Fh in Bank 0 and
between F0h-FFh in Bank 1.
The example:
a)
b)
c)
d)
e)
f)
Stores the W register.
Stores the Status register in Bank 0.
Stores the PCLATH register
Stores the FSR register.
Executes the interrupt service routine code
(User-generated).
Restores all saved registers in reverse order
from which they were stored
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2 “PORTB and the TRISB Register”).
EXAMPLE 9-1:
MOVWF
SWAPF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
RETFIE
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
W_TEMP
STATUS,W
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
FSR_TEMP,W
FSR
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;Restore FSR
;Move W into FSR
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Return from interrupt and enable GIE
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 67
PIC16F716
9.12
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip, RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run, even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device have been
stopped, for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the Status register
will be cleared upon a Watchdog Timer time-out.
FIGURE 9-14:
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 9.1 “Configuration
Bits”).
WDT time-out period values may be found in the
Electrical Specifications section under TWDT (parameter #31). Values for the WDT prescaler (actually a
postscaler, but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
Note:
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device Reset condition.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
.
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 4-2)
0
1
WDT Timer
Postscaler
M
U
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 4-2)
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
FIGURE 9-15:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bits 13:8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Config. bits
(1)
BORV(1)
BOREN(1)
—
—
PWRTE(1)
WDTE
FOSC1
FOSC0
81h
OPTION_REG
N/A
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend:
Note 1:
Shaded cells are not used by the Watchdog Timer.
See Register 9-1 for operation of these bits.
DS41206A-page 68
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
9.13
Power-down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low or high-impedance).
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
ECCP capture mode interrupt.
ADC running in ADRC mode.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
The MCLR pin must be at a logic high level (parameter
D042).
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the SLEEP
instruction.
9.13.1
9.13.2
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external
circuitry is drawing current from the I/O pin, powerdown the A/D and the disable external clocks. Pull all
I/O pins that are hi-impedance inputs, high or low
externally, to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The
contribution from on-chip pull-ups on PORTB should be
considered.
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or some
peripheral interrupts.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the Status register can be used to determine the
cause of device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 69
PIC16F716
FIGURE 9-16:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 3)
GIE bit
(INTCON<7>)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
Instruction
fetched Inst(PC) = Sleep
Instruction
executed Inst(PC - 1)
Note
9.14
1:
2:
3:
4:
PC+1
PC+2
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC Osc mode.
GIE = ‘1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ‘0’, execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
Program Verification/Code
Protection
9.16
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
9.15
PC+2
Inst(PC + 1)
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during program/verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
DS41206A-page 70
In-Circuit Serial Programming™
PIC16F716
microcontrollers
can
be
serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For complete details on serial programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Specification, (DS40245).
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
10.0
INSTRUCTION SET SUMMARY
Each PIC16F716 instruction is a 14-bit word divided
into an opcode which specifies the instruction type and
one or more operands which further specify the
operation of the instruction. The PIC16F716 instruction
set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations.
Table 10-1 shows the opcode field descriptions.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven bit constant or literal value.
TABLE 10-1:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
normal instruction execution time is 1 µs. If a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Table 10-2 lists the instructions recognized by the
MPASM™ assembler.
Figure 10-1 shows the three general formats that the
instructions can have.
Note 1: Any unused opcode is reserved. Use of
any reserved opcode may cause
unexpected operation.
OPCODE FIELD
DESCRIPTIONS
Field
2: To maintain upward compatibility with
future PICmicro products, do not use the
OPTION and TRIS instructions.
Description
All examples use the following format to represent a
hexadecimal number:
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip
software tools.
d
The instruction set is highly orthogonal and is grouped
into three basic categories:
0xhh
where h signifies a hexadecimal digit.
FIGURE 10-1:
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label
Label name
TOS
Top of Stack
PC
Program Counter
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7 6
OPCODE
d
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
PCLATH Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
dest
Destination either the W register or the specified register
file location
[ ]
Options
Bit-oriented file register operations
13
10 9
76
OPCODE
b (BIT #)
0
f (FILE #)
b = 3-bit address
f = 7-bit file register address
( )
Contents
Literal and control operations
→
Assigned to
General
<>
Register bit field
∈
In the set of
italics
User defined term (font is courier)
13
8 7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 71
PIC16F716
TABLE 10-2:
PIC16F716 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1(2)
1(2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note
1:
2:
3:
k
k
k
—
k
k
k
—
k
—
—
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the
pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data
will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the
Timer0 Module.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed
as a NOP.
DS41206A-page 72
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
10.1
Instruction Descriptions
ADDLW
Add Literal and W
Syntax:
[ label ] ADDLW
Operands:
ANDLW
AND Literal with W
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) + k → (W)
Operation:
(W) .AND. (k) → (W)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
11
Encoding:
11
Description:
The contents of the W register
are added to the eight bit literal
‘k’ and the result is placed in the
W register.
Description:
The contents of W register are
AND’ed with the eight bit literal
‘k’. The result is placed in the W
register.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ADDLW
Example
ANDLW
111x
k
kkkk
kkkk
0x15
Before Instruction
W = 0x10
After Instruction
W = 0x25
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Status Affected:
C, DC, Z
1001
k
kkkk
kkkk
0x5F
Before Instruction
W = 0xA3
After Instruction
W = 0x03
f,d
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .AND. (f) → (dest)
Status Affected:
Z
Encoding:
00
0101
f,d
dfff
ffff
Encoding:
00
Description:
Description:
Add the contents of the W
register with register ‘f’. If ‘d’ is 0
the result is stored in the W
register. If ‘d’ is 1 the result is
stored back in register ‘f’.
AND the W register with register
‘f’. If ‘d’ is 0 the result is stored in
the W register. If ‘d’ is 1 the
result is stored back in register
‘f’.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ANDWF
Example
ADDWF
0111
dfff
ffff
REG1, 0
Before Instruction
W
= 0x17
REG1 = 0xC2
After Instruction
W
= 0x17
REG1 = 0x02
Before Instruction
W
= 0x17
REG1 = 0xC2
After Instruction
W
= 0xD9
REG1 = 0xC2
Z
= 0
C
= 0
DC
= 0
 2003 Microchip Technology Inc.
REG1, 1
Preliminary
DS41206A-page 73
PIC16F716
BCF
Bit Clear f
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BCF
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
Description:
Bit ‘b’ in register ‘f’ is cleared.
Words:
1
Cycles:
1
Example
BCF
f,b
00bb
bfff
ffff
Encoding:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
1 → (f<b>)
Status Affected:
None
Encoding:
01
Description:
Bit ‘b’ in register ‘f’ is set.
Words:
1
Cycles:
1
Example
BSF
01bb
bfff
ffff
If bit ‘b’ in register ‘f’ is ‘0’ then the
next instruction is skipped.
If bit ‘b’ is ‘0’ then the next
instruction fetched during the
current instruction execution is
discarded, and a NOP is executed
instead, making this a two-cycle
instruction.
Words:
1
Cycles:
1(2)
Example
HERE
FALSE
TRUE
f,b
bfff
10bb
Description:
REG1, 7
Before Instruction
REG1 = 0xC7
After Instruction
REG1 = 0x47
01
ffff
BTFSC
GOTO
•
•
•
REG1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if REG<1> = 0,
PC = address TRUE
if REG<1>=1,
PC = address FALSE
REG1, 7
Before Instruction
REG1 = 0x0A
After Instruction
REG1 = 0x8A
DS41206A-page 74
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CALL k
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ k ≤ 2047
Operation:
Operation:
skip if (f<b>) = 1
Status Affected:
None
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Encoding:
01
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘1’ then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next
instruction fetched during the
current instruction execution, is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
Encoding:
10
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit
immediate address is loaded
into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle
instruction.
Words:
1
Cycles:
2
Example
HERE
Words:
1
Cycles:
1(2)
Example
HERE
FALSE
TRUE
11bb
BTFSS
GOTO
•
•
•
bfff
ffff
REG1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE
0kkk
CALL
kkkk
kkkk
THERE
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
CLRF
Syntax:
Clear f
[ label ] CLRF
Operands:
0 ≤ f ≤ 127
Operation:
00h → (f)
1→Z
f
Status Affected:
Z
Encoding:
00
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
Words:
1
Cycles:
1
Example
CLRF
0001
1fff
ffff
REG1
Before Instruction
REG1 = 0x5A
After Instruction
REG1 = 0x00
Z
= 1
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 75
PIC16F716
CLRW
Clear W
COMF
Complement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
00h → (W)
1→Z
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (dest)
Status Affected:
Z
Status Affected:
Z
Encoding:
00
Encoding:
00
Description:
W register is cleared. Zero bit
(Z) is set.
Description:
Words:
1
Cycles:
1
The contents of register ‘f’ are
complemented. If ‘d’ is 0 the
result is stored in W. If ‘d’ is 1
the result is stored back in
register ‘f’.
Example
CLRW
Words:
1
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z = 1
Cycles:
1
Example
COMF
CLRWDT
Clear Watchdog Timer
DECF
Syntax:
[ label ] CLRWDT
Operands:
None
Operands:
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (dest)
Status Affected:
Z
Status Affected:
TO, PD
Encoding:
Encoding:
00
Description:
0001
0000
0011
1001
f,d
dfff
ffff
REG1, 0
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
W
= 0xEC
Syntax:
Decrement f
[ label ] DECF f,d
00
0011
dfff
ffff
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
Decrement register ‘f’. If ‘d’ is 0
the result is stored in the W
register. If ‘d’ is 1 the result is
stored back in register ‘f’.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
DECF
Example
0000
0110
CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter =
WDT prescaler =
=
TO
=
PD
DS41206A-page 76
0100
0x00
0
1
1
Preliminary
CNT, 1
Before Instruction
CNT = 0x01
Z
= 0
After Instruction
CNT = 0x00
Z
= 1
 2003 Microchip Technology Inc.
PIC16F716
DECFSZ
Decrement f, Skip if 0
GOTO
Unconditional Branch
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 2047
Operation:
(f) - 1 → (dest);
0
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
10
00
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is 0 the result
is placed in the W register. If ‘d’
is 1 the result is placed back in
register ‘f’.
If the result is 0, the next
instruction, which is already
fetched, is discarded. A NOP is
executed instead making it a
two-cycle instruction.
Description:
GOTO is an unconditional
branch. The eleven-bit
immediate value is loaded into
PC bits <10:0>. The upper bits
of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
Words:
1
Cycles:
2
Example
GOTO THERE
Words:
1
Cycles:
1(2)
Example
HERE
1011
DECFSZ
GOTO
CONTINUE •
•
•
skip if result =
dfff
ffff
GOTO k
1kkk
kkkk
kkkk
After Instruction
PC = Address THERE
REG1, 1
LOOP
Before Instruction
PC
= address HERE
After Instruction
REG1 = REG1 - 1
if REG1 = 0,
PC = address CONTINUE
if REG1 ≠ 0,
PC
= address HERE+1
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 77
PIC16F716
INCF
Increment f
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (dest)
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Z
Status Affected:
None
Encoding:
00
Encoding:
00
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is 0 the result
is placed in the W register. If ‘d’
is 1 the result is placed back in
register ‘f’.
Description:
Words:
1
Cycles:
1
Example
INCF
The contents of register ‘f’ are
incremented. If ‘d’ is 0 the result
is placed in the W register. If ‘d’
is 1 the result is placed back in
register ‘f’.
If the result is 0, the next
instruction, which is already
fetched, is discarded. A NOP is
executed instead making it a
two-cycle instruction.
Words:
1
INCF f,d
1010
dfff
ffff
REG1, 1
Before Instruction
REG1 = 0xFF
Z
= 0
After Instruction
REG1 = 0x00
Z
= 1
INCFSZ f,d
1111
Cycles:
1(2)
Example
HERE
dfff
INCFSZ
GOTO
CONTINUE •
•
•
ffff
REG1, 1
LOOP
Before Instruction
PC
= address HERE
After Instruction
REG1 = REG1 + 1
if CNT = 0,
PC = address CONTINUE
if REG1≠ 0,
PC
= address HERE +1
DS41206A-page 78
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → (W)
Operation:
k → (W)
Status Affected:
Z
Status Affected:
None
Encoding:
11
Encoding:
11
Description:
The contents of the W register is
OR’ed with the eight bit literal ‘k’.
The result is placed in the W
register.
Description:
The eight bit literal ‘k’ is loaded
into W register. The don’t cares
will assemble as ‘0’s.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
MOVLW
Example
IORLW
IORLW k
1000
kkkk
kkkk
0x35
MOVLW k
00xx
kkkk
kkkk
0x5A
After Instruction
W = 0x5A
Before Instruction
W = 0x9A
After Instruction
W = 0xBF
Z = 0
IORWF
Inclusive OR W with f
MOVF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (dest)
Status Affected:
Z
Encoding:
00
Description:
The contents of register ‘f’ is
moved to a destination
dependent upon the status of
‘d’. If ‘d’ = 0, destination is W
register. If ‘d’ = 1, the destination
is file register ‘f’ itself. ‘d’ = 1 is
useful to test a file register since
status flag Z is affected.
Words:
1
Cycles:
1
Example
MOVF
IORWF
f,d
Operation:
(W) .OR. (f) → (dest)
Status Affected:
Z
Encoding:
00
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is 0 the result is
placed in the W register. If ‘d’ is
1 the result is placed back in
register ‘f’.
Words:
1
Cycles:
1
Example
IORWF
0100
dfff
REG1, 0
Before Instruction
REG1 = 0x13
W
= 0x91
After Instruction
REG1 = 0x13
W
= 0x93
Z
= 1
 2003 Microchip Technology Inc.
ffff
Move f
MOVF f,d
1000
dfff
ffff
REG1, 0
After Instruction
W= value in REG1 register
Z = 1
Preliminary
DS41206A-page 79
PIC16F716
MOVWF
Move W to f
OPTION
Load Option Register
Syntax:
[ label ]
Syntax:
[ label ]
0 ≤ f ≤ 127
Operands:
None
Operands:
Operation:
(W) → (f)
Operation:
(W) → OPTION
Status Affected:
None
Status Affected:
None
Encoding:
00
Encoding:
00
Description:
The contents of the W register are
loaded in the OPTION register.
This instruction is supported for
code compatibility with PIC16C5X
products. Since OPTION is a
readable/writable register, the
user can directly address it. Using
only register instruction such as
MOVWF.
Words:
1
Cycles:
1
MOVWF
0000
f
1fff
ffff
Description:
Move data from W register to
register ‘f’.
Words:
1
Cycles:
1
Example
MOVWF
REG1
Before Instruction
REG1 = 0xFF
W
= 0x4F
After Instruction
REG1 = 0x4F
W
= 0x4F
OPTION
0000
0110
0010
Example
To maintain upward compatibility with future PICmicro®
products, do not use this
instruction.
NOP
No Operation
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS → PC,
1 → GIE
Encoding:
00
Status Affected:
None
Description:
No operation.
Encoding:
00
Words:
1
Description:
Cycles:
1
Example
NOP
Return from Interrupt. Stack is
POPed and Top of Stack (TOS)
is loaded in the PC. Interrupts
are enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a
two-cycle instruction.
Words:
1
Cycles:
2
Example
RETFIE
NOP
0000
0xx0
0000
RETFIE
0000
0000
1001
After Interrupt
PC = TOS
GIE = 1
DS41206A-page 80
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
RETLW
Return with Literal in W
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k → (W);
TOS → PC
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Encoding:
11
Encoding:
00
Description:
The W register is loaded with
the eight bit literal ‘k’. The
program counter is loaded from
the top of the stack (the return
address). This is a two-cycle
instruction.
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is 0 the result
is placed in the W register. If ‘d’ is
1 the result is stored back in
register ‘f’.
Words:
1
Cycles:
2
Example
CALL TABLE;W contains table
;offset value
•
;W now has table value
•
•
ADDWF PC;W = offset
RETLW k1;Begin table
RETLW k2;
•
•
•
RETLW kn; End of table
TABLE
RETLW k
01xx
kkkk
kkkk
1
Cycles:
1
Example
RLF
f,d
1101
C
Words:
RLF
dfff
ffff
REGISTER F
REG1, 0
Before Instruction
REG1=1110 0110
C
= 0
After Instruction
REG1=1110 0110
W = 1100 1100
C
= 1
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN
Return from Subroutine
Syntax:
[ label ]
Operands:
None
Operation:
TOS → PC
Status Affected:
None
Encoding:
00
Description:
Return from subroutine. The
stack is POPed and the top of
the stack (TOS) is loaded into
the program counter. This is a
two-cycle instruction.
Words:
1
Cycles:
2
Example
RETURN
RETURN
0000
0000
1000
After Interrupt
PC = TOS
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 81
PIC16F716
RRF
Rotate Right f through Carry
SUBLW
Subtract W from Literal
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
k - (W) → (W)
Operation:
See description below
C, DC, Z
Status Affected:
C
Status
Affected:
Encoding:
00
Encoding:
11
Description:
The contents of register ‘f’ are
rotated one bit to the right
through the Carry Flag. If ‘d’ is 0
the result is placed in the W
register. If ‘d’ is 1 the result is
placed back in register ‘f’.
Description:
The W register is subtracted (2’s
complement method) from the eight
bit literal ‘k’. The result is placed in
the W register.
1100
C
Words:
1
Cycles:
1
Example
RRF
RRF f,d
dfff
ffff
REGISTER F
SUBLW k
110x
Words:
1
Cycles:
1
Example 1:
SUBLW
kkkk
kkkk
0x02
Before Instruction
W = 1
C = ?
REG1, 0
After Instruction
Before Instruction
REG1 = 1110 0110
C
= 0
After Instruction
REG1 = 1110 0110
W
= 0111 0011
C
= 0
W = 1
C = 1; result is positive
Example 2:
Before Instruction
W = 2
C = ?
After Instruction
W = 0
C = 1; result is zero
SLEEP
Example 3:
Syntax:
[ label ]
SLEEP
Operands:
None
Operation:
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
W =
C =
W =
C =
TO, PD
Encoding:
00
Description:
The power-down Status bit, PD
is cleared. Time out Status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator
stopped.
Words:
1
Cycles:
1
Example:
SLEEP
DS41206A-page 82
0110
3
?
After Instruction
Status Affected:
0000
Before Instruction
0xFF
0; result is negative
0011
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - (W) → (dest)
Operation:
Status
Affected:
C, DC, Z
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Status Affected:
None
Encoding:
00
Encoding:
00
Description:
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is 0
the result is stored in the W register.
If ‘d’ is 1 the result is stored back in
register ‘f’.
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
0 the result is placed in W
register. If ‘d’ is 1 the result is
placed in register ‘f’.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example 1:
SUBWF
Example
SWAPF
SUBWF f,d
0010
dfff
ffff
REG1, 1
Before Instruction
Example 2:
1
2
1; result is positive
0
1
After Instruction
Example 3:
TRIS
REG1 = 1
W
= 2
C
= ?
[ label ] TRIS
Operands:
5≤f≤6
Operation:
(W) → TRIS register f;
Status Affected:
None
Encoding:
00
Description:
The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and
writable, the user can directly
address them.
Words:
1
Cycles:
1
 2003 Microchip Technology Inc.
0000
f
0110
0fff
Example
After Instruction
=
=
=
=
Load TRIS Register
Syntax:
0
2
1; result is zero
DC = 1
Before Instruction
REG1
W
C
Z
REG1, 0
REG1 = 0xA5
W
= 0x5A
REG1 = 2
W
= 2
C
= ?
=
=
=
=
ffff
After Instruction
Before Instruction
REG1
W
C
Z
dfff
REG1 = 0xA5
After Instruction
=
=
=
=
=
1110
Before Instruction
REG1 = 3
W
= 2
C
= ?
REG1
W
C
Z
DC
SWAPF f,d
0xFF
2
0; result is negative
DC = 0
Preliminary
To maintain upward compatibility with future PICmicro®
products, do not use this
instruction.
DS41206A-page 83
PIC16F716
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (dest)
Status Affected:
Z
Encoding:
00
Description:
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
0 the result is stored in the W
register. If ‘d’ is 1 the result is
stored back in register ‘f’.
Words:
1
Cycles:
1
Example
XORWF
XORLW k
Operation:
(W) .XOR. k → (W)
Status Affected:
Z
Encoding:
11
Description:
The contents of the W register
are XOR’ed with the eight bit
literal ‘k’. The result is placed in
the W register.
1010
Words:
1
Cycles:
1
Example:
XORLW
kkkk
0xAF
Before Instruction
W = 0xB5
kkkk
XORWF
0110
f,d
dfff
ffff
REG1, 1
Before Instruction
After Instruction
REG1 = 0xAF
W
= 0xB5
W = 0x1A
After Instruction
REG1 = 0x1A
W
= 0xB5
DS41206A-page 84
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
11.0
DEVELOPMENT SUPPORT
11.1
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
- KEELOQ®
- PICDEM MSC
- microID®
- CAN
- PowerSmart®
- Analog
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
based application that contains:
• An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High level source code debugging
• Mouse over variable inspection
• Extensive on-line help
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
11.2
MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard hex
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 85
PIC16F716
11.3
MPLAB C17 and MPLAB C18
C Compilers
11.6
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
11.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from pre-compiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of pre-compiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
11.5
MPLAB C30 C Compiler
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been validated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, timekeeping, and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic
information for high level source debugging with the
MPLAB IDE.
DS41206A-page 86
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
11.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The
execution can be performed in Single-Step, Execute
Until Break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
11.8
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many commandline options and language extensions to take full
advantage of the dsPIC30F device hardware capabilities, and afford fine control of the compiler code
generator.
MPLAB ASM30 Assembler, Linker,
and Librarian
MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
11.9
MPLAB ICE 2000
High Performance Universal
In-Circuit Emulator
11.11 MPLAB ICD 2 In-Circuit Debugger
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
11.10 MPLAB ICE 4000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed performance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low cost, run-time development tool,
connecting to the host PC via an RS-232 or high speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
11.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-alone mode, the
PRO MATE II device programmer can read, verify, and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
11.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 87
PIC16F716
11.14 PICDEM 1 PICmicro
Demonstration Board
11.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device programmer, or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional application components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
11.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface, and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
11.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
DS41206A-page 88
11.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8-, 14-, and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts,
including LIN and Motor Control using ECCP. Special
provisions are made for low power operation with the
super capacitor circuit, and jumpers allow on-board
hardware to be disabled to eliminate current draw in
this mode. Included on the demo board are provisions
for Crystal, RC or Canned Oscillator modes, a five volt
regulator for use with a nine volt wall adapter or battery,
DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2,
2x16 liquid crystal display, PCB footprints for H-Bridge
motor driver, LIN transceiver and EEPROM. Also
included are: header for expansion, eight LEDs, four
potentiometers, three push buttons and a prototyping
area. Included with the kit is a PIC16F627A and a
PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
11.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
11.20 PICDEM 18R PIC18C601/801
Demonstration Board
11.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/De-multiplexed and 16-bit
memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
11.21 PICDEM LIN PIC16C43X
Demonstration Board
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus
communication.
11.22 PICkitTM 1 Flash Starter Kit
A complete "development system in a box", the PICkit
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation, and development
of 8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user's guide (on
CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB® IDE (Integrated Development Environment) software, software
and hardware "Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers" Handbook and a USB Interface
Cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
 2003 Microchip Technology Inc.
11.24 Evaluation and
Programming Tools
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
Preliminary
DS41206A-page 89
PIC16F716
NOTES:
DS41206A-page 90
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
12.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias......................................................................................................... .-55°C to +125°C
Storage temperature ........................................................................................................................... -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.3V to (VDD +0.3V)
Voltage on VDD with respect to VSS ...................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ...................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss ............................................................................................................ 0V to +8.5V
Total power dissipation (Note 1) (PDIP and SOIC)................................................................................................ 1.0W
Total power dissipation (Note 1) (SSOP) ............................................................................................................. 0.65W
Maximum current out of VSS pin ........................................................................................................................ 300 mA
Maximum current into VDD pin ........................................................................................................................... 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA
Maximum output current sunk by any I/O pin....................................................................................................... 25 mA
Maximum output current sourced by any I/O pin ................................................................................................. 25 mA
Maximum current sunk by PORTA and PORTB (combined).............................................................................. 200 mA
Maximum current sourced by PORTA and PORTB (combined) ........................................................................ 200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 91
PIC16F716
PIC16F716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +85°C(1)
FIGURE 12-1:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
PIC16F716 VOLTAGE-FREQUENCY GRAPH, 85°C < TA < +125°C(1)
FIGURE 12-2:
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1:
The shaded region indicates the permissible combinations of voltage and frequency.
DS41206A-page 92
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
12.1
DC Characteristics: PIC16F716 (Industrial, Extended)
DC CHARACTERISTICS
Param
No.
Sym
VDD
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Min
Typ†
Max Units
Conditions
2.0
3.0
—
—
5.5
5.5
V
V
—
1.5*
—
V
—
Vss
—
V
0.05
TBD
—
—
—
—
3.65
4.0
4.35
V
BOREN bit set, BOR bit = ‘1’
TBD
2.5
TBD
V
BOREN bit set, BOR bit = ‘0’
Supply Voltage
D001
D001A
RAM Data Retention
Voltage(1)
D002*
VDR
D003
VPOR VDD Start Voltage to ensure
internal Power-on Reset signal
D004* SVDD VDD Rise Rate to ensure
D004A*
internal Power-on Reset signal
Industrial
Extended
See section on Power-on Reset for
details
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for
details
VBOR Brown-out Reset voltage trip
point
D005
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 93
PIC16F716
12.2
DC Characteristics: PIC16F716 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C
DC CHARACTERISTICS
Para
m No.
Sym
VDD
Characteristic
2.0
—
—
—
Max Units
VDD
Conditions
5.5
V
—
0.1
0.8
µA
2.0
0.1
0.85
µA
3.0
—
0.2
2.7
µA
5.0
—
1
2.0
µA
2.0
—
2
3.5
µA
3.0
—
9
13.5
µA
5.0
—
TBD
TBD
µA
3.0
—
40
TBD
µA
4.5
—
45
TBD
µA
5.0
—
1.8
TBD
µA
2.0
—
2.6
TBD
µA
3.0
—
3.0
TBD
µA
5.0
—
14
17
µA
2.0
—
23
28
µA
3.0
Power-down Base Current
D020
∆IMOD Peripheral Module Current
D021
D022
D025
IDD
Typ†
Supply Voltage
D001
IPD
Min
WDT, BOR and T1OSC:
disabled
(1)
WDT Current
BOR Current
T1OSC Current
Supply Current
D010
D011
D012
D013
—
45
60
µA
5.0
—
120
160
µA
2.0
—
180
250
µA
3.0
—
290
370
µA
5.0
—
220
300
µA
2.0
—
350
470
µA
3.0
—
600
780
µA
5.0
—
2.1
2.9
mA
4.5
—
2.5
3.3
mA
5.0
FOSC = 32 kHz
LP Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 20 MHz
HS Oscillator mode
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
2: ADC on, not converting.
DS41206A-page 94
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
12.3
DC Characteristics: PIC16F716 (Extended)
DC CHARACTERISTICS
Param
No.
Sym
VDD
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Characteristic
Typ† Max Units
VDD
Conditions
Supply Voltage
D001
IPD
Min
3.0
—
5.5
V
—
—
0.1
TBD
µA
3.0
—
0.2
TBD
µA
5.0
—
2
TBD
µA
3.0
9
TBD
µA
5.0
TBD TBD
µA
3.0
Power-down Base Current
D020E
WDT, BOR and T1OSC: disabled
∆IMOD Peripheral Module Current(1)
D021E
—
—
D022E
D025E
IDD
—
40
TBD
µA
4.5
—
45
TBD
µA
5.0
—
2.6
TBD
µA
3.0
—
3.0
TBD
µA
5.0
—
21
TBD
µA
3.0
WDT Current
BOR Current
T1OSC Current
Supply Current
D010E
D011E
D012E
D013E
—
38
TBD
µA
5.0
—
182
TBD
µA
3.0
—
293
TBD
µA
5.0
—
371
TBD
µA
3.0
—
668
TBD
µA
5.0
—
2.6
TBD
mA
4.5
—
3
TBD
mA
5.0
FOSC = 32 kHz
LP Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 20 MHz
HS Oscillator mode
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
2: ADC on, not converting.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 95
PIC16F716
12.4
DC Characteristics: PIC16F716 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics: PIC16F716 (Industrial, Extended)”.
DC CHARACTERISTICS
Param
No.
Sym
VIL
D030
D030A
D031
D032
D033
VIH
D040
D040A
D041
D042
D042A
D043
D060
IIL
D061
D063
D070
IPURB
D080
VOL
D083
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in HS mode)
OSC1 (in XT and LP modes)
Input High Voltage
I/O ports
with TTL buffer
Min
Typ†
Max
Units
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.8
0.15 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.6
V
V
V
V
V
V
—
—
—
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
otherwise
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP modes)
OSC1 (in RC mode)
2.0
0.25 VDD +
0.8V
0.8 VDD
0.8 VDD
0.7 VDD
0.9 VDD
Input Leakage Current(2), (3)
I/O ports
—
—
±1
µA
—
—
±500
nA
MCLR, RA4/T0CKI
OSC1/CLKIN
—
—
—
—
±5
±5
µA
µA
PORTB weak pull-up current
Output Low Voltage
I/O ports
50
250
400
µA
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
VDD-0.7
—
—
V
VDD-0.7
—
—
V
VDD-0.7
—
—
V
VDD-0.7
—
—
V
OSC2/CLKOUT (RC Osc mode)
Conditions
4.5V ≤ VDD ≤ 5.5V
otherwise
(Note1)
(Note1)
Vss ≤ VPIN ≤ VDD, Pin at
high-impedance
Vss ≤ VPIN ≤ VDD, Pin configured as
analog input
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
modes
VDD = 5V, VPIN = VSS
IOL = 8.5 mA, VDD = 4.5V, -40°C to
+85°C
IOL = 7.0 mA, VDD = 4.5V, -40°C to
+125°C
IOL = 1.6 mA, VDD = 4.5V, -40°C to
+85°C
IOL = 1.2 mA, VDD = 4.5V, -40°C to
+125°C
Output High Voltage
D090
VOH
D092
D150*
Note
I/O ports(3)
OSC2/CLKOUT (RC Osc mode)
IOH = -3.0 mA, VDD = 4.5V, -40°C to
+85°C
IOH = -2.5 mA, VDD = 4.5V, -40°C to
+125°C
IOH = -1.3 mA, VDD = 4.5V, -40°C to
+85°C
IOH = -1.0 mA, VDD = 4.5V, -40°C to
+125°C
RA4 pin
Open-Drain High Voltage
—
—
8.5
V
VOD
These parameters are characterized but not tested.
Data in “Type” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with
external clock in RC mode.
2:
The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3:
Negative current is defined as current sourced by the pin.
*
†
1:
DS41206A-page 96
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics: PIC16F716 (Industrial, Extended)”.
DC CHARACTERISTICS
Param
No.
Sym
Note
Min
Typ†
Max
Units
Conditions
—
15
pF
In XT, HS and LP modes when external
clock is used to drive OSC1.
Capacitive Loading Specs on Output Pins
COSC2 OSC2/CLKOUT pin
—
D100
D101
Characteristic
All I/O pins and OSC2 (in RC mode)
—
—
50
pF
CIO
These parameters are characterized but not tested.
Data in “Type” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with
external clock in RC mode.
2:
The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3:
Negative current is defined as current sourced by the pin.
*
†
1:
12.5
12.5.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
 2003 Microchip Technology Inc.
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
Preliminary
DS41206A-page 97
PIC16F716
12.5.2
TIMING CONDITIONS
The temperature and voltages specified in Table 12-1
apply to all timing specifications, unless otherwise
noted. Figure 12-3 specifies the load conditions for the
timing specifications.
TABLE 12-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
AC CHARACTERISTICS
FIGURE 12-3:
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics:
PIC16F716 (Industrial, Extended)”. LC parts operate for commercial/industrial
temp’s only.
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 2
Load condition 1
VDD/2
Rl
Cl
Pin
VSS
Cl
Pin
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
15 pF for OSC2 output
12.5.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 12-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
DS41206A-page 98
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
TABLE 12-2:
Param
No.
Sym
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
Units
Conditions
Ext. Clock Input Frequency(1)
DC
—
4
MHz RC and XT Osc modes
DC
—
20
MHz HS Osc mode
DC
—
200
kHz LP Osc mode
(1)
Oscillator Frequency
DC
—
4
MHz RC Osc mode
0.1
—
4
MHz XT Osc mode
4
—
20
MHz HS Osc mode
5
—
200
kHz LP Osc mode
1
TOSC External CLKIN Period(1)
250
—
—
ns RC and XT Osc modes
50
—
—
ns HS Osc mode
5
—
—
µs LP Osc mode
Oscillator Period(1)
250
—
—
ns RC Osc mode
250
—
10,000
ns XT Osc mode
50
—
250
ns HS Osc mode
5
—
—
µs LP Osc mode
2
Tcy
Instruction Cycle Time(1)
200
—
DC
ns TCY = 4/FOSC
3*
TosL, External Clock in (OSC1) High or 100
—
—
ns XT oscillator
TosH Low Time
2.5
—
—
µs LP oscillator
15
—
—
ns HS oscillator
4*
TosR, External Clock in (OSC1) Rise or —
—
25
ns XT oscillator
TosF Fall Time
—
—
50
ns LP oscillator
—
—
15
ns HS oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at "min."
values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
1A
FOSC
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 99
PIC16F716
FIGURE 12-5:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note 1:
Refer to Figure 12-3 for load conditions.
TABLE 12-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ
†
Max
Units Conditions
10*
TOSH2CKL
OSC1↑ to CLKOUT↓
—
75
200
ns
(Note 1)
11*
TOSH2CKH OSC1↑ to CLKOUT↑
—
75
200
ns
(Note 1)
12*
TCKR
CLKOUT rise time
—
35
100
ns
(Note 1)
13*
TCKF
CLKOUT fall time
—
35
100
ns
(Note 1)
—
—
20
ns
(Note 1)
TOSC +
200
—
—
ns
(Note 1)
(Note 1)
14*
TCKL2IOV
CLKOUT ↓ to Port out valid
15*
TIOV2CKH
Port input valid before CLKOUT ↑
16*
TCKH2IOI
Port input hold after CLKOUT ↑
0
—
—
ns
17*
TOSH2IOV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18*
TOSH2IOI
OSC1↑ (Q2 cycle) to Port
input invalid (I/O in hold
time)
18A*
Standard
100
—
—
ns
Extended (LC)
200
—
—
ns
19*
TIOV2OSH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TIOR
Port output rise time
Standard
—
10
40
ns
Extended (LC)
—
—
80
ns
TIOF
Port output fall time
Standard
—
10
40
ns
—
—
80
ns
22††*
TINP
INT pin high or low time
Tcy
—
—
ns
23††*
TRBP
RB7:RB4 change INT high or low time
Tcy
—
—
ns
20A*
21*
21A*
Extended (LC)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS41206A-page 100
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 12-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING(1)
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note 1:
Refer to Figure 12-3 for load conditions.
FIGURE 12-7:
BROWN-OUT RESET TIMING
BVDD
VDD
TABLE 12-4:
Param
No.
Sym
35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Characteristic
Min
Typ†
Max Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +125°C
31*
TWDT
Watchdog Timer Time-out Period
7
18
33
ms
VDD = 5V, -40°C to +85°C
TBD
TBD
TBD
ms
VDD = 5V, +85°C to +125°C
32
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
TPWRT
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +85°C
TBD
TBD
TBD
ms
VDD = 5V, +85°C to +125°C
34
TIOZ
I/O high-impedance from MCLR
Low or WDT Reset
—
—
2.1
µs
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
(No Prescaler)
35
VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 101
PIC16F716
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS(1)
FIGURE 12-8:
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note 1:
Refer to Figure 12-3 for load conditions.
TABLE 12-5:
Param
No.
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
41*
Tt0L
T0CKI Low Pulse Width
42*
Tt0P
T0CKI Period
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
T1CKI High Time Synchronous, Prescaler = 1
Synchronous, Standard
Prescaler =
2,4,8
Asynchronous Standard
T1CKI Low Time Synchronous, Prescaler = 1
Synchronous, Standard
Prescaler =
2,4,8
Asynchronous Standard
T1CKI input
Synchronous Standard
period
Min
Typ†
Max
Units
Conditions
0.5TCY + 20
10
0.5TCY + 20
10
TCY + 40
Greater of:
20 or TCY + 40
N
0.5TCY + 20
15
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
—
—
—
—
ns
ns
N = prescale
value
(2, 4,..., 256)
Must also meet
parameter 47
30
0.5TCY + 20
15
—
—
—
—
—
—
ns
ns
ns
Must also meet
parameter 47
30
Greater of:
30 OR TCY + 40
N
60
32.768
—
—
—
—
ns
ns
Must also meet
parameter 42
Must also meet
parameter 42
45*
Tt1H
46*
Tt1L
47*
Tt1P
48*
Asynchronous Standard
—
—
ns
Timer1 oscillator input frequency range
— 32.768 kHz
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
— 7Tosc
—
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Ft1
DS41206A-page 102
Preliminary
N = prescale
value (1, 2, 4, 8)
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 12-9:
CAPTURE/COMPARE/PWM TIMINGS(1)
CCP1
(Capture Mode)
50
51
52
CCP1
(Compare or PWM Mode)
53
Note 1:
Refer to Figure 12-3 for load conditions.
TABLE 12-6:
CAPTURE/COMPARE/PWM REQUIREMENTS
Param
Sym
No.
50*
51*
TccL CCP1 input low
time
Characteristic
Min
—
—
ns
10
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
3TCY + 40
N
—
—
ns
Standard
—
10
40
ns
Extended
—
—
80
ns
Standard
—
10
40
ns
Extended
—
—
80
ns
With Prescaler Standard
TccH CCP1 input high No Prescaler
time
With Prescaler Standard
TccP CCP1 input period
53*
TccR CCP1 output rise time
53A*
TccF CCP1 output fall time
54A*
Typ
Max Units
†
0.5TCY + 20
No Prescaler
52*
54*
54
Conditions
N = prescale
value (1,4, or
16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 103
PIC16F716
TABLE 12-7:
Para
m
No.
A/D CONVERTER CHARACTERISTICS: PIC16F716 (INDUSTRIAL, EXTENDED)
Sym
Characteristic
A00
VDD VDD Operation
A01
NR
A02
Resolution
EABS Total Absolute error
Min
Typ†
Max
Units
Conditions
2.5
—
5.5
V
—
—
8-bits
bit
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03
EIL
Integral linearity error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05
EFS
Full scale error
—
—
<±1
LSb VREF = VDD= 5.12V,
VSS ≤ VAIN ≤ VREF
A06
EOFF Offset error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
Monotonicity
—
guaranteed(3)
—
—
A20
VREF Reference voltage
2.5V
—
VDD + 0.3
V
A25
VAIN Analog input voltage
VSS 0.3
—
VREF +
0.3
V
A30
ZAIN Recommended impedance of
analog voltage source
—
—
10.0
kΩ
A40
IAD
—
180
—
µA
Average current
consumption when
A/D is on.(1)
A50
IREF VREF input current(2)
10
—
1000
µA
—
—
10
µA
During VAIN
acquisition.
Based on differential
of VHOLD to VAIN to
charge CHOLD, see
Section 12.1 “DC
Characteristics:
PIC16F716 (Industrial, Extended)”.
During A/D
Conversion cycle
A10
—
A/D conversion
current (VDD)
Standard
VSS ≤ VAIN ≤ VREF
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
DS41206A-page 104
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
FIGURE 12-10:
A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 Tcy
(TOSC/2)(1)
131
Q4
130
A/D CLK
132
7
A/D DATA
6
5
4
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note
1:
TABLE 12-8:
Param
No.
Sym
130
TAD
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
A/D CONVERSION REQUIREMENTS
Characteristic
A/D clock period
Min
Typ†
Max
Units
Conditions
Industrial
1.6
—
—
µs
TOSC based, VREF ≥ 3.0V
Industrial
1.6
4.0
6.0
µs
A/D RC mode
Extended
1.6
—
—
µs
TOSC based, VREF ≥ 3.0V
Extended
1.6
6.0
9.0
µs
A/D RC mode
131
TCNV Conversion time (not including S/H time)(1)
132
TACQ Acquisition time
134
TGO
135
TSWC Switching from convert → sample time
Q4 to A/D clock start
9.5
—
9.5
TAD
(Note 2)
20
—
µs
5*
—
—
µs
The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
—
TOSC/2 **
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
1.5 **
—
—
TAD
* These parameters are characterized but not tested.
** This specification ensured by design.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” for min. conditions.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 105
PIC16F716
NOTES:
DS41206A-page 106
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
13.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are
outside specified operating range (i.e., outside
specified VDD range). This is for information only and
devices will operate properly only within the specified
range.
The data presented in this section is a statistical
summary of data collected on units from different lots
over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C. 'Max' or
'min' represents (mean + 3σ) or (mean - 3σ)
respectively, where σ is standard deviation, over the
whole temperature range.
Graphs and Tables not available at this
time.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 107
PIC16F716
NOTES:
DS41206A-page 108
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
14.0
PACKAGING INFORMATION
14.1
Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
18-Lead SOIC
PIC16F716-04/P
0023CBA
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
20-Lead SSOP
PIC16F716
-20/SO
0018CDK
Example
PIC16F716
-20I/SS025
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
Note:
*
0020CBK
Customer specific information*
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 109
PIC16F716
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
α
1
E
A2
A
L
c
A1
B1
β
p
B
eB
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
18
.100
.155
.130
MAX
MILLIMETERS
NOM
18
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
22.61
22.80
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.890
.898
.905
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
§
eB
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
DS41206A-page 110
Preliminary
MAX
4.32
3.68
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
15
 2003 Microchip Technology Inc.
PIC16F716
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.093
.088
.004
.394
.291
.446
.010
.016
0
.009
.014
0
0
A1
INCHES*
NOM
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
.011
.017
12
12
MAX
.104
.094
.012
.420
.299
.462
.029
.050
8
.012
.020
15
15
MILLIMETERS
NOM
18
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.39
7.49
11.33
11.53
0.25
0.50
0.41
0.84
0
4
0.23
0.27
0.36
0.42
0
12
0
12
MIN
MAX
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
0.30
0.51
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 111
PIC16F716
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Lead Thickness
Foot Angle
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
c
φ
B
α
β
MIN
.068
.064
.002
.299
.201
.278
.022
.004
0
.010
0
0
INCHES*
NOM
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
.013
5
5
MAX
.078
.072
.010
.322
.212
.289
.037
.010
8
.015
10
10
MILLIMETERS
NOM
20
0.65
1.73
1.85
1.63
1.73
0.05
0.15
7.59
7.85
5.11
5.25
7.06
7.20
0.56
0.75
0.10
0.18
0.00
101.60
0.25
0.32
0
5
0
5
MIN
MAX
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS41206A-page 112
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
APPENDIX A:
REVISION HISTORY
APPENDIX B:
Revision A (June 2003)
Original data sheet. However, the device described in
this data sheet are upgrades to PIC16C716.
 2003 Microchip Technology Inc.
CONVERSION
CONSIDERATIONS
This is a Flash program memory version of the
PIC16C716 device. Refer to the migration document,
DS40059, for more information about differences
between the PIC16F716 and PIC16C716.
Preliminary
DS41206A-page 113
PIC16F716
APPENDIX C:
MIGRATION FROM
BASE-LINE TO
MID-RANGE DEVICES
To convert code written for PIC16C5X to PIC16F716,
the user should take the following steps:
1.
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16F716).
2.
The following are the list of modifications over the
PIC16C5X microcontroller family:
3.
1.
4.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
register file (128 bytes now versus 32 bytes
before).
A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from Status register.
Data memory paging is redefined slightly.
Status register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for
compatibility with PIC16C5X.
OPTION_REG and TRIS registers are made
addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
Reset vector is changed to 0000h.
Reset of all registers is revisited. Five different
Reset (and wake-up) types are recognized.
Registers are reset differently.
Wake-up from Sleep through interrupt is added.
Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt-onchange feature.
T0CKI pin is also a port pin (RA4) now.
FSR is made a full eight bit register.
“In-circuit serial programming” is made possible.
The user can program PIC16F716 devices
using only five pins: VDD, VSS, MCLR/VPP, RB6
(clock) and RB7 (data in/out).
PCON status register is added with a Power-on
Reset Status bit (POR).
Brown-out protection circuitry has been added.
Controlled by configuration word bits BOREN
and BORV. Brown-out Reset ensures the device
is placed in a Reset condition if VDD dips below
a fixed setpoint.
DS41206A-page 114
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to Status, Option, and FSR
registers since these have changed.
Change Reset vector to 0000h
5.
.
Note 1: This device has been designed to
perform to the parameters of its data
sheet. It has been tested to an electrical
specification designed to determine its
conformance with these parameters. Due
to process differences in the manufacture
of this device, this device may have different performance characteristics than its
earlier version. These differences may
cause this device to perform differently in
your application than the earlier version of
this device.
Preliminary
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may be
required.
 2003 Microchip Technology Inc.
PIC16F716
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 115
PIC16F716
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Application (optional):
Would you like a reply?
Device: PIC16F716
Y
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Literature Number: DS41206A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41206A-page 116
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
INDEX
A
A/D ...................................................................................... 49
A/D Converter Enable (ADIE Bit) ................................ 14
A/D Converter Flag (ADIF Bit) .............................. 15, 50
A/D Converter Interrupt, Configuring .......................... 50
ADCON0 Register................................................... 9, 49
ADCON1 Register................................................. 10, 50
ADRES Register ........................................................... 9
Analog Port Pins, Configuring..................................... 52
Channel Select (CHS2:CHS0 Bits) ............................. 49
Clock Select (ADCS1:ADCS0 Bits)............................. 49
Configuring the Module............................................... 50
Conversion Clock (Tad) .............................................. 52
Conversion Status (GO/DONE Bit) ....................... 49, 50
Conversions ................................................................ 53
Converter Characteristics ......................................... 104
Module On/Off (ADON Bit).......................................... 49
Port Configuration Control (PCFG2:PCFG0 Bits) ....... 50
Sampling Requirements.............................................. 51
Special Event Trigger (CCP)................................. 35, 53
Timing Diagram......................................................... 105
Absolute Maximum Ratings ................................................ 91
ADCON0 Register................................................................. 9
ADCON1 Register............................................................... 10
ADDLW Instruction ............................................................. 73
ADDWF Instruction ............................................................. 73
ADRES Register ................................................................... 9
Analog Input Model ............................................................. 51
Analog-to-Digital Converter. See A/D
ANDLW Instruction ............................................................. 73
ANDWF Instruction ............................................................. 73
Assembler
MPASM Assembler..................................................... 85
B
Banking, Data Memory ................................................... 7, 11
BCF Instruction ................................................................... 74
Block Diagrams
A/D .............................................................................. 51
Capture (CCP Module) ............................................... 34
Compare (CCP Module) ............................................. 35
Interrupt Sources ........................................................ 65
On-Chip Reset Circuit ................................................. 60
PIC16F716.................................................................... 5
PORTA.................................................................. 19, 20
PORTB........................................................................ 21
PWM (CCP Module) ................................................... 36
PWM (Enhanced)........................................................ 38
RB1/T1OSO/T1CKI..................................................... 22
RB2/T1OSI.................................................................. 22
RB3/CCP1/P1A........................................................... 23
RB4 ............................................................................. 23
RB5 ............................................................................. 24
RB6/P1C ..................................................................... 24
RB7/P1D ..................................................................... 25
Timer0......................................................................... 27
Timer0/WDT Prescaler ............................................... 28
Timer1......................................................................... 30
Timer2......................................................................... 32
Watchdog Timer (WDT) .............................................. 67
BOR. See Brown-out Reset
Brown-out Detect (BOD) ..................................................... 59
Brown-out Reset (BOR) .................................... 55, 58, 62, 63
 2003 Microchip Technology Inc.
BOR Enable (BODEN Bit) .......................................... 56
BOR Status (BOR Bit) ................................................ 16
Timing Diagram ........................................................ 101
BSF Instruction ................................................................... 74
BTFSC Instruction .............................................................. 74
BTFSS Instruction............................................................... 75
C
C Compilers
MPLAB C17................................................................ 86
MPLAB C18................................................................ 86
MPLAB C30................................................................ 86
CALL Instruction ................................................................. 75
Capture (CCP Module) ....................................................... 34
CCP Pin Configuration ............................................... 34
CCPR1H:CCPR1L Registers ..................................... 34
Software Interrupt ....................................................... 34
Timer1 Mode Selection............................................... 34
Capture/Compare/PWM (CCP) .......................................... 33
Capture Mode. See Capture
CCP1CON Register...................................................... 9
CCPR1H Register .................................................. 9, 33
CCPR1L Register ................................................... 9, 33
Compare Mode. See Compare
Enable (CCP1IE Bit)................................................... 14
Flag (CCP1IF Bit) ....................................................... 15
PWM Mode. See PWM
Timer Resources ........................................................ 33
Timing Diagram ........................................................ 103
CLRF Instruction................................................................. 75
CLRW Instruction................................................................ 76
CLRWDT Instruction........................................................... 76
Code Examples
Capture (CCP Module)
Changing Between Capture Prescalers ............. 34
How to Clear RAM Using Indirect Addressing............ 18
Initializing PORTA ...................................................... 19
Initializing PORTB ...................................................... 21
Code Protection ............................................................ 55, 69
CP1:CP0 Bits.............................................................. 56
COMF Instruction................................................................ 76
Compare (CCP Module) ..................................................... 34
CCP Pin Configuration ............................................... 35
Software Interrupt ....................................................... 35
Special Event Trigger ..................................... 30, 35, 53
Timer1 Mode Selection............................................... 35
Configuration Bits ............................................................... 55
Conversion Considerations............................................... 113
D
Data Memory ........................................................................ 7
Bank Select (RP1:RP0 Bits) ................................... 7, 11
General Purpose Registers .......................................... 8
Register File Map ......................................................... 8
Special Function Registers........................................... 9
DC Characteristics............................................ 93, 94, 95, 96
DECF Instruction ................................................................ 76
DECFSZ Instruction............................................................ 77
Demonstration Boards
PICDEM 1................................................................... 88
PICDEM 17................................................................. 88
PICDEM 18R PIC18C601/801 ................................... 89
PICDEM 2 Plus........................................................... 88
PICDEM 3 PIC16C92X............................................... 88
Preliminary
DS41206A-page 117
PIC16F716
PICDEM 4 ................................................................... 88
PICDEM LIN PIC16C43X ........................................... 89
PICDEM USB PIC16C7X5.......................................... 89
PICDEM.net Internet/Ethernet .................................... 88
Development Support ......................................................... 85
Direct Addressing................................................................ 18
E
ECCP
Auto-Shutdown ........................................................... 45
and Automatic Restart ........................................ 47
Start-up Considerations .............................................. 47
Electrical Characteristics..................................................... 91
Enhanced Capture/Compare/PWM (ECCP)
PWM Mode. See PWM (ECCP Module)
Enhanced CCP Auto-Shutdown.......................................... 45
Enhanced PWM Mode. See PWM (ECCP Module)............ 38
Errata .................................................................................... 3
Evaluation and Programming Tools .................................... 89
External Power-on Reset Circuit ......................................... 58
G
GOTO Instruction ................................................................ 77
I
I/O Ports .............................................................................. 19
ID Locations .................................................................. 55, 69
INCF Instruction .................................................................. 78
INCFSZ Instruction.............................................................. 78
In-Circuit Serial Programming (ICSP) ........................... 55, 69
Indirect Addressing ............................................................. 18
FSR Register ...................................................... 8, 9, 18
INDF Register ............................................................... 9
Instruction Set
ADDLW ....................................................................... 73
ADDWF ....................................................................... 73
ANDLW ....................................................................... 73
ANDWF ....................................................................... 73
BCF ............................................................................. 74
BSF ............................................................................. 74
BTFSC ........................................................................ 74
BTFSS ........................................................................ 75
CALL ........................................................................... 75
CLRF........................................................................... 75
CLRW ......................................................................... 76
CLRWDT..................................................................... 76
COMF ......................................................................... 76
DECF .......................................................................... 76
DECFSZ...................................................................... 77
GOTO ......................................................................... 77
INCF............................................................................ 78
INCFSZ ....................................................................... 78
IORLW ........................................................................ 79
IORWF ........................................................................ 79
MOVF.......................................................................... 79
MOVLW ...................................................................... 79
MOVWF ...................................................................... 80
NOP ............................................................................ 80
OPTION ...................................................................... 80
RETFIE ....................................................................... 80
RETLW ....................................................................... 81
RETURN ..................................................................... 81
RLF ............................................................................. 81
RRF............................................................................. 82
SLEEP ........................................................................ 82
SUBLW ....................................................................... 82
DS41206A-page 118
SUBWF....................................................................... 83
SWAPF ....................................................................... 83
TRIS ........................................................................... 83
XORLW ...................................................................... 84
XORWF ...................................................................... 84
Instruction Set Summary .................................................... 71
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON Register............................................................ 9, 13
GIE Bit ........................................................................ 13
INTE Bit ...................................................................... 13
INTF Bit ...................................................................... 13
PEIE Bit ...................................................................... 13
RBIE Bit ...................................................................... 13
RBIF Bit ...................................................................... 13
T0IE Bit ....................................................................... 13
T0IF Bit ....................................................................... 13
Interrupt Sources .......................................................... 55, 65
A/D Conversion Complete .......................................... 50
Capture Complete (CCP)............................................ 34
Compare Complete (CCP).......................................... 35
Interrupt-on-Change (RB7:RB4 ) ................................ 21
RB0/INT Pin, External................................................. 66
TMR0 Overflow..................................................... 28, 66
TMR1 Overflow..................................................... 29, 30
TMR2 to PR2 Match ................................................... 32
TMR2 to PR2 Match (PWM) ................................. 31, 36
Interrupts, Context Saving During....................................... 66
Interrupts, Enable Bits
A/D Converter Enable (ADIE Bit)................................ 14
CCP1 Enable (CCP1IE Bit) .................................. 14, 34
Global Interrupt Enable (GIE Bit) .......................... 13, 65
Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit)... 13,
66
Peripheral Interrupt Enable (PEIE Bit) ........................ 13
RB0/INT Enable (INTE Bit) ......................................... 13
TMR0 Overflow Enable (T0IE Bit) .............................. 13
TMR1 Overflow Enable (TMR1IE Bit)......................... 14
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 14
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) .............................. 15, 50
CCP1 Flag (CCP1IF Bit)....................................... 15, 34
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .. 13, 66
RB0/INT Flag (INTF Bit) ............................................. 13
TMR0 Overflow Flag (T0IF Bit)............................. 13, 66
TMR1 Overflow Flag (TMR1IF Bit) ............................. 15
TMR2 to PR2 Match Flag (TMR2IF Bit)...................... 15
IORLW Instruction .............................................................. 79
IORWF Instruction .............................................................. 79
M
Master Clear (MCLR)
MCLR Reset, Normal Operation..................... 58, 62, 63
MCLR Reset, Sleep ........................................ 58, 62, 63
Memory Organization
Data Memory ................................................................ 7
Program Memory .......................................................... 7
Migration from Base-Line to Mid-Range Devices ............. 114
MOVF Instruction................................................................ 79
MOVLW Instruction............................................................. 79
MOVWF Instruction ............................................................ 80
MPLAB ASM30 Assembler, Linker, Librarian ..................... 86
MPLAB ICD 2 In-Circuit Debugger ..................................... 87
MPLAB ICE 2000 High Performance Universal
In-Circuit Emulator ...................................................... 87
MPLAB ICE 4000 High Performance Universal
In-Circuit Emulator ...................................................... 87
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
MPLAB Integrated Development Environment Software .... 85
MPLINK Object Linker/MPLIB Object Librarian .................. 86
N
NOP Instruction................................................................... 80
O
OPTION Instruction............................................................. 80
OPTION_REG Register ................................................ 10, 12
INTEDG Bit ................................................................. 12
PS2:PS0 Bits ........................................................ 12, 27
PSA Bit.................................................................. 12, 27
RBPU Bit..................................................................... 12
T0CS Bit................................................................ 12, 27
T0SE Bit................................................................ 12, 27
Oscillator Configuration................................................. 55, 57
HS ......................................................................... 57, 62
LP.......................................................................... 57, 62
RC................................................................... 57, 58, 62
Selection (FOSC1:FOSC0 Bits).................................. 56
XT ......................................................................... 57, 62
Oscillator, Timer1 .......................................................... 29, 30
Oscillator, WDT ................................................................... 67
P
Packaging ......................................................................... 109
Paging, Program Memory ............................................... 7, 17
PCON Register ............................................................. 16, 62
BOR Bit ....................................................................... 16
POR Bit ....................................................................... 16
PICkit 1 FLASH Starter Kit .................................................. 89
PICSTART Plus Development Programmer ....................... 87
PIE1 Register ................................................................ 10, 14
ADIE Bit ...................................................................... 14
CCP1IE Bit.................................................................. 14
TMR1IE Bit.................................................................. 14
TMR2IE Bit.................................................................. 14
PIR1 Register.................................................................. 9, 15
ADIF Bit....................................................................... 15
CCP1IF Bit .................................................................. 15
TMR1IF Bit.................................................................. 15
TMR2IF Bit.................................................................. 15
Pointer, FSR ....................................................................... 18
POR. See Power-on Reset
PORTA
PORTA Register ..................................................... 9, 19
TRISA Register ..................................................... 10, 19
PORTB
PORTB Register ..................................................... 9, 21
Pull-up Enable (RBPU Bit) .......................................... 12
RB0/INT Edge Select (INTEDG Bit)............................ 12
RB0/INT Pin, External................................................. 66
RB7:RB4 Interrupt-on-Change.................................... 66
RB7:RB4 Interrupt-on-Change Enable
(RBIE Bit) ...................................................... 13, 66
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit)........... 66
TRISB Register ..................................................... 10, 21
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bits) ............................. 31
Postscaler, WDT ................................................................. 27
Assignment (PSA Bit) ........................................... 12, 27
Rate Select (PS2:PS0 Bits) .................................. 12, 27
Switching Between Timer0 and WDT ......................... 28
Power-down Mode. See Sleep
Power-on Reset (POR) ..................................... 55, 58, 62, 63
Oscillator Start-up Timer (OST) ............................ 55, 59
 2003 Microchip Technology Inc.
POR Status (POR Bit) ................................................ 16
Power Control (PCON) Register................................. 62
Power-down (PD Bit) ............................................ 11, 58
Power-on Reset Circuit, External ............................... 58
Power-up Timer (PWRT) ...................................... 55, 59
PWRT Enable (PWRTE Bit) ....................................... 56
Time-out (TO Bit).................................................. 11, 58
Time-out Sequence .................................................... 62
Time-out Sequence on Power-up............................... 64
Timing Diagram ........................................................ 101
Prescaler, Capture.............................................................. 34
Prescaler, Timer0 ............................................................... 27
Assignment (PSA Bit) ........................................... 12, 27
Rate Select (PS2:PS0 Bits) .................................. 12, 27
Switching Between Timer0 and WDT ......................... 28
Prescaler, Timer1 ............................................................... 30
Select (T1CKPS1:T1CKPS0 Bits) .............................. 29
Prescaler, Timer2 ............................................................... 37
Select (T2CKPS1:T2CKPS0 Bits) .............................. 31
PRO MATE II Universal Device Programmer ..................... 87
Program Counter
PCL Register .......................................................... 9, 17
PCLATH Register ............................................. 9, 17, 66
Reset Conditions ........................................................ 62
Program Memory .................................................................. 7
Interrupt Vector............................................................. 7
Paging .................................................................... 7, 17
Program Memory Map.................................................. 7
Reset Vector................................................................. 7
Program Verification ........................................................... 69
PWM (CCP Module) ........................................................... 36
CCPR1H:CCPR1L Registers ..................................... 36
Duty Cycle .................................................................. 37
Example Frequencies/Resolutions ............................. 37
Output Diagram .......................................................... 36
Period ......................................................................... 36
Set-Up for PWM Operation......................................... 37
TMR2 to PR2 Match ............................................. 31, 36
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 14
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 15
PWM (ECCP Module)......................................................... 38
Associated Registers.................................................. 48
Direction Change in Full-Bridge Output Mode............ 43
Effects of Reset .......................................................... 48
Full-Bridge Application Example................................. 43
Full-Bridge Mode ........................................................ 43
Half-Bridge Mode........................................................ 42
Half-Bridge Output Mode Applications Example ........ 42
Output Configurations................................................. 38
Output Relationships (Active High and Low) .............. 40
Output Relationships (Active-High and Low).............. 39
Output Relationships Diagram.............................. 39, 41
Programmable Dead-band Delay ............................... 45
Setup for Operation .................................................... 48
Shoot-through Current ................................................ 45
Start-up Considerations .............................................. 47
Q
Q-Clock....................................................................... 37, 100
Preliminary
DS41206A-page 119
PIC16F716
R
RA3:RA0 ............................................................................. 19
RA4/T0CKI Pin.................................................................... 20
RAM. See Data Memory.
RB0 Pin ............................................................................... 21
Register File .......................................................................... 8
Register File Map .................................................................. 8
Registers
A/D ADCON0 .............................................................. 49
A/D ADCON1 .............................................................. 49
A/D ADRES........................................................... 49, 50
ADCON0 ADCS1:ADCS0 Bits .................................... 49
ADCON0 ADON Bit .................................................... 49
ADCON0 CHS2:CHS0 Bits ......................................... 49
ADCON0 GO/DONE Bit ........................................ 49, 50
ADCON1 PCFG2:PCFG0 Bits .................................... 50
CCP1CON CCP1M3:CCP1M0 Bits ............................ 33
CCP1CON CCP1X:CCP1Y Bits ................................. 33
Compare (CCP Module)
CCPR1H:CCPR1L .............................................. 34
INTCON Register
RBIF.................................................................... 21
PWM1CON (Enhanced PWM Configuration) ............. 46
T1CON Register
T1CKPS1:T1CKPS0 Bits .................................... 29
T1OSCEN Bit...................................................... 29
T1SYNC Bit......................................................... 29
TMR1CS Bit ........................................................ 29
TMR1ON Bit........................................................ 29
T2CON Register T2CKPS1:T2CKPS0 Bits ................ 31
T2CON Register TMR2ON Bit .................................... 31
T2CON Register TOUTPS3:TOUTPS0 Bits ............... 31
Timer2
PR2 ..................................................................... 36
Timer2 PR2 Register .................................................. 31
Timer2 TMR2 Register................................................ 31
TMR1H Timer1 Register ............................................. 29
TMR1L Timer1 Register.............................................. 29
Reset............................................................................. 55, 58
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for PCON Register.......................... 62
Reset Conditions for Program Counter ....................... 62
Reset Conditions for Status Register .......................... 62
Timing Diagram......................................................... 101
WDT Reset. See Watchdog Timer (WDT)
RETFIE Instruction.............................................................. 80
RETLW Instruction .............................................................. 81
RETURN Instruction............................................................ 81
Revision History ................................................................ 113
RLF Instruction.................................................................... 81
RRF Instruction ................................................................... 82
S
Shoot-through Current ........................................................ 45
Sleep ....................................................................... 55, 58, 68
Sleep Instruction ................................................................. 82
Software Simulator (MPLAB SIM)....................................... 86
Software Simulator (MPLAB SIM30)................................... 86
Special Event Trigger. See Compare
Special Features of the CPU............................................... 55
Special Function Registers ................................................... 9
Speed, Operating .................................................................. 1
Stack ................................................................................... 17
DS41206A-page 120
Status Register ............................................................... 9, 66
C Bit ............................................................................ 11
DC Bit ......................................................................... 11
IRP Bit ........................................................................ 11
PD Bit ................................................................... 11, 58
RP1:RP0 Bits.............................................................. 11
TO Bit ................................................................... 11, 58
Z Bit ............................................................................ 11
SUBLW Instruction ............................................................. 82
SUBWF Instruction ............................................................. 83
SWAPF Instruction ............................................................. 83
T
T1CON Register ................................................................... 9
T2CON Register ................................................................... 9
Timer0................................................................................. 27
Clock Source Edge Select (T0SE Bit) .................. 12, 27
Clock Source Select (T0CS Bit)............................ 12, 27
Overflow Enable (T0IE Bit) ......................................... 13
Overflow Flag (T0IF Bit)........................................ 13, 66
Overflow Interrupt ................................................. 28, 66
Prescaler. See Prescaler, Timer0
Timing Diagram ........................................................ 102
TMR0 Register.............................................................. 9
Timer1................................................................................. 29
Clock Source Select (TMR1CS Bit) ............................ 29
External Clock Input Sync (T1SYNC Bit).................... 29
Module On/Off (TMR1ON Bit)..................................... 29
Oscillator............................................................... 29, 30
Oscillator Enable (T1OSCEN Bit) ............................... 29
Overflow Enable (TMR1IE Bit).................................... 14
Overflow Flag (TMR1IF Bit) ........................................ 15
Overflow Interrupt ................................................. 29, 30
Prescaler. See Prescaler, Timer1
Special Event Trigger (CCP) ................................ 30, 35
T1CON Register ........................................................... 9
Timing Diagram ........................................................ 102
TMR1H Register ........................................................... 9
TMR1L Register............................................................ 9
Timer2
Postscaler. See Postscaler, Timer2
PR2 Register .............................................................. 10
Prescaler. See Prescaler, Timer2
T2CON Register ........................................................... 9
TMR2 Register.............................................................. 9
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 14
TMR2 to PR2 Match Flag (TMR2IF Bit)...................... 15
TMR2 to PR2 Match Interrupt......................... 31, 32, 36
Timing Diagrams
Half-Bridge PWM Output ............................................ 42
PWM Auto-Shutdown (PRSEN = 0, Auto-Restart
Disabled) ............................................................ 47
PWM Auto-Shutdown (PRSEN = 1, Auto-Restart
Enabled) ............................................................. 47
PWM Direction Change .............................................. 44
PWM Direction Change at Near 100% Duty Cycle..... 44
Time-out Sequence on Power-up ............................... 64
Wake-up from Sleep via Interrupt ............................... 69
Timing Diagrams and Specifications .................................. 98
A/D Conversion......................................................... 105
Brown-out Reset (BOR)............................................ 101
Capture/Compare/PWM (CCP) ................................ 103
CLKOUT and I/O ...................................................... 100
External Clock............................................................. 98
Oscillator Start-up Timer (OST) ................................ 101
Power-up Timer (PWRT) .......................................... 101
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
Reset......................................................................... 101
Timer0 and Timer1.................................................... 102
Watchdog Timer (WDT) ............................................ 101
TRIS Instruction .................................................................. 83
W
W Register .......................................................................... 66
Wake-up from Sleep ..................................................... 55, 68
Interrupts............................................................... 62, 63
MCLR Reset ............................................................... 63
Timing Diagram........................................................... 69
WDT Reset ................................................................. 63
Watchdog Timer (WDT) ................................................ 55, 67
Enable (WDTE Bit)................................................ 56, 67
Postscaler. See Postscaler, WDT
Programming Considerations ..................................... 67
RC Oscillator............................................................... 67
Time-out Period .......................................................... 67
Timing Diagram......................................................... 101
WDT Reset, Normal Operation ....................... 58, 62, 63
WDT Reset, Sleep .......................................... 58, 62, 63
WWW, On-Line Support ....................................................... 3
X
XORLW Instruction ............................................................. 84
XORWF Instruction ............................................................. 84
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 121
PIC16F716
NOTES:
DS41206A-page 122
Preliminary
 2003 Microchip Technology Inc.
PIC16F716
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device
PIC16F716, PIC16F716T, VDD range 2.0V to 5.5V
Temperature Range
I
E
= -40°C to +85°C
= -40°C to +125°C
Package
SO
P
SS
=
=
=
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
PIC16F716 -I/P 301= Industrial temp., PDIP
package, QTP pattern #301.
PIC16F716 - E/SO = Extended temp, SOIC
package
(Industrial)
(Extended)
SOIC
PDIP
SSOP
Note
1:
T = in tape and reel SOIC and SSOP
packages only.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2003 Microchip Technology Inc.
Preliminary
DS41206A-page 123
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Korea
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Atlanta
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
China - Beijing
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
Phoenix
China - Shunde
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
San Jose
China - Qingdao
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
Toronto
India
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 905-673-6509
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
DS41206A-page 124
Preliminary
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
 2003 Microchip Technology Inc.
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