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Si5356
I 2C P ROGRAMMABLE , A NY - F R E Q U E N C Y 1 – 2 0 0 M H Z ,
Q UAD F R E Q U E N C Y 8-O UTPUT C LOCK G ENERATOR
Features









Generates any frequency from 1 to

200 MHz on each of the 4 output banks
Programmable frequency configuration 
Guaranteed 0 ppm frequency synthesis
error for any combination of frequencies 
25 or 27 MHz xtal or 5–200 MHz input clk
Eight CMOS clock outputs
Easy to use programming software

Configurable “triple A” spread spectrum: 
any clock, any frequency, and with any 
spread amount
Programmable output phase adjustment 
with <20 ps error

Interrupt pin indicates LOS or LOL
OEB pin disables all outputs or per
bank OEB control via I2C
Low jitter: 50 ps pk-pk (typ), 100 ps
pk-pk period jitter (max)
Excellent PSRR performance
eliminates need for external power
supply filtering
Low power: 45 mA
Core VDD: 1.8, 2.5, or 3.3 V
Separate VDDO for each bank of
outputs: 1.8, 2.5, or 3.3 V
Small size: 4x4 mm 24-QFN
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 24.
Pin Assignments
Applications
CLK1
CLK1
VDDOA
VDDOA
P3
SDA
Top
TopView
View
Storage area networks
Switches/routers
Servers
CLK0
CLK0



24 24 2323 2222
2121
20
20
19
19
GND
GND
Printers
Audio/video
DSLAM
VDD
VDD



Description
XAXA1 1
18
18 CLK2
CLK2
The Si5356 is a highly flexible, I2C programmable clock generator capable of
synthesizing four completely non-integer related frequencies up to 200 MHz. The
device has four banks of outputs with each bank supporting two CMOS outputs at
the same frequency. Using Silicon Laboratories' patented MultiSynth fractional
divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis
error regardless of configuration, enabling the replacement of multiple clock ICs
and crystal oscillators with a single device. Each output bank is independently
configurable to support 1.8, 2.5, or 3.3 V. The device is programmable via an I2C/
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
3.3 V core supply.
XBXB2 2
17
17 CLK3
CLK3
16
16 VDDOB
VDDOB
I2C_LSB
P1 3 3
GND
GND
GND
GND
CLKIN
CLKIN4 4
15
15 VDDOC
VDDOC
14
14 CLK4
CLK4
SSC_DIS
P4 5 5
LOS
INTR
CLK7
CLK7
1010
11
11
12
12
P2
SCL
99
CLK6
CLK6
8 8
VDDOD
VDDOD
7 7
VDD
VDD
OEB6 6
P5
13
13 CLK5
CLK5
Functional Block Diagram
Preliminary Rev. 0.3 2/11
Copyright © 2011 by Silicon Laboratories
Si5356
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5356
2
Preliminary Rev. 0.3
Si5356
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3. Breakthrough MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5. Configuring the Si5356 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6. Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.11. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.12. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Si5356 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Pin Descriptions: Si5356 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Preliminary Rev. 0.3
3
Si5356
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Ambient Temperature
TA
–40
—
85
Core Supply Voltage
VDD
2.97
3.3
3.63
2.25
2.5
2.75
1.71
1.8
1.98
1.71
—
3.63
Output Buffer Supply Voltage
VDDO
Units
o
C
V
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless
otherwise noted.
Table 2. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Units
VDD
–0.5 to +3.8
V
Input Voltage Range (all pins except pins 1,2,5,6)
VI
–0.5 to 3.8
V
Input Voltage Range (pins 1,2,5,6)
VI2
–0.5 to 1.2
V
Output Voltage Range
VO
–0.5 to VDD + 0.3
V
Storage Temperature Range
TS
–55 to +150
oC
HBM
2.5
kV
CDM
550
V
MM
175
V
Supply Voltage Range
ESD Tolerance
Latch-up Tolerance
LU
2
Soldering Temperature (Pb-free profile)
TPEAK
JESD78 Compliant
260
Notes:
1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional
o
C
operation should be restricted to the conditions as specified in the operational sections of this data sheet.
Exposure to maximum rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C.
4
Preliminary Rev. 0.3
Si5356
Table 3. DC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Current Consumption
IDD
100 MHz on all outputs,
25 MHz refclk
—
45
60
mA
High Level Input Voltage
VIH
CLKIN, I2C_LSB
0.8 x VDD
—
3.63
V
SSC_DIS, OEB
0.85
—
1.3
V
CLKIN, I2C_LSB
–0.2
—
0.2 x VDD
V
SSC_DIS, OEB
—
—
0.3
V
Low Level Input Voltage
VIL
Clock Output High Level Output
Voltage
VOH
Pins: CLK0–7
IOH = –4 mA
VDDO – 0.3
—
—
V
Clock Output Low Level Output Voltage
VOL
Pins: CLK0–7
IOH = +4 mA
—
—
0.3
V
VOLINTR
Pin: LOS
IOH = +3 mA
0
—
0.4
V
20
—
—
k
INTR Low Level Output Voltage
SSC_DIS, OEB Input
Resistance
RIN
Preliminary Rev. 0.3
5
Si5356
Table 4. AC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
5
—
200
MHz
Input Clock
Clock Input Frequency
Clock Input Rise/Fall Time
FIN
TR/TF
20 to 80% VDD
—
—
2
ns
Clock Input Duty Cycle
DC
< 2 ns tr/tf
40
—
60
%
Clock Input Capacitance
CIN
—
2
—
pF
FO
1
—
200
MHz
—
—
0
ppm
—
15
—
pF
Output Clocks
Clock Output Frequency
Clock Output Frequency Synthesis
Resolution
Output Load Capacitance
FRES
See "3.4. Frequency Configuration" on page 11
CL
Clock Output Rise/Fall Time
TR/TF
20 to 80% VDD,
CL = 15 pF
—
—
1.7
ns
Clock Output Rise/Fall Time
TR/TF
20 to 80% VDD,
CL = 2 pF
—
0.45
0.85
ns
Clock Output Duty Cycle
DC
Measured at VDD/2
45
50
55
%
Powerup Time
TPU
POR to output clock valid
—
—
2
ms
Output Enable Time
TOE
—
—
10
µs
Output-Output Skew
TSKEW
Outputs at same
frequency, fOUT > 5 MHz
–150
—
+150
ps
Period Jitter
JPPKPK
10000 cycles
—
50
75
ps pk-pk
Cycle-Cycle Jitter
JCCPK
10000 cycles
—
40
70
ps pk
Phase Jitter
JPH
12 kHz to 20 MHz
—
2
—
ps rms
PLL Loop Bandwidth
FBW
—
1.6
—
MHz
6
Preliminary Rev. 0.3
Si5356
Table 5. Crystal Specifications
Parameter
Crystal Frequency
Symbol
Test Condition
Min
Typ
Max
Units
FXTAL
Option 1
—
25
—
MHz
Option 2
—
27
—
MHz
Load Capacitance
(on-chip differential)
CL
11
12
13
pF
Crystal Output Capacitance
CO
—
—
4
pF
25 MHz
—
—
100

27 MHz
—
—
75

100
—
—
µW
Equivalent Series Resistance
ESR
Max Drive Level
dL
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance
Junction to Ambient
JA
Still Air
37
°C/W
Thermal Resistance
Junction to Case
JC
Still Air
25
°C/W
Table 7. I2C Specifications (SCL,SDA)2
Parameter
Symbol
Test Condition
Fast Mode3
Standard Mode
Unit
Min
Max
Min
Max
LOW level input
voltage:
VILI2C
–0.5
0.3*VDDI2C
–0.5
0.3*VDDI2C1
V
HIGH level input
voltage:
VIHI2C
0.7*VDDI2C
3.63
0.7*
VDDI2C1
3.63
V
Hysteresis of
Schmitt trigger
inputs
VHYS
N/A
N/A
0.1
—
V
0
0.4
0
0.4
V
N/A
N/A
0
0.2 x VDDI2C
V
–10
10
–10
10
µA
—
4
—
4
pF
25
35
25
35
ms
LOW level output
voltage (open drain
or open collector)
at 3 mA sink
current
VOLI2C1 VDDI2C1 = 2.5 / 3.3 V
1
VDDI2C = 1.8 V
Input current
III2C
Capacitance for
each I/O pin
CII2C
I2C Bus timeout
—
VIN = –0.1 to VDDI2C
Notes:
1. Only I2C pull up voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I2C bus voltage
is less than 2.25 V.
2. Refer to NXP’s UM10204 I2C-bus specification and user manual, revision 03, for further details:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
3. Compliant with Fast Mode+ pending characterization.
Preliminary Rev. 0.3
7
Si5356
2. Typical Application Circuits
+3.3 V
0.1 uF Power Supply
Decoupling Capacitors
(1 per VDD or VDDOx pin)
1
2
4
+3.3V
VDDOD
VDDOB
CLK0
CLKIN
CLK1
1k
CLK2
8
19
I2C Bus
12
3
I C Address = 111 0000 (0x70)
or 111 0001 (0x71)
2
Rse
5
Rse
6
Note: See section 3.1 for
information on selecting
Rse and Rsh.
XB
Rsh
CLK3
INTR
CLK4
Si5356
SDA
CLK5
SCL
CLK6
I2C_LSB
CLK7
22
25 MHz
25 MHz
25 MHz
25 MHz
21
18
17
14
13
10
9
x
x
125 MHz
33/66 MHz
MCU/
Processor
SSC_DIS
OEB
Rsh
Ethernet
Ethernet
PHY
Ethernet
PHY
Ethernet
PHY
PHY
Ethernet
Switch
GND
1k
XA
GND
1k
15 11
VDDOC
25 MHz
XTAL
20 16
VDD
VDD
7 24
VDDOA
4-Port Ethernet Switch/Router
PAD
PAD
23
23
Laser Printer
+3.3 V
0.1 uF Power Supply
Decoupling Capacitors
(1 per VDD or VDDOx pin)
1
2
4
+3.3 V
1k
1k
XA
125 MHz
XB
CLK0
CLKIN
CLK1
1k
CLK2
8
19
2
I C Bus
12
2
I C Address = 111 0000 (0x70)
or 111 0001 (0x71)
3
USB
Controller
CLK3
INTR
CLK4
Si5356
SDA
CLK5
SCL
CLK6
I2C_LSB
Processor
DDR
Memory
VDDOD
VDDOB
15 11
VDDOC
25 MHz
XTAL
20 16
VDD
VDD
7 24
VDDOA
Ethernet
PHY
CLK7
Print Head
22
21
18
17
14
13
10
9
x
48 MHz
Paper Tray
x
66/100 MHz
x
Key Pad
x
35.788 MHz
8
Rse
6
Rsh
Rsh
SSC_DIS
Touchscreen
Controller
OEB
23
23
GND
5
GND
Note: See section 3.1 for
information on selecting
Rse and Rsh.
Rse
PAD
PAD
Preliminary Rev. 0.3
LCD Screen
Si5356
3. Functional Description
3.1. Overview
I 2C
The Si5356 is a highly flexible,
programmable clock
generator capable of synthesizing four independent
frequencies up to 200 MHz. The device has four banks
of outputs with each bank supporting two CMOS
outputs at the same frequency. The Si5356 supports
free-running mode of operation using an external
crystal, or it can lock to an external clock for generating
synchronous clocks. The output drivers support 1.8, 2.5,
and 3.3 V CMOS formats, and each output bank is
independently configurable. Adjustable output-to-output
phase offsets are also available to compensate for PCB
trace delays or for fine tuning of setup and hold
margins.
Configuration and control of the Si5356 is handled
through the I2C/SMBus interface. The device also
provides the option of storing a user-definable clock
configuration in its non-volatile memory (NVM), which
becomes the default clock configuration an power-up.
See section "3.5.1. Ordering a Custom NVM
Configuration" on page 11 for details.
3.1.1. ClockBuilder™ Desktop Software
To simplify device configuration, Silicon Labs has
released the ClockBuilder Desktop. The software
serves two purposes: to configure the Si5356 with
optimal configuration based on the desired frequencies,
and to control the EVB, when connected to a host PC.
The optimal configuration can be saved from the
software in text files that can be used in any system,
which configures the device over I2C. ClockBuilder
Desktop can be downloaded from www.silabs.com/
ClockBuilder and runs on Windows XP, Windows Vista,
and Windows 7. Additionally, an NVM file can be
generated using the NVMSave for Factory
Programming... menu option. An NVM file can be used
by factory to prepare custom pre-programmed devices.
3.2. Input Configuration
The Si5356 input can be driven from either an external
crystal or a reference clock. If the crystal input option is
used, the Si5356 operates as a free-running clock
generator. In this mode of operation the device requires
a low cost 25 or 27 MHz fundamental mode crystal
connected across XA and XB as shown in Figure 1.
Given the Si5356’s frequency flexibility, the same crystal
can be reused to generate any combination of output
frequencies. Custom frequency crystals are not
required. The Si5356 integrates the crystal load
capacitors on-chip to reduce external component count.
The crystal should be placed very close to the device to
minimize stray capacitance. To ensure a stable and
accurate output frequency, the recommended crystal
specifications provided in Table 5 on page 7 must be
followed. See AN360 for additional details regarding
crystal recommendations.
Preliminary Rev. 0.3
9
Si5356
3.3. Breakthrough MultiSynth Technology
Si5356
XA
XTAL
XB
Figure 1. Connecting an XTAL to the Si5356
For synchronous timing applications, the Si5356 can
lock to a 5 to 200 MHz CMOS reference clock. A typical
interface circuit is shown in Figure 2. A series
termination resistor matching the driver’s output
impedance to the impedance of the transmission line is
recommended to reduce reflections.
Si5356
Rs
50
CLKIN
Figure 2. Interfacing CMOS Reference Clocks
to the Si5356
Control input signals to SSC_DIS and OEB cannot
exceed 1.3 V yet also need to meet the VOH and VOL
specifications outlined in Table 3 on page 5. When
these inputs are driven from CMOS sources, a resistive
attenuator as shown in the Typical Application Circuits
must be used. Suggested standard 1% resistor values
for RSE and RSH, when using a CMOS source, are
given below.
CMOS Level
1.8 V
2.5 V
3.3 V
RSE ohms
1000
1960
3090
RSH ohms
1580
1580
1580
Modern timing architectures require a wide range of
frequencies which are often non-integer related.
Traditional clock architectures address this by using a
combination of single PLL ICs, 4-PLL ICs and discrete
XOs, often at the expense of BOM complexity and
power. The Si5356 use patented MultiSynth technology
to dramatically simplify timing architectures by
integrating the frequency synthesis capability of 4
phase-locked loops (PLLs) in a single device, greatly
minimizing size and power requirements versus
traditional solutions. Based on a fractional-N PLL, the
heart of the architecture is a low phase noise, highfrequency VCO. The VCO supplies a high frequency
output clock to the MultiSynth block on each of the four
independent output paths. Each MultiSynth operates as
a high-speed fractional divider with Silicon Laboratories'
proprietary phase error correction to divide down the
VCO clock to the required output frequency with very
low jitter.
The first stage of the MultiSynth architecture is a
fractional-N divider which switches seamlessly between
the two closest integer divider values to produce the
exact output clock frequency with 0 ppm error. To
eliminate phase error generated by this process,
MultiSynth calculates the relative phase difference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
Based on this architecture, each clock output can
produce any frequency from 1 to 200 MHz.
MultiSynth
fVCO
Fractional-N
Divider
Phase
Adjust
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
Figure 3. Silicon Labs' MultiSynth Technology
10
Preliminary Rev. 0.3
fOUT
Si5356
3.4. Frequency Configuration
The Si5356 utilizes a single PLL-based architecture,
four independent MultiSynth fractional output dividers,
and a MultiSynth fractional feedback divider such that a
single device provides the clock generation capability of
four independent PLLs. Unlike competitive multi-PLL
solutions, the Si5356 can generate four unique noninteger related output frequencies with 0 ppm frequency
error, with respect to the reference, for any combination
of output frequencies. In addition, any combination of
output frequencies can be generated from a single
reference frequency without having to change the
crystal or reference clock frequency between
configurations.
Frequency configurations are fully programmable by
writing to device registers using the I2C interface. Any
combination of output frequencies ranging from 1 to
200 MHz can be configured on each of the device
outputs.
The following equation governs how the output
frequency is calculated.
f IN  N
f OUT = ----------------P  Mi
Two versions of the Si5356 are available. First, noncustomized Si5356 devices are available in which the
RAM can be configured in-circuit via I2C. These blank
Si5356 devices can also be field programmed using the
Si5338/56-PROG-EVB (see “3.5.5. Writing a Custom
Configuration to NVM”). Second, custom factoryprogrammed Si5356 devices are available that include
a user-specified startup frequency configuration
(example part number Si5356A-Axxxxx-GM).
3.5.1. Ordering a Custom NVM Configuration
where fIN is the reference frequency, N is the MultiSynth
feedback divider value, P is the reference divider value,
Mi is the MultiSynth output divider value and fOUT is the
resulting output frequency. The MultiSynth output and
feedback dividers are fractional dividers expressed in
terms of an integer and a fraction. The integer portion
has 10-bit resolution and the fractional portion has 30bit resolution in both the numerator and denominator,
meaning that any output frequency can be defined
exactly from the input frequency with exact (0 ppm)
frequency synthesis error.
3.5. Configuring the Si5356
The Si5356 is a highly-flexible clock generator that is
entirely configurable through its I2C interface. The
device’s default configuration is stored in non-volatile
memory (NVM) as shown in Figure 4. The NVM is a
one-time programmable memory (OTP), which can
store a custom user configuration at power-up. This is a
useful feature for applications that need a clock present
at power-up (e.g., for providing a clock to a processor).
The Si5356 is orderable with a factory-programmed
custom NVM configuration. This is the simplest way of
using the Si5356 since it generates the desired output
frequencies at power-up or after a power-on reset
(POR). This default configuration can be reconfigured in
RAM through the I2C interface after power-up (see
“3.5.2. Creating a New Configuration for RAM”).
The first step in ordering a custom device is generating
an NVM file which defines the input and output clock
frequencies and signal formats. This is easily done
using the NVMSave for Factory Programming... menu
option in ClockBuilder Desktop. (See "3.1.1.
ClockBuilder™ Desktop Software" on page 9.) This
Windows based software allows the user to generate an
NVM file, which is used by the factory to manufacture
custom parts. Each custom part is marked with a unique
part number identifying the specific configuration (e.g.,
Si5356A-A00100-GM).
Consult your local sales representative for more details
on ordering a custom Si5356.
3.5.2. Creating a New Configuration for RAM
Any Si5356 device can be configured by writing to
registers in RAM through the I2C interface. A nonfactory programmed device must be configured in this
manner.
Power-Up/POR
NVM
(OTP)
Default
Config
During a power cycle or a power-on reset (POR), the
contents of the NVM are copied into random access
memory (RAM), which sets the device configuration that
will be used during operation. Any changes to the
device configuration after power-up are made by
reading and writing to registers in the RAM space
through the I2C interface. ClockBuilder Desktop (see
"3.1.1. ClockBuilder™ Desktop Software" on page 9)
can be used to easily configure register map files that
can be written into RAM (see “3.5.2. Creating a New
Configuration for RAM” for details). Alternatively, the
register map file can be created manually with the help
of the equations in AN565.
RAM
I2C
Figure 4. Si5356 Memory Configuration
Preliminary Rev. 0.3
11
Si5356
When creating a custom RAM configuration, use the
following procedure:
3.5.4. Modifying a MultiSynth Output Divider Ratio/
Frequency Configuration
1. Create a device configuration (register map) using
ClockBuilder Desktop (v2.7 or later; see "3.1.1.
ClockBuilder™ Desktop Software" on page 9) or
manually using the equations in “AN565: Configuring
the Si5356A”.
Any of the four output frequencies of a previously
configured Si5356 may be modified without disturbing
the other outputs. In this case, do not write the feedback
Multisynth registers. Instead, only write the set of
registers associated with the output MultiSynth divider
of interest (see “AN565: Configuring the Si5356A”).
a. Configure the frequency plan.
b. Configure the output driver format and supply
voltage.
c. Configure initial phase offset (if desired).
d. Configure spread spectrum (if desired).
2. Save the configuration using the Options > Save
Register Map File or Options > Save C code Header
File, or create the register contents by the
conversions listed in AN565.
At this point, the new configuration can be written to the
device RAM according to the instructions in “3.5.3.
Writing a Custom Configuration to RAM”.
3.5.3. Writing a Custom Configuration to RAM
Writing a new configuration (register map) to the RAM
consists of pausing the LOL state-machine, writing new
values to the IC accounting for the write-allowed mask
given in AN565, validating the input clock or crystal,
locking the PLL to the input with the new configuration,
restarting the LOL state-machine, and calibrating the
VCO for robust operation across temperature. The flow
chart in Figure 5 on page 12 enumerates the details:
Note: The write-allowed mask specifies which bits must be
read and modified before writing the entire register
byte (a.k.a. read-modify-write). “AN428: Jump Start: InSystem, Flash-Based Programming for Silicon Labs’
Timing Products” illustrates the procedure defined in
Section 3.5.2 with ANSI C code.
To avoid intermediate frequencies, it is recommended
that the output to be modified is disabled before
changing the divider ratios (see AN565 for a description
of Register 230).
Any output Multisynth that is reconfigured will lose its
output skew alignment with the other outputs.
SOFT_RESET can be used to realign the outputs;
however, a soft reset will temporarily disable all outputs
in the process of realignment.
3.5.5. Writing a Custom Configuration to NVM
An alternative to ordering an Si5356 with a custom NVM
configuration is to use the field programming kit
(Si5338/56-PROG-EVB) to write directly to the NVM of
a "blank" Si5356. Since NVM is an OTP memory, it can
only be written once. The default configuration can be
reconfigured by writing to RAM through the I2C interface
(see “3.5.2. Creating a New Configuration for RAM”).
3.6. Output Phase Adjustment
The Si5356 has a digitally-controlled phase adjustment
feature that allows the user to adjust the phase of each
output clock in relation to the other output clocks. The
phase of each output clock can be adjusted with an
error of <20 ps over a range of ±45 ns. This feature is
available on any clock output that does not have Spread
Spectrum enabled.
D isa b le O u tp u ts
S e t O E B _ A L L = 1 ; re g 2 3 0 [4 ]
S e t re g 2 4 1 = 0 x 6 5
R e g iste r
M ap
U s e C lo ck B u ild e r
D e sk to p v 3 .0 o r la te r
W rite n e w c o n fig u ra tio n to d e vic e
a c co u n tin g fo r th e w rite -a llo w e d m a sk
(S e e A N 5 6 5 : C o n fig u rin g th e S i5 3 5 6 A )
A p p ly S o ft R e s e t
S e t S O F T _ R E S E T = 1 ; re g 2 4 6 [1 ]
E n a b le O u tp u ts
S e t O E B _ A L L = 0 ; re g 2 3 0 [4 ]
Figure 5. I2C Programming Procedure
12
Preliminary Rev. 0.3
Si5356
3.7. CMOS Output Drivers
The Si5356 has 4 banks of outputs with each bank
comprised of 2 clocks for a total of 8 CMOS outputs per
device. By default, each bank of CMOS output clocks
are in-phase. Alternatively, each output clock can be
inverted. This feature enables each output pair to
operate as a differential CMOS clock. Each of the
output banks can operate from a different VDDO supply
(1.8 V, 2.5 V, 3.3 V), simplifying usage in mixed supply
applications. All clock outputs between 5 and 200 MHz
are in-phase to within ±150 ps.
The CMOS output driver has a controlled impedance in
the range of 42 to 50 which includes an internal 22 
series resistor. An external series resistor is not needed
when driving 50  traces. If higher impedance traces
are used then a series resistor may be added. A typical
configuration is shown in Figure 6.
3.8. Jitter Performance
The Si5356 provides consistently low jitter for any
combination of output frequencies. The device
leverages a low phase noise single PLL architecture
and Silicon Laboratories’ patented MultiSynth fractional
output divider technology to deliver period jitter less
than 100 ps pk-pk (max) for any frequency
configuration. This level of jitter performance is
guaranteed across process, temperature and voltage.
The Si5356 provides superior performance to traditional
multi-PLL solutions which may suffer from degraded
jitter performance depending on frequency plan and the
number of active PLLs.
3.9. Status Indicators
An interrupt pin (INTR) is available to indicate a loss of
signal (LOS) condition, a PLL loss of lock (LOL)
condition, or that the PLL is in the process of acquiring
lock (SYS_CAL). As shown in Figure 7, a status register
at address 218 is available to help identify the exact
event that caused the interrupt pin to become active. A
LOS condition occurs when there is no clock input to the
Si5356. The loss of lock algorithm works by
continuously monitoring the frequency difference
between the two inputs of the phase frequency detector.
When this frequency difference is greater than
1000 ppm, a loss of lock condition is declared. Note that
the VCO will track the input clock frequency for up to
~25000 ppm, which will keep the inputs to the phase
frequency detector at the same frequency until the PLL
comes out of lock. When a clock input is removed, the
interrupt pin will assert, and the clock outputs may drift
up to 5%. When the input clock is reapplied with an
appropriate frequency, the PLL will again lock.
Si5356
+1.8V, +2.5V, +3.3V
VDDOA
Bank A
CLK0
MultiSynth
50
CLK1
50
PLL
+1.8V, +2.5V, +3.3V
VDDOB
Bank B
CLK2
MultiSynth
50
CLK3
50
+1.8V, +2.5V, +3.3V
VDDOC
Bank C
CLK4
MultiSynth
50
CLK5
50
+1.8V, +2.5V, +3.3V
VDDOD
Bank D
CLK6
MultiSynth
CLK7
50
50
Figure 6. CMOS Output Driver Configuration
Preliminary Rev. 0.3
13
Si5356
3.10. I2C Interface
Figure 8 for the command format for both read and write
access.
The Si5356 control interface is a 2-wire bus for
bidirectional communication. The bus consists of a
bidirectional serial data line (SDA) and a serial clock
input (SCL). The device operates as a slave device on
the 2-wire bus and is compatible with I2C specifications.
Both lines must be connected to the positive supply via
an external pull-up. Standard-Mode (100 kbps) and
Fast-Mode (400 kbps) operation and 7-bit addressing
are supported as specified in the I2C-Bus Specification
standard. To accommodate multiple Si5356 devices on
the same I2C bus, the Si5356 has pin 3 as I2C_LSB.
The complete 7-bit I2C bus address for the device is
70h or 71h depending upon the state of the I2C_LSB
pin. In binary, this is written as 111 000[I2C_LSB]. See
218
7
6
5
Data is always sent MSB first. Table 7 includes the AC
and DC electrical parameters for the SCL and SDA I/
Os, respectively. The timing specifications and timing
diagram for the I2C bus can be found in the I2C-Bus
Specification standard. SDA timeout support is
supported for compatibility with SMBus interfaces.
The I2C interface is 3.3 V tolerant.
The I2C bus can be operated at a bus voltage of 1.71 to
3.63 V and should have a pullup resistor as
recommended by the I2C-Bus Specification.
LOL
LOS
Clk
LOS
XTAL
4
3
2
SYS
Cal
1
0
System Calibration
(Lock Acquisition)
Loss of Signal
XTAL Input
Loss of Signal
Clock Input
Loss of Lock
Figure 7. Status Register
S
Slv Addr [6:0]
0
A Reg Addr [7:0] A S
Slv Addr [6:0]
1
A Data [7:0] A Data [7:0] N P
Repeated Start Read
S
Slv Addr [6:0]
A Reg Addr [7:0] A P
0
Write Data
S
S
Slv Addr [6:0]
Optional
1 A
Two Command Read
Slv Addr [6:0]
0 A Reg Addr [7:0] A Data [7:0] A
Write
From master to slave
Data [7:0]
A Data [7:0] N P
Read Data
Data [7:0] A
Optional
P
Optional
From slave to master
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
S – START condition
P – STOP condition
Figure 8. I2C/SMBus-Compatible Command Format
14
Preliminary Rev. 0.3
Si5356
3.11. Spread Spectrum
To reduce electro magnetic interference (EMI), the
Si5356 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread
energy across a broader range of frequencies, lowering
system EMI. The modulation rate is the time required to
transition from the maximum spread spectrum
frequency to the minimum spread spectrum frequency
and then back to the maximum frequency.
output clock, any clock frequency, and any spread
amount. Spread spectrum can be enabled or disabled
on a per-bank basis. The device supports center spread
(±0.1% to ±5%) and down spread (–0.1% to –5%). In
addition, the device has extensive on-chip voltage
regulation such that power supply variation does not
influence the device’s spread spectrum clock
waveforms.
The Si5356 implements spread spectrum using
patented MultiSynth technology to achieve previously
unattainable precision in both modulation rate and
spreading magnitude as shown in Figure 9. This
enables the Si5356 to provide “triple A” spread
spectrum. Spread spectrum can be applied to any
The programming of Spread Spectrum is made easy by
using the Si5356 Programmer. Spread spectrum on all
the outputs can be enabled or disabled using the
SSC_DIS pin, or independently for each output bank
through the I2C interface.
0
No spread
-10
-20
Relative Power (dB)
-30
-40
±1.0%
-50
±2.5%
-60
±5.0%
-70
-80
-90
-10%
-8%
-6%
-4%
-2%
0%
2%
4%
6%
8%
10%
Relative Frequency
Figure 9. Configurable Spread Spectrum
Preliminary Rev. 0.3
15
Si5356
3.12. Power Supply Considerations
The Si5356 has two core supply voltage pins (VDD) and four clock output bank supply voltage pins (VDDOA–
VDDOD), enabling the device to be used in mixed supply applications. The Si5356 does not require ferrite beads for
power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power
supply noise on output jitter. Figure 10 shows that the additive jitter created when a significant amount of noise is
applied to the device power supply is very small.
Figure 10. Peak-to-Peak Additive Jitter from 100 mV Sine Wave on Supply
16
Preliminary Rev. 0.3
Si5356
4. Si5356 Registers
For many applications, the Si5356's register values are easily configured using ClockBuilder Desktop (see "3.1.1.
ClockBuilder™ Desktop Software" on page 9). However, for customers interested in using the Si5356 in operating
modes beyond the capabilities available with ClockBuilder, refer to “AN565: Configuring the Si5356A” for a detailed
description of the Si5356 registers and their usage. Also refer to “AN428: Jump Start: In-System, Flash-Based
Programming for Silicon Labs’ Timing Products” for a working application example of register programming using
the Silicon Labs' C8051F301 MCU.
Preliminary Rev. 0.3
17
Si5356
5. Pin Descriptions: Si5356
VDD
GND
CLK0
CLK1
VDDOA
SDA
Top View
24
23
22
21
20
19
XA 1
18 CLK2
XB 2
17 CLK3
16 VDDOB
I2C_LSB 3
GND
GND
CLKIN 4
15 VDDOC
14 CLK4
SSC_DIS 5
9
10
INTR
CLK7
CLK6
11
12
SCL
8
VDDOD
7
VDD
OEB 6
13 CLK5
Note: Center pad must be tied to GND for normal operation.
Table 8. Si5356 Pin Descriptions
Pin # Pin Name
18
I/O
Description
1
XA
I
External Crystal.
If a 25 or 27 MHz crystal is used as the device frequency reference, connect it across
XA and XB. If no input clock is used, this pin should be tied to GND.
2
XB
I
External Crystal.
If a 25 or 27 MHz crystal is used as the device frequency reference, connect it across
XA and XB. If no input clock is used, this pin should be tied to GND.
3
I2C_LSB
I
I2C LSB Address Bit
This pin is the least significant bit of the Si5356 I2C address allowing up to two Si5356
devices to occupy the same I2C bus.
4
CLKIN
I
Single-Ended Input Clock.
If a single-ended clock is used as the device frequency reference, connect it to this pin.
This pin functions as a high-impedance input for CMOS clock signals. The input should
be dc coupled. If a crystal is used as the device frequency reference, this pin should be
tied to GND.
Preliminary Rev. 0.3
Si5356
Table 8. Si5356 Pin Descriptions (Continued)
5
SSC_DIS
I
Spread Spectrum Disable.
This pin allows disabling of the spread spectrum feature on the output clocks. Connect
to 1.2 V to disable spread spectrum on all outputs. Connect to GND to enable spread
spectrum. Note that the maximum voltage level on this pin must not exceed 1.2 V. A
resistor voltage divider is recommended when controlled by a signal greater than 1.2 V.
See the Typical Application Circuit for details.
6
OEB
I
Output Enable (Active Low)
This pin allows disabling the output clocks. Connect to 1.2 V to disable all outputs.
Connect to GND to enable all outputs. Note that the maximum voltage level on this pin
must not exceed 1.2 V. A resistor voltage divider is recommended when controlled by a
signal greater than 1.2 V. See the Typical Application Circuit for details.
7
VDD
8
INTR
O
Interrupt
This pin functions as an maskable interrupt output.
0 = No interrupt
1 = Interrupt present
This pin is open drain and requires an external >1 k pullup resistor.
9
CLK7
O
Output Clock 7.
CMOS output clock. If unused, this pin must be left floating.
10
CLK6
O
Output Clock 6.
CMOS output clock. If unused, this pin must be left floating.
11
VDDOD
12
SCL
I
I2C Serial Clock Input.
13
CLK5
O
Output Clock 5.
CMOS output clock. If unused, this pin must be left floating.
14
CLK4
O
Output Clock 4.
CMOS output clock. If unused, this pin must be left floating.
15
VDDOC
VDD Clock Output Bank C Supply Voltage.
Power supply for clock outputs 4 and 5. May be operated from a 1.8, 2.5 or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK4/5 are not
used, this pin must be tied to pin 7 and/or pin 24.
16
VDDOB
VDD Clock Output Bank B Supply Voltage.
Power supply for clock outputs 2 and 3. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK2/3 are not
used, this pin must be tied to pin 7 and/or pin 24.
17
CLK3
O
Output Clock 3.
CMOS output clock. If unused, this pin must be left floating.
18
CLK2
O
Output Clock 2.
CMOS output clock. If unused, this pin must be left floating.
19
SDA
I/O
I2C Serial Data.
VDD Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should
be located very close to this pin.
VDD Clock Output Bank D Supply Voltage.
Power supply for clock outputs 6 and 7. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK6/7 are not
used, this pin must be tied to pin 7 and/or pin 24.
Preliminary Rev. 0.3
19
Si5356
Table 8. Si5356 Pin Descriptions (Continued)
20
VDDOA
21
CLK1
O
Output Clock 1.
CMOS output clock. If unused, this pin must be left floating.
22
CLK0
O
Output Clock 0.
CMOS output clock. If unused, this pin must be left floating.
23
GND
GND Ground.
Must be connected to system ground. Minimize the ground path impedance for optimal
performance of the device.
24
VDD
VDD Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should
be located very close to this pin.
GND
PAD
GND
GND Ground Pad.
This is the large pad in the center of the package. Device specifications cannot be guaranteed unless the ground pad is properly connected to a ground plane on the PCB. See
"8. Recommended PCB Layout" on page 23 for the PCB pad sizes and ground via
requirements.
20
VDD Clock Output Bank A Supply Voltage.
Power supply for clock outputs 0 and 1. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK0/1 are not
used, this pin must be tied to pin 7 and/or pin 24.
Preliminary Rev. 0.3
Si5356
6. Ordering Guide
Si5356A
I2C Programmable
Any-Frequency 1–200 MHz
Quad Frequency
8-Output Clock Generator
Axxxxx
GMR
Operating Temperature Range:
–40 to +85 oC
Package: 4x4 mm QFN, RoHS6, Pb-free
R = Tape & Reel (ordering option)
When ordering non-tape & reel shipment
media, contact your sales representative
for more information.
A = product revision
xxxxx = 5-digit custom code
assigned to each unique
device configuration. Leave
xxxxx blank for standard
factory default configuration
(Si5356A-A-GMR)
Preliminary Rev. 0.3
21
Si5356
7. Package Outline: 24-Lead QFN
Figure 11. 24-Lead Quad Flat No-Lead (QFN)
Table 9. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
4.00 BSC.
2.35
2.50
e
0.50 BSC.
E
4.00 BSC.
2.65
E2
2.35
2.50
2.65
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Notes:
1.
2.
3.
4.
22
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing per ANSI Y14.5M-1994.
This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Preliminary Rev. 0.3
Si5356
8. Recommended PCB Layout
Table 10. PCB Land Pattern
Dimension
P1
P2
X1
Y1
C1
C2
E
Min
2.50
2.50
0.20
0.75
Nom
2.55
2.55
0.25
0.80
3.90
3.90
0.50
Max
2.60
2.60
0.30
0.85
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no
more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground
plane is allowed if more vias are used to keep the inductance from increasing.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Preliminary Rev. 0.3
23
Si5356
9. Top Marking
Si5356
Xxxxxx
RTTTTT
YYWW
Line
Characters
Description
Line 1
Si5356A
Base part number.
Line 2
Xxxxxx
X = Frequency and configuration code (e.g.: A, B, C, etc.)
xxxxx = Optional NVM code for custom factory-programmed devices;
(characters are not included for blank devices).
See Section “ Document Change List” section in data sheet for more
information.
Line 3
RTTTTT
R = Product revision (A).
TTTTT = Manufacturing trace code.
Line 4
Circle with 0. mm diameter; Pin 1 indicator.
left-justified
YYWW
24
YY = Year.
WW = Work week
Characters correspond to the year and work week of package assembly.
Preliminary Rev. 0.3
Si5356
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2






Improved specification details on input signals.
Added phase and cycle-cycle jitter specifications.
Added thermal resistance junction to case.
Improved application circuits.
Added GND via requirement details.
Added differential CMOS capability.
Revision 0.2 to Revision 0.3







Added Section “3.1. Overview”
Updated Section “3.2. Input Configuration”
Updated Section “3.4. Frequency Configuration”
Added Section “3.5. Configuring the Si5356”
Added Section “4. Si5356 Registers”
Added Section “9. Top Marking”
Updated “Figure 10. Peak-to-Peak Additive Jitter
from 100 mV Sine Wave on Supply”
Preliminary Rev. 0.3
25
Si5356
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ClockBuilder are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
26
Preliminary Rev. 0.3
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