DALC208SC6 скачать даташит

DALC208SC6 скачать даташит
DALC208
Low capacitance diode array
Features
■
Protection of 4 lines
■
Peak reverse voltage: VRRM = 9 V per diode
■
Very low capacitance per diode: C < 5 pF
■
Very low leakage current: IR < 1 µA
1
SOT23-6L
(Plastic)
Benefits
■
Cost-effective solution compared with discrete
solution
■
High efficiency in ESD suppression
■
No significant signal distortion thanks to very
low capacitance
■
High reliability offered by monolithic integration
■
Lower PCB area consumption versus discrete
solution
Figure 1.
Functional diagram
I/O 1
I/O 4
REF 2
REF 1
I/O 2
I/O 3
Complies with the following standards
■
IEC61000-4-2 level 4
■
MIL STD 883G-Method 3015-7: class 3,
human body model
Applications
Where ESD and/or over and undershoot
protection for datalines is required:
■
Sensitive logic input protection
■
Microprocessor based equipment
■
Audio / video inputs
■
Portable electronics
■
Networks
■
ISDN equipment
■
USB interface
March 2008
Description
The DALC208SC6 diode array is designed to
protect components which are connected to data
and transmission lines from over voltages caused
by electrostatic discharge (ESD) or other
transients. It is a rail-to-rail protection device also
suited for overshoot and undershoot suppression
on sensitive logic inputs.
The low capacitance of the DALC208SC6
prevents significant signal distortion.
Rev 7
1/14
www.st.com
14
Characteristics
DALC208
1
Characteristics
Table 1.
Absolute maximum ratings (Tamb = 25 °C)
Value
Unit
IEC61000-4-2, air discharge
IEC61000-4-2, contact discharge
15
8
kV
VRRM
Peak reverse voltage per diode
9
V
ΔVREF
Reference voltage gap between VREF2 and VREF1
9
V
Symbol
VPP
Parameter
VIn max.
Maximum operating signal input voltage
VREF2
V
VIn min.
Minimum operating signal input voltage
VREF1
V
Continuous forward current (single diode loaded)
200
mA
IFRM
Repetitive peak forward current (tp = 5 ms, F = 50 kHz)
700
mA
IFSM
Surge non repetitive forward current - rectangular waveform (See
curve on Figure 3.)
tp = 2.5 µs
tp = 1 µs
tp = 100 µs
6
2
1
A
Tstg
Tj
Storage temperature range
Maximum junction temperature
-55 to + 150
150
°C
°C
Value
Unit
500
°C/W
IF
Table 2.
Thermal resistance
Symbol
Parameter
Junction to ambient (1)
Rth(j-a)
1. Device mounted on FR4 PCB with recommended footprint dimensions.
Table 3.
Electrical characteristics (Tamb = 25 °C)
Symbol
Parameter
Conditions
VF
Forward voltage
IF = 50 mA
IR
Reverse leakage current per diode
VR = 5 V
C
Input capacitance between Line and GND
See Figure 2.
Figure 2.
Typ.
7
Max.
Unit
1.2
V
1
µA
10
pF
Input capacitance measurement
REF2
I/O
VR
+V CC
G
REF1
2/14
REF1 connected to GND
REF2 connected to +Vcc
Input applied :
Vcc = 5 V, Vsign = 30 mV, F = 1 MHz
DALC208
Characteristics
Figure 3.
Maximum non-repetitive peak
Figure 4.
forward current versus rectangular
pulse duration (Tj initial = 25 °C)
Reverse clamping voltage versus
peak pulse current
(Tj initial = 25 °C), typical values.
Rectangular waveform tp = 2.5 ms
Ipp(A)
IFSM(A)
2.0
8
I/O vs
REF1 or
REF2
7
tp=2.5µs
1.0
6
5
4
3
2
1
tp(ms)
0
0.001
0.01
Figure 5.
0.1
I/O vs REF1
or REF2
VCL(V)
1
10
100
1000
0.1
5
Variation of leakage current versus Figure 6.
junction temperature
(typical values)
10
15
20
25
30
Input capacitance versus reverse
applied voltage (typical values)
C(pF)
IR(µA)
100
8.0
7.5
10
7.0
1
6.5
6.0
0.1
F=1MHz
Vsign=30mV
Vref1/ref2=5V
5.5
VR(V)
Tj(°C)
0.01
25
50
Figure 7.
75
100
125
150
5.0
0
1
2
3
4
5
Peak forward voltage drop versus
peak forward current
(typical values),
rectangular waveform tp = 2.5 ms
IFM(A)
10.0
Tj=25°C
Tj=150°C
1.0
I/O vs REF 1
or REF2
VFM(V)
0.1
0
2
4
6
8
10
12
14
16
18
20
3/14
Technical information
2
Technical information
2.1
Surge protection
DALC208
The DALC208SC6 is particularly optimized to perform surge protection based on the rail to
rail topology.
The clamping voltage VCL can be calculated as follow :
VCL+ = VREF2 + VF for positive surges
VCL- = VREF1 - VF for negative surges
with
VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
According to the curve Figure 7 we assume that the value of the dynamic resistance of the
clamping diode is typically Rd = 0.7 Ω and VT = 1.2 V.
For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg=8 kV, Rg=330 Ω), VREF2 = +5 V,
VREF1 = 0 V, and if in first approximation, we assume that : Ip = Vg / Rg ′ 24 A.
So, we find:
–
VCL+′ +23V
–
VCL-′ -18V
Note:
The calculations do not take into account phenomena due to parasitic inductances.
2.2
Surge protection application example
If we consider that the connections from the pin REF2 to VCC and from REF1 to GND are
done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic
inductances of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs, due
to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to Lw.dI/dt.
The dI/dt is calculated as: dI/dt = Ip/tr ′ 24 A/ns
The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 ′ 144V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be :
–
VCL+ = +23 + 144 ′ 167V
–
VCL- = -18 - 144 ′ -162V
We can reduce as much as possible these phenomena with simple layout optimization.
It’s the reason why some recommendations have to be followed (See Section 2.3: How to
ensure good ESD protection).
4/14
DALC208
Technical information
Figure 8.
ESD behavior: parasitic phenomena due to unsuitable layout
Vcl+
167V
Lw
ESD
SURGE
REF2=+Vcc
Vf
Lw di
dt
Lw di
dt
POSITIVE
SURGE
Vcc+Vf
t
I/O
tr=1ns
VI/O
Lw di
dt
di
Vcl+ = Vcc+Vf+Lw dt surge >0
di
surge <0
Vcl- = -Vf- Lw
dt
tr=1ns
t
-Vf
-Lw
NEGATIVE
SURGE
di
dt
REF1=GND
-162V
Vcl-
2.3
How to ensure good ESD protection
While the DALC208SC6 provides a high immunity to ESD surge, an efficient protection
depends on the layout of the board. In the same way, with the rail to rail topology, the track
from the VREF2 pin to the power supply +VCC and from the VREF1 pin to GND must be as short
as possible to avoid over voltages due to parasitic phenomena. See Figure 8.
It’s often harder to connect the power supply near to the DALC208SC6 unlike the ground
thanks to the ground plane that allows a short connection.
To ensure the same efficiency for positive surges when the connections can’t be short
enough, we recommend putting a capacitance of 100 nF close to the DALC208SC6,
between VREF2 and ground, to prevent these kinds of overvoltage disturbances.
See Figure 9.
The addition of this capacitance will allow a better protection by providing a constant voltage
during a surge.
Figure 10, Figure 11, and Figure 12 show the improvement of the ESD protection according
to the recommendations described above.
5/14
Technical information
Figure 9.
DALC208
ESD behavior: optimized layout and Figure 10. ESD behavior: measurement
add of a capacitance of 100 nF
conditions (with coupling
capacitance)
ESD
SURGE
Vcl+
TEST BOARD
Lw
ESD
SURGE
REF2=+Vcc
POSITIVE
SURGE
C=100nF
t
DALC
208
I/O
VI/O
Vcl+ = Vcc+Vf
surge >0
Vcl- =
surge <0
-Vf
t
+5V
NEGATIVE
SURGE
REF1=GND
Vcl-
Figure 11. Remaining voltage after the
DALC208SC6 during positive ESD
surge
Figure 12. Remaining voltage after the
DALC208SC6 during negative ESD
surge
IEC61000-4-2
Air Discharge
(150pF/330Ω)
Vpp=15kV
IEC61000-4-2
Air Discharge
(150pF/330Ω)
Vpp=15kV
Important
A precaution to take is to put the protection device as close as possible to the disturbance
source (generally the connector).
Note:
6/14
The measurements have been done with the DALC208SC6 in open circuit.
DALC208
Crosstalk behavior
3
Crosstalk behavior
3.1
Crosstalk phenomena
Figure 13. Crosstalk phenomena
RG1
Line 1
VG1
RL1
RG2
α 1 VG1 + β12VG2
Line 2
VG2
RL2
DRIVERS
α 2VG2 + β21VG1
RECEIVERS
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12
or β21) increases when the gap across lines decreases, particularly in silicon dice. In the
example in Figure 13 the expected signal on load RL2 is α2VG2, in fact the real voltage at this
point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the
crosstalk phenomenon of line 1 on line 2. This phenomenon has to be taken into account
when the drivers impose fast digital data or high frequency analog signals in the disturbing
line. The disturbed line will be more affected if it works with low voltage signal or high load
impedance (few kΩ). The following sections give the value of both digital and analog
crosstalk.
3.2
Digital crosstalk
Figure 14. Digital crosstalk measurements
+5V
+5V
74HC04
Figure 15. Digital crosstalk results
+5V
100nF
74HC04
Line 1
Square
Pulse
Generator
5KHz
+5V
VG1
Line 2
β21 VG1
DALC208SC6
Figure 14 shows the measurement circuit used to quantify the crosstalk effect in a classical
digital application. Figure 15 shows that in such a condition: signal from 0 V to 5 V and a rise
time of 5 ns, the impact on the disturbed line is less than 100mV peak to peak. No data
disturbance was noted on the concerned line. The same results were obtained with falling
edges.
7/14
Crosstalk behavior
DALC208
Note:
The measurements have been done in the worst case i.e. on two adjacent cells (I/O1 and
I/O4).
3.3
Analog crosstalk
Figure 16. Analog crosstalk measurements
TRACKING GENERATOR
SPECTRUM ANALYSER
TEST BOARD
50Ω
DALC
208
+5V
50Ω
Vg
Vin
Vout
C=100nF
Figure 16 shows the measurement circuit for the analog application. For the usual frequency
range of analog signals (up to 100MHz) the effect on disturbed line is less than -45 dBm.
See Figure 17.
Figure 17. Analog crosstalk results
Figure 18. DALC208SC6 attenuation
dBm
0
dBm
0
-20
-10
-40
-60
-20
-80
-100
1
10
100
f(MHz)
1,000
-30
1
10
100
1,000
f(MHz)
As the DALC208SC6 is designed to protect high speed data lines, it must ensure a good
transmission of operating signals. The attenuation curve give such an information.
Figure 18 shows that the DALC208SC6 is well suitable for data line transmission up to
100 Mbit/s while it works as a filter for undesirable signals such as GSM carrier (900 MHz).
8/14
DALC208
4
Application examples
Application examples
Figure 19. Video line protection
+Vcc
100nF
Pin N°
Signal
1
2
RED VIDEO
GREEN VIDEO
or COMPOSITE SYNC with GREEN VIDEO
BLUE VIDEO
GROUND
DDC (Display Data Channel) GROUND
RED GROUND
GREEN GROUND
BLUE GROUND
NC
SYNC GROUND
GROUND
SDA (Sérial Data)
HORIZONTAL SYNC
or COMPOSITE SYNC
VERTICAL SYNC (VCLK)
SCL (Serial Clock)
DALC
208
5
3
4
5
6
7
8
9
10
11
12
13
1
15
+Vcc
DALC
208
100nF
14
15
Figure 20. T1/E1 protection
Figure 21. USB port protection
VBUS
USB
TRANSCEIVER
D+
D-
Tx
GND
SMP75-8
15k
DATA
+Vcc
100nF
DALC
208
15k
+V
TRANSCEIVER
100nF
VBUS
D+
Rx
DGND
SMP75-8
DALC
208
+V
1.5k
(1)
(1) Full speed
only
(2) Low speed
only
1.5k
(2)
USB
TRANSCEIVER
Figure 22. Another way to connect the DALC208SC6
I/O1
I/O2
DALC208
I/O3
GND
I/O4
Note It is absolutely necessary to connect
the pin 5 (REF1) to GND !
9/14
PSpice model
5
DALC208
PSpice model
Figure 23 shows the PSpice model of one DALC208SC6 cell. In this model, the diodes are
defined by the PSpice parameters given in Table 4.
Figure 23. PSpice model of one DALC208SC6 Figure 24. PSpice model simulation: surge > 0
cell
IEC 61000-4-2 contact discharge
response
Vref2
Current (A) / Voltage (V)
60
Current
Surge
0.8nH
50
0.3Ω
I/O
Voltage
40
Dpos
0.8nH 0.3Ω
30
I/O
Dneg
20
0.5Ω
10
1.45nH
0
0
50
t(ns)
Vref1
Note:
100
This simulation model is available only for an ambient temperature of 27 °C. The simulations
done (Figure 24, Figure 25 and Figure 26) show that the PSpice model is close to the
product behavior.
Figure 25. PSpice model simulation: surge < 0 Figure 26. Attenuation comparison
IEC61000-4-2 contact discharge
response
Current (A) / Voltage (V)
0
dBm
0
Current
Surge
-10
Measured
PSpice
I/O
Voltage
-20
-30
-10
-20
-40
-50
10/14
-30
0
50
t(ns)
100
1
10
100
f(MHz)
1,000
DALC208
PSpice model
Table 4.
PSpice parameter
Parameter
DPOS
DNEG
BV
9
9
CJO
7p
7p
IBV
1u
1u
IKF
28.357E-3
1000
IS
118.78E-15
5.6524E-9
ISR
100E-12
472.3E-9
M
0.3333
0.3333
N
1.3334
2.413
NR
2
2
RS
0.68377
0.71677
VJ
0.6
0.6
11/14
Package information
6
DALC208
Package information
●
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Table 5.
SOT23-6L dimensions
Dimensions
Ref.
Millimeters
Inches
A
Min. Typ. Max.
E
e
b
D
e
A2
Typ.
Max.
A
0.90
A1
0
A2
0.90
1.30 0.035
0.051
b
0.35
0.50 0.014
0.020
c
0.09
0.20 0.004
0.008
D
2.80
3.05
0.11
0.118
E
1.50
1.75 0.059
0.069
e
c
Min.
1.45 0.035
0.057
0.10
0.004
0
0.95
0.037
A1
θ
L
H
2.60
3.00 0.102
0.118
L
0.10
0.60 0.004
0.024
θ
0°
H
10°
Figure 27. Footprint (dimensions in mm)
0.60
1.20
0.95
3.50
12/14
2.30
1.10
0°
10°
DALC208
7
Ordering information
Ordering information
Table 6.
8
Ordering information
Order code
Marking
Package
Weight
Base qty
Packing mode
DALC208SC6
DALC
SOT23-6L
16.7 mg
3000
Tape and reel
Revision history
Table 7.
Document revision history
Date
Revision
Changes
Feb-2002
5C
28-Oct-2004
6
SOT23-6L package dimensions change for reference “D” from 3.0
millimeters (0.118 inches) to 3.05 millimeters (0.120 inches).
20-Mar-2008
7
Reformatted to current standard. Added ECOPACK paragraph.
Last update.
13/14
DALC208
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