DS1306 Serial Alarm Real-Time Clock FEATURES

DS1306 Serial Alarm Real-Time Clock  FEATURES

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FEATURES

§ Real-Time Clock (RTC) Counts Seconds,

Minutes, Hours, Date of the Month, Month,

Day of the Week, and Year with Leap-Year

Compensation Valid Up to 2100

§ 96-Byte, Battery-Backed NV RAM for Data

Storage

§ Two Time-of-Day Alarms, Programmable on

Combination of Seconds, Minutes, Hours, and Day of the Week

§ 1Hz and 32.768kHz Clock Outputs

§ Supports Motorola SPI

(Serial Peripheral

Interface) Modes 1 and 3 or Standard 3-Wire

Interface

§ Burst Mode for Reading/Writing Successive

Addresses in Clock/RAM

§ Dual-Power Supply Pins for Primary and

Backup Power Supplies

§ Optional Trickle Charge Output to Backup

Supply

§ 2.0V to 5.5V Operation

§ Optional Industrial Temperature Range:

-40°C to +85°C

§ Available in Space-Efficient, 20-Pin TSSOP

Package

§ Underwriters Laboratory (UL) Recognized

DS1306

Serial Alarm Real-Time Clock

PIN CONFIGURATIONS

V

CC2

V

BAT

X1

N.C.

1

2

3

4

20

19

18

17

V

CC1

N.C.

32kHz

V

CCIF

X2

5 16 SDO

N.C.

6 15 SDI

INT0

INT1

1Hz

GND

V

CC2

V

BAT

X1

X2

INT0

INT1

1Hz

GND

7

8

9

10

14

13

12

11

TSSOP (4.4mm)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SCLK

CE

SERMODE

V

CC1

N.C.

32kHz

V

CCIF

SDO

SDI

SCLK

CE

SERMODE

DIP (300 mils)

Package Dimension Information can be found at: www.maxim-ic.com/DallasPackInfo

TYPICAL OPERATING CIRCUIT

SPI is a trademark of Motorola, Inc.

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DS1306

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE TOP MARK*

DS1306

DS1306+

DS1306N

DS1306N+

DS1306E+

0°C to +70°C 16 DIP (300 mils)

0°C to +70°C 16 DIP (300 mils)

-40°C to +85°C 16 DIP (300 mils)

0°C to +70°C 16 DIP (300 mils)

DS1306

DS1306 +

DS1306N

DS1306N +

0°C to +70°C 20 TSSOP (173 mils) DS1306 +

DS1306EN+ -40°C to +85°C 20 TSSOP (173 mils) DS1306N +

DS1306EN+T&R -40°C to +85°C 20 TSSOP (173 mils) DS1306N +

DS1306E+T&R

DS1306E

0°C to +70°C

0°C to +70°C

20 TSSOP (173 mils) DS1306 +

20 TSSOP (173 mils) DS1306

DS1306EN -40°C to +85°C 20 TSSOP (173 mils) DS1306N

DS1306EN/T&R -40°C to +85°C 20 TSSOP (173 mils) DS1306N

DS1306E/T&R 0°C to +70°C 20 TSSOP (173 mils) DS1306

+ Denotes a lead-free/RoHS-compliant device.

* An “N” on the top mark indicates an industrial device.

PIN DESCRIPTION

PIN

TSSOP DIP

NAME FUNCTION

1 1 V

CC2

Backup Power Supply. This is the secondary power supply pin. In systems using the trickle charger, the rechargeable energy source is connected to this pin.

2 2 V

BAT

Battery Input for Any Standard +3V Lithium Cell or Other Energy

Source. If not used, V

BAT

must be connected to ground. Diodes must not be placed in series between V

BAT

and the battery, or improper operation will result. UL recognized to ensure against reverse charging current when used in conjunction with a lithium battery. See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm

.

Connections for Standard 32.768kHz Quartz Crystal. The internal

3 3 X1 capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58, “Crystal Considerations with Dallas Real-Time Clocks.” The DS1306 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

7 5 INT0

Active-Low Interrupt 0 Output. The INT0 pin is an active-low output of the DS1306 that can be used as an interrupt input to a processor. The

INT0 pin can be programmed to be asserted by Alarm 0. The INT0 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT0 pin operates when the

DS1306 is powered by V

CC1

, V

CC2

, or V

BAT

. The INT0 pin is an open-drain output and requires an external pullup resistor.

Interrupt 1 Output. The INT1 pin is an active high output of the DS1306 that can be used as an interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1. When an alarm condition is present, only when the DS1306 is powered by V

CC2 pin is internally pulled up to V internally pulled low.

CC2

or V

BAT

or V

BAT

. When active, the INT1

. When inactive, the INT1 pin is

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DS1306

PIN DESCRIPTION (continued)

PIN

NAME FUNCTION

TSSOP DIP

1Hz Output. The 1Hz pin provides a 1Hz square wave output. This output is active when the 1 Hz bit in the control register is a logic 1. Both INT0 and clock continue to run regardless of the level of V

CC source is present).

(as long as a power

Serial Interface Mode. The SERMODE pin offers the flexibility to choose

3-wire communication is selected. When connected to V

CC communication is selected.

, SPI

Chip Enable. The chip enable signal must be asserted high during a read or pulldown resistor (typical).

Serial Data In. When SPI communication is selected, the SDI pin is the single I/O pin when tied together).

Serial Data Out. When SPI communication is selected, the SDO pin is the

17 14 V

CCIF

20 16 V

CC1

4, 6, 13,

19 single I/O pin when tied together). V

CCIF

provides the logic high level.

Interface Logic Power-Supply Input. The V

CCIF

pin allows the DS1306 to drive SDO and 32kHz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to 3V logic in mixed supply systems. This pin is physically connected to the source connection of the pchannel transistors in the output buffers of the SDO and 32kHz pins.

CCIF

provides the logic high level.

Primary Power Supply. DC power is provided to the device on this pin.

V

CC1

is the primary power supply.

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DS1306

DESCRIPTION

The DS1306 serial alarm real-time clock (RTC) provides a full binary coded decimal (BCD) clock calendar that is accessed by a simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24hour or 12-hour format with AM/PM indicator. In addition, 96 bytes of NV RAM are provided for data storage.

An interface logic-power supply input pin (V

CCIF

) allows the DS1306 to drive SDO and 32kHz pins to a level that is compatible with the interface logic. This allows an easy interface to 3V logic in mixed supply systems. The DS1306 offers dual-power supplies as well as a battery-input pin. The dual-power supplies support a programmable trickle charge circuit that allows a rechargeable energy source (such as a super cap or rechargeable battery) to be used for a backup supply. The V

BAT

pin allows the device to be backed up by a non-rechargeable battery. The DS1306 is fully operational from 2.0V to 5.5V.

Two programmable time-of-day alarms are provided by the DS1306. Each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be inserted into one or more fields if it is desired for them to be ignored for the alarm condition. A 1Hz and a

32kHz clock output are also available.

The DS1306 supports a direct interface to SPI serial data ports or standard 3-wire interface. An easy-touse address and data format is implemented in which data transfers can occur 1 byte at a time or in multiple-byte burst mode.

OPERATION

The block diagram in Figure 1 shows the main elements of the serial alarm RTC. The following paragraphs describe the function of each pin.

Figure 1. BLOCK DIAGRAM

1Hz

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DS1306

RECOMMENDED LAYOUT FOR CRYSTAL

Local ground plane (Layer 2) crystal

X1

X2

GND

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application

Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.

CLOCK, CALENDAR, AND ALARM

The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are illustrated in Figure 2. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. Note that some bits are set to 0. These bits always read 0 regardless of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved. These registers always read 0 regardless of how they are written. The contents of the time, calendar, and alarm registers are in the BCD format.. Values in the day register that correspond to the day of the week are user-defined, but must be sequential (e.g. if 1 equals Sunday, 2 equals Monday and so on). The day register increments at midnight. Illogical time and date entries result in undefined operation.

WRITING TO THE CLOCK REGISTERS

The internal time and date registers continue to increment during write operations. However, the countdown chain is reset when the seconds register is written. Writing the time and date registers within one second after writing the seconds register ensures consistent data.

Terminating a write before the last bit is sent aborts the write for that byte.

READING FROM THE CLOCK REGISTERS

Buffers are used to copy the time and date register at the beginning of a read. When reading in burst mode, the user copy is static while the internal registers continue to increment.

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DS1306

Figure 2. RTC REGISTERS AND ADDRESS MAP

HEX ADDRESS

READ

WRITE

Bit

7

00H 80H SEC

01H 81H

Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

MIN

P

SEC

MIN

02H 82H A 10-HR HOURS

24 10

DAY

DATE

MONTH

RANGE

00–59

00–59

01–12 + P/A

00–23

01–07

1–31

01–12

06H 86H

07H

08H

87H

88H

M

M

09H 89H

10-YEAR

10-SEC ALARM 0

10-MIN ALARM 0

P

A

24 10

10-HR

YEAR

SEC ALARM 0

MIN ALARM 0

HOUR ALARM 0

00–99

00–59

00–59

01–12 + P/A

00–23

0AH 8AH M 0 0 0 0 DAY ALARM 0 01–07

0BH

0CH

8BH

8CH

M 10 SEC ALARM 1

M 10 MIN ALARM 1

P

0DH 8DH A

24 10

10-HR

0EH 8EH M 0 0 0

0

SEC ALARM 1

MIN ALARM 1

HOUR ALARM 1

DAY ALARM 1

00–59

00–59

01–12 + P/A

00–23

01–07

0FH 8FH

10H 90H

11H 91H

12–1FH 92–9FH

TRICKLE CHARGER REGISTER

RESERVED

20–7FH

A0–

FFH

96-BYTES USER RAM —

Note: Range for alarm registers does not include mask’m’ bits.

The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the

12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours).

The DS1306 contains two time-of-day alarms. Time-of-day alarm 0 can be set by writing to registers 87h to 8Ah. Time-of-day Alarm 1 can be set by writing to registers 8 Bh to 8 Eh. Bit 7 of each of the time-ofday alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time-of-day alarm only occurs once per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time-of-day alarm registers. An alarm is generated every day when bit 7 of the day alarm register is set to a logic 1. An alarm is generated every hour when bit 7 of the day and hour alarm registers is set to a logic 1. Similarly, an alarm is generated every minute when bit 7 of the day, hour, and

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DS1306 minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and seconds alarm registers is set to a logic 1, an alarm occurs every second.

During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated.

Table 1. TIME-OF-DAY ALARM MASK BITS

ALARM REGISTER MASK BITS (BIT 7)

FUNCTION

SECONDS MINUTES HOURS DAYS

0

0

1

0

0

0

1

1

1

0

1

1

1

1

1

1

Alarm once per second

Alarm when seconds match

Alarm when minutes and seconds match

Alarm hours, minutes, and seconds match

0 0 0 0 Alarm day, hours, minutes and seconds match

SPECIAL PURPOSE REGISTERS

The DS1306 has three additional registers (control register, status register, and trickle charger register) that control the real-time clock, interrupts, and trickle charger.

CONTROL REGISTER (READ 0FH, WRITE 8FH)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

WP (Write Protect) – Before any write operation to the clock or RAM, this bit must be logic 0. When high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the control register. Upon initial power-up, the state of the WP bit is undefined. Therefore, the WP bit should be cleared before attempting to write to the device. When WP is set, it must be cleared before any other control register bit can be written.

1Hz (1Hz Output Enable) – This bit controls the 1Hz output. When this bit is a logic 1, the 1Hz output is enabled. When this bit is a logic 0, the 1Hz output is high-Z.

AIE0 (Alarm Interrupt Enable 0) – When set to a logic 1, this bit permits the interrupt 0 request flag

(IRQF0) bit in the status register to assert

INT0

. When the AIE0 bit is set to logic 0, the IRQF0 bit does not initiate the

INT0

signal.

AIE1 (Alarm Interrupt Enable 1) – When set to a logic 1, this bit permits the interrupt 1 request flag

(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal, and the INT1 pin is set to a logic 0 state.

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DS1306

STATUS REGISTER (READ 10H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

IRQF0 (Interrupt 0 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the

INT0

pin goes low. IRQF0 is cleared when the address pointer goes to any of the Alarm 0 registers during a read or write. IRQF0 is activated when the device is powered by V

CC1

, V

CC2

, or V

BAT

.

IRQF1 (Interrupt 1 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current time has matched the Alarm 1 registers. If the AIE1 bit is also a logic 1, the INT1 pin generates a 62.5ms active-high pulse. IRQF1 is cleared when the address pointer goes to any of the alarm 1 registers during a read or write. IRQF1 is activated only when the device is powered by V

CC2

or V

BAT

.

TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)

This register controls the trickle charge characteristics of the DS1306. The simplified schematic of Figure

3 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits 4–7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns disable the trickle charger. The DS1306 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2–3) select whether one diode or two diodes are connected between V

CC1

and V

CC2

. The diode select (DS) bits (bits 2–3) select whether one diode or two diodes are connected between V connected between V in Table 2.

CC1

and V

CC2

CC1

and V

CC2

. The resistor select (RS) bits select the resistor that is

. The resistor and diodes are selected by the RS and DS bits as shown

Figure 3. PROGRAMMABLE TRICKLE CHARGER

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DS1306

Table 2. TRICKLE CHARGER RESISTOR AND DIODE SELECT

TCS

Bit 7

TCS

Bit 6

TCS

Bit 5

TCS

Bit 4

DS

Bit 3

DS

Bit 2

RS

Bit 1

RS

Bit 0

FUNCTION

X X X X X X 0 0 Disabled

X X X X 0 0 X X

X X X X 1 1 X X

Disabled

Disabled

1 0 1 0 0 1 0 1 1 2kΩ

1 0 1 0 0 1 1 0 1 4kΩ

1 0 1 0 0 1 1 1 1 8kΩ

1 0 1 0 1 0 0 1 2 2kΩ

1 0 1 0 1 0 1 0 2 4kΩ

1 0 1 0 1 0 1 1 2 8kΩ

If RS is 00, the trickle charger is disabled independently of TCS.

Diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 5V is applied to V connected to V

CC2

CC1

and a super cap is

. Also assume that the trickle charger has been enabled with one diode and resister R1 between V

CC1

and V

CC2

. The maximum current I

MAX

would, therefore, be calculated as follows:

I

MAX

= (5.0V - diode drop) / R1

» (5.0V - 0.7V) / 2kΩ » 2.2mA

As the super cap charges, the voltage drop between V

CC1

and V

CC2

decreases and, therefore, the charge current decreases.

POWER CONTROL

Power is provided through the V

CC1

, V

CC2

, and V

BAT

pins. Three different power supply configurations are illustrated in Figure 4. Configuration 1 shows the DS1306 being backed up by a non-rechargeable energy source such as a lithium battery. In this configuration, the system power supply is connected to

V

CC1

and V

CC2

is grounded. When V

CC

falls below V

BAT

the device switches into a low-current battery backup mode. Upon power-up, the device switches from V

BAT

to V

CC

when V

CC

is greater than

V

BAT

+ 0.2V. The device is write-protected whenever it is switched to V

BAT

.

Configuration 2 illustrates the DS1306 being backed up by a rechargeable energy source. In this case, the

V

BAT

pin is grounded, V

CC1

is connected to the primary power supply, and V

CC2

is connected to the secondary supply (the rechargeable energy source). The DS1306 operates from the larger of V

CC1

or

V

V

CC2

CC2

. When V

, V

CC2

CC1

is greater than V

CC2

+ 0.2V (typical), V

CC1

powers the DS1306. When V

CC1

is less than

powers the DS1306. The DS1306 does not write-protect itself in this configuration.

Configuration 3 shows the DS1306 in battery-operate mode, where the device is powered only by a single battery. In this case, the V

CC1

and V

BAT

pins are grounded and the battery is connected to the V

CC2

pin.

Only these three configurations are allowed. Unused supply pins must be grounded.

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Figure 4. POWER SUPPLY CONFIGURATIONS

CONFIGURATION 1: BACKUP SUPPLY IS

NONRECHARGEABLE LITHIUM BATTERY

DS1306

NOTE: DEVICE IS WRITE-PROTECTED IF V

CC

< V

CCTP

.

CONFIGURATION 2: BACKUP SUPPLY IS A

RECHARGEABLE BATTERY OR SUPER

CAPACITOR

NOTE: DEVICE DOES NOT PROVIDE AUTOMATIC WRITE PROTECTION.

CONFIGURATION 3: BATTERY OPERATE

MODE

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DS1306

SERIAL INTERFACE

The DS1306 offers the flexibility to choose between two serial interface modes. The DS1306 can communicate with the SPI interface or with a standard 3-wire interface. The interface method used is determined by the SERMODE pin. When this pin is connected to V

CC

, SPI communication is selected.

When this pin is connected to ground, standard 3-wire communication is selected.

SERIAL PERIPHERAL INTERFACE (SPI)

The serial peripheral interface (SPI) is a synchronous bus for address and data transfer and is used when interfacing with the SPI bus on specific Motorola microcontrollers such as the 68HC05C4 and the

68HC11A8. The SPI mode of serial communication is selected by tying the SERMODE pin to V

CC

.

Four pins are used for the SPI. The four pins are the SDO (serial data out), SDI (serial data in), CE (chip enable), and SCLK (serial clock). The DS1306 is the slave device in an SPI application, with the microcontroller being the master.

The SDI and SDO pins are the serial data input and output pins for the DS1306, respectively. The CE input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data movement between the master (microcontroller) and the slave (DS1306) devices.

The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus. The inactive clock polarity is programmable in some microcontrollers. The DS1306 determines on the clock polarity by sampling SCLK when CE becomes active. Therefore either SCLK polarity can be accommodated. Input data (SDI) is latched on the internal strobe edge and output data (SDO) is shifted out on the shift edge (Figure 5). There is one clock for each bit transferred. Address and data bits are transferred in groups of eight.

Figure 5. SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER

CLOCK POLARITY (CPOL)

CPOL = 1

CPOL = 0

CE

SCLK

SCLK

SHIFT DATA OUT (READ)

SHIFT DATA OUT (READ)

DATA LATCH (WRITE)

DATA LATCH (WRITE)

NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.

NOTE 2: CPOL IS A BIT THAT IS SET IN THE MICROCONTROLLER’S CONTROL REGISTER.

NOTE 3: SDO REMAINS AT HIGH-Z UNTIL 8 BITS OF DATA ARE READY TO BE SHIFTED OUT DURING A READ.

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DS1306

ADDRESS AND DATA BYTES

Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data output (SDO). Any transfer requires the address of the byte to specify a write or read to either a RTC or

RAM location, followed by one or more bytes of data. Data is transferred out of the SDO for a read operation and into the SDI for a write operation (Figures 6 and 7).

Figure 6. SPI SINGLE-BYTE WRITE

* SCLK CAN BE EITHER POLARITY.

Figure 7. SPI SINGLE-BYTE READ

* SCLK CAN BE EITHER POLARITY.

The address byte is always the first byte entered after CE is driven high. The most significant bit (A7) of this byte determines if a read or write takes place. If A7 is 0, one or more read cycles occur. If A7 is 1, one or more write cycles occur.

Data transfers can occur one byte at a time or in multiple-byte burst mode. After CE is driven high an address is written to the DS1306. After the address, 1 or more data bytes can be written or read. For a single-byte transfer, one byte is read or written and then CE is driven low. For a multiple-byte transfer, however, multiple bytes can be read or written to the DS1306 after the address has been written. Each read or write cycle causes the RTC register or RAM address to automatically increment. Incrementing continues until the device is disabled. When the RTC is selected, the address wraps to 00h after incrementing to 1Fh (during a read) and wraps to 80h after incrementing to 9Fh (during a write). When the RAM is selected, the address wraps to 20h after incrementing to 7Fh (during a read) and wraps to

A0h after incrementing to FFh (during a write).

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Figure 8. SPI MULTIPLE-BYTE BURST TRANSFER

DS1306

READING AND WRITING IN BURST MODE

Burst mode is similar to a single-byte read or write, except that CE is kept high and additional SCLK cycles are sent until the end of the burst. The clock registers and the user RAM may be read or written in burst mode. When accessing the clock registers in burst mode, the address pointer will wrap around after reaching 1Fh (9Fh for writes). When accessing the user RAM in burst mode, the address pointer wraps around after reaching 7Fh (FFh for writes).

3-WIRE INTERFACE

The 3-wire interface mode operates similar to the SPI mode. However, in 3-wire mode there is one I/O instead of separate data in and data out signals. The 3-wire interface consists of the I/O (SDI and SDO pins tied together), CE, and SCLK pins. In 3-wire mode, each byte is shifted in LSB first, unlike SPI mode, where each byte is shifted in MSB first.

As is the case with the SPI mode, an address byte is written to the device followed by a single data byte or multiple data bytes. Figure 9 illustrates a read and write cycle. In 3-wire mode, data is input on the rising edge of SCLK and output on the falling edge of SCLK.

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Figure 9. 3-WIRE SINGLE BYTE TRANSFER

CE

SCLK

I/O*

CE

SCLK

I/O*

A0 A1 A2 A3 A4 A5 A6 0

A0 A1 A2 A3 A4 A5 A6 1

SINGLE-BYTE READ

D0 D1 D2 D3 D4 D5 D6 D7

SINGLE-BYTE WRITE

D0 D1 D2 D3 D4 D5 D6 D7

NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST.

*I/O IS SDI AND SDO TIED TOGETHER.

DS1306

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DS1306

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +7.0V

Storage Temperature Range……………………………………………………………….-55

°C to +125°C

Soldering Temperature.……………………………….See IPC/JEDEC Standard J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.

OPERATING RANGE

RANGE TEMP V

CC

(V)

Commercial 0°C to +70°C 2.0 to 5.5 V

CC1

or V

CC2

Industrial -40°C to +85°C 2.0 to 5.5 V

CC1

or V

CC2

RECOMMENDED DC OPERATING CONDITIONS

(T

A

= Over the operating range, unless otherwise specified.)

MIN MAX

Supply Voltage

V

CC1

, V

CC2

Logic 1 Input

V

CC1

, V

CC2

2.0 5.5 V

Logic 0 Input

V

BAT

Battery Voltage

V

IH

V

IL

V

BAT

V

CC

V

CC

= 2.0V

= 5V

2.0 V

CC

+ 0.3 V

-0.3

+0.3

+0.8

V

2.0 5.5 V

V

CCIF

Supply Voltage V

CCIF

2.0 5.5 V 10

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DS1306

DC ELECTRICAL CHARACTERISTICS

(T

A

= Over the operating range, unless otherwise specified.)

Input Leakage

Output Leakage

Logic 0 Output

Logic 1 Output

I

OL

I

OL

I

OH

I

OH

= 1.5mA

= 4.0mA

= -0.4mA

= -1.0mA

Logic 1 Output Current

(INT1 pin)

V

CC1

Active Supply Current

V

CC1

Timekeeping Current

V

CC2

Active Supply Current

V

CC2

Timekeeping Current

Battery Timekeeping Current

Battery Timekeeping Current

(IND)

V

CC

Trip Point

Trickle Charge Resistors

I

LI

-100

I

LO

-1

V

V

I

OL

OH

OH

,

INT1

V

CC

V

CC

= 2.0

= 5V

V

CCIF

V

CCIF

(V

CC2

= 2.0V

= 5V

-0.3V

, V

BAT

)

1.6

2.4

0.4

0.4

-100

V

V mA

I

I

I

I

CC1A

CC1T

CC2A

CC2T

V

CC1

V

CC1

V

CC1

V

CC1

V

V

CC2

CC2

= 2.0V

= 5V

= 2.0V

= 5V

= 2.0V

= 5V

V

CC2

= 2.0V

V

CC2

= 5V

0.425

1.28

25.3

81

0.4

1.2

0.4

1 mA mA

1, 7

1, 8

I

BAT

V

BAT

= 3V 550 nA 9

I

BAT

V

BAT

= 3V nA 9

V

CCTP

R1

R2

R3

800

V

BAT

50

-

2

4

8

V

BAT

+

200 mV k

W

V

TD

0.7 V

Trickle Charger Diode Voltage

Drop

CAPACITANCE

(T

A

= +25

°C)

Input Capacitance

Output Capacitance

Crystal Capacitance

C

I

C

O

C

X

10

15

6 pF pF pF

16 of 21

3-WIRE AC ELECTRICAL CHARACTERISTICS

(T

A

= Over the operating range, unless otherwise specified.) (Figure 10 and Figure 11)

Data to CLK Setup

CLK to Data Hold

CLK to Data Delay

CLK Low Time

CLK High Time

CLK Frequency

CLK Rise and Fall

CE to CLK Setup

CLK to CE Hold

CE Inactive Time

CE to Output High-Z

SCLK to Output High-Z t t t

DC

CDH

CDD t

CLK t

R

, t

F t t t t t

CL t

CH t

CC

CCH

CWH

CDZ

CCZ

V

CC

V

CC

V

CC

V

CC

= 2.0V

= 5V

= 2.0V

= 5V

= 2.0V V

CC

V

CC

V

CC

V

CC

= 5V

= 2.0V

= 5V

= 2.0V V

CC

V

CC

V

CC

V

CC

= 5V

= 2.0V

= 5V

= 2.0V V

CC

V

CC

V

CC

V

CC

= 5V

= 2.0V

= 5V

= 2.0V V

CC

V

CC

V

CC

V

CC

= 5V

= 2.0V

= 5V

= 2.0V V

CC

V

CC

V

CC

V

CC

= 5V

= 2.0V

= 5V

4

1

240

60

4

1

200

50

280

70

1000

250

1000

250

DC

500

280

70

280

70

800

200

0.6

2.0

2000 ns

DS1306 ns 4 ns 4

MHz 4 ns ms

4 ns 4 ms

3, 4, 5

4

17 of 21

Figure 10. TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER

DS1306

* I/O IS SDI AND SDO TIED TOGETHER.

Figure 11. TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER

* I/O IS SDI AND SDO TIED TOGETHER.

18 of 21

DS1306

SPI AC ELECTRICAL CHARACTERISTICS

(T

A

= Over the operating range, unless otherwise specified.)

Data to CLK Setup

CLK to Data Hold

CLK to Data Delay

CLK Low Time

CLK High Time

CLK Frequency

CLK Rise and Fall

CE to CLK Setup

CLK to CE Hold

CE Inactive Time

CE to Output High-Z t

CLK t

R

, t

F t

CC t

CCH t

CWH t

DC t

CDH t

CDD t

CL t

CH t

CDZ

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

V

CC

= 2.0V

V

CC

= 5V

1000

250

1000

250

DC

4

1

240

60

4

1

200

50

280

70

0.6

2.0

2000

500

800

200

280

70 ns 3, 4, 5 ns 4 ns 4

MHz 4 ns ms

4 ns 4 ms

4

19 of 21

Figure 12. TIMING DIAGRAM: SPI READ DATA TRANSFER

DS1306

* SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1.

Figure 13. TIMING DIAGRAM: SPI WRITE DATA TRANSFER

* SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1.

20 of 21

DS1306

NOTES:

1) I

CC1T

and I

CC2T

are specified with CE set to a logic 0.

2) I

CC1A

and I

CC2A

are specified with CE = V

CC

, SCLK = 2MHz at V

CC

= 5V; SCLK = 500kHz at V

CC

=

2.0V, V

IL

= 0V, V

IH

= V

CC

.

3) Measured at V

IH

= 2.0V or V

IL

= 0.8V and 10ms maximum rise and fall time.

4) Measured with 50pF load.

5) Measured at V

OH

= 2.4V or V

OL

= 0.4V.

6) V

CC

= V

CC1

, when V

CC1

> V

CC2

+ 0.2V (typical); V

CC

= V

CC2

, when V

CC2

> V

CC1

.

7) V

CC2

= 0V.

8) V

CC1

= 0V.

9) V

CC1

< V

BAT

.

10) V

CCIF

must be less than or equal to the largest of V

CC1

, V

CC2

, and V

BAT

.

21 of 21

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Ma xi m I nt e gr at e d Pr o du ct s, 1 2 0 S a n G abr i el Dr i ve, S un n yv al e, C A 94 0 8 6 40 8- 7 37- 7 60 0

© 2005 Maxim Integrated Products · Printed USA

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

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