HP 13255

G~APrlICS ~-CONTkULLlR MUUUL~

Manual

~art ~o. Ij2~5-~1125 t<EVIS~i.)

,..011C£

The information contained in thlS document is suoject to cnanQe

\lw'ithout notlce.

Irt~~LE'l'l-PACr<AHJj ~~Ar\t.5

i.'"

A Tr..:td AL,

NU

~Af<t'A!'4T't lJ1" Af-.'{

I<L~U ~11t

1

NC LUD LI4 G, tiUT j~OT

L 1,...1 'fED TO ThE. 11': P L 1 fo..u f'4

AkRAri T 1 £5

IJr

M£~CHANTABILlrY

ANO fllNESS fUR A

~ANTICULAR PU~POS~. hewlett-Pac~ara

Shall not be liaole tor errors containeo nerein or tor lncidental or consequelltial damages 1n connection

~itn the turni~ning, pertormance, lOr use

Ot tnis material.

Tnis docun.ent contains proprletary intormatlon wnict1

is

protecteci oy cop y rig h t •

A 11 r 1 q h t S are res e r ve d •

I\:

0 par t o t t n i s doc u men t ill a y

0 e pnotocopiea or reproduced

~ltnout the prior wrltten consent of Hewlett-

PacKard Company.

NOT~: tnis aocument is part ot the

~b4XX

DATA f~~MINAL product serles Technical Intormatlon PacKage lHP

13255).

132~5

Graphics

~-controller

MOdule

13255-~11~~/02

~EV MAY-04-7~

1.0

2.0 l~T~UuUCTIU~.

Grapnlcs M-controller peA togetner witn the

Grap~ics

Display PCA

- oislay vectors On the terminal·s screen wnen commanded SO by

- toe Processor peA.

-~-controller·s major tasks are to read the image illemory in normal or zoom moce, to refresh the 1mage memory, to generate and store vectors or cursor in tne 1mage men,ory. rne vectors are speclfiea oy the processor

~CA in form of a siartPoint, slope and length. fne

~-controller intertaces with tne frocessor peA Vla connector

PI and witn the Graph1Cs U1splay PCA througtl the connector Pl.

OPEHATING PAHAMitERS.

A sunlmary of operating parameters tor tne

Gra~hics

M·controller is contained 1n taoles l.u tnrougn

~.4. laDle

1.0

Pnyslcdl Parameters

Part Size (L x

~ x 0) weignt

Numoer

I ~ornenclature

I

+/-0.100

InChes

I

(Pounds)

=============1==============================1=======================i=========

I I

I I

02640-b0125 I

Graphics

~-controller

12.5 x

~.OO x 0.5 0.5

I

I

,

I

,

-------------------------------------------------------------------------------

Number ot dackplane slots

~equired:

1

13255

Graphics M-controller Module

13255-911l5/03

REV MAY-04-7ij

Table

l.O

Reliability and Environmental Information

I

I

I

I

,

Environmental: ( X ) kP Class B ( ) Utner:

Restrictions: Type tested at product level

I

I

,

I

1==============================================================================1

I

1 failure kate: 1.49 (percent per 1000 hours)

I

I

Table 3.U Power SupplY and CloCk Requirements - Measured

(At

+1-5%

Unless utherwise Specified)

+S Volt Supply +12 volt Supply -12 Volt supply id

1.76 A

1~1 A

N/A

N/A

----.----------------------------------

---------~-----------------------------

115 volts ac 220 volts ac

N/A N/A

-42

Volt Supply

ClOCK Frequency: 1U.5 MHz

13255

Graphics

~-controller ~odule

13255-91125/04

REV MAY-04-7H

Table

4.0

Connector Information Graphics M-controller PCA

-----------------------~------------------------------ --------------------------

Connector

~iqnal

Signal ana Fin NO.

I ~ame

======~=======I================

PI, P-in

1 t +5V

-

I

I

Description

==============================================t

I

+5

Volt Power Supply

I

-2 I

Gt'4i)

Ground Common Feturn (Power and signal)

I

-3

}

{"ot llsed

}

-4

}

-5

-0

-7

-8

-9

-10

-11

--

AVDKO

---

AlJDkl

- -

AODR2

---

AOD~3

--

ADDR4

- -

AIJDH5

- -

A DIHH)

~egative true, address bit

0

Negative true, address bit

1

~egative true, address bit

2

Negative true, address oit

3

Negative true, address bit

4

Negative true, address bit

5

Negatlve true, adoress oit

6

Not used

-12

-13

-14

-15

-16

-17

-1H

-19

--

AO().R~

--------

AUJ)H9

- -

ADDR10

- -

ADDRll

Negative true, address bit

8

Negative true, address oit

9

Negative true, address bit 10

Negative true, address oit

11

}

}

}

}

}

}

}

NOt used

-20

Negative true, lop-ut/Output memory

-21

lID

GND

-22

Ground Common Return (Power and Signal)

13255

Graphics M-controller Module

13255-911~5/05

REV MAY-04-78

Table

4.0

Connector Information Graphics

~-controller ~CA

(Cont'd.)

--------------------------------------------------------------------------------

Connector Signal Signal and

Pin

NO. I hame

==============1================

PI, Pin A

I

GNU

I

Description

----------------------------------------------

Ground Common Return (Power and Signal)

-b

I

I

}

Not Used

I

-C I

I

-0 I t t

•

}

-~

-1'-

-J

-L

-~

8USO dUSl riUS:l

BUS3 fjUS4 bUS~

BUSt>

HUSI

Negative true, Data rlus Bit

0

Negative true, Data bus Bit

1

Negative true, Data Bus bit

2

Negative true, Data Bus Bit

3

Neqative true, Data Bus Bit

4

Negative true, Data bUS cit

5

Negative true, Data Bus Bit b

:~egdt i ve true, Data Bus Bit

7 t-4egatlve true, ... rite strooe

-H. t

}

}

Not used

-S

-r

-u

-v

-'"

-x

PRIUH L·J

PHIOl'< UUT

}

}

}

}

}

Bus Controller Priority Out

Rus Controller Priority Out

'';ot Used

-:t

Negative true,

HllS

Data Vnlid

-z

Illot Used

---_._---------------------------------------------------------------------------

13255

Graphics M-controller Module

13255-911l5/0b

REV ft1AY-04-7H

Table

4.1 Conn~ctor lntormat10n GraPhIcs

M-controller~PCA

--------------------------------------------------------------------------------

Connector and pln No.

I

Signal

~ame

Siqnal

DescrIption

1

-------------- ----------------

P2,Pin

1

AO

: : : : = : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ; : : : : : 1

Color Row Address, SIt

0

~

-2

Al Col or

Ro~

Address, BIt

1

I

I

-3

AI.

Color Row Address, Bit

2

I

I

-4 A3

Col or Row Address, Bit

3

-5

-6

-7

-8

-9

-11)

-11

-12

-13

A4

A5

A6

xo

,,(1

X'l.

X3

HAS

CA~

Col or

~ow

Address, Bit

4

Col or Row Address, Bit

5

Col or

KOW

Address, bIt

6 t)lt Adoress, Bit

0

Bit Address,

~lt

1 tiit Address, "'it

'l.

Bit Address, Bit

.3

Row Address Strobe

Column Address Strobe

-14 IN

Negatlve True, Write Enable

-15

---------------

LOAD

Neaatlve True, Load

--------~--------------------------------------------- ----------

13255

GraPhics M-controller MOdule

13255-911:l5/0"l

REV MAY-04-78

Table 4.1 Connector Information Graphlcs M-controller PCA (cont'd.)

Connector and Pin No.

-a

Signal

Name

--------------

P2, Pin -A

----------------

CLK

----------------------------------------------

10.5 r'H1Z

ClOCK

Gf'tl>

Ground

Signal

Description

-C ~egative ~rue, lO.5MHZ

Clock

-{j

-E

-t-

-!-i n

CLK

- -

103.D2

01

A7

Negative True, Col

103 and Dot

2

Data In

Address bit 7 lnnlbit Graphics Dlsplay

-J

-i'

-L

-jill

Sl'~3

5110(4

Sl~5

VK

~egatlve

True, Strooe

3

Negative True, Strooe 4

~egative

True, Strooe

S

Vertical Retrace

-t~

STk6 hegatlve True , Strooe b

-p i

I

I

I hot used

-H

SAMPL~

Sample Bit t

I

-s

I

Gf>JD

I

Ground

I

1====:===========================================================================

13255

Graphics M-controller Module

132~5-9112~/O~ kEY

MAY-04-78 function

Pe r tor ni e d :

Table

~.O

Module Sus Pin Assignments

Loaa registers, load b-oufter, set ana clear flags as specifiec by

AO,A5,Ab

Poll Bit: Not Applicaole

Moaule Address: (ADDR

4,11,10,~)

= (1100)

Function Speclfier: ti1ts AO,A5,Ab determine whicn register or flag will be strooed.

I t;us

Value I

Signal

======~

1

------------

ADOR

1~

0

ADDk

14

0

0

1

0

0

X

X

Ab

A~

1

X

X

X

AO

-------

87

ADUR 13

ADDR

12

ADDR 11

ADOR

10

ADDk

9

AODR

~

ADDR.

7

ADDR b

ADDk

5

ADOR

4

AOl.)R 3

ADDH

2

ADDR

1

ADDR

0

------------

!jUS

7

SUS

b

BUS

5 bb

B5

B4

83

6US 4

BuS

.3

82 tH

BUS

BUS

2

1

SO

BUS

0

--------------------

l=Logical 1=Bus LOW

O=Loglcal O=Bus Hign

X=Don't Care

---------------------

IAblASIAOISignall

Function

----------------------------------------------

,1 11 '1

I eLK VR I

Clear Vert. Retr. Latch

I 1 I

1

I 0 I RESt:. T

11 10 11 I STRS

Clear Address Counter

Load Moce Heg

11 10 10 IS'fR4

10 11 i1 ISTF3

10

11

10 1

STH2

Load Pattern Reg

Loaa Prescaler Reg

ClOCK Flags

Load B-buffer bits 8-11

10 10 11 t

STRI

10

10 lOt STRO

Load B-buffer bits 0-1

----------------------------------------------

Data Bus Bit Interpretation: See Tables 5.1 through 5.4

================================================================================

13255

Graphics M-controller Module

13255-911l5/0Y

REV MA~-04-78

•

Table 5.1 Module Bus Pin Ass1gnments

-----,---------------------------------------------------------------------------

function Load B-butter wlth

!jus

Performed: vector drawing parameters

Poll

~it:

Not Applicaole

Value

------- ------------

1

o o o

Signal

------------

ADDH. 15

ADDR 14

ADDH 13

ADDR 12

ADOR

11

1 o

o

AS

Al>OP 10

ADDk

9

ADOR 8

Module 4ddress: (AuOK

4,11,10,9)

=

(1100)

X

o

o

1 ft.3

ADU~ 7

AU!)£-? 6

ADDR 5

ADOR 4

AD

DR 3

Function Specifier:

Bits Al,A2,A3,A8 specify location in the B-outter that is loadea. bit AO specifies lo~er or upper half of ttle rl-bufter.

A2

Al

AO I

ADl>k 2

ADDR 1

=======1============

67

86

I

ADD..

U

BUS 7

I BUS 6

Uata bus Interpretation: See Table below.

See also Section 4.

65 I BUS 5 b4 I 8US 4

K3

82

I

I bUS

3

BUS 2

81 I bUS 1

<~-----~-AO=l-~--------> <~----AO=O---~---bO I BUS 0

----------------------------------------------------------------

Upper 4ljits

-_

..

Lower B tiits

-----------------------------------------------------------

IA81A31A21Ali Ib7'H6IB5Ib4Ib3Ib21~lleOIB7IB6IB5IB4Ie3182IBIIBOI

-----------------------------------------

X

IX F IX IX IX IX IX IX IX IX IX IX IX

Y/~ draw 1st dot

-------

o

10 o

I u

o

10

o

10

------------

o

10

(J

I 1

1

10

1 I 1 u

11

o

11 o iO o

11 o

11 1 10 o

II 1 11

IX

I X

IX

IX

IX

IX

IX

IX

x

X

X

X

X

X

X

X

I. IX

X

IX

X II f.. IX

X IX

X I A

1.

II.

F IX IX IX IX IX IX IX IX IX IX IX f I), f write Dot Count

Display Control Byte

IX IX

IX IX IA. IX IX Ii.. IX

IX

IX IX IX IX IX IX IX IX Ix IX IX

UppeI

b

oits of vector start aodr.

Lowerl2 oits ot vector start addr.

'i/~ cont.test

YIN self-test

YIN new aadress

1

1 10 0 i

V

'0

0 11

1

10 1 10

IX

IX

IX

X

X

X

}. IX

X

IX

X I X

Init1al Slope Value

Initial Vector Lenqtn

Upper

b

bits ot vector displ. M2

1 10 1 11

1 .1 0 ' 0

IX

IX

X

X

.x.

I X

X IX

Lowerll blts ot vector displ.

~2

Upper bOlts of vector displ.

~1

1 '1 10

11

IX

X

X IX LowerlL bits of vector displ. M1

1 11 I 1 10

IX

X It.

IX

Slope increment D2

1 I 1

11

I 1

IX

X X

I

X

Slope increment Ul

--_._----------------------------------------------------------

---------------------------------------------------------------------------------

13255

Graphics M-controller Module

13255-911lS/IO

R~V ~A:'-04-7ij

Taole 5.2

"

--------------------------------------------------------------------------------

~-------------------------------------------------------------~----------~-----function Load b-ouffer with Bus

I

Pertormea: zoom parameters Value Signal

I

-------

1

============1

A\)D~

15

0

Poll Bit: Not Applicable

Module Address: (AOOR 4,11,lO,Y)

=

(1100)

Function Specifier:

Bits Al,A2,A3,AH specity location in the B-ouffer that is loaded.

Bit AO specifies lower or upoer halt of the a-butfer.

Data Bus Interpretation: See lable below.

See also Section 4.

0

0

1

0

0

AJ

X

0

0

1

A3

A'J.

Al

AU

-------

B7 st>

B~

B4

1:33

ADD~

14

ADDR

13

AL>DR

12

ADDk

11

ADDH lU

AL>U}{

<}

ADOR

8

ADDF<

I

ADDH b

ADDR

5

ADOk

4

ADDk

3

AUDR

2

ADDR

1

ADDH

0

------------

bUS

7

BUS b

BUS 5 tjUS 4

BUS

3

<--------AO=l---~------> <-----AO=O-----~--

B2

81

80

BUS

BUS

BUS

2

1

0

Upper 4 Bits Lower ij

Bits

--------------------------------------------------------------

IAblA31A21Ali

IB7IBb'~5Ib4IB3IB2181IBOIB11~bl~~IS4IB3IB2IBIIBOI

--------------------------------------------------------------

0

0

0

0 0 0

0 0 1

0

1

0

0

0

1 1

0 1 0

0

X

X

X

X

X

IX I X I X IX

IX

IX IX IX

I

A-

IX I

X X X

X

~rlte

Oot Count

X X X

X

Display Control Hyte

X X X

X word Count per Line

X

X X

X

Magnltication-l

x

0

0

1

0

1 X

A

X X

X I )( IA

I X IX

I

X

IX IX

IX

I X IX I X

1

1

0

X X

X

X X I X IX iA

IX

I X

IX

I X

IX IX IX IX

0 1 1 1

1 0 0 0

X

X

X

X

X

I X IX IX IX IX IX ix IX

I

X

IX I X

X X X

X

Upper b hits of Zoom Start Addr.

1 0 0 1

1 0 1 0

A

X

X

X Lower

12

Bits of Zoom Start Addr.

X X X

X

X IX IX IX

IX

IX I X IX IX IX IX I X

1

0

1

1

X X

X

X X IX

IX

IX IX IX IX I X IX IX IX , X

1 1 10 0

X

X

1 1 10 1

1 1

11

0

1 1 11

1

X

X

X

X ix X X IX IX i ){ IX IX IX

IX

IX IX IX

IX ix X X IX IX I X IX IX IX I X IX IX IX I X

X IX

X

X IX IX I

X.

IX

IX IX IX IX IX IX I X

X

IX

X X IX

IX

I X ix IX IX I X IX IX IX·· IX

================================================================================

13255

Graphics M-controller Module

13255-91125/11

REV MAY-04-78

Table 5.3 MOdule 8us P1n Ass1gnments

Function Load 8-buffer with

Performed: cursor parameters

Poll tiit: Not Applicaole

Module AOdress: (ADUR 4,11,10,9)

=

(l100) function Speclfier:

Bits

Al,A2,A3,A~

5pecity location in tne b-ouffer tnat 15 loaded. tilt AO specifies lower or upper halt

Ot the B-buffer.

Value

======

1

1

0

0

0

0

0

A~

X

0

0

1

Aj

A2

Al

AO

-------

67 tib

85

84

83

Data Bus Interpretation: See Taole oelow.

See aiso Section 4.

82 tSUS i-

BUS

1

81

<--~-----AO=l·~-------~> <~---~AO=O--------

BO

----------------------------------------------------------------

Upper

<}

Bits Lower

~

Bits

---,-----------------------------------------------------------

------------------------------------------- -----------------

BUS 0

----------------------------------------------------------------

---,-----------~-~--------------------------------~--- ---------

IA81A3iA21Ali 187Ib6Itl~tB4tbjlblltiltrlOtB7IbbI85Id41831~2IAlI801

---,-----------------------------------------------------------

0

{J

10

0 :f..

IX

X I X

X IX IX IX IX Ix x

IX IX IX I X IX v

0 to

1 X IX X IX X

IX

IX

IX tX IX

X

IX

IX

IX IX I X

0

0

0 0

, 1

0

X IX

X i X

X

I A IX

I X IX

1 1 X ax

X IX IX I

x

I X

IX

IX

X IX

X IX t

X

IX IX

IA X

I }. IX IX IX IX

0

1

0

U

0 1 0

X I.{ X IX

A IX IX IX

IX

IX X I X IX I ;(

IX

IX

1

X iX

A

I A

A

IX IX IX

IX 1;(

X

IX

IX IX

IX IX

(J 1 1 0

0 1 1

X 1..(

X

I

X

X IA

IX

IX

IX IX X

I X

IX

IX IX IX

1 X IX

X

IX

X

I X I.{

IX IX IX

X

IX IX IX IX IX

1 0

0

0 X

IX

X

I).

X

IX IX IX IX IX X I

J{ tX

IX IX IX

1 0 0

1

()

1

X

IX

X i

X X

IX iX IX IX

IX

X I )(

IX I X IX IX

1

{J

X

IX

X

IX

Start dddress

+7'J.O

(upper

b

bits

)

Vertical

1

0 1 1 ).

IX X

IX

Start address

+7}.0

(lower

1'J.

01tS) vector

1

1

0 0

I

1

0 1

X

X

1.(

X IX Start address

IX

X

IX

Start address

-

1

(upper

b

bits

)

IHorlzontal

-

1

(lower

12 bits) Ivector

1

1

1

0

X

IX X IX vertical Vector Length

1

1 1

1

IX

I x

X I X Horizontal vector Lengtn

I

I

8us

Signal

I

============1

ADDK

15

ADDH

14

ADDR

13

ADOR

12

ADDk

11

ADOi-<

10

ADDR

9

AUDR

B

ADOR

7

ADDR

b

ADDR

5

ADDk

4

AD

DR j

ADDt< 2

ADDR

1

ADDt<

0

------------

au~ 7

BUS

0

8US

5

BUS 4 bUS

3

13255

Graphlcs M-controller Module

132~5-911l5/1:l

REV MAY-04-78

Table 5.4 MOdule Bus Pin Assignments function

Perrormed:

~et/Clear flags

Poll Bit; NOt Applicaole

MOdule Adaress: (ADDR

4,11,lO,Y)

=

1100

Data Bus Bit Interpretation:

----------------------------

ISOI

1/0 set/clear flag 1

IBll

1/0

set/clear flag 3

1821

1831

1851 not used

1/0 set/clear flag 4

1841

1/0

set/clear flag 5 not used

I

Bb

I not used

1871 not used

----------------------------

bus

Value

----

..

1

---

Signal

------------

ADDR 15

0

AODR

14

0

0

1

0

0

X

X

0

ADOi'<

13

AODR

12

AOJ.)K

11

AOJ.)R

10

ADDR

9

ADDR

8

AD DR 7

ADDR b

1

1

X

X

X

0

-------

B7 t)O tj5

ADUR

~

AODR

4

ADDR

3

ADDR

2

ADDR

1

ADDR

0

------------

HUS

7

BUS

0 bUS

5

B4 BUS 4

83

~2

BUS 3

BUS

2

81

BUS

1

80

BUS

0

--------------------

1=Log1cal l=Bus LOW

O=Log1cal O=8us High

X=Don-t Care

---------------------

13255

Grapnics M-controller

13255-911:l5/13

REV MAY-04-78

3.0 FUNCTIONAL DESCHIPTION. Refer to the block diagram (figure 1), scnematic diagram (figure ~), component location dia~ram (figure 3),

1nstruction format (tigure 4), image memory aadress (figure 5), image memory bit displacement (figure 6), zoom example (tigure 7), flowCharts

A,d,C (figures ij,9,and 10), and parts list (02640-60125) located 1n the

~p pen d 1 x • He fer a 1 sot 0 t h.e g rap hi c s m i c roc 0 deli s tin gin sec t ion 6. 0 •

The Graphics M-Controller peA consists of an address counter, ROM,

HOM output regIster, instruction decoder, decoder enable flip-flop, condition selector, halt, A-butfer, hold register A, B-buffer, nold register S, address multiplexer, constant multiplexer, adder, carry flip-flop, s1gn flip-flOp, S11 flip-flop, aadress register, bit register, RAS and CAS flip-flop, bus gates, bus decoder, flags, and test logic blocks.

To accomplish the taSKS described oy the algorithms outlined in section 4.0, the M-controller is designed as a microprogrammable macnine. It 1S provided with a set of 8 instructions and 25b woras of control storage, eacn 20 cits wide.

The hardware has basically two Dutfers A and 8, both 16 words lonq and 12 bits wioe. Each bufter can load its own hold register A,B. Both registers are aadends of a 12-bit wide adder. The output of the adder is route a cacK to tne cutter A.

The bufter

~ is loaded trom the 2648 bUS. rour load instructions can load the hold registers witn a Duffer location. hold register b can oe loadea also with a constant. STO instruction stores the result ot the adaition oacK in cuffer A. The computation is done in

~'s compleiTlent.

To Drancn within tne microco~e, a condit10nal jump with ij-bit tarqet address 1S prov1ded.

10 indic~te c~rtaln states of toe hardware, fLG instruction can set or clear seven hardware tlags. In addition fLG instruction can halt the adaress counter. Three LS~'s of the RUM field provide tne timing signals for the image memory.

M-controller instruction set. lkefer to figure 4).

LAB nold reg A:= buffer A(A); nold req rl:= buffer 8lti); it Z=l then hold reg A:=O; seno bits (w,R,C) to image memory;

LAC nold reg A:= buffer A(A); nold reg b(Dlt 0-7):= CONSTANT

I i

nola reg dlbit 8-11):= 0; send bits

(~,R,C) to image memory;

LDC

LOA hold reg A:= 0; nola reg b:= CUNSTANT

l;

send olts (w,i\,C) to image mell,ory; nOld reg A:= Dufter A(A); send olts l~,k,C) to image memory;

13255

Grapnics M-controller Module

132~5-911~5/14

REV MAY-04-78

v

S10

JMP

FLG

NOP it C=l then sum

.butfer A(A):= sum 5; holo reg hold reg

A

A

+

+ nold reg hold reg

B

B;

+ carry 1n carry

tt:=

carry out: if 5=1 tnen sign ft:= Sell):

If X=l then bit reg XR:=

SO-53; if L=1 tnen if ,.,=1 then address reg AR:= SO-S5,SI1 ff; if M=O then aCldr reg AR:= S4-510; send blts (v.,R,C) to image memory: if ClJNO=Tf<Ut. tClen address count'er AC:=

TARGET; sene bits

(~,R,C) to image memory:

Conditions:

0 unconditional

1 carry ff

~ not carry tt b

.,

3

4

5 not flag

1 not flag

'2. tlag

3 not tlag

4 vertical retr.

8 flag b

9

10 not used slgn ff

11 test not OK

12 tlag

5

13 not sign ft

14

1~ not vertical retr. not used it f=

0 then nop: if f=

1 tnen set not tlag 1 ; it F=

'2. tnen clear not tlag

'i: if f=

3 then set not flag

2; it F= 4 then set not flag 4; it F=

5 then set tlag

5: if F= b then set flag b; it F=

-, then clear flag it f=

H then nop: it f=

9 then nop;

0: it f=lO then enable self-test; it F=ll then disable self-test;

If 1'"'=12 then set vertical retrace latch: it F=13 tnen nop; if t'=14 then send

STH6 to image memory;

If 1'-=1

S then set

H olt; it til=l then set halt

1 ; if H2=1 then set halt 2; send bits (w,R,C) to image memory; send bits (w,R,C) to image memory:

13255

Graphics M-controller Module

13255-91125/15

REV MAY-04-7H

3.1

3.2

3.3

3.4

3.5

Instruction execution speed.

An instruction cycle takes two clocks. One ClOCK for f~tch and one for execute. To speed up tne code execution, the M-controller works in pipel1ned tashlon. while one instruction 1s being executed, the next instruction is oeing fetched. Since the ClOCK period is

95 nsec, the instruction execution rate is

10.5 MHZ.

This is true tor all instructions exept the successful jump, Where the execution taKes two clocks

(test and jam).

Slnce a new line of microcode is loaded into the RUM output register

(ROR) on every clock, the image memory timing is controlled directly trom

ROk bits

0,1,2

(signals

RAS,CAS,~RITE).

ADDRESS

COUNTEk

(AC).

Address Counter (AC) provides the

~-bit address tor tne

RUM.

It is ariven oy

10.5

MHz clock. If Signal TESTOK is asserted by the

JMP conaition selector, the address specified by

ROR

5-1~ is jammed into the Address Counter ana brancn in the COde is accomplished. AC can be trom advancing by Halt circuit. It can be initialized to zero by the

RES~T siqnal from the Bus DeCOder.

BEAD ONL~ MEMUKY.

Read Only Memory provides storage tor the

~icrocode.

It is

2~6 wordS long and

~O bits wide.

ROM is composed of

5

PROM'S HarriS

7611-5 or equivalent. kUM

UUTPUI

REGISTER (RUR).

HOM output RegIster

(HOR) is

20 bits wide and holOS tne instruction oeing executed.

Ne~ instruction is clocked in on every ClOCK. The signal

H£S~r clears opcode oits thus forcing

NOP into the instructlon decoder.

INSTRUCTION

U~CUDEk llk).

The

]R deCOdes the tnree most siqnificant bits ot the

KOR.

There is one instruction decodea per one ClOCK period

(95 nsee) as long as it is enaoled by Oecoder

~nable tlip-flop.

D~COU~R ~~A~L~

FLIP-fLOP.

Decode r

~nab

1 e FF ai sab Ie s trle nex tins t ruct ion after JMP f rom be i ng executed it the jump condition was found

uK.

It forces one dead clock when successtul oranCh occurs.

13255

Graphics M-controller Module

13:l55-911:l~/16

REV MAY-04-78

3.6

3.7

3.8

3.8.1

3.8.2

CONDItION SELECTOR.

Condition Selector selects one of the

10 possible branchinq conditlons.

The condition is determined bY ROR

13-16 bits. Tne selected condition and the decoded JMP signal determine the outcome of the

1~STOK line.

-

"The possible jump condttions are:

3

4

5

0

0

1

2

7 unconditional carry ff not carry ff not flag

1 not flag

2 flag

3 not flag

4 synch vert. retrace

8

9

10

11

1:l

13

14

15 flag

0 not used sign tt test not

OK flaq

5 not sign ft not synch vert. retrace not used

HALT.

Halt circuit enables nalting the Address Counter programatically bY issuing the fLG instruction. Tne FLG instruction and bit ROR

11 on, halts the Address Counter until the Graphics Display asserts the synch pulse

103.02 that re-enable the counter. FLG instruction and kUH bit

12 on, nalts the Address Counter until the

~raphics

Oisplay sends the next LOAD pulse. The hal~s are used to synchronize the

M-controller and the image memory when reading and displaying a word.

A-BUfFER.

A-buff~r is d lo-word

~AM, 12 bits wide. It nolds different variables as shown on tne flowchart, figure

10.

The micrcode can write Into or read any location

Of the"A-buffer, but it is not accessible to the

~O~o Pr~cessor.

The STO instruction stores the result from the adder into a location of the A-butfer specified bY bits MOR

13-10.

The instructions

LA~,LAC or LOA loads a location specified by ROR

13-1b from the A-buffer into the Hold Register A.

Since the bit

~UR

4 high disables the

RA~, any LOAU instruction

~ith

ROR 4 high

~ill load zero into the Hold Reg A.

A-buffer consists of three HAM·s

145189.

The signal WE low strObes the data into the buffer. When the FAM·s are disaoled by RUR 4, the tri-state outputs are pulled high by external resistors. This loads effectively zero into the Hold Register A, Since the register uses the complementary outputs.

13255

Gra~hics

M-controller Module

13255-91125/17

REV

MAY-04-7~

3.9

-

3.9.1 -

3.9.2

HOLD REGISTER A.

Hold Register

A holds one addend of the addition. It 1s loaded oy toe instruction LAB, LAC or LOA with the content of a location specified by ROR 13-16. zero is loaded into the register by instruction LDC or .LAB it HOH 4 is set. The other instructions dO not affect the register.

The register consists of tnree 74LS17S's. Complementary outputs are used to compensate for the inversion-in

RA~'s.

Since-the bit

ROR1~ is

3.10

3.10.1

3.11

3.11.1 set only in

LOAD instructions, the trailing edge of signal

HOH19.CLK is used as strobe.

B-BUf" fER.

B-buffer is a

16-~ord

KAM, 12 bits wide. It holdS variaoles as shown in the tlowchart, figure 10. The microcode can only read a location out ot tne B-butfer into the

~old

Register b.

The M-outter is loaaed oy tne Processor via the terminal bUS.

Tne Address MUltiplexer select~ either the signals

HOR 9-12 or

------

ADDR 1,2,3,8 as address for the B-buffer, depending whether the butter lS read out or

~ritten into. Tne 12 bit word is loaded lnto the butter by the Processor in two bytes: the bUS decoder signal STRO strObes ous data

BUSO-1 into the bit position 0-1 and STRI loadS

BUSO-3 into the bit position 8-11 ot a location specified bY the address

ADDRl,2,3,8.

H-butfer consists ot tnree

RAM'S 145189.

Since HAM inverts the input data, toe negatlve true DUS data appears as positive at the outputs.

It should De noted, tnat Since the bUS adaress

ADDkl,2,3,8 is negative true tne Processor has to compiement the address when loading tne B-tiuffer.

HOLD

R~~ISTER ti.

This register holds one aadend ot the addition. If tne instruction

LAb loads the Hold Register B, tne addena is a location trom the B-outter.

It LAC is executed then the register bits 0-1 are loadea witn RORS-l:l

(constant 1) and bits

~-11 are zero-ed. finally, the register is loadea with oits RGR5-1b if LUC is executed.

13255

Graphics M-controller

132S5-91125/1ij

REV MAY-04-78

3.11.L

Hold register ti is composed ot three multiplexer registers

74L~~Y8.

Tne Inputs are switcned to the B-butter, wnen tne LAB signal is true, otherwise tne signals HOH's are used as inputs. The trailing edge

-------

_ ot tne signal ROR19.DE.LOA.CLK is used as a strobe.

3.12 ADDRESS MULTIPLEX~R. this multiplexer selects tne address for the B-butter. It either the tlag fl or l"4

IS set then

RUi< 9-12 adoress is used. Otnerwise the bUS

---_._--adaress

ADDK 1,2,3,8 is selec~ed.

3.13

3.14

3.15

3.16

COhSTA~l MULT1PL£X~R.

The multIplexer 1s used tor loading either CONSTANt

1 or CONStANT

2 into Hold register ti. when a Load Instruction other than LOC is aeCOded tne multiplexer supplies zero to the Holo register

8. if

LDC 1S deCOded then the bits

i<Ok

13-1b are used as the upper four D1tS ot toe constant.

ADDEK.

Tne adder adds two numpers in hold Registers A and tie

The output ot the

Carry

Ff is adaed to the sum it enabled by the oit

ROR6.

The carry out and MSB ot tne adder are made available to the Larry and Sign Fi. lne adder outputs are valid as long as HOld Registers A,e are not loadea with new values or carry in is not disabled by

HORb.

The sum is forwarded to tne A-butter, Adaress Register AR dno bit Register

X~.

CARRY FLIP-fLUP.

It saves the carry out when tne STO instruction is executed and maKes it available to tne adder In tne next aadition, provided ROko IS on.

Both outputs of the FF are used as jump conditions.

SIGN

FLIP-FLOP.

It stores the MSB of the addition wnen the instruction STO is executea and the bit ROi<5 is set.

The sign FF set to one means negative number.

~otn outputs ot tne fF are used as jump conditions.

13255

Graphics M-controller

13255-91125/19

REV

MA~-04-78

3.11

3.18

3.18.1

3.18.2

S11

FLIP-FLOP.

Similarly, as with the Sign Fr, the S11 FF saves MSB

Of the addition but data is clocked in by the positive transition of the signal

POHle

ADDRESS REGISTER (AR).

The Address Register has the primary functlon ot holding the address wnen M-controller accesses the image memory. Since the image memory is organized as 16K words times

1 bit RAM, it taKes

18 bits to address a single bit. Four bits are needed to polnt out toe bit within a word ana

14 upper bits piCK tne wora within toe Chip.

16~

RAMs use address multiplexing. First 7 row address bits are sent followeo by

7 column bits.

(~ee figure

~).

Since adder and

RAM buffers are only

12 bits wide, it requires two locations in

A or

B buffer to store the complete memory address.

It Should be noted that to increment the image memory oit address means to add one to the LSB, While to increment the

~ord address involves adding one in bit position

4

(add decimal

16).

Note that the 7 oit row address is contained fully in one location wALU or HALO (write address low or read address low),;

6 bits of the 7 bit column address are in wAHl or RAMI (write addr.nigh or read addr.nign) but one bit is in ~ALO (or RALO). Therefore, t~e LSB of the column address is stored in the 511 Ff when WALO (or

PALU)

Is being sent to the image memory.

The process of sending the memory address then lies in two ste9s:

1. Load WALU (or RALO) into the Hold Registers. Issue

S10

Instruction

~ith ROR7 high and ROR3 10*. This loads the Adder oits

54-10 into the

Address Register. Send RORI (RAS) to the memory, thUS strobing the row aadress and saving the MSB in 511 FF.

i.

Load

~AHI

(or RAHI) into the Hold Reqlsters. Issue 510 instruct10n with

ROR3 and ROR7 high. Tnis loads the Adder bits SO-5 and S11

FF into the Address Register. Then send strobing the column address.

RORO (CAS) to the memory, thus

Besides sena1ng the memory aodress through the Address register, the M-controller dispatches tne Display Control Byte to the Graphics

Display via the Adoress

~egister.

The ij upper bits are sent througn the

AR and

4 lower bIts via the Bit Register

(XR).

(see description of Graphics Display peA 1n module sectIon 13255-91126).

Address Register consists of two multiplexer registers 74LS298.

The select input is controlled proqramatlcally by ROR3. The data is strobed in the AR when the STO instruction is decoded and the bit ROR7 Is on.

13255

Graphics M-controller

132!>5-911:lS/20

HEV ~AY-u4-78

3.19

3.20

3.21

3.22

BIT REGISTER (XR).

This register holds the lowest four bits of the memory address or four lowest bits of the Control Display Byte. During self-test, in case of an error the four lowest bits of the failing address are saved here.

- Data from the aader are loaded in the register when the S10 instruction

_ is· decoded and the bit

ROR8 is set.

RAS

~

CAS fLIP-fLUP.

The flip-flops send the RAS and CAS signals to the image memory. Since they are clocked with CLK, the signals RAS and CAS are shifted halt a ClOCK

(47 nsec) oehind the leaainq ClOcK edge. This allows to propagate the address through the Address Register and drlvers on the

Grapnics Oisplay PCA before it is clocked in.

BUS GATES. wnen enableo oy the READ signal, the gates propaqate the contents of tne bi t register

XR, flag

FS, signal

£'4f1.lIfF4, latched image memory data and the signal VRIN.

BUS

DECODER.

Bus Decoder decodes signals sent by the Processor to the grapnics hardware (mOdule no. is 14B), and passes them in the form of strobes to the other inner blocks as follows:

STRO strooes

OUS data into B-bufter bit 0-7

STR1 strObes bUS data into b-buffer bit

8-11

STR2 ClOCKS flags

Fl,~3,F4 and F5

STR3 loads prescaler on the GraPhics Display PCA

STR4 loads pattern reg on the Graphics Display PCA

STRS loads mode reg on the Graphics Display peA

STR6 is the signal RESET whiCh initializes Address Counter to zero

STR7 clears the Vertical Retrace latCh

13255i

Graphics M-controller

13255-91125/21

REV

MAY-04-7B

3.23

3.23.1

FLAGS.

The bloCK called Flags is a set of flip-flOps that indicates the internal states'of the graphics hardware and firmware.

Flag Fl when set indicates the input S-buffer was loaded by the

Processor with new data. It is set by tne Processor and cleared oy the

~-controller's

FLG instruction.

Flag

F~ wnen set indicates the vector drawing is in progress. It is set and cleared by tne FLG instruction. flag F3 wnen set indicates the zoom mode is on.

It is cleared and set by the Processor.

Flag f'4 when set indicates the input 8-ouffer was loaded

~ith new zoom parameters. It is set by the Processor and cleared by the FLG instruction.

,,'lag f5 has tlfiO rreanings:

First, if set oy tne M-controller during selt-test, it signals to the Processor that the selt-test tailed.

Be fore se 1 f -tes t il:

RlUS t be cleared by the. Processor.

Second, it during vertical retrace both flags fl and

F~ are set oy Processor, it maKes the M-controller to draw cursor. flag f6 is used tor reentry from WRITE sUbroutine in the grapnics tirmware. It is set and Cleared by FLG instruction.

Flag T when reset enables self-test logic. It is set and cleared by tne iLG instruction.

Flag H wnen set, forces the Graphics Display peA to send blanKS to tne screen. It is set by tne FLG instruction dnd reset oy the synch signal

103.02.

Vertical Retrace Latcn

~nen set by tne FLG instruction indicates to the Processor that vertical retrace occurred.

It is clearea by tne Processor.

StR6 is a strobe that loads the Display Control Byte onto the

Gra~niCs Display peA.It is asserted oy the fLG instruction.

13255

Graphics M-controller

Ij25~-~112S/22

RE~

MAk-04-7B

3.23.2

3.24

3.24.1

3.24.2

4.0

4.1

The Flag logic contains decoders, flip-flops and k-S latcnes. The two decoders 74LS138 decode toe slgnals ROR 13-1b woen enaD)ed oy the signal iLG. Tne decoder o~tputs manipulate tne flags. The flags f l , f l ,

F4,F5 are flip-flops tnat use bus data as inputs ana are clocKed by signal STR2 trom bus decoder. Note that STR2 is NANOed with eLK for synChronization purposes. wnen the Processor sets flag 1 or flag 4, it actually maKes Q-outputs of toe

J4LS74 lo~ since toe bus data is negative true. Tnat·s

~ny tne signals are called

Nfl,~F4.

In case Of flag

3 and flag

5 tne

Q-outputs are used, so tnat Noen these tlip-flops are set by Processor tne names F3,f"S corresponds to high level signals.

TEST LOGIC.

This blOCK provides tne self-test teature when enaoled by the T-flag.

The image memory data bit

01 is latChed and compared with tne expected value SAMPLE loaded by the Processor into the GraphiCS Display

~CA.

Resulting signal OK is a condition tor the

J~P instruction. Latched memory data bit DATA is made available to the

~080 via Bus Gates.

Memory data bit 01 is strObed by the leading edge of ROR2 (the WRITE signal to the memory) when read portion ot the ~-M-w cycle is finished. SAMPLE is a latChed data bit sent by the Processor.

~hen signal

NT is low the compare logic 1s enabled and toe signal

~OK is determined by

SA~PLE and UATA.

GENERAL.

This section outlines tne image memory organization and in terms

Of algorithms describes the toree tasKS the graphiCS hardware performs: vector plotting, line displaying and zooming.

IMAGE MEMORY SIZE.

If the screen of 720 by 360 dots is viewed as two dimensional array,

19 it ta~es

19 bits to adaress a dot and memory size of 2 bits

(0<=x<=719 ; O<=y<=359). But if tne memory is organized as a linear array wn~re each screen dot is assigned a number, then the screen tits

18 into tne size of 2 bits.

To meet tnls oDjective the memory array is organized as Ib,200 words,

16 olts wide. Each 45 words cover one raster line (45*16=720).

Given screen dot address x,y the corresponding memory address is: bit addr 45*y*16

+ x word"addr 45*y

+ x/lb

(18 bits)

(14 oits)

13255

Graphics M-controller

13255-911l5/23

REV MAY-04-18

4.2 VECTOR PLOTTING ALGORITHM.

Given a cartesian grid, a vector with a slope delta y/delta x less than 45 degrees can be plotted as follows: step 1: Set d=-1/2+(delta y/delta x). Set X and Y to the x,y coordinates of the startpoint of the line. step 2: Place a dot at coordinates X,Y. step 3: If X equals x coordinate of the end of the line, stop.

Otherwise go to step 4. step 4: If d is negative set d=d+(delta y/delta x) and set X=X+l.

Go step 2.

It d is positive set d=d+(delta y/delta x)-l and set X=X+l,

Y=Y+l. Go to step

L.

Now the different addressing scoeme between screen and toe linear memory must be considered. Given a dot on toe screen, the adjacent dots nave eight different displacements in the image memory.

(see Figure 6)

Tnerefore for tne first octant, the step 4 of the algorithm is ctlanged: screen increment X=X+l is substituted by memory increment M=M+l and increment X=X+l,Y=Y+l is substituted oy M=M-119.

Similarly, for eacn octant there are two memory displacements for two adjacent pOints on tne screen. Vector plotting algorithm tnen can be modified with regara to the linear memory arrangement:

Given two pOints on the screen PO(xO,yO), Pl(xl,yl). PO is the beginning. step 1: Set delta x=xl-xO, delta y=yl-yO

Determine which octant the vector will be plotted in.

Assign the memory displacement Ml,M2 according to the octant.

Calculate tne vector start address

~A=45*(359-yO)*16+xO

Set the initial value D=2*delta y delta x and increments Dl=2*delta y, D2=2*delta y -

2*delta x.

Set the dot count (vector length) DC=delta x. step 2: Write a dot at address wA step 3: Decrement the dot count OC=DC-l. If DC=O then done; else go to step 4. step 4: If 0 is positive tnen upaate D=0+D2 and address

WA=WA+~2.

Go to step 2.

If D is negative tnen update D=D+01 and address wA=WA+Ml.

Go to step 2.

13255

Graphics

M-controll~r

13255-911l5/24

REV

MA~-04-7H

4.3

4.4

LINE DISPLAYING ALGORITHM.

Displaying a horizontal line requires reading consecutively 45 words

_ each

16 bits wiae, converting them to a serial stream and sendinq the

~ bits to monitor. Whenever

45 words have been read, the Deam is in horizontal retrace and new read operatlon must be synchronized with the raster. To display tull frame requires to read

360 lines. step

1 :

Initialize line count IJC=O and read address RA=O. step

2:

Initialize word count WC=O. itait for the raster to beqin the line. step

3 :

Read a

\~ora at address RA, convert

16 parallel bits to a serial stream and direct it to the monitor. U9date address RA=RA+l and word count wC=~~C

+

1 • step

4: If wC=45 then go to step 5 else go to step

3. step

5:

Increment line count LC=LC+l, if LC=360 then frame DONE else go to step

l .

ZOOM

ANU

PAN

AL(iORITHM.

Zoom is a feature that displays a bit from memory, for a given magnification m in the form of (m-l)*(m-l) dots, followed by one blank row and one blanK column. (see figure 7)

To stretcn the line horizoritally on the screen in the zoom mode, requires to send each dot (m-l) times to the monitor, followed oy a blank dot, before shifting to the next dot.

This means to reduce the Shifting frequency of P-S convertor to 21MHz/m. Vertical extention is achieved by reading the same line

(m-1) times. start point is specified by start zoom address ZASTP. step

1 : step

2: step

3: step

4: step

5: step b: step step

7 :

8:

Initialize current zoom address ZA=ZASfR, line zoom address

ZAO=ZASTR, word count per line K=45/m, line count LC=O.

Initialize repeat count RC=O.

Initialize word count wC=O, wait for raster to oegin line.

Read a word at ZA, update ZA=ZA+l and wC=WC+l. wait till serial conversion of the word is tinished.

If WC<K then go to step 4, if WC=K then proceed to step 7.

Increment LC=LC+l, if LC=360 then frame DONE else proceed to step 8.

Update RC=RC+l. if RC<m-1 then reinitlalize ZA=ZAO, go to step 3. if RC=m-l then do one blanK line and update ZAO=ZAO+45, ZA=ZAO go to step 2.

13255

Graphics M-controller

13255-91125/25

REV MAY-04-78

4.5 TASK PARTITIONING BETwEEN GRAPHICS M-CONTKOLLER AND PROCESSuR PCA.

Tne qraphics M-controller serves the tollowinq functions: a) It reads and refreShes tne imaqe memory either in normal or zoom mode. By changing zoom start address, panning through the image memory is accomplished. b)

During the norizontal retrace it generates and stores a vector into the image memory. Vector specification is recieved from the Processor in the form of an endpoint, vector length and vector slope.

The vector is generated by turning on the dots in the image memory that most closely approximate the straight line oetween the endpoints. c) During vertical retrace it generates and stores graphics cursor into the image memory if desired by the Processor. d) It reads any point on the screen and maK~S it known to the

Processor, if so desired. e) It can aiagnose the whole image memory and identify

RAM

Chip failure.

The

~rocessor snares some of the taSKS:

(Refer to sections

~.O through 5.5, the flowCharts figures

8,9,and

10 and the graphic microcode list1ng in sect10n

6.0). a) Read ana refresh is the sole function of the graphics hardware

Read in the zoom mode is specified DY the Processor into the d-buffer on the M-controller ooard in the for~ of magnification M, word count per line K, zoom start address ZASIRLO,

ZASTRHI and display control byte. b) Vector generation during horizontal retrace is done as outlined in section

4.2.

Processor does the step

1 of the algoritnm and outputs the vector parameters into the B-butfer on the M-controller Doard. The parameters are: start memory address wALO,wAHI, dot count DC, initial slope

0, slope increments

D1, 02, image memory increments

MILO, MlriI, M2LO,

M2HI. 8080 Processor indicates by sett1ng MSB In the location

8(10)

Whether the endpOint of the last vector is the beginning of the new one or if the new wA should be used.

If self-test is requested, Processor sets

Msa in

8(11) or it test is to be continued atter previous failure,

MSb

In

8(12) is set. The number ot dots generated per scan line is passed in the location

8(14). c) The graphiCS cursor is generated as one horizontal and one vertical vector. The

~rocessor has to specify both vectors DY start points WA1LG,

~A1Hl, ~A2LO,wA2rlI and oy lenyth

~Cl,DC2.

13255

GraPhics M-controller

13255-91125/26

REV MAY-04-78

5.0

5.1

PROCfSSuR fIRMwARE SPECIfICATION.

Tne Processor causes tne graphlcs M-controller to perform

- tne fOllowing tasKS: vector drawing,self-test,zoom,cursor drawing

~ and reading a raster bit.

-It does so by loading the input 8-butfer,scanning and setting flags on toe M-controller as descrioed oelow.

Since the ous aadress is negative true, the Processor has to complement the address before loading the 8-buffer.

For example if the Processor specifies address

15, it actually loadS

Duffer location 8(0) etc. Then to load the buffer see tables

5.0 through 5.4.

VECTOR

DKA~ING.

Processor action comment: if

B~s

{O)=O tnen

Begin

B (O):=delta 01

B (1):=delta D2

B (2):=delta MILO

B (3):=delta M1Hl

B (4):=delta M2LO

B (S):=delta M2HI

*

*

*

*

*

*

** it

Fl,f'4 reset then load b-buffer load slope increment 01 slope increment 02 lower 12 bits of mem. displacement Ml upper 0 bits of mem. displacement Ml lower 12 bits ot mem. displacement

~2 upper 6 bits of mem. displacement M2

S (6):=OC

8

(7):=D

b (8):=new wALO

B (9):=new WAHl

8(10):=40008/0

8(11):=0

8(12):=0

B(13):=Display Byte ***

8(14):=~rite

Dot Count** intial vector lengtn lnitial slope lower 12 bits of vector start adore upper b oits of vector start addr. use new start addr/use last addr. do not start self-test do not continue self-test

Graphics DisPlay Control Bits

4 dots in normal read,3 dots in zoom

8(15):=40008/0

Load Mode register

Set 1"1

End;

Draw 1st dot/Don't draw 1st dot

~ode

Reg on Graphics Display PCA set Flag 1

* only ne~ative values loaded in 2's complement

**load always as negative 2's complement

***for meaning of Display Control Bits refer to the

Graphics Display Module (13255-91126).

13255

Graphics M-controller

13255-91125/27

REV MAY-04-18

5.2

5.3

SELF-TEST.

Processor action:

A. Start self-test: if Bus

(0)=0 then

BeQin load B-buffer as under vector drawing but B (11):=40008 load SAMPLE bit into Graphics Display peA fl:=l

£05:=0

End;

B.

Evaluate self-test: if fl=O and

F5=0 then test

OK; go

DONE: it Fl=O and F5=1 then test failed; c.

Continue self-test:

Begin t3

(12):=40008

F.1:=l

F5:=O go B t:::nd;

ZUOH.

A. Start Zooming.

Processor action: if 8us (0)=0 then tjeg.in o (

11 ) :

=:-1

Fl- (

12 ) : =K t3

H

(b):=ZASTRLO

(7):=ZASTRHI

B(13):=Display 8yte f3:=1

1"'4:=1

End;

*

* comment: if fl,F4=O then load b-outfer load zoom magnification-1 load no. ot words per line lower

12 bits of zoom start addr. upper

6 bits ot zoom start addr.

Graphics display control bits set flag E'1 set flag F4

*load as negative 2's complement

13:l55

Graphics M-controller

13255-91125/28

REV MAY-04-78

5.4

5.5

B. End Zooming. if

8us(O)=0 tnen f3:=0;

.CURSOR.

Processor action: comment: it 8us(0)=0 ana Bus(S):1 tnen

Begin

B (O):=DCl

H

(l):=DC~

*

*

8 (2):=wAILlJ

B

(3):=IrtAlril

B (4):=WA~LO f t:3

(5):=wA2HI

1 :

=

F5:=1 if F1,f4=0 and vertical latch is set then load 8-buffer length of horizontal vector length of vertical vector start addr. of noriz.vector-l start addr. of vert. vector+7~0 set flag f1 set flag

F5'

* load as negative

L'S complement

READ A RASTER Hil.

Processor action: if Bus (0)=0 then

Begin

B (6):=77778

B

(S):=wALU

B (9):=WAHI

8(10):=40008

8(11):=0

B(12):=0

13(15):=40008

Mode Reg

F1:=1 comment:

1t fl,F4=0 tnen load 8-buffer vector length=1 (2's complement)

12 lower bits of raster addr.

6 upper bits of raster aadr. use new adore do not start self-test do not continue self-test draw 1st dot load Mode reg. set flag Fl

13255

Graphics M-controller

6.0

IJ255-911l5/29

Rev

MAY-04-78

GRAPHICS MICROCODE LISTING.

Tne following microcode is described by flowcharts A, Band

C (figures

8, 9, and

10).

It is stored in M-controller-s ROMs packs

U14,u15,Ulb,U17,~26.

000 (r420000 PON

001 01'60000

002 10500000

003 0560000

004 0660000

005 1300340

A

006 1002300

007 1062300

010 :2000020

CURSR

011 1400000

012

:l0420~O

013 1510000

014 :2063020

015 1540000

016 2520040

017 1520600

CURSI

0202540002

021 1540312

022 l021033

023 1420013

024

2400053

025 1400013

026 1040707

027 ~104027

030 1620000

031 2125020

032 1640000

033 3323020 CURS2

034 3020000

035 162u600

036 2657742

037 1040312

040 0000013

041 0000013

042 2420053

043 1420013

044 1041547

045 0420007

046 1162740 AO

047 3374020 A3

050 1760000

051 2721000 REF

052 1720200

053 2760042

054 ~760002

FLG F=Ol

FLG F=03

FLG f=04

FLG F=07

FLG F=11

JMP

C=12 T=CURSR

Jr1P

C=OO T=AO

JMt>

C=03 T=AO

LAB A=OO B=OO

STO A=OO

LAo

A=02 8=02

STO

A=05

LA8

A=03 8=03

STD

A=Ob

LAC

A=05 C=+0001

STU A=05

LAC

A=Ob C=+OOOu

STU A=06

LAB

A=Ol 8=01

STO A=OI

LAC

A=OO C=+OOOI

STU A=OO

J~P C=02 T=CUHSI

XL

LC

LA8 A=04 B=04

STU

A=09

LA8 A=05 8=05

S'IO A=10

LDC C=-0720

LDA A=09

STU A=09

XL

LAC A=lO

C=+7777~

STU

A=10

LC i~OP

~~OP

LAC A=Ol C=+OOOI

STU A=01

JMP

C=02 T=CURS2

FLG f=Ol

JMP C=07 T=Al

LDC

C=-0064

5TO A=15

LAC

A=13 C=+0010

STO A=13

LAC A=15 C=+OOOI

S10 A=15

L z z z

R

M

1-<

Z

~ RC

M

~C

M

RC

t-1

RC w~C

Z wRC z

R

M R

M RC

M f<C

~

RC

M RC wRC

WRC

R to<

Nfl <= 0

NF2

<=

0

NF4

<=

0

F6

<=

0

DISABLE SELF TEST

IF F5

=

I DO CURSOH

ELSE GO TO AO

IF Nfl GOTU AO

COP¥ DC 1

COP~

WAlLO

COt'Y

WA1HI

WAlLO

<= wAlLO +1 wAIHI <= wAIHI

+

Ct

COP¥

DC2

DCI

<=

DCI

+

1

IF CURSOR

CDP~ wA2LO

1

~OT

DONE, LOUP

COP~ wA2HI wA2LO

<= wA2LO 720 wA2HI

<=

~A2HI + C

OC2

<= DC2

+

1

IF CURSOR 2

NFl

<= 0

NOT

IF Vk

THEN

GO A2

DON~,

EL5~ wC

=

REfR[SH 04

RO~S

-64

SEND kOw

ADDRt:SS

LOUP wC

=

~C

+

1

13255

Graphics M-controller

13255-911:l5/30

R~V

MAY-04-78

055 1042442

056 1342342

057 0700000

060 1132340

061 1263240

062 337:7760

06.3 1760000

064 074000·0

065 33514i0

A2

Ai

066 1400000

067 3375100

070 17buOOO

071 3377020

072 1520000

073 3003760

074 1~40000

075 1163640 Ll

076 00000()1

077 2521000 L2

JMP

JMP fo'LG

JMP

JMP

LDC

STU fLG

LDC

STU

LDC

C=02 l'=HEF

C=14 I=A3

F=12

C=O~

'1'=l,UOM

C=11 l'=Al

C=+7777B

A=15

1'"=14

C=-0360

A=OO

C=-004~

STU

LDC

STU

A=15

C=-0010

A=05

LDC

S1'O

JMP

NOP

C=t00778

A=06

C=07 T=L1

LAC A=05 C=+0016

XL

R

R

C

100 1520200

101

254000~

102 1:>40312

103 0404013

STO A=05

LAC A=06

STO A=06 fo'LG f=OO

C=+OO(JO

HLT1

L

LC

104 0000013

105 0000013

• CO~TROLLEf<

106 2760040

107 1760000

110 0000000

111 0000000

11:l

0000000

113 0000000

114 2521000

11~ 1520200

~OP

NOP rlALTEO UNTIL NEXT

103.D2

LAC A=15 C=t0001

A=15

STU

NOP

NOP

NOt>

NOP

READ

A=05 C=+0016

A=05

L

116 ~54000~

117 1540312

120 2760053

121 1760013

122 1044613

123 2400053

124 1400000

125 1020240

LAC

STO

LAC

STO

LAC

Sl'O

JMP

LAC

STO

JMP

A=06 C=+OOOO

A=06

A=15 C=+OOOI

A=15

C=02 T=READ

A=OO C=+OOOI

A=OO

C=01 T=A

LC

R

M R

M

RC

M RC

M RC

PULSE

R

M

R

M

~C

M

HC

M

RC

M RC

126 0540000

127 1005600

130 0560000

131 3375160

132 1760000

133 1003740

134 1110100

135 2376020

RET1

WRITE

FLG

JMP

FLG

LDC

STO

JMP

JMP

LAB f=06

C=OO T=WRITE f=07

C=-0045

A=15

C=OO T=L2

C=04 T=Lfl

A=15 H=14

Z

IF

~C

LESS

ThA~

0

TH~N

LOOP

IF NOT

VR

uO 64 MORE RO~S

SET

VERI RtTRACE fLAG

IF F3

IHEN

GO

ZOOM

DONT SEND DISPL HITS If NUK

SEND DISPLAY

CO~TROL

'fO THt: MEMORY

BIIS

LC<=-360

WC<=-45

RALO<=-16

~AHI<=+778

IF VR

THEN

L1

CLOCK

THE CLEAR

MEMORY

LATCH

RALO<=RALOt16 f<AHI<=RAHI+ C hALT! wC<=wC+l

READ LOOP RALO<=RALOt16

RAHI<=RAHI+C wC<=WC+1

LC

=

LC t

1

IF wC<O

ThE~

GO

IF

LC=O fHEN

GO A f6<=1

GO WRITE

RE-ENTRY POINT 1 :F6

<=

0

WC<=

-45

GO READ

AGAIN

IF F2=0 THEN GO LF1

LOAD

WORD COUNT

13255

Graphics M-controller

13255-911:l5/31

REV MAY-04-78

136 1760000

137 2420000

140 1420040

141 1246640 wO

142 2064000

143

1~60600

144 2..1 05002

145

1~500312

146 2021013

147 1420053

150 2440u53

151 1440013

152 1027707

153 1007307

154 0000007

155 2062000

15t> 1460600

157 2103002

160 1500312

161 2020013

162 1420053

163 2440053

164 1440013

165 1027707 wI

STO A=15

LAC A=Ol C=+OOOO

STO A=OI

J~P

C=10 T=wl

LAB A=03 8=04

STO A=03

LAB A=04 8=05

SID A=04

LAB A=Ol 8=01

STO A=OI

LAC A=02 C=+OOOI

STO A=02

JMP

C=OI T=DONE.

JMP C=OO T=w2

NOP

LAB A=03 8=02

STO A=03

LA8 A=04 B=03

STO A=04

LAB A=Ol 8=00

STO A=OI

LAC A=02 C=+uOOI

STO A=02

166 1267541 w2

167 2760040

170 17600UU

171 1046040

J~P C=01 T=DUNE

JMP C=11 T=BAD

LAC A=15 C=+OOOI

STU A=15

JMP

C=O~

T=WU

172 1010000 JMP C=OO l=kETR,,"

173 2460000

BAD

LAC A=03 C=+OOOO

174

14b040U STU

A=03

175 0520000

FLG f=05

176 0420000 DONE fo'LG f=01

177 0460000 f~LG f=03

200 120~400

H~TRN

JMlJ C=Ob l'=R~Tl

201 1015440 JMP C=OO T=RET2

202 1070000 Lf1

JMP C=03 l'=RETHl~

203 1310000

J~;P

C=12 l'=RETRN

204 23740.l0

LA~ A=l~ B=12

205 1700040

20b 04400()O

STU

A=15

FLG r'=02

207 1250000

210

:lO46020

211 1440000

212 2027020

~13 1420000

214 i37202U

JI'llP

LAB

A=O~ 1-1=06

STU

LAti

STU

C=10 T=RFTt-<N

A=02

A=Ol B=07

A=Ol

LoAd

A=l~

8=10

215 1760040

216 l331140

217 2070020 ~3

S1'O

A=15

JMP

C=13 T=w4

LAB A=03 U=Ob

;(L

X

LC

S

S

XL

R

LC r4 tw1

R

HC

S

tl;

M

PC

RC

~1

RC

wRC

WRC

S

S

Z

Z

Z

Z

Z

M

M

M

M

R

R

RC

RC

RC

M kC wRC r-RC vvRC

SET

S

FROM §IGN

Of'

D

IF D<O

THEN

GO

WI

WALO<= WALO+M2LO wAHI<= WAHI+M2HI+CARRY

0<= D+ 02

DC<= DC+l

IF DC=O THEN GO DONE t:LSE

GO w2 wALO<= wALO+MILO wAtiI<= wAHI+MIHI+CARRY

D<= 0+

01

DC<=DC+l

If OC=O THEN GO DONE

If DATA wC<= r"OK

THEN

GO BAD we+l

IF wC=O

TH£i'4

RETURN

BIT REG <= BAD AllDR 0-3

F5<=

1 f1<=

0 f2<=

0

If'

NFl GO

RETURN

Rt::TlJRN IF CURSOR FLAG ON

IF' B(12)=1 THEN

COf'4 TIN UE.

St:Lt' TEST.

A(2)<= INlT DC

A(l)<= I r~

1 T D l~-

B(10)=1

THEN

Ft:tCH

~Ew wA

IF

!\lOT

Sf tHEN

GO w4

FETChING

13255

Grapnics M-controller

13:l~5-91125/32

~EV

MAY-04-78

220 1460000

221 2111020

222 1500000

STO A=03

LAn A=04 R=OY

STu

A=04

LAC A=03 C=+OOOO

223 2460000

~4

224 l'tbObOO

225 250.0002

226 1500212

S10

S1'O

,"=03

LAC

,~=O4

C=+OOOO

A=04

227 231303'3

230 1760053

231 0640013

232 1251b13

LAB

S10

A=I~

A=15

F'LG F=10

8=11

JMP C=10 T=WS

233 0060013

234 2377033 w5

235 1760053 fLG F=11

LAB A=15 8=15

STU A=15

JMP C=13

T=~6 236 1332113

237 0000003

240 0000007

!'4UP

241 0000007

242 2440040 W6

243 1440000

244 1267540

245 10500uO

NUt:>

NO?

LAC A=02 C=+OOOI

STO A=O:l

J~IP C=11 T=BAl>

JMP C=02 T=RETPN

246 100770()

251 1560000

JMP c=OO T=DONE.

247 1153200 ZOOM

JMP C=06 T=ZO

250

l166020

LAb A=07 B=06

S1'O A=07

252 2207020

LAB A=08 B=07

253 1600000

254 2353020

STO A=08

LAjj A=14 B=11

255 1740000

STO A=14

256 2274020

257 1660000

LAS A=11 B=12

STO A=11

260 2375020

261 1'160600

262 0740000

LAB A=15 B=13

STO A=15

FLG f=14

263 0500000

264 3351420 ZO

FLG F=04

LOC C=-0360

265 1400000

266 2560000

267 1520000

STO A=OO

LAC A=07 C=+0000

STO A=05

210 2600000

LAC A=08 C=+OOOO

271 1540000

STO A=06

272 2560000

213 1620000

LAC A=07 C=+OOOO

STO A=09

214 2600000

211 2740001

B

LAC

A=O~

C=+OOOO

215 1640000

STO A=10

216 1173700 ZVR

JMP C=07 T=ZVR

LAC A=14 C=+OOOO

300 1100000

301 2660000 Zl

STO A=12

LAC A=11 C=+OOOO

XL

Z

XL

L

R

M R

Z t-l

RC

S

M

RC

M

M

M

RC

HC

RC

S

Z

M j~

RC

RC

M

RC

RC

WRC

WRC

Z

Z

Z

Z

Z

C

NEw wALO

AND

WAHl

PUT wALO IN AR

PUT WAHl IN AR

IF B(11)=1 THEN

ENABLE SELf TEST

ELSE

DISABLE SELF TlST

IF ;3(15) =

1

THEN wRIIE

TH~

FIRST

OUT Uf

TH~

VECTOR

I)C<= OC+l

IF

DATA NOK GO BAD

IF DC<O l'HEf\4 NOT DONE

GO TO

DOl'~E

IF

UIJD

ZOOM GO ZO t::LSE A(7)<=ZASTRTLO

A(S)<=ZASTRTHI

A(14)<= -M

A(11)<=

-I(

SEND DISPLAY CONTHOL

'fO

THE MEMORY

STROBE 0 SENT TO Ml::MORY

Nf4<=

0

LC<= -360

ZALO<= ZASTRTLO

ZAHl<= ZASTHTHI

ZAOLO<= ZASTRLO

ZAOHI<= ZASTRHI wAIT fOR END OF VERT R'fRACE

RC <= -M (CLOCK CLEAR wC<= -K

13255

Graphics M-controller

13255-91125/33

REV fIlAY-04-78

302 1760000

303 2520000

304 1520200

305 2540002

306 1_540312

307 2760053

310

lil

60013

311 0404013

312 0000013

313 0000013

STO A=15

LAC A=05 C=+OOOO

STO A=05

LAC A=06 C=+OOOO

STO A=06

LAC A=15 C=+OOOI

STO A=15

FLG f=OO HLTI

NOP

NOP

L

LC

*

CONTROLLER HALT~O UNTIL

314 2521000 ZLOOP LAC A=05 C=+0016

315 1520200 STO A=05

L

316 2540002

317 1540312

LAC A=06 C=+OOOO

STO A=06 LC

320 0410013

321 27b0053

322 0000013

FLG f=OO hLT2

LAC A=15 C=+OOOI

NOP

CONTROLLER HALTED UNTIL

STO A=15

324 1054613

325 240<.J040

326 1400000

Jfv,P

C=02 T=ZLODP

LAC A=OO C=+OOOI

STO A=Ou

327 1020240

330 1005600

JMP

JMP

C=OI T=A

C=OO T=WRITE

331 2700040 Rt:T2

LAC A=12 C=+OOOI

332 1700000

333 1036040

334 2620000

STO A=12

JMP

C=OI T=Z2

LAC

A=09 C=+OOOO

335 1520000

336 :lb40000

STO A=05

LAC A=10 C=+OOOO

337 15400UO

340 1014040

341

30t>50:i0

Z2

342 3620000

343 1520000

344 1620000

345 2640000

346 1540100

347 2540000

350 Ib40000

351 3374020

352 1760000

353 0404000

354 0000000

355 0000000

S'l'O

A=Ob

JMP

C=OO T=ZI

LDC

C=+0720

LDA A=09

STO A=05

STO A=09

LAC A=10 C=+OOOO

S'fO A=06

LAC A=Ob C=+OOOO

STu A=10

LDC

C=-00b4

51'0 A=15

FLG F=OO

NOP

NOP

HLTI

C i<

M R k

RC

M RC

M

RC

M RC

M RC

103.02

R

M R

M RC

M

M

RC

RC

NeXT LOAD

M RC

M RC

PULSE

PULSE

READ

1ST wORD

~ALO wC<=wC+l

HALT

1

ZOO LOOP

ZALO

ZAHI

HALT 2 wC<=wC+l

IF WC<O GO ZLOOP

LC<= LC+l

IF LC = 0 THEN GO A

GO WRITE

RENTRY 2: RC<= RC+l

IF RC = o THEN GO Z2

ZALO<= ZADLO

ZAHl<= ZAOHI

ZAO <= ZAO + 720

ZA <= ZAO

WC <= -64

ZAHI

HALT

1

13255

GraPhics M-controller

13255-911:l5/34

REV MAY-04-78

357 2721UOO RLOOP LAC A=13

360 1720200

361

27~O042

362 17QOOO2

363 105-67,,2

364

2400042

CUNTROLLER

FL(; 1"=15 hAL'l'ED UNTIL NEXT 103.02

S10 A=13

LAC A=15

STO A=15

JMP C=02

LAC A=OO

C=+0010

C=+0001

'l'=RLOOP

C=+0001

L

R

R

R

R

365 140vOOO

30b 1020240

367 1013740

370 0000000

END

STO A=OO

JMP C=01

JMP C=OO

NOP

T=A

T=8

PULSE

TURN

SE~D

IF

THE

ROW ADDRESS wC<= WC+1

LC=O

ELSE GO

Ol~PLAY

If'

WC<O THEN LOOP

LC<= LC+1

GO A

B.

OFf

H

M t1

M

H v~ cue eLI:.

'>

~ elK

~

~

M M

.-

--

Ii

I~ r

.

~.I

I

I

'1-

S"'-AlI1L.S

JNrr~

1="A(£J'

MAr~GffAPHK~

Ols'lA'j HdI()(.e

B -

tJI6NItl-t>

l~rAC!~1J

t(J1N1

JlntMINAL fltlS,

Polt~

W

"!o

RillS c<\s

..

H

H

M

J.7

~

M

-,

Ao-"

----~

M

-----+--£.1-

~o-~ - ~

Ii

____ /2. _____________ ---' fl"F~

-------

.;...;FS"~-"!ot[)

__

~_-

_

DATA

~EA./)

B

Figure 1

Graphics M-controller Hlock Diagram

MAY-04-78 13255-~1125

rz.-M

~~'~~-+--~~-------------------r--~

______ ;-1

(!LK

..,r-COr::'

I I I I

C:O:~a:

-Zl:".J~

, • I I

~ti.d.£

I t-.ell

III

PI-'~

(.)1-/4

P'-.2.1 p,-

'1

-i

1-- - - --

-1~+Nl

1 lSoS"" R.,"

I

I

I

I

I

I

I

. - - - - ----he'"'

& ' ; '

DCCC(lER

1

~'"

I®'----~

I.,

PI-P

PI-$"

PI-IQ

1"1- II

J :ltl"')

I 1 • n ... .,.

"a...

D. a...

/t7

A&

As

'4

P2.-

F

f';t-7 r2.-

Ii.

P.2-S

A" fin

A

P2-'1

P2-1

P2-.a.

P1-1

..

)(,

P'2.-II

P2.-lo f~-9 f'2-&

L

-""-----1_ ... __ _ _ __ __ _

__-~------_-_-

______ _

I

~

I

I

I

I

I

----!...:---~---+J§>" ~~I.'"

tLS7¥

~ ,~>,.':' n~

L.

~~

._

~i--_-,b~". "J~>

-

... Nol(

-

tfl:

I~

r

~

""

~ ~I

,

,

~~

NoTIES

I)

~ ~o

('c.NIIJ(;C""OAJ

;z)

RI,R2 A.£" RE'S. rA(.~

0""

I

-

.,tlo-oo7l.

~) rl~L.

11<.n j:..EC;.

ARC ijW)

C!J\Rft.N

P'L-13

<!L.,,"

~

~c;::;..

"

«

<l

~

W

P2.-I'1

Cu:

eLi l"a..-A

P:l-c..

6HA

Gi.i:O

P2-!

P'l-$ fiGure

2

Gr~pnlcs

MA't-04-78

I

M-conttoller

SChematic D1agram

13255-91125

rz.-M

~.------

I I

rt-IS'

PI-r

;:

~ ~o :::L~:~2!~~~ ~======:====~

1'1-"

1

I

L ___

-=-= __ _

~rJli

, ' I I

~cit!:~ r)ru.w a:k~i

I i:

1'1-1

P~-I'

--'=-----;:~- :~~~

~::~:

Gr~pnlcs

r-IAY-04-78

M-controller

Schematic Diagram

13255-91125

,....

0

CD

~

""'"

0 an

[;,J]

GRAPHICS M-CONTROLLER

02640-60125 B- 1725 -42

I

U11

~

I

U12

5

I

U13

~~II

U14

~1I1

U15

@)

R3

I

U21

S

I

U22

~

I

U23

S

I

U24

~ I

Cl0

U25

C8

C3

R4

( I

U41

~

I

U42

C4

C6

s

I

U43

~

I

U44

I

U51

S

I

U52

~

I

U53

~

I

U54

C5

s

S

~I

I

U45

U55

C20

$111 s

S s

II

I

U16

Cl1

U26

U46

51

511

~

II

U17

C12

I

U27

C13

U47

C21

R5

I

U56

~

.....

(.)

I

U57

I

U61

s~1

U62

~

R7

Cl+

-------~

S

S

C22

51

I

U18

5

M

~I

U28

5

<

I

U38

S

I

U48

(

s co a:

I

U58

S

(

C15

I

U68

5

C16

I

U19

S

I

Ul10

5

51

Ulll

5

,

I

U29

5

I

U210

S

C24

I

U211

C17

S

I

U39

S

I

U310

S

I

U311

S

I

U49

S

I

U410

~

I

U411

5

-.

R1

)

C25 C18

I

-,

I

U59

~

I U510

~ I

U511

S

)

R2

C19

I

-,

I

U69

s~1

U610

~

I

U611

5--

1

-.

-.

figure 3

Graphics

~-controller

Component Location Diagram

MAY-04-7b 13255-91125

LDC

STO

Jt·1P

FLG

NOP

LAB

LAC

LDA

INSTRUCTION FORrlAT:

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

1

1

1

1

0

0

0

1

A3 A2 A1

Ao B3

A3 A2 A1

A

0

B2 B1 Bo

7

CONSTANT 1

6 5

4

1

1

A3 A2 A1

Ao

1 0 11 10 9

8

7

CONSTANT 2

6

5

4

3 2

3 2

1

1

0

0

Z r~ ~I

- R C a

I)

1 r1

~1 r1 w

W

H

0

R C

R C

R

C

0

X L

C S

0

~1 t~

R

C

0

0

1 1

A3 A2 Al Ao

~UI\~U2

1

0

1

0

7

61f\K~tl 4

0

1

F3 F2 F1 Fo H2 H1

3 2

1

0

0 r1 w

R

0

:~ w

R

C

C

0 0

0

0

r,'

t~

R

C

SHADOHED. BITS ARE DON

I

T CARE fi'lgure 4

Instruction format

MAY-04-78

13255-91125

IMAGE

MB·10RY

ADDRESS BIT ARRANGEMENT

ADDER BITS

ABSOLUTE MEM. ADDR.

17

COLUMN ADDR

11 10

WORD ADDR

RAHI OR WAHl

ROW ADDR

RALO OR WALO

BIT ADDR

o figure 5

Image Memory Address

'wlAY-04-7d

13~55-911:.l5

COLUMN Y-I

LINE

X - I - - -

I

-72(

y

-720

y+(

-719

x - - -

-I

X+,----d

-t719

/

+720

+721

+1

IMAGE MEMORY

BIT

DISPLACEMENTS.

figure b

Image Memory bit Oisplacement

MAt-04-7~ 13255-91125

ZOOM EXAMPLE

MAGNIFICATION M=4

MEM.

LOC.

M M+I oooxooox

oooxOOox

o

0

---~~OOOiOOOX

)(XXXXXXX

IN MEMORY

ON THE SCREE N

O==VISIBLE

X =BLANK

DOT

DOT figure 7

MAY-04-787

ZOOM Example

13255-9112~

0)~-------·

VE~TI

CAL

~F."n~.AC€

IAJ

P~oUt>

\ F f'I AN& F'S S€T'"

'n!E'~

Do

C(JRS.O~

IN~'

U.

T£

IItJPOT

fuFFCR.

&

IS

AVAILA~E

WHIlE

~~IT/~6 F""olC:.

VCRr/o.L

REr MC

E

.J

<;...

HE:

J.{oft

If

8

FLS,e

DO

F?€'uLA~ f(€~O

CE'NDI''iA:4)1' ,:#FA)D DI$PLAY

C4JN~1.. elT~

-n

HCf-/. 811D

I~I

TII*LI?G

LINe CctJAJ7 L

C.

WoR.O

C O()N;

R€AD tAlc-

f1DOIt~S

RA

WA/i OI../TILL

V€~"C"'L

REf!)Ac.€"

r:-IN/~IIElJ

UPOATt!"

~eAb

IfOIJI<,.I</1

iVciU)

~uAJi

we

HAL T R.oH

AOORE"~S

CcUIJTclt.

(JAJilLL $'1NC.t/.

PULSe

/Ol.

bt

Fll..o

H ttc #-to'

'1 !oA~()

OCCul?S

REAl) J...ooP

f<~~b

A

lAJo~

tJ

UPb!+T€

M

We.

I~

FRAH€

()ONF

("!hO

LIIJ€"S,)

THE"N

~o

To

A eLSE $el

FLA~r;

!-oN/)

~o

rC;)

~~

T€ ficJB (itDU TlAJG'

IN,TlIiL,

'tE

lJIf)~O ~,,~r

I<r-AJ) lIVre NGJC'T LIIJE"

Figure 8

MAY-04-7~

Flowchart A

13255-91125

Sbll/J) OISPLAY

CON"'ROi..

41TS

11= I='LAG

4

S6T it4EN COPY

PA~A/tIfc

rGIlS

;:OR IV.W ZOOM

;::-~OM ~JjF;::£1l.

, , :

START ZOOM

AOOIlGSS

MA&N/~/t:ATION

.2A

I="ACrOSl

STI&;

/VI

WOJl.O (;OI.lN T

I<

SEND OISPLAY CON;IfU)t..

41lG IN

,OCATION

d

(1,3)

Bl'rs rt4AT

LINE COUNT

/..C

1.1"'£

~ooN1

AODJlGSS

Z.4¢

CI./IlllalVT iOOM ADI)Il.

~

WAIT m. eND

O~

VERTICAi.. IlETRACE

~--......---'

UPOATE "/NE R£P£A7 COL/NT

£LS. I'IlES&T iA

Tt!)

U ¢

AND i..OoP zA

~ ~A

¢

...-_....L.._---.

fNI"'14i.iZE:

LINE R.P£AT COLiNT IlC

LINE. IlEPIiA7£D

tY/-

TIMES

TH't:1V i./POAi/Z L.INE '&ooM ADDR.

{I

~tf),'f r#~ N~XT

'-/NE AND

GoO ,0

1l£~R.ESI-I

ME"'10Iiy

- - - I

*

.--_.-L.._---,

IN

1 , /

WOIlO COL/NT we

'-R,-G',-:A-D--A-......

READ r.LIE .r:/IlST w.-'O-Il-a-,A-7-Z-A-, WOIiO 0;:' TI-IE I.INE.

2,A

~

we

~

+

1 we

~

I

UPOAT. CLlII.IlIlN.,.

'lOlJM ADOIl uPOATE W()IiIO COl/NT.

a4.

!-IAL

7

1

I-IA'-T ADOICSSS COl/NiER,

~------.---------~

NAIT PaR. SYNCf1.

PULSE

/O~.02 P~"'1

Iv1EIV1012.Y

~OAR.O

I

NAI7

~"Il

SyA/CJ.I.

PLiLSE

103.0'2 I=ROM

MEMORY !JoAIlD

200M i..OoP:

r-R-£-A-O--A-:-W~O-Il-D-A--i-i!.-A-:--1

REAO.4 N0I20.

2A

~ ~A

we

~

we

~

I i-JAI.T

~

I.!POATE 2,4

(jPOA'TE we

WALT ADOIlESS COL/Ni£/<

OIS4!J/"E OISPi.-4Y

5ENO

,&<ow

AOOQ.

I<OW

~

we

+-

we:

+1

1 - - - - - - - - - - i

UPOATE LINE CtJLlNT

ANO

ENA~LE

O/SPLAY

NAli I=OIl L.OAO

PLli..S. .r:1l0M

MEMOI2.Y 6oARO

11= K. WOt:lO NO, IlEAD

TI-IGN LOOP

E'-~&

l./PoATE LING COUNT

11= FIlA""'£ (360 '-IIII.'S) OONe

I;: I=IlA""'E 00A/& n ..

/EN

GO ro "A"

ElSE STAM!.;

Z~1Vf

ON Nax; l1N6.

JIf

IZG!!'~GSi-I

:

':::JI..I.QIIi/~

.t:J..J:Il.ESf1

(I

~/N&)'

;1-1.

OISP~4Y

/S

i:)ISAa~So

AND

"4

JZ.oWS 01='

- - -

--

~------

MaM()Il.Y el-/IPS AilE

R.~.r:~GSI-I~O

A

flqure 9

MAY-04-78 flowcnart B

13:l55-91125

I;:

.&t.A(#

2

SET

T;.I4N VEc;OR

DRAWING, IS IN

P~OGo~"SS

GI..SE.

IN TGIlROGATJii

;::-~AGr

.J

L.OAD WilliE 00;

CO"""', INTO

We:::

it,.

IS NI).

O~ O~rs

Wil/

TrAN \

\'PEAl

!-IOIlIZOAlTAI.

~.TIl.AC.)

Jl.£4 D MOO. -

WIi!./ I .

C.4EC/I( SI(6oN 01=

4) i.

()()P l/POATS SJ..I)P£ D AND

WlIllr. AI)OIZESS

~O~

wA poslrw.

S/(i,IV I:OIl

- - ' - - - -

.

I

I

~-/Y1-W

I

READ

-N'lOD/~Y-

40DICS~S WA

WR.Jr/;

,;.Ie 81T AT W!l./IE

ADO; AT WA t/POAi£ 00;

cO~NT

'(

.---'----'--....., STORE

41..5~'

~~

WA

I . . . - - T - . . . . I

INO/CArli

SEI..~-;ESr

.t:A/4EtJ

NO. i/PJ:)A 7 ;

WIlI;E 007 COI.INr

I..AST OOT otc'

Tl-la

I-I~RllOII/TA~

IlET~4CE

?

~U~~GIl

I!J

AVA/4.4S46

II!"

~i.A(i

J

SET r;.l&A/

8UF~EIl

I!!J

IS 1='1.11.1-

ELsa

G)(/'r WlZlrE

St/S~OI.lTIf\l1

,cLAG

5

SGT

INo/cAre

THAT

INPI.II

~u,r:~£R

CONT411VS

04TA f:"a,q

CI.I~.sO~,

/iX-Ii

WRit&'

I~

MS!3

IN /..OC. 8(12) SiT

;I-fEN CONTINI.IE 5£1.1=·

TEST

EI..SE

COPy INITIAl.. OaT

AND /NITI,41.. VAlUE o'&:

SkOPJ:

0

If:

/VIsa IN 1.0CA;ION

8

(to)

IS SE7

THEN

C.OPY N.£'IV

WIlITG

ADDt:l.E SS

I

WA. r

15 STAJl r

ADDRESS

0,1:"

A

NEW

VECTOR

I.t: MSd IN 1..0CA710/l/

d

(11)15

SET

T{wji:.N

GN.4/!I.E O,4TA

cw£c~

(I.ISIiO ONLY IN SEI.I=-TEsr)

R~AD·

Moo/f."Y·

NIl.I rs

i!-lE / V'

OOT

OF Ti-IE VSCTOIi!.

LlP0.4TE oor

COI.INi

OI.lCIN&

~EJ..f:-

i.£sr c.I-Iecl<

O.4i~

VE~TOIZ.

If:

yES

OON.?

r~£N

rNDICATE

BUFF£~

~

AVAILA"I-S

_LSE

INCICATI r.J.IAT

V't:.;O~

OIlAWI!l/tJ,

I~

IN

PR06.c6SS

'£)(/7 TO

P.r.l{)PEIl. POINT

figure

10

MA~-04-18

Flowchart C

13255-91125

Replaceable Parts

Reference

Designation

U51

U52

U53

U54

U55

U56

U57

U58

U59 u41

U42

U43

U44

U45

U46

U47

U48

U49

U21

U22

U23

U24

U25

U26

U27

U28

U29

U30

U38

U39

Cl

C2 thru C19

C20 thru C27

E1 thru E3

Rl thru R2

R3 thru

R8

U14

U15

U16

U17

Ul8

U19

U61

U62

U68

U69

U110

Ul11

U210

U211

U310

U311

U410

U411

U510

U511

U610

U611

Ull

U12

U13

XU14 thru X1J17

XU26

Replaceable Parts

HP Part

Number

02640-60125

Qty

1

Description

ASSEMBLY GRAPHICS M-CONTROLLER

DATE CODE: 8-1725-42

CAPACITOR-39UF 10V

CAPACITOR-.OIUF

CAPACITOR-O.IUF

STUD SOLDER TERM

NETWORK-RES SIP

RESISTOR 1000 5% .25

IC MEMORY

IC MEMORY

IC MEMORY

IC MEMORY

IC SN74S189N

IC SN74LS298N

IC SN74LS74N

IC SN74LS74N

IC SN74LS279N

IC SN74LS175N

IC SN74LS273N

IC MEMORY

IC SN74LS273N

IC SN74S189N

IC SN74LS298N

IC SN74S189N

IC SN74LS298N

IC SN74S251N

IC SN74S251N

IC SN74S138

IC SN74S74N

IC SN74S163N

IC SN74S163N

IC SN74LS157N

IC SN74LS157N

IC SN74LS175N

IC SN74LS74N

IC SN74S74N

IC SN74S04N

IC SN74LS38N

IC SN74LS138N

IC SN74LS136N

IC SN74LS05N

IC SN74LS74N

IC SN74LS175N

IC SN74LS08N

IC SN74LSOON

IC SN74S00N

IC SN74LS175N

IC 74S283

IC SN74LS298N

IC 74S283

IC SN74LS298N

IC 74S283

IC SN74LS174N

IC SN74S189N

IC SN74LS74N

IC SN74S189N

IC SN74LS38N

IC SN74S189N

IC SN74S08N

IC SN74S00N

IC SN74LS138N

IC SN74LS138N

SOCKET 16-DIP SLDR

SOCKET 16-DIP SLDR

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

4

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

18

8

3

1816-0724

1820-1444

1820-1302

1820-1302

1820-1240

1820-0693

1820-1453

1820-1453

1820-1470

1820-1470

1820-1195

1820-1112

1820-0693

1820-0683

1820-1209

1820-1216

1820-1215

1820-1200

1820-1112

1820-1195

1820-1201

1820-1197

1820-0681

1820-1195

1820-1871

1820-1444

1820-1871

1820-1444

1820-1871

1820-1196

L816-0724

1820-1112

1816-0724

1820-1209

1816-0724

1820-1367

1820-0681

1820-1216

1820-1216

1200-0607

1200-0607

0180-0393

0160-2055

0150-0121

0360-0124

1810-0076

0683-1025

1816-1121

1816-1123

1816-1122

1816-1124

1816-0724

1820-1444

1820-1112

1820-1112

1820-1440

1820-1195

1820-1730

1816-1125

1820-1730

1816-0724

1820-1444

Mfr

Code

Replaceable Parts

Mfr Part Number