M950x0 M950x0-W M950x0-R with high-speed clock

M950x0 M950x0-W M950x0-R with high-speed clock
M950x0
M950x0-W M950x0-R
4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM
with high-speed clock
Features
■
Compatible with SPI bus serial interface
(Positive clock SPI modes)
■
Single supply voltage:
– 4.5 V to 5.5 V for M950x0
– 2.5 V to 5.5 V for M950x0-W
– 1.8 V to 5.5 V for M950x0-R
■
High speed
– 10 MHz Clock rate, 5 ms write time
■
Status Register
■
Byte and Page Write (up to 16 bytes)
■
Self-timed programming cycle
■
Adjustable size read-only EEPROM area
■
Enhanced ESD protection
■
More than 1 Million write cycles
■
More than 40-year data retention
■
Packages
– RoHS-compliant and Halogen-free
(ECOPACK2®)
Table 1.
SO8 (MN)
150 mil width
UFDFPN8 (MB or MC)
2 × 3 mm
Device summary
Reference
TSSOP8 (DW)
169 mil width
Part number
M95040
M95040
M95040-W
M95040-R
M95020
M95020
M95020-W
M95020-R
M95010
M95010
M95010-W
M95010-R
February 2012
Doc ID 6512 Rev 10
1/44
www.st.com
1
Contents
M950x0 M950x0-W M950x0-R
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.9
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.9.1
3
2.9.3
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
4
2.9.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/44
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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6.3.3
7
Contents
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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List of tables
M950x0 M950x0-W M950x0-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
4/44
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M950x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M950x0-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M950x0-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC characteristics (M950x0-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics (M950x0, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (M950x0-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M950x0-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AC characteristics (M950x0-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO8N — 8-lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSSOP8 — 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . 38
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SO8N — 8-lead plastic small outline 150 mils body width, package outline. . . . . . . . . . . . 37
TSSOP8 — 8-lead thin shrink small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . 38
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Description
1
M950x0 M950x0-W M950x0-R
Description
The M95040 is a 4 Kbit (512 x 8) electrically erasable programmable memory (EEPROM),
accessed by a high-speed SPI-compatible bus. The other members of the family (M95020
and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively).
Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD). WRITE instructions are disabled by Write Protect
(W).
Figure 1.
Logic diagram
VCC
D
Q
C
S
M95xxx
W
HOLD
VSS
AI01789C
Figure 2.
8-pin package connections
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01790D
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
6/44
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M950x0 M950x0-W M950x0-R
Table 2.
Description
Signal names
Signal name
Function
C
Serial Clock
D
Serial Data input
Q
Serial Data output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply voltage
VSS
Ground
Doc ID 6512 Rev 10
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Signal description
2
M950x0 M950x0-W M950x0-R
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals can be held high or low (according to voltages of VIH, VOH,
VIL or VOL, as specified in Table 13: DC characteristics (M950x0, device grade 3) to
Table 16: DC characteristics (M950x0-R, device grade 6)). These signals are described
next.
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
8/44
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M950x0 M950x0-W M950x0-R
2.6
Signal description
Write Protect (W)
This input signal is used to control whether the memory is write protected. When Write
Protect (W) is held low, writes to the memory are disabled, but other operations remain
enabled. Write Protect (W) must either be driven high or low, but must not be left floating.
2.7
VSS ground
VSS is the reference for the VCC supply voltage.
2.8
Supply voltage (VCC)
2.9
Supply voltage (VCC)
2.9.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8: Operating
conditions (M950x0), Table 9: Operating conditions (M950x0-W) and Table 10: Operating
conditions (M950x0-R)). This voltage must remain stable and valid until the end of the
transmission of the instruction and, for a Write instruction, until the completion of the internal
write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to
decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF)
close to the VCC/VSS package pins.
2.9.2
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the internal reset threshold voltage (this threshold is defined in Table 8: Operating
conditions (M950x0), Table 9: Operating conditions (M950x0-W) and Table 10: Operating
conditions (M950x0-R) as VRES).
When VCC passes over the POR threshold, the device is reset and is in the following state:
●
in Standby Power mode
●
deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
●
Status register value:
–
the Write Enable Latch (WEL) is reset to 0
–
Write In Progress (WIP) is reset to 0
–
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode. The device must not be accessed until VCC reaches a valid and stable VCC
voltage within the specified [VCC(min), VCC(max)] range defined in Table 8: Operating
conditions (M950x0), Table 9: Operating conditions (M950x0-W) and Table 10: Operating
conditions (M950x0-R).
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Signal description
2.9.3
M950x0 M950x0-W M950x0-R
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 3: Bus master and memory devices on the SPI bus).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 8: Operating conditions (M950x0), Table 9: Operating conditions (M950x0W) and Table 10: Operating conditions (M950x0-R) and the rise time must not vary faster
than 1 V/µs.
2.9.4
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 8: Operating conditions (M950x0), Table 9:
Operating conditions (M950x0-W) and Table 10: Operating conditions (M950x0-R)), the
device must be:
10/44
●
deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
●
in Standby Power mode (there should not be any internal write cycle in progress).
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3
Connecting to the SPI bus
Connecting to the SPI bus
The device is fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3: Bus master and memory devices on the SPI bus shows an example of three
memory devices connected to an MCU, on an SPI bus. Only one memory device is selected
at a time, so only one memory device drives the Serial Data output (Q) line at a time, the
other memory devices are high impedance.
The pull-up resistor R (represented in Figure 3: Bus master and memory devices on the SPI
bus) ensures that a device is not selected if the bus master leaves the S line in the high
impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an Instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.
Figure 3.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
Bus master
SPI mmory
device
R
CS3
VCC
C Q D
VSS
VCC
C Q D
VSS
SPI memory
device
R
VSS
SPI memory
device
R
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12304b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Doc ID 6512 Rev 10
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Connecting to the SPI bus
3.1
M950x0 M950x0-W M950x0-R
SPI modes
The device can be driven by a microcontroller with its SPI peripheral running in either of the
two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4: SPI modes supported, is the
clock polarity when the bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
12/44
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M950x0 M950x0-W M950x0-R
Operating features
4
Operating features
4.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5: Hold condition activation).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5: Hold condition activation also shows what happens if the rising and falling edges
are not timed to coincide with Serial Clock (C) being low.
Figure 5.
Hold condition activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
4.2
Status register
Figure 6: Block diagram shows the position of the Status register in the control logic of the
device. This register contains a number of control bits and status bits, as shown in Table 5:
Status register format. For a detailed description of the Status register bits, see Section 6.3:
Read Status Register (RDSR).
Doc ID 6512 Rev 10
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Operating features
4.3
M950x0 M950x0-W M950x0-R
Data protection and protocol control
To help protect the device from data corruption in noisy or poorly controlled environments, a
number of safety features have been built in to the device. The main security measures can
be summarized as follows:
●
The WEL bit is reset at power-up.
●
Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to
start a non-volatile Write cycle (in the memory array or in the Status register).
●
Accesses to the memory array are ignored during the non-volatile programming cycle,
and the programming cycle continues unaffected.
●
Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the
next rising edge of Serial Clock (C).
For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the
eighth bit of a data byte, depending on the instruction (except in the case of RDSR and
READ instructions). Moreover, the “next rising edge of CLOCK” might (or might not) be the
next bus transaction for some other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by
ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is
complete.
Table 3.
Write-protected block size
Status register bits
Protected array addresses
Protected block
14/44
BP1
BP0
M95040
M95020
M95010
0
0
none
none
none
none
0
1
Upper quarter
180h - 1FFh
C0h - FFh
60h - 7Fh
1
0
Upper half
100h - 1FFh
80h - FFh
40h - 7Fh
1
1
Whole memory
000h - 1FFh
00h - FFh
00h - 7Fh
Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R
Memory organization
The memory is organized as shown in Figure 6: Block diagram.
Figure 6.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
Y Decoder
5
Memory organization
1 Page
X Decoder
AI01272C
Doc ID 6512 Rev 10
15/44
Instructions
6
M950x0 M950x0-W M950x0-R
Instructions
Each instruction starts with a single-byte code, as summarized in Table 4: Instruction set.
If an invalid instruction is sent (one not contained in Table 4: Instruction set), the device
automatically deselects itself.
Table 4.
Instruction set
Instruction
Description
Instruction Format
WREN
Write Enable
0000 X110(1)
WRDI
Write Disable
0000 X100(1)
RDSR
Read Status Register
0000 X101(1)
WRSR
Write Status Register
0000 X001(1)
READ
Read from Memory Array
0000 A8011(2)
WRITE
Write to Memory Array
0000 A8010(2)
1. X = Don’t Care.
2. A8 = 1 for the upper half of the memory array of the M95040, and 0 for the lower half, and is Don’t Care for
other devices.
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7: Write Enable (WREN) sequence, to send this instruction to the
device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on
Serial Data Input (D). The device then enters a wait state. It waits for a the device to be
deselected, by Chip Select (S) being driven high.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI01441D
16/44
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M950x0 M950x0-W M950x0-R
6.2
Instructions
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8: Write Disable (WRDI) sequence, to send this instruction to the device,
Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data
Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion
●
Write Protect (W) line being held low.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03790D
Doc ID 6512 Rev 10
17/44
Instructions
6.3
M950x0 M950x0-W M950x0-R
Read Status Register (RDSR)
The Read Status Register instruction is used to read the Status Register.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven low.
The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current state
of the bits in the Status register is shifted out, on Serial Data Out (Q). The Read Cycle is
terminated by driving Chip Select (S) high.
The Status Register is always readable, even if a Write or Write Status Register cycle is in
progress. During a Write Status Register cycle, the values of the non-volatile bits (BP0,
BP1) become available when a new RDSR instruction is executed, after completion of the
Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write In
Progress (WIP)) are dynamically updated during the ongoing Write cycle.
It is also possible to read the Status Register contents continuously, as described in
Figure 9.
Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status
register are as follows:
Table 5.
Status register format
b7
1
b0
1
1
1
BP1
BP0
WEL
WIP
Block Protect bits
Write Enable Latch bit
Write In Progress bit
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 3: Write-protected block size) becomes
protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.
18/44
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M950x0 M950x0-W M950x0-R
Figure 9.
Instructions
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
MSB
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI01444D
Doc ID 6512 Rev 10
19/44
Instructions
6.4
M950x0 M950x0-W M950x0-R
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
register. Before it can be accepted, a Write Enable (WREN) instruction must previously have
been executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
sending the instruction code followed by the data byte on Serial Data input (D), and driving
the Chip Select (S) signal high. Chip Select (S) must be driven high after the rising edge of
Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not
executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed write cycle that takes tW to complete (as specified in Table 13: DC characteristics
(M950x0, device grade 3) to Table 20: AC characteristics (M950x0-R, device grade 6)). The
instruction sequence is shown in Figure 10: Write Status Register (WRSR) sequence.
While the Write Status Register cycle is in progress, the Status register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
reset at the end of the write cycle tW.
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits which define the size of the area that is to be treated as read only, as defined
in Table 3: Write-protected block size.
The contents of the BP1, BP0 bits are updated after the completion of the WRSR
instruction, including the tW write cycle.
The Write Status Register (WRSR) instruction has no effect on the b7, b6, b5, b4, b1 and b0
bits in the Status register. Bits b7, b6, b5, b4 are always read as 0.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI01445B
20/44
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M950x0 M950x0-W M950x0-R
Instructions
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, after the
eighth bit, b0, of the data byte has been latched in
●
if Write Protect (W) is low during the WRSR command (instruction, address and data)
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Instructions
6.5
M950x0 M950x0-W M950x0-R
Read from Memory Array (READ)
As shown in Figure 11: Read from Memory Array (READ) sequence, to send this instruction
to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address
byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant
address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 4:
Instruction set. The address is loaded into an internal address register, and the byte of data
at that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, an internal bit-pointer is automatically
incremented at each clock cycle, and the corresponding data bit is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Table 6.
Address range bits
Device
Address Bits
M95040
M95020
M95010
A8-A0
A7-A0
A6-A0
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
C
Instruction
D
A8
Byte Address
A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High Impedance
7
Q
6
5
4
3
2
1
0
AI01440E
1. Depending on the memory size, as shown in Table 6: Address range bits, the most significant address bits
are Don’t Care.
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M950x0 M950x0-W M950x0-R
6.6
Instructions
Write to Memory Array (WRITE)
As shown in Figure 12: Byte Write (WRITE) sequence, to send this instruction to the device,
Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least
one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by
driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle,
triggered by the rising edge of Chip Select (S), continues for a period tW (as specified in
Table 13: DC characteristics (M950x0, device grade 3) to Table 20: AC characteristics
(M950x0-R, device grade 6)). After this time, the Write in Progress (WIP) bit is reset to 0.
In the case of Figure 12: Byte Write (WRITE) sequence, Chip Select (S) is driven high after
the eighth bit of the data byte has been latched in, indicating that the instruction is being
used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown
in Figure 13: Page Write (WRITE) sequence, the next byte of input data is shifted in, so that
more than a single byte, starting from the given address towards the end of the same page,
can be written in a single internal Write cycle. If Chip Select (S) still continues to be driven
low, the next byte of input data is shifted in, and used to overwrite the byte at the start of the
current page.
The instruction is not accepted, and is not executed, under the following conditions:
Note:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and
before the next rising edge of Serial Clock (C) occurs anywhere on the bus)
●
if Write Protect (W) is low or if the addressed page is in the area protected by the Block
Protect (BP1 and BP0) bits
The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction
D
A8
Byte Address
A7 A6 A5 A4 A3 A2 A1 A0 7
Data Byte
6
5
4
3
2
1
0
High Impedance
Q
AI01442D
1. Depending on the memory size, as shown in Table 6: Address range bits, the most significant address bits
are Don’t Care.
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Instructions
M950x0 M950x0-W M950x0-R
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
Instruction
Byte Address
A8
D
Data Byte 1
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
7
143
142
141
140
139
138
137
136
15+8N
14+8N
13+8N
12+8N
11+8N
10+8N
9+8N
24 25 26 27 28 29 30 31
8+8N
S
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte N
1
0
7
6
5
4
3
2
Data Byte 16
1
0
7
6
5
4
3
2
1
0
AI01443D
1. Depending on the memory size, as shown in Table 6: Address range bits, the most significant address bits
are Don’t Care.
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M950x0 M950x0-W M950x0-R
Power-up and delivery states
7
Power-up and delivery states
7.1
Power-up state
After Power-up, the device is in the following state:
●
low power Standby Power mode
●
deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
●
not in the Hold Condition
●
the Write Enable Latch (WEL) is reset to 0
●
Write In Progress (WIP) is reset to 0
The BP1 and BP0 bits of the Status register are unchanged from the previous power-down
(they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1
and BP0) bits are initialized to 0.
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Maximum rating
8
M950x0 M950x0-W M950x0-R
Maximum rating
Stressing the device outside the ratings listed in Table 7: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 7.
Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
Lead temperature during soldering
see note
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
VCC+1.0
V
IOL
DC output current (Q = 0)
-
5
mA
IIH
DC output current (Q = 1)
-
5
mA
–0.50
6.5
V
-
4000
V
VCC
VESD
Supply voltage
Electrostatic pulse (Human Body Model)
voltage(2)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with JEDEC
Std JESD22-A114, C1=100pF, R1=1500Ω, R2=500Ω)
26/44
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M950x0 M950x0-W M950x0-R
9
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (M950x0)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
4.5
5.5
V
Ambient operating temperature (device grade 3)
–40
125
°C
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (M950x0-W)
Symbol
VCC
TA
Table 10.
Parameter
Operating conditions (M950x0-R)
Symbol
VCC
TA
Table 11.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
AC test measurement conditions
Symbol
CL
Parameter
Load capacitance
30
Input rise and fall times
-
pF
50
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
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DC and AC parameters
M950x0 M950x0-W M950x0-R
Figure 14. AC test measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 12.
Symbol
COUT
CIN
Capacitance
Parameter
Test condition
Min.
Max.
Unit
VOUT = 0 V
-
8
pF
Input capacitance (D)
VIN = 0 V
-
8
pF
Input capacitance (other pins)
VIN = 0 V
-
6
pF
Output capacitance (Q)
1. Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz.
Table 13.
Symbol
DC characteristics (M950x0, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
VIN = VSS or VCC
-
±2
µA
S = VCC, VOUT = VSS or VCC
-
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open
-
3
mA
S = VCC, VIN = VSS or VCC
VCC = 5 V
-
5
µA
ILI
Input leakage current
ILO
Output leakage current
ICC
Supply current
ICC1
Supply current
(Standby Power mode)
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
IOL = 2 mA, VCC = 5 V
-
0.4
V
VOH
Output high voltage
IOH = –2 mA, VCC = 5 V
0.8 VCC
-
V
2.5
4.0
V
VRES(1)
Internal reset threshold
voltage
1. Characterized only, not 100% tested.
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M950x0 M950x0-W M950x0-R
Table 14.
Symbol
DC and AC parameters
DC characteristics (M950x0-W, device grade 6)
Parameter
Test condition
Min.
Max.
Unit
VIN = VSS or VCC
-
±2
µA
S = VCC, VOUT = VSS or VCC
-
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
-
2
mA
S = VCC, VIN = VSS or VCC
VCC = 2.5 V
-
1
µA
ILI
Input leakage current
ILO
Output leakage current
ICC
Supply current
ICC1
Supply current
(Standby Power mode)
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
IOL = 1.5 mA, VCC = 2.5 V
-
0.4
V
VOH
Output high voltage
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
-
V
1.0
1.65
V
VRES(1)
Internal reset threshold
voltage
1. Characterized only, not 100% tested.
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DC and AC parameters
Table 15.
Symbol
M950x0 M950x0-W M950x0-R
DC characteristics (M950x0-W, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
VIN = VSS or VCC
-
±2
µA
ILI
Input leakage current
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
-
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
-
2
mA
ICC1
Supply current
(Standby Power mode)
S = VCC, VIN = VSS or VCC
VCC = 2.5 V
-
2
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
IOL = 1.5 mA, VCC = 2.5 V
-
0.4
V
VOH
Output high voltage
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
-
V
1.0
1.65
V
Min.
Max.
Unit
VRES
(1)
Internal reset threshold voltage
1. Characterized only, not 100% tested.
Table 16.
Symbol
DC characteristics (M950x0-R, device grade 6)
Parameter
Test condition
ILI
Input leakage current VIN = VSS or VCC
-
±2
µA
ILO
Output leakage
current
S = VCC, voltage applied on Q = VSS or
VCC
-
±2
µA
VCC = 2.5 V, C = 0.1 VCC or 0.9VCC,
fC = 5 MHz, Q = open
-
3
mA
VCC = 1.8 V, C = 0.1VCC or 0.9VCC at
max clock frequency, Q = open
-
2
mA
VCC = 5.0 V, S = VCC, VIN = VSS or VCC
-
2
µA
VCC = 2.5 V, S = VCC, VIN = VSS or VCC
-
1
µA
VCC = 1.8 V, S = VCC, VIN = VSS or VCC
-
1
µA
2.5 V < VCC < 5.5 V
–0.45
0.3VCC
V
1.8 V < VCC < 2.5 V
–0.45
0.25VCC
V
2.5 V < VCC < 5.5 V
0.7VCC
VCC+1
V
1.8 V < VCC < 2.5 V
0.75VCC
VCC+1
V
VCC = 2.5 V, IOL = 1.5 mA,
or VCC = 5.5 V, IOL = 2 mA
-
0.2VCC
V
VCC = 1.8 V, IOL = 0.15 mA
-
0.3
V
0.8VCC
-
V
1.0
1.65
V
ICCR
ICC1
Supply current
(Read)
Supply current
(Standby)
VIL
Input low voltage
VIH
Input high voltage
VOL
VOH
VRES(1)
Output low voltage
Output high voltage
VCC = 2.5 V, IOH = –0.4 mA,
or VCC = 5.5 V, IOH = –2 mA,
or VCC = 1.8 V, IOH = –0.1 mA
Internal reset
threshold voltage
1. Characterized only, not 100% tested.
30/44
Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R
Table 17.
DC and AC parameters
AC characteristics (M950x0, device grade 3)
Test conditions specified in Table 11 and Table 8
Symbol
Alt.
Min.
Max.
Unit
fC
fSCK
Clock frequency
D.C.
5
MHz
tSLCH
tCSS1
S active setup time
90
-
ns
tSHCH
tCSS2
S not active setup time
90
-
ns
tSHSL
tCS
S deselect time
100
-
ns
tCHSH
tCSH
S active hold time
90
-
ns
S not active hold time
90
-
ns
tCHSL
Parameter
tCH(1)
tCLH
Clock high time
90
-
ns
tCL(1)
90
-
ns
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
1
µs
tCHCL
(2)
tFC
Clock fall time
1
µs
tDVCH
tDSU
Data in setup time
20
-
ns
tCHDX
tDH
Data in hold time
30
-
ns
tHHCH
Clock low hold time after HOLD not active
70
-
ns
tHLCH
Clock low hold time after HOLD active
40
-
ns
tCLHL
Clock low setup time before HOLD active
0
-
ns
tCLHH
Clock low setup time before HOLD not active
0
-
ns
Output disable time
-
100
ns
Clock low to output valid
-
60
ns
tSHQZ
(2)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
0
-
ns
tQLQH(2)
tRO
Output rise time
-
50
ns
tQHQL(2)
tFO
Output fall time
-
50
ns
tHHQV
tLZ
HOLD high to output valid
-
50
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
-
100
ns
tW
tWC
Write time
-
5
ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
Doc ID 6512 Rev 10
31/44
DC and AC parameters
Table 18.
M950x0 M950x0-W M950x0-R
AC characteristics (M950x0-W, device grade 6)
Test conditions specified in Table 11 and Table 9
Symbol
Alt.
Min.
Max.
Unit
fC
fSCK
Clock frequency
D.C.
10
MHz
tSLCH
tCSS1
S active setup time
15
-
ns
tSHCH
tCSS2
S not active setup time
15
-
ns
tSHSL
tCS
S deselect time
40
-
ns
tCHSH
tCSH
S active hold time
25
-
ns
S not active hold time
15
-
ns
tCHSL
Parameter
tCH(1)
tCLH
Clock high time
40
-
ns
(1)
tCLL
Clock low time
40
-
ns
tCLCH
(2)
tRC
Clock rise time
-
1
µs
tCHCL
(2)
tFC
Clock fall time
-
1
µs
tCL
tDVCH
tDSU
Data in setup time
15
-
ns
tCHDX
tDH
Data in hold time
15
-
ns
tHHCH
Clock low hold time after HOLD not active
15
-
ns
tHLCH
Clock low hold time after HOLD active
20
-
ns
tCLHL
Clock low setup time before HOLD active
0
-
ns
tCLHH
Clock low setup time before HOLD not active
0
-
ns
Output disable time
-
25
ns
Clock low to output valid
-
35
ns
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
0
-
ns
tQLQH
(2)
tRO
Output rise time
-
20
ns
tQHQL
(2)
tFO
Output fall time
-
20
ns
tHHQV
tLZ
HOLD high to output valid
-
25
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
-
35
ns
tW
tWC
Write time
-
5
ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
32/44
Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R
Table 19.
DC and AC parameters
AC characteristics (M950x0-W, device grade 3)
Test conditions specified in Table 11 and Table 9
Symbol
Alt.
Min.
Max.
Unit
fC
fSCK
Clock frequency
D.C.
5
MHz
tSLCH
tCSS1
S active setup time
90
-
ns
tSHCH
tCSS2
S not active setup time
90
-
ns
tSHSL
tCS
S deselect time
100
-
ns
tCHSH
tCSH
S active hold time
90
-
ns
S not active hold time
90
-
ns
tCHSL
Parameter
tCH(1)
tCLH
Clock high time
90
-
ns
(1)
tCLL
Clock low time
90
-
ns
tCLCH(2)
tRC
Clock rise time
-
1
µs
tCHCL(2)
tFC
Clock fall time
-
1
µs
tDVCH
tDSU
Data in setup time
20
-
ns
tCHDX
tDH
Data in hold time
30
-
ns
tHHCH
Clock low hold time after HOLD not active
70
-
ns
tHLCH
Clock low hold time after HOLD active
40
-
ns
tCLHL
Clock low setup time before HOLD active
0
-
ns
tCLHH
Clock low setup time before HOLD not active
0
-
ns
Output disable time
-
100
ns
Clock low to output valid
-
60
ns
tCL
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
0
-
ns
tQLQH(2)
tRO
Output rise time
-
50
ns
(2)
tFO
Output fall time
-
50
ns
tHHQV
tLZ
HOLD high to output valid
-
50
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
-
100
ns
tW
tWC
Write time
-
5
ms
tQHQL
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
Doc ID 6512 Rev 10
33/44
DC and AC parameters
Table 20.
M950x0 M950x0-W M950x0-R
AC characteristics (M950x0-R, device grade 6)
Test conditions specified in Table 11 and Table 10(1)
Symbol
Alt.
Min.
Max.
Unit
fC
fSCK
Clock frequency
D.C.
5
MHz
tSLCH
tCSS1
S active setup time
90
-
ns
tSHCH
tCSS2
S not active setup time
90
-
ns
tSHSL
tCS
S deselect time
100
-
ns
tCHSH
tCSH
S active hold time
90
-
ns
S not active hold time
90
-
ns
tCHSL
Parameter
tCH(2)
tCLH
Clock high time
90
-
ns
tCL(1)
tCLL
Clock low time
90
-
ns
tCLCH
(3)
tRC
Clock rise time
-
1
µs
tCHCL
(2)
tFC
Clock fall time
-
1
µs
tDVCH
tDSU
Data in setup time
20
-
ns
tCHDX
tDH
Data in hold time
30
-
ns
tHHCH
Clock low hold time after HOLD not active
70
-
ns
tHLCH
Clock low hold time after HOLD active
40
-
ns
tCLHL
Clock low setup time before HOLD active
0
-
ns
tCLHH
Clock low setup time before HOLD not active
0
-
ns
Output disable time
-
100
ns
Clock low to output valid
-
80
ns
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
0
-
ns
tQLQH
(2)
tRO
Output rise time
-
50
ns
tQHQL
(2)
tFO
Output fall time
-
50
ns
tHHQV
tLZ
HOLD high to output valid
-
50
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
-
100
ns
tW
tWC
Write time
-
5
ms
1. The test flow guarantees the AC parameter values defined in this table (when VCC = 1.8 V) and the AC
parameter values defined in Table 18: AC characteristics (M950x0-W, device grade 6) (when VCC = 2.5 or
when VCC = 5.0 V).
2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
3. Value guaranteed by characterization, not 100% tested in production.
34/44
Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R
DC and AC parameters
Figure 15. Serial input timing
tSHSL
S
tCHSL
tCH
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCL
tCLCH
tCHDX
D
Q
LSB IN
MSB IN
High impedance
AI01447d
Figure 16. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQV
Q
HOLD
AI01448c
Doc ID 6512 Rev 10
35/44
DC and AC parameters
M950x0 M950x0-W M950x0-R
Figure 17. Serial output timing
S
tCH
tSHSL
C
tCLQV
tCLCH
tCHCL
tCL
tSHQZ
tCLQX
Q
tQLQH
tQHQL
ADDR
D LSB IN
AI01449f
36/44
Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R
10
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers the device in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 18. SO8N — 8-lead plastic small outline 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 21.
SO8N — 8-lead plastic small outline, 150 mils body width, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
-
-
1.75
-
-
0.0689
A1
-
0.1
0.25
-
0.0039
0.0098
A2
-
1.25
-
-
0.0492
-
b
-
0.28
0.48
-
0.011
0.0189
c
-
0.17
0.23
-
0.0067
0.0091
ccc
-
-
0.1
-
-
0.0039
D
4.9
4.8
5
0.1929
0.189
0.1969
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
-
-
0.05
-
-
h
-
0.25
0.5
-
0.0098
0.0197
k
-
0°
8°
-
0°
8°
L
-
0.4
1.27
-
0.0157
0.05
L1
1.04
-
-
0.0409
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 6512 Rev 10
37/44
Package mechanical data
M950x0 M950x0-W M950x0-R
Figure 19. TSSOP8 — 8-lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 22.
TSSOP8 — 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
-
-
1.2
-
-
0.0472
A1
-
0.05
0.15
-
0.002
0.0059
A2
1
0.8
1.05
0.0394
0.0315
0.0413
b
-
0.19
0.3
-
0.0075
0.0118
c
-
0.09
0.2
-
0.0035
0.0079
CP
-
-
0.1
-
-
0.0039
D
3
2.9
3.1
0.1181
0.1142
0.122
e
0.65
-
-
0.0256
-
-
E
6.4
6.2
6.6
0.252
0.2441
0.2598
E1
4.4
4.3
4.5
0.1732
0.1693
0.1772
L
0.6
0.45
0.75
0.0236
0.0177
0.0295
L1
1
-
-
0.0394
-
-
α
-
0°
8°
-
0°
8°
N (number of leads)
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
38/44
Doc ID 6512 Rev 10
8
M950x0 M950x0-W M950x0-R
Package mechanical data
Figure 20. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, outline
$
-"
E
B
-#
,
,
%
E
B
,
,
0IN
%
%
+
+
,
,
!
$
$
EEE
!
:7?-%E
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering
process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 23.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.550
0.450
0.600
0.0217
0.0177
0.0236
A1
0.020
0.000
0.050
0.0008
0.0000
0.0020
b
0.250
0.200
0.300
0.0098
0.0079
0.0118
D
2.000
1.900
2.100
0.0787
0.0748
0.0827
D2 (rev MB)
1.600
1.500
1.700
0.0630
0.0591
0.0669
D2 (rev MC)
-
1.200
1.600
-
0.0472
0.0630
E
3.000
2.900
3.100
0.1181
0.1142
0.1220
E2 (rev MB)
0.200
0.100
0.300
0.0079
0.0039
0.0118
E2 (rev MC)
-
1.200
1.600
-
0.0472
0.0630
e
0.500
-
-
0.0197
-
-
K (rev MB)
-
0.800
-
-
0.0315
-
K (rev MC)
-
0.300
-
-
0.0118
-
L (rev MB)
0.450
0.400
0.500
0.0177
0.0157
0.0197
L (rev MC)
-
0.300
0.500
-
0.0118
0.0197
L1
-
-
0.150
-
-
0.0059
L3
-
0.300
-
-
0.0118
-
(2)
eee
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
Doc ID 6512 Rev 10
39/44
Part numbering
11
M950x0 M950x0-W M950x0-R
Part numbering
Table 24.
Ordering information scheme
Example:
M95040
–
W MN 6
T P /G
Device type
M95 = SPI serial access EEPROM
Device function
040 = 4 Kbit (512 x 8)
020 = 2 Kbit (256 x 8)
010 = 1 Kbit (128 x 8)
Operating voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB or MC = UFDFPN8 (MLP8) 2 × 3mm
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with high reliability certified flow(1).
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(2)
/G or /S = F6SP36%
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
2. Used only for device grade 3
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
40/44
Doc ID 6512 Rev 10
M950x0 M950x0-W M950x0-R
12
Revision history
Revision history
Table 25.
Document revision history
Date
Version
10-May-2000
2.2
s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte
Write Operation
16-Mar-2001
2.3
Human Body Model meets JEDEC std (Table 2). Minor adjustments to
Figs 7,9,10,11 & Tab 9. Wording changes, according to the standard
glossary
Illustrations and Package Mechanical data updated
19-Jul-2001
2.4
Temperature range ‘3’ added to the -W supply voltage range in DC and
AC characteristics
11-Oct-2001
3.0
Document reformatted using the new template
26-Feb-2002
3.1
Description of chip deselect after 8th clock pulse made more explicit
27-Sep-2002
3.2
Position of A8 in Read Instruction Sequence Figure corrected. Load
Capacitance CL changed
24-Oct-2002
3.3
Minimum values for tCHHL and tCHHH changed.
24-Feb-2003
3.4
Description of Read from Memory Array (READ) instruction corrected,
and clarified
28-May-2003
3.5
New products, identified by the process letter W, added
25-Jun-2003
3.6
Correction to current products, identified by the process letter K not L.
ICC changed in DC characteristics, and tCHHL, tCHHH substituted in AC
characteristics
Voltage range -S upgraded by removing it, and adding the -R voltage
range in its place
Temperature range 5 removed.
21-Nov-2003
4.0
Table of contents, and Pb-free options added. VIL(min) improved to -0.45V
02-Feb-2004
4.1
VIL(max) and tCLQV(max) changed
5.0
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices.
New 5V and 2.5V devices, with process letter W, promoted from
preliminary data to full data. Device Grade 3 clarified, with reference to
HRCF and automotive environments
6.0
Product List summary table added. Process identification letter “G”
information added. Order information for Tape and Reel changed to T.
AEC-Q100-002 compliance. Device Grade information clarified. tHHQX
corrected to tHHQV. Signal Description updated.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint
clarified
01-Mar-2004
05-Oct-2004
Changes
Doc ID 6512 Rev 10
41/44
Revision history
M950x0 M950x0-W M950x0-R
Table 25.
Document revision history
Date
06-Nov-2006
20-Mar-2008
42/44
Version
Changes
7
Document converted to new template, Table 5: Status register format
moved to below Section 6.3: Read Status Register (RDSR).
PDIP package removed. UFDFPN8 (MB) package added (see Figure 20
and Table 23) and SO8N package specifications updated (see Figure 18
and Table 21). Packages are ECOPACK® compliant.
Section 6.7: Cycling added. Section 2.8: Supply voltage (VCC) added and
information removed below Section 4: Operating features.
Figure 3: Bus master and memory devices on the SPI bus modified.
TLEAD parameter modified, Note 1 changed, and TA added to Table 7:
Absolute maximum ratings.
Characteristics of previous product identified by process letter K removed.
CL modified in Table 11: AC test measurement conditions. Note removed
below Table 13 and Table 13.
Information in Table 16 is no longer Preliminary data, ICC, ICC1 and VIL
modified. End timing line of tSHQZ moved in Figure 17.
tCHHL and tCHHH changed to tCLHL and tCLHH, respectively in Figure 16,
Table 18, Table 17, Table 18, Table 19 and Table 20.
Plating technology and Process updated in Table 24: Ordering information
scheme.
8
Section 2.8: Supply voltage (VCC) updated.
Section 3: Connecting to the SPI bus modified.
Section 6.6: Write to Memory Array (WRITE) modified.
Device grade 6 removed in the 4.5 to 5.5 V VCC range (seeTable 8).
Table 16: DC characteristics (M950x0-R, device grade 6) modified.
Table 18: AC characteristics (M950x0-W, device grade 6) modified:
frequency changed from 5 MHz to 10 MHz.
Table 20: AC characteristics (M950x0-R, device grade 6) modified:
frequency changed from 2 MHz to 5 MHz.
Section 10: Package mechanical data:
– Inches are calculated from millimeters and rounded to the third decimal
digit.
– UFDFPN8 package specifications modified.
Blank option removed below Plating technology in Table 24: Ordering
information scheme. Table 25, Table 26 and Table 27 added.
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M950x0 M950x0-W M950x0-R
Table 25.
Revision history
Document revision history
Date
24-Sep-2009
02-Feb-2012
Version
Changes
9
Section 2.8: Supply voltage (VCC) and Section 6.4: Write Status Register
(WRSR) updated.
Section 6.6: Write to Memory Array (WRITE) clarified.
IOL and IOH added to Table 7: Absolute maximum ratings.
VRES added to DC characteristics tables 13, 14, 15 and 16. tCLQV
modified in Figure 20: AC characteristics (M950x0-R, device grade 6).
Note added to Table 20: AC characteristics (M950x0-R, device grade 6).
Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial
output timing updated.
Note added below Figure 20: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch
dual flat package no lead 2 × 3mm, outline.
/W process option removed from Table 24: Ordering information scheme.
ECOPACK text updated. Small text changes.
10
Document renamed from “M95040 M95020 M95010” to “M950x0
M950x0-W M950x0-R”
Silhouette of UDFPN8 (MB or MC) on the cover page updated.
Section 6.3: Read Status Register (RDSR) updated.
Text modified in Section 6.3.1: WIP bit.
Table 7: Absolute maximum ratings updated.
Figure 20: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, outline modified.
Table 23: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, data updated.
Removed tables of available products from Section 11: Part numbering.
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M950x0 M950x0-W M950x0-R
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