M29W800DT M29W800DB 8-Mbit (1 Mbit x 8 or 512 Kbits x 16,... 3 V supply flash memory

M29W800DT M29W800DB 8-Mbit (1 Mbit x 8 or 512 Kbits x 16,... 3 V supply flash memory
M29W800DT
M29W800DB
8-Mbit (1 Mbit x 8 or 512 Kbits x 16, boot block)
3 V supply flash memory
Features
■
Supply voltage
– VCC = 2.7 V to 3.6 V for program, erase and
read
■
Access times: 45, 70, 90 ns
■
Programming time
– 10 µs per byte/word typical
■
19 memory blocks
– 1 boot block (top or bottom location)
– 2 parameter and 16 main blocks
■
Program/erase controller
– Embedded byte/word program algorithms
■
Erase suspend and resume modes
– Read and program another block during
erase suspend
■
Unlock bypass program command
– Faster production/batch programming
■
Temporary block unprotection mode
■
Common flash interface
– 64-bit security code
■
Low power consumption
– Standby and automatic standby
■
100,000 program/erase cycles per block
■
Electronic signature
– Manufacturer code: 0020h
– Top device code M29W800DT: 22D7h
– Bottom device code M29W800DB: 225Bh
March 2008
SO44 (M)
TSOP48 (N)
12 x 20 mm
FBGA
TFBGA48 (ZE)
6 x 8 mm
Rev 10
1/52
www.numonyx.com
1
Contents
M29W800DT, M29W800DB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
2/52
2.1
Address inputs (A0-A18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Data input/output or address input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . . 12
2.5
Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
Output enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Write enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8
Reset/block temporary unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9
Ready/busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10
Byte/word organization select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.11
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.12
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5
Automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.2
Block protection and blocks unprotection . . . . . . . . . . . . . . . . . . . . . . . 16
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M29W800DT, M29W800DB
5
Contents
4.6
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.10
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12
Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . 20
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Data polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3
Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4
Erase timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5
Alternative toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix B Common flash interface (CFI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10
C.1
Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
C.2
In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3/52
List of tables
M29W800DT, M29W800DB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
4/52
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 22
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write AC characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset/block temporary unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SO44 – 44 lead plastic small outline, 525 mils body width, package mechanical data . . . 35
TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data . . . . 36
TFBGA48 6 x 8 mm – 6 x 8 active ball array – 0.80 mm pitch, package mechanical data. 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Top boot block addresses, M29W800DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Bottom boot block addresses, M29W800DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . 46
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
M29W800DT, M29W800DB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block addresses (x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block addresses (x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Write AC waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write AC waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset/block temporary unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SO44 – 44 lead plastic small outline, 525 mils body width, package outline . . . . . . . . . . . 34
TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 36
TFBGA48 6 x 8 mm – 6 x 8 ball array – 0.80 mm pitch, bottom view package outline. . . . 37
Programmer equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
In-system equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
In-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5/52
Description
1
M29W800DT, M29W800DB
Description
The M29W800D is a 8-Mbit (1 Mbit x 8 or 512 Kbits x 16) non-volatile memory that can be
read, erased and reprogrammed. These operations can be performed using a single low
voltage (2.7 to 3.6 V) supply. On power-up the memory defaults to its read mode where it
can be read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental program or erase commands from modifying the memory. Program and
erase commands are written to the command interface of the memory. An on-chip
program/erase controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see Figure 5: Block addresses (x 8)
and Figure 6: Block addresses (x 16). The first or last 64 Kbytes have been divided into four
additional blocks. The 16-Kbyte boot block can be used for small initialization code to start
the microprocessor, the two 8-Kbyte parameter blocks can be used for parameter storage
and the remaining 32-Kbyte is a small main block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in SO44, TSOP48 (12 x 20 mm) and TFBGA48 6 x 8 mm (0.8 mm
pitch) packages. The memory is supplied with all the bits erased (set to ’1’).
Figure 1.
Logic diagram
VCC
19
15
A0-A18
DQ0-DQ14
DQ15A–1
W
E
M29W800DT
M29W800DB
G
RB
RP
BYTE
VSS
AI05470B
6/52
M29W800DT, M29W800DB
Table 1.
Description
Signal names
Signal
Description
Direction
A0-A18
Address inputs
Inputs
DQ0-DQ7
Data inputs/outputs
I/O
DQ8-DQ14
Data inputs/outputs
I/O
DQ15A–1
Data input/output or address input
I/O
E
Chip enable
Input
G
Output enable
Input
W
Write enable
Input
RP
Reset/block temporary unprotect
Input
RB
Ready/busy output (not available on SO44 package)
Output
BYTE
Byte/word organization select
Input
VCC
Supply voltage
–
VSS
Ground
–
NC
Not connected internally
–
Figure 2.
SO connections
RP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M29W800DT 34
12 M29W800DB 33
13
32
14
31
15
30
16
29
28
17
27
18
26
19
25
20
21
24
22
23
W
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
AI05462b
7/52
Description
M29W800DT, M29W800DB
Figure 3.
TSOP connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
12 M29W800DT 37
13 M29W800DB 36
24
25
AI05461
8/52
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
M29W800DT, M29W800DB
Figure 4.
Description
TFBGA connections (top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
NC
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
NC
NC
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI00656
9/52
Description
Figure 5.
M29W800DT, M29W800DB
Block addresses (x 8)
M29W800DT
Top boot block addresses (x 8)
M29W800DB
bottom boot block addresses (x 8)
FFFFFh
FFFFFh
16 Kbyte
64 Kbyte
FC000h
FBFFFh
F0000h
EFFFFh
8 Kbyte
64 Kbyte
FA000h
F9FFFh
E0000h
Total of 15
64 Kbyte blocks
8 Kbyte
F8000h
F7FFFh
32 Kbyte
F0000h
EFFFFh
1FFFFh
64 Kbyte
64 Kbyte
E0000h
10000h
0FFFFh
32 Kbyte
Total of 15
64 Kbyte blocks
1FFFFh
08000h
07FFFh
8 Kbyte
06000h
05FFFh
64 Kbyte
10000h
0FFFFh
8 Kbyte
04000h
03FFFh
64 Kbyte
00000h
16 Kbyte
00000h
AI05463
1. Also see Appendix A: Block address table, Table 20 and Table 21 for a full listing of the block addresses.
10/52
M29W800DT, M29W800DB
Figure 6.
Description
Block addresses (x 16)
M29W800DT
Top boot block addresses (x 16)
M29W800DB
Bottom boot block addresses (x 16)
7FFFFh
7FFFFh
8 Kword
32 Kword
7E000h
7DFFFh
78000h
77FFFh
4 Kword
32 Kword
7D000h
7CFFFh
70000h
Total of 15
32 Kword blocks
4 Kword
7C000h
7BFFFh
16 Kword
78000h
77FFFh
0FFFFh
32 Kword
32 Kword
70000h
08000h
07FFFh
16 Kword
Total of 15
32 Kword blocks
0FFFFh
04000h
03FFFh
4 Kword
03000h
02FFFh
32 Kword
08000h
07FFFh
4 Kword
02000h
01FFFh
32 Kword
00000h
8 Kword
00000h
AI05464
1. Also see Appendix A: Block address table, Table 20 and Table 21 for a full listing of the block addresses.
11/52
Signal descriptions
2
M29W800DT, M29W800DB
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A18)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the internal state machine.
2.2
Data inputs/outputs (DQ0-DQ7)
The data inputs/outputs output the data stored at the selected address during a bus read
operation. During bus write operations they represent the commands sent to the command
interface of the internal state machine.
2.3
Data inputs/outputs (DQ8-DQ14)
The data inputs/outputs output the data stored at the selected address during a bus read
operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are
high impedance. During bus write operations the command register does not use these bits.
When reading the status register these bits should be ignored.
2.4
Data input/output or address input (DQ15A-1)
When BYTE is High, VIH, this pin behaves as a data input/output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of
the word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text
consider references to the data input/output to include this pin when BYTE is High and
references to the address inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
2.5
Chip enable (E)
The chip enable, E, activates the memory, allowing bus read and bus write operations to be
performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output enable (G)
The output enable, G, controls the bus read operation of the memory.
12/52
M29W800DT, M29W800DB
2.7
Signal descriptions
Write enable (W)
The write enable, W, controls the bus write operation of the memory’s command interface.
2.8
Reset/block temporary unprotect (RP)
The reset/block temporary unprotect pin can be used to apply a hardware reset to the
memory or to temporarily unprotect all blocks that have been protected.
A hardware reset is achieved by holding reset/block temporary unprotect Low, VIL, for at
least tPLPX. After reset/block temporary unprotect goes High, VIH, the memory will be ready
for bus read and bus write operations after tPHEL or tRHEL, whichever occurs last. See the
Section 2.9: Ready/busy output (RB), Table 15: Reset/block temporary unprotect AC
characteristics and Figure 14: Reset/block temporary unprotect AC waveforms, for more
details.
Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program
and erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
2.9
Ready/busy output (RB)
The ready/busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations ready/busy is
Low, VOL. Ready/busy is high-impedance during read mode, auto select mode and erase
suspend mode.
After a hardware reset, bus read and bus write operations cannot begin until ready/busy
becomes high-impedance. See Table 15: Reset/block temporary unprotect AC
characteristics and Figure 14: Reset/block temporary unprotect AC waveforms.
The use of an open-drain output allows the ready/busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.10
Byte/word organization select (BYTE)
The byte/word organization select pin is used to switch between the 8-bit and 16-bit bus
modes of the memory. When byte/word organization select is Low, VIL, the memory is in 8bit mode, when it is High, VIH, the memory is in 16-bit mode.
2.11
VCC supply voltage
The VCC supply voltage supplies the power for all operations (read, program, erase etc.).
The command interface is disabled when the VCC supply voltage is less than the lockout
voltage, VLKO. This prevents bus write operations from accidentally damaging the data
during power-up, power-down and power surges. If the program/erase controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
13/52
Signal descriptions
M29W800DT, M29W800DB
A 0.1 µF capacitor should be connected between the VCC supply voltage pin and the VSS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, ICC3.
2.12
VSS ground
The VSS ground is the reference for all voltage measurements.
14/52
M29W800DT, M29W800DB
3
Bus operations
Bus operations
There are five standard bus operations that control the device. These are bus read, bus
write, output disable, standby and automatic standby. See Table 2 and Table 3, Bus
operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
3.1
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. A valid bus read operation involves setting the desired address on the address
inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The data inputs/outputs will output the value, see Figure 11: Read mode
AC waveforms, and Figure 12: Read AC characteristics for details of when the output
becomes valid.
3.2
Bus write
Bus write operations write to the command interface. A valid bus write operation begins by
setting the desired address on the address inputs. The address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole bus write operation. See Figure 12 and Figure 13, Write AC waveforms,
and Table 13 and Table 14, Write AC characteristics, for details of the timing requirements.
3.3
Output disable
The data inputs/outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the memory enters standby mode and the data
inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to
the standby supply current, ICC2, Chip Enable should be held within VCC ± 0.2 V. For the
standby current level see Table 11: DC characteristics.
During program or erase operations the memory will continue to use the program/erase
supply current, ICC3, for program or erase operations until the operation completes.
3.5
Automatic standby
If CMOS levels (VCC ± 0.2 V) are used to drive the bus and the bus is inactive for 150 ns or
more the memory enters automatic standby where the internal supply current is reduced to
the standby supply current, ICC2. The data inputs/outputs will still output data if a bus read
operation is in progress.
15/52
Bus operations
3.6
M29W800DT, M29W800DB
Special bus operations
Additional bus operations can be performed to read the electronic signature and also to
apply and remove block protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.6.1
Electronic signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2
and Table 3, Bus operations.
3.6.2
Block protection and blocks unprotection
Each block can be separately protected against accidental program or erase. Protected
blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment and the other for in-system use. Block protect and chip unprotect
operations are described in Appendix C: Block protection.
Table 2.
Bus operations, BYTE = VIL(1)
Operation
E
G
Address inputs
DQ15A–1, A0-A18
W
Data inputs/outputs
DQ14-DQ8
DQ7-DQ0
Bus read
VIL
VIL
VIH
Cell address
Hi-Z
Data output
Bus write
VIL
VIH
VIL
Command address
Hi-Z
Data input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read manufacturer code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 =
VID, others VIL or VIH
Hi-Z
20h
Read device code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 =
VID, others VIL or VIH
Hi-Z
D7h (M29W800DT)
5Bh (M29W800DB)
Output disable
1. X = VIL or VIH.
Table 3.
Bus operations, BYTE = VIH (1)
Operation
Address inputs
A0-A18
Data inputs/outputs
DQ15A–1, DQ14-DQ0
E
G
W
Bus read
VIL
VIL
VIH
Cell address
Bus write
VIL
VIH
VIL
Command address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read manufacturer code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
others VIL or VIH
0020h
Read device code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 = VID,
others VIL or VIH
22D7h (M29W800DT)
225Bh (M29W800DB)
Output disable
1. X = VIL or VIH.
16/52
Data output
Data input
M29W800DT, M29W800DB
4
Command interface
Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. Failure to observe a
valid sequence of bus write operations will result in the memory returning to read mode. The
long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being
used, for a summary of the commands.
4.1
Read/Reset command
The Read/Reset command returns the memory to its read mode where it behaves like a
ROM or EPROM, unless otherwise stated. It also resets the errors in the status register.
Either one or three bus write operations can be used to issue the Read/Reset command.
The Read/Reset command can be issued, between bus write cycles before the start of a
program or erase operation, to return the device to read mode. Once the program or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an erase operation when issued while in erase suspend.
4.2
Auto Select command
The Auto Select command is used to read the manufacturer code, the device code and the
block protection status. Three consecutive bus write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
auto select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset
commands are accepted in auto select mode, all other commands are ignored.
From the auto select mode the manufacturer code can be read using a bus read operation
with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The
manufacturer code for Numonyx is 0020h.
The device code can be read using a bus read operation with A0 = VIH and A1 = VIL. The
other address bits may be set to either VIL or VIH. The device code for the M29W800DT is
22D7h and for the M29W800DB is 225Bh.
The block protection status of each block can be read using a bus read operation with A0 =
VIL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits may
be set to either VIL or VIH. If the addressed block is protected then 01h is output on data
inputs/outputs DQ0-DQ7, otherwise 00h is output.
4.3
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four bus write operations, the final write operation latches
the address and data in the internal state machine and starts the program/erase controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The status register is never read and no error condition is given.
17/52
Command interface
M29W800DT, M29W800DB
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 6: Program, erase times and program, erase endurance cycles. Bus read operations
during the program operation will output the status register on the data inputs/outputs. See
the Section 5: Status register for more details.
After the program operation has completed the memory will return to the read mode, unless
an error has occurred. When an error occurs the memory will continue to output the status
register. A Read/Reset command must be issued to reset the error condition and return to
read mode.
Note that the Program command cannot change a bit set to ’0’ back to ’1’. One of the erase
commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.4
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the access time to the device is long (as with
some EPROM programmers) considerable time saving can be made by using these
commands. Three bus write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in read mode.
4.5
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at
a time. The command requires two bus write operations, the final write operation latches the
address and data in the internal state machine and starts the program/erase controller.
The program operation using the Unlock Bypass Program command behaves identically to
the program operation using the Program command. A protected block cannot be
programmed; the operation cannot be aborted and the status register is read. Errors must
be reset using the Read/Reset command, which leaves the device in unlock bypass mode.
See the Program command for details on the behavior.
4.6
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to read/reset mode from unlock
bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from unlock bypass mode.
18/52
M29W800DT, M29W800DB
4.7
Command interface
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six bus write operations are
required to issue the Chip Erase command and start the program/erase controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the chip erase operation appears to start but will terminate within
about 100 µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands. It is not possible to issue
any command to abort the operation. Typical chip erase times are given in Table 6: Program,
erase times and program, erase endurance cycles. All bus read operations during the chip
erase operation will output the status register on the data inputs/outputs. See the Section 5:
Status register for more details.
After the chip erase operation has completed the memory will return to the read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.8
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six bus write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth bus write operation using the address of the additional
block. The block erase operation starts the program/erase controller about 50 µs after the
last bus write operation. Once the program/erase controller starts it is not possible to select
any more blocks. Each additional block must therefore be selected within 50 µs of the last
block. The 50 µs timer restarts when an additional block is selected. The status register can
be read after the sixth bus write operation. See the status register for details on how to
identify if the program/erase controller has started the block erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the block erase operation appears to
start but will terminate within about 100 µs, leaving the data unchanged. No error condition
is given when protected blocks are ignored.
During the block erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 6: Program, erase times
and program, erase endurance cycles. All bus read operations during the block erase
operation will output the status register on the data inputs/outputs. See the Section 5: Status
register for more details.
After the block erase operation has completed the memory will return to the read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
The Block Erase command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
19/52
Command interface
4.9
M29W800DT, M29W800DB
Erase Suspend command
The Erase Suspend command may be used to temporarily suspend a block erase operation
and return the memory to read mode. The command requires one bus write operation.
The program/erase controller will suspend within the erase suspend latency time (refer to
Table 6 for value) of the Erase Suspend command being issued. Once the program/erase
controller has stopped the memory will be set to read mode and the erase will be
suspended. If the Erase Suspend command is issued during the period when the memory is
waiting for an additional block (before the program/erase controller starts) then the erase is
suspended immediately and will start immediately when the Erase Resume command is
issued. It is not possible to select any further blocks to erase after the erase resume.
During erase suspend it is possible to read and program cells in blocks that are not being
erased; both read and program operations behave as normal on these blocks. If any attempt
is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The status register is not read and
no error condition is given. Reading from blocks that are being erased will output the status
register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an erase suspend. The Read/Reset command must be issued to return the device to
read array mode before the Resume command will be accepted.
4.10
Erase Resume command
The Erase Resume command must be used to restart the program/erase controller from
erase suspend. An erase can be suspended and resumed more than once.
4.11
Read CFI Query command
The Read CFI Query command is used to read data from the common flash interface (CFI)
memory area. This command is valid when the device is in the read array mode, or when the
device is in auto select mode.
One bus write cycle is required to issue the Read CFI Query command. Once the command
is issued subsequent bus read operations read from the common flash interface memory
area.
The Read/Reset command must be issued to return the device to the previous mode (read
array mode or auto select mode). A second Read/Reset command would be needed if the
device is to be put in the read array mode from auto select mode.
See Appendix B: Common flash interface (CFI), Table 22, Table 23, Table 24, Table 25,
Table 26 and Table 27 for details on the information contained in the common flash interface
(CFI) memory area.
4.12
Block Protect and Chip Unprotect commands
Each block can be separately protected against accidental program or erase. The whole
chip can be unprotected to allow the data inside the blocks to be changed.
Block protect and chip unprotect operations are described in Appendix C: Block protection.
20/52
M29W800DT, M29W800DB
Table 4.
Command interface
Commands, 16-bit mode, BYTE = VIH(1)
Command
Length
Bus write operations
1st
2nd
3rd
4th
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
X
F0
3
555
AA
2AA
55
X
F0
Auto Select
3
555
AA
2AA
55
555
90
Program
4
555
AA
2AA
55
555
A0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
555
Erase Suspend
1
X
B0
Erase Resume
1
X
30
Read CFI Query
1
55
98
Read/Reset
PA
PD
80
555
AA
2AA
55
555
10
80
555
AA
2AA
55
BA
30
1. X don’t care, PA program address, PD program data, BA any address in the block.
All values in the table are in hexadecimal format.
The command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15
are don’t care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
21/52
Command interface
Table 5.
M29W800DT, M29W800DB
Commands, 8-bit mode, BYTE = VIL(1)
Length
Bus write operations
Command
1st
2nd
3rd
4th
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
X
F0
3
AAA
AA
555
55
X
F0
Auto Select
3
AAA
AA
555
55
AAA
90
Program
4
AAA
AA
555
55
AAA
A0
Unlock Bypass
3
AAA
AA
555
55
AAA
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
AAA
AA
555
55
AAA
Block Erase
6+
AAA
AA
555
55
AAA
Erase Suspend
1
X
B0
Erase Resume
1
X
30
Read CFI Query
1
AA
98
Read/Reset
PA
PD
80
AAA
AA
555
55
AAA
10
80
AAA
AA
555
55
BA
30
1. X don’t care, PA program address, PD program data, BA any address in the block.
All values in the table are in hexadecimal.
The command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15
are don’t care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Table 6.
Program, erase times and program, erase endurance cycles
Parameter
Min.
Chip erase
Block erase (64 Kbytes)
Erase suspend latency time
Typ. (1)(2)
Max.(2)
Unit
12
60(3)
s
0.8
6(4)
s
15
(3)
25
(3)
µs
µs
Program (byte or word)
10
200
Chip program (byte by byte)
12
60(3)
s
(4)
s
Chip program (word by word)
Program/erase cycles (per block)
6
30
100,000
cycles
20
years
Data retention
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC.
22/52
M29W800DT, M29W800DB
5
Status register
Status register
Bus read operations from any address always read the status register during program and
erase operations. It is also read during erase suspend when an address within a block being
erased is accessed.
The bits in the status register are summarized in Table 7: Status register bits.
5.1
Data polling bit (DQ7)
The data polling bit can be used to identify whether the program/erase controller has
successfully completed its operation or if it has responded to an erase suspend. The data
polling bit is output on DQ7 when the status register is read.
During program operations the data polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the program operation the memory
returns to read mode and bus read operations from the address just programmed output
DQ7, not its complement.
During erase operations the data polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the erase operation the memory returns to read
mode.
In erase suspend mode the data polling bit will output a ’1’ during a bus read operation
within a block being erased. The data polling bit will change from a ’0’ to a ’1’ when the
program/erase controller has suspended the erase operation.
Figure 7: Data polling flowchart gives an example of how to use the data polling bit. A valid
address is the address being programmed or an address within the block being erased.
5.2
Toggle bit (DQ6)
The toggle bit can be used to identify whether the program/erase controller has successfully
completed its operation or if it has responded to an erase suspend. The toggle bit is output
on DQ6 when the status register is read.
During program and erase operations the toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive bus read operations at any address. After successful completion of the operation
the memory returns to read mode.
During erase suspend mode the toggle bit will output when addressing a cell within a block
being erased. The toggle bit will stop toggling when the program/erase controller has
suspended the erase operation.
If any attempt is made to erase a protected block, the operation is aborted, no error is
signalled and DQ6 toggles for approximately 100 µs. If any attempt is made to program a
protected block or a suspended block, the operation is aborted, no error is signalled and
DQ6 toggles for approximately 1 µs.
Figure 8: Data toggle flowchart gives an example of how to use the toggle bit.
23/52
Status register
5.3
M29W800DT, M29W800DB
Error bit (DQ5)
The error bit can be used to identify errors detected by the program/erase controller. The
error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the
correct data to the memory. If the error bit is set a Read/Reset command must be issued
before other commands are issued. The error bit is output on DQ5 when the status register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One
of the erase commands must be used to set all the bits in a block or in the whole memory
from ’0’ to ’1’
5.4
Erase timer bit (DQ3)
The erase timer bit can be used to identify the start of program/erase controller operation
during a Block Erase command. Once the program/erase controller starts erasing the erase
timer bit is set to ’1’. Before the program/erase controller starts the erase timer bit is set to ’0’
and additional blocks to be erased may be written to the command interface. The erase
timer bit is output on DQ3 when the status register is read.
5.5
Alternative toggle bit (DQ2)
The alternative toggle bit can be used to monitor the program/erase controller during erase
operations. The alternative toggle bit is output on DQ2 when the status register is read.
During chip erase and block erase operations the toggle bit changes from ’0’ to ’1’ to ’0’,
etc., with successive bus read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to read mode.
During erase suspend the alternative toggle bit changes from ’0’ to ’1’ to ’0’, etc. with
successive bus read operations from addresses within the blocks being erased. Bus read
operations to addresses within blocks not being erased will output the memory cell data as if
in read mode.
After an erase operation that causes the error bit to be set the alternative toggle bit can be
used to identify which block or blocks have caused the error. The alternative toggle bit
changes from ’0’ to ’1’ to ’0’, etc. with successive bus read operations from addresses within
blocks that have not erased correctly. The alternative toggle bit does not change if the
addressed block has erased correctly.
24/52
M29W800DT, M29W800DB
Table 7.
Status register
Status register bits(1)
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any address
DQ7
Toggle
0
–
–
0
Program during erase
suspend
Any address
DQ7
Toggle
0
–
–
0
Program error
Any address
DQ7
Toggle
1
–
–
0
Chip erase
Any address
0
Toggle
0
1
Toggle
0
Block erase before
timeout
Erasing block
0
Toggle
0
0
Toggle
0
Non-erasing block
0
Toggle
0
0
No toggle
0
Erasing block
0
Toggle
0
1
Toggle
0
Non-erasing block
0
Toggle
0
1
No toggle
0
Erasing block
1
No toggle
0
–
Toggle
1
Block erase
Erase suspend
Non-erasing block
Data read as normal
1
Good block address
0
Toggle
1
1
No toggle
0
Faulty block address
0
Toggle
1
1
Toggle
0
Erase error
1. Unspecified data bits should be ignored.
Figure 7.
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI03598
25/52
Status register
Figure 8.
M29W800DT, M29W800DB
Data toggle flowchart
START
READ DQ6
READ
DQ5 & DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
TWICE
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI01370C
26/52
M29W800DT, M29W800DB
6
Maximum rating
Maximum rating
Stressing the device above the rating listed in the Table 8: Absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
operating sections of this specification is not implied. Refer also to the Numonyx SURE
program and other relevant quality documents.
Table 8.
Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature under bias
–50
125
°C
TSTG
Storage temperature
–65
150
°C
–0.6
VCC + 0.6
V
(1) (2)
VIO
Input or output voltage
VCC
Supply voltage
–0.6
4
V
VID
Identification voltage
–0.6
13.5
V
1. Minimum voltage may undershoot to –2 V during transition and for less than 20 ns during transitions.
2. Maximum voltage may overshoot to VCC + 2 V during transition and for less than 20 ns during transitions.
27/52
DC and AC parameters
7
M29W800DT, M29W800DB
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 9: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 9.
Operating and AC measurement conditions
M29W800D
Parameter
45 ns
70 ns
90 ns
Min
Max
Min
Max
Min
Max
VCC supply voltage
3.0
3.6
2.7
3.6
2.7
3.6
Ambient operating temperature (range 6)
–40
85
–40
85
–40
85
Ambient operating temperature (range 1)
0
70
0
70
0
70
Unit
V
°C
Load capacitance (CL)
30
Input rise and fall times
10
Input pulse voltages
Input and output timing ref. voltages
Figure 9.
30
100
10
10
ns
0 to VCC
0 to VCC
0 to VCC
V
VCC/2
VCC/2
VCC/2
V
AC measurement I/O waveform
VCC
VCC/2
0V
AI04498
28/52
pF
M29W800DT, M29W800DB
DC and AC parameters
Figure 10. AC measurement load circuit
VCC
VCC
25kΩ
DEVICE
UNDER
TEST
0.1µF
CL
CL includes JIG capacitance
Table 10.
Symbol
CIN
COUT
25kΩ
AI04499
Device capacitance(1)
Parameter
Input capacitance
Output capacitance
Test condition
Min
Max
Unit
VIN = 0 V
6
pF
VOUT = 0 V
12
pF
1. Sampled only, not 100% tested.
Table 11.
Symbol
DC characteristics
Parameter
Test condition
ILI
Input leakage current
ILO
Max
Unit
0 V ≤ VIN ≤ VCC
±1
µA
Output leakage current
0 V ≤ VOUT ≤ VCC
±1
µA
ICC1
Supply current (read)
E = VIL, G = VIH,
f = 6 MHz
10
mA
ICC2
Supply current (standby)
E = VCC ± 0.2 V,
RP = VCC ± 0.2 V
100
µA
Program/erase
controller active
20
mA
ICC3 (1)
Supply current (program/erase)
Min
VIL
Input low voltage
–0.5
0.8
V
VIH
Input high voltage
0.7VCC
VCC + 0.3
V
VOL
Output low voltage
IOL = 1.8 mA
0.45
V
VOH
Output high voltage
IOH = –100 µA
VID
Identification voltage
IID
Identification current
VLKO
Program/erase lockout supply
voltage
VCC – 0.4
11.5
A9 = VID
1.8
V
12.5
V
100
µA
2.3
V
1. Sampled only, not 100% tested.
29/52
DC and AC parameters
M29W800DT, M29W800DB
Figure 11. Read mode AC waveforms
tAVAV
A0-A18/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGHQZ
tGLQV
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
Table 12.
tBLQZ
AI05448
Read AC characteristics
M29W800D
Symbol
Alt
Parameter
Test condition
Unit
45 ns
70 ns
90 ns
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
45
70
90
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
45
70
90
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
45
70
90
ns
tOLZ
Output Enable Low to Output Transition
E = VIL
Min
0
0
0
ns
tGLQX
(1)
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
25
30
35
ns
tEHQZ
(1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
20
25
30
ns
tGHQZ
(1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
20
25
30
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or Address
Transition to Output Transition
Min
0
0
0
ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
5
5
5
ns
tBLQZ
tFLQZ
BYTE Low to Output Hi-Z
Max
25
25
30
ns
tBHQV
tFHQV BYTE High to Output Valid
Max
30
30
40
ns
1. Sampled only, not 100% tested.
30/52
M29W800DT, M29W800DB
DC and AC parameters
Figure 12. Write AC waveforms, write enable controlled
tAVAV
A0-A18/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
Table 13.
AI05449
Write AC characteristics, write enable controlled
M29W800D
Symbol
Alt
Parameter
Unit
45 ns
70 ns
90 ns
tAVAV
tWC
Address Valid to Next Address Valid
Min
45
70
90
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
30
45
50
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
25
45
50
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
40
45
50
ns
Output Enable High to Write Enable Low
Min
0
0
0
ns
tOEH
Write Enable High to Output Enable Low
Min
0
0
0
ns
tBUSY
Program/Erase Valid to RB Low
Max
30
30
35
ns
tVCS
VCC High to Chip Enable Low
Min
50
50
50
µs
tGHWL
tWHGL
tWHRL
(1)
tVCHEL
1. Sampled only, not 100% tested.
31/52
DC and AC parameters
M29W800DT, M29W800DB
Figure 13. Write AC waveforms, chip enable controlled
tAVAV
A0-A18/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
Table 14.
AI05450
Write AC characteristics, chip enable controlled
M29W800D
Symbol
Alt
Parameter
Unit
45 ns
70 ns
90 ns
tAVAV
tWC
Address Valid to Next Address Valid
Min
45
70
90
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
30
45
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
25
45
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
40
45
50
ns
Output Enable High Chip Enable Low
Min
0
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
0
ns
tEHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
35
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
50
µs
1. Sampled only, not 100% tested.
32/52
M29W800DT, M29W800DB
DC and AC parameters
Figure 14. Reset/block temporary unprotect AC waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI06870
Table 15.
Reset/block temporary unprotect AC characteristics
M29W800D
Symbol
Alt
Parameter
Unit
45 ns
70 ns
90 ns
tPHWL (1)
tPHEL
tPHGL (1)
tRH
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
50
50
50
ns
tRHWL (1)
tRHEL (1)
tRHGL (1)
tRB
RB High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
0
0
0
ns
tPLPX
tRP
RP pulse width
Min
500
500
500
ns
tPLYH (1)
tREADY
RP Low to read mode
Max
10
10
10
µs
RP rise time to VID
Min
500
500
500
ns
tPHPHH
(1)
tVIDR
1. Sampled only, not 100% tested.
33/52
Package mechanical data
8
M29W800DT, M29W800DB
Package mechanical data
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
Figure 15. SO44 – 44 lead plastic small outline, 525 mils body width, package outline
A
A2
C
b
e
CP
D
N
E
1
EH
A1
α
L
SO-d
1. Drawing is not to scale.
34/52
M29W800DT, M29W800DB
Table 16.
Package mechanical data
SO44 – 44 lead plastic small outline, 525 mils body width, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
2.80
A1
Max
0.110
0.10
0.004
A2
2.30
2.20
2.40
0.091
0.087
0.094
b
0.40
0.35
0.50
0.016
0.014
0.020
C
0.15
0.10
0.20
0.006
0.004
0.008
CP
0.08
0.003
D
28.20
28.00
28.40
1.110
1.102
1.118
E
13.30
13.20
13.50
0.524
0.520
0.531
EH
16.00
15.75
16.25
0.630
0.620
0.640
e
1.27
–
–
0.050
–
–
L
0.80
0.031
a
N
8°
44
8°
44
35/52
Package mechanical data
M29W800DT, M29W800DB
Figure 16. TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, package outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
α
A1
DIE
L
C
CP
TSOP-G
1. Drawing is not to scale.
Table 17.
TSOP48 – 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.20
Max
0.047
A1
0.10
0.05
0.15
0.004
0.002
0.006
A2
1.00
0.95
1.05
0.039
0.037
0.041
B
0.22
0.17
0.27
0.009
0.007
0.011
0.10
0.21
0.004
0.008
C
CP
0.08
0.003
D1
12.00
11.90
12.10
0.472
0.468
0.476
E
20.00
19.80
20.20
0.787
0.779
0.795
E1
18.40
18.30
18.50
0.724
0.720
0.728
e
0.50
–
–
0.020
–
–
L
0.60
0.50
0.70
0.024
0.020
0.028
L1
0.80
a
3°
0°
5°
36/52
0.031
0°
5°
3°
M29W800DT, M29W800DB
Package mechanical data
Figure 17. TFBGA48 6 x 8 mm – 6 x 8 ball array – 0.80 mm pitch, bottom view package outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z32
1. Drawing is not to scale.
Table 18.
TFBGA48 6 x 8 mm – 6 x 8 active ball array – 0.80 mm pitch, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.20
A1
0.047
0.26
A2
0.010
0.90
b
Max
0.35
0.45
0.035
0.014
0.018
D
6.00
5.90
6.10
0.236
0.232
0.240
D1
4.00
–
–
0.157
–
–
ddd
0.10
0.004
E
8.00
7.90
8.10
0.315
0.311
0.319
E1
5.60
–
–
0.220
–
–
e
0.80
–
–
0.031
–
–
FD
1.00
–
–
0.039
–
–
FE
1.20
–
–
0.047
–
–
SD
0.40
–
–
0.016
–
–
SE
0.40
–
–
0.016
–
–
37/52
Ordering information
9
M29W800DT, M29W800DB
Ordering information
Table 19.
Ordering information scheme
Example:
M29W800DB
90 N
6
T
Device type
M29
Operating voltage
W = VCC = 2.7 to 3.6 V
Device function
800D = 8-Mbit (x 8/x 16), boot block
Array matrix
T = top boot
B = bottom boot
Speed
45 = 45 ns
70 = 70 ns
90 = 90 ns
Package
M = SO44
N = TSOP48: 12 x 20 mm
ZE = TFBGA48: 6 x 8 mm, 0.80 mm pitch
Temperature range
6 = –40 to 85 °C
1 = 0 to 70 °C
Option
T = tape & reel packing
E = lead-free package, standard packing
F = lead-free package, tape & reel packing
Note:
38/52
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
M29W800DT, M29W800DB
Appendix A
Table 20.
Block address table
Block address table
Top boot block addresses, M29W800DT
#
Size (Kbytes)
Address range (x 8)
Address range (x 16)
18
16
FC000h-FFFFFh
7E000h-7FFFFh
17
8
FA000h-FBFFFh
7D000h-7DFFFh
16
8
F8000h-F9FFFh
7C000h-7CFFFh
15
32
F0000h-F7FFFh
78000h-7BFFFh
14
64
E0000h-EFFFFh
70000h-77FFFh
13
64
D0000h-DFFFFh
68000h-6FFFFh
12
64
C0000h-CFFFFh
60000h-67FFFh
11
64
B0000h-BFFFFh
58000h-5FFFFh
10
64
A0000h-AFFFFh
50000h-57FFFh
9
64
90000h-9FFFFh
48000h-4FFFFh
8
64
80000h-8FFFFh
40000h-47FFFh
7
64
70000h-7FFFFh
38000h-3FFFFh
6
64
60000h-6FFFFh
30000h-37FFFh
5
64
50000h-5FFFFh
28000h-2FFFFh
4
64
40000h-4FFFFh
20000h-27FFFh
3
64
30000h-3FFFFh
18000h-1FFFFh
2
64
20000h-2FFFFh
10000h-17FFFh
1
64
10000h-1FFFFh
08000h-0FFFFh
0
64
00000h-0FFFFh
00000h-07FFFh
39/52
Block address table
Table 21.
40/52
M29W800DT, M29W800DB
Bottom boot block addresses, M29W800DB
#
Size (Kbytes)
Address range (x 8)
Address range (x 16)
18
64
F0000h-FFFFFh
78000h-7FFFFh
17
64
E0000h-EFFFFh
70000h-77FFFh
16
64
D0000h-DFFFFh
68000h-6FFFFh
15
64
C0000h-CFFFFh
60000h-67FFFh
14
64
B0000h-BFFFFh
58000h-5FFFFh
13
64
A0000h-AFFFFh
50000h-57FFFh
12
64
90000h-9FFFFh
48000h-4FFFFh
11
64
80000h-8FFFFh
40000h-47FFFh
10
64
70000h-7FFFFh
38000h-3FFFFh
9
64
60000h-6FFFFh
30000h-37FFFh
8
64
50000h-5FFFFh
28000h-2FFFFh
7
64
40000h-4FFFFh
20000h-27FFFh
6
64
30000h-3FFFFh
18000h-1FFFFh
5
64
20000h-2FFFFh
10000h-17FFFh
4
64
10000h-1FFFFh
08000h-0FFFFh
3
32
08000h-0FFFFh
04000h-07FFFh
2
8
06000h-07FFFh
03000h-03FFFh
1
8
04000h-05FFFh
02000h-02FFFh
0
16
00000h-03FFFh
00000h-01FFFh
M29W800DT, M29W800DB
Appendix B
Common flash interface (CFI)
Common flash interface (CFI)
The common flash interface is a JEDEC approved, standardized data structure that can be
read from the flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query command is issued the device enters CFI query mode and the data
structure is read from the memory. Table 22, Table 23, Table 24, Table 25, Table 26 and
Table 27 show the addresses used to retrieve the data.
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Table 27: Security code area). This area can be accessed only in read mode
by the final user. It is impossible to change the security number after it has been written by
Numonyx. Issue a Read command to return to read mode.
Query structure overview (1)
Table 22.
Address
Sub-section name
Description
x 16
x8
10h
20h
CFI query identification string
Command set ID and algorithm data offset
1Bh
36h
System interface information
Device timing & voltage information
27h
4Eh
Device geometry definition
Flash device layout
40h
80h
Primary algorithm-specific extended
query table
Additional information specific to the
primary algorithm (optional)
61h
C2h
Security code area
64-bit unique device number
1. Query data are always presented on the lowest order data outputs.
41/52
Common flash interface (CFI)
M29W800DT, M29W800DB
CFI query identification string(1)
Table 23.
Address
Data
Description
Value
x 16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
Alternate vendor command set and control interface ID
code second vendor - specified algorithm supported
19h
32h
0000h
Address for alternate algorithm extended query table
1Ah
34h
0000h
‘Q’
Query unique ASCII string ‘QRY’
‘R’
‘Y’
Primary algorithm command set and control interface ID
code 16-bit ID code defining a specific algorithm
AMD
compatible
Address for primary algorithm extended query table (see
Table 26)
P = 40h
NA
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Table 24.
CFI query system interface information
Address
Data
Value
x8
1Bh
36h
0027h
VCC logic supply minimum program/erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
2.7 V
1Ch
38h
0036h
VCC logic supply maximum program/erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
3.6 V
1Dh
3Ah
0000h
VPP [programming] supply minimum program/erase voltage
NA
1Eh
3Ch
0000h
VPP [programming] supply maximum program/erase voltage
NA
1Fh
20h
21h
3Eh
40h
42h
0004h
0000h
000Ah
Typical timeout per single byte/word program =
2n
µs
16 µs
n
Typical timeout for minimum size write buffer program = 2 µs
Typical timeout per individual block erase =
2n
ms
1s
0000h
Typical timeout for full chip erase =
23h
46h
0004h
Maximum timeout for byte/word program = 2n times typical
25h
26h
4Ah
4Ch
0000h
0003h
0000h
1. Not supported in the CFI.
Maximum timeout for write buffer program =
2n
Maximum timeout per individual block erase =
Maximum timeout for chip erase =
2n
NA
(1)
44h
48h
ms
2n
22h
24h
42/52
Description
x 16
times typical
2n
times typical
times typical
(1)
256 µs
NA
8s
M29W800DT, M29W800DB
Table 25.
Common flash interface (CFI)
Device geometry definition
Address
Data
Description
Value
x 16
x8
27h
4Eh
0014h
Device size = 2n in number of bytes
1 Mbyte
28h
29h
50h
52h
0002h
0000h
Flash device interface code description
x 8, x 16
async.
2Ah
2Bh
54h
56h
0000h
0000h
Maximum number of bytes in multi-byte program or page =
2n
2Ch
58h
0004h
Number of erase block regions within the device.
It specifies the number of regions within the device
containing contiguous erase blocks of the same size.
4
2Dh
2Eh
5Ah
5Ch
0000h
0000h
Region 1 information
Number of identical size erase block = 0000h+1
1
2Fh
30h
5Eh
60h
0040h
0000h
Region 1 information
Block size in region 1 = 0040h * 256 bytes
31h
32h
62h
64h
0001h
0000h
Region 2 information
Number of identical size erase block = 0001h+1
33h
34h
66h
68h
0020h
0000h
Region 2 information
Block size in region 2 = 0020h * 256 bytes
35h
36h
6Ah
6Ch
0000h
0000h
Region 3 information
Number of identical size erase block = 0000h+1
37h
38h
6Eh
70h
0080h
0000h
Region 3 information
Block size in region 3 = 0080h * 256 byte
39h
3Ah
72h
74h
000Eh
0000h
Region 4 information
Number of identical-size erase block = 000Eh+1
3Bh
3Ch
76h
78h
0000h
0001h
Region 4 information
Block size in region 4 = 0100h * 256 byte
NA
16-Kbyte
2
8-Kbyte
1
32-Kbyte
15
64-Kbyte
43/52
Common flash interface (CFI)
Table 26.
M29W800DT, M29W800DB
Primary algorithm-specific extended query table
Address
Data
x 16
x8
40h
80h
Description
0050h
‘P’
Primary algorithm extended query table unique ASCII string
‘PRI’
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
‘1’
44h
88h
0030h
Minor version number, ASCII
‘0’
‘R’
Yes
‘I’
45h
8Ah
0000h
Address sensitive unlock (bits 1 to 0)
00 = required, 01= not required
silicon revision number (bits 7 to 2)
46h
8Ch
0002h
Erase suspend
00 = not supported, 01 = read only, 02 = read and write
2
47h
8Eh
0001h
Block protection
00 = not supported, x = number of sectors in per group
1
48h
90h
0001h
Temporary block unprotect
00 = not supported, 01 = supported
49h
92h
0004h
Block protect /unprotect
04 = M29W800D
4Ah
94h
0000h
Simultaneous operations, 00 = not supported
No
4Bh
96h
0000h
Burst mode, 00 = not supported, 01 = supported
No
4Ch
98h
0000h
Page mode, 00 = not supported, 01 = 4 page word, 02 = 8
page word
No
Table 27.
Security code area
Data
x 16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Yes
4
Address
Description
64-bit: unique device number
44/52
Value
M29W800DT, M29W800DB
Appendix C
Block protection
Block protection
Block protection can be used to prevent any operation from modifying the data stored in the
Flash. Each block can be protected individually. Once protected, program and erase
operations on the block fail to change the data.
There are three techniques that can be used to control block protection, these are the
programmer technique, the in-system technique and temporary unprotection. Temporary
unprotection is controlled by the reset/block temporary unprotection pin, RP; this is
described in the Section 2: Signal descriptions.
Unlike the command interface of the program/erase controller, the techniques for protecting
and unprotecting blocks change between different Flash memory suppliers. For example,
the techniques for AMD parts will not work on Numonyx parts. Care should be taken when
changing drivers for one part to work on another.
C.1
Programmer technique
The programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in programming equipment.
To protect a block follow the flowchart in Figure 18: Programmer equipment block protect
flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all
blocks can be unprotected at the same time. To unprotect the chip follow Figure 19:
Programmer equipment chip unprotect flowchart. Table 28: Programmer technique bus
operations, BYTE = VIH or VIL, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
C.2
In-system technique
The in-system technique requires a high voltage level on the reset/blocks temporary
unprotect pin, RP. This can be achieved without violating the maximum ratings of the
components on the microprocessor bus, therefore this technique is suitable for use after the
Flash has been fitted to the system.
To protect a block follow the flowchart in Figure 20: In-system equipment block protect
flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all
the blocks can be unprotected at the same time. To unprotect the chip follow Figure 21: Insystem equipment chip unprotect flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.
45/52
Block protection
Table 28.
M29W800DT, M29W800DB
Programmer technique bus operations, BYTE = VIH or VIL
E
G
W
Address inputs
A0-A18
Data inputs/outputs
DQ15A–1, DQ14-DQ0
Block protect
VIL
VID
VIL pulse
A9 = VID, A12-A18 block address
others = X
X
Chip unprotect
VID
VID
VIL pulse
A9 = VID, A12 = VIH, A15 = VIH
others = X
X
Block protection
verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
A12-A18 block address
others = X
Pass = XX01h
Retry = XX00h
Block unprotection
verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIH,
A9 = VID, A12-A18 block address
others = X
Retry = XX01h
Pass = XX00h
Operation
46/52
M29W800DT, M29W800DB
Block protection
Figure 18. Programmer equipment block protect flowchart
START
Set-up
ADDRESS = BLOCK ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Protect
Wait 4µs
W = VIL
Wait 100µs
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA
NO
=
01h
YES
A9 = VIH
E, G = VIH
++n
= 25
NO
End
YES
PASS
A9 = VIH
E, G = VIH
FAIL
AI03469
47/52
Block protection
M29W800DT, M29W800DB
Figure 19. Programmer equipment chip unprotect flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Unprotect
Wait 4µs
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1, A6 = VIH
E = VIL
Wait 4µs
G = VIL
INCREMENT
CURRENT BLOCK
Verify
Wait 60ns
Read DATA
NO
End
NO
48/52
++n
= 1000
DATA
=
00h
YES
LAST
BLOCK
YES
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
FAIL
PASS
NO
AI03470
M29W800DT, M29W800DB
Block protection
Figure 20. In-system equipment block protect flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 100µs
Verify
WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 4µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
DATA
NO
=
01h
YES
End
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI03471
49/52
Block protection
M29W800DT, M29W800DB
Figure 21. In-system equipment chip unprotect flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
NO
End
NO
++n
= 1000
YES
DATA
=
00h
INCREMENT
CURRENT BLOCK
YES
LAST
BLOCK
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI03472
50/52
M29W800DT, M29W800DB
10
Revision history
Revision history
Table 29.
Document revision history
Date
Version
August 2001
1.0
First issue
03-Dec-2001
2.0
Block protection appendix added, SO44 drawing and package
mechanical data updated, CFI Table 26, address 39h/72h data clarified,
read/reset operation during erase suspend clarified
01-Mar-2002
3.0
Description of Ready/Busy signal clarified (and Figure 14 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query
command section
11-Apr-2002
4.0
Temperature range 1 added
Document promoted from preliminary data to full datasheet
4.1
Erase suspend latency time (typical and maximum) and data retention
parameters added to Table 6: Program, erase times and program, erase
endurance cycles, and typical after 100k W/E cycles column removed.
Minimum voltage corrected for 70 ns speed class in Table 9: Operating
and AC measurement conditions.
Logic diagram and data toggle flowchart corrected.
Lead-free package options E and F added to Table 19: Ordering
information scheme.
31-Mar-2003
Changes
13-Feb-2004
5
TSOP48 package outline and mechanical data updated.
TFBGA48 6 x 8 mm – 6 x 8 active ball array – 0.80 mm pitch added.
Table 9: Operating and AC measurement conditions updated for 70 ns
speed option.
23-Apr-2004
6
Figure 2: SO connections updated.
16-Sep-2004
7
45 ns speed class added.
21-Mar-2006
8
Removed TFBGA48 (ZA) (6 x 9 mm) package. Converted to new ST
corporate template.
10-Dec-2007
9
Applied Numonyx branding.
25-Mar-2008
10
Minor text changes.
51/52
M29W800DT, M29W800DB
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applications.
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