Integrated Power Management Unit Top Specification TPS65910 TPS659104, FEATURES

Integrated Power Management Unit Top Specification TPS65910 TPS659104, FEATURES

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TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Integrated Power Management Unit Top Specification

Check for

Samples: TPS65910 , TPS659101 , TPS659102 , TPS659103 , TPS659104 , TPS659105 , TPS659106 , TPS659107 , TPS659108 , TPS659109

1

FEATURES

The purpose of the TPS65910 device is to provide the following resources:

Embedded power controller

Two efficient step-down dc-dc converters for processor cores

One efficient step-down dc-dc converter for I/O power

One efficient step-up 5-V dc-dc converter

SmartReflex

compliant dynamic voltage management for processor cores

8 LDO voltage regulators and one RTC LDO

(internal purpose)

One high-speed I

2

C interface for general-purpose control commands (CTL-I

2

C)

One high-speed I

2

C interface for SmartReflex

Class 3 control and command (SR-I

2

C)

Two enable signals multiplexed with SR-I

2

C, configurable to control any supply state and processor cores supply voltage

Thermal shutdown protection and hot-die detection

A real-time clock (RTC) resource with:

Oscillator for 32.768-kHz crystal or 32-kHz built-in RC oscillator

Date, time and calendar

Alarm capability

One configurable GPIO

DC-DC switching synchronization through internal or external 3-MHz clock

DESCRIPTION

The TPS65910 is an integrated power-management

IC available in 48-QFN package and dedicated to applications powered by one Li-Ion or Li-Ion polymer battery cell or 3-series Ni-MH cells, or by a 5-V input; it requires multiple power rails. The device provides three step-down converters, one step-up converter, and eight LDOs and is designed to support the specific power requirements of OMAP-based applications.

Two of the step-down converters provide power for dual processor cores and are controllable by a dedicated class-3 SmartReflex interface for optimum power savings. The third converter provides power for the I/Os and memory in the system.

The device includes eight general-purpose LDOs providing a wide range of voltage and current capabilities; they are fully controllable by the I

2

C interface. The use of the LDOs is flexible; they are intended to be used as follows: Two LDOs are designated to power the PLL and video DAC supply rails on the OMAP based processors, four general-purpose auxiliary LDOs are available to provide power to other devices in the system, and two LDOs are provided to power DDR memory supplies in applications requiring these memories.

In addition to the power resources, the device contains an embedded power controller (EPC) to manage the power sequencing requirements of the

OMAP systems and an (RTC).

Figure 1

shows the top-level diagram of the device.

APPLICATIONS

Portable and handheld systems

OMAP3 power management

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2010 – 2011, Texas Instruments Incorporated

2

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

C

BB

VBAT

VCC7

Ci

(VCC7)

Co

(VRTC)

VRTC

OSC32KIN

OSC32KOUT

CLK32KOUT

SDA_SDI

SCL_SCK

GPIO_CKSYNC

VRTC (LDO) and POR

Backup management

GNDA GNDA

VDDIO

2

I C

OSC

32-kHz

REFGND

Real-time clock

Bus control

SDASR_EN2

SCLSR_EN1

INT1

SLEEP

PWRON

BOOT1

BOOT0

PWRHOLD

NRESPWRON

Co

(VREF)

VREF

TESTV

REFGND

VDAC

Co

(VDAC)

VBAT

VCC5

Ci

(VCC5)

Co

(VPLL)

VPLL

VAUX1

Co

(VAUX1)

VBAT

VCC4

Ci

(VCC4)

VAUX2

Co

(VAUX2)

2

I C

VCC 7

Analog references and comparators

VDAC

(LDO)

AGND

VPLL

(LDO)

AGND

VAUX1

(LDO)

Power control statemachine

Test interface

DGND

VBAT

VAUX33 VCC7

VDDIO

Ci

(VDD3)

SW3

GND3

VDD3

(SMPS)

AGND

VCC7

VFB3

VDD1

(SMPS)

VCC1

SW1

GND1

Co

(VDD1)

VFB1

VCC4

AGND

Co

(VDD3)

VBAT

Ci

(VCC1)

VBAT

VDD2

(SMPS)

VCC7

AGND

VCC2

SW2

GND2

Co

(VDD2)

VFB2

Ci

(VCC2)

VBAT

VIO

(SMPS)

VCCIO

SWIO

GNDIO

Co

(VIO)

VFBIO

Ci

(VCCIO)

AGND2

VCC7

VDIG1

(LDO) VDIG1

Co

(VDIG1)

AGND2

VCC7

VCC6

VDIG2

Co

(VDIG2)

VDIG2

(LDO)

AGND2

VAUX33

(LDO)

AGND2

AGND2

VAUX2

(LDO)

AGND2

DGND AGND AGND2 GND3

VMMC

(LDO)

AGND2

GNDP: Power pad ground

Figure 1. 48-QFN Top-Level Diagram

VAUX33

Co

(VAUX33)

VBAT

VCC3

Ci

(VCC4)

VMMC

Co

(VMMC)

SWCS046-001

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Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

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Table 1. SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS

Compatible Processor

(1)

TI processors: AM1705/07, AM1806/08, AM3505/17, AM3703/15, DM3730/25,

OMAP-L137/38, OMAP3503/15/25/30, TMS320C6742/6/8

Samsung - S5PV210, S5PC110

Reserved

Samsung - S5PC100

Samsung - S5P6440

TI processors - DM643x, DM644x

Reserved

Freescale - i.MX27, Freescale - i.MX35

Freescale - i.MX508

Freescale - i.MX51

Part Number

(1)

TPS65910A1RSL

TPS659101A1RSL

TPS659102A1RSL

TPS659103A1RSL

TPS659104A1RSL

TPS659105A1RSL

TPS659106A1RSL

TPS659107A1RSL

TPS659108A1RSL

TPS659109A1RSL

(1) The RSL package is available in tape and reel. See for details for corresponding part numbers, quantities and ordering information.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Stresses beyond those listed under below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated below are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

The absolute maximum ratings for the TPS65910 device are listed below:

PARAMETER MIN MAX UNIT

Voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4,

VCC5, VCC6, VCC7

Voltage range on pins/balls VDDIO

Voltage range on pins/balls OSC32KIN, OSC32KOUT, BOOT1,

BOOT0

Voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2,

SCLSR_EN1, SLEEP, INT1, CLK32KOUT, NRESPWRON

Voltage range on pins/balls PWRON

Voltage range on pins/balls PWRHOLD

(1)

GPIO_CKSYNC

(2)

Functional junction temperature range

Peak output current on all other terminals than power resources

– 0.3

– 0.3

– 0.3

– 0.3

– 0.3

– 0.3

– 45

– 5

7

3.6

VRTC

MAX

+ 0.3

VDDIO

MAX

+ 0.3

7

7

150

5

V

V

V

V

V

V

° C mA

(1) I/O supplied from VDDIO but which can be driven from to a VBAT voltage level

(2) I/O supplied from VRTC but can be driven to a VBAT voltage level

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

Package

RSL 48-QFN

R

θ

ja

(

°

C/W)

37

DERATING

TA

<

25

°

C Power FACTOR ABOVE TA = 70

°

C Power TA = 85

°

C Power

Rating (W) 25

°

C

(mW/

°

C)

(W) Rating (W)

2.6

37 1.48

1

The thermal resistance R

θ JP junction-to-power PAD of the RSL package is 1.1

° C/W

The value of thermal resistance R

θ JA junction-to-ambient was measured on a high K.

Copyright © 2010 – 2011, Texas Instruments Incorporated

3

4

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

Lists of the recommended operating maximum ratings for the TPS65910 device are given below.

Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that

VCC2 and VCC4 can be higher than VCC7.

Note2: VCC2 and VCC4 must be connected together (to the same voltage).

Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.

MIN NOM MAX UNIT PARAMETER TEST CONDITIONS

V

CC

: Input voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5,

VCC7

V

CCP

: Input voltage range on pins/balls VCC6

Input voltage range on pins/balls VDDIO

Input voltage range on pins/balls PWRON

Input voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1,

SLEEP

Input voltage range on pins/balls PWRHOLD, GPIO_CKSYNC

Input voltage range on balls BOOT1, BOOT0, OSC32KIN

Operating free-air temperature, T

A

Junction temperature T

J

Storage temperature range

Lead temperature (soldering, 10 s)

VREF filtering capacitor C

O(VREF)

Power References

Connected from VREF to REFGND

VDD1 SMPS

Input capacitor C

I(VCC1)

Filter capacitor C

O(VDD1)

C

O filter capacitor ESR

Inductor L

O(VDD1)

L

O inductor dc resistor DCR

L

X5R or X7R dielectric

X5R or X7R dielectric f = 3 MHz

VDD2 SMPS

Input capacitor C

I(VCC2)

Filter capacitor C

O(VDD2)

C

O filter capacitor ESR

Inductor L

O(VDD2)

L

O inductor dc resistor DCR

L

X5R or X7R dielectric

X5R or X7R dielectric f = 3 MHz

VIO SMPS

Input capacitor C

I(VIO)

Filter capacitor C

O(VIO)

C

O filter capacitor ESR

Inductor L

O(VIO)

L

O inductor dc resistor DCR

L

X5R or X7R dielectric

X5R or X7R dielectric f = 3 MHz

VDIG1 LDO

Input capacitor C

I(VCC6)

Filtering capacitor C

O(VDIG1)

C

O filtering capacitor ESR

X5R or X7R dielectric

VDIG2 LDO

Filtering capacitor C

O(VDIG2)

C

O filtering capacitor ESR

VPLL LDO

Input capacitor C

I(VCC5)

Filtering capacitor C

O(VPLL)

X5R or X7R dielectric

2.7

1.7

1.65

0

1.65

1.65

1.65

– 40

– 40

– 65

4

4

4

0.8

0

0.8

0

0.8

3.6

3.6

1.8/3.3

3.6

VDDIO

VDDIO

VRTC

27

27

27

260

100

10

10

10

2.2

10

10

10

2.2

10

10

10

2.2

4.7

2.2

2.2

4.7

2.2

5.5

5.5

3.45

5.5

3.45

5.5

1.95

85

125

150

12

300

125

12

300

125

12

300

125

2.64

500

2.64

500

2.64

V

µ F

µ F m Ω

µ H m Ω

µ F

µ F m Ω

µ H m Ω

µ F

µ F m Ω

µ H m Ω

µ F

µ F m Ω

V

V

V

V nF

µ F m Ω

µ F

µ F

° C

° C

° C

V

V

° C

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

Lists of the recommended operating maximum ratings for the TPS65910 device are given below.

Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that

VCC2 and VCC4 can be higher than VCC7.

Note2: VCC2 and VCC4 must be connected together (to the same voltage).

Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.

MAX

500

UNIT

m Ω

PARAMETER

C

O filtering capacitor ESR

TEST CONDITIONS MIN

0

NOM

VDAC LDO

Filtering capacitor C

O(VDAC)

C

O filtering capacitor ESR

0.8

0

2.2

VMMC LDO

Input capacitor C

I(VCC4)

Filtering capacitor C

O(VMMC)

C

O filtering capacitor ESR

X5R or X7R dielectric

0.8

0

4.7

2.2

VAUX33 LDO

Filtering capacitor C

O(VAUX33)

C

O filtering capacitor ESR

0.8

0

2.2

VAUX1 LDO

Input capacitor C

I(VCC3)

Filtering capacitor C

O(VAUX1)

C

O filtering capacitor ESR

X5R or X7R dielectric

0.8

0

4.7

2.2

VAUX2 LDO

Filtering capacitor C

O(VAUX2)

C

O filtering capacitor ESR

0.8

0

2.2

VRTC LDO

Input capacitor C

I(VCC7)

Filtering capacitor C

O(VRTC)

C

O filtering capacitor ESR

X5R or X7R dielectric

0.8

0

4.7

2.2

VDD3 SMPS

Input capacitor C

I(VDD3)

Filter capacitor C

O(VDD3)

C

O filter capacitor ESR

Inductor L

O(VDD3)

L

O inductor DC resistor DCR

L

X5R or X7R dielectric

X5R or X7R dielectric f = 1 MHz

4

2.8

Backup battery capacitor C

Series resistors

BB

Backup Battery

Battery or superCap supplying VBACKUP

Capacitor supplying VBACKUP

5 to 15 mF

100 to 2000 mF

I

2

C Interfaces

5

1

10

5

10

SDA_SDI, SCL_SCK, SDASR_EN2,

SCLSR_EN1 external pull-up resistor

Connected to VDDIO

Crystal Oscillator (connected from OSC32KIN to OSC32KOUT)

Crystal frequency

Crystal tolerance

@ specified load cap value

@ 27 ° C – 20

1.2

32.768

0

Frequency Temperature coefficient.

Oscillator contribution (not including crystal variation)

0.5

Secondary temperature coefficient

Voltage coefficient

– 0.04

– 2

– 0.035

4.7

10

10

4.7

50

2.64

500

2.64

500

2.64

500

2.64

500

2.64

500

2.64

500

12

300

6.6

500

2000

40

1500

15

20

0.5

– 0.03

2

µ F m Ω

µ F

µ F m Ω

µ F m Ω

µ F

µ F m Ω

µ F m Ω

µ F

µ F m Ω

µ F m Ω

µ H m Ω mF

µ F

Ω k Ω kHz ppm ppm/

°

C ppm/ ° C

2 ppm/V

Copyright © 2010 – 2011, Texas Instruments Incorporated

5

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

Lists of the recommended operating maximum ratings for the TPS65910 device are given below.

Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that

VCC2 and VCC4 can be higher than VCC7.

Note2: VCC2 and VCC4 must be connected together (to the same voltage).

Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.

MIN NOM PARAMETER

Max crystal series resistor

Crystal load capacitor

Load crystal oscillator

Coscin ,Coscout

Quality factor

TEST CONDITIONS

@ Fundamental frequency

According to crystal data sheet parallel mode Including parasitic PCB capacitor

6

12

8000

MAX

90

12.5

25

80000

UNIT

k Ω pF pF

ESD SPECIFICATIONS

over operating free-air temperature range (unless otherwise noted)

ESD METHOD STANDARD REFERENCE

Human body model (HBM)

Charge device model (CDM)

EIA/JESD22-A114D

EIA/JESD22-C101C

PERFORMANCE

2000 V

500 V

TI STANDARD

REQUIREMENTS

2000 V

500 V

6

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

I/O PULLUP AND PULLDOWN CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER TEST CONDITIONS

SDA_SDI, SCL_SCK, SDASR_EN2,

SCLSR_EN1 Programmable pullup (DFT, default Grounded, VDDIO = 1.8 V inactive)

SLEEP programmable pulldown (default active) @ 1.8 V, VRTC = 1.8 V

@ 1.8 V, VRTC = 1.8 V, VCC7 = 2.7

V

PWRHOLD programmable pulldown (default active)

@ 5.5 V, VRTC = 1.8 V, VCC7 = 5.5

V

BOOT0, BOOT1 programmable pulldown (default active)

NRESPWRON pulldown

32KCLKOUT pulldown (disabled in Active-sleep state)

PWRON programmable pullup (default active)

GPIO_CKSYNC programmable pullup (default active)

@ 1.8 V, VRTC = 1.8 V

@ 1.8 V, VCC7 = 5.5 V, OFF state

@ 1.8 V, VRTC = 1.8 V, OFF state

Grounded, VCC7 = 5.5 V

Grounded, VRTC = 1.8 V

MIN

– 45%

2

2

7

2

2

2

– 40

27

TYP

8

4.5

4.5

14

4.5

4.5

4.5

– 31

18

MAX

+45%

10

10

30

10

10

10

– 15

9

UNIT

k Ω

µ A

µ A

µ A

µ A

µ A

µ A

µ

A

(1) The internal pullups on the CTL-I

2

C and SR-I

2

C balls are used for test purposes or when the SR-I pullups to the VIO supply must be mounted on the board in order to use the I

2

2

C interface is not used. Discrete

C interfaces. The internal I

2

C pullups must not be used for functional applications

Copyright © 2010 – 2011, Texas Instruments Incorporated

7

8

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

DIGITAL I/O VOLTAGE ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN TYP

Related I/O: PWRON

Low-level input voltage V

IL

High-level input voltage V

IH

0.7 x VCC7

Related I/Os: PWRHOLD, GPIO_CKSYNC

Low-level input voltage V

IL

High-level input voltage V

IH

1.3

VDDIO/V

CC7

Related I/Os: BOOT0, BOOT1, OSC32KIN

Low-level input voltage V

IL

High-level input voltage V

IH

0.65 x VRTC

Related I/Os: SLEEP

Low-level input voltage V

IL

High-level input voltage V

IH

Low-level output voltage V

High-level output voltage V

OL

OH

0.65 x VDDIO

Related I/Os: NRESPWRON, INT1, 32KCLKOUT

I

OL

= 100 µ A

I

OL

= 2 mA

I

OH

= 100 µ A VDDIO – 0.2

I

OH

= 2 mA VDDIO

Related Open-Drain I/Os: GPIO0

– 0.45

Low-level output voltage V

Low-level input voltage V

IL

High-level input voltage V

IH

Hysteresis

OL

I

OL

= 100 µ A

I

OL

= 2 mA

I

2

C-Specific Related I/Os: SCL, SDA, SCLSR_EN1, SDASR_EN2

– 0.5

0.7 x VDDIO

0.1 x VDDIO

Low-level output voltage V

OL

@ 3mA (sink current), VDDIO = 1.8 V

Low-level output voltage V

OL

@ 3mA (sink current), VDDIO = 3.3 V

MAX

0.3 x VCC7

0.45

VCC7

0.35 x VRTC

0.35 x VDDIO

0.2

0.45

0.2

0.45

0.3 x VDDIO

0.2

× VDDIO

0.4 x VDDIO

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UNIT

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

I

2

C INTERFACE AND CONTROL SIGNALS

I3

I4

I7

I8

I9

I3

I4

I7

I8

I9

I3

I4

I7

I8

I9 over operating free-air temperature range (unless otherwise noted)

I1

I2

I1

I2

I1

I2

NO.

PARAMETER

t su(SDA-SCLH) t h(SCLL-SDA) t su(SCLH-SDAL) t h(SDAL-SCLL) t su(SDAH-SCLH) t su(SDA-SCLH) t h(SCLL-SDA) t su(SCLH-SDAL) t h(SDAL-SCLL) t su(SDAH-SCLH) t su(SDA-SCLH) t h(SCLL-SDA) t su(SCLH-SDAL) t h(SDAL-SCLL) t su(SDAH-SCLH) t w(SCLL) t w(SCLH) t w(SCLL) t w(SCLH) t w(SCLL) t w(SCLH)

TEST CONDITIONS

INT1 rise and fall times, C

L

= 5 to 35 pF

NRESPWRON rise and fall times, C

L

= 5 to 35 pF

SLAVE HIGH

SPEED MODE

SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall time, C

L

= 10 to 100 pF

Data rate

Setup time, SDA valid to SCL high

Hold time, SDA valid from SCL low

Setup time, SCL high to SDA low

Hold time, SCL low from SDA low

Setup time, SDA high to SCL high

SLAVE FAST MODE

SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall time, C

L

= 10 to 400 pF

Data rate

Setup time, SDA valid to SCL high

Hold time, SDA valid from SCL low

Setup time, SCL high to SDA low

Hold time, SCL low from SDA low

Setup time, SDA high to SCL high

SLAVE STANDARD MODE

SCL/SCLSR_EN1 and SDA/SDASR_EN2 rise and fall time, C

L

= 10 to 400 pF

Data rate

Setup time, SDA valid to SCL high

Hold time, SDA valid from SCL low

Setup time, SCL high to SDA low

Hold time, SCL low from SDA low

Setup time, SDA high to SCL high

SWITCHING CHARACTERISTICS

SLAVE HIGH

SPEED MODE

Pulse duration, SCL low

Pulse duration, SCL high

SLAVE FAST MODE

Pulse duration, SCL low

Pulse duration, SCL high

SLAVE STANDARD MODE

Pulse duration, SCL low

Pulse duration, SCL high

MIN

5

5

10

10

0

160

160

160

20 +

0.1

× C

L

100

0

0.6

0.6

0.6

250

0

4.7

4

4

160

60

1.3

0.6

4.7

4

TYP

10

10

80

3.4

70

250

400

0.9

250

100

MAX

ns ns ns

Kbps ns

µ s

µ s

µ s

µ s

Mbps ns ns ns ns ns ns

Kbps ns

µ s

µ s

µ s

µ s ns ns ns

µ s

µ s

µ s

µ s

Copyright © 2010 – 2011, Texas Instruments Incorporated

9

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

POWER CONSUMPTION

over operating free-air temperature range (unless otherwise noted)

All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage.

MIN PARAMETER TEST CONDITIONS

Device BACKUP state VBAT = 2.4 V, VBACKUP = 0 V,

Device OFF state

VBAT = 0 V, VBACKUP = 3.2 V

VBAT = 3.6 V, CK32K clock running

BOOT[1:0] = 00: 32-kHz RC oscillator

Device SLEEP state

Device ACTIVE state

BOOT[1:0] = 01: 32-kHz quartz or bypass oscillator, BOOT0P

= 0

BOOT[1:0] = 01, Backup Battery Charger on, VBACKUP = 3.2

V

VBAT = 5 V, CK32K clock running:

BOOT[1:0] = 00: RC oscillator

VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0

BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load

BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load,

BOOT0P = 0

VBAT = 3.6 V, CK32K clock running, PWRHOLDP = 0

BOOT[1:0] = 00, 3 DC-DCs on, 5 LDOs and VRTC on, no load

BOOT[1:0] = 01, 3 DC-DCs on, 3 LDOs and VRTC on, no load,

BOOT0P = 0

BOOT[1:0] = 00, 3 DC-DCs on PWM mode (VDD1_PSKIP =

VDD2_PSKIP = VIO_PSKIP = 0), 5 LDOs and VRTC on, no load

TYP

11

6

16.5

15

32

20

295

279

1

0.9

21

MAX

16

9

23

20

42

28

www.ti.com

UNIT

µ A

µ A

µ A mA

POWER REFERENCES AND THRESHOLDS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Output reference voltage (VREF terminal)

TEST CONDITIONS

Device in active or low-power mode

Main battery charged Measured on VCC7 terminal threshold VMBCH (programmable) Triggering monitored through NRESPRWON

VMBCH_VSEL = 11, BOOT[1:0] = 11 or 00

VMBCH_VSEL = 10

VMBCH_VSEL = 01

VMBCH_VSEL = 00

Main battery discharged Measured on VCC7 terminal (MTL prg) threshold VMBDCH (programmable) Triggering monitored through INT1

Main battery low threshold VMBLO Measured on VCC7 terminal (Triggering

(MB comparator) monitored on terminal NRESPWRON)

Main battery high threshold VMBHI

VBACKUP = 0 V, measured on terminal VCC7

(MB comparator)

VBACKUP = 3.2 V, measured on terminal VCC7

Main battery not present threshold Measured on terminal VCC7

VBNPR (Triggering monitored on terminal VRTC)

Ground current (analog references

+ comparators + backup battery switch)

V

CC

= 3.6 V

Device in OFF state

Device in ACTIVE or SLEEP state

MIN

– 1%

2.5

2.6

2.5

1.9

TYP

0.85

3

2.9

2.8

bypassed

VMBCH –

100 mV

2.6

2.75

2.55

2.1

8

20

MAX

+1%

2.7

3

3

2.2

UNIT

V

V

V

V

V

V

µ A

10

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

THERMAL MONITORING AND SHUTDOWN

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Hot-die temperature rising threshold

TEST CONDITIONS

THERM_HDSEL[1:0] = 00

THERM_HDSEL[1:0] = 01

THERM_HDSEL[1:0] = 10

THERM_HDSEL[1:0] = 11

Hot-die temperature hysteresis

Thermal shutdown temperature rising threshold

Thermal shutdown temperature hysteresis

Ground current

Device in ACTIVE state, Temp = 27 ° C,

VCC7 = 3.6 V

MIN

113

136

TYP

117

121

125

130

10

148

10

6

MAX

136

160

UNIT

° C

°

C

° C

° C

µ A

32-kHz RTC CLOCK

over operating free-air temperature range (unless otherwise noted)

Output frequency

Oscillator startup time

Ground current

PARAMETER

CLK32KOUT rise and fall time

Input bypass clock frequency

Input bypass clock duty cycle

Input bypass clock rise and fall time

CLK32KOUT duty cycle

Bypass clock setup time

Ground current

TEST CONDITIONS MIN

C

L

= 35 pF

Bypass Clock (OSC32KIN: input, OSC32KOUT floating)

OSCKIN input

40% OSCKIN input

10%

90%, OSC32KIN input,

Logic output signal

32KCLKOUT output

Bypass mode

40%

Crystal oscillator (connected from OSC32KIN to OSC32KOUT)

CK32KOUT output

On power on

Output frequency

Output frequency accuracy

Cycle jitter (RMS)

Output duty cycle

Settling time

Ground current

RC oscillator (OSC32KIN: grounded, OSC32KOUT floating)

CK32KOUT output

@ 25

°

C

Oscillator contribution

15%

+40%

Active @ fundamental frequency

TYP

32

10

32.768

1.5

32

0%

+50%

4

MAX

10

60%

20

60%

1

1.5

2

+15%

+10%

+60%

150

UNIT

ns kHz ns ms

µ A kHz s

µ A kHz

µ s

µ A

Copyright © 2010 – 2011, Texas Instruments Incorporated

11

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

BACKUP BATTERY CHARGER

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

Backup battery charging current VBACKUP = 0 to 2.4 V, BBCHEN = 1

End-of-charge backup battery voltage

(1)

VCC7 = 3.6 V, BBSEL = 10

VCC7 = 3.6 V, BBSEL = 00

VCC7 = 3.6 V, BBSEL = 01

VCC7 = 3.6 V, BBSEL = 11

Ground current On mode

(1) Note:

(a) BBSEL = 10, 00, or 01 intended to charge battery or superCap

(b) BBSEL = 11 intended to charge capacitor

MIN

350

– 3%

– 3%

– 3%

VBAT –

0.3 V

VRTC LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

Input voltage V

IN

DC output voltage V

OUT

Rated output current I

OUTmax

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Ripple rejection

Ground current

On mode

Back-up mode

On mode, 3.0 V < V

IN

< 5.5 V

Back-up mode, 2.3 V ≤ V

IN

≤ 2.6 V

On mode

Back-up mode

On mode, I

OUT

= I

OUTmax to 0

Back-up mode, I

OUT

= I

OUTmax to 0

On mode, V

IN

= 3.0 V to V

INmax

@ I

OUT

= I

OUTmax

Back-up mode, V

IN

I

OUTmax

= 2.3 V to 5.5 V @ I

OUT

=

On mode, V

IN

= V

INmin

+ 0.2 V to V

INmax

I

OUT

= I

OUTmax and I

OUT

= I

/2 to I

OUTmax

OUTmax to I in 5

OUTmax

µ s

/2 in 5 µ s

On mode, V

IN

= V

INmin

+ 0.5 V to V

INmin in 30 µ s

And V

IN

I

OUTmax

/2

= V

INmin to V

INmin

+ 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, V

IN rising from 0 up to 3.6 V, @ V

OUT

0.1 V up to V

OUTmin

=

V

IN

= V

INDC

+ 100 mV pp

0.1 V to V

INmax

@ I

OUT tone, V

INDC+

= I

OUTmax

/2

= V

INmin

+ f = 217 Hz f = 50 kHz

Device in ACTIVE state

Device in BACKUP or OFF state

(1) These parameters are not tested. They are used for design specification only.

MIN

2.5

1.9

1.78

1.72

20

0.1

TYP

500

3.15

3

2.52

10

TYP

1.83

1.78

2.2

55

35

23

3

www.ti.com

MAX

700

+3%

+3%

+3%

VBAT

UNIT

µ A

V

µ A

MAX

5.5

3

1.88

1.84

50

50

2.5

25

50

(1)

25

(1)

UNIT

V

V mA mV mV mV mV ms dB

µ A

12

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VIO SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage (VCCIO and VCC7) V

IN

DC output voltage (V

OUT

)

Rated output current I

OUTmax

P-channel MOSFET

On-resistance R

DS(ON)_PMOS

P-channel leakage current I

LK_PMOS

N-channel MOSFET

On-resistance R

DS(ON)_NMOS

N-channel leakage current I

LK_NMOS

PMOS current limit (high-side)

NMOS current limit (low-side)

DC load regulation

DC line regulation

Transient load regulation t on, off to on

Overshoot

TEST CONDITIONS

I

OUT

≤ 800 mA

V

OUT

= 1.5 V or 1.8 V, I

OUT

> 800 mA

V

OUT

= 2.5 V, I

OUT

> 800 mA

V

OUT

= 3.3 V, I

OUT

> 800 mA

PWM mode (VIO_PSKIP = 0) or pulse skip mode I

OUT to I

MAX

VSEL=00

VSEL = 01, default BOOT[1:0] = 00 and 01

VSEL = 10

VSEL = 11

Power down

ILMAX[1:0] = 00, default

ILMAX[1:0] = 01

V

IN

= V

INmin

V

IN

= 3.8 V

V

IN

= V

INMAX

, SWIO = 0 V

V

IN

= V

MIN

V

IN

= 3.8 V

V

IN

= V

INmax

, SWIO = V

INmax

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 00

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 01

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 01

Source current load:

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 00

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 01

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 10

Sink current load:

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 00

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 01

V

IN

= V

INmin to V

INmax

, ILMAX[1:0] = 10

On mode, I

OUT

= 0 to I

OUTmax

On mode, V

IN

= V

INmin to V

INmax

V

IN

= 3.8 V, V

OUT

= 1.8 V

I

OUT

= 0 to 500 mA , Max slew = 100 mA/ µ s

I

OUT

= 700 to 1200 mA , Max slew = 100 mA/ µ s

I

OUT

= 200 mA

SMPS turned on

Power-save mode Ripple voltage Pulse skipping mode, I

OUT

= 1 mA

Switching frequency

Duty cycle

Minimum On Time T

ON(MIN)

P-channel MOSFET

VFBIO internal resistance

Discharge resistor for power-down sequence R

DIS

During device switch-off sequence

Note: No discharge resistor is applied if VIO is turned off while the device is on.

MIN

2.7

3.2

4.0

4.4

– 3%

– 3%

– 3%

– 3%

500

1000

650

1200

1700

650

1200

1700

800

1200

1700

0.5

TYP

1.5

1.8

2.5

3.3

0

300

250

300

250

350

3%

0.025

×

V

OUT

3

35

1

30

MAX

5.5

5.5

5.5

5.5

+3%

+3%

+3%

+3%

400

2

400

2

20

20

50

100

50

UNIT

V

V mA m Ω

µ A m Ω

µ A mA mA mV mV mV

µ s

V

PP

MHz

% ns

M Ω

Ω

Copyright © 2010 – 2011, Texas Instruments Incorporated

13

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

VIO SMPS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Ground current (I

Q

)

Conversion efficiency

TEST CONDITIONS

Off

PWM mode, I

OUT

VIO_PSKIP = 0

= 0 mA, V

IN

= 3.8 V,

Pulse skipping mode, no switching, 3-MHz clock on

Low-power (pulse skipping) mode, no switching

ST[1:0]=11

PWM mode, DCR

L

= 3.6 V:

< 50 m Ω , V

OUT

= 1.8 V, V

IN

I

OUT

= 10 mA

I

OUT

= 100 mA

I

OUT

= 400 mA

I

OUT

= 800 mA

I

OUT

= 1000 mA

Pulse Skipping mode, DCR

L

1.8 V, V

IN

= 3.6 V:

< 50 m Ω , V

OUT

=

I

OUT

= 1 mA

I

OUT

= 10 mA

I

OUT

= 200 mA

MIN TYP

7500

250

63

44%

87%

86%

76%

72%

71%

80%

87%

www.ti.com

MAX

1

UNIT

µ A

14

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VDD1 SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage (VCC1 and VCC7) V

IN

DC output voltage (V

OUT

)

TEST CONDITIONS

I

OUT

≤ 1200 mA

I

V

OUT

OUT

= 0.6 V to 1.5 V, VGAIN_SEL = 00,

> 1200 mA

I

2.5 V ≤ V

OUT

OUT

> 1200 mA

3.3 V, VGAIN_SEL = 10 or 11,

VGAIN_SEL = 00, I

OUT

= 0 to I

OUTmax

: max programmable voltage, SEL[6:0] = 1001011 default voltage, BOOT[1:0] = 00 default voltage, BOOT[1:0] = 01 min programmable voltage, SEL[6:0] = 0000011

SEL[6:0] = 000000: power down

VGAIN_SEL = 10, SEL = 0101011 = 43, I

OUT to I

OUTmax

= 0

VGAIN_SEL = 11, SEL = 0101000 = 40, I

OUT to I

OUTmax

= 0

DC output voltage programmable step (V

OUTSTEP

)

Rated output current I

OUTmax

VGAIN_SEL = 00, 72 steps

P-channel MOSFET

On-resistance R

DS(ON)_PMOS

P-channel leakage current

I

LK_PMOS

N-channel MOSFET

On-resistance R

DS(ON)_NMOS

N-channel leakage current I

LK_NMOS

PMOS current limit (high-side)

ILMAX = 0, default

ILMAX = 1

V

IN

= V

INmin

V

IN

= 3.8 V

V

IN

= V

INmax

, SW1 = 0 V

NMOS current limit (low-side)

DC load regulation

DC line regulation

Transient load regulation t on, off to on

Output voltage transition rate

Overshoot

V

IN

= V

MIN

V

IN

= 3.8 V

V

IN

= V

INmax

, SW1 = V

INmax

V

IN

= V

INmin to V

INmax

, ILMAX = 0

V

IN

= V

INmin to V

INmax

, ILMAX = 1

Source current load:

V

IN

= V

INmin to V

INmax

, ILMAX = 0

V

IN

= V

INmin to V

INmax

, ILMAX = 1

Sink current load:

V

IN

= V

INmin to V

INmax

, ILMAX = 0

V

IN

= V

INmin to V

INmax

, ILMAX = 1

On mode, I

OUT

= 0 to I

OUTmax

On mode, V

IN

= V

INmin to V

INmax

V

IN

= 3.8 V, V

OUT

= 1.2 V

I

OUT

= 0 to 500 mA , Max slew = 100 mA/ µ s

I

OUT

= 700 mA to 1.2A , Max slew = 100 mA/ µ s

I

OUT

= 200 mA

From V

OUT

0.6 V I

OUT

= 0.6 V to 1.5 V and V

= 500 mA

OUT

= 1.5 V to

TSTEP[2:0] = 001

TSTEP[2:0] = 011 (default)

TSTEP[2:0] = 111

SMPS turned on

Power-save mode ripple voltage Pulse skipping mode, I

OUT

= 1 mA

Switching frequency

MIN

2.7

V

OUT

V

+ 2

4.5

– 3%

– 3%

– 3%

– 3%

1000

1500

1150

2000

1150

2000

1200

2000

TYP

1.5

1.2

1.2

0.6

0

2.2

3.2

12.5

300

250

300

250

350

12.5

7.5

2.5

3%

0.025

×

V

OUT

3

MAX

5.5

5.5

5.5

+3%

+3%

+3%

+3%

400

2

400

2

20

20

50

UNIT

V

V

V

V mV mA m Ω

µ A m Ω

µ A mA mA mV mV mV

µ s mV/ µ s

V

PP

MHz

Copyright © 2010 – 2011, Texas Instruments Incorporated

15

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

VDD1 SMPS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Duty cycle

Minimum on time t

ON(MIN)

P-channel MOSFET

VFB1 internal resistance

Discharge resistor for power-down sequence R

DIS

Ground current (I

Q

)

TEST CONDITIONS

Conversion efficiency

Off

PWM mode, I

OUT

VDD1_PSKIP = 0

= 0 mA, V

IN

= 3.8 V,

Pulse skipping mode, no switching

Low-power (pulse skipping) mode, no switching

ST[1:0] = 11

PWM mode, DCR

L

3.6 V:

< 0.1

Ω , V

OUT

= 1.2 V, V

IN

=

I

OUT

= 10 mA

I

OUT

= 200 mA

I

OUT

= 400 mA

I

OUT

= 800 mA

I

OUT

= 1500 mA

Pulse skipping mode, DCR

L

V, V

IN

= 3.6 V:

< 0.1

Ω , V

OUT

= 1.2

I

OUT

= 1 mA

I

OUT

= 10 mA

I

OUT

= 200 mA

MIN

0.5

TYP

35

1

30

7500

78

63

35%

82%

81%

74%

62%

59%

70%

82%

www.ti.com

MAX

100

UNIT

% ns

M Ω

Ω 50

1

µ A

16

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VDD2 SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage (VCC2 and VCC4) V

IN

DC output voltage (V

OUT

)

TEST CONDITIONS

I

OUT

≤ 1200 mA

I

V

OUT

OUT

= 0.6 V to 1.5 V, VGAIN_SEL = 00,

> 1200 mA

I

2.5 V ≤ V

OUT

OUT

> 1200 mA

3.3 V, VGAIN_SEL = 10 or 11,

VGAIN_SEL = 00, I

OUT

= 0 to I

OUTmax

: max programmable voltage, SEL[6:0] = 1001011 default, BOOT[1:0] = 01 min programmable voltage, SEL[6:0] = 0000011

SEL[6:0] = 000000: power down

VGAIN_SEL = 10, SEL = 0101011 = 43

VGAIN_SEL = 11, default, BOOT[1:0] = 00

DC output voltage programmable step (V

OUTSTEP

)

Rated output current I

OUTmax

VGAIN_SEL = 00, 72 steps

P-channel MOSFET

On-resistance R

DS(ON)_PMOS

P-channel leakage current I

LK_PMOS

N-channel MOSFET

On-resistance R

DS(ON)_NMOS

N-channel leakage current I

LK_NMOS

PMOS current limit (high-side)

NMOS current limit (low-side)

DC load regulation

DC line regulation

Transient load regulation t on, Off to on

Output voltage transition rate

ILMAX = 0, default

ILMAX = 1

V

IN

= V

INmin

V

IN

= 3.8 V

V

IN

= V

INmax

, SW2 = 0 V

V

IN

= V

MIN

V

IN

= 3.8 V

V

IN

= V

INmax

, SW2 = V

INmax

V

IN

= V

INmin to V

INmax

, ILMAX = 0

V

IN

= V

INmin to V

INmax

, ILMAX = 1

Source current load:

V

IN

= V

INmin to V

INmax

, ILMAX = 0

V

IN

= V

INmin to V

INmax

, ILMAX = 1

Sink current load:

V

IN

= V

INmin to V

INmax

, ILMAX = 0

V

IN

= V

INmin to V

INmax

, ILMAX = 1

On mode, I

OUT

= 0 to I

OUTmax

On mode, V

IN

= V

INmin to V

INmax

@ I

OUT

= I

OUTmax

V

IN

= 3.8 V, V

OUT

= 1.2 V

I

OUT

= 0 to 500 mA , Max slew = 100 mA/ µ s

I

OUT

= 700 mA to 1.2 A , Max slew = 100 mA/ µ s

I

OUT

= 200 mA

From V

OUT

0.6 V I

OUT

= 0.6 V to 1.5 V and V

= 500 mA

OUT

= 1.5 V to

TSTEP[2:0] = 001

TSTEP[2:0] = 011 (default)

TSTEP[2:0] = 111

Pulse skipping mode, I

OUT

= 1 mA Power-save mode ripple voltage

Overshoot

Switching frequency

Duty cycle

Minimum On time

P-Channel MOSFET

MIN

2.7

V

OUT

V

+ 2

4.5

– 3%

– 3%

3%

1000

1500

1150

2200

1150

2000

1200

2000

TYP

1.5

1.2

0.6

0

2.2

3.3

12.5

300

250

300

250

350

12.5

7.5

2.5

0.025

V

OUT

3%

3

35

MAX

5.5

5.5

5.5

+3%

+3%

+3%

400

2

400

2

20

20

50

100

UNIT

V

V mV mA m Ω

µ A m

Ω

µ A mA mA mV mV mV

µ s

µ s

V

PP

MHz

% ns

Copyright © 2010 – 2011, Texas Instruments Incorporated

17

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

VDD2 SMPS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

VFB2 internal resistance

Discharge resistor for power-down sequence R

DIS

Ground current (I

Q

)

TEST CONDITIONS

Conversion efficiency

Off

PWM mode, I

OUT

VDD2_PSKIP = 0

= 0 mA, V

IN

= 3.8 V,

Pulse skipping mode, no switching

Low-power (pulse skipping) mode, no switching

ST[1:0] = 11

PWM mode, DCR

L

3.6 V:

< 50 m Ω , V

OUT

= 1.2 V, V

IN

=

I

OUT

= 10 mA

I

OUT

= 200 mA

I

OUT

= 400 mA

I

OUT

= 800 mA

I

OUT

= 1200 mA

I

OUT

= 1500 mA

Pulse skipping mode mode, DCR

L

= 1.2 V, V

IN

= 3.6 V:

< 50 m Ω , V

OUT

I

OUT

= 1 mA

I

OUT

= 10 mA

I

OUT

= 200 mA

PWM mode, DCR

L

5 V:

< 50 m Ω , V

OUT

= 3.3 V, V

IN

=

I

OUT

= 10 mA

I

OUT

= 200 mA

I

OUT

= 400 mA

I

OUT

= 800 mA

I

OUT

= 1200 mA

I

OUT

= 1500 mA

Pulse skipping mode mode, DCR

L

= 3.3 V, V

IN

= 5 V:

< 50 m Ω , V

OUT

I

OUT

= 1 mA

I

OUT

= 10 mA

I

OUT

= 200 mA

MIN

0.5

TYP

1

30

7500

78

63

35%

82%

81%

74%

66%

62%

59%

70%

82%

44%

90%

91%

88%

84%

81%

75%

83%

90%

www.ti.com

MAX

50

1

UNIT

M Ω

Ω

µ A

18

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VDD3 SMPS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage V

IN

DC output voltage (V

OUT

)

Rated output current I

OUTmax

N-channel MOSFET

On-resistance R

DS(ON)_NMOS

N-channel MOSFET leakage current I

LK_NMOS

N-channel MOSFET DC current limit

Turn-on inrush current

Ripple voltage

DC load regulation

DC line regulation

Turn-on time

Overshoot

Switching frequency

VFB3 internal resistance

Ground current (I

Q

)

V

IN

= 3.6 V

TEST CONDITIONS

V

IN

= V

INmax

, SW3 = V

INmax

V

IN

= V

INmin to V

INmax

, sink current load

V

IN

= V

INmin to V

INmax

On mode, I

OUT

= 0 to I

OUTmax

On mode, V

IN

= V

INmin to 5 V @ I

OUT

= I

OUTmax

I

OUT

= 8 mA, V

OUT

= 0 to 4.4 V

Conversion efficiency

Off

I

OUT

= 0 mA to I

OUTmax

, V

IN

= 3.6 V

V

IN

= 3.6 V:

I

OUT

= 10 mA

I

OUT

= 50 mA

I

OUT

= 100 mA

MIN

3

4.65

100

430

TYP

5

500

550

20

200

3%

1

088

360

81%

85%

85%

MAX

5.5

5.25

2

850

100

100

1 mA mA mV mV mV

µ s

UNIT

V

V mA m Ω

µ A

MHz

M

Ω

µ A

Copyright © 2010 – 2011, Texas Instruments Incorporated

19

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

VDIG1 AND VDIG2 LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage (VCC6) V

IN

DC output voltage V

OUT

Rated output current I

OUTmax

TEST CONDITIONS

V

OUT

(VDIG1) = 1.2 V / 1.5 V @ 100 mA and

V

OUT

(VDIG2) =1.2 V / 1.1 V / 1.0 V

V

OUT

(VDIG1) = 1.5 V and V

OUT

(VDIG1,VDIG2) =

1.8 V @ 200mA

V

OUT

(VDIG1) = 1.8 V and V

OUT

(VDIG1) = 1.8 V

V

OUT

(VDIG1) = 2.7 V

VDIG1

ON and Low-power mode, V

IN

= V

INmin to V

INmax

SEL = 11, I

OUT

= 0 to I

OUTmax

SEL = 10 I

OUT

= 0 to I

OUTmax

SEL = 01 I

OUT

= 0 to 100 mA/I

OUTmax

SEL = 00, I

OUT

= 0 to I

OUTmax default BOOT[1:0] = 00 or 01

, V

IN

= V

INmin to 4 V,

On mode

Low-power mode

Load current limitation (short-circuit protection)

Dropout voltage V

DO

On mode, V

OUT

= V

OUTmin

100 mV

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Turn-on inrush current

ON mode, VDO = V

IN

– V

OUT

V

OUTtyp

25 ° C

= 2.7 V, V

IN

= 2.8 V, I

OUT

= I

OUTmax

, T =

V

OUTtyp

25 ° C

= 1.5 V, V

IN

= 1.7 V, I

OUT

= I

OUTmax

, T =

On mode, I

OUT

= I

OUTmax to 0

On mode, V

IN

= V

INmin to V

INmax

@ I

OUT

= I

OUTmax

ON mode, V

IN

= 3.8 V

I

OUT

I

OUT

= 20 mA to 180 mA in 5 µ s and

= 180 mA to 20 mA in 5 µ s

On mode, V

IN

= 2.7 + 0.5 V to 2.7 in 30 µ s,

I

And V

IN

OUTmax

/2

= 2.7 to 2.7 + 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

Ripple rejection

VDIG1 internal resistance

Ground current

DC output voltage V

OUT

V

IN

= V

INDC

I

OUTmax

/2

+ 100 mV pp tone,

VINDC+

= 3.8 V, I

OUT

= f = 217 Hz f = 50 kHz

LDO off

On mode, I

OUT

= 0, VCC6 = VBAT, V

OUT

= 2.7 V

On mode, I

OUT

= 0, VCC6 = 1.8 V, V

OUT

= 1.2 V

On mode, I

OUT

2.7 V

= I

OUTmax

, VCC6 = VBAT, V

OUT

=

On mode, I

OUT

1.2 V

= I

OUTmax

, VCC6 = 1.8 V, V

OUT

=

Low-power mode, VCC6 = VBAT, V

OUT

= 2.7 V

Low-power mode, VCC6 = 1.8 V, V

OUT

= 1.2 V

Off mode

VDIG2

On and low-power mode, V

IN

= V

INmin to V

INmax

MIN

1.7

2.1

2.7

3.2

– 3%

– 3%

– 3%

– 3%

300

1

350

TYP

600

10

2

100

300

70

40

400

54

67

1870

1300

13

10

2.7

1.8

1.5

1.2

150

300

MAX

5.5

5.5

5.5

5

UNIT

V

+3%

+3%

+3%

+3%

25

3

1

www.ti.com

V mA mA mV mV mV mV mV

µ s mA dB

Ω

µ A

20

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VDIG1 AND VDIG2 LDO (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Rated output current I

OUTmax

TEST CONDITIONS

SEL = 11, I

OUT

= 0 to I

OUTmax

SEL = 10 I

OUT

= 0 to I

OUTmax

, V

IN

= V

INmin to 4 V

SEL = 01 I

OUT to 4 V

= 0 to 100 mA/I

OUTmax

, V

IN

= V

INmin

SEL = 00, I

OUT

= 0 to I

OUTmax default BOOT[1:0] = 00 or 01

, V

IN

= V

INmin to 4 V,

On mode

Low-power mode

Load current limitation (short-circuit protection)

Dropout voltage V

DO

On mode, V

OUT

= V

OUTmin

– 100 mV

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Turn-on inrush current

ON mode, V

DO

= V

IN

– V

OUT

,

V

OUTtyp

25 ° C

= 1.8 V, V

IN

= 2.1 V, IOUT=I

OUTmax

, T =

On mode, I

OUT

= I

OUTmax to 0

On mode, V

IN

= V

INmin to V

INmax

@ I

OUT

= I

OUTmax

ON mode, V

IN

= 3.8 V

I

OUT

I

OUT

= 20 mA to 180 mA in 5 µ s and

= 180 mA to 20 mA in 5 µ s

On mode, V

IN

= 2.7 + 0.5 V to 2.7 in 30 µ s,

And V

IN

I

OUTmax

/2

= 2.7 to 2.7 + 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

Ripple rejection

VDIG2 internal resistance

Ground current

V

IN

= V

I

OUTmax

INDC

/2

+ 100 mV pp tone,

VINDC+

= 3.8 V, I

OUT

= f = 217 Hz f = 50 kHz

LDO off

On mode, I

OUT

= 0, VCC6 = VBAT, V

OUT

= 1.8 V

On mode, I

OUT

= 0, VCC6 = 1.8 V, V

OUT

= 1.0 V

On mode, I

OUT

1.8 V

= I

OUTmax

, VCC6 = VBAT, V

OUT

=

On mode, I

OUT

1.0 V

= I

OUTmax

, VCC6 = 1.8 V, V

OUT

=

Low-power mode, VCC6 = VBAT, V

OUT

= 1.8 V

Low-power mode, VCC6 = 1.8 V, V

OUT

= 1.0 V

Off mode

MIN

– 3%

– 3%

– 3%

– 3%

300

1

350

TYP

1.8

1.2

1.1

1

600

250

10

2

100

300

70

40

400

52

67

1750

1300

11

10

MAX

+3%

+3%

+3%

+3%

25

3

1

UNIT

V mA mA mV mV mV mV mV

µ s mA dB

Ω

µ

A

Copyright © 2010 – 2011, Texas Instruments Incorporated

21

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

VAUX33 AND VMMC LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage (VCC3) V

IN

DC output voltage V

OUT

Rated output current I

OUTmax

TEST CONDITIONS

V

OUT

1.8 V

(VAUX33) = 1.8 V / 2 V and V

OUT

(VMMC) =

V

OUT

(VAUX33) = 2.8 V

V

OUT

(VAUX33) = 3.3 V

V

OUT

(VMMC) = 2.8 V @ 200 mA

V

OUT

(VMMC) = 3.0 V

V

OUT

(VMMC) = 3.3 V @ 200 mA

VAUX33

On and low-power mode, V

IN

= V

INmin to V

INmax

SEL = 11, I

OUT

01

= 0 to I

OUTmax

, Default BOOT[1:0] =

SEL = 10, I

OUT

= 0 to I

OUTmax

SEL = 01, I

OUT

= 0 to I

OUTmax

SEL = 00, I

OUT

00

= 0 to I

OUTmax

, default BOOT[1:0] =

On mode

Low-power mode

Load current limitation

(short-circuit protection)

Dropout Voltage V

DO

On mode, V

OUT

= V

OUTmin

– 100 mV

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Turn-on inrush current

On mode, V

OUTtyp

= 2.8 V, V

DO

= V

IN

– V

OUT

,

V

IN

= 2.9 V, I

OUT

= I

OUTmax

, T = 25 ° C

On mode, I

OUT

= I

OUTmax to 0

On mode, I

OUT

= I

OUTmax

On mode, V

IN

= 3.8 V

I

OUT

I

OUT

= 0.1

× I

OUTmax

= 0.9

× I

OUTmax to 0.9

× I

OUTmax to 0.1

× I

OUTmax in 5 µ s and in 5 µ s

On mode, I

OUT

V

INmin in 30 µ s

= I

OUTmax

,V

IN

= V

INmin

+ 0.5 V to

I and V

IN

OUTmax

= V

/2

INmin to V

INmin

+ 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

Ripple Rejection

VAUX33 internal resistance

Ground current

DC output voltage V

OUT

V

IN

= V

INDC

= I

OUTmax

/2

+ 100 mV pp tone, V

INDC+

= 3.8 V, I

OUT f = 217 Hz f = 50 kHz

LDO off

On mode, I

OUT

= 0

On mode, I

OUT

= I

OUTmax

Low-power mode

Off mode

VMMC

On and low-power mode, V

IN

= V

INmin to V

INmax

SEL = 11, I

OUT

00

= 0 to 200 mA, default BOOT[1:0] =

SEL = 10, I

OUT

= 0 to I

OUTmax

SEL = 01, I

OUT

= 0 to 200 mA

SEL = 00, I

OUT

01

= 0 to I

OUTmax

, default BOOT[1:0] =

– 3%

– 3%

– 3%

– 3%

MIN

2.7

3.2

3.6

3.2

3.6

3.6

– 3%

3%

– 3%

– 3%

150

1

350

TYP

500

150

12

2

100

600

70

40

70

55

1600

15

3.3

2.8

2.0

1.8

3.3

3.0

2.8

1.8

22

MAX

5.5

5.5

5.5

5.5

5.5

5.5

20

3

1

+3%

+3%

+3%

+3%

+3%

+3%

+3%

+3%

www.ti.com

UNIT

V

V mV

µ s mA dB

Ω

µ A

V

Copyright © 2010 – 2011, Texas Instruments Incorporated mA mA mV mV mV mV

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VAUX33 AND VMMC LDO (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Rated output current I

OUTmax

TEST CONDITIONS

On mode

Low-power mode

Load current limitation

(short-circuit protection)

Dropout voltage V

DO

On mode, V

OUT

= V

OUTmin

– 100 mV

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Ripple rejection

VMMC internal resistance

Ground current

Dropout voltage V

DO

V

IN

= 3.0 V, I

OUT

= 200 mA, T = 25 ° C

On mode, I

OUT

= I

OUTmax to 0

On mode, V

IN

= V

INmin to V

INmax

@ I

OUT

= I

OUTmax

On mode, V

IN

= 3.8 V

I

OUT

= 20 mA to 180 mA in 5 to 20 mA in 5 µ s

µ s and I

OUT

= 180 mA

On mode, I

OUT

V

INmin in 30 µ s

= 200 mA, V

IN

= V

INmin

+ 0.5 V to

And V

IN

I

OUTmax

/2

= V

INmin to V

INmin

+ 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

V

IN

= V

I

OUTmax

INDC

/2

+ 100 mV pp tone, V

INDC+

= 3.8 V, I

OUT

= f = 217 Hz f = 50 kHz

LDO Off

On mode, I

OUT

= 0

On mode, I

OUT

= I

OUTmax

Low-power mode

Off mode

MIN

300

1

350

TYP

500

200

12

2

100

70

40

70

55

2700

15

MAX

25

3

1

UNIT

mA mA mV mV mV mV mV

µ s dB

Ω

µ A

Copyright © 2010 – 2011, Texas Instruments Incorporated

23

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

VAUX1 AND VAUX2 LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage (VCC4) V

IN

DC output voltage V

OUT

Rated output current I

OUTmax

TEST CONDITIONS

V

OUT

(VAUX1) = 1.8 V and V

OUT

(AUX2) = 1.8 V

V

OUT

(VAUX1) = 2.5 V

V

OUT

@ I load

(VAUX1) = 2.8 V @ I load

= 200mA

= 200 mA and 2.85 V

V

OUT

(VAUX2) = 2.8 V

V

OUT

(VAUX2) = 2.9 V @ I load

= 100mA

V

OUT

(VAUX2) = 3.3 V

VAUX1

On and low-power mode, V

IN

= V

INmin to V

INmax

SEL = 11, I

OUT

= 0 to 200 mA

SEL = 10, I

OUT

= 0 to 200 mA

SEL = 01, I

OUT

= 0 to I

OUTmax

SEL = 00, I

OUT

00 or 01

= 0 to I

OUTmax

, default BOOT[1:0] =

On mode

Low-power mode

Load current limitation

(short-circuit protection)

Dropout voltage V

DO

On mode, V

OUT

= V

OUTmin

– 100 mV

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Turn-on inrush current

On mode, V

OUTtyp

= 2.8 V, V

DO

= V

IN

– V

OUT

,

V

IN

= 3.0 V, I

OUT

= 200 mA, T = 25 ° C

On mode, I

OUT

= 200 mA to 0

On mode, I

OUT

= 200 mA

On mode, V

IN

µ s

= 3.8 V, I

OUT

= 20 mA to 180 mA in 5 and I

OUT

= 180 mA to 20 mA in 5 µ s

On mode, I

OUT

V

INmin in 30 µ s

= 200 mA, V

IN

= V

INmin

+ 0.5 V to and V

IN

= V

INmin

I

OUTmax

/2 to V

INmin

+ 0.5v in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

, no load

Ripple Rejection

VAUX1 internal resistance

Ground current

Rated output current I

OUTmax

I

V

IN

= V

OUTmax

INDC

/2

+ 100 mV pp tone, V

INDC+

= 3.8 V, I

OUT

= f = 217 Hz f = 50 kHz

LDO Off

On mode, I

OUT

= 0

On mode, I

OUT

= I

OUTmax

Low-power mode

Off mode

VAUX2

On and low-power mode, V

IN

= V

INmin to V

INmax

SEL = 11, I

OUT

= 0 to I

OUTmax

SEL = 10, I

OUT

= 0 to 100 mA

SEL = 01, I

OUT

= 0 to I

OUTmax

SEL = 00, I

OUT

00 or 01

= 0 to I

OUTmax

, default BOOT[1:0] =

On mode

Low-power mode

MIN

2.7

3.2

3.2

3.2

3.2

3.6

– 3%

– 3%

– 3%

– 3%

300

1

350

– 3%

– 3%

– 3%

– 3%

150

1

24

TYP

2.85

2.8

2.5

1.8

500

200

15

2

100

600

3.3

2.9

2.8

1.8

70

40

80

60

2700

12

MAX

5.5

5.5

5.5

5.5

5.5

5.5

+3%

+3%

+3%

+3%

15

5

1

+3%

+3%

+3%

+3%

www.ti.com

UNIT

V

V mA mA mV mA

V mV mV

µ s mA dB

Ω

µ A

V mA

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VAUX1 AND VAUX2 LDO (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Load current limitation

(short-circuit protection)

Dropout voltage V

DO

TEST CONDITIONS

On mode, V

OUT

= V

OUTmin

– 100 mV

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Turn-on Inrush current

On mode, V

OUTtyp

= 2.8 V, V

DO

= V

IN

– V

OUT

V

IN

= 2.9 V, I

OUT

= I

OUTmax

, T = 25 ° C

On mode, I

OUT

= I

OUTmax to 0

On mode, V

IN

= V

INmin to V

INmax

@ I

OUT

= I

OUTmax

I

On mode, V

IN

OUTmax in 5 µ s

= 3.8 V, I

OUT

= 0.1

× I

OUTmax to 0.9

×

And I

OUT

= 0.9

× IOUTmax to 0.1

× IOUTmax in 5us

On mode, I

OUT

V

INmin in 30 µ s

= I

OUTmax

, V

IN

= V

INmin

+ 0.5 V to

And V

IN

= V

INmin

I

OUTmax

/2 to V

INmin

+ 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

Ripple rejection

VAUX2 internal resistance

Ground current

I

V

IN

= V

OUTmax

INDC

/2

+ 100 mV pp tone, V

INDC+

= 3.8 V, I

OUT

= f = 217 Hz f = 50 kHz

LDO off

On mode, I

OUT

= 0

On mode, I

OUT

= I

OUTmax

Low-power mode

Off mode

MIN

350

TYP

500

150

12

2

100

600

70

40

80

60

1600

12

MAX

15

2

1

UNIT

mA mV mV mV mV mV

µ s mA dB

Ω

µ

A

Copyright © 2010 – 2011, Texas Instruments Incorporated

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TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

VDAC AND VPLL LDO

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Input voltage (VCC5) V

IN

DC Output voltage V

OUT

Rated output current I

OUTmax

TEST CONDITIONS

V

OUT

(VDAC) = 1.8 V and V

OUT

(VPLL) = 1.8 V / 1.1 V

/ 1.0 V

V

OUT

(VDAC) = 2.6 V and V

OUT

(VPLL) = 2.5 V

V

OUT

(VDAC) = 2.8 V / 2.85 V

VDAC

On and low-power mode, V

IN

= V

INmin to V

INmax

SEL = 11, I

OUT

= 0 to I

OUTmax

SEL = 10, I

OUT

= 0 to I

OUTmax

SEL = 01, I

OUT

= 0 to I

OUTmax

SEL = 00, I

OUT

00 or 01

= 0 to I

OUTmax

, default BOOT[1:0] =

On mode

Low-power mode

Load current limitation

(short-circuit protection)

Dropout Voltage V

DO

On mode, V

OUT

= V

OUTmin

– 100 mV

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Turn-on Inrush current

On mode, V

OUTtyp

= 2.8 V, V

DO

= V

IN

– V

OUT

,

V

IN

= 2.9 V, I

OUT

= I

OUTmax

, T = 25 ° C

On mode, V

OUT

= V

OUTmin

– 100 mV

On mode, V

OUT

= 1.8 V, I

OUT

= I

OUTmax

I

On mode, V

IN

OUTmax in 5 µ s

= 3.8 V, I

OUT

= 0.1

× I

OUTmax to 0.9

×

And I

OUT

= 0.9

× I

OUTmax to 0.1

× I

OUTmax in 5 µ s

On mode, I

OUT

V

INmin in 30 µ s

= I

OUTmax

, V

IN

= V

INmin

+ 0.5 V to

And V

IN

I

OUTmax

/2

= V

INmin to V

INmin

+ 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

Ripple Rejection

VDAC internal resistance

Ground current

DC output voltage V

OUT

Rated output current I

OUTmax

V

IN

= V

I

OUTmax

INDC

/2

+ 100 mV pp tone, V

INDC+

= 3.8 V, I

OUT

= f = 217 Hz f = 50 kHz

LDO off

On mode, I

OUT

= 0

On mode, I

OUT

= I

OUTmax

Low-power mode

Off mode

VPLL

On and low-power mode, V

IN

= V

INmin to V

INmax

SEL = 11, I

OUT

= 0 to I

OUTmax

SEL = 10, I

OUT or 01

= 0 to I

OUTmax

, default BOOT[1:0 = 00

SEL = 01, I

OUT

= 0 to I

OUTmax

SEL = 00, I

OUT

= 0 to I

OUTmax

On mode

Low-power mode

Load current limitation

(short-circuit protection)

Dropout voltage V

DO

On mode, V

OUT

= V

OUTmin

100 mV

On mode, V

OUTtyp

= 2.5 V, V

DO

= V

IN

– V

OUT

,

MIN

2.7

3.0

3.2

– 3%

– 3%

3%

– 3%

50

1

200

– 3%

– 3%

– 3%

– 3%

150

1

350

26

TYP

2.85

2.8

2.6

1.8

500

150

15

0.5

100

600

2.5

1.8

1.1

1.0

70

40

360

60

1600

12

400

100

MAX

5.5

5.5

5.5

+3%

+3%

+3%

+3%

15

2

1

+3%

+3%

+3%

+3%

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UNIT

V

V mA mA mV mA mA mV mV mV mV mV

µ s mA dB k Ω

µ A

V

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VDAC AND VPLL LDO (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

DC load regulation

DC line regulation

Transient load regulation

Transient line regulation

Turn-on time

Turn-on inrush current

TEST CONDITIONS

V

IN

= 2.5 V, I

OUT

= I

OUTmax

, T = 25 ° C

On mode, I

OUT

= I

OUTmax to 0

On mode, V

IN

= V

INmin to V

INmax

@ I

OUT

= I

OUTmax

I

On mode, V

IN

OUTmax in 5 µ s

= 3.8 V, I

OUT

= 0.1

× I

OUTmax to 0.9

×

And I

OUT

= 0.9

× I

OUTmax to 0.1

× I

OUTmax in 5 µ s

On mode, V

IN

= V

INmin

+ 0.5 V to V

INmin in 30 µ s

And V

IN

I

OUTmax

/2

= V

INmin to V

INmin

+ 0.5 V in 30 µ s, I

OUT

=

I

OUT

= 0, @ V

OUT

= 0.1 V up to V

OUTmin

Ripple rejection

VPLL internal resistance

Ground current

V

IN

= V

INDC

I

OUTmax

/2

+ 100 mV pp tone, V

INDC+

= 3.8 V, I

OUT

= f = 217 Hz f = 50 kHz

LDO off

On mode, I

OUT

= 0

On mode, I

OUT

= I

OUTmax

Low-power mode

Off mode

MIN TYP

9

0.5

100

300

70

40

535

60

1600

12

MAX

10

1

1

UNIT

mV mV mV mV

µ s mA dB k Ω

µ A

SWITCH-ON/-OFF SEQUENCES AND TIMING

Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition.

BOOT1 = 0, BOOT0 = 0

Table 2

provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot mode is provided in

Figure 2 .

Register

VDD1_OP_REG

VDD1_REG

EEPROM

DCDCCTRL_REG

VDD2_OP_REG/VDD2_SR_REG

VDD2_REG

EEPROM

DCDCCTRL_REG

VIO_REG

EEPROM

DCDCCTRL_REG

EEPROM

VDIG1_REG

EEPROM

VDIG2_REG

EEPROM

Table 2. Fixed Boot Mode: 00

Bit Description

SEL

VGAIN_SEL

VDD1 voltage level selection for boot

VDD1 Gain selection, x1 or x2

VDD1 time slot selection

VDD1_PSKIP VDD1 pulse skip mode enable

SEL VDD2 voltage level selection for boot

VGAIN_SEL

SEL

VDD2 Gain selection, x1 or x3

VDD2 time slot selection

VDD2_PSKIP VDD2 pulse skip mode enable

VIO voltage selection

VIO time slot selection

VIO_PSKIP

SEL

VIO pulse skip mode enable

VDD3 time slot

LDO voltage selection

SEL

LDO time slot

LDO voltage selection

LDO time slot

TPS65910

Boot 00

1.2 V x1

3 skip enabled

1.1 V x3

2 skip enabled

1.8 V

1 skip enabled

OFF

1.2 V

OFF

1.0 V

OFF

Copyright © 2010 – 2011, Texas Instruments Incorporated

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SWCS046I – MARCH 2010 – REVISED JULY 2011

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SWITCH-ON/-OFF SEQUENCES AND TIMING (continued)

Table 2. Fixed Boot Mode: 00 (continued)

VDAC_REG

EEPROM

VPLL_REG

EEPROM

VAUX1_REG

EEPROM

VMMC_REG

EEPROM

VAUX33_REG

EEPROM

VAUX2_REG

EEPROM

CLK32KOUT pin

NRESPWRON pin

VRTC_REG

DEVCTRL_REG

DEVCTRL_REG

DEVCTRL2_REG

DEVCTRL2_REG

INT_MSK_REG

VMBCH_REG

SEL

SEL

SEL

SEL

SEL

SEL

VRTC_OFFMAS

K

RTC_PWDN

CK32K_CTRL

TSLOT_LENGTH

[0]

IT_POL

VMBHI_IT_MSK

VMBCH_SEL[1:0]

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

CLK32KOUT time slot

NRESPWRON time slot

0: VRTC LDO will be in low-power mode during OFF state

1: VRC LDO will be in full-power mode during OFF state

0: RTC in normal power mode

1: Clock gating of RTC register and logic, low-power mode

0: Clock source is crystal/external clock

1: Clock source is internal RC oscillator

Boot sequence time slot duration:

0: 0.5 ms

1: 2 ms

0: INT1 signal will be active-low

1: INT1 signal will be active-high

0: Device will automatically switch-on at NOSUPPLY to

OFF or BACKUP to OFF transition

1: Startup reason required before switch-on

Select threshold for main battery comparator threshold

VMBCH.

Low-power mode

1

RC

2 ms

Active-low

0: Automatic switch-on from supply insertion

3 V

6

1.8 V

OFF

1.8 V

5

7

7 + 1

1.8 V

5

1.8 V

4

1.8 V

1

3.3 V

28

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Figure 2

shows the 00 Boot mode timing characteristics.

t dSOFF2

PWRHOLD t dSON1

VIO/VFBIO 1.8 V

VAUX1

VDD2/VFB2

VDD1/VFB1

VPLL

VDAC t dSON2

1.8 V t dSON3

3.3 V

1.2 V t dSON4 t dSON5

1.8 V

1.8 V

VAUX2

VMMC

CLK32KOUT

NRESPWRON t dSON6

1.8 V t dSON7

3.3 V t dSON8 t dSOFF1

Switch-off sequence

SWCS046-018

Figure 2. Boot Mode: BOOT1 = 0, BOOT0 = 0

Table 3

lists the 00 Boot mode timing characteristics.

PARAMETER

t dSON1 t dSON2 t dSON3 t dSON4 t dSON5 t dSON6 t dSON8 t dSONT t dSOFF1 t dSOFF1B t dSOFF2

Table 3. Boot Mode: BOOT1 = 0, BOOT0 = 0 Timing Characteristics

MIN TEST CONDITIONS

PWRHOLD rising edge to VIO, VAUX1 enable delay

VIO to VDD2 enable delay

VDD2 to VDD1 enable delay

VDD1 to VPLL enable delay

VPLL to VDAC,VAUX2 enable delay

VDAC to VMMC enable delay

VMMC to CLK32KOUT rising edge delay

CLK32KOUT to NRESPWRON rising edge delay

Total switch-on delay

PWRHOLD falling edge to NRESPWRON falling edge delay

NRESPWRON falling edge to CLK32KOUT low delay

PWRHOLD falling edge to supplies and reference disable delay

TYP

66 × t

CK32k

= 2060

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

16

2 × t

CK32k

= 62.5

3 × t

CK32k

= 92

5 × t

CK32k

= 154

MAX

Registers default setting: CK32K_CTRL = 1 (32-kHz RC oscillator is used), RTC_PWDN = 1 (RTC domain off),

IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on Battery plug),

VMBCH_SEL = 11.

UNIT

µ s

µ s

µ s

µ s

µ s

µ s

µ s

µ s ms

µ s

µ s

µ s

BOOT1 = 0, BOOT0 = 1

Table 4

provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot mode is provided in

Figure 3 .

Copyright © 2010 – 2011, Texas Instruments Incorporated

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TPS65910, TPS659101, TPS659102, TPS659103

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SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 4. Fixed Boot Mode: 01

Register

VDD1_OP_REG

VDD1_REG

EEPROM

DCDCCTRL_REG

VDD2_OP_REG/VDD2_SR_REG

VDD2_REG

EEPROM

DCDCCTRL_REG

VIO_REG

EEPROM

DCDCCTRL_REG

EEPROM

VDIG1_REG

EEPROM

VDIG2_REG

EEPROM

VDAC_REG

EEPROM

VPLL_REG

EEPROM

VAUX1_REG

EEPROM

VMMC_REG

EEPROM

VAUX33_REG

EEPROM

VAUX2_REG

EEPROM

CLK32KOUT pin

NRESPWRON pin

VRTC_REG

DEVCTRL_REG

DEVCTRL_REG

DEVCTRL2_REG

DEVCTRL2_REG

INT_MSK_REG

VMBCH_REG

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Bit Description

SEL

VGAIN_SEL

VDD1 voltage level selection for boot

VDD1 Gain selection, x1 or x2

VDD1 time slot selection

VDD1_PSKIP VDD1 pulse skip mode enable

SEL

VGAIN_SEL

VIO_PSKIP

VDD2 voltage level selection for boot

VDD2 Gain selection, x1 or x3

VDD2 time slot selection

VDD2_PSKIP VDD2 pulse skip mode enable

SEL VIO voltage selection

VIO time slot selection

VIO pulse skip mode enable

SEL

SEL

SEL

SEL

SEL

VDD3 time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

SEL

SEL

SEL

VRTC_OFFMAS

K

RTC_PWDN

CK32K_CTRL

TSLOT_LENGTH

[0]

IT_POL

VMBHI_IT_MSK

VMBCH_SEL[1:0]

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

LDO voltage selection

LDO time slot

CLK32KOUT time slot

NRESPWRON time slot

0: VRTC LDO will be in low-power mode during OFF state

1: VRC LDO will be in full-power mode during OFF state

0: RTC in normal power mode

1: Clock gating of RTC register and logic, low-power mode

0: Clock source is crystal/external clock

1: Clock source is internal RC oscillator

Boot sequence time slot duration:

0: 0.5 ms

1: 2 ms

0: INT1 signal will be active-low

1: INT1 signal will be active-high

0: Device will automatically switch-on at NOSUPPLY to

OFF or BACKUP to OFF transition

1: Startup reason required before switch-on

Select threshold for main battery comparator threshold

VMBCH.

low-power mode

1

Crystal

2 ms

Active-low

0: Automatic switch-on from supply insertion

3 V

OFF

1.2 V

OFF

1.0 V

OFF

1.8 V

OFF

1.8 V

2

1.8 V

TPS65910

Boot 01

1.2 V x1

3

Skip enabled

1.2 V x1

4

Skip enabled

1.8 V

1

Skip enabled

OFF

1.8 V

OFF

3.3 V

6

1.8 V

5

7

7+1

30

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Figure 3

shows the 01 Boot mode timing characteristics.

t dSOFF2

PWRHOLD

VIO/VFBIO

VPLL

VDD1/VFB1

VDD2/VFB2

VAUX2

VAUX33

CLK32KOUT t dSON1 t dSON2

1.8 V t dSON3

1.8 V

1.2 V t dSON4 t dSON5

1.2 V t dSON6

1.8 V t dSON7

3.3 V t dSON8 t dSOFF1

NRESPWRON

Switch-off sequence

SWCS046-019

Figure 3. Boot Mode: BOOT1 = 0, BOOT0 = 1

Table 5

lists the 01 Boot mode timing characteristics.

PARAMETER

t dSON1 t dSON2 t dSON3 t dSON4 t dSON5 t dSON7 t dSON8 t dSONT t dSOFF1 t dSOFF1B t dSOFF2

Table 5. Boot Mode: BOOT1 = 0, BOOT0 = 1 Timing Characteristics

TEST CONDITIONS

PWRHOLD rising edge to VIO enable delay

VIO to VPLL enable delay

VPLL to VDD1 enable delay

VDD1 to VDD2 enable delay

VDD2 to VAUX2 enable delay

VAUX2 to VAUX33 enable delay

VAUX33 to CLK32KOUT enable delay

CLK32KOUT to NRESPWRON enable delay

Total switch-on delay

PWRHOLD falling edge to NRESPWRON falling edge

NRESPWRON falling edge to CLK32KOUT low delay

PWRHOLD falling edge to supplies disable delay

MIN TYP

66 × t

CK32k

= 2060

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

64 × t

CK32k

= 2000

16

2 × t

CK32k

= 62.5

3 × t

CK32k

= 92

5 × t

CK32k

= 154

MAX

µ s

µ s

µ s

µ s

µ s

UNIT

µ s

µ s

µ s ms

µ s

µ s

µ s

Registers default setting: CK32K_CTRL = 0 (32-kHz quartz or external bypass clock is used), RTC_PWDN = 1

(RTC domain off), IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on battery plug), VMBCH_SEL = 11.

POWER CONTROL TIMING

Device Turn-On/Off With Rising/Falling Input Voltage

Figure 4

shows the device turn-on/-off with rising/falling input voltage.

Copyright © 2010 – 2011, Texas Instruments Incorporated

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TPS65910, TPS659101, TPS659102, TPS659103

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SWCS046I – MARCH 2010 – REVISED JULY 2011

POWER CONTROL TIMING (continued)

www.ti.com

VMBCH threshold

VMBHI threshold

VMBDCH threshold

VMBLO threshold

VBNPR threshold

VCC7

VRTC

1.8V

VBACKUP > VBNPR

VIO

CLK33KOUT

NRESPWRON

t dOINT1

1.8V

t dbVMBLO

(1)

INT1

Interrupt aknowledge

VMBHI_IT=1

t dbVMBDCH

PWRHOLD

t d32KON t dONVMBHI

Switch-off sequence

t dbVMBHI t dSONT

Switch-on sequence

SWCS046-022

NOTE: (1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after the switch-on sequence. If none of these devce Power On enable conditions is set, the supplies will be turned off after t dOINT1 delay.

Figure 4. Device Turn-On/Off with Rising/Falling Input Voltage

Device State Control Through PWRON Signal

Figure 5

shows the device state control through PWRON signal.

PWRON

VIO

CLK33KOUT

1.8 V

NRESPWRON

INT1 t dOINT1

Interrupt acknowledge

PWRON_IT=1

(1)

Interrupt acknowledge

PWRON_IT=1

PWRHOLD t dbPWRHOLDF t dbPWRONF t dSONT

Switch-on sequence t dONPWHOLD t dbPWRONF

NOTE: (1) The DEV_ON control bit (set to 1) or the PWRHOLD signal (set high) can be used to maintain supplies on after switch-on sequence, If none of these device POWER ON enable condition is set the supplies will be turned off after

T dOINT1 delay.

Switch-off sequence

SWCS046-009

Figure 5. PWRON Turn-On/Turn-Off

Figure 6

shows the long-press turn-off timing characteristics.

32

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

POWER CONTROL TIMING (continued)

PWRON

VIO

NRESPWRON

INT1

PWRON_IT=1

PWRON_IT=1

PWRON_LP_IT=1

PWRHOLD t dbPWRONF t dPWRONLP t dPWRONLPTO

Switch-off sequence

NOTE: If the DEV_ON control bit is set to 1 or PWRHOLD is kept high, the device will be turned on again after PWRON long press turn-off and PWRON released.

SWCS046-010

Figure 6. PWRON Long-Press Turn-Off

Table 6

lists the power control timing characteristics.

PARAMETER

Table 6. Power Control Timing Characteristics

t d32KON

: 32-kHz Oscillator turn-on time

TEST CONDITIONS

BOOT[1:0] = 00, RC oscillator

BOOT[1:0] = 01, Quartz oscillator

BOOT[1:0] = 01, Bypass clock

MIN

t dbVMBHI

: VMBHI rising-edge debouncing delay t dbVMBDCH

: Main Battery voltage = VMBDCH threshold to INT1 falling-edge delay t dbVMBLO

: Main Battery voltage = VMBLO threshold to

NRESPWRON falling-edge delay t dbPWRONF

: PWRON falling-edge debouncing delay t dbPWRONR

: PWRON rising-edge debouncing delay t dbPWRHOLD

: PWRON rising-edge debouncing delay

3 × t

CK32k

94

=

3 × t

CK32k

94

=

3 × t

CK32k

94

=

500

3 × t

CK32k

=

94

2 × t

CK32k

63

= t dOINT

: INT1 (internal) Power-on pulse duration after PWRON low-level (debounced) event t dONPWHOLD

: delay to set high PWRHOLD signal or DEV_ON control bit after NRESPWRON released to keep on the supplies t dPWRONLP

: PWRON long-press delay to interrupt t dPWRONLPTO

: PWRON long-press delay to turn-off

PWRON falling edge to

PWON_LP_IT = 1

PWRON falling edge to

NRESPWRON falling edge

TYP

0.1

400

0.1

1

984

6

8

MAX

2000

4 × t

CK32k

= 125

4 × t

CK32k

= 125

4 × t

CK32k

= 125

550

4

× t

CK32k

= 125

3 × t

CK32k

=

94

UNIT

ms

µ s s s

µ s

µ s

µ s s ms s s

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SWCS046I – MARCH 2010 – REVISED JULY 2011

Device SLEEP State Control

Figure 7

shows the device SLEEP state control timing characteristics.

www.ti.com

SLEEP

VIO/VFBIO 1.8 V

PWM mode

SWIO

VAUX1

VDD2/VFB2

1.8 V

Active mode

3.3 V

Pulse skip mode

SW2

VDD1/VFB1

1.2 V

PWM mode

SW1 t

ACT2SLP

1.8 V

Low-power mode

1.8 V

Low-power mode

3.3 V

Low-power mode

Off t

SLP2ACT

1.8 V

PWM mode

1.8 V

Active mode

3.3 V

Pulse skip mode t dONDCDCSLP

1.2 V

PWM mode

VPLL

VDAC

VAUX2

VMMC

1.8 V

Active mode

1.8 V

Active mode

1.8 V

Active mode

3.3 V

Active mode

CLK32KOUT

Off

Off

1.8 V

Active mode

3.3 V

Low-power mode t

SLP2ACTCK32K

3.3 V

Active mode

1.8 V

Active mode

1.8 V

Active mode

1.8 V

Active mode t

ACT2SLPCK32K t dSLPONST t dSLPON1 t dSLPONST

NOTE: Registers programming: VIO_PSKIP = 0, VDD1_PSKIP = 0, VDD1_SETOFF = 1, VDAC_SETOFF = 1,

VPLL_SETOFF = 1, VAUX2_KEEPON = 1

Figure 7. Device SLEEP State Control

SWCS046-024 t

ACT2SLP

PARAMETER

t

ACT2SLP t

SLP2ACT t

SLP2ACTCK32K t dSLPON1 t dSLPONST t dSLPONDCDC

Table 7. Device SLEEP State Control Timing Characteristics

MIN TYP TEST CONDITIONS

SLEEP falling edge to supply in low power mode

(SLEEP resynchronization delay)

2 × t

CK32k

62

=

SLEEP falling edge to CLK32KOUT low 156 t

ACT2SLP

+ 3 t

CK32k

×

SLEEP rising edge to supply in high power mode

8 × t

CK32k

250

=

SLEEP rising edge to CLK32KOUT running 344

281 t

SLP2ACT

+ 3 t

CK32k

× t

SLP2ACT

+ 1 t

CK32k

× SLEEP rising edge to time step 1 of the tun-on sequence from SLEEP state turn-on sequence step duration, from SLEEP state

TSLOT_LENGTH[1:0] = 00

TSLOT_LENGTH[1:0] = 01

TSLOT_LENGTH[1:0] = 10

TSLOT_LENGTH[1:0] = 11

VDD1, VDD2 or VIO tun-on delay from tun-on sequence time step

0

200

500

2000

2 × t

CK32k

62

=

MAX

3 × t

CK32k

94

=

188

9 × t

CK32k

281

=

375

312

UNIT

µ s

µ s

µ s

µ s

µ s

µ s us

34

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

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Power Supplies State Control Through the SCLSR_EN1 and SDASR_EN2 Signals

Figure 8 and Figure 9

show the power supplies state control through the SCLSR_EN1 and SDASR_EN2 signals timing characteristics.

Switch-on sequence

Device on

Switch-off sequence

NRESPWRON

SCLSR_EN1 t dEN t dVEN t dEN

VDIG1

1.2 V

t dEN t dSOFF2

SCLSR_EN2 t dEN

VPLL

1.8 V

Low-power mode

NOTE: Register setting: VDIG1_EN1 = 1, VPLL_EN2 = 1, and VPLL_KEEPON = 1

Figure 8. LDO Type Supplies State Control Through SCLSR_EN1 and SCLSR_EN2

SWCS046-016

Switch-off sequence

NRESPWRON

SCLSR_EN2

Switch-on sequence

VDD2/VFB2 t dOEN

0 V

t dVDDEN

Device on

3.3 V

t dEN t dVDDEN t dSOFF2

SCLSR_EN1

VDD1/VFB1

1.2 V

PWM mode t dEN t dEN

Low-power mode

PFM (pulse skipping) mode

SW1

SWCS046-017

NOTE: Register setting: VDD2_EN2 = 1, VDD1_EN1 = 1, VDD1_KEEPON = 1, VDD1_PSKIP = 0, and SEL[6:0] = hex00 in

VDD2_SR_REG

Figure 9. VDD1 and VDD2 Supplies State Control Through SCLSR_EN1 and SCLSR_EN2

Table 8. Supplies State Control Though SCLSR_EN1 and SCLSR_EN2 Timing Characteristics

PARAMETER

t dEN

: NREPSWON to supply state change delay, SCLSR_EN1 or

SCLSR_EN2 driven t dEN

: SCLSR_EN1 or

SCLSR_EN2 edge to supply state change delay t dVDDEN

: SCLSR_EN1 or

SCLSR_EN2 edge to VDD1 or

VDD2 dc-dc turn on delay

TEST CONDITIONS MIN TYP

0

1 × t

CK32k

= 31

3 × t

CK32k

= 63

MAX UNIT

ms

µ s

µ s

Copyright © 2010 – 2011, Texas Instruments Incorporated

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TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

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VDD1 and VDD2 Voltage Control Through SCLSR_EN1 and SDASR_EN2 Signals

Figure 10

shows the VDD1 and VDD2 voltage control through the SCLSR_EN1 and SDASR_EN2 signals timing characteristics.

SCLSR_EN2

VDD1/VFB1 t dDVSEN

1.2 V

TSTEP[2:0]=001

TSTEP[2:0]=011 t dDVSENL

0.8 V

t dDVSEN t dDVSENL

SW1

PFM (pulse skipping) mode

PWM mode

PFM (pulse skipping) mode

PWM mode

NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG

Figure 10. VDD1 Supply Voltage Control Though SCLSR_EN1

PFM (pulse skipping) mode

SWCS046-021

Table 9. VDD1 Supply Voltage Control Through SCLSR_EN1 Timing Characteristics

TEST CONDITIONS MIN TYP MAX PARAMETER

t dDVSEN

: SCLSR_EN1 or SCLSR_EN2 edge to

VDD1 or VDD2 voltage change delay t dDVSENL

: VDD1 or VDD2 voltage settling delay

2

× t

CK32k

= 62

TSTEP[2:0] = 001

TSTEP[2:0] = 011 (default)

TSTEP[2:0] = 111

32

0.4/7.5 = 53

160

SMPS Switching Synchronization

Figure 11

shows the SMPS switching synchronization timing characteristics.

SWIO

SW1

SW2 t dviosync t dswio2sw1 t dswio2sw2

SW3 t dswio2sw3

SWCS046-025

NOTE: VDD1 or VDD2 switching synchronization is available in PWM mode (VDD1_PSKIP = 0 or VDD2_PSKIP = 0). SMPS external clock (GPIO_CKSYNC) synchronization is available when VIO PWM mode is set (VIO_PSKIP = 0).

Figure 11. SMPS Switching Synchronization

UNIT

µ s

µ s

Table 10. SMPS Switching Synchronization Timing Characteristics

PARAMETER

t dSWIO2SW1

: delay from SWIO rising edge to SW1 rising edge t dSWIO2SW2

: delay from SWIO rising edge to SW1 rising edge

TEST CONDITIONS

VDD1_PSKIP = 0,

DCDCCKSYNC[1:0] = 11

DCDCCKSYNC[1:0] = 01

VDD2_PSKIP = 0,

DCDCCKSYNC[1:0] = 11

DCDCCKSYNC[1:0] = 01

MIN TYP

160

220

160

290 t dSWIO2SW3

: delay from SWIO rising edge to SW3 rising edge

206

36

MAX UNIT

ns ns ns

Copyright © 2010 – 2011, Texas Instruments Incorporated

SDASR_EN2

SCLSR_EN1

SLEEP

PWRHOLD

PWRON

NRESPWRON

INT1

BOOT0

BOOT1

CLK32KOUT

OSC32KIN

OSC32KOUT

VREF

REFGND

TESTV

VBACKUP

VCC1

GND1

SW1

VFB1

VCC2

GND2

SW2

VFB2

VCCIO

GNDIO

SWIO

VFBIO

VCC3

VMMC

www.ti.com

NAME

VDDIO

SDA_SDI

SCL_SCK

GPIO_CKSYNC

QFN PIN

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

DEVICE INFORMATION

SUPPLIES

VDDIO/DGND

VDDIO/DGND

VDDIO/DGND

VDDIO/DGND

VDDIO/DGND

VDDIO/DGND

VDDIO/DGND

Table 11. Terminal Functions

TYPE

Power

Digital

Digital

Digital

Digital

Digital

Digital

I/O

I

I/O

I/O

I/O

I/O

I

I/O

DESCRIPTION

Digital I/Os supply

I

2

C bidirectional data signal/serial peripheral interface data input

(multiplexed)

I

2

C bidirectional clock signal/serial peripheral interface Clock Input

(multiplexed)

I

2

C SmartReflex bidirectional data signal/enable of supplies (multiplexed)

I

2

C SmartReflex bidirectional clock signal/enable of supplies (multiplexed)

Active-sleep state transition control signal

Configurable general-purpose I/O or

DC-DCs synchronization clock input signal

VRTC/DGND Digital I Switch-on/-off control signal

PU/PD

No

External PU

External PU

External PU

VBAT/DGND

VDDIO/DGND

VDDIO/DGND

VRTC/DGND

VRTC/DGND

VDDIO/DGND

VRTC/REFGND

VRTC/REFGND

VCC7/REFGND

REFGND

VCC7/AGND

VBACKUP/AGND

VCC1/GND1

VCC1/GND1

VCC1/GND1

VCC7/AGND

VCC2/GND2

VCC2/GND2

VCC2/GND2

VCC4/AGND2

VCCIO/GNDIO

VCCIO/GNDIO

VCCIO/GNDIO

VCC7/AGND

VCC3/AGND2

VCC3/REFGND

Digital

Digital

Digital

Digital

Digital

Digital

O

I/O

O

I

I

I

I

I/O

O

I

I

I

I/O

O

I

I/O

O

I

I

O

Analog

Analog

Analog

Analog

Analog

Power

Power

Power

Power

Analog

Power

Power

Power

Analog

Power

Power

Power

Analog

Power

Power

I

O

O

I

I

O

External switch-on control (ON button)

Power off reset

Interrupt flag

Power-up sequence selection

Power-up sequence selection

32-kHz clock output

32-kHz crystal oscillator

32-kHz crystal oscillator

Bandgap voltage

Reference ground

Analog test output (DFT)

Backup battery input (short to VCC5 if not used)

VDD1 dc-dc power input

VDD1 dc-dc power ground

VDD1 dc-dc switched output

VDD1 feedback voltage

VDD2 dc-dc power input

VDD2 dc-dc power ground

VDD2 dc-dc switched output

VDD2 dc-dc feedback voltage

VIO dc-dc power input

VIO dc-dc power ground

VIO dc-dc switched output

VIO feedback voltage

VMMC VAUX33 power input

LDO regulator output

No

No

No

No

PD

No

No

No

No

PD

No

No

PD

No

PD

External PU

Programmable PD

(default active)

Programmable PD

(default active)

Programmable PD

(default active)

Programmable PU

(default active)

PD active during device OFF state

No

Programmable PD

(default active)

Programmable PD

(default active)

PD disable in

ACTIVE or SLEEP state

No

No

No

No

No

Copyright © 2010 – 2011, Texas Instruments Incorporated

37

NAME

VAUX33

VCC4

VAUX1

VAUX2

VCC5

VDAC

VPLL

VRTC

VCC6

VDIG1

VDIG2

VCC7

VFB3

SW3

GND3

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

QFN PIN

Table 11. Terminal Functions (continued)

SUPPLIES

VCC3/REFGND

VCC4/AGND2

VCC4/REFGND

VCC4/REFGND

VCC5/AGND

VCC5/REFGND

VCC5/REFGND

VCC7/REFGND

VCC6/AGND2

VCC6/REFGND

VCC6/REFGND

VCC7/REFGND

VCC7/AGND

VCC7/GND3

TYPE

Power

Power

Power

Power

Power

Power

Power

Power

Power

Power

Power

Power

Analog

Power

I/O

O

O

O

O

I

O

I

O

O

I

O

I

I

O

DESCRIPTION

LDO regulator output, VDD3 internal regulated supply

VAUX1, VAUX2 power input

LDO regulator output

LDO regulator output

VDAC, VPLL power input

LDO regulator output

LDO regulator output

LDO regulator output

VDIG1, VDIG2 power input

LDO regulator output

LDO regulator output

VRTC power input, VDD3 internal and analog references supply

VDD3 feedback voltage

VDD3 dc-dc switched output

AGND Power I/O VDD3 dc-dc power ground

AGND

AGND2

DGND

Power

PAD

Power

PAD

Power

PAD

Power

PAD

AGND

AGND

DGND

Power

Power

Power

I/O

I/O

I/O

Analog ground

Analog ground

Digital ground

www.ti.com

PU/PD

PD

PD

No

No

No

No

PD

PD

No

PD

PD

No

No

No

No

No

No

No

38

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TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

PIN ASSIGNMENT (TOP VIEW)

SLEEP 37

CLK32KOUT

38

GPIO/CKSYN 39

NRESPWRON 40

VCC2

41

SW2 42

GND2

43

VFB2 44

INT1 45

VAUX1 46

VCC4

47

VAUX2

48

PowerPad

24 VPLL

23 VCC5

22 VDAC

21 OSC32KOUT

20 OSC32KIN

19 BOOT1

18 VREF

17 REFGND

16 VFBIO

15 GNDIO

14 SWIO

13 VCCIO

Figure 12. 48-QFN Top View Pin Assignment

SWCS046-004

Copyright © 2010 – 2011, Texas Instruments Incorporated

39

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

DETAILED DESCRIPTION

www.ti.com

POWER REFERENCE

The bandgap voltage reference is filtered by using an external capacitor connected across the VREF output and the analog ground REFGND (see

RECOMMENDED OPERATING CONDITIONS

, Recommended Operating

Conditions). The VREF voltage is distributed and buffered inside the device.

POWER SOURCES

The power resources provided by the TPS65910 device include inductor-based switched mode power supplies

(SMPS) and linear low drop-out voltage regulators (LDOs). These supply resources provide the required power to the external processor cores and external components, and to modules embedded in the TPS65910 device.

Two of these SMPS have DVS capability SmartReflex Class 3 compatible. These SMPS provide independent core voltage domains to the host processor. The remaining SMPS provides supply voltage for the host processor

I/Os.

Table 12

lists the power sources provided by the TPS65910 device.

RESOURCE

VIO

VDD1

VDD2

VDD3

VDIG1

VDIG2

VPLL

VDAC

VAUX1

VAUX2

VAUX33

VMMC

TYPE

SMPS

SMPS

SMPS

SMPS

LDO

LDO

LDO

LDO

LDO

LDO

LDO

LDO

Table 12. Power Sources

VOLTAGES

1.5 V / 1.8 V / 2.5 V / 3.3 V

0.6 ... 1.5 in 12.5-mV steps

Programmable multiplication factor: x2, x3

0.6 ... 1.5 in 12.5-mV steps

Programmable multiplication factor: x2, x3

5 V

1.2 V, 1.5 V, 1.8 V, 2.7 V

1 V, 1.1 V, 1.2 V, 1.8 V

1.0 V, 1.1 V, 1.8 V, 2.5 V

1.8 V, 2.6 V, 2.8 V, 2.85 V

1.8 V, 2.5 V, 2.8 V, 2.85 V

1.8 V, 2.8 V, 2.9 V, 3.3 V

1.8 V, 2.0 V, 2.8 V, 3.3 V

1.8 V, 2.8 V, 3.0 V, 3.3 V

POWER

1000 mA

1500 mA

1500 mA

100 mA

300 mA

300 mA

50 mA

150 mA

300 mA

150 mA

150 mA

300 mA

EMBEDED POWER CONTROLLER

The embedded power controller manages the state of the device and controls the power-up sequence.

STATE-MACHINE

The EPC supports the following states:

No supply: The main battery supply voltage is not high enough to power the VRTC regulator. A global reset is asserted in this case. Everything on the device is off.

Backup: The main battery supply voltage is high enough to enable the VRTC domain but not enough to switch on all the resources. In this state, the VRTC regulator is in backup mode and only the 32-K oscillator and RTC module are operating (if enabled). All other resources are off or under reset.

Off: The main battery supply voltage is high enough to start the power-up sequence but device power on is not enabled. All power supplies are in OFF state except VRTC.

Active: Device power-on enable conditions are met and regulated power supplies are on or can be enabled with full current capability.

Sleep: Device SLEEP enable conditions are met and some selected regulated power supplies are in low-power mode.

40

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Figure 13

shows the transitions of the state-machine.

NRESPWRON

INT1

Pulse generator

PWRHOLD

DEV_ON t

DOINT

PWRON

POWER ON enable

NO SUPPLY

PWRON_LP_IT t

D

THERM_TS

DEV_OFF

DEV_OFF_RST

SLEEPSIG_POL

MB and BB<VBNPR

SLEEP

DEV_SLP

INT1

SLEEP enable

MB>VMBHI

MB<VMBLO

OFF

MB and BB<VBNPR

MB>VMBHI

POWER ON disabled

Backup

MB or BB>VBNPR and

MB<VMBLO

ACTIVE

POWER ON enabled and

MB>VMBCH

MB and BB<VBNPR

POWER ON disabled

MB<VMBLO

SLEEP disabled

SLEEP enabled

MB: Main battery voltage

BB: Backup battery voltage

MB<VMBLO

SLEEP

SWCS046-011

Figure 13. Embebded Power Control State-Machine

Device power-on enable conditions:

If none of the device power-on disable conditions is met, the following conditions are available to turn on and/or maintain the ON state of the device:

• PWRON signal low level.

Or PWRHOLD signal high level.

• Or DEV_ON control bit set to 1 (default inactive).

Copyright © 2010 – 2011, Texas Instruments Incorporated

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TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

• Or interrupt flag active (default INT1 low) while the device is off (NRESPWRON = 0) generates a power-on enable condition during a fixed delay (T

TIMING

, Power Control Timing).

DOINT1 pulse duration defined in

POWER CONTROL

The power-on enable condition pulse occurs only if the interrupt status bit is initially low (no previous identical interrupt pending in the status register).

The Interrupt sources expected when the device is off are:

PWRON low-level interrupt (PWRON_IT = 1 in INT_STS_REG register)

PWRHOLD rising-edge interrupt (PWRHOLD_IT = 1 in INT_STS_REG register)

The Interrupt sources expected if enabled when the device is off are:

• RTC Alarm interrupt (RTC_ALARM_IT = 1 or RTC_PERIOD_IT = 1 in INT_STS_REG register)

• First-time input voltage rising above VMBHI threshold (Boot mode or EEPROM dependent) and input voltage > VMBCH threshold (VMBCH_IT = 1 in INT_STS_REG register).

GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE state transition), even if its associated interrupt is not masked, but can be used as an interrupt source to wake up the device from SLEEP-to-ACTIVE state.

Device power-on disable conditions:

PWRON signal low level during more than the long-press delay: t dPWRONLP

(can be disabled though register programming). The interrupt corresponding to this condtion is PWRON_LP_IT in the INT_STS_REG register.

• Or Die temperature has reached the thermal shutdown threshold.

• Or DEV_OFF or DEV_OFF_RST control bit set to 1 (value of DEV_OFF is cleared when the device is in OFF state).

Device SLEEP enable conditions:

• SLEEP signal low level (default, or high level depending on the programmed polarity)

• And DEV_SLP control bit set to 1

And interrupt flag inactive (default INT1 high): no nonmasked interrupt pending

SLEEP state can be controlled by programming DEV_SLP and keeping the SLEEP signal floating, or it can be controlled through the SLEEP signal setting DEV_SLP = 1 once after device turn-on .

SWITCH-ON/-OFF SEQUENCES

The power sequence is the automated switching on of the device resources when an off-to-active transition takes place.

The device supports three embedded power sequences selectable by the device BOOT pins.

BOOT0

0

1

0

BOOT1

0

0

1

Processor Supported

AM3517, AM3505

OMAP3 Family, AM3715/03, DM3730/25

EEPROM sequence

Details of the boot sequence timing are given in

SWITCH-ON/-OFF SEQUENCES AND TIMING . EEPROM

sequences can be used for specific power up sequence for corresponding application processor. For details of

EEPROM sequence refer to the http://focus.ti.com/docs/prod/folders/print/tps65910.html

.

user guides on the product folder:

CONTROL SIGNALS

SLEEP

When none of the device sleep-disable conditions are met, a falling edge (default, or rising edge, depending on the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge

(default, or falling edge, depending on the programmed polarity) causes a transition back to ACTIVE state. This input signal is level sensitive and no debouncing is applied.

While the device is in SLEEP state, predefined resources are automatically set in their low-power mode or off.

42

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TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Resources can be kept in their active mode: (full-load capability), programming the SLEEP_KEEP_LDO_ON and the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power resource. If the bit is set to 1, then that resource stays in active mode when the device is in SLEEP state. 32KCLKOUT is also included in the

SLEEP_KEEP_RES_ON register and the 32-kHz clock output is maintained in SLEEP state if the corresponding mask bit is set.

PWRHOLD

When none of the device power-on disable conditions are met, a rising edge of this signal causes an

OFF-to-ACTIVE state transition of the device and a falling edge causes a transition back to OFF state. Typically, this signal is used to control the device in a slave configuration. It can be connected to the SYSEN output signal from other TPS659xx devices, or the NRESPWRON signal of another TPS65910 device. This input signal is level sensitive and no debouncing is applied.

A rising edge of PWRHOLD is highlighted though an associated interrupt.

BOOT0/BOOT1

These signals determine which processor the device is working with and hence which power-up sequence is needed. See

SWITCH-ON/-OFF SEQUENCES AND TIMING

for more details. There is no debouncing on this input signal.

NRESPWRON

This signal is used as the reset to the processor. It is held low until the ACTIVE state is reached. See

POWER

CONTROL TIMING

to get detailed timing.

CLK32KOUT

This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence, depending on the Boot mode. It can be enabled and disabled by register bit, during ACTIVE state of the device.

CLK32KOUT output can also be enabled or not during SLEEP state of the device depending on the

SLEEPMASK register programming.

PWRON

A falling edge on this signal causes after t dbPWRONF debouncing delay (defined in

Figure 5

and

Table 6 ) an

OFF-to-ACTIVE state or SLEEP-to-ACTIVE state transition of the device and makes the corresponding interrupt

(PWRON_IT) active. The PWRON input is connected to an external push-button. The built-in debouncing time defines a minimum button press duration that is required for button press detection. Any button press duration which is lower than this value is ignored, considered an accidental touch.

After an OFF-to-ACTIVE state transition, the PMIC maintains ACTIVE during t dOINT delay, if the button is released. After this delay if none of the device enabling conditions is set by the processor supplied, the PMIC automatically turns off. If the button is not released, the PMIC maintains ACTIVE up to t dPWRONLPTO

, because

PWRON low is a device enabling condition. After a SLEEP-to-ACTIVE state transition, the PMIC maintains

ACTIVE as long as an interrupt is pending.

If the device is already in ACTIVE state, a PWRON low level makes the corresponding interrupt (PWRON_IT) active.

When the PMIC is in ACTIVE mode, if the button is pressed for longer time than t dPWRONLP

, the PMIC generates the PWON_LP_IT interrupt. If the processor does not acknowledge the long press interrupt within a period of t dPWRONLPTO

– t dPWRONLP

, the PMIC goes to OFF mode and shuts down the DCDCs and LDOs.

INT1

INT1 signal (default active low) warns the host processor of any event that occurred on the TPS65910 device.

The host processor can then poll the interrupt from the interrupt status register through I

2

C to identify the interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG register. The polarity of INT1 can be set by programming the IT_POL control bit.

Copyright © 2010 – 2011, Texas Instruments Incorporated

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TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Any (not masked or masked) interrupt detection causes a POWER ON enable condition during a fixed delay t

DOINT1

(only) when the device is in OFF state (when NRESPWON signal is low). Any (not masked) interrupt detection is causing a device wakeup from SLEEP state up to acknowledge of the pending interrupt. Any of the interrupt sources can be masked by programming the INT_MSK_REG register. When an interrupt is masked, its corresponding interrupt status bit is still updated, but the INT1 flag is not activated.

Interrupt source masking can be used to mask a device switch-on event. Because interrupt flag active is a

POWER ON enable condition during t

DOINT1 the device after the t

DOINT1 delay, any interrupt not masked must be cleared to allow turn off of

POWER ON enable pulse duration.. See section: Interrupts, for interrupt sources definition.

SDASR_EN2 and SCLSR_EN1

SDASR_EN2 and SCLSR_EN1 are the data and clock signals of the serial control interface (SR-I

2

C) dedicated to SmartReflex applications. These signals can also be programmed to be used as enable signals of one or several supplies, when the device is on (NRESPWRON high). A resource assigned to SDASR_EN2 or

SCLSR_EN1 control automatically disables the serial control interface.

Programming EN1_LDO_ASS_REG, EN2_LDO_REG, and SLEEP_KEEP_LDO_ON_REG registers:

SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or sleep state of any LDO type supplies.

Programming EN1_SMPS_ASS_REG, EN2_SMPS_ASS_REG, and SLEEP_KEEP_RES_ON registers:

SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or low-power state (PFM mode) of

SMPS type supplies.

SDASR_EN2 and SCLSR_EN1 can be used to set output voltage of VDD1 and VDD2 SMPS from a roof to a floor value, preprogrammed in the VDD1_OP_REG, VDD2_OP_REG, and teh VDD1_SR_REG, VDD2_SR_REG registers. Tun-off of VDD1 and VDD2 can also be programmed either in VDD1_OP_REG, VDD2_OP_REG or in

VDD1_SR_REG, VDD2_SR_REG registers.

When a supply is controlled through SCLSR_EN1 or SCLSR_EN2 signals, its state is no longer driven by the device SLEEP state.

GPIO_CKSYNC

GPIO_CKSYNC is a configurable open-drain digital I/O: directivity, debouncing delay and internal pullup can be programmed in the GPIO0_REG register. GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE state transition), even if its associated interrupt is not masked, but can be used as an interrupt source to wake up the device from SLEEP-to-ACTIVE state.

Programming DCDCCKEXT = 1, VDD1, VDD2, VIO, and VDD3 dc-dc switching can be synchronized using a

3-MHz clock set though the GPIO_CKSYNC pin.

DYNAMIC VOLTAGE FREQUENCY SCALING AND ADAPTIVE VOLTAGE SCALING OPERATION

Dynamic voltage frequency scaling (DVFS) operation: a supply voltage value corresponding to a targeted frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG registers.

The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG programmed value is limited to 12.5 mV/ µ s, fixed value. Adaptative voltage scaling (AVS) operation: a supply voltage value corresponding to a supply voltage adjustment is programmed in VDD1_SR_REG or VDD2_SR_REG registers.

The supply voltage is then intended to be tuned by the digital core supplied, based its performance self-evaluation. The slew rate of VDD1 or VDD2 voltage supply reaching a new programmed value is programmable though the VDD1_REG or VDD2_REG register, respectively.

A serial control interface (SR-I

2

C) is dedicated to SmartReflex applications such as DVFS and class 3 AVS, and thus gives access to the VDD1_OP_REG, VDD1_SR_REG, and VDD2_OP_REG, VDD2_SR_REG register.

A general-purpose serial control interface (CTL-I

2

C) also gives access to these registers, if SR_CTL_I2C_SEL control bit is set to 1 in the DEVCTRL_REG register (default inactive).

Both control interfaces are compliant with HS-I

2

C specification (100 kbps, 400 kbps, or 3.4 Mbps).

Figure 14

shows an example of a SmartReflex operation. To optimize power efficiency, the voltage domains of the host processor uses the DVFS and AVS features provided by SmartReflex.

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SWCS046I – MARCH 2010 – REVISED JULY 2011

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OPP5

OPP4

OPP3

Coarse steps (DVFS) Fine steps (AVS)

OPP Change end

OPP2

OPP Change start

OPP1

TSR TI2C TSMPS TSR TI2C TSMPS TSR TI2C TSMPS TSR TI2C TSMPS

SWCS046-012

(1) T

SR

: Time used by the SmartReflex controller

(2) T

I2C

: Time used for data transfer through the I

2

C interface

(3) T

SMPS

: Time required by the SMPS to converge to new voltage value

Figure 14. SmartReflex Operation Example

32-kHz RTC CLOCK

The TPS65910 device can provide a 32-kHz clock to the platform through the CLK32KOUT output, the source of this 32-kHz clock can be:

• 32-kHz crystal connected from OSC32IN to OSC32KOUT pins

• A square-wave 32-kHz clock signal applied to OSC32IN input (OSC32KOUT kept floating).

• Internal 32-kHz RC oscillator, to reduce the BOM, if an accurate clock is not needed by the system.

Default selection of a 32-kHz RC oscillator versus 32-kHz crystal oscillator or external square-wave 32-kHz clock depends on the Boot mode or device version (EEPROM programming):

• BOOT1 = 0, BOOT0 = 1: quartz oscillator or external square wave 32-kHz clock default

• BOOT1 = 0, BOOT0 = 0: 32-kHz RC oscillator default

Switching from the 32-kHz RC oscillator to the 32-kHz crystal oscillator or external square-wave 32-kHz clock can also be programmed though DEVCTRL_REG register, taking benefit of the shorter turn-on time of the internal RC oscillator.

Switching from the 32-kHz crystal oscillator or external square-wave clock to the RC oscillator is not supported.

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SWCS046I – MARCH 2010 – REVISED JULY 2011

VRTC

32 kHz to digital block

Biasing and amplitude control

www.ti.com

OSC32KIN REFGND OSC32KOUT

Q

Coscin

Coscout

SWCS046-013

Figure 15. Crystal Oscillator 32-kHz Clock

RTC

The RTC, which is driven by the 32-kHz clock, provides the alarm and timekeeping functions. The RTC is kept supplied when the device is in the OFF or the BACKUP state.

The main functionalities of the RTC block are:

• Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) format

• Calendar information (Day/Month/Year/Day of the week) directly in BCD code up to year 2099

• Programmable interrupts generation: The RTC can generate two interrupts: a timer interrupt

RTC_PERIOD_IT periodically (1s/1m/1h/1d period) and an alarm interrupt RTC_ALARM_IT at a precise time of the day (alarm function). These interrupts are enabled using IT_ALARM and IT_TIMER control bits.

Periodically interrupts can be masked during the SLEEP period to avoid host interruption and are automatically unmasked after SLEEP wakeup (using the IT_SLEEP_MASK_EN control bit).

• Oscillator frequency calibration and time correction

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32-kHz clock input

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

32-kHz counter

Frequency compensation

Week

Days

Control

Seconds Minutes Hours

Days

Months Years

Interrupt

Alarm

Figure 16. RTC Digital Section Block Diagram

NOTE

INT_ALARM can generate a wakeup of the platform.

INT_TIMER cannot generate a wakeup of the platform.

INT_ALARM

INT_TIMER

SWCS046-014

TIME CALENDAR REGISTERS

All the time and calendar information are available in these dedicated registers, called TC registers. Values of the

TC registers are written in BCD format.

1. Year data ranges from 00 to 99

– Leap year = Year divisible by four (2000, 2004, 2008, 2012...)

Common year = other years

2. Month data ranges from 01 to 12

3. Day value ranges from:

1 to 31 when months are 1, 3, 5, 7, 8, 10, 12

– 1 to 30 when months are 4, 6, 9, 11

– 1 to 29 when month is 2 and year is a leap year

– 1 to 28 when month is 2 and year is a common year

4. Week value ranges from 0 to 6

5. Hour value ranges from 00 to 23 in 24-hour mode and ranges from 1 to 12 in AM/PM mode

6. Minutes value ranges from 0 to 59

7. Seconds value ranges from 0 to 59

To modify the current time, software writes the new time into TC registers to fix the time/calendar information.

The DBB can write into TC registers without stopping the RTC. In addition, software can stop the RTC by clearing the STOP_RTC bit of the control register and check the RUN bit of the status to be sure that the RTC is frozen. Then update TC values, and then restart the RTC by setting the STOP_RTC bit.

Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5, previous register values are:

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TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

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Register

SECONDS_REG

MINUTES_REG

HOURS_REG

DAYS_REG

MONTHS_REG

YEARS_REG

Value

0x36

0x54

0x90

0x05

0x09

0x08

The user can round to the closest minute, by setting the ROUND_30S register bit. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is performed.

Example:

• If current time is 10H59M45S, a round operation changes time to 11H00M00S.

• if current time is 10H59M29S, a round operation changes time to 10H59M00S.

GENERAL REGISTERS

Software can access the RTC_STATUS_REG and RTC_CTRL_REG registers at any time (except for the

RTC_CTRL_REG[5] bit, which must be changed only when the RTC is stopped).

COMPENSATION REGISTERS

The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers must respect the available access period.

These registers must be updated before each compensation process. For example, software can load the compensation value into these registers after each hour event, during an available access period.

4

Hours

Seconds

3

58 59 0 1 2

6

58 59 0 1 2

Compensation event

Hours

Seconds

3

59 0

4

1

Compensation event swcs046-015

Figure 17. RTC Compensation Scheduling

This drift can be balanced to compensate for any inaccuracy of the 32-kHz oscillator. Software must calibrate the oscillator frequency, calculate the drift compensation versus one time hour period; and then load the

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compensation registers with the drift compensation value. Indeed, if the AUTO_COMP_EN bit in the

RTC_CTRL_REG is enabled, the value of COMP_REG (in twos-complement) is added to the RTC 32-kHz counter at each hour and one second. When COMP_REG is added to the RTC 32-kHz counter, the duration of the current second becomes (32768 - COMP_REG)/32768s; so, the RTC can be compensated with a 1/32768 s/hour time unit accuracy.

NOTE

The compensation is considered once written into the registers.

BACKUP BATTERY MANAGEMENT

The device includes a back-up battery switch connecting the VRTC regulator input to a main battery (VCC7) or to a back-up battery (VBACKUP), depending on the batteries voltage value.

The VRTC supply can then be maintained during a BACKUP state as far as the input voltage is high enough

( > VBNPR threshold). Below the VBNPR voltage threshold the digital core of the device is set under reset by internal signal POR (PowerOnReset).

The back-up domain functions which are always supplied from VRTC comprehend:

• The internal 32-kHz oscillator

• Backup registers

The back-up battery can be charged from the main battery through an embedded charger. The back-up battery charge voltage and enable is controlled through BBCH_REG register programming. This register content is maintained during the device Backup state.

Hence enabled the back-up battery charge is maintained as far as the main battery voltage is higher than the

VMBLO threshold and the back-up battery voltage.

BACKUP REGISTERS

As part of the RTC the device contains five 8-bit registers which can be used for storage by the application firmware when the external host is powered down. These registers retain their content as long as the VRTC is active.

I

2

C INTERFACE

A general-purpose serial control interface (CTL-I

2

C) allows read and write access to the configuration registers of all resources of the system.

A second serial control interface (SR-I

2

C) is dedicated to SmartReflex applications such as DVFS or AVS.

Both control interfaces are compliant with HS-I

2

C specification.

These interfaces support the standard slave mode (100 Kbps), Fast mode (400 Kbps), and high-speed mode

(3.4 Mbps). The general-purpose I

2

C module using one slave hard-coded addresse (ID1 = 2Dh). The

SmartReflex I

2

C module uses one slave hard-coded address (ID0 = 12h). The master mode is not supported.

Addressing: Seven-bit mode addressing device

They do not support the following features:

• 10-bit addressing

• General call

THERMAL MONITORING AND SHUTDOWN

A thermal protection module monitors the junction temperature of the device versus two thesholds:

• Hot-die temperature threshold

• Thermal shutdown temperature theshold

When the hot-die temperature threshold is reached an interrupt is sent to software to close the noncritical running tasks.

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www.ti.com

When the thermal shutdown temperature theshold is reached, the TPS65910 device is set under reset and a transition to OFF state is initiated. Then the power-on enable conditions of the device is not considered until the die temperature has decreased below the hot-die threshold. An hysteresis is applied to the hot-die and shutdown threshold, when detecting a falling edge of temperature, and both detection are debounced to avoid any parasitic detection. The TPS65910 device allows programming of four hot-die temperature thresholds to increase the flexibility of the system.

By default, the thermal protection is enabled in ACTIVE state, but can be disabled through programming register

THERM_REG.

The thermal protection can be enabled in SLEEP state programming register

SLEEP_KEEP_RES_ON. The thermal protection is automatically enabled during an OFF-to-ACTIVE state transition and is kept enabled in OFF state after a switch-off sequence caused by a thermal shutdown event.

Transition to OFF state sequence caused by a thermal shutdown event is highlighted in the INT_STS_REG status register. Recovery from this OFF state is initiated (switch-on sequence) when the die temperature falls below the hot-die temperature threshold.

Hot-die and thermal shutdown temperature threshold detections state can be monitored or masked by reading or programming the THERM_REG register. Hot-die interrupt can be masked by programming the INT_MSK_REG register.

INTERRUPTS

Interrupt

RTC_ALARM_IT

RTC_PERIOD_IT

HOT_DIE_IT

PWRHOLD_IT

PWRON_LP_IT

PWRON_IT

VMBHI_IT

VMBDCH_IT

GPIO0_R_IT

GPIO0_F_IT

Table 13. Interrupt Sources

Description

RTC alarm event: Occurs at programmed determinate date and time

(running in ACTIVE, OFF, and SLEEP state, default inactive)

RTC periodic event: Occurs at programmed regular period of time (every second or minute)

(running in ACTIVE, OFF, and SLEEP state, default inactive)

The embedded thermal monitoring module has detected a die temperature above the hot-die detection threshold (running in ACTIVE and SLEEP state)

Level sensitive interrupt.

PWRHOLD signal rising edge

PWRON is low during more than the long-press delay: t dPWRONLP register programming).

(can be disable though

PWRON is low while the device is on (running in ACTIVE and SLEEP state) or PWON was low while the device was off (causing a device turn-on). Level-sensitive interrupt

The battery voltage rise above the VMBHI threshold: NOSUPPLY to Off or Backup-to-Off device states transition (first battery plug or battery voltage bounce detection). This interrupt source can be disabled through EEPROM programming (VMBHI_IT_DIS). Edge-sensitive interrupt

The battery voltage falls down below the VMBDCH threshold(running in ACTIVE and SLEEP state, if enabled programming VMBCH_VSEL). Edge-sensitive interrupt

GPIO_CKSYNC rising-edge detection (available in ACTIVE and SLEEP state)

GPIO_CKSYNC falling-edge detection (available in ACTIVE and SLEEP state)

INT1 signal (active low) warns the host processor of any event that occurred on the TPS65910 device. The host processor can then poll the interrupt from the interrupt status register via I

2

C to identify the interrupt source. Each interrupt source can be individually masked via the interrupt mask register.

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SWCS046I – MARCH 2010 – REVISED JULY 2011

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PACKAGE DESCRIPTION

The following are the package descriptions of the TPS65910 PMU devices:

• Package type:

Package

Type

Size (mm)

Substrate layers

Pitch ball array (mm)

ViP (via-in-pad)

Number of balls

Thickness (mm) (max. height including balls)

Others

• Moisture sensitivity level target: JEDEC MSL3 @ 260 ° C

APPENDIX A: FUNCTIONAL REGISTERS

TPS65910

RSL QFN-N48

6x6

1 layer

0.4 mm

No

48

1

Green, ROHS-compliant

Register Name

SECONDS_REG

MINUTES_REG

HOURS_REG

DAYS_REG

MONTHS_REG

YEARS_REG

WEEKS_REG

ALARM_SECONDS_REG

ALARM_MINUTES_REG

ALARM_HOURS_REG

ALARM_DAYS_REG

ALARM_MONTHS_REG

ALARM_YEARS_REG

RTC_CTRL_REG

RTC_STATUS_REG

RTC_INTERRUPTS_REG

RTC_COMP_LSB_REG

RTC_COMP_MSB_REG

RTC_RES_PROG_REG

RTC_RESET_STATUS_REG

BCK1_REG

BCK2_REG

BCK3_REG

BCK4_REG

BCK5_REG

PUADEN_REG

REF_REG

VRTC_REG

VIO_REG

TPS65910_FUNC_REG REGISTERS MAPPING SUMMARY

Table 14. TPS65910_FUNC_REG Register Summary

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Type

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Register Width (Bits)

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

0x00

0x00

0x27

0x00

0x00

0x01

0x00

0x00

0x80

0x00

Register Reset

0x00

0x00

0x00

0x01

0x01

0x00

0x00

0x00

0x00

0x00

0x01

0x00

0x00

0x00

0x00

0x9F

0x01

0x01

0x00

Address Offset

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x08

0x09

0x0A

0x0B

0x13

0x14

0x15

0x16

0x17

0x0C

0x0D

0x10

0x11

0x12

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x20

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SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 14. TPS65910_FUNC_REG Register Summary (continued)

Register Name

VDD1_REG

VDD1_OP_REG

VDD1_SR_REG

VDD2_REG

VDD2_OP_REG

VDD2_SR_REG

VDD3_REG

VDIG1_REG

VDIG2_REG

VAUX1_REG

VAUX2_REG

VAUX33_REG

VMMC_REG

VPLL_REG

VDAC_REG

THERM_REG

BBCH_REG

DCDCCTRL_REG

DEVCTRL_REG

DEVCTRL2_REG

SLEEP_KEEP_LDO_ON_REG

SLEEP_KEEP_RES_ON_REG

SLEEP_SET_LDO_OFF_REG

SLEEP_SET_RES_OFF_REG

EN1_LDO_ASS_REG

EN1_SMPS_ASS_REG

EN2_LDO_ASS_REG

EN2_SMPS_ASS_REG

RESERVED

RESERVED

INT_STS_REG

INT_MSK_REG

INT_STS2_REG

INT_MSK2_REG

GPIO0_REG

JTAGVERNUM_REG

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Register Width (Bits)

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RO

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

Type

RW

RW

RW

RW

RW

RW

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x02

0x00

0x00

0x0A

0x00

0x00

0x00

0x00

0x00

0x0D

0x00

0x3B

0x40

0x34

0x00

Register Reset

0x0C

0x00

0x00

0x04

0x00

0x00

0x04

0x00

0x00

0x00

0x00

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0x47

0x48

0x49

0x4A

0x50

0x42

0x43

0x44

0x45

0x46

0x51

0x52

0x53

0x60

0x80

0x39

0x3E

0x3F

0x40

0x41

0x34

0x35

0x36

0x37

0x38

Address Offset

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x30

0x31

0x32

0x33

TPS65910_FUNC_REG REGISTER DESCRIPTIONS

Table 15. SECONDS_REG

Address Offset

Physical Address

Description

Type

0x00

RTC register for seconds

RW

Instance

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7

Reserved

Bits

7

Field Name

Reserved

6

6:4

3:0

SEC1

SEC0

Address Offset

Physical Address

Description

Type

7

Reserved

Bits

7

Field Name

Reserved

6

6:4

3:0

MIN1

MIN0

Address Offset

Physical Address

Description

Type

7

PM_NAM

6

Reserved

Bits

7

Field Name

PM_NAM

6 Reserved

Second digit of minutes (range is 0 up to 5)

First digit of minutes (range is 0 up to 9)

Table 17. HOURS_REG

0x02

RTC register for hours

RW

Instance

5 4 3

HOUR1

Description

Only used in PM_AM mode (otherwise it is set to 0)

0 is AM

1 is PM

Reserved bit

5:4

3:0

HOUR1

HOUR0

Address Offset

Physical Address

Description

Type

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

5

SEC1

4 3 2

SEC0

1 0

Description

Reserved bit

Type

RO

R returns

0s

RW

RW

Reset

0

0x0

0x0

Second digit of seconds (range is 0 up to 5)

First digit of seconds (range is 0 up to 9)

Table 16. MINUTES_REG

0x01

Instance

RTC register for minutes

RW

5

MIN1

Description

Reserved bit

4 3 2

MIN0

1

Type

RO

R returns

0s

RW

RW

0

Reset

0

0x0

0x0

Second digit of hours(range is 0 up to 2)

First digit of hours (range is 0 up to 9)

Table 18. DAYS_REG

0x03

Instance

RTC register for days

RW

2

HOUR0

1

Type

RW

RO

R returns

0s

RW

RW

0

Reset

0

0

0x0

0x0

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SWCS046I – MARCH 2010 – REVISED JULY 2011

7 6 5 4 3 2

Reserved DAY1 DAY0

Bits

7:6

Field Name

Reserved

Description

Reserved bit

5:4

3:0

DAY1

DAY0

Address Offset

Physical Address

Description

Type

Second digit of days (range is 0 up to 3)

First digit of days (range is 0 up to 9)

Table 19. MONTHS_REG

0x04

Instance

RTC register for months

RW

1

Type

RO

R returns

0s

RW

RW

7 6

Reserved

Bits

7:5

Field Name

Reserved

5

Description

Reserved bit

4

MONTH1

3 2

MONTH0

1

Type

RO

R returns

0s

RW

RW

4

3:0

MONTH1

MONTH0

Address Offset

Physical Address

Description

Type

Second digit of months (range is 0 up to 1)

First digit of months (range is 0 up to 9)

Table 20. YEARS_REG

0x05

RTC register for day of the week

RW

Instance

7

Bits

7:4

3:0

Field Name

YEAR1

YEAR0

Address Offset

Physical Address

Description

Type

6 5 4 3

YEAR1

Description

Second digit of years (range is 0 up to 9)

First digit of years (range is 0 up to 9)

Table 21. WEEKS_REG

0x06

RTC register for day of the week

RW

Instance

7 6 5

Reserved

4 3

2

2

YEAR0

1

Type

RW

RW

1

WEEK

www.ti.com

0

Reset

0x0

0x0

0x1

0

Reset

0x0

0

0x1

0

Reset

0x0

0x0

0

54

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

Bits

7:3

Field Name

Reserved

2:0 WEEK

Address Offset

Physical Address

Description

Type

7

Reserved

Bits

7

Field Name

Reserved

6

6:4

3:0

ALARM_SEC1

ALARM_SEC0

Address Offset

Physical Address

Description

Type

7

Reserved

Bits

7

Field Name

Reserved

6

6:4

3:0

ALARM_MIN1

ALARM_MIN0

Address Offset

Physical Address

Description

Type

7 6

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Description

Reserved bit

First digit of day of the week (range is 0 up to 6)

Type

RO

R returns

0s

RW

Reset

0x00

0

Table 22. ALARM_SECONDS_REG

0x08

Instance

RTC register for alarm programmation for seconds

RW

5

ALARM_SEC1

4 3 2

ALARM_SEC0

1 0

Reset

0

Description

Reserved bit

Second digit of alarm programmation for seconds (range is 0 up to 5)

First digit of alarm programmation for seconds (range is 0 up to 9)

Table 23. ALARM_MINUTES_REG

0x09

Instance

RTC register for alarm programmation for minutes

RW

5

ALARM_MIN1

4 3 2

ALARM_MIN0

1

Type

RO

R returns

0s

RW

RW

Description

Reserved bit

Type

RO

R returns

0s

RW

RW

Second digit of alarm programmation for minutes (range is 0 up to 5)

First digit of alarm programmation for minutes (range is 0 up to 9)

Table 24. ALARM_HOURS_REG

0x0A

Instance

RTC register for alarm programmation for hours

RW

5 4 3 2 1

0x0

0x0

0

Reset

0

0x0

0x0

0

Reserved ALARM_HOUR1 ALARM_HOUR0

Copyright © 2010 – 2011, Texas Instruments Incorporated

55

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

7

6

Field Name

ALARM_PM_NAM

Reserved

Description

Only used in PM_AM mode for alarm programmation (otherwise it is set to 0)

0 is AM

1 is PM

Reserved bit

5:4

3:0

ALARM_HOUR1

ALARM_HOUR0

Second digit of alarm programmation for hours(range is 0 up to 2)

First digitof alarm programmation for hours (range is 0 up to 9)

Type

RW

RO

R returns

0s

RW

RW

Address Offset

Physical Address

Description

Type

7

Reserved

6

Table 25. ALARM_DAYS_REG

0x0B

Instance

RTC register for alarm programmation for days

RW

5

ALARM_DAY1

4 3 2

ALARM_DAY0

1

Bits

7:6

5:4

3:0

Field Name

Reserved

ALARM_DAY1

ALARM_DAY0

Address Offset

Physical Address

Description

Type

7 6

Description

Reserved bit

Second digit of alarm programmation for days (range is 0 up to 3)

First digit of alarm programmation for days (range is 0 up to 9)

Table 26. ALARM_MONTHS_REG

0x0C

Instance

RTC register for alarm programmation for months

RW

5 4 3 2

Type

RO

R Special

RW

RW

1

www.ti.com

Reset

0

0

0x0

0x0

0

Reset

0x0

0x0

0x1

0

Reserved ALARM_MONTH0

Bits

7:5

Field Name

Reserved

Description

Reserved bit

4

3:0

ALARM_MONTH1

ALARM_MONTH0

Address Offset

Physical Address

Description

Type

Second digit of alarm programmation for months (range is 0 up to 1)

First digit of alarm programmation for months (range is 0 up to 9)

Table 27. ALARM_YEARS_REG

0x0D

Instance

RTC register for alarm programmation for years

RW

56

Type

RO

R returns

0s

RW

RW

Reset

0x0

0

0x1

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

7

Bits

7:4

3:0

Field Name

ALARM_YEAR1

ALARM_YEAR0

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

6

ALARM_YEAR1

5 4 3 2

ALARM_YEAR0

1 0

Address Offset

Physical Address

Description

Type

Description

Second digit of alarm programmation for years (range is 0 up to 9)

First digit of alarm programmation for years (range is 0 up to 9)

Type

RW

RW

Table 28. RTC_CTRL_REG

0x10

Instance

RTC control register:

NOTES: A dummy read of this register is necessary before each I

2

C read in order to update the

ROUND_30S bit value.

RW

Reset

0x0

0x0

7 6 5 4 3 2 1 0

RTC_V_OPT GET_TIME TEST_MODE MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC

Bits

7

6

5

4

3

2

1

0

Field Name

RTC_V_OPT

GET_TIME

Description

RTC date / time register selection:

0: Read access directly to dynamic registers (SECONDS_REG,

MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG,

YEAR_REG, WEEKS_REG)

1: Read access to static shadowed registers: (see GET_TIME bit).

When writing a 1 into this register, the content of the dynamic registers

(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG,

MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into static shadowed registers. Each update of the shadowed registers needs to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then re-write it to 1)

SET_32_COUNTER 0: No action

1: set the 32-kHz counter with COMP_REG value.

It must only be used when the RTC is frozen.

TEST_MODE 0: functional mode

1: test mode (Auto compensation is enable when the 32kHz counter reaches at its end)

MODE_12_24

AUTO_COMP

ROUND_30S

STOP_RTC

0: 24 hours mode

1: 12 hours mode (PM-AM mode)

It is possible to switch between the two modes at any time without disturbed the RTC, read or write are always performed with the current mode.

0: No auto compensation

1: Auto compensation enabled

0: No update

1: When a one is written, the time is rounded to the closest minute.

This bit is a toggle bit, the micro-controller can only write one and RTC clears it. If the micro-controller sets the ROUND_30S bit and then read it, the micro-controller will read one until the rounded to the closet.

0: RTC is frozen

1: RTC is running

Type

RW

RW

RW

RW

RW

RW

RW

RW

Reset

0

0

0

0

0

0

0

0

Copyright © 2010 – 2011, Texas Instruments Incorporated

57

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Address Offset

Physical Address

Description

Type www.ti.com

Table 29. RTC_STATUS_REG

0x11

Instance

RTC status register:

NOTES: A dummy read of this register is necessary before each I

2

C read in order to update the status register value.

RW

3

2

5

4

1

7

POWER_UP

6

ALARM

Bits

7

6

Field Name

POWER_UP

ALARM

0

EVENT_1D

EVENT_1H

EVENT_1M

EVENT_1S

RUN

Reserved

Address Offset

Physical Address

Description

Type

7 6

5

EVENT_1D

4

EVENT_1H

3

EVENT_1M

2

EVENT_1S

1

RUN

Description

Indicates that a reset occurred (bit cleared to 0 by writing 1).

POWER_UP is set by a reset, is cleared by writing one in this bit.

Indicates that an alarm interrupt has been generated (bit clear by writing

1).

The alarm interrupt keeps its low level, until the micro-controller write 1 in the ALARM bit of the RTC_STATUS_REG register.

The timer interrupt is a low-level pulse (15 µ s duration).

One day has occurred

One hour has occurred

One minute has occurred

One second has occurred

0: RTC is frozen

1: RTC is running

This bit shows the real state of the RTC, indeed because of STOP_RTC signal was resynchronized on 32-kHz clock, the action of this bit is delayed.

Reserved bit

Type

RW

RW

RO

RO

RO

RO

RO

RO

R returns

0s

Table 30. RTC_INTERRUPTS_REG

0x12

Instance

RTC interrupt control register

RW

5 4 3 2 1

0

0

0

0

0

0

Reserved

Reset

1

0

0

0

Reserved IT_ALARM IT_TIMER EVERY

58

Bits

7:5

4

Field Name

Reserved

Description

Reserved bit

IT_SLEEP_MASK_E 1: Mask periodic interrupt while the TPS65910 device is in SLEEP mode.

N Interrupt event is back up in a register and occurred as soon as the

TPS65910 device is no more in SLEEP mode.

0: Normal mode, no interrupt masked

Type

RO

R returns

0s

RW

Reset

0x0

0

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

Bits

3

Field Name

IT_ALARM

2 IT_TIMER

1:0 EVERY

Address Offset

Physical Address

Description

Type

7

Bits

7:0

Field Name

RTC_COMP_LSB

Address Offset

Physical Address

Description

Type

7

6

6

Bits

7:0

Field Name

RTC_COMP_MSB

Address Offset

Physical Address

Description

Type

7

Reserved

6

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Type

RW

Reset

0

Description

Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers

Enable periodic interrupt

0: interrupt disabled

1: interrupt enabled

Interrupt period

00: every second

01: every minute

10: every hour

11: every day

RW

RW

0

0x0

Table 31. RTC_COMP_LSB_REG

0x13

Instance

RTC compensation register (LSB)

Notes: This register must be written in 2-complement.

This means that to add one 32kHz oscillator period every hour, micro-controller needs to write FFFF into

RTC_COMP_MSB_REG

&

RTC_COMP_LSB_REG.

To remove one 32-kHz oscillator period every hour, micro-controller needs to write 0001 into

RTC_COMP_MSB_REG

&

RTC_COMP_LSB_REG.

The 7FFF value is forbidden.

RW

1 0 5 4 3

RTC_COMP_LSB

2

Description

This register contains the number of 32-kHz periods to be added into the

32-kHz counter every hour [LSB]

Table 32. RTC_COMP_MSB_REG

0x14

Instance

RTC compensation register (MSB)

Notes: See RTC_COMP_LSB_REG Notes.

RW

5 4 3

RTC_COMP_MSB

2

Description

This register contains the number of 32-kHz periods to be added into the

32-kHz counter every hour [MSB]

Table 33. RTC_RES_PROG_REG

0x15

Instance

RTC register containing oscillator resistance value

RW

5 4 3

SW_RES_PROG

2

Type

RW

1

Type

RW

1

Reset

0x00

0

Reset

0x00

0

Copyright © 2010 – 2011, Texas Instruments Incorporated

59

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

7:6

Field Name

Reserved

Description

Reserved bit

5:0 SW_RES_PROG

Address Offset

Physical Address

Description

Type

7 6

Value of the oscillator resistance

Table 34. RTC_RESET_STATUS_REG

0x16

Instance

RTC register for reset status

RW

5 4 3 2

Reserved

Type

RO

R returns

0s

RW

www.ti.com

Reset

0x0

0x27

1 0

Bits

7:6

Field Name

Reserved

5:0 RESET_STATUS

Address Offset

Physical Address

Description

Type

7 6

Bits

7:0

Field Name

BCKUP

Address Offset

Physical Address

Description

Type

7 6

Bits

7:0

Field Name

BCKUP

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

0x27

Table 35. BCK1_REG

0x17

Instance

Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.

RW

5 4 3 2 1 0

BCKUP

Description

Backup bit

Type

RW

Reset

0x00

Table 36. BCK2_REG

0x18

Instance

Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.

RW

5 4 3 2 1 0

BCKUP

Description

Backup bit

Type

RW

Reset

0x00

60

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

Address Offset

Physical Address

Description

Type

7

Bits

7:0

Field Name

BCKUP

Address Offset

Physical Address

Description

Type

7

Bits

7:0

Field Name

BCKUP

Address Offset

Physical Address

Description

Type

7

Bits

7:0

Field Name

BCKUP

6

6

6

Address Offset

Physical Address

Description

Type

7

RESERVED

6

I2CCTLP

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 37. BCK3_REG

0x19

Instance

Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.

RW

5 4 3 2 1 0

BCKUP

Description

Backup bit

Type

RW

Reset

0x00

Table 38. BCK4_REG

0x1A

Instance

Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.

RW

5 4 3 2 1 0

BCKUP

Description

Backup bit

Type

RW

Reset

0x00

Table 39. BCK5_REG

0x1B

Instance

Backup register which can be used for storage by the application firmware when the external host is powered down. These registers will retain their content as long as the VRTC is active.

RW

5 4 3 2 1 0

BCKUP

Type

RW

Reset

0x00

Description

Backup bit

Table 40. PUADEN_REG

0x1C

Pull-up/pull-down control register.

RW

Instance

5

I2CSRP

4

PWRONP

3

SLEEPP

2

PWRHOLDP

1

BOOT1P

0

BOOT0P

Copyright © 2010 – 2011, Texas Instruments Incorporated

61

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

7

6

5

4

3

2

1

0

Field Name

RESERVED

I2CCTLP

I2CSRP

PWRONP

SLEEPP

PWRHOLDP

BOOT1P

BOOT0P

Description

Reserved bit

SDACTL and SCLCTL pull-up control:

1: Pull-up is enabled

0: Pull-up is disabled

SDASR and SCLSR pull-up control:

1: Pull-up is enabled

0: Pull-up is disabled

PWRON pad pull-up control:

1: Pull-up is enabled

0: Pull-up is disabled

SLEEP pad pull-down control:

1: Pull-down is enabled

0: Pull-down is disabled

PWRHOLD pad pull-down control:

1: Pull-down is enabled

0: Pull-down is disabled

BOOT1 pad control:

1: Pull-down is enabled

0: Pull-down is disabled

BOOT0 pad control:

1: Pull-down is enabled

0: Pull-down is disabled

Table 41. REF_REG

Address Offset

Physical Address

Description

Type

0x1D

Reference control register

RW

Instance

7

Bits

7:4

Field Name

Reserved

6

Reserved

5

Description

Reserved bit

4 3

VMBCH_SEL

2

3:2 VMBCH_SEL

1:0 ST

Address Offset

Physical Address

Description

Type

Type

RW

RW

RW

RW

RW

RW

RW

RW

www.ti.com

Reset

1

0

0

1

1

1

1

1

Main Battery comparator VMBCH programmable threshold (EEPROM bits):

VMBCH_SEL[1:0] = 00 : bypass

VMBCH_SEL[1:0] = 01 : VMBCH = 2.8 V

VMBCH_SEL[1:0] = 10 : VMBCH = 2.9 V

VMBCH_SEL[1:0] = 11 : VMBCH = 3.0 V

Reference state:

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Reserved

ST[1:0] = 11 : On low power (SLEEP)

(Write access available in test mode only)

Table 42. VRTC_REG

0x1E

Instance

VRTC internal regulator control register

RW

1

Type

RO

R returns

0s

RW

ST

0

Reset

0x0

0x0

RO 0x1

62

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

7 6

Reserved

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

5 4 3 2 1 0

Reserved ST

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3 VRTC_OFFMASK VRTC internal regulator off mask signal: when 1, the regulator keeps its full-load capability during device OFF state.

when 0, the regulator will enter in low-power mode during device OFF state.(EEPROM bit)

Reserved bit

0

2 Reserved

1:0 ST

RO

R returns

0s

RO

0

Address Offset

Physical Address

Description

Type

7

ILMAX

6

Reference state:

ST[1:0] = 00 : Reserved

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Reserved

ST[1:0] = 11 : On low power (SLEEP)

(Write access available in test mode only)

Table 43. VIO_REG

0x20

Instance

VIO control register

RW

5

Reserved

4 3

SEL

2 1

0x1

0

ST

Bits

7:6

Field Name

ILMAX

Description

Select maximum load current: when 00: 0.5 A when 01: 1.0 A when 10: 1.0 A when 11: 1.0 A

Reserved bit

Type

RW

Reset

0x0

5:4 Reserved RO

R returns

0s

RW

0x0

3:2

1:0

SEL

ST

Output voltage selection (EEPROM bits):

SEL[1:0] = 00 : 1.5 V

SEL[1:0] = 01 : 1.8 V

SEL[1:0] = 10 : 2.5 V

SEL[1:0] = 11 : 3.3 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

(Write access available in test mode only)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Copyright © 2010 – 2011, Texas Instruments Incorporated

63

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 44. VDD1_REG

Address Offset

Physical Address

Description

Type

0x21

VDD1 control register

RW

Instance

7

VGAIN_SEL

6

Bits

7:6

Field Name

VGAIN_SEL

5:4 ILMAX

3:2 TSTEP

1:0 ST

Address Offset

Physical Address

Description

Type

7

CMD

6

www.ti.com

5

ILMAX

4 3

TSTEP

3

SEL

2 1

ST

0

Description

Select output voltage multiplication factor: G (EEPROM bits): when 00: x1 when 01: x1 when 10: x2 when 11: x3

Select maximum load current: when 0: 1.0 A when 1: 1.5 A

Time step: when changing the output voltage, the new value is reached through successive 12.5 mV voltage steps (if not bypassed). The equivalent programmable slew rate of the output voltage is then:

TSTEP[2:0] = 000 : step duration is 0, step function is bypassed

TSTEP[2:0] = 001 : 12.5 mV/ µ s (sampling 3 Mhz)

TSTEP[2:0] = 010 : 9.4 mV/ µ s (sampling 3 Mhz × 3/4)

TSTEP[2:0] = 011 : 7.5 mV/ µ s (sampling 3 Mhz × 3/5) (default)

TSTEP[2:0] = 100 : 6.25 mV/ µ s(sampling 3 Mhz/2)

TSTEP[2:0] = 101 : 4.7 mV/ µ s(sampling 3 Mhz/3)

TSTEP[2:0] = 110 : 3.12 mV/ µ s(sampling 3 Mhz/4)

TSTEP[2:0] = 111 : 2.5 mV/ µ s(sampling 3 Mhz/5)

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On, high power mode

ST[1:0] = 10 : Off

ST[1:0] = 11 : On, low power mode

Type

RW

RW

RW

RW

Table 45. VDD1_OP_REG

0x22

Instance

VDD1 voltage selection register.

This register can be accessed by both control and smartreflex I

2

C interfaces depending on

SR_CTL_I2C_SEL register bit value.

RW

Reset

0x0

0

0x3

0x0

5 4 2 1 0

64

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Bits

7

6:0

Field Name

CMD

SEL

Description

Smart-Reflex command: when 0: VDD1_OP_REG voltage is applied when 1: VDD1_SR_REG voltage is applied

Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,

12.5 mV per LSB):

SEL[6:0] = 1001011 to 1111111 : 1.5 V

...

SEL[6:0] = 0111111 : 1.35 V

...

SEL[6:0] = 0110011 : 1.2 V

...

SEL[6:0] = 0000001 to 0000011 : 0.6 V

SEL[6:0] = 0000000 : Off (0.0 V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout = (SEL[6:0] × 12.5 mV + 0.5625 mV) × G

Type

RW

RW

Reset

0

See

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Address Offset

Physical Address

Description

Type

Table 46. VDD1_SR_REG

0x23

Instance

VDD1 voltage selection register for smartreflex.

This register can be accessed by both control and smartreflex I

2

C interfaces depending on

SR_CTL_I2C_SEL register bit value.

RW

7

Reserved

6 5 4 3

SEL

2 1 0

Bits

7

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0

6:0 SEL Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,

12.5 mV per LSB):

SEL[6:0] = 1001011 to 1111111 : 1.5V

...

SEL[6:0] = 0111111 : 1.35V

...

SEL[6:0] = 0110011 : 1.2V

...

SEL[6:0] = 0000001 to 0000011 : 0.6V

SEL[6:0] = 0000000 : Off (0.0V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout = (SEL[6:0]

×

12.5 mV + 0.5625 mV)

×

G

See

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 47. VDD2_REG

Address Offset

Physical Address

Description

Type

0x24

VDD2 control register

RW

Instance

7

VGAIN_SEL

6 5

ILMAX

4 3

TSTEP

2 1

ST

0

Copyright © 2010 – 2011, Texas Instruments Incorporated

65

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

7:6

Field Name

VGAIN_SEL

5:4

3:2

1:0

ILMAX

TSTEP

ST

Description

Select output voltage multiplication factor: G (EEPROM bits): when 00: x1 when 01: x1 when 10: x2 when 11: x3

Select maximum load current: when 0: 1.0 A when 1: 1.5 A

Time step: when changing the output voltage, the new value is reached through successive 12.5 mV voltage steps (if not bypassed). The equivalent programmable slew rate of the output voltage is then:

TSTEP[2:0] = 000: step duration is 0, step function is bypassed

TSTEP[2:0] = 001: 12.5 mV/ µ s (sampling 3 Mhz)

TSTEP[2:0] = 010: 9.4 mV/ µ s (sampling 3 Mhz × 3/4)

TSTEP[2:0] = 011: 7.5 mV/ µ s (sampling 3 Mhz × 3/5) (default)

TSTEP[2:0] = 100: 6.25 mV/ µ s(sampling 3 Mhz/2)

TSTEP[2:0] = 101: 4.7 mV/ µ s(sampling 3 Mhz/3)

TSTEP[2:0] = 110: 3.12 mV/ µ s(sampling 3 Mhz/4)

TSTEP[2:0] = 111: 2.5 mV/ µ s(sampling 3 Mhz/5)

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On, high power mode

ST[1:0] = 10 : Off

ST[1:0] = 11 : On, low power mode

Address Offset

Physical Address

Description

Type

Type

RW

RW

RW

RW

Table 48. VDD2_OP_REG

0x25

Instance

VDD2 voltage selection register.

This register can be accessed by both control and smartreflex I

2

C interfaces depending on

SR_CTL_I2C_SEL register bit value.

RW

www.ti.com

Reset

0x0

0

0x1

0x0

7

CMD

6 5 4 3

SEL

2 1 0

Bits

7

6:0

Field Name

CMD

SEL

Description

Smart-Reflex command: when 0: VDD2_OP_REG voltage is applied when 1: VDD2_SR_REG voltage is applied

Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,

12.5 mV per LSB):

SEL[6:0] = 1001011 to 1111111 : 1.5 V

...

SEL[6:0] = 0111111 : 1.35 V

...

SEL[6:0] = 0110011 : 1.2 V

...

SEL[6:0] = 0000001 to 0000011 : 0.6 V

SEL[6:0] = 0000000 : Off (0.0 V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout= (SEL[6:0] × 12.5 mV + 0.5625 mV) × G

Type

RW

RW

Reset

0

See

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Address Offset

Physical Address

Description

66

Table 49. VDD2_SR_REG

0x26

Instance

VDD2 voltage selection register for smartreflex.

This register can be accessed by both control and smartreflex I

2

C interfaces depending on

SR_CTL_I2C_SEL register bit value.

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

RW

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 49. VDD2_SR_REG (continued)

Type

7

Reserved

2 1

Bits

7

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0

6:0 SEL Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,

12.5 mV per LSB):

SEL[6:0] = 1001011 to 1111111: 1.5 V

...

SEL[6:0] = 0111111: 1.35V

...

SEL[6:0] = 0110011: 1.2V

...

SEL[6:0] = 0000001 to 0000011: 0.6V

SEL[6:0] = 0000000: Off (0.0V)

Note: from SEL[6:0] = 3 to 75 (dec)

Vout= (SEL[6:0] × 12.5 mV + 0.5625 mV) × G

See

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Address Offset

Physical Address

Description

Type

Table 50. VDD3_REG

0x27

Instance

VDD2 voltage selection register for smartreflex.

This register can be accessed by both control and smartreflex I

2

C interfaces depending on

SR_CTL_I2C_SEL register bit value.

RW

7

Bits

7:3

Field Name

Reserved

2

1:0

CKINEN

ST

Address Offset

Physical Address

Description

Type

7

6

6

5

5

Reserved

Description

Reserved bit

6

Reserved

5

4

4

4

3

SEL

3

Enable 1Mhz clock synchronization

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

Table 51. VDIG1_REG

0x30

Instance

VDIG1 regulator control register

RW

3

SEL

2

CKINEN

2

1

Type

RO

R returns

0s

RW

RW

1

ST

ST

0

0

Reset

0x00

1

0x0

0

Copyright © 2010 – 2011, Texas Instruments Incorporated

67

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

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Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.2 V

SEL[1:0] = 01 : 1.5 V

SEL[1:0] = 10 : 1.8 V

SEL[1:0] = 11 : 2.7 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 52. VDIG2_REG

Address Offset

Physical Address

Description

Type

0x31

VDIG2 regulator control register

RW

Instance

7 6

Reserved

5

6

Reserved

5

4 3

SEL

SEL

2 1

ST

ST

0

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.0 V

SEL[1:0] = 01 : 1.1 V

SEL[1:0] = 10 : 1.2 V

SEL[1:0] = 11 : 1.8 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 53. VAUX1_REG

Address Offset

Physical Address

Description

Type

0x32

VAUX1 regulator control register

RW

Instance

7 4 3 2 1 0

68

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.8 V

SEL[1:0] = 01 : 2.5 V

SEL[1:0] = 10 : 2.8 V

SEL[1:0] = 11 : 2.85 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 54. VAUX2_REG

Address Offset

Physical Address

Description

Type

0x33

VAUX2 regulator control register

RW

Instance

7 6

Reserved

5

6

Reserved

5

4 3

SEL

SEL

2 1

ST

ST

0

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.8 V

SEL[1:0] = 01 : 2.8 V

SEL[1:0] = 10 : 2.9 V

SEL[1:0] = 11 : 3.3 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Address Offset

Physical Address

Description

Type

Table 55. VAUX33_REG

0x34

VAUX33 regulator control register

RW

Instance

7 4 3 2 1 0

Copyright © 2010 – 2011, Texas Instruments Incorporated

69

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.8 V

SEL[1:0] = 01 : 2.0 V

SEL[1:0] = 10 : 2.8 V

SEL[1:0] = 11 : 3.3 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 56. VMMC_REG

Address Offset

Physical Address

Description

Type

0x35

VMMC regulator control register

RW

Instance

7 6

Reserved

5

6

Reserved

5

4 3

SEL

SEL

2 1

ST

ST

0

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.8 V

SEL[1:0] = 01 : 2.8 V

SEL[1:0] = 10 : 3.0 V

SEL[1:0] = 11 : 3.3 V

Supply state (EEPROM bits):

ST[1:0] = 00: Off

ST[1:0] = 01: On high power (ACTIVE)

ST[1:0] = 10: Off

ST[1:0] = 11: On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 57. VPLL_REG

Address Offset

Physical Address

Description

Type

0x36

VPLL regulator control register

RW

Instance

7 4 3 2 1 0

70

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.0V

SEL[1:0] = 01 : 1.1 V

SEL[1:0] = 10 : 1.8 V

SEL[1:0] = 11 : 2.5 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 58. VDAC_REG

Address Offset

Physical Address

Description

Type

0x37

VDAC regulator control register

RW

Instance

7 6

Reserved

5 4 3

SEL

2 1

ST

0

Bits

7:4

Field Name

Reserved

Description

Reserved bit

Type

RO

R returns

0s

RW

Reset

0x0

3:2

1:0

SEL

ST

Supply voltage (EEPROM bits):

SEL[1:0] = 00 : 1.8 V

SEL[1:0] = 01 : 2.6 V

SEL[1:0] = 10 : 2.8 V

SEL[1:0] = 11 : 2.85 V

Supply state (EEPROM bits):

ST[1:0] = 00 : Off

ST[1:0] = 01 : On high power (ACTIVE)

ST[1:0] = 10 : Off

ST[1:0] = 11 : On low power (SLEEP)

RW

See

0x0

(1)

(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor user guide to find the correct default value.

Table 59. Therm_REG

Address Offset

Physical Address

Description

Type

0x38

Thermal control register

RW

Instance

7 6 5 4 3 2 1 0

Reserved THERM_HD THERM_TS THERM_HDSEL RSVD1

Copyright © 2010 – 2011, Texas Instruments Incorporated

71

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

7:6

5

4

3:2 THERM_HDSEL

Address Offset

Physical Address

Description

Type

7

Bits

7:4

Field Name

Reserved

2:1 BBSEL

0

Address Offset

Physical Address

Description

Type

7

Reserved

6

Bits

7:6

Field Name

Reserved

5

4

3

1

0

Field Name

Reserved

THERM_HD

THERM_TS

RSVD1

THERM_STATE

BBCHEN

VDD2_PSKIP

VDD1_PSKIP

VIO_PSKIP

6

Description

Reserved bit

Hot die detector output: when 0: the hot die threshold is not reached when 1: the hot die threshold is reached

Thermal shutdown detector output: when 0: the thermal shutdown threshold is not reached when 1: the thermal shutdown threshold is reached

Temperature selection for Hot Die detector: when 00: Low temperature threshold

… when 11: High temperature threshold

Reserved bit

Thermal shutdown module enable signal: when 0: thermal shutdown module is disable when 1: thermal shutdown module is enable

Table 60. BBCH_REG

0x39

Instance

Back-up battery charger control register

RW

4 3 5

Reserved

Description

Reserved bit

2

BBSEL

Back up battery charge voltage selection:

BBSEL[1:0] = 00 : 3.0 V

BBSEL[1:0] = 01 : 2.52 V

BBSEL[1:0] = 10 : 3.15 V

BBSEL[1:0] = 11 : VBAT

Back up battery charge enable

Table 61. DCDCCTRL_REG

0x3E

Instance

DCDC control register

RW

5 4

VDD2_PSKIP VDD1_PSKIP

3

VIO_PSKIP

2

DCDCCKEXT

Description

Reserved bit

VDD2 pulse skip mode enable (EEPROM bit)

VDD1 pulse skip mode enable (EEPROM bit)

VIO pulse skip mode enable (EEPROM bit)

Type

RO

R returns

0s

RO

1

RO

RW

RW

RW

Type

RO

R returns

0s

RW

RW

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Reset

0x0

0

0

0x3

0

1

0

BBCHEN

Reset

0x00

0x0

0

1

DCDCCKSYNC

0

Type

RO

R returns

0s

RW

RW

RW

Reset

0x0

1

1

1

72

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

Bits

2

Field Name

DCDCCKEXT

1:0 DCDCCKSYNC

Address Offset

Physical Address

Description

Type

7 6

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Type

RW

Reset

0

Description

This signal control the muxing of the GPIO0 pad:

When 0: this pad is a GPIO

When 1: this pad is used as input for an external clock used for the synchronisation of the DCDCs

DCDC clock configuration:

DCDCCKSYNC[1:0] = 00 : no synchronization of DCDC clocks

DCDCCKSYNC[1:0] = 01 : DCDC synchronous clock with phase shift

DCDCCKSYNC[1:0] = 10 : no synchronization of DCDC clocks

DCDCCKSYNC[1:0] = 11 : DCDC synchronous clock

RW 0x3

Table 62. DEVCTRL_REG

0x3F

Instance

Device control register

RW

5 4 3 2 1 0

Reserved RTC_PWDN CK32K_CTRL DEV_ON DEV_SLP DEV_OFF

Bits

7

Field Name

Reserved

6

5

4

3

2

1

0

RTC_PWDN

CK32K_CTRL

SR_CTL_I2C_SEL

DEV_OFF_RST

DEV_ON

DEV_SLP

DEV_OFF

Address Offset

Physical Address

Description

Description

Reserved bit

When 1, disable the RTC digital domain (clock gating and reset of RTC registers and logic).

This register bit is not reset in BACKUP state. (EEPROM bit)

Internal 32-kHz clock source control bit (EEPROM bit): when 0, the internal 32-kHz clock source is the crystal oscillator or an external 32-kHz clock in case the crystal oscillator is used in bypass mode when 1, the internal 32-kHz clock source is the RC oscillator.

Smartreflex registers access control bit: when 0: access to smartreflex registers by smartreflex I2C when 1: access to smartreflex registers by control I2C The smartreflex registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG and

VDD2_SR_REG.

Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state transition (switch-off event) and activate reset of the digital core.

Write 1 will maintain the device on (ACTIVE or SLEEP device state) (if

DEV_OFF = 0 and DEV_OFF_RST = 0).

Write 1 allows SLEEP device state (if DEV_OFF = 0 and

DEV_OFF_RST = 0).

Write ‘ 0 ’ will start an SLEEP to ACTIVE device state transition (wake-up event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in

OFF state.

Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state transition (switch-off event). This bit is cleared in OFF state.

Type

RO

R returns

0s

RW

RW

RW

RW

RW

RW

RW

Table 63. DEVCTRL2_REG

0x40

Instance

Device control register

Copyright © 2010 – 2011, Texas Instruments Incorporated

Reset

0

1

0

0

0

0

0

0

73

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 63. DEVCTRL2_REG (continued)

Type

RW

7 6 5 4 3 2

Reserved TSLOT_LENGTH

1

www.ti.com

0

IT_POL

Bits

7:6

Field Name

Reserved

5:4 TSLOT_LENGTH

3

2

1

0

SLEEPSIG_POL

PWRON_LP_OFF

PWRON_LP_RST

IT_POL

Address Offset

Physical Address

Description

Type

7 6

Description

Reserved bit

Time slot duration programming (EEPROM bit):

When 00 : 0 µ s

When 01 : 200 µ s

When 10 : 500 µ s

When 11 : 2 ms

When 1, SLEEP signal active high

When 0, SLEEP signal active low

When 1, allows device turn-off after a PWRON long press (signal low).

When 1, allows digital core reset when the device is OFF after a

PWRON long press (signal low).

INT1 interrupt pad polarity control signal (EEPROM bit):

When 0, active low

When 1, active high

Type

RO

R returns

0s

RW

RW

RW

RW

RW

Reset

0x0

0x3

0

1

0

0

Table 64. SLEEP_KEEP_LDO_ON_REG

0x41

Instance

When corresponding control bit=0 in EN1/2_ LDO_ASS register (default setting): Configuration Register keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.

When control bit=1, LDO regulator full load capability (ACTIVE mode) is maintained during device

SLEEP state.

When control bit=0, the LDO regulator is set or stay in low power mode during device SLEEP state(but then supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO regulator is off.

When corresponding control bit=1 in EN1/2_ LDO_ASS register: Configuration Register setting the LDO regulator state driven by SCLSR_EN1/2 signal low level (when SCLSR_EN1/2 is high the regulator is on, full power):

- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)

- the regulator is set in low power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON register

RW

5 4 3 2 1 0

74

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Bits

7

Field Name

VDAC_KEEPON

6

5

4

VPLL_KEEPON

VAUX33_KEEPON

VAUX2_KEEPON

3

2

1

0

VAUX1_KEEPON

VDIG2_KEEPON

VDIG1_KEEPON

VMMC_KEEPON

Address Offset

Physical Address

Description

Type

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Type

RW

Reset

0

Description

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

Setting supply state during device SLEEP state or when SCLSR_EN1/2 is low

RW

RW

RW

RW

RW

RW

RW

0

0

0

0

0

0

0

Table 65. SLEEP_KEEP_RES_ON_REG

0x42

Instance

Configuration Register keeping, during the SLEEP state of the device (but then supply state can be overwritten programming ST[1:0]):

- the full load capability of LDO regulator (ACTIVE mode),

- The PWM mode of DCDC converter

- 32KHz clock output

- Register access though I2C interface (keeping the internal high speed clock on)

- Die Thermal monitoring on

Control bit value has no effect if the resource is off.

RW

7 6 5 4 3 2 1 0

VIO_KEEPON

Bits

7

6

5

4

3

Field Name

THERM_KEEPON

Description

When 1, thermal monitoring is maintained during device SLEEP state.

When 0, thermal monitoring is turned off during device SLEEP state.

CLKOUT32K_KEEPO When 1, CLK32KOUT output is maintained during device SLEEP state.

N When 0, CLK32KOUT output is set low during device SLEEP state.

VRTC_KEEPON When 1, LDO regulator full load capability (ACTIVE mode) is maintained during device SLEEP state.

When 0, the LDO regulator is set or stays in low power mode during device SLEEP state.

I2CHS_KEEPON

VDD3_KEEPON

When 1, high speed internal clock is maintained during device SLEEP state.

When 0, high speed internal clock is turned off during device SLEEP state.

When 1, VDD3 SMPS high power mode is maintained during device

SLEEP state. No effect if VDD3 working mode is low power.

When 0, VDD3 SMPS low power mode is set during device SLEEP state.

Type

RW

RW

RW

RW

RW

Copyright © 2010 – 2011, Texas Instruments Incorporated

0

0

Reset

0

0

0

75

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

2

Field Name

VDD2_KEEPON

1

0

VDD1_KEEPON

VIO_KEEPON

Description

If VDD2_EN1

&

2 control bit = 0 (default setting):

When 1, VDD2 SMPS PWM mode is maintained during device SLEEP state. No effect if VDD2 working mode is PFM.

When 0, VDD2 SMPS PFM mode is set during device SLEEP state.

If VDD1_EN1 & 2 control bit=0 (default setting):

When 1, VDD1 SMPS PWM mode is maintained during device SLEEP state. No effect if VDD1 working mode is PFM.

When 0, VDD1 SMPS PFM mode is set during device SLEEP state.

If VIO_EN1 & 2 control bit=0 (default setting): When 1, VIO SMPS PWM mode is maintained during device SLEEP state. No effect if VIO working mode is PFM.

When 0, VIO SMPS PFM mode is set during device SLEEP state.

Address Offset

Physical Address

Description

Type

Type

RW

RW

RW

www.ti.com

Reset

0

0

0

Table 66. SLEEP_SET_LDO_OFF_REG

0x43

Instance

Configuration Register turning-off LDO regulator during the SLEEP state of the device.

Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this

*_SET_OFF control bit effective

RW

7 6 5 4 3 2 1 0

VPLL_SETOFF

2

1

0

5

4

3

Bits

7

6

Field Name

VDAC_SETOFF

VPLL_SETOFF

VAUX33_SETOFF

IVAUX2_SETOFF

VAUX1_SETOFF

VDIG2_SETOFF

VDIG1_SETOFF

VMMC_SETOFF

Address Offset

Physical Address

Description

Type

Description

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

When 1, LDO regulator is turned off during device SLEEP state.

When 0, No effect

Type

RW

RW

RW

RW

RW

RW

RW

RW

Table 67. SLEEP_SET_RES_OFF_REG

0x44

Instance

Configuration Register turning-off SMPS regulator during the SLEEP state of the device.

Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON2 register should be 0 to make this

*_SET_OFF control bit effective. Supplies voltage expected after their wake-up (SLEEP to ACTIVE state transition) can also be programmed.

RW

Reset

0

0

0

0

0

0

0

0

76

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

7 6

RSVD

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

5 4 3 2 1 0

VIO_SETOFF

Bits

7

Field Name

DEFAULT_VOLT

6:5 RSVD

2

1

4

3

0

SPARE_SETOFF

VDD3_SETOFF

VDD2_SETOFF

VDD1_SETOFF

VIO_SETOFF

Address Offset

Physical Address

Description

Description

When 1, default voltages (registers value after switch-on) will be used to turned-on supplies during SLEEP to ACTIVE state transition.

When 0, voltages programmed before the ACTIVE to SLEEP state transition will be used to turned-on supplies during SLEEP to ACTIVE state transition.

Reserved bit

Type

RW

RO

R returns

0s

RW

RW

Spare bit

When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

When 1, SMPS is turned off during device SLEEP state.

When 0, No effect.

RW

RW

RW

Reset

0

0x0

0

0

0

0

0

Table 68. EN1_LDO_ASS_REG

0x45

Instance

Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.

When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting:

When SCLSR_EN1 is high the regulator is on,

When SCLSR_EN1 is low:

- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register

- the regulator is working in low power mode if its corresponding control bit = 1 in

SLEEP_KEEP_LDO_ON register

When control bit = 0 no effect : LDO regulator state is driven though registers programming and the device state

Any control bit of this register set to 1 will disable the I2C SR Interface functionality

RW

Type

7

VDAC_EN1

Bits

7

6

5

4

3

2

1

0

Field Name

VDAC_EN1

VPLL_EN1

VAUX33_EN1

VAUX2_EN1

VAUX1_EN1

VDIG2_EN1

VDIG1_EN1

VMMC_EN1

6

VPLL_EN1

5

VAUX33_EN1

4

VAUX2_EN1

3

VAUX1_EN1

Description

Setting supply state control though SCLSR_EN1 signal

Setting supply state control though SCLSR_EN1 signal

Setting supply state control though SCLSR_EN1 signal

Setting supply state control though SCLSR_EN1 signal

Setting supply state control though SCLSR_EN1 signal

Setting supply state control though SCLSR_EN1 signal

Setting supply state control though SCLSR_EN1 signal

Setting supply state control though SCLSR_EN1 signal

2

VDIG2_EN1

1

VDIG1_EN1

Type

RW

RW

RW

RW

RW

RW

RW

RW

0

VMMC_EN1

Reset

0

0

0

0

0

0

0

0

Copyright © 2010 – 2011, Texas Instruments Incorporated

77

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Address Offset

Physical Address

Description

Type www.ti.com

Table 69. EN1_SMPS_ASS_REG

0x46

Instance

Configuration Register setting the SMPS Supplies driven by the multiplexed SCLSR_EN1 signal.

When control bit = 1, SMPS Supply state and voltage is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_RES_ON register setting.

When control bit = 0 no effect : SMPS Supply state is driven though registers programming and the device state.

Any control bit of this register set to 1 will disable the I2C SR Interface functionality

RW

7 6

RSVD

5 4

SPARE_EN1

3

VDD3_EN1

2

VDD2_EN1

1

VDD1_EN1

0

VIO_EN1

Bits

7:5

4

3

Field Name

RSVD

SPARE_EN1

VDD3_EN1

2

1

0

VDD2_EN1

VDD1_EN1

VIO_EN1

Description

Reserved bit

Spare bit

When 1:

When SCLSR_EN1 is high the supply is on.

When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = '0' the supply voltage is off.

When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = '1' the SMPS is working in low power mode.

When control bit = 0 no effect: supply state is driven though registers programming and the device state

When control bit = 1:

When SCLSR_EN1 is high the supply voltage is programmed though

VDD2_OP_REG register, and it can also be programmed off.

When SCLSR_EN1 is low the supply voltage is programmed though

VDD2_SR_REG register, and it can also be programmed off.

When SCLSR_EN1 is low and VDD2_KEEPON = 1 the SMPS is working in low power mode, if not tuned off through VDD2_SR_REG register.

When control bit = 0 no effect: supply state is driven though registers programming and the device state

When 1:

When SCLSR_EN1 is high the supply voltage is programmed though

VDD1_OP_REG register, and it can also be programmed off.

When SCLSR_EN1 is low the supply voltage is programmed though

VDD1_SR_REG register, and it can also be programmed off.

When SCLSR_EN1 is low and VDD1_KEEPON = 1 the SMPS is working in low power mode, if not tuned off though VDD1_SR_REG register.

When control bit = 0 no effect: supply state is driven though registers programming and the device state

When control bit = 1, supply state is driven by the SCLSR_EN1 control signal and is also defined though SLEEP_KEEP_RES_ON register setting:

When SCLSR_EN1 is high the supply is on,

When SCLSR_EN1 is low:

- the supply is off (default) or the SMPS is working in low power mode if

VIO_KEEPON = 1

When control bit = 0 no effect: SMPS state is driven though registers programming and the device state

Type

RW

Rw

RW

RW

RW

RW

Reset

0

0

0

0

0

0

78

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

Address Offset

Physical Address

Description

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 70. EN2_LDO_ASS_REG

0x47

Instance

Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.

When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also defined though SLEEP_KEEP_LDO_ON register setting:

When SDASR_EN2 is high the regulator is on,

When SCLSR_EN2 is low:

- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register

- the regulator is working in low power mode if its corresponding control bit = 1 in

SLEEP_KEEP_LDO_ON register

When control bit = 0 no effect: LDO regulator state is driven though registers programming and the device state

Any control bit of this register set to 1 will disable the I2C SR Interface functionality

RW

Type

7

VDAC_EN2

6

VPLL_EN2

4

3

2

1

0

Bits

7

6

5

Field Name

VDAC_EN2

VPLL_EN2

VAUX33_EN2

VAUX2_EN2

VAUX1_EN2

VDIG2_EN2

VDIG1_EN2

VMMC_EN2

Address Offset

Physical Address

Description

Type

7

Bits

7:5

Field Name

RSVD

6

RSVD

5 4

VAUX33_EN2 VAUX2_EN2

3

VAUX1_EN2

2

VDIG2_EN2

1

VDIG1_EN2

0

VMMC_EN2

Description

Setting supply state control though SDASR_EN2 signal

Setting supply state control though SDASR_EN2 signal

Setting supply state control though SDASR_EN2 signal

Setting supply state control though SDASR_EN2 signal

Setting supply state control though SDASR_EN2 signal

Setting supply state control though SDASR_EN2 signal

Setting supply state control though SDASR_EN2 signal

Setting supply state control though SDASR_EN2 signal

Type

RW

RW

RW

RW

RW

RW

RW

RW

0

0

0

0

0

Reset

0

0

0

Table 71. EN2_SMPS_ASS_REG

0x48

Instance

Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.

When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is also defined though SLEEP_KEEP_RES_ON register setting.

When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the device state

Any control bit of this register set to 1 will disable the I2C SR Interface functionality

RW

5 4

SPARE_EN2

3

VDD3_EN2

2

VDD2_EN2

1

VDD1_EN2

0

VIO_EN2

Reset

0x0

4

3

SPARE_EN2

VDD3_EN2

Description

Reserved bit

Spare bit

When 1:

When SDASR_EN2 is high the supply is on.

When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 0 the supply voltage is off.

When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is working in low power mode.

When control bit = 0 no effect: supply state is driven though registers programming and the device state

Type

RO

R returns

0s

RW

RW

0

0

Copyright © 2010 – 2011, Texas Instruments Incorporated

79

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

2

Field Name

VDD2_EN2

1

0

VDD1_EN2

VIO_EN2

Description

When control bit = 1:

When SDASR_EN2 is high the supply voltage is programmed though

VDD2_OP_REG register, and it can also be programmed off.

When SDASR_EN2 is low the supply voltage is programmed though

VDD2_SR_REG register, and it can also be programmed off.

When SDASR_EN2 is low and and VDD2_KEEPON = 1 the SMPS is working in low power mode, if not tuned off though VDD2_SR_REG register.

When control bit = 0 no effect: supply state is driven though registers programming and the device state

When control bit = 1:

When SDASR_EN2 is high the supply voltage is programmed though

VDD1_OP_REG register, and it can also be programmed off.

When SDASR_EN2 is low the supply voltage is programmed though

VDD1_SR_REG register, and it can also be programmed off.

When SDASR_EN2 is low and and VDD1_KEEPON = 1 the SMPS is working in low power mode, if not tuned off though VDD1_SR_REG register.

When control bit = 0 no effect: supply state is driven though registers programming and the device state

When control bit = 1, supply state is driven by the SCLSR_EN2 control signal and is also defined though SLEEP_KEEP_RES_ON register setting:

When SDASR _EN2 is high the supply is on,

When SDASR _EN2 is low :

- the supply is off (default) or the SMPS is working in low power mode if

VIO_KEEPON = 1

When control bit = 0 no effect: SMPS state is driven though registers programming and the device state

Table 72. RESERVED

Address Offset

Physical Address

Description

Type

0x49

Reserved register

RW

Instance

7 6 5 4

RESERVED

3 2

Bits

7:0

Field Name

RESERVED

Description

Reserved bit

Table 73. RESERVED

Address Offset

Physical Address

Description

Type

7 6

0x4A

Reserved register

RW

5

Instance

4

RESERVED

3 2

Bits

7:0

Field Name

RESERVED

Description

Reserved bit

Type

RW

1

1

RW

RW

Type

RW

Type

RW

www.ti.com

Reset

0

0

0

0

Reset

0

0

Reset

0x00

80

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

Address Offset

Physical Address

Description

Type

7 6

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Table 74. INT_STS_REG

0x50

Instance

Interrupt status register:

The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1.

RW

5 4 3 2 1 0

HOTDIE_IT PWRHOLD_IT PWRON_LP_IT PWRON_IT VMBHI_IT VMBDCH_IT

4

3

2

1

0

Bits

7

6

5

Field Name

RTC_PERIOD_IT

RTC_ALARM_IT

HOTDIE_IT

PWRHOLD_IT

PWRON_LP_IT

PWRON_IT

VMBHI_IT

VMBDCH_IT

Address Offset

Physical Address

Description

Type

7 6

Description

RTC period event interrupt status.

RTC alarm event interrupt status.

Hot die event interrupt status.

Type

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

PWRHOLD event interrupt status.

PWRON Long Press event interrupt status.

PWRON event interrupt status.

VBAT

>

VMHI event interrupt status

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

VBAT > VMBDCH event interrupt status.

RW

Active only if Main Battery comparator VMBCH programmable threshold W1 to Clr is not bypassed (VMBCH_SEL[1:0] ≠ 00)

Table 75. INT_MSK_REG

0x51

Instance

Interrupt mask register:

When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.

When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.

RW

0

0

0

Reset

0

0

0

0

0

5 4 3 2 1 0

Copyright © 2010 – 2011, Texas Instruments Incorporated

81

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Bits

7

6

3

2

1

5

4

0

Field Name Description

RTC_PERIOD_IT_MS RTC period event interrupt mask.

K

RTC_ALARM_IT_MS RTC alarm event interrupt mask.

K

HOTDIE_IT_MSK Hot die event interrupt mask.

PWRHOLD_IT_MSK PWRHOLD rising edge event interrupt mask.

PWRON_LP_IT_MSK PWRON Long Press event interrupt mask.

PWRON_IT_MSK

VMBHI_IT_MSK

PWRON event interrupt mask.

VBAT > VMBHI event interrupt mask.

When 0, enable the device automatic switch on at BACKUP to OFF or

NOSUPPLY to OFF device state transition (EEPROM bit)

VMBDCH_IT_MSK VBAT < VMBDCH event interrupt status.

Active only if the main battery comparator VMBCH programmable threshold is not bypassed (VMBCH_SEL[1:0] ≠ 00).

Address Offset

Physical Address

Description

Type

Type

RW

RW

RW

RW

RW

RW

RW

RW 0

Table 76. INT_STS2_REG

0x52

Instance

Interrupt status register:

The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is cleared by writing 1.

RW

www.ti.com

Reset

0

0

0

0

1

0

0

7 6

Bits

7:2

1

0

Field Name

Reserved

GPIO0_F_IT

GPIO0_R_IT

Address Offset

Physical Address

Description

Type

7 6

5

Reserved

4 3 2 1

GPIO0_F_IT

0

GPIO0_R_IT

Description

Reserved bit

GPIO_CKSYNC falling edge detection interrupt status

GPIO_CKSYNC rising edge detection interrupt status

Type

RW

W1 to Clr

RW

W1 to Clr

RW

W1 to Clr

Reset

0

0

0

Table 77. INT_MSK2_REG

0x53

Instance

Interrupt mask register:

When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT interrupt status bit is updated.

When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is updated.

RW

5 4 3 2 1 0

Reserved

82

Copyright © 2010 – 2011, Texas Instruments Incorporated

www.ti.com

Bits

7:2

1

0

Field Name

Reserved

GPIO0_F_IT_MSK

GPIO0_R_IT_MSK

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

Description

Reserved bit

GPIO_CKSYNC falling edge detection interrupt mask.

GPIO_CKSYNC rising edge detection interrupt mask.

Type

RW

RW

RW

Reset

0

0

0

Table 78. GPIO0_REG

Address Offset

Physical Address

Description

Type

7 6

Reserved

Bits

7:5

Field Name

Reserved

0x60

GPIO0 configuration register

RW

5 4

GPIO_DEB

Description

Reserved bit

Instance

3

GPIO_PUEN

2

GPIO_CFG

4 GPIO_DEB

3 GPIO_PUEN

2 GPIO_CFG

1

0

GPIO_STS

GPIO_SET

GPIO_CKSYNC input debouncing time configuration:

When 0, the debouncing is 91.5

µ s using a 30.5

µ s clock rate

When 1, the debouncing is 150 ms using a 50 ms clock rate

GPIO_CKSYNC pad pull-up control:

1: Pull-up is enabled

0: Pull-up is disabled

Configuration of the GPIO_CKSYNC pad direction:

When 0, the pad is configured as an input

When 1, the pad is configured as an output

Status of the GPIO_CKSYNC pad

Value set on the GPIO output when configured in output mode

1

GPIO_STS

Type

RO

R returns

0s

RW

0

GPIO_SET

Reset

0x0

0

RW

RW

RO

RW

1

0

1

0

3:0 VERNUM

Table 79. JTAGVERNUM_REG

Address Offset

Physical Address

Description

Type

7

Bits

7:4

Field Name

Reserved

0x80

Silicon version number

RO

6

Reserved

5

Description

Reserved bit

4

Instance

3 2

VERNUM

1

Value depending on silicon version number 0000 - Revision 1.0

Type

RO

R returns

0s

RO

0

Reset

0x0

0x0

Copyright © 2010 – 2011, Texas Instruments Incorporated

83

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

GLOSSARY

IR

I/O

JEDEC

JTAG

LBC7

LDO

LP

LSB

MMC

MOSFET

NVM

OMAP ™

RTC

SMPS

SPI

POR

GND

GPIO

HBM

HD

HS-I

2

C

I

2

C

IC

ID

IDDQ

IEEE

ACRONYM

DDR

ES

ESD

FET

EPC

FSM

ACRONYMS, ABBREVIATIONS, AND DEFINITIONS

DEFINITION

Dual-Data Rate (memory)

Engineering Sample

Electrostatic Discharge

Field Effect Transistor

Embedded Power Controller

Finite State Machine

Ground

General-Purpose I/O

Human Body Model

Hot-Die

High-Speed I

2

C

Inter-Integrated Circuit

Integrated Circuit

Identification

Quiescent supply current

Institute of Electrical and Electronics Engineers

Instruction Register

Input/Output

Joint Electron Device Engineering Council

Joint Test Action Group

Lin Bi-CMOS 7 (360 nm)

Low Drop Output voltage linear regulator

Low-Power application mode

Least Significant Bit

Multimedia Card

Metal Oxide Semiconductor Field Effect Transistor

Nonvolatile Memory

Open Multimedia Application Platform ™

Real-Time Clock

Switched Mode Power Supply

Serial Peripheral Interface

Power-On Reset

www.ti.com

84

Copyright © 2010 – 2011, Texas Instruments Incorporated

TPS65910, TPS659101, TPS659102, TPS659103

TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109

SWCS046I – MARCH 2010 – REVISED JULY 2011

www.ti.com

VERSION

*

A

B

C

D

E

F

G

H

I

Table 80. REVISION HISTORY

DATE

03/2010

05/2010

06/2010

06/2010

11/2010

01/2011

01/2011

05/2011

06/2011

07/2011

NOTES

See

(1)

.

See

(2)

.

See

(3)

.

See

(4)

.

See

(5)

.

See

(6)

.

See

(7)

.

See

(8)

.

See

(9)

.

See

(10)

(1) Initial release

(2) SWCS046A: Updated register tables VMMC_REG and VDAC_REG. Added register table VPLL_REG

(3) SWCS046B: Update Absolute Maximum Ratings, Recommended Operating Conditions, I/O Pullup and Pulldown Characteristics, DigitaL

I/Os Voltage Electrical Characteristics, Power Consumption, Power References and Thresholds, Thermal Monitoring and Shutdown,

32-kHz RTC Clock, VRTC LDO, VIO SMPS, VDD1 SMPS, VDD2 SMPS, VDD3 SMPS, Switch-On/-Off Sequences and Timing

(4) SWCS046C: Associate parts; no change.

(5) SWCS046D: Update Recommended Operating Conditions - Backup Battery, I/O Pullup and Pulldown Characteristics, Backup Battery

Charger. Update Rated output current, PMOS current limit (High-Side), NMOS current limit (Low-Side), and Conversion Efficiency for

VIO SMPS, VDD1/VDD2/VDD3 SMPS and VDIG1/VDIG2 LDO. Update Input Voltage for VIO/VDD1/VDD2 SMPS. Update DC and

Transient Load and Line Regulatio and Internal Resistance for VDIG1/VDIG2 LDO, VAUX33/VMMC LDO, VAUX1,VAUX2, LDO, and

VDAC/VPLL LDO. Update DC Load Regulation for VAUX3/VMMC/VDAC. Update Power Control Timing. Add Device SLEEP State

Control. Add SMPS Switching Synchronization. Update VIO_REG, VDD1_REG, and VDD2_REG.

(6) SWCS046E: Manually added Thermal Pad Mechanical Data.

(7) SWCS046F: Update

Table 1 , SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.

(8) SWCS046G: Update

PACKAGE DESCRIPTION ,

RECOMMENDED OPERATING CONDITIONS ,

DIGITAL I/O VOLTAGE ELECTRICAL

CHARACTERISTICS

, and

PWRON .

(9) SWCS046H: Update

Table 40 , PUADEN_REG,

Table 72 , RESERVED, and Table 73

, RESERVED.

(10) SWCS046I: Update DC Output voltage V

OUT in

VAUX1 AND VAUX2 LDO

.

Copyright © 2010 – 2011, Texas Instruments Incorporated

85

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device

TPS659101A1RSL

Status

(1) Package Type Package

Drawing

ACTIVE VQFN RSL

Pins Package Qty

48 60

TPS659101A1RSLR

TPS659102A1RSL

ACTIVE

ACTIVE

VQFN

VQFN

RSL

RSL

48

48

2500

60

TPS659102A1RSLR

TPS659103A1RSL

TPS659103A1RSLR

TPS659104A1RSL

TPS659104A1RSLR

TPS659105A1RSL

TPS659105A1RSLR

TPS659106A1RSL

TPS659106A1RSLR

TPS659107A1RSL

TPS659107A1RSLR

TPS659108A1RSL

TPS659108A1RSLR

TPS659109A1RSL

TPS659109A1RSLR

TPS65910A1RSL

TPS65910A1RSLR

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

RSL

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

VQFN

ACTIVE

PREVIEW

PREVIEW

PREVIEW

PREVIEW

PREVIEW

PREVIEW

ACTIVE

ACTIVE

PREVIEW

PREVIEW

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

48

48

48

48

48

48

48

48

48

48

48

48

48

48

48

48

48

2500

60

2500

60

2500

2500

60

2500

60

2500

60

2500

60

2500

60

2500

60

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TBD

TBD

TBD

TBD

TBD

TBD

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TBD

TBD

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Lead/

Ball Finish

MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

(3)

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI Call TI

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

Call TI

Call TI

Call TI

Call TI

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

Addendum-Page 1

5-Jul-2011

Samples

(Requires Login)

PACKAGE OPTION ADDENDUM

www.ti.com

5-Jul-2011

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

22-Jul-2011

*All dimensions are nominal

Device

TPS659101A1RSLR

TPS659102A1RSLR

Package

Type

Package

Drawing

VQFN

VQFN

RSL

RSL

Pins

48

48

SPQ

2500

2500

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

16.4

330.0

16.4

A0

(mm)

6.3

6.3

B0

(mm)

6.3

6.3

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.1

1.1

12.0

12.0

16.0

16.0

Q2

Q2

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

22-Jul-2011

*All dimensions are nominal

Device

TPS659101A1RSLR

TPS659102A1RSLR

Package Type Package Drawing Pins

VQFN

VQFN

RSL

RSL

48

48

SPQ

2500

2500

Length (mm) Width (mm) Height (mm)

346.0

346.0

346.0

346.0

33.0

33.0

Pack Materials-Page 2

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