MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications Freescale Semiconductor

Freescale Semiconductor

Technical Data

Document Number: MPC8347EEC

Rev. 10, 07/2007

MPC8347E PowerQUICC™ II Pro

Integrated Host Processor Hardware

Specifications

The MPC8347E PowerQUICC™ II Pro is a next generation

PowerQUICC II integrated host processor. The MPC8347E contains a PowerPC™ processor core built on Power

Architecture™ technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349E PowerQUICC™ II Pro Integrated

Host Processor Reference Manual.

To locate published errata or updates for this document, refer to the MPC8347E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office.

NOTE

The information in this document is accurate for revision 1.1 silicon and earlier. For information on revision 3.0 silicon and later versions (for orderable part numbers ending in A or B), see the

MPC8347EA PowerQUICC™ II Pro Integrated

Host Processor Hardware Specifications.

See

Section 23.1, “Part Numbers Fully Addressed by This Document,”

for silicon revision level determination.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13

6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8. Ethernet: Three-Speed Ethernet, MII Management . 22

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12. I

2

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 55

19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

21. System Design Information . . . . . . . . . . . . . . . . . . . 90

22. Document Revision History . . . . . . . . . . . . . . . . . . . 94

23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 96

© Freescale Semiconductor, Inc., 2005–2007. All rights reserved.

Overview

1 Overview

This section provides a high-level overview of the MPC8347E features. Figure 1 shows the major

functional units within the MPC8347E.

Security

DUART

Dual I

2

C

Timers

GPIO

Interrupt

Controller

e300 Core

32KB

D-Cache

32KB

I-Cache

Local Bus

DDR

SDRAM

Controller

High-Speed

USB 2.0

Dual

Role

Host

10/100/1000

Ethernet

10/100/1000

Ethernet

PCI

SEQ

DMA

Figure 1. MPC8347E Block Diagram

Major features of the MPC8347E are as follows:

• Embedded PowerPC e300 processor core; operates at up to 667 MHz

— High-performance, superscalar processor core

— Floating-point, integer, load/store, system register, and branch processing units

— 32-Kbyte instruction cache, 32-Kbyte data cache

— Lockable portion of L1 cache

— Dynamic power management

— Software-compatible with the other Freescale processor families that implement Power

Architecture technology

• Double data rate, DDR SDRAM memory controller

— Programmable timing for DDR-1 SDRAM

— 32- or 64-bit data interface, up to 333-MHz data rate for TBGA, 266 MHz for PBGA

— Four banks of memory, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbit to 1 Gbit with x8/x16 data ports

— Full error checking and correction (ECC) support

— Page mode support (up to 16 simultaneous open pages)

— Contiguous or discontiguous memory mapping

— Read-modify-write support

— Sleep mode for self-refresh SDRAM

— Auto refresh

2

MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Overview

— On-the-fly power management using CKE

— Registered DIMM support

— 2.5-V SSTL2 compatible I/O

• Dual three-speed (10/100/1000) Ethernet controllers (TSECs)

— Dual controllers designed to comply with IEEE 802.3®, 802.3u®, 820.3x®, 802.3z®,

802.3ac® standards

— Ethernet physical interfaces:

– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex

– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex

— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100 programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module

— MII management interface for control and status

— Programmable CRC generation and checking

• PCI interface

— Designed to comply with PCI Specification Revision 2.2

— Data bus width:

– 32-bit data PCI interface operating at up to 66 MHz

— PCI 3.3-V compatible

— PCI host bridge capabilities

— PCI agent mode on PCI interface

— PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses and support for delayed read transactions

— Posting of processor-to-PCI and PCI-to-memory writes

— On-chip arbitration supporting five masters on PCI

— Accesses to all PCI address spaces

— Parity supported

— Selectable hardware-enforced coherency

— Address translation units for address mapping between host and peripheral

— Dual address cycle for target

— Internal configuration registers accessible from PCI

• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs):

— Public key execution unit (PKEU) :

– RSA and Diffie-Hellman algorithms


Freescale Semiconductor 3

Overview

– Programmable field size up to 2048 bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511 bits

— Data encryption standard (DES) execution unit (DEU)

– DES and 3DES algorithms

– Two key (K1, K2) or three key (K1, K2, K3) for 3DES

– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric-key cipher

– Key lengths of 128, 192, and 256 bits

– ECB, CBC, CCM, and counter (CTR) modes

— ARC four execution unit (AFEU)

– Stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160-, or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random number generator (RNG)

— Four crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units through an integrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

• Universal serial bus (USB) dual role controller

— USB on-the-go mode with both device and host functionality

— Complies with USB specification Rev. 2.0

— Can operate as a stand-alone USB device

– One upstream facing port

– Six programmable USB endpoints

— Can operate as a stand-alone USB host controller

– USB root hub with one downstream-facing port

– Enhanced host controller interface (EHCI) compatible

– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)

• Universal serial bus (USB) multi-port host controller

— Can operate as a stand-alone USB host controller

– USB root hub with one or two downstream-facing ports

4



Overview

– Enhanced host controller interface (EHCI) compatible

– Complies with USB Specification Rev. 2.0

— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— Direct connection to a high-speed device without an external hub

— External PHY with serial and low-pin count (ULPI) interfaces

• Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 133 MHz

— Four chip selects support four external slaves

— Up to eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller

— Three protocol engines on a per chip select basis:

– General-purpose chip select machine (GPCM)

– Three user-programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

• Programmable interrupt controller (PIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for 8 external and 35 internal discrete interrupt sources

— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources

— Programmable highest priority request

— Four groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Redirects interrupts to external INTA pin in core disable mode.

— Unique vector number for each interrupt source

• Dual industry-standard I

2

C interfaces

— Two-wire interface

— Multiple master support

— Master or slave I

2

C mode support

— On-chip digital filtering rejects spikes on the bus

— System initialization data optionally loaded from I

2

C-1 EPROM by boot sequencer embedded hardware

• DMA controller

— Four independent virtual channels

— Concurrent execution across multiple channels with programmable bandwidth control

— All channels accessible to local core and remote PCI masters

— Misaligned transfer capability



Overview

— Data chaining and direct mode

— Interrupt on completed segment and chain

• DUART

— Two 4-wire interfaces (RxD, TxD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• Serial peripheral interface (SPI) for master or slave

• General-purpose parallel I/O (GPIO)

— 52 parallel I/O pins multiplexed on various chip interfaces

• System timers

— Periodic interrupt timer

— Real-time clock

— Software watchdog timer

— Eight general-purpose timers

• Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan

• Integrated PCI bus and SDRAM clock generation

6



Electrical Characteristics

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8347E. The MPC8347E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

Table 1

provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings

1

Characteristic Symbol Max Value Unit Notes

Core supply voltage

PLL supply voltage

DDR DRAM I/O voltage

Three-speed Ethernet I/O, MII management voltage

PCI, local bus, DUART, system control and power management, I

2

C, and JTAG I/O voltage

Input voltage DDR DRAM signals

DDR DRAM reference

Three-speed Ethernet signals

Local bus, DUART, CLKIN, system control and power management, I

2

C, and JTAG signals

V

DD

AV

DD

GV

DD

LV

DD

OV

DD

MV

IN

MV

REF

LV

IN

OV

IN

–0.3 to 1.32

–0.3 to 1.32

–0.3 to 3.63

–0.3 to 3.63

–0.3 to 3.63

–0.3 to (GV

DD

+ 0.3)

–0.3 to (GV

DD

+ 0.3)

–0.3 to (LV

DD

+ 0.3)

–0.3 to (OV

DD

+ 0.3)

V

V

V

V

V

V

V

V

V

2, 5

2, 5

4, 5

3, 5

PCI

Storage temperature range

OV

IN

T

STG

–0.3 to (OV

DD

+ 0.3)

–55 to 150

V

°

C

6

6

Notes:

1

Functional and tested operating conditions are given in

Table 2 . Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.

2

Caution: MV

IN

must not exceed GV

DD

by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

3

Caution: OV

IN

must not exceed OV

DD


4

Caution: LV

IN

must not exceed LV

DD


5

(M,L,O)V

IN

and MV

REF

may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2

.

OV

IN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3.




2.1.2

Power Supply Voltage Specification

Table 2

provides the recommended operating conditions for the MPC8347E. Note that the values in

Table 2

are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.

Table 2. Recommended Operating Conditions

Characteristic Symbol

Recommended

Value

Unit Notes

Core supply voltage

PLL supply voltage

DDR DRAM I/O supply voltage

Three-speed Ethernet I/O supply voltage

V

AV

GV

LV

DD

DD

DD

DD1

1.2 V ± 60 mV

1.2 V ± 60 mV

2.5 V ± 125 mV

3.3 V ± 330 mV

2.5 V ± 125 mV

V

V

V

V

1

1

Three-speed Ethernet I/O supply voltage LV

DD2

3.3 V ± 330 mV

2.5 V ± 125 mV

3.3 V ± 330 mV

V

PCI, local bus, DUART, system control and power management, I

2

C, and JTAG I/O voltage

OV

DD

V

Note:

1

GV

DD

, LV

DD

, OV

DD

, AV

DD

, and V

DD

must track each other and must vary in the same direction—either in the positive or negative direction.

Figure 2

shows the undershoot and overshoot voltages at the interfaces of the MPC8347E.

V

IH

G/L/OV

DD

+ 20%

G/L/OV

DD

+ 5%

G/L/OV

DD

GND

GND – 0.3 V

V

IL

GND – 0.7 V

Not to Exceed 10% of t interface

1

Note:

1. t interface

refers to the clock period associated with the bus clock interface.

Figure 2. Overshoot/Undershoot Voltage for GV

DD

/OV

DD

/LV

DD

8




Figure 3

shows the undershoot and overshoot voltage of the PCI interface of the MPC8347E for the 3.3-V signals, respectively.

11 ns

(Min)

+7.1 V

Overvoltage

Waveform

7.1 V p-to-p

(Min)

4 ns

0 V

(Max)

4 ns

(Max)

62.5 ns

+3.6 V

Undervoltage

Waveform

7.1 V p-to-p

(Min)

–3.5 V

Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling

2.1.3

Output Driver Characteristics

Table 3

provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 3. Output Drive Capability

Driver Type

Local bus interface utilities signals

PCI signals (not including PCI output clocks)

PCI output clocks (including PCI_SYNC_OUT)

DDR signal

TSEC/10/100 signals

DUART, system control, I

2

C, JTAG, USB

GPIO signals

Output Impedance

(

Ω

)

40

40

40

40

25

40

18

Supply

Voltage

OV

DD

= 3.3 V

GV

DD

= 2.5 V

LV

DD

= 2.5/3.3 V

OV

DD

= 3.3 V

OV

DD

= 3.3 V,

LV

DD

= 2.5/3.3 V

2.2

Power Sequencing

MPC8347E does not require the core supply voltage and I/O supply voltages to be applied in any particular order. Note that during the power ramp up, before the power supplies are stable, there may be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are three-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up.



Power Characteristics

3 Power Characteristics

The estimated typical power dissipation for the MPC8347E device is shown in

Table 4 .

Table 4. MPC8347E Power Dissipation

1

Core

Frequency

(MHz)

CSB

Frequency

(MHz)

Typical at T

J

= 65 Typical

2,3

Maximum

4

Unit

PBGA

TBGA

266

400

400

333

266

133

266

133

200

100

333

166

266

1.3

1.1

1.5

1.4

1.5

1.3

2.0

1.8

2.1

1.6

1.4

1.9

1.7

1.8

1.7

3.0

2.8

3.0

1.8

1.6

2.1

1.9

2.0

1.9

3.2

2.9

3.3

400

450

133

300

150

333

1.9

2.3

2.1

2.4

2.9

3.2

3.0

3.3

3.1

3.5

3.2

3.6

W

W

W

W 500

533

166

266

2.2

2.4

3.1

3.3

3.4

3.6

W

W

133 2.2

3.1

3.4

W

Notes:

1. The values do not include I/O supply power (OV

2. Typical power is based on a voltage of V

DD

DD

, LV

DD

, GV

DD

) or AV

DD

. For I/O power values, see

Table 5 .

= 1.2 V, a junction temperature of T

J

= 105

°

C, and a Dhrystone benchmark application.

3. Thermal solutions may need to design to a value higher than typical power based on the end application, T

A

target, and I/O power.

4. Maximum power is based on a voltage of V

DD

= 1.2 V, worst case process, a junction temperature of T

J artificial smoke test.

= 105

°

C, and an

W

W

W

W

W

W

W

W

W

10



Power Characteristics

Table 5

shows the estimated typical I/O power dissipation for MPC8347E.

Table 5. MPC8347E Typical I/O Power Dissipation

Interface Parameter

DDR I/O

65% utilization

2.5 V

Rs = 20

Ω

Rt = 50

Ω

2 pair of clocks

PCI I/O load = 30 pF

Local bus I/O load = 25 pF

200 MHz, 32 bits

200 MHz, 64 bits

266 MHz, 32 bits

266 MHz, 64 bits

300 MHz,

1

32 bits

300 MHz,

1

64 bits

333 MHz,

1

32 bits

333 MHz,

1

64 bits

400 MHz,

1

32 bits

400 MHz,

1

64 bits

33 MHz, 32 bits

66 MHz, 32 bits

167 MHz, 32 bits

133 MHz, 32 bits

83 MHz, 32 bits

66 MHz, 32 bits

50 MHz, 32 bits

TSEC I/O load = 25 pF

USB

Other I/O

Note:

1. TBGA package only.

MII

GMII or TBI

RGMII or RTBI

12 MHz

480 MHz

DDR2

GV

DD

(1.8 V)

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

DDR1

GV

DD

(2.5 V)

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

0.54

0.7

0.58

0.76

0.42

0.55

0.5

0.66

OV

DD

(3.3 V)

LV

DD

(3.3 V)

LV

DD

(2.5 V)

0.34

0.27

0.17

0.14

0.11

—

—

—

—

—

0.04

0.07

0.01

0.2

0.01

—

—

—

—

—

—

—

—

—

—

—

—

—

0.01

0.06

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

0.04

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Unit

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

Comments

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Multiply by number of interfaces used.

Multiply by 2 if using

2 ports.

—



Clock Input Timing

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8347E.

4.1

DC Electrical Characteristics

Table 7

provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8347E.

Table 6. CLKIN DC Timing Specifications

Parameter

Input high voltage

Input low voltage

CLKIN input current

PCI_SYNC_IN input current

PCI_SYNC_IN input current

Condition

—

—

0 V

≤

V

IN

≤

OV

DD

OV

0 V

DD

≤

V

IN

≤

0.5 V or

– 0.5 V

≤

V

IN

≤

OV

DD

0.5 V

≤

V

IN

≤

OV

DD

– 0.5 V

Symbol

V

IH

V

IL

I

IN

I

IN

I

IN

Min

2.7

–0.3

—

—

—

Max

OV

DD

+ 0.3

0.4

±10

±10

±50

Unit

V

V

μ

A

μ

A

μ

A

4.2

AC Electrical Characteristics

The primary clock source for the MPC8347E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode.

Table 7

provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the MPC8347E.

Table 7. CLKIN AC

Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

CLKIN/PCI_CLK frequency

CLKIN/PCI_CLK cycle time

CLKIN/PCI_CLK rise and fall time

CLKIN/PCI_CLK duty cycle f

CLKIN t

CLKIN t

KH

, t

KL t

KHK

/t

CLKIN

—

—

15

0.6

40

—

—

1.0

—

66

—

2.3

60

MHz ns ns

%

1

—

2

3

CLKIN/PCI_CLK jitter — — ±150 ps 4, 5

Notes:

1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

12



RESET Initialization

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8347E.

5.1

RESET DC Electrical Characteristics

Table 8

provides the DC electrical characteristics for the RESET pins of the MPC8347E.

Table 8. RESET Pins DC Electrical Characteristics

1

Characteristic Symbol Condition

Input high voltage

Input low voltage

Input current

V

IH

V

IL

I

IN

V

OH

Output high voltage

Output low voltage

Output low voltage

2

V

OL

V

OL

I

OH

= –8.0 mA

I

I

OL

OL

= 8.0 mA

= 3.2 mA

Notes:

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus V

OH

is not relevant for those pins.

Min

2.0

–0.3

2.4

—

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.5

0.4

5.2

RESET AC Electrical Characteristics

Table 9

provides the reset initialization AC timing specifications of the MPC8347E.

Table 9. RESET Initialization Timing Specifications

Parameter/Condition

Required assertion time of HRESET or SRESET (input) to activate reset flow

Required assertion time of PORESET with stable clock applied to CLKIN when the MPC8347E is in PCI host mode

Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the MPC8347E is in PCI agent mode

HRESET/SRESET assertion (output)

HRESET negation to SRESET negation (output)

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347E is in PCI host mode

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347E is in PCI agent mode

Min

32

32

32

512

16

4

4

Max

—

—

—

—

—

—

—

Unit

t

PCI_SYNC_IN t

CLKIN t

PCI_SYNC_IN t

PCI_SYNC_IN t

PCI_SYNC_IN t

CLKIN t

PCI_SYNC_IN

Notes

1

2

1

1

1

2

1

Unit

V

V

μ

A

V

V

V



RESET Initialization

Table 9. RESET Initialization Timing Specifications (continued)

Parameter/Condition Min Max Unit Notes

Input hold time for POR configuration signals with respect to negation of HRESET

Time for the MPC8347E to turn off POR configuration signals with respect to the assertion of HRESET

Time for the MPC8347E to turn on POR configuration signals with respect to the negation of HRESET

0

—

1

—

4

— ns ns t

PCI_SYNC_IN

3

1, 3

Notes:

1. t

PCI_SYNC_IN

is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349E

PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual.

2. t

CLKIN

is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349E

PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual.

3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 10

lists the PLL and DLL lock times.

Table 10. PLL and DLL Lock Times

Parameter/Condition Min Max Unit Notes

PLL lock times

DLL lock times

—

7680

100

122,880

μ s csb_clk cycles 1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”

14



DDR SDRAM

6 DDR SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8347E.

NOTE

The information in this document is accurate for revision 1.1 silicon and earlier. For information on revision 3.0 silicon and earlier versions see the

MPC8347EA PowerQUICC™ II Pro Integrated Host Processor Hardware

Specifications. See Section 23.1, “Part Numbers Fully Addressed by This

Document ,” for silicon revision level determination.

6.1

DDR SDRAM DC Electrical Characteristics

Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the

MPC8347E.

Table 11. DDR SDRAM DC Electrical Characteristics

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage

I/O reference voltage

I/O termination voltage

Input high voltage

Input low voltage

Output leakage current

Output high current (V

OUT

= 1.95 V)

Output low current (V

OUT

= 0.35 V)

MV

REF

input leakage current

GV

DD

MV

REF

V

TT

V

IH

V

IL

I

OZ

I

OH

I

OL

I

VREF

2.375

0.49

×

GV

DD

MV

REF

– 0.04

MV

REF

+ 0.18

–0.3

–10

–15.2

15.2

—

2.625

0.51

×

GV

DD

MV

REF

+ 0.04

GV

DD

+ 0.3

MV

REF

– 0.18

10

—

—

5

V

V

V

V

V

μ

A mA mA

μ

A

1

2

3

4

Notes:

1. GV

2. MV

DD

is expected to be within 50 mV of the DRAM GV

DD at all times.

REF

is expected to be equal to 0.5

×

GV

DD

, and to track GV

DD

DC variations as measured at the receiver. Peak-to-peak noise on MV

REF

may not exceed ±2% of the DC value.

3. V

TT

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MV

REF

. This rail should track variations in the DC level of MV

4. Output leakage is measured with all outputs disabled, 0 V

≤

V

REF

.

OUT

≤

GV

DD

.



DDR SDRAM

Table 12

provides the DDR capacitance.

Table 12. DDR SDRAM Capacitance

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

C

IO

C

DIO

6

—

8

0.5

pF pF

1

1

Note:

1. This parameter is sampled. GV

DD

= 2.5 V ± 0.125 V, f = 1 MHz, T

A

= 25

°

C, V

OUT

= GV

DD

/2, V

OUT

(peak-to-peak) = 0.2 V.

6.2

DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR SDRAM Input AC Timing Specifications

Table 13

provides the input AC timing specifications for the DDR SDRAM interface.

Table 13. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GV

DD

of 2.5 V ± 5%.

Parameter Symbol Min Max Unit

AC input low voltage

AC input high voltage

MDQS—MDQ/MECC input skew per byte

333 MHz

266 MHz t

V

V

IL

IH

DISKEW

—

MV

REF

+ 0.31

—

MV

REF

– 0.31

GV

DD

+ 0.3

750

1125

V

V ps

Note:

1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if

0 <= n <= 7) or ECC (MECC[{0...7}] if n = 8).

Notes

1

16



DDR SDRAM

6.2.2

DDR SDRAM Output AC Timing Specifications

Table 14

and

Table 15

provide the output AC timing specifications and measurement conditions for the

DDR SDRAM interface.

Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode


DD

of 2.5 V ± 5%.

Parameter Symbol

1

Min Max Unit Notes

6 10 ns ps

2

3

MCK[n] cycle time, (MCK[n]/MCK[n] crossing)

Skew between any MCK to ADDR/CMD

333 MHz

266 MHz

200 MHz

ADDR/CMD output setup with respect to MCK

333 MHz

266 MHz

200 MHz

ADDR/CMD output hold with respect to MCK

333 MHz

266 MHz

200 MHz

MCS(n) output setup with respect to MCK

333 MHz

266 MHz

200 MHz

MCS(n) output hold with respect to MCK

333 MHz

266 MHz

200 MHz

MCK to MDQS

333 MHz

266 MHz

200 MHz

MDQ/MECC/MDM output setup with respect to

MDQS

333 MHz

266 MHz

200 MHz

MDQ/MECC/MDM output hold with respect to

MDQS

333 MHz

266 MHz

200 MHz t t t t t t t

MCK

AOSKEW

DDKHAS

DDKHAX

DDKHCS

DDKHCX

DDKHMH t

DDKHDS, t

DDKLDS t

DDKHDX, t

DDKLDX

–1000

–1100

–1200

2.8

3.45

4.6

2.0

2.65

3.8

2.8

3.45

4.6

2.0

2.65

3.8

–0.9

–1.1

–1.2

900

900

1200

900

900

1200

0.3

0.5

0.6

—

200

300

400

—

—

—

—

— ns ns ns ns ns ps ps

4

4

4

4

5

6

6



DDR SDRAM

Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)


DD

of 2.5 V ± 5%.


1


MDQS preamble start

MDQS epilogue end t

DDKHMP t

DDKLME

–0.25

× t

MCK

–0.9

– 0.9

–0.25

× t

MCK

0.3

+ 0.3

ns ns

7

7

Notes:

1. The symbols used for timing specifications follow the pattern of t inputs and t

(first two letters of functional block)(reference)(state)(signal)(state)

(first two letters of functional block)(signal)(state)(reference)(state)

for

for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t

DDKHAS

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t

DDKLDX

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the clock control register.

For the skew measurements referenced for t

AOSKEW

it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of MCK.

4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by

1/2 applied cycle.

5. Note that t

DDKHMH follows the symbol conventions described in note 1. For example, t

DDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t

DDKHMH

can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the MPC8349E PowerQUICC™ II Pro Integrated Host

Processor Family Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits.

6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8347E.

7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8347E. Note that t

DDKHMP follows the symbol conventions described in note 1.

Figure 4

shows the DDR SDRAM output timing for address skew with respect to any MCK.

MCK[n]

MCK[n] t

MCK t

AOSKEWmax)

18

ADDR/CMD CMD t

AOSKEW(min)

NOOP

ADDR/CMD CMD NOOP

Figure 4. Timing Diagram for t

AOSKEW

Measurement



DDR SDRAM

Figure 5

provides the AC test load for the DDR bus.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 5. DDR AC Test Load

Table 15

shows the DDR SDRAM measurement conditions.

Table 15. DDR SDRAM Measurement Conditions

Symbol

V

TH

V

OUT

Notes:

1. Data input threshold measurement point.

2. Data output measurement point.

DDR

MV

REF

± 0.31 V

0.5

×

GV

DD

Figure 6

shows the DDR SDRAM output timing diagram for source synchronous mode.

MCK[n]

MCK[n] t

MCK

Unit

V

V

Notes

1

2

ADDR/CMD Write A0 t

DDKHAS

,t

DDKHCS t

DDKHAX

, t

DDKHCX

NOOP t

DDKHMP t

DDKHMH

MDQS[n] t

DDKHDS t

DDKLDS t

DDKHME

MDQ[x] D0 D1 t

DDKLDX t

DDKHDX

Figure 6. DDR SDRAM Output Timing Diagram for Source Synchronous Mode

Table 16

provides approximate delay information that can be expected for the address and command signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.

These numbers are the result of simulations for one topology. The delay numbers will strongly depend on the topology used. These delay numbers show the total delay for the address and command to arrive at the

DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the



DDR SDRAM

system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM.

Table 16. Expected Delays for Address/Command

Load

4 devices (12 pF)

9 devices (27 pF)

36 devices (108 pF) + 40 pF compensation capacitor

36 devices (108 pF) + 80 pF compensation capacitor

Delay

3.0

3.6

5.0

5.2

Unit

ns ns ns ns

20



DUART

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the

MPC8347E.

7.1

DUART DC Electrical Characteristics

Table 17

provides the DC electrical characteristics for the DUART interface of the MPC8347E.

Table 17. DUART DC Electrical Characteristics

Parameter

High-level input voltage

Low-level input voltage

Input current (0.8 V

≤

V

IN

≤

2 V)

High-level output voltage, I

OH

= –100

μ

A

Low-level output voltage, I

OL

= 100

μ

A

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

Min

2

–0.3

—

OV

DD

– 0.2

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.2

Unit

V

V

μ

A

V

V

7.2

DUART AC Electrical Specifications

Table 18

provides the AC timing parameters for the DUART interface of the MPC8347E.

Table 18. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate

Maximum baud rate

Oversample rate

256

>1,000,000

16 baud baud

—

1

2

Notes:

1. Actual attainable baud rate will be limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8 th

sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16 th

sample.



Ethernet: Three-Speed Ethernet, MII Management

8 Ethernet: Three-Speed Ethernet, MII Management

This section provides the AC and DC electrical characteristics for three-speeds (10/100/1000 Mbps) and

MII management.

8.1

Three-Speed Ethernet Controller (TSEC)—

GMII/MII/TBI/RGMII/RTBI Electrical Characteristics

The electrical characteristics specified here apply to the gigabit media independent interface (GMII), the media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), and reduced ten-bit interface (RTBI) signals except management data input/output

(MDIO) and management data clock (MDC). The MII, GMII, and TBI interfaces are defined for 3.3 V, and the RGMII and RTBI interfaces can operate at 3.3 or 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device

Specification, Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified

in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”

8.1.1

TSEC DC Electrical Characteristics

All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes

specified in Table 19

and

Table 20

. The potential applied to the input of a GMII, MII, TBI, RGMII, or

RTBI receiver may exceed the potential of the receiver power supply (that is, a RGMII driver powered from a 3.6-V supply driving V

OH

into a RGMII receiver powered from a 2.5-V supply). Tolerance for dissimilar RGMII driver and receiver supply potentials is implicit in these specifications. The RGMII and

RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.

Table 19. GMII/TBI and MII DC Electrical Characteristics

Parameter Symbol Conditions Min

Supply voltage 3.3 V LV

DD

2

— 2.97

Output high voltage

Output low voltage

V

V

OH

OL

I

OH

= –4.0 mA

I

OL

= 4.0 mA

—

LV

DD

= Min

LV

DD

= Min

—

2.40

GND

Input high voltage

Input low voltage

V

IH

V

IL

— —

2.0

–0.3

Input high current

Input low current

I

I

IH

IL

V

IN

1

= LV

DD

V

IN

1

= GND

—

–600

Notes:

1. The symbol V

IN

, in this case, represents the LV

IN

symbol referenced in

Table 1 and

Table 2

.

2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OV

DD

supply.

Max

3.63

LV

DD

+ 0.3

0.50

LV

DD

+ 0.3

0.90

40

—

Unit

V

V

V

V

V

μ

A

μ

A

22




Table 20. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics

Parameters Symbol Conditions Min

Supply voltage 2.5 V

Output high voltage

Output low voltage

LV

DD

V

V

OH

OL

I

OH

= –1.0 mA

I

OL

= 1.0 mA

—

—

LV

DD

= Min

LV

DD

= Min

LV

DD

= Min

2.37

2.00

GND – 0.3

Input high voltage V

IH

1.7

Input low voltage

Input high current

V

I

IL

IH

— LV

DD

= Min

V

IN

1

= LV

DD

V

IN

1

= GND

–0.3

—

Input low current I

IL

–15

Note:

1. The symbol V

IN


IN


Table 1 and

Table 2

.

Max

2.63

LV

DD

+ 0.3

0.40

LV

DD

+ 0.3

0.70

10

—

8.2

GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications

The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.

Unit

V

V

V

V

V

μ

A

μ

A

8.2.1

GMII Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.1.1

GMII Transmit AC Timing Specifications

Table 21

provides the GMII transmit AC timing specifications.

Table 21. GMII Transmit AC Timing Specifications

At recommended operating conditions with LV

DD

/OV

DD of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

GTX_CLK clock period

GTX_CLK duty cycle

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay t

GTX t

GTXH

/t

GTX

t

GTKHDX

—

43.75

0.5

8.0

—

—

—

56.25

5.0

ns

% ns

GTX_CLK clock rise time, V

IL

(min) to V

IH

(max) t

GTXR

GTX_CLK clock fall time, V

IH

(max) to V

IL

(min) t

GTXF

GTX_CLK125 clock period t

G125

2

GTX_CLK125 reference clock duty cycle measured at LV

DD

/2 t

G125H

/t

G125

—

—

—

45

—

—

8.0

—

1.0

1.0

—

55 ns ns ns

%

Notes:

1. The symbols for timing specifications follow the pattern t

(first two letters of functional block)(signal)(state)(reference)(state) t

(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t

GTKHDV for inputs and

symbolizes GMII transmit timing

(GT) with respect to the t

GTX

clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, t

GTKHDX

symbolizes GMII transmit timing (GT) with respect to the t

GTX

clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t

GTX

represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This symbol represents the external GTX_CLK125 signal and does not follow the original symbol naming convention.




Figure 7

shows the GMII transmit AC timing diagram.

t

GTX

GTX_CLK t

GTXH t

GTXF

TXD[7:0]

TX_EN

TX_ER t

GTXR t

GTKHDX

Figure 7. GMII Transmit AC Timing Diagram

8.2.1.2

GMII Receive AC Timing Specifications

Table 22

provides the GMII receive AC timing specifications.

Table 22. GMII Receive AC Timing Specifications


DD

/OV

DD of 3.3 V ± 10%.


1


RX_CLK clock period

RX_CLK duty cycle t

GRX t

GRXH

/t

GRX

—

40

8.0

—

—

60 ns

%

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise, V

IL

(min) to V

RX_CLK clock fall time, V

IH

IH

(max)

(max) to V

IL

(min) t

GRDVKH t

GRDXKH t

GRXR t

GRXF

2.0

0.5

—

—

—

—

—

—

—

—

1.0

1.0

ns ns ns ns

Note:

1. The symbols for timing specifications follow the pattern of t


for inputs and t


for outputs. For example, t

GRDVKH

symbolizes GMII receive timing

(GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

RX

clock reference (K) going to the high state (H) or setup time. Also, t signals (D) went invalid (X) relative to the t

GRDXKL

symbolizes GMII receive timing (GR) with respect to the time data input

GRX

clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t

GRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

24




Figure 8

shows the GMII receive AC timing diagram.

G t

GRX

RX_CLK t

GRXH t

GRXF

RXD[7:0]

RX_DV

RX_ER t

GRXR t

GRDXKH t

GRDVKH

Figure 8. GMII Receive AC Timing Diagram

8.2.2

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.2.1

MII Transmit AC Timing Specifications

Table 23

provides the MII transmit AC timing specifications.

Table 23. MII Transmit AC Timing Specifications


DD

/OV

DD of 3.3 V ± 10%.


1


TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle t

MTX t

MTX t

MTXH/ t

MTX

—

—

35

400

40

—

—

—

65 ns ns

%

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise V

IL

(min) to V

IH

(max) t

MTKHDX t

MTXR

TX_CLK data clock fall V

IH

(max) to V

IL

(min) t

MTXF

1

1.0

1.0

5

—

—

15

4.0

4.0

ns ns ns

Note:



for inputs and t



MTKHDX

symbolizes MII transmit timing

(MT) for the time t

MTX

clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of t

MTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:





Figure 9

shows the MII transmit AC timing diagram.

t

MTX

TX_CLK t

MTXH t

MTXF

TXD[3:0]

TX_EN

TX_ER t

MTXR t

MTKHDX

Figure 9. MII Transmit AC Timing Diagram

8.2.2.2

MII Receive AC Timing Specifications

Table 24

provides the MII receive AC timing specifications.

Table 24. MII Receive AC Timing Specifications


DD

/OV

DD of 3.3 V ± 10%.


1


RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle t

MRX t

MRX t

MRXH

/t

MRX

—

—

35

400

40

—

—

—

65 ns ns

%

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise V

IL

(min) to V

RX_CLK clock fall time V

IH

(max)

IH

(max) to V

IL

(min) t

MRDVKH t

MRDXKH t

MRXR t

MRXF

10.0

10.0

1.0

1.0

—

—

—

—

—

—

4.0

4.0

ns ns ns ns

Note:



for inputs and t



MRDVKH

symbolizes MII receive timing

(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MRX

clock reference (K) going to the high (H) state or setup time. Also, t

MRDXKL

symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the t

MRX

clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular functionl. For example, the subscript of t

MRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:


Figure 10

provides the AC test load for TSEC.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 10. TSEC AC Test Load

26




Figure 11 shows the MII receive AC timing diagram.

t

MRX

RX_CLK

RXD[3:0]

RX_DV

RX_ER t

MRXR t

MRXH t

MRXF

Valid Data t

MRDVKH t

MRDXKH

Figure 11. MII Receive AC Timing Diagram

8.2.3

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.3.1

TBI Transmit AC Timing Specifications

Table 25

provides the TBI transmit AC timing specifications.

Table 25. TBI Transmit AC Timing Specifications


DD

/OV

DD of 3.3 V ± 10%.


1


GTX_CLK clock period

GTX_CLK duty cycle t

TTX t

TTXH

/t

TTX

GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK clock rise, V

IL

(min) to V

IH

(max)

t

TTKHDX t

TTXR

GTX_CLK clock fall time, V

IH

(max) to V

IL

(min) t

TTXF

GTX_CLK125 reference clock period t

G125

2

GTX_CLK125 reference clock duty cycle t

G125H

/t

G125

—

40

1.0

—

—

—

45

8.0

—

—

—

—

8.0

—

—

60

5.0

1.0

1.0

—

55 ns

% ns ns ns ns ns

Notes:



for inputs and t



TTKHDV

symbolizes the TBI transmit timing (TT) with respect to the time from t

TTX

(K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, t

TTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from t

TTX

(K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t

TTX

represents the TBI (T) transmit

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention




Figure 12

shows the TBI transmit AC timing diagram.

t

TTX

GTX_CLK t

TTXH t

TTXF

TXD[7:0]

TX_EN

TX_ER t

TTXR t

TTKHDX

Figure 12. TBI Transmit AC Timing Diagram

8.2.3.2

TBI Receive AC Timing Specifications

Table 26

provides the TBI receive AC timing specifications.

Table 26. TBI Receive AC Timing Specifications


DD

/OV

DD of 3.3 V ± 10%.


1


PMA_RX_CLK clock period

PMA_RX_CLK skew

RX_CLK duty cycle

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising

PMA_RX_CLK

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising

PMA_RX_CLK t

TRXH t t t t

TRX

SKTRX

/t

TRX

TRDVKH

2

TRDXKH

2

7.5

40

2.5

1.5

16.0

—

—

—

—

8.5

60

—

— ns ns

% ns ns

RX_CLK clock rise time V

IL

(min) to V

IH

(max) t

TRXR

RX_CLK clock fall time V

IH

(max) to V

IL

(min) t

TRXF

0.7

0.7

—

—

2.4

2.4

ns ns

Note:



for inputs and t



TRDVKH

symbolizes TBI receive timing

(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

TRX


TRDXKH

symbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the t

TRX

clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t

TRX

represents the TBI

(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).

2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.

28




Figure 13

shows the TBI receive AC timing diagram.

t

TRX

PMA_RX_CLK1 t

TRXH t

TRXF t

TRXR

RCG[9:0] Even RCG Odd RCG t

TRDVKH t

SKTRX t

TRDXKH

PMA_RX_CLK0 t

TRXH t

TRDVKH t

TRDXKH

Figure 13. TBI Receive AC Timing Diagram

8.2.4

RGMII and RTBI AC Timing

Specifications

Table 27

presents the RGMII and RTBI AC timing specifications.

Table 27. RGMII and RTBI AC Timing Specifications


DD

of 2.5 V ± 5%.


1


Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

2

Clock cycle duration

3

Duty cycle for 1000Base-T

4, 5

Duty cycle for 10BASE-T and 100BASE-TX

3, 5 t t

SKRGT

SKRGT t

RGT t

RGTH

/t

RGT

–0.5

1.0

7.2

45

—

—

8.0

50

0.5

2.8

8.8

55 ns ns ns

%

Rise time (20%–80%)

Fall time (20%–80%)

GTX_CLK125 reference clock period

GTX_CLK125 reference clock duty cycle t

RGTH

/t

RGT t

RGTR t

RGTF t

G12

6 t

G125H

/t

G125

40

—

—

—

47

50

—

—

8.0

—

60

0.75

0.75

—

53

% ns ns ns

%

Notes:

1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of t

RGT

represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).

2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal.

3. For 10 and 100 Mbps, t

RGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t

RGT

of the lowest speed transitioned.

5. Duty cycle reference is LV

DD

/2.

6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention.




Figure 14

shows the RBMII and RTBI AC timing and multiplexing diagrams.

t

RGT t

RGTH

GTX_CLK

(At Transmitter) t

SKRGT

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[3:0]

TXD[8:5]

TXD[7:4]

TX_CTL

TXD[4]

TXEN

TXD[9]

TXERR

TX_CLK

(At PHY) t

SKRGT

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[3:0]

RXD[8:5]

RXD[7:4] t

SKRGT

RX_CTL

RXD[4]

RXDV

RXD[9]

RXERR

RX_CLK

(At PHY)

Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams

t

SKRGT

30




8.3

Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to the MII management interface signals management data input/output (MDIO) and management data clock (MDC). The electrical characteristics for GMII,

RGMII, TBI and RTBI are specified in

Section 8.1, “Three-Speed Ethernet Controller (TSEC)—

GMII/MII/TBI/RGMII/RTBI Electrical Characteristics .”

8.3.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 2.5 or 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in

Table 28 and Table 29 .

Table 28. MII Management DC Electrical Characteristics Powered at 2.5 V


Supply voltage (2.5 V)

Output high voltage

Output low voltage

Input high voltage

LV

DD

V

V

V

OH

OL

IH

—

I

OH

= –1.0 mA LV

DD

= Min

I

OL

= 1.0 mA

—

LV

DD

= Min

LV

DD

= Min

2.37

2.00

GND – 0.3

1.7

Input low voltage

Input high current

V

I

IL

IH

— LV

DD

= Min

V

IN

1

= LV

DD

V

IN

= LV

DD

–0.3

—

Input low current I

IL

–15

Note:

1. The symbol V

IN


IN


Table 1 and

Table 2

.

Max

2.63

LV

DD

+ 0.3

0.40

—

0.70

10

—

Unit

V

V

V

V

V

μ

A

μ

A

Table 29. MII Management DC Electrical Characteristics Powered at 3.3 V


Supply voltage (3.3 V)

Output high voltage

Output low voltage

Input high voltage

LV

DD

V

OH

V

OL

V

IH

I

OH

I

OL

= –1.0 mA

= 1.0 mA

—

—

LV

LV

DD

DD

= Min

= Min

2.97

2.10

GND

2.00

Input low voltage

Input high current

Input low current

V

IL

I

IH

I

IL

LV

LV

DD

DD

= Max

= Max

—

V

IN

1

= 2.1 V

V

IN

= 0.5 V

—

—

–600

Note:

1. The symbol V

IN


IN


Table 1 and

Table 2

.

Max

3.63

LV

DD

+ 0.3

0.50

—

0.80

40

—

Unit

V

V

V

V

V

μ

A

μ

A




8.3.2

MII Management AC Electrical Specifications

Table 30

provides the MII management AC timing specifications.

Table 30. MII Management AC Timing Specifications


DD

is 3.3 V ± 10% or 2.5 V ± 5%.


1

Min Typ Max Unit Notes

MDC frequency

MDC period

MDC clock pulse width high

MDC to MDIO delay f

MDC t

MDC t

MDCH t

MDKHDX

—

—

32

10

2.5

400

—

—

—

—

—

170

MHz ns ns ns

2

3

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time

MDC fall time t

MDDVKH t

MDDXKH t

MDCR t

MDHF

5

0

—

—

—

—

—

—

—

—

10

10 ns ns ns ns

Notes:



for inputs and t



MDKHDX

symbolizes management data timing (MD) for the time t

MDC

from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, t

MDDVKH

symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MDC

clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz).

3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of

333 MHz, the delay is 58 ns).

Figure 15

shows the MII management AC timing diagram.

t

MDC

MDC t

MDCH t

MDCF

MDIO

(Input) t

MDDVKH t

MDCR t

MDDXKH

MDIO

(Output) t

MDKHDX

Figure 15. MII Management Interface Timing Diagram

32



USB

9 USB

This section provides the AC and DC electrical specifications for the USB interface of the MPC8347E.

9.1

USB DC Electrical Characteristics

Table 31

provides the DC electrical characteristics for the USB interface.

Table 31. USB DC Electrical Characteristics

Parameter



Input current


OH

= –100

μ

A


OL

= 100

μ

A

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

Min

2

–0.3

—

OV

DD

– 0.2

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.2

9.2

USB AC Electrical Specifications

Table 32

describes the general timing parameters of the USB interface of the MPC8347E.

Table 32. USB General Timing Parameters


1


USB clock cycle time

Input setup to USB clock—all inputs

Input hold to USB clock—all inputs

USB clock to output valid—all outputs t

USCK t

USIVKH t

USIXKH t

USKHOV

15

4

1

—

—

—

—

7 ns ns ns ns

2–5

2–5

2–5

2–5

Output hold from USB clock—all outputs t

USKHOX

2 — ns 2–5

Notes:


(First two letters of functional block)(signal)(state)(reference)(state)

for inputs and t

(First two letters of functional block)(reference)(state)(signal)(state)


USIXKH

symbolizes USB timing (US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t

USKHOX

symbolizes

USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to USB clock.

3. All signals are measured from OV

DD

/2 of the rising edge of the USB clock to 0.4

×

OV

DD

of the signal in question for 3.3 V signaling levels.

4. Input timings are measured at the pin.

5. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification.

Unit

V

V

μ

A

V

V



USB

Figure 16

and

Figure 17 provide the AC test load and signals for the USB, respectively.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 16. USB AC Test Load

USB0_CLK/USB1_CLK/DR_CLK t

USIXKH t

USIVKH

Input Signals

Output Signals: t

USKHOV t

USKHOX

Figure 17. USB Signals

34



Local Bus

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the

MPC8347E.

10.1

Local Bus DC Electrical Characteristics

Table 33

provides the DC electrical characteristics for the local bus interface.

Table 33. Local Bus DC Electrical Characteristics

Parameter



Input current


OH

= –100

μ

A


OL

= 100

μ

A

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

Min

2

–0.3

—

OV

DD

– 0.2

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.2

10.2

Local Bus AC Electrical Specification

Table 34

and Table 35 describe the general timing parameters of the local bus interface of the MPC8347E.

Table 34. Local Bus General Timing Parameters—DLL On


1


Local bus cycle time

Input setup to local bus clock (except LUPWAIT)

LUPWAIT input setup to local bus clock

Input hold from local bus clock (except LUPWAIT)

LUPWAIT Input hold from local bus clock

LALE output fall to LAD output transition (LATCH hold time)



Local bus clock to LALE rise

Local bus clock to output valid (except LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

Local bus clock to address valid for LAD

Output hold from local bus clock (except LAD/LDP and LALE) t

LBK t

LBIVKH1 t

LBIVKH2 t

LBIXKH1 t

LBIXKH2 t

LBOTOT1 t

LBOTOT2 t

LBOTOT3 t

LBKHLR t

LBKHOV1 t

LBKHOV2 t

LBKHOV3 t

LBKHOX1

1.0

1.5

3

2.5

7.5

1.5

2.2

1.0

—

—

—

—

1

—

—

—

—

—

—

—

—

4.5

4.5

4.5

4.5

— ns ns ns ns ns ns ns ns ns ns ns ns ns

3

3

3

3, 4

5

6

7

2

3, 4

3, 4

3, 4

Unit

V

V

μ

A

V

V



Local Bus

Table 34. Local Bus General Timing Parameters—DLL On (continued)


1


Output hold from local bus clock for LAD/LDP

Local bus clock to output high impedance for LAD/LDP t

LBKHOX2 t

LBKHOZ

1

—

—

3.8

ns ns

3

8

Notes:



for inputs and t



LBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t

LBK

(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK clock reference (K) goes high (H), in this case for clock one clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to the rising edge of LSYNC_IN.


DD

/2 of the rising edge of LSYNC_IN to 0.4

×

OV

DD



5. t

LBOTOT1

should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins.

6. t

LBOTOT2

should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins.

7. t

LBOTOT3

should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD output pins.

8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification.

Table 35. Local Bus General Timing Parameters—DLL Bypass

9


1

Min Max

Local bus cycle time

Input setup to local bus clock

Input hold from local bus clock



LALE output fall to LAD output transition (LATCH hold time) t

LBK t

LBIVKH t

LBIXKH t

LBOTOT1 t

LBOTOT2 t

LBOTOT3

15

7

1.0

1.5

3

2.5

—

—

—

—

—

—

Unit

ns ns ns ns ns ns

Notes

2

3, 4

3, 4

5

6

7

36



Local Bus

Table 35. Local Bus General Timing Parameters—DLL Bypass

9

(continued)


1


Local bus clock to output valid

Local bus clock to output high impedance for LAD/LDP t

LBKHOV t

LBKHOZ

—

—

3

4 ns ns

3

8

Notes:



for inputs and t



LBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t

LBK

(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK clock reference (K) goes high (H), in this case for clock one clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge of LCLK0 (for all other inputs).


DD

/2 of the rising/falling edge of LCLK0 to 0.4

×

OV

DD



5. t

LBOTOT1

should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins.

6. t

LBOTOT2

should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins.the

7. t

LBOTOT3

should be used when RCWH[LALE] is set and when the load on the LALE output pin equals to the load on the LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.

9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.

Figure 18

provides the AC test load for the local bus.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 18. Local Bus C Test Load



Local Bus

Figure 19

through Figure 24 show the local bus signals.

LSYNC_IN t

LBIXKH t

LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE t

LBKHOV t

LBIXKH t

LBKHOV t

LBKHOZ t

LBKHOX

Output (Data) Signals:

LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOZ t

LBKHOX

Output (Address) Signal:

LAD[0:31] t

LBKHLR t

LBOTOT

LALE

Figure 19. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)

LCLK[n] t

LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

Input Signal:

LGTA

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE

Output Signals:

LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOV t

LBIXKH t

LBKHOZ t

LBIVKH t

LBKLOV t

LBOTOT

LALE

Figure 20. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)

t

LBIXKH

38



Local Bus

LSYNC_IN

T1

T3 t

LBKHOZ1 t

LBKHOV1

GPCM Mode Output Signals:

LCS[0:3]/LWE t

LBIXKH2 t

LBIVKH2

UPM Mode Input Signal:

LUPWAIT t

LBIXKH1 t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3] t

LBKHOZ1 t

LBKHOV1

LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)

LCLK

T1

T3 t

LBKHOZ t

LBKHOV


LCS[0:3]/LWE t

LBIXKH t

LBIVKH


LUPWAIT t

LBIXKH t

LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode) t

LBKHOZ t

LBKHOV

UPM Mode Output Signals:

LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)



Local Bus

LCLK

T1

T2

T3

T4 t

LBKHOZ t

LBKHOV


LCS[0:3]/LWE t

LBIXKH t

LBIVKH


LUPWAIT t

LBIXKH t

LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode) t

LBKHOZ t

LBKHOV


LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)

40



LSYNC_IN

T1

T2

T3

T4 t

LBKHOZ1 t

LBKHOV1


LCS[0:3]/LWE t

LBIXKH2 t

LBIVKH2


LUPWAIT t

LBIXKH1 t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3] t

LBKHOZ1 t

LBKHOV1


LCS[0:3]/LBS[0:3]/LGPL[0:5]

Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)

Local Bus



JTAG

11 JTAG

This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8347E

11.1

JTAG DC Electrical Characteristics

Table 36

provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the

MPC8347E.

Table 36. JTAG interface DC Electrical Characteristics

Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

Output low voltage


V

IH

V

IL

I

IN

V

OH

V

OL

V

OL

Condition Min Max

I

OH

= –8.0 mA

I

OL

= 8.0 mA

I

OL

= 3.2 mA

OV

DD

– 0.3

OV

DD

+ 0.3

–0.3

0.8

2.4

—

—

±5

—

0.5

0.4

Unit

V

V

μ

A

V

V

V

11.2

JTAG AC Timing Specifications

This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the

MPC8347E.

Table 37

provides the JTAG AC timing specifications as defined in Figure 26 through

Figure 29

.

Table 37. JTAG AC Timing Specifications (Independent of CLKIN)

1

At recommended operating conditions (see Table 2 ).


2


JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

Input setup times:

Boundary-scan data

TMS, TDI

Input hold times:

Boundary-scan data

TMS, TDI

Valid times:

Boundary-scan data

TDO f

JTG t

JTG t

JTKHKL t

JTGR

, t

JTGF t

TRST t

JTDVKH t

JTIVKH t

JTDXKH t

JTIXKH t

JTKLDV t

JTKLOV

0

30

15

0

25

10

10

2

2

4

4

33.3

—

—

2

—

—

—

—

—

11

11

MHz ns ns ns ns ns ns ns

3

4

4

5

42



JTAG

Table 37. JTAG AC Timing Specifications (Independent of CLKIN)

1

(continued)

At recommended operating conditions (see Table 2 ).


2


Output hold times: ns

Boundary-scan data

TDO t

JTKLDX t

JTKLOX

2

2

—

—

5

JTAG external clock to output high impedance:

Boundary-scan data

TDO t

JTKLDZ t

JTKLOZ

2

2

19

9 ns

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t

TCLK

to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50

Ω

load (see Figure 25

).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.



for inputs and t



JTDVKH

symbolizes JTAG device timing

(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

JTG


JTDXKH

symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t

JTG

clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t

TCLK

.

5. Non-JTAG signal output timing with respect to t

TCLK

.

6. Guaranteed by design and characterization.

Figure 25

provides the AC test load for TDO and the boundary-scan outputs of the MPC8347E.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 25. AC Test Load for the JTAG Interface

Figure 26

provides the JTAG clock input timing diagram.

JTAG

External Clock

VM VM VM t

JTKHKL t

JTG

VM = Midpoint Voltage (OVDD/2) t

JTGR

Figure 26. JTAG Clock Input Timing Diagram

t

JTGF



JTAG

Figure 27

provides the TRST timing diagram.

TRST VM VM t

TRST

VM = Midpoint Voltage (OVDD/2)

Figure 27. TRST Timing Diagram

Figure 28

provides the boundary-scan timing diagram.

JTAG

External Clock

VM VM t

JTDVKH t

JTDXKH

Boundary

Data Inputs

Input

Data Valid t

JTKLDV t

JTKLDX

Boundary

Data Outputs

Output Data Valid

Boundary

Data Outputs t

JTKLDZ

Output Data Valid


Figure 28. Boundary-Scan Timing Diagram

Figure 29

provides the test access port timing diagram.

JTAG

External Clock

VM VM t

JTIVKH t

JTIXKH

TDI, TMS

Input

Data Valid t

JTKLOV t

JTKLOX

TDO Output Data Valid

TDO t

JTKLOZ

Output Data Valid


Figure 29. Test Access Port Timing Diagram

44



12 I

2

C

This section describes the DC and AC electrical characteristics for the I

2

C interface of the MPC8347E.

I

2

C

12.1

I

2

C DC Electrical Characteristics

Table 38

provides the DC electrical characteristics for the I

2

C interface of the MPC8347E.

Table 38. I

2

C DC Electrical Characteristics

At recommended operating conditions with OV

DD

of 3.3 V ± 10%.

Input high voltage level

Input low voltage level

Parameter

Low level output voltage

Output fall time from V

IH

(min) to V

IL

(max) with a bus capacitance from 10 to 400 pF

Symbol

t

V

V

V

IH

IL

OL

I2KLKV

0.7

Min

×

–0.3

0

OV

DD

20 + 0.1

×

C

B

Max

OV

DD

+ 0.3

0.3

×

OV

DD

0.2

×

OV

DD

250

Unit

V

V

V ns

Notes

1

2

Pulse width of spikes which must be suppressed by the input filter t

I2KHKL

0 50 ns 3

Input current each I/O pin (input voltage is between

0.1

×

OV

DD

and 0.9

×

OV

DD

(max)

Capacitance for each I/O pin

I

I

–10 10

μ

A 4

C

I

— 10 pF

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C

B

= capacitance of one bus line in pF.

3. Refer to the MPC8349E PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual, for information on the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if OV

DD

is switched off.

12.2

I

2

C AC Electrical Specifications

Table 39

provides the AC timing parameters for the I

2

C interface of the MPC8347E. Note that all values refer to V

IH

(min) and V

IL

(max) levels (see

Table 39

).

Table 39. I

2

C AC Electrical Specifications


1

Min Max Unit

SCL clock frequency

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated START condition

Hold time (repeated) START condition (after this period, the first clock pulse is generated)

Data setup time

Data hold time: CBUS compatible masters

I

2

C bus devices f

I2C t

I2CL t

I2CH t

I2SVKH t

I2SXKL t

I2DVKH t

I2DXKL

0

1.3

0.6

0.6

0.6

100

—

0

2

400

—

—

—

—

—

—

0.9

3 kHz

μ s

μ s

μ s

μ s ns

μ s



I

2

C

Table 39. I

2

C AC Electrical Specifications (continued)

Parameter

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Noise margin at the LOW level for each connected device (including hysteresis)

Noise margin at the HIGH level for each connected device (including hysteresis)

Symbol

t t t

I2CR t

I2CF

I2PVKH

I2KHDX

V

V

NL

NH

1

Min

20 + 0.1 C

20 + 0.1 C

0.6

1.3

0.1

×

OV

0.2

×

OV b

4 b

4

DD

DD

Max

300

300

—

—

—

—

Unit

ns ns

μ s

μ s

V

V

Notes:

1. The symbols for timing specifications follow the pattern of t and t




I2DVKH

symbolizes I

2

for inputs

C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t

I2C


I2SXKL

symbolizes I

2

C timing (I2) for the time that the data with respect to the start condition (S) goes invalid (X) relative to the t

I2C

clock reference (K) going to the low (L) state or hold time. Also, t

I2PVKH

symbolizes I

2

C timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the t

I2C

clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. MPC8347E provides a hold time of at least 300 ns for the SDA signal (referred to the V

IH

(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

3. The maximum t

I2DVKH

must be met only if the device does not stretch the LOW period (t

I2CL

) of the SCL signal.

4. C

B

= capacitance of one bus line in pF.

Figure 30

provides the AC test load for the I

2

C.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 30. I

2

C AC Test Load

Figure 31

shows the AC timing diagram for the I

2

C bus.

SDA

SCL

S t

I2CF t

I2CL t

I2SXKL t

I2DVKH t

I2SXKL t

I2KHKL t

I2CR t

I2CH t

I2SVKH t

I2DXKL Sr

Figure 31. I

2

C Bus AC Timing Diagram

t

I2PVKH

P t

I2CF

S

46



PCI

13 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8347E.

13.1

PCI DC Electrical Characteristics

Table 40

provides the DC electrical characteristics for the PCI interface of the MPC8347E.

Table 40. PCI DC Electrical Characteristics

Parameter Symbol Test Condition



Input current

High-level output voltage

V

V

V

I

IH

IL

IN

OH

V

OUT

≥

V

OH

(min) or

V

OUT

≤

V

OL

(max)

V

IN

1

= 0 V or V

IN

= OV

DD

I

OV

DD

OH

= min,

= –100

μ

A

Low-level output voltage V

OL

I

OV

DD

OL

= min,

= 100

μ

A

Note:

1. The symbol V

IN

, in this case, represents the OV

IN


Table 1 .

Min

2

–0.3

—

OV

DD

– 0.2

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.2

Unit

V

V

μ

A

V

V

13.2

PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the MPC8347E. Note that the

PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8347E

is configured as a host or agent device. Table 41

provides the PCI AC timing specifications at 66 MHz.

Table 41. PCI AC Timing Specifications at 66 MHz

1


2


Clock to output valid

Output hold from clock t

PCKHOV t

PCKHOX

—

1

6.0

— ns ns

3

3

Clock to output high impedance

Input setup to clock t

PCKHOZ t

PCIVKH

—

3.0

14

— ns ns

3, 4

3, 5

Input hold from clock t

PCIXKH

0 — ns 3, 5

Notes:

1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a description of M66EN.



for inputs and t



PCIVKH

symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t

SYS

, reference (K) going to the high (H) state or setup time. Also, t

PCRHFV

symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

3. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.




PCI

Table 42

provides the PCI AC timing specifications at 33 MHz.

Table 42. PCI AC Timing Specifications at 33 MHz


1


Clock to output valid

Output hold from clock t

PCKHOV t

PCKHOX

—

2

11

— ns ns

2

2

Clock to output high impedance

Input setup to clock t

PCKHOZ t

PCIVKH

—

3.0

14

— ns ns

2, 3

2, 4

Input hold from clock t

PCIXKH

0 — ns 2, 4

Notes:



for inputs and t



PCIVKH

symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t

SYS

, reference (K) going to the high (H) state or setup time. Also, t

PCRHFV

symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.


Figure 32

provides the AC test load for PCI.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 32. PCI AC Test Load

Figure 33

shows the PCI input AC timing diagram.

CLK t

PCIVKH t

PCIXKH

Input

Figure 33. PCI Input AC Timing Diagram

48



Figure 34

shows the PCI output AC timing diagram.

CLK t

PCKHOV t

PCKHOX

Output Delay t

PCKHOZ

High-Impedance

Output

Figure 34. PCI Output AC Timing Diagram

PCI



Timers

14 Timers

This section describes the DC and AC electrical specifications for the timers.

14.1

Timer DC Electrical Characteristics

Table 43

provides the DC electrical characteristics for the MPC8347E timer pins, including TIN, TOUT,

TGATE, and RTC_CLK.

Table 43. Timer DC Electrical Characteristics

Condition Characteristic

Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

Output low voltage

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

V

OL

I

OH

= –8.0 mA

I

OL

= 8.0 mA

I

OL

= 3.2 mA

Min

2.0

–0.3

2.4

—

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.5

0.4

Unit

V

V

μ

A

V

V

V

14.2

Timer AC Timing Specifications

Table 44

provides the timer input and output AC timing specifications.

Table 44. Timers Input AC Timing Specifications

1


2

Min Unit

Timers inputs—minimum pulse width t

TIWID

20 ns

Notes:

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.

Timings are measured at the pin.

2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external synchronous logic. Timer inputs are required to be valid for at least t

TIWID ns to ensure proper operation.

50



GPIO

15 GPIO

This section describes the DC and AC electrical specifications for the GPIO.

15.1

GPIO DC Electrical Characteristics

Table 45

provides the DC electrical characteristics for the MPC8347E GPIO.

Table 45. GPIO DC Electrical Characteristics


Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

Output low voltage

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

V

OL

I

OH

= –8.0 mA

I

OL

= 8.0 mA

I

OL

= 3.2 mA

Min

2.0

–0.3

2.4

—

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.5

0.4

15.2

GPIO AC Timing Specifications

Table 46

provides the GPIO input and output AC timing specifications.

Table 46. GPIO Input AC Timing Specifications

1


2

Min Unit

GPIO inputs—minimum pulse width t

PIWID

20 ns

Notes:



2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least t

PIWID

ns to ensure proper operation.

Unit

V

V

μ

A

V

V

V



IPIC

16 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins.

16.1

IPIC DC Electrical Characteristics

Table 47

provides the DC electrical characteristics for the external interrupt pins.

Table 47. IPIC DC Electrical Characteristics

1

Characteristic Symbol Condition Min

Input high voltage

Input low voltage

V

IH

V

IL

2.0

–0.3

Input current

Output low voltage

I

IN

V

OL

I

OL

= 8.0 mA —

Output low voltage V

OL

I

OL

= 3.2 mA —

Notes:

1. This table applies for pins IRQ[0:7], IRQ_OUT, and MCP_OUT.

2. IRQ_OUT and MCP_OUT are open-drain pins; thus V

OH

is not relevant for those pins.

Max

OV

DD

+ 0.3

0.8

±5

0.5

0.4

Unit Notes

V

V

μ

A

V

V

2

2

16.2

IPIC AC Timing Specifications

Table 48

provides the IPIC input and output AC timing specifications.

Table 48. IPIC Input AC Timing Specifications

1


2

Min Unit

IPIC inputs—minimum pulse width t

PICWID

20 ns

Notes:



2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least t

PICWID ns to ensure proper operation in edge triggered mode.

52



SPI

17 SPI

This section describes the SPI DC and AC electrical specifications.

17.1

SPI DC Electrical Characteristics

Table 49

provides the SPI DC electrical characteristics.

Table 49. SPI DC Electrical Characteristics


Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

Output low voltage

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

V

OL

I

OH

= –8.0 mA

I

OL

= 8.0 mA

I

OL

= 3.2 mA

Min

2.0

–0.3

2.4

—

—

Max

OV

DD

+ 0.3

0.8

±5

—

0.5

0.4

17.2

SPI AC Timing Specifications

Table 50

provides the SPI input and output AC timing specifications.

Table 50. SPI AC Timing Specifications

1


2

Min Max Unit

SPI outputs valid—Master mode (internal clock) delay

SPI outputs hold—Master mode (internal clock) delay

SPI outputs valid—Slave mode (external clock) delay

SPI outputs hold—Slave mode (external clock) delay t

NIKHOV t

NIKHOX t

NEKHOV t

NEKHOX

0.5

2

6

8 ns ns ns ns

SPI inputs—Master mode (internal clock input setup time

SPI inputs—Master mode (internal clock input hold time

SPI inputs—Slave mode (external clock) input setup time

SPI inputs—Slave mode (external clock) input hold time t

NIIVKH t

NIIXKH t

NEIVKH t

NEIXKH

4

0

4

2 ns ns ns ns

Notes:

1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.




for inputs and t



NIKHOX

symbolizes the internal timing

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Unit

V

V

μ

A

V

V

V



SPI

Figure 35

provides the AC test load for the SPI.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 35. SPI AC Test Load

Figure 36 and Figure 37 represent the AC timings from

Table 50 . Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

Figure 36

shows the SPI timings in slave mode (external clock).

SPICLK (Input) t

NEIXKH t

NEIVKH

Input Signals:

SPIMOSI

(See Note) t

NEKHOX

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 36. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 37

shows the SPI timings in master mode (internal clock).

SPICLK (Output) t

NIIXKH t

NIIVKH

Input Signals:

SPIMISO

(See Note) t

NIKHOX

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 37. SPI AC Timing in Master Mode (Internal Clock) Diagram

54



Package and Pin Listings

18 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8347E is available in two packages—a tape ball grid array (TBGA) and a plastic ball grid array (PBGA). See

Section 18.1,

“Package Parameters for the MPC8347E TBGA,”

Section 18.2, “Mechanical Dimensions for the

MPC8347E TBGA,”

Section 18.3, “Package Parameters for the MPC8347E PBGA,”

and Section 18.4,

“Mechanical Dimensions for the MPC8347E PBGA.”

18.1

Package Parameters for the MPC8347E TBGA

The package parameters are provided in the following list. The package type is 35 mm

× 35 mm, 672 tape ball grid array (TBGA).

Package outline 35 mm

× 35 mm

Interconnects 672

Pitch

Module height (typical)

Solder Balls

Ball diameter (typical)

1.00 mm

1.46 mm

62 Sn/36 Pb/2 Ag (ZU package)

95.5 Sn/0.5 Cu/4Ag (VV package)

0.64 mm




18.2

Mechanical Dimensions for the MPC8347E TBGA

Figure 38

shows the mechanical dimensions and bottom surface nomenclature for the MPC8347E

672-TBGA package.

Notes:

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

5. Parallelism measurement must exclude any effect of mark on top surface of package.

Figure 38. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347E TBGA

56




18.3

Package Parameters for the MPC8347E PBGA

The package parameters are as provided in the following list. The package type is 29 mm

× 29 mm,

620 plastic ball grid array (PBGA).

Package outline

Interconnects

Pitch

Module height (maximum)

Module height (typical)

Module height (minimum)

Solder Balls

Ball diameter (typical)

29 mm

× 29 mm

620

1.00 mm

2.46 mm

2.23 mm

2.00 mm

62 Sn/36 Pb/2 Ag (ZQ package)

95.5 Sn/0.5 Cu/4Ag (VR package)

0.60 mm




18.4

Mechanical Dimensions for the MPC8347E PBGA

Figure 39

shows the mechanical dimensions and bottom surface nomenclature for the MPC8347E

620-PBGA package.

58

Notes:

1. All dimensions are in millimeters.

2. Dimensioning and tolerancing per ASME Y14. 5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

Figure 39. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8347E PBGA




18.5

Pinout Listings

Table 51 provides the pinout listing for the MPC8347E 672 TBGA package.

Table 51. MPC8347E (TBGA) Pinout Listing

Signal

PCI_INTA/IRQ_OUT

PCI_RESET_OUT

PCI_AD[31:0]

PCI_C/BE[3:0]

PCI_PAR

PCI_FRAME

PCI_TRDY

PCI_IRDY

PCI_STOP

PCI_DEVSEL

PCI_IDSEL

PCI_SERR

PCI_PERR

PCI_REQ[0]

PCI_REQ[1]/CPCI1_HS_ES

PCI_REQ[2:4]

PCI_GNT0

PCI_GNT1/CPCI1_HS_LED

PCI_GNT2/CPCI1_HS_ENUM

PCI_GNT[3:4]

M66EN

MDQ[0:63]

MECC[0:4]/MSRCID[0:4]

Package Pin Number Pin Type

J30, M31, P33, T34

P32

M32

N29

M34

N31

N30

J31

N34

N33

PCI

B34

C33

G30, G32, G34, H31, H32, H33, H34,

J29, J32, J33, L30, K31, K33, K34,

L33, L34, P34, R29, R30, R33, R34,

T31, T32, T33, U31, U34, V31, V32,

V33, V34, W33, W34

D32

D34

I/O

I

E34, F32, G29 I

C34 I/O

D33

E33

F31, F33

A19

DDR SDRAM Memory Interface

D5, A3, C3, D3, C4, B3, C2, D4, D2,

E5, G2, H6, E4, F3, G4, G3, H1, J2,

L6, M6, H2, K6, L2, M4, N2, P4, R2,

T4, P6, P3, R1, T2, AB5, AA3, AD6,

AE4, AB4, AC2, AD3, AE6, AE3, AG4,

AK5, AK4, AE2, AG6, AK3, AK2, AL2,

AL1, AM5, AP5, AM2, AN1, AP4, AN5,

AJ7, AN7, AM8, AJ9, AP6, AL7, AL9,

AN8

W4, W3, Y3, AA6, T1

I/O

I/O

O

O

O

I

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

I/O

Power

Supply

Notes

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

GV

DD

GV

DD



2

5

5

5

5

5

5

5

59


Table 51. MPC8347E (TBGA) Pinout Listing (continued)

Signal Package Pin Number

MECC[5]/MDVAL

MECC[6:7]

MDM[0:8]

MDQS[0:8]

MBA[0:1]

MA[0:14]

MWE

MRAS

MCAS

MCS[0:3]

MCKE[0:1]

MCK[0:5]

MCK[0:5]

MODT[0:3]

MBA[2]

SPARE1

SPARE2

LAD[0:31]

LDP[0]/CKSTOP_OUT

LDP[1]/CKSTOP_IN

LDP[2]

LDP[3]

LA[27:31]

LCS[0:3]

LWE[0:3]/LSDDQM[0:3]/LBS[0:3]

LBCTL

U1

Y1, Y6

B1, F1, K1, R4, AD4, AJ1, AP3, AP7,

Y4

B2, F5, J1, P2, AC1, AJ2, AN4, AL8,

W2

AD1, AA5

W1, U4, T3, R3, P1, M1, N1, L3, L1,

K2, Y2, K3, J3, AP2, AN6

AF1

AF4

AG3

AG2, AG1, AK1, AL4

H3, G1

U2, F4, AM3, V3, F2, AN3

U3, E3, AN2, V4, E1, AM4

Pins Reserved for Future DDR2

(They should be left unconnected for MPC8347E)

AH3, AJ5, AH1, AJ4

H4

AA1

AB1

Local Bus Controller Interface

AM13, AP13, AL14, AM14, AN14,

AP14, AK15, AJ15, AM15, AN15,

AP15, AM16, AL16, AN16, AP16,

AL17, AM17, AP17, AK17, AP18,

AL18, AM18, AN18, AP19, AN19,

AM19, AP20, AK19, AN20, AL20,

AP21, AN21

AM21

AP22

AN22

AM22

AK21, AP23, AN23, AP24, AK22

AN24, AL23, AP25, AN25

AK23, AP26, AL24, AM25

AN26

Pin Type

I/O

I/O

O

I/O

O

O

O

O

O

O

O

O

O

—

—

—

—

I/O

Power

Supply

GV

DD

GV

DD

GV

GV

GV

GV

DD

—

—

—

—

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

OV

DD

DD

DD

DD

I/O OV

DD

I/O OV

DD

I/O

I/O

OV

DD

OV

DD

O

O

O

O

OV

DD

OV

DD

OV

DD

OV

DD

Notes

3

8

6

60






LALE

LGPL0/LSDA10/cfg_reset_source0

LGPL1/LSDWE/cfg_reset_source1

LGPL2/LSDRAS/LOE

LGPL3/LSDCAS/cfg_reset_source2

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5/cfg_clkin_div

LCKE

AK24

AP27

AL25

AJ24

AN27

AP28

AL26

AM27

LCLK[0:2]

LSYNC_OUT

LSYNC_IN

GPIO1[0]/GTM1_TIN1/GTM2_TIN2

GPIO1[1]/GTM1_TGATE1/GTM2_TGATE2

GPIO1[2]/GTM1_TOUT1



GPIO1[5]/GTM1_TOUT2/GTM2_TOUT1



GPIO1[8]/GTM1_TOUT3


B23

A23

GPIO1[10]/GTM1_TGATE4/GTM2_TGATE3 F22

GPIO1[11]/GTM1_TOUT4/GTM2_TOUT3 E22

A25

B24

A24

D23

F24

E24

B25

D24

AN28, AK26, AP29

AM12

AJ10

General Purpose I/O Timers

USB Port 1

MPH1_D0_ENABLEN/DR_D0_ENABLEN

MPH1_D1_SER_TXD/DR_D1_SER_TXD

MPH1_D2_VMO_SE0/DR_D2_VMO_SE0

MPH1_D3_SPEED/DR_D3_SPEED

MPH1_D4_DP/DR_D4_DP

MPH1_D5_DM/DR_D5_DM

MPH1_D6_SER_RCV/DR_D6_SER_RCV

MPH1_D7_DRVVBUS/DR_D7_DRVVBUS

MPH1_NXT/DR_SESS_VLD_NXT

A26

B26

D25

A27

B27

C27

D26

E26

D27

Pin Type

I/O

I/O

I/O

O

O

I/O

I/O

O

O

O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Power

Supply

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Notes






MPH1_DIR_DPPULLUP/

DR_XCVR_SEL_DPPULLUP

MPH1_STP_SUSPEND/

DR_STP_SUSPEND

MPH1_PWRFAULT/

DR_RX_ERROR_PWRFAULT

MPH1_PCTL0/DR_TX_VALID_PCTL0

MPH1_PCTL1/DR_TX_VALIDH_PCTL1

MPH1_CLK/DR_CLK

A28

F26

E27

A29

D28

B29

USB Port 0

MPH0_D0_ENABLEN/DR_D8_CHGVBUS C29

MPH0_D1_SER_TXD/DR_D9_DCHGVBUS A30

MPH0_D2_VMO_SE0/DR_D10_DPPD E28

MPH0_D3_SPEED/DR_D11_DMMD

MPH0_D4_DP/DR_D12_VBUS_VLD

MPH0_D5_DM/DR_D13_SESS_END

MPH0_D6_SER_RCV/DR_D14

B30

C30

A31

B31

MPH0_D7_DRVVBUS/DR_D15_IDPULLUP C31

MPH0_NXT/DR_RX_ACTIVE_ID B32

MPH0_DIR_DPPULLUP/DR_RESET

MPH0_STP_SUSPEND/DR_TX_READY

A32

A33

MPH0_PWRFAULT/DR_RX_VALIDH

MPH0_PCTL0/DR_LINE_STATE0


MPH0_CLK/DR_RX_VALID

C32

D31

E30

B33

MCP_OUT

IRQ0/MCP_IN/GPIO2[12]

IRQ[1:5]/GPIO2[13:17]

IRQ[6]/GPIO2[18]/CKSTOP_OUT

IRQ[7]/GPIO2[19]/CKSTOP_IN

EC_MDC

EC_MDIO

EC_GTX_CLK125

Programmable Interrupt Controller

AN33

C19

C22, A22, D21, C21, B21

A21

C20

Ethernet Management Interface

A7

E9

Gigabit Reference Clock

C8

Pin Type

I/O

O

O

I/O

I/O

I/O

I/O

O

O

I

O

I/O

I

I

I

I/O

I/O

I

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Power

Supply

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Notes

LV

DD1

LV

DD1

LV

DD1

2

2

62





Signal Package Pin Number Pin Type

Power

Supply

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_COL/GPIO2[20]

TSEC1_CRS/GPIO2[21]

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RX_ER/GPIO2[26]

TSEC1_RXD[7:4]/GPIO2[22:25]

TSEC1_RXD[3:0]

TSEC1_TX_CLK

TSEC1_TXD[7:4]/GPIO2[27:30]

TSEC1_TXD[3:0]

TSEC1_TX_EN

TSEC1_TX_ER/GPIO2[31]

A17

F12

D10

A11

B11

B17

B16, D16, E16, F16

E10, A8, F10, B8

D17

A15, B15, A14, B14

A10, E11, B10, A9

B9

A16

I/O

I/O

O

I

I

I/O

I/O

I

I

I/O

O

O

I/O

TSEC2_COL/GPIO1[21]

TSEC2_CRS/GPIO1[22]

TSEC2_GTX_CLK

TSEC2_RX_CLK

TSEC2_RX_DV/GPIO1[23]




TSEC2_TXD[7]/GPIO1[31]


C14

TSEC2_TXD[6]/DR_XCVR_TERM_SEL

TSEC2_TXD[5]/DR_UTMI_OPMODE1




TSEC2_TX_EN/GPIO1[12]

TSEC2_TX_CLK/GPIO1[30]

D6

A4

B4

E6

A13, B13, C13, A12

D7, A6, E8, B7

D14

B12

C12

D12

E12

B5, A5, F8, B6

F14

C5

E14

I/O

I/O

O

OV

DD

LV

DD2

LV

DD2

I LV

DD2

I/O LV

DD2

I/O OV

DD

I/O LV

DD2

I/O OV

DD

I/O OV

DD

O OV

DD

O OV

DD

O

I/O

OV

DD

LV

DD2

I/O OV

DD

I/O LV

DD2

I/O OV

DD

DUART

OV

DD

LV

DD1

LV

DD1

LV

DD1

LV

DD1

OV

DD

OV

DD

LV

DD1

OV

DD

OV

DD

LV

DD1

LV

DD1

OV

DD

UART_SOUT[1:2]/MSRCID[0:1]/LSRCID[0:1] AK27, AN29

UART_SIN[1:2]/MSRCID[2:3]/LSRCID[2:3]

UART_CTS[1]/MSRCID4/LSRCID4

AL28, AM29

AP30

O

I/O

I/O

OV

DD

OV

DD

OV

DD

Notes

3

3




Signal

UART_CTS[2]/MDVAL/ LDVAL

UART_RTS[1:2]

IIC1_SDA

IIC1_SCL

IIC2_SDA

IIC2_SCL

SPIMOSI

SPIMISO

SPICLK

SPISEL

PCI_CLK_OUT[0:4]

PCI_SYNC_IN/PCI_CLOCK

PCI_SYNC_OUT

RTC/PIT_CLOCK

CLKIN

TCK

TDI

TDO

TMS

TRST

TEST

TEST_SEL

QUIESCE

PORESET

HRESET

SRESET

THERM0


Package Pin Number

E20

F20

B20

A20

B19

AN30

AP31, AM30

I

2

C interface

AK29

AP32

AN31

AM31

SPI

AN32

AP33

AK30

AL31

Clocks

AN9, AP9, AM10, AN10, AJ11

AK12

AP11

AM32

AM9

JTAG

Test

D22

AL13

PMC

A18

System Control

C18

B18

D18

Thermal Management

K32

Pin Type

I/O

O

O

I

O

I

I

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I

I/O

I/O

I

I

O

I

O

I

I

I

I

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

—

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Power

Supply

OV

DD

OV

DD

Notes

2

2

2

2

3

6

7

1

2

9

4

3

4

4

64



AV

DD

1

AV

DD

2

AV

DD

3

AV

DD

4

GND

GV

DD

LV

DD

1

LV

DD

2

V

DD

Signal




Power

Supply

Power and Ground Signals

L31

AP12

AE1

AJ13

Power for e300

PLL (1.2 V)

Power for system PLL

(1.2 V)

Power for DDR

DLL (1.2 V)

Power for LBIU

DLL (1.2 V)

A1, A34, C1, C7, C10, C11, C15, C23,

C25, C28, D1, D8, D20, D30, E7, E13,

E15, E17, E18, E21, E23, E25, E32,

F6, F19, F27, F30, F34, G31, H5, J4,

J34, K30, L5, M2, M5, M30, M33, N3,

N5, P30, R5, R32, T5, T30, U6, U29,

U33, V2, V5, V30, W6, W30, Y30,

AA2, AA30, AB2, AB6, AB30, AC3,

AC6, AD31, AE5, AF2, AF5, AF31,

AG30, AG31, AH4, AJ3, AJ19, AJ22,

AK7, AK13, AK14, AK16, AK18, AK20,

AK25, AK28, AL3, AL5, AL10, AL12,

AL22, AL27, AM1, AM6, AM7, AN12,

AN17, AN34, AP1, AP8, AP34

—

A2, E2, G5, G6, J5, K4, K5, L4, N4, P5,

R6, T6, U5, V1, W5, Y5, AA4, AB3,

AC4, AD5, AF3, AG5, AH2, AH5, AH6,

AJ6, AK6, AK8, AK9, AL6

Power for DDR

DRAM I/O voltage

(2.5 V)

C9, D11

C6, D9

Power for three-speed

Ethernet #1 and for

Ethernet management interface I/O

(2.5 V, 3.3 V)


Ethernet #2

I/O (2.5 V,

3.3 V)

E19, E29, F7, F9, F11,F13, F15, F17,

F18, F21, F23, F25, F29, H29, J6,

K29, M29, N6, P29, T29, U30, V6,

V29, W29, AB29, AC5, AD29, AF6,

AF29, AH29, AJ8, AJ12, AJ14, AJ16,

AJ18, AJ20, AJ21, AJ23, AJ25, AJ26,

AJ27, AJ28, AJ29, AK10

Power for core

(1.2 V)

AV

DD

1

AV

DD

2

AV

DD

3

AV

DD

4

GV

LV

LV

V

—

DD

DD

DD

DD

1

2

Notes






Power

Supply

Notes

OV

DD

B22, B28, C16, C17, C24, C26, D13,

D15, D19, D29, E31, F28, G33, H30,

L29, L32, N32, P31, R31, U32, W31,

Y29, AA29, AC30, AE31, AF30, AG29,

AJ17, AJ30, AK11, AL15, AL19, AL21,

AL29, AL30, AM20, AM23, AM24,

AM26, AM28, AN11, AN13

PCI, 10/100

Ethernet, and other standard

(3.3 V)

MVREF1 M3 I

OV

DD

MVREF2 AD2 I

DDR reference voltage


NC

No Connection

W32, AA31, AA32, AA33, AA34,

AB31, AB32, AB33, AB34, AC29,

AC31, AC33, AC34, AD30, AD32,

AD33, AD34, AE29, AE30, AH32,

AH33, AH34, AM33, AJ31, AJ32,

AJ33, AJ34, AK32, AK33, AK34,

AM34, AL33, AL34, AK31, AH30,

AC32, AE32, AH31, AL32, AG34,

AE33, AF32, AE34, AF34, AF33,

AG33, AG32, AL11, AM11, AP10, Y32,

Y34, Y31, Y33

—

Notes:

1. This pin is an open-drain signal. A weak pull-up resistor (1 k

Ω

) should be placed on this pin to OV

DD

.

2. This pin is an open-drain signal. A weak pull-up resistor (2–10 k

Ω


DD

.

3. During reset, this output is actively driven rather than three-stated.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.

6. This pin must always be tied to GND.

7. This pin must always be pulled up to OV

DD

.

8. This pin must always be left not connected.

9. Thermal sensitive resistor.

—

66




Table 52 provides the pinout listing for the MPC8347E 620 PBGA package.

Table 52. MPC8347E (PBGA) Pinout Listing


PCI

PCI1_INTA/IRQ_OUT

PCI1_RESET_OUT

D20

B21

PCI1_AD[31:0]

PCI1_C/BE[3:0]

PCI1_PAR

PCI1_FRAME

D13

B14

PCI1_TRDY A13

PCI1_IRDY E13

PCI1_STOP C13

E19, D17, A16, A18, B17, B16, D16,

B18, E17, E16, A15, C16, D15, D14,

C14, A12, D12, B11, C11, E12, A10,

C10, A9, E11, E10, B9, B8, D9, A8,

C9, D8, C8

A17, A14, A11, B10

PCI1_DEVSEL

PCI1_IDSEL

PCI1_SERR

B13

C17

C12

PCI1_PERR B12

PCI1_REQ[0] A21

PCI1_REQ[1]/CPCI1_HS_ES C19

PCI1_REQ[2:4]

PCI1_GNT0

PCI1_GNT1/CPCI1_HS_LED

PCI1_GNT2/CPCI1_HS_ENUM

PCI1_GNT[3:4]

M66EN

MDQ[0:63]

C18, A19, E20

B20

C20

B19

A20, E18

L26

DDR SDRAM Memory Interface

AC25, AD27, AD25, AH27, AE28,

AD26, AD24, AF27, AF25, AF28,

AH24, AG26, AE25, AG25, AH26,

AH25, AG22, AH22, AE21, AD19,

AE22, AF23, AE19, AG20, AG19,

AD17, AE16, AF16, AF18, AG18,

AH17, AH16, AG9, AD12, AG7, AE8,

AD11, AH9, AH8, AF6, AF8, AE6,

AF1, AE4, AG8, AH3, AG3, AG4, AH2,

AD7, AB4, AB3, AG1, AD5, AC2, AC1,

AC4, AA3, Y4, AA4, AB1, AB2, Y5, Y3

Pin Type

O

O

I/O

I/O

I/O

I

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

O

O

O

I

Power

Supply

Notes

OV

DD

OV

DD

OV

DD

2

5

5 OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

GV

DD

5

5

5

5

5




Table 52. MPC8347E (PBGA) Pinout Listing (continued)


MECC[0:4]/MSRCID[0:4]

MECC[5]/MDVAL

MECC[6:7]

MDM[0:8]

MDQS[0:8]

MBA[0:1]

MA[0:14]

MWE

MRAS

MCAS

MCS[0:3]

MCKE[0:1]

MCK[0:5]

MCK[0:5]

MODT[0:3]

MBA[2]

SPARE1

SPARE2

LAD[0:31]

LDP[0]/CKSTOP_OUT

LDP[1]/CKSTOP_IN

LDP[2]

LDP[3]

LA[27:31]

LCS[0:3]

LWE[0:3]/LSDDQM[0:3]/LBS[0:3]

LBCTL

AG13, AE14, AH12, AH10, AE15

AH14

AE13, AH11

AG28, AG24, AF20, AG17, AE9, AH5,

AD1, AA2, AG12

AE27, AE26, AE20, AH18, AG10, AF5,

AC3, AA1, AH13

AF10, AF11

AF13, AF15, AG16, AD16, AF17,

AH20, AH19, AH21, AD18, AG21,

AD13, AF21, AF22, AE1, AA5

AD10

AF7

AG6

AE7, AH7, AH4, AF2

AG23, AH23

AH15, AE24, AE2, AF14, AE23, AD3

AG15, AD23, AE3, AG14, AF24, AD2

Pins Reserved for Future DDR2

(They should be left unconnected for MPC8347E)

AG5, AD4, AH6, AF4

AD22

AF12

AG11

Local Bus Controller Interface

T4, T5, T1, R2, R3, T2, R1, R4, P1, P2,

P3, P4, N1, N4, N2, N3, M1, M2, M3,

N5, M4, L1, L2, L3, K1, M5, K2, K3, J1,

J2, L5, J3

H1

K5

H2

G1

J4, H3, G2, F1, G3

J5, H4, F2, E1

F3, G4, D1, E2

H5

I/O

I/O

I/O

O

I/O

O

O

O

O

O

O

O

O

O

—

—

—

I/O

GV

GV

GV

DD

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

—

—

—

OV

DD

DD

I/O OV

DD

I/O OV

DD

I/O

I/O

OV

DD

OV

DD

O

O

O

O

OV

DD

OV

DD

OV

DD

OV

DD

Power

Supply

GV

DD

GV

DD

GV

DD

GV

DD

Notes

3

7

6

68






LALE

LGPL0/LSDA10/cfg_reset_source0

LGPL1/LSDWE/cfg_reset_source1

LGPL2/LSDRAS/LOE

LGPL3/LSDCAS/cfg_reset_source2

LGPL4/LGTA/LUPWAIT/LPBSE

LGPL5/cfg_clkin_div

LCKE

LCLK[0:2]

LSYNC_OUT

LSYNC_IN



GPIO1[2]/GTM1_TOUT1



GPIO1[5]/GTM1_TOUT2/GTM2_TOUT1



GPIO1[8]/GTM1_TOUT3

E27

E28

H25

GPIO1[9]/GTM1_TIN4/GTM2_TIN3 F27

GPIO1[10]/GTM1_TGATE4/GTM2_TGATE3 K24

GPIO1[11]/GTM1_TOUT4/GTM2_TOUT3 G26

D27

E26

D28

G25

J24

F26

E3

F4

D2

C1

C2

C3

B3

E4

D4, A3, C4

U3

Y2

General Purpose I/O Timers

USB Port 1

MPH1_D0_ENABLEN/DR_D0_ENABLEN

MPH1_D1_SER_TXD/DR_D1_SER_RXD

MPH1_D2_VMO_SE0/DR_D2_VMO_SE0

MPH1_D3_SPEED/DR_D3_SPEED

MPH1_D4_DP/DR_D4_DP

MPH1_D5_DM/DR_D5_DM

MPH1_D6_SER_RCV/DR_D6_SER_RCV

MPH1_D7_DRVVBUS/DR_D7_DRVVBUS

MPH1_NXT/DR_SESS_VLD_NXT

C28

F25

B28

C27

D26

E25

C26

D25

B26

Pin Type

I/O

O

O

O

I

O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Power

Supply

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Notes






MPH1_DIR_DPPULLUP/

DR_XCVR_SEL_DPPULLUP

MPH1_STP_SUSPEND/

DR_STP_SUSPEND

MPH1_PWRFAULT/

DR_RX_ERROR_PWRFAULT

MPH1_PCTL0/DR_TX_VALID_PCTL0

MPH1_PCTL1/DR_TX_VALIDH_PCTL1

MPH1_CLK/DR_CLK

E24

A27

C25

A26

B25

A25

USB Port 0

MPH0_D0_ENABLEN/DR_D8_CHGVBUS D24

MPH0_D1_SER_TXD/DR_D9_DCHGVBUS C24

MPH0_D2_VMO_SE0/DR_D10_DPPD B24

MPH0_D3_SPEED/DR_D11_DMMD

MPH0_D4_DP/DR_D12_VBUS_VLD

A24

D23

MPH0_D5_DM/DR_D13_SESS_END

MPH0_D6_SER_RCV/DR_D14

C23

B23

MPH0_D7_DRVVBUS/DR_D15_IDPULLUP A23

MPH0_NXT/DR_RX_ACTIVE_ID

MPH0_DIR_DPPULLUP/DR_RESET

MPH0_STP_SUSPEND/DR_TX_READY

MPH0_PWRFAULT/DR_RX_VALIDH



MPH0_CLK/DR_RX_VALID

D22

C22

B22

A22

E21

D21

MCP_OUT

IRQ0/MCP_IN/GPIO2[12]

IRQ[1:5]/GPIO2[13:17]

IRQ[6]/GPIO2[18]/CKSTOP_OUT

IRQ[7]/GPIO2[19]/CKSTOP_IN

C21

Programmable Interrupt Controller

E8

J28

K25, J25, H26, L24, G27

G28

EC_MDC

EC_MDIO

J26

Ethernet Management Interface

Y24

Y25

Pin Type

I/O

O

I

O

I/O

I/O

I/O

I/O

O

O

I

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O

I

I/O

I/O

I

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

LV

DD1

LV

DD1

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Power

Supply

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Notes

2

2

70






Power

Supply

EC_GTX_CLK125

Gigabit Reference Clock

Y26


I LV

DD1

TSEC1_COL/GPIO2[20]

TSEC1_CRS/GPIO2[21]

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV



TSEC1_RXD[3:0]

TSEC1_TX_CLK


TSEC1_TXD[3:0]

TSEC1_TX_EN


TSEC2_COL/GPIO1[21]

TSEC2_CRS/GPIO1[22]

TSEC2_GTX_CLK

TSEC2_RX_CLK

TSEC2_RX_DV/GPIO1[23]




TSEC2_TXD[7]/GPIO1[31]

TSEC2_TXD[6]/DR_XCVR_TERM_SEL





TSEC2_TX_EN/GPIO1[12]

TSEC2_TX_CLK/GPIO1[30]

M26

U25

V24

U26

U24

L28

M27, M28, N26, N27

W26, W24, Y28, Y27

N25

N28, P25, P26, P27

V28, V27, V26, W28

W27

AC26

R28, T24, T25, T26

T27

T28

U28

U27

AD28

R26

I/O

I/O

O

I/O

I

I

I

I

I/O

I/O

O

O

N24


I/O

P28

AC28

AC27

AB25

AA25, AA26, AA27, AA28

R25

AB26, AB27, AA24, AB28

R27

I/O

I/O

O

I

OV

DD

LV

DD2

LV

DD2

LV

DD2

I/O LV

DD2

I/O OV

DD

I/O LV

DD2

I/O OV

DD

I/O OV

DD

O OV

DD

O OV

DD

O OV

DD

I/O LV

DD2

I/O OV

DD

I/O LV

DD2

I/O OV

DD

OV

DD

LV

DD1

OV

DD

OV

DD

LV

DD1

LV

DD1

OV

DD

OV

DD

LV

DD1

LV

DD1

LV

DD1

LV

DD1

OV

DD

Notes

3

3





Pin Type Signal Package Pin Number

DUART

UART_SOUT[1:2]/MSRCID[0:1]/LSRCID[0:1] B4, A4

UART_SIN[1:2]/MSRCID[2:3]/LSRCID[2:3] D5, C5

UART_CTS[1]/MSRCID4/LSRCID4

UART_CTS[2]/MDVAL/LDVAL

UART_RTS[1:2]

B5

A5

D6, C6

IIC1_SDA

IIC1_SCL

IIC2_SDA

IIC2_SCL

SPIMOSI

SPIMISO

SPICLK

SPISEL

PCI_CLK_OUT[0:2]

PCI_CLK_OUT[3]/LCS[6]

PCI_CLK_OUT[4]/LCS[7]

PCI_SYNC_IN/PCI_CLOCK

PCI_SYNC_OUT

RTC/PIT_CLOCK

CLKIN

W1

V3

U4

U5

E9

W5

I

2

C interface

E5

A6

B6

E7

SPI

D7

C7

B7

A7

Y1, W3, W2

Clocks

JTAG

TCK

TDI

TDO

TMS

TRST

H27

H28

M24

J27

K26

Test

TEST

TEST_SEL

F28

T3

O

I/O

I/O

I/O

O

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

I

I

O

I

I

I

I

O

I

I

O

I

O

O

Power

Supply

Notes

3

6

6

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

2

2

2

2

4

3

4

4

72



QUIESCE

PORESET

HRESET

SRESET

THERM0

AV

DD

1

AV

DD

2

AV

DD

3

AV

DD

4

GND

GV

DD

Signal




Power

Supply

PMC

K27 O

System Control

K28

M25

L27

I

I/O

I/O

Thermal Management

B15

Power and Ground Signals

C15

I

U1

AF9

U2

Power for e300

PLL (1.2 V)

Power for system PLL

(1.2 V)

Power for DDR

DLL (1.2 V)

Power for LBIU

DLL (1.2 V)

A2, B1, B2, D10, D18, E6, E14, E22,

F9, F12, F15, F18, F21, F24, G5, H6,

J23, L4, L6, L12, L13, L14, L15, L16,

L17, M11, M12, M13, M14, M15, M16,

M17, M18, M23, N11, N12, N13, N14,

N15, N16, N17, N18, P6, P11, P12,

P13, P14, P15, P16, P17, P18, P24,

R5, R11, R12, R13, R14, R15, R16,

R17, R18, R23, T11, T12, T13, T14,

T15, T16, T17, T18, U6, U11, U12,

U13, U14, U15, U16, U17, U18, V12,

V13, V14, V15, V16, V17, V23, V25,

W4, Y6, AA23, AB24, AC5, AC8,

AC11, AC14, AC17, AC20, AD9,

AD15, AD21, AE12, AE18, AF3, AF26

—

U9, V9, W10, W19, Y11, Y12, Y14,

Y15, Y17, Y18, AA6, AB5, AC9, AC12,

AC15, AC18, AC21, AC24, AD6, AD8,

AD14, AD20, AE5, AE11, AE17, AG2,

AG27

Power for DDR

DRAM I/O voltage

(2.5 V)

OV

OV

OV

OV

DD

DD

DD

—

AV

DD

1

AV

DD

2

AV

DD

3

AV

DD

4

—

GV

DD

DD

Notes

1

2

8






Power

Supply

Notes

LV

LV

V

DD

OV

DD

DD

DD

1

2

U20, W25

V20, Y23


Ethernet #1 and for

Ethernet management interface I/O

(2.5 V, 3.3 V)


Ethernet #2

I/O (2.5 V,

3.3 V)

J11, J12, J15, K10, K11, K12, K13,

K14, K15, K16, K17, K18, K19, L10,

L11, L18, L19, M10, M19, N10, N19,

P9, P10, P19, R10, R19, R20, T10,

T19, U10, U19, V10, V11, V18, V19,

W11, W12, W13, W14, W15, W16,

W17, W18

Power for core

(1.2 V)

B27, D3, D11, D19, E15, E23, F5, F8,

F11, F14, F17, F20, G24, H23, H24,

J6, J14, J17, J18, K4, L9, L20, L23,

L25, M6, M9, M20, P5, P20, P23, R6,

R9, R24, U23, V4, V6

PCI, 10/100

Ethernet, and other standard

(3.3 V)

MVREF1 AF19 I

LV

LV

V

DD

DD

DD

OV

1

2

DD

MVREF2 AE10 I

NC

No Connection

V1, V2, V5

Notes:

1. This pin is an open-drain signal. A weak pull-up resistor (1 k

Ω


DD

.

2. This pin is an open-drain signal. A weak pull-up resistor (2–10 k

Ω


DD

.

3. During reset, this output is actively driven rather than three-stated.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.

6. This pin must always be tied to GND.

7. This pin must always be left not connected.

8. Thermal sensitive resistor.



74



Clocking

19 Clocking

Figure 40

shows the internal distribution of the clocks.

MPC8347E e300 Core

Core PLL core_clk

CFG_CLKIN_DIV

CLKIN

System PLL csb_clk

Clock

Unit

To DDR

Memory

Controller ddr_clk

DDR

Clock

Div

/2 lbiu_clk

/n

To Local Bus

Memory

Controller

LBIU

DLL csb_clk to Rest of the Device

6

6

MCK[0:5]

MCK[0:5]

DDR

Memory

Device

LCLK[0:2]

LSYNC_OUT

Local Bus

Memory

Device

LSYNC_IN

PCI_CLK/

PCI_SYNC_IN

PCI_SYNC_OUT

PCI Clock

Divider

5

PCI_CLK_OUT[0:4]

Figure 40. MPC8347E Clock Subsystem

The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the MPC8347E is configured as a PCI host device,

CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (

÷2) and the multiplexors for

PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether

CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the MPC8347E to function. When the

MPC8347E is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND.



Clocking

As shown in Figure 40 , the primary clock input (frequency) is multiplied up by the system phase-locked

loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the

DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the

csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset, clocking, and initialization in the MPC8349E Reference Manual for more information on the clock subsystem.

The internal ddr_clk frequency is determined by the following equation:

ddr_clk = csb_clk × (1 + RCWL[DDRCM])

ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (

÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk.

The internal lbiu_clk frequency is determined by the following equation:

lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])

lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is controlled by LCCR[CLKDIV].

In addition, some of the internal units may have to be shut off or operate at lower frequency than the

csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped

register after the device exits reset. Table 53 specifies which units have a configurable clock frequency.

Table 53. Configurable Clock Units

Unit

TSEC1

TSEC2, I

2

C1

Security Core

USB DR, USB MPH

PCI and DMA complex

Default

Frequency

csb_clk/3 csb_clk/3 csb_clk/3 csb_clk/3 csb_clk

Options

Off, csb_clk, csb_clk/2, csb_clk/3




Off, csb_clk

76



Clocking

Table 54

provides the operating frequencies for the MPC8347E TBGA under recommended operating conditions (see

Table 2 ).

Table 54. Operating Frequencies for TBGA

Characteristic

1

400 MHz 533 MHz 667 MHz Unit

e300 core frequency ( core_clk)

Coherent system bus frequency ( csb_clk)

DDR memory bus frequency (MCLK)

2

Local bus frequency (LCLK n)

3

PCI input frequency (CLKIN or PCI_CLK)

Security core maximum internal operating frequency

266–400

100–266

100–133

16.67–133

25–66

133

266–533

100–333

100–133

16.67–133

25–66

133

266–667

100–333

100–166.67

16.67–133

25–66

166

MHz

MHz

MHz

MHz

MHz

MHz

USB_DR, USB_MPH maximum internal operating frequency

133 133 166 MHz

2

3

1

The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,

LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.

The DDR data rate is 2x the DDR memory bus frequency.

The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]).

Table 55

provides the operating frequencies for the MPC8347E PBGA under recommended operating conditions.

Table 55. Operating Frequencies for PBGA

Characteristic

1

266 MHz 333 MHz 400 MHz Unit

e300 core frequency ( core_clk)

Coherent system bus frequency ( csb_clk)

DDR memory bus frequency (MCLK)

2

Local bus frequency (LCLK n)

3

PCI input frequency (CLKIN or PCI_CLK)

Security core maximum internal operating frequency

200–266 200–333

100–266

100–133

16.67–133

25–66

133

200–400 MHz

MHz

MHz

MHz

MHz

MHz

USB_DR, USB_MPH maximum internal operating frequency

133 MHz

2

3

1

The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,

LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.

The DDR data rate is 2x the DDR memory bus frequency.

The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]).



Clocking

19.1

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter.

Table 56

shows the multiplication factor encodings for the system PLL.

Table 56. System PLL Multiplication Factors

RCWL[SPMF]

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

System PLL Multiplication

Factor

× 12

× 13

× 14

× 15

× 8

× 9

× 10

× 11

× 16

Reserved

× 2

× 3

× 4

× 5

× 6

× 7

As described in Section 19, “Clocking,”

the LBIUCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 57

and

Table 58 show the expected frequency values for the CSB frequency for select csb_clk to

CLKIN/PCI_SYNC_IN ratios.

78



CFG_CLKIN_DIV at Reset

1

Table 57. CSB Frequency Options for Host Mode

Input Clock Frequency (MHz)

2

SPMF csb_clk :

Input Clock

Ratio

2

16.67

25 33.33

66.67

csb_clk Frequency (MHz)

Low

Low

Low

High

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

1010

1011

1100

1101

1110

1111

0000

0010

0010

0011

0100

0101

0110

0111

1000

1001

10 : 1

11 : 1

12 : 1

13 : 1

14 : 1

15 : 1

16 : 1

2 : 1

6 : 1

7 : 1

8 : 1

9 : 1

2 : 1

3 : 1

4 : 1

5 : 1

100

116

133

150

166

183

200

216

233

250

266

100

125

150

175

200

225

250

275

300

325

High

High

High

High

0011

0100

0101

0110

3 : 1

4 : 1

5 : 1

6 : 1

High 0111 7 : 1

High 1000 8 : 1

1

2

CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

100

133

166

200

233

233

266

300

333

100

133

166

200

133

200

266

333

133

200

266

333

Clocking



Clocking

CFG_CLKIN_DIV at Reset

1

Table 58. CSB Frequency Options for Agent Mode

Input Clock Frequency (MHz)

2

SPMF csb_clk :

Input Clock

Ratio

2

16.67

25 33.33

66.67

csb_clk Frequency (MHz)

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

High

Low

Low

Low

Low

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0010

2 : 1

3 : 1

4 : 1

5 : 1

6 : 1

7 : 1

8 : 1

9 : 1

10 : 1

11 : 1

12 : 1

13 : 1

14 : 1

15 : 1

16 : 1

4 : 1

100

116

133

150

166

183

200

216

233

250

266

High

High

High

High

0011

0100

0101

0110

6 : 1

8 : 1

10 : 1

12 : 1

100

133

166

200

100

150

200

250

300

High 0111 14 : 1 233

High 1000 16 : 1 266

1

2

CFG_CLKIN_DIV doubles csb_clk if set high.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

200

225

250

275

100

125

150

175

300

325

133

200

266

333

233

266

300

333

100

133

166

200

133

200

266

333

266

19.2

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 59

shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in Table 59 should be considered as reserved.

80



Clocking

NOTE

Core VCO frequency = core frequency

× VCO divider

VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz.

Table 59. e300 Core PLL Configuration

RCWL[COREPLL] core_clk : csb_clk Ratio VCO Divider

1

0–1 2–5 6 nn

00

01

10

11

00

01

10

11

00

01

10

0000

0001

0001

0001

0001

0001

0001

0001

0001

0010

0010

0010

n

0

0

0

0

1

1

1

1

0

0

0

PLL bypassed

(PLL off, csb_clk clocks core directly)

1:1

1:1

1:1

1:1

1.5:1

1.5:1

1.5:1

1.5:1

2:1

2:1

2:1

PLL bypassed

(PLL off, csb_clk clocks core directly)

2

4

8

8

2

4

8

8

2

4

8

11

00

01

10

0010

0010

0010

0010

1

1

0

1

2:1

2.5:1

2.5:1

2.5:1

4

8

8

2

11

00

01

10

0010

0011

0011

0011

1

0

0

0

2.5:1

3:1

3:1

3:1

8

2

4

8

11 0011

0 3:1 8

1

Core VCO frequency = core frequency

×

VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800–1800 MHz.

19.3

Suggested PLL Configurations

Table 60

shows suggested PLL configurations for 33 and 66 MHz input clocks.



Clocking

Table 60. Suggested PLL Configurations

Ref

No.

1

RCWL 400 MHz Device 533 MHz Device 667 MHz Device

SPMF

CORE

PLL

Input

Clock

Freq

(MHz)

2

CSB

Freq

(MHz)

Core

Freq

(MHz)

Input

Clock

Freq

(MHz)

2

CSB

Freq

(MHz)

Core

Freq

(MHz)

Input

Clock

Freq

(MHz)

2

CSB

Freq

(MHz)

Core

Freq

(MHz)

705

606

904

805

704

724

A03

804

803

823

903

923

922

723

604

624

A04

304

324

403

423

305

503

1001 0100010

0111 0100011

0110 0000100

0110 0100100

1000 0000011

1000 0100011

1001 0000011

1001 0100011

0111 0000011

0111 0100011

1010 0000011

1000 0000100

0111 0000101

0110 0000110

1001 0000100

1000 0000101

1010 0000100

0011 0000100

0011 0100100

0100 0000011

0100 0100011

0011 0000101

0101 0000011

—

33

33

33

33

33

66

66

66

66

—

—

—

—

—

—

—

—

—

200

266

266

—

—

33 MHz CLKIN/PCI_CLK Options

— — —

233

200

350

400

33

33

233

200

400

400

400

33

33

33

200

266

266

—

33

33

33 266

—

—

—

—

—

233

233

—

— —

66 MHz CLKIN/PCI_CLK Options

200

200

266

266

—

—

400

400

400

400

66

66

66

66

66

200

200

266

266

200

—

300

350

400

400

400

400

466

466

533

400

400

400

400

500

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

66

66

66

66

66

66

200

200

266

266

200

333

400

400

400

400

500

500

404

306

405

0100 0000100

0011 0000110

0100 0000101

—

—

—

66 266

—

—

533 66

66

66

266

200

266

533

600

667

504 0101 0000100

— — 66 333 667

1

2

The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and

COREPLL settings given in the table.

The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode.

233

200

300

266

233

233

333

266

266

266

300

300

300

233

200

200

333

583

600

600

667

466

466

500

533

400

400

450

450

300

350

400

400

667

82



Thermal

20 Thermal

This section describes the thermal specifications of the MPC8347E.

20.1

Thermal Characteristics

Table 61

provides the package thermal characteristics for the 672 35

× 35 mm TBGA of the MPC8347E.

Table 61. Package Thermal Characteristics for TBGA

Characteristic Symbol Value Unit Notes

Junction-to-ambient natural convection on single-layer board (1s)

Junction-to-ambient natural convection on four-layer board (2s2p)

Junction-to-ambient (@ 200 ft/min) on single-layer board (1s)

Junction-to-ambient (@ 200 ft/min) on four-layer board (2s2p)

Junction-to-ambient (@ 2 m/s) on single-layer board (1s)

Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p)

Junction-to-board thermal

Junction-to-case thermal

Junction-to-package natural convection on top

R

θ

JA

R

θ

JMA

R

θ

JMA

R

θ

JMA

R

θ

JMA

R

θ

JMA

R

θ

JB

R

θ

JC

ψ

JT

14

11

11

8

9

7

3.8

1.7

1

°

°

°

°

°

°

°

°

°

C/W

C/W

C/W

C/W

C/W

C/W

C/W

C/W

C/W

1, 2

1, 3

1, 3

1, 3

1, 3

1, 3

4

5

6

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM).

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 62

provides the package thermal characteristics for the 620 29

× 29 mm PBGA of the MPC8347E.

Table 62. Package Thermal Characteristics for PBGA

Characteristic

Junction-to-ambient natural convection on single-layer board (1s)

Junction-to-ambient natural convection on four-layer board (2s2p)

Junction-to-ambient (@ 200 ft/min) on single-layer board (1s)

Junction-to-ambient (@ 200 ft/min) on four-layer board (2s2p)

Junction-to-board thermal

Symbol

R

θ

JA

R

θ

JMA

R

θ

JMA

R

θ

JMA

R

θ

JB

Value

21

15

17

12

6

Unit Notes

°

C/W

°

C/W

°

C/W

°

C/W

°

C/W

1, 2

1, 3

1, 3

1, 3

4



Thermal

Table 62. Package Thermal Characteristics for PBGA (continued)

Characteristic Symbol Value Unit Notes

Junction-to-case thermal

Junction-to-package natural convection on top

R

θ

JC

ψ

JT

5

5

°

°

C/W

C/W

5

6

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

20.2

Thermal Management Information

For the following sections, P

D

= (V

DD

× I

DD

) + P

See

Table 5 for I/O power dissipation values.

I/O

where P

I/O

is the power dissipation of the I/O drivers.

20.2.1

Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, T

J

, can be obtained from the equation:

T

J

= T

A

+ (R

θ

JA

× P

D

) where:

T

J

= junction temperature (

°C)

T

A

= ambient temperature for the package (

°C)

R

θ

JA

= junction-to-ambient thermal resistance (

°C/W)

P

D

= power dissipation in the package (W)

The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Generally, the value obtained on a single-layer board is appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity T

J

– T

A

) are possible.

20.2.2

Estimation of Junction Temperature with Junction-to-Board


The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of

84



Thermal

surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter

(edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T

J

= T

A

+ (R

θ

JA

× P

D

) where:

T

J


°C)

T

A

= ambient temperature for the package (

°C)

R

θ

JA


°C/W)

P

D


When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.

20.2.3

Experimental Determination of Junction Temperature

To determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter (

Ψ

JT

) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation:

T

J

= T

T

+ (

Ψ

JT

× P

D

) where:

T

J


°C)

T

T

= thermocouple temperature on top of package (

°C)

Ψ

JT


°C/W)

P

D


The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type

T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

20.2.4

Heat Sinks and Junction-to-Case Thermal Resistance

Some application environments require a heat sink to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

R

θ

JA

= R

θ

JC

+ R

θ

CA



Thermal

where:

R

θ

JA


°C/W)

R

θ

JC

= junction-to-case thermal resistance (

°C/W)

R

θ

CA

= case-to-ambient thermal resistance (

°C/W)

R

θ

JC

is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, R

θ

CA

. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device.

The thermal performance of devices with heat sinks has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required.

Table 63

and

Table 64

show heat sink thermal resistance for TBGA and PBGA of the MPC8347E.

Table 63. Heat Sink and Thermal Resistance of MPC8347E (TBGA)

35

×

35 mm TBGA

Heat Sink Assuming Thermal Grease Air Flow


AAVID 30

×

30

×

9.4 mm pin fin

AAVID 30

×

30

×

9.4 mm pin fin

AAVID 30

×

30

×

9.4 mm pin fin

AAVID 31

×

35

×

23 mm pin fin

AAVID 31

×

35

×

23 mm pin fin

AAVID 31

×

35

×

23 mm pin fin

Wakefield, 53

×

53

×

25 mm pin fin

Wakefield, 53

×

53

×

25 mm pin fin

Wakefield, 53

×

53

×

25 mm pin fin

MEI, 75

×

85

×

12 no adjacent board, extrusion

MEI, 75

×

85

×


MEI, 75

×

85

×


MEI, 75

×

85

×

12 mm, adjacent board, 40 mm side bypass

Natural convection

1 m/s

2 m/s

Natural convection

1 m/s

2 m/s

Natural convection

1 m/s

2 m/s

Natural convection

1 m/s

2 m/s

1 m/s

6.7

4.1

2.8

3.1

4

5.7

3.5

2.7

10

6.5

5.6

8.4

4.7

f

Table 64. Heat Sink and Thermal Resistance of MPC8347E (PBGA)

29

×

29 mm PBGA



AAVID 30

×

30

×

9.4 mm pin fin

AAVID 30

×

30

×

9.4 mm pin fin

Natural convection

1 m/s

13.5

9.6

86



Table 64. Heat Sink and Thermal Resistance of MPC8347E (PBGA) (continued)

29

×

29 mm PBGA


AAVID 30

×

30

×

9.4 mm pin fin

AAVID 31

×

35

×

23 mm pin fin

AAVID 31

×

35

×

23 mm pin fin

AAVID 31

×

35

×

23 mm pin fin

Wakefield, 53

×

53

×

25 mm pin fin

Wakefield, 53

×

53

×

25 mm pin fin

Wakefield, 53

×

53

×

25 mm pin fin

MEI, 75

×

85

×


MEI, 75

×

85

×


MEI, 75

×

85

×


MEI, 75

×

85

×

12 mm, adjacent board, 40 mm side bypass

2 m/s

Natural convection

1 m/s

2 m/s

Natural convection

1 m/s

2 m/s

Natural convection

1 m/s

2 m/s

1 m/s


9.1

7.1

6.5

10.1

8.8

11.3

8.1

7.5

7.7

6.6

6.9

Thermal

Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request.

Heat sink vendors include the following list:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

Alpha Novatech

473 Sapena Ct. #12

Santa Clara, CA 95054

Internet: www.alphanovatech.com

408-567-8082

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

408-436-8770 Millennium Electronics (MEI)

Loroco Sites

671 East Brokaw Road

San Jose, CA 95112

Internet: www.mei-thermal.com



Thermal

Tyco Electronics

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

Interface material vendors include the following:

Chomerics, Inc.

77 Dragon Ct.

Woburn, MA 01801

Internet: www.chomerics.com

Dow-Corning Corporation

Dow-Corning Electronic Materials

P.O. Box 994

Midland, MI 48686-0997

Internet: www.dowcorning.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

Internet: www.microsi.com

The Bergquist Company

18930 West 78th St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

800-522-2800

603-635-5102

781-935-4850

800-248-2481

888-642-7674

800-347-4572

20.3

Heat Sink Attachment

When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip.

The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. The recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements.

20.3.1

Experimental Determination of the Junction Temperature with a

Heat Sink

When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally

88



Thermal

required in the heat sink. Minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.

T

J

= T

C

+ (R

θ

JC

× P

D

) where:

T

J


°C)

T

C

= case temperature of the package (

°C)

R

θ

JC

= junction-to-case thermal resistance (

°C/W)

P

D

= power dissipation (W)



System Design Information

21 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8347E.

21.1

System Clocking

The MPC8347E includes two PLLs.

1. The platform PLL (AV

DD

1

) generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in

Section 19.1, “System PLL Configuration.”

2. The e300 core PLL (AV

DD

2

) generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300

PLL ratio configuration bits as described in Section 19.2, “Core PLL Configuration.”

21.2

PLL Power Supply Filtering

Each PLL gets power through independent power supply pins (AV

DD

1, AV

DD

2, respectively). The AV

DD level should always equal to V

DD

, and preferably these voltages are derived directly from V low frequency filter scheme.

DD

through a

There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to

provide five independent filter circuits as illustrated in Figure 41

, one to each of the five AV

DD

pins.

Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.

The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic

(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor.

To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the specific AV

DD

pin being supplied. It should be possible to route directly from the capacitors to the AV

DD pin, which is on the periphery of package, without the inductance of vias.

Figure 41

shows the PLL power supply filter circuit.

10

Ω

V

DD

2.2 µF 2.2 µF

AV

DD

(or L2AV

DD

)

GND

Low ESL Surface Mount Capacitors

Figure 41. PLL Power Supply Filter Circuit

90




21.3

Decoupling Recommendations

Due to large address and data buses and high operating frequencies, the MPC8347E can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8347E system, and the

MPC8347E itself requires a clean, tightly regulated source of power. Therefore, the system designer should place at least one decoupling capacitor at each V

DD

, OV

DD

, GV

DD

, and LV

DD

pin of the

MPC8347E. These capacitors should receive their power from separate V

DD

, OV

DD

, GV

DD

, LV

DD

, and

GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under the device using a standard escape pattern. Others can surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, distribute several bulk storage capacitors around the PCB, feeding the V

DD

, OV

DD

, GV

DD

, and LV

DD

planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

21.4

Connection Recommendations

To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OV

DD

, GV

DD

, or LV

DD

as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V

DD the MPC8347E.

, GV

DD

, LV

DD

, OV

DD

, and GND pins of

21.5

Output Buffer DC Impedance

The MPC8347E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I

2

C).

To measure Z

0

for the single-ended drivers, an external resistor is connected from the chip pad to OV

DD or GND. Then the value of each resistor is varied until the pad voltage is OV

DD

/2 (see Figure 42 ). The

output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and R

P

is trimmed until the voltage at the pad equals

OV

DD

/2. R

P

then becomes the resistance of the pull-up devices. R

P

and R

N

are designed to be close to each other in value. Then, Z

0

= (R

P

+ R

N

)/2.




Data

OV

DD

R

N

Pad

SW2

SW1

R

P

OGND

Figure 42. Driver Impedance Measurement

Two measurements give the value of this resistance and the strength of the driver current source. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V

1

= R source

× I source

. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value R term

V

2

= (1/(1/R

1

+ 1/R

2

))

× I source

. Solving for the output impedance gives R

. The measured voltage is source

= R term

× (V

1

/V

2

– 1). The drive current is then I source

= V

1

/R source

.

Table 65

summarizes the signal impedance targets. The driver impedance are targeted at minimum V nominal OV

DD

, 105

°C.

DD

,

Table 65. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI Signals

(Not Including PCI

Output Clocks)

R

N

R

P

Differential

42 Target

42 Target

25 Target

25 Target

NA NA

Note: Nominal supply voltages. See

Table 1

, T j

= 105

°

C.

PCI Output Clocks

(Including

PCI_SYNC_OUT)

42 Target

42 Target

NA

DDR DRAM Symbol

20 Target

20 Target

NA Z

Z

Z

0

0

DIFF

Unit

Ω

Ω

Ω

21.6

Configuration Pin Multiplexing

The MPC8347E power-on configuration options can be set through external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see the customer-visible configuration pins). These pins are used as output only pins in normal operation.

However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with

92




the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for the output pins.

21.7

Pull-Up Resistor Requirements

The MPC8347E requires high resistance pull-up resistors (10 k

Ω is recommended) on open-drain pins, including I

2

C pins, the Ethernet Management MDIO pin, and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface, refer to application note AN2931, PowerQUICC™ Design Checklist.



Document Revision History

22 Document Revision History

Table 66

provides a revision history of this document.

Table 66. Document Revision History

Revision

10

Date

4/2007

9

8

7

3/2007

2/2007

8/2006

Substantive Change(s)

In Table 3 ,

“Output Drive Capability,” changed the values in the Output Impedance column and added USB to the seventh row.

In Figure 20, “Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode),”

updated LALE time line.

In Table 54

, “Operating Frequencies for TBGA,” added column for 400 MHz.

In Section 21.7, “Pull-Up Resistor Requirements,”

deleted last two paragraphs and after first paragraph, added a new paragraph.

Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”

In Table 54, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency ( csb_clk)’ row, changed the value in the 533 MHz column to 100–333.

In Table 60, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK

Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz

CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306, changed the CORE PLL value to 0000110.

In Section 23, “Ordering Information,” replaced first paragraph and added a note.

In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced first paragraph.

Page 1, updated first paragraph to reflect PowerQUICC II information. Updated note after second paragraph.

In the features list in Section 1, “Overview,” corrected DDR data rate to show:

• 266 MHz for PBGA parts for all silicon revisions

• 333 MHz for DDR for TBGA parts for silicon Rev. 1.x

In Table 5, “MPC8347E Typical I/O Power Dissipation,” added GV

DD

1.8-V values for DDR2; added table footnote to designate rates that apply only to the TBGA package.

In Figure 43, “JTAG Interface Connection,” updated with new figure.

In Section 23, “Ordering Information ,” replicated note from document introduction.

In Section 23.1, “Part Numbers Fully Addressed by This Document ,” replaced third sentence of first paragraph directing customer to product summary page for available frequency configuration parts.

Updated back page information.

Changed all references to revision 2.0 silicon to revision 3.0 silicon.

Changed V

IH

minimum value in Table 36, “JTAG Interface DC Electrical Characteristics,” to

OV

DD

– 0.3.

In Table 60, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.

94



Revision

6

5

4

3

2

1

0

Document Revision History

Table 66. Document Revision History (continued)

Date Substantive Change(s)

3/2006 Section 2, “Electrical Characteristics,” moved to second section and all other section, table, and figure numbering change accordingly.

Table 7, “CLKIN AC Timing Specifications:” Changed max rise and fall time from 1.2 to 2.3.

Table 22, “GMII Receive AC Timing Specifications:” Changed min t

TTKHDX

from 0.5 to 1.0.

Table 30, “MII Management AC Timing Specifications:” Changed max value of t

MDKHDX

from 70 to

170.

Table 34, “Local Bus General Timing Parameters—DLL on:” Changed min t

LBIVKH2

from 1.7 to 2.2.

Table 36, “JTAG interface DC Electrical Characteristics:” Changed V

IH

input high voltage min to 2.0.

Table 54, “Operating Frequencies for TBGA:”

• Updated TBD values.

• Changed maximum coherent system bus frequency for TBGA 667-MHz device to 333 MHz.

Table 55, “Operating Frequencies for PBGA:”

• Updated TBD values.

• Changed PBGA maximum coherent system bus frequency to 266 MHz, and maximum DDR memory bus frequency to 133 MHz.

Table 60, “Suggested PLL Configurations”: Removed some values from suggested PLL configurations for reference numbers 902, 922, 903, and 923.

Table 67, “Part Numbering Nomenclature”: Updated TBD values in note 1.

Added Table 68, “SVR Settings.”

Added Section 23.2, “Part Marking.”

10/2005 In Table 57, updated AAVID 30x30x9.4 mm Pin Fin (natural convection) junction-to-ambient thermal resistance, from 11 to 10.

9/2005

8/2005

5/2005

4/2005

4/2005

Added Table 2, “MPC8347E Typical I/O Power Dissipation.”

Table 1: Updated values for power dissipation that were TBD in Revision 2.

Table 1: Typical values for power dissipation are changed to TBD.

Table 48: Footnote numbering was wrong. THERM0 should have footnote 9 instead of 8.

Table 1: Addition of note 1

Table 48: Addition of Therm0 (K32)

Table 49: Addition of Therm0 (B15)

Initial release.



Ordering Information

23 Ordering Information

This section presents ordering information for the device discussed in this document, and it shows an example of how the parts are marked.

NOTE

The information in this document is accurate for revision 1.1 silicon and earlier. For information on revision 3.0 silicon and later versions (orderable part numbers ending with A or B), see the MPC8347EA PowerQUICC™ II

Pro Integrated Host Processor Hardware Specifications (Document Order

No. MPC8347EAEC).

23.1

Part Numbers Fully Addressed by This Document

Table 67

shows an analysis of the Freescale part numbering nomenclature for the MPC8347E. The individual part numbers correspond to a maximum processor core frequency. Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration parts including extended temperatures, refer to the MPC8347E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office.

Table 67. Part Numbering Nomenclature

MPC nnnn e t pp aa a r

Product

Code

Part

Identifier

Encryption

Acceleration

Temperature

1

Range

Package

2

Processor

Frequency

3

Platform

Frequency

Revision

Level

MPC 8347 Blank = Not included

E = included

Blank = 0 to 105

C = –40 to 105

°

°

C

C ZU =TBGA

VV = PB free TBGA

ZQ = PBGA

VR = PB Free PBGA e300 core speed

AD = 266

AG = 400

AJ = 533

AL = 667

D = 266

F = 333

Blank = 1.1 or 1.0

Notes:

1. For temperature range = C, processor frequency is limited to 400 with a platform frequency of 266.

2. See

Section 18, “Package and Pin Listings,”

for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies.

Table 68

shows the SVR settings by device and package type.

Table 68. SVR Settings

Device

MPC8347E

MPC8347

MPC8347E

MPC8347

Package

TBGA

TBGA

PBGA

PBGA

SVR (Rev. 1.0)

8052_0010

8053_0010

8054_0010

8055_0010

96



23.2

Part Marking

Parts are marked as in the example shown in

Figure 43

.

MPCnnnnetppaaar core/platform MHz

ATWLYYWW

CCCCC

*MMMMM YWWLAZ

TBGA/PBGA

Notes

:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

Figure 43. Freescale Part Marking for TBGA or PBGA Devices





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98



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Document Number: MPC8347EEC

Rev. 10

07/2007

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