AMD Athlon Processor Module Data Sheet TM

Preliminary Information
AMD Athlon
TM
Processor Module
Data Sheet
Publication # 21016
Rev: M
Issue Date: June 2000
Preliminary Information
© 2000 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
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AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.
Trademarks
AMD, the AMD logo, AMD Athlon, and combinations thereof, 3DNow!, AMD-751, and AMD-756 are trademarks
of Advanced Micro Devices, Inc.
MMX is a trademark of Intel Corporation.
Digital and Alpha are trademarks of Digital Equipment Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Contents
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
About This Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AMD Athlon System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 8
3
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 15
Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
Contents
AMD Athlon™ Processor Microarchitecture Summary . . . . . 5
The AMD Athlon System Bus . . . . . . . . . . . . . . . . . . . . . . . . . 23
Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Frequency Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OD Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CLKFWD Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SYSCLK, SYSCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Southbridge AC and DC Characteristics . . . . . . . . . . . . . . . . 35
APIC Pin AC and DC Characteristics . . . . . . . . . . . . . . . . . . . 37
Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . 37
iii
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
7
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
7.2
7.3
8
21016M/0—June 2000
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AMD Athlon Processor Card-Edge Signal Listing . . . . . . . . . 45
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Standard AMD Athlon Processor Products . . . . . . . . . . . . . . . . . . . . 53
Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . 57
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s63
iv
Contents
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
List of Figures
Figure 1.
Typical AMD Athlon™ Processor System Block Diagram . . . . . 6
Figure 2.
Logic Symbol Diagram for AMD Athlon Processor . . . . . . . . . 11
Figure 3.
AMD Athlon Processor Power Management States . . . . . . . . . 13
Figure 4.
Example System Bus Disconnection Sequence . . . . . . . . . . . . . 17
Figure 5.
Exiting Stop Grant State/Bus Reconnection Sequence . . . . . . 18
Figure 6.
System Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7.
Processor Connection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8.
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9.
AMD Athlon Processor Module Dimensions—Front View . . . 40
Figure 10. AMD Athlon Processor Module Dimensions—Plate Side
View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. AMD Athlon Processor Module Dimensions—Side View . . . . 42
Figure 12. AMD Athlon Processor Module Dimensions—Edge View. . . . 42
Figure 13. Card Edge Dimensions—Thermal Plate Side View . . . . . . . . . 43
Figure 14. Card Edge Dimensions (Detail) . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 15. OPN Example for the AMD Athlon Processor Model 2 . . . . . . 53
Figure 16. OPN Example for the AMD Athlon Processor Model 4 . . . . . . 54
List of Figures
v
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
vi
21016M/0—June 2000
List of Figures
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
List of Tables
List of Tables
Table 1.
Pin-Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2.
AMD Athlon™ System Bus and Legacy Interface Signals . . . . . 8
Table 3.
AMD Athlon Processor Power Management States . . . . . . . . . 16
Table 4.
AMD Athlon Processor Interface Signal Groupings . . . . . . . . . 24
Table 5.
Source-Synchronous Clock Signal Groups . . . . . . . . . . . . . . . . . 24
Table 6.
Voltage ID Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7.
Signal and Clock Layout and Termination Requirements. . . . 26
Table 8.
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9.
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10.
VCC_CORE Power and Current for Model 1, Model 2, and
Model 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11.
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12.
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13.
Southbridge AC and DC Characteristics . . . . . . . . . . . . . . . . . . 35
Table 14.
APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 37
Table 15.
AMD Athlon Processor Module Dimensions . . . . . . . . . . . . . . . 39
Table 16.
Notes for Dimension Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17.
AMD Athlon Processor Signals Ordered by Pin Number. . . . . 45
Table 18.
AMD Athlon Processor Signals Ordered by Pin Name. . . . . . . 48
Table 19.
AMD Athlon Processor Signals Ordered by Physical
Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 20.
Valid Ordering Part Number Combinations for Model 1 . . . . . 55
Table 21.
Valid Ordering Part Number Combinations for Model 2 . . . . . 55
Table 22.
Valid Ordering Part Number Combinations for Model 4 . . . . . 56
Table 23.
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24.
Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
vii
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
viii
21016M/0—June 2000
List of Tables
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Revision History
Date
Rev
Description
Added information about the AMD Athlon™ processor Model 4 to the following chapters:
“About This Data Sheet” on page 1.
■
Chapter 1, “Overview” on page 3.
■
Chapter 6, “Electrical Data” on page 23.
■
Chapter 8, “Ordering Information” on page 53.
Revised SADDIN and SADDOUT information in Chapter 3, “Logic Symbol Diagram” on page 11.
■
June 2000
M
Added “Signal and Power-Up Requirements” on page 37.
Revised Chapter 5, “Thermal Design” on page 21.
May 2000
L
Non-public version
Added information about the 950-MHz AMD Athlon processor in the following tables:
Table 10, “VCC_CORE Power and Current for Model 1, Model 2, and Model 4,” on page 30
■
Table 21, “Valid Ordering Part Number Combinations for Model 2,” on page 55
Revised information about the 900-MHz and 1-GHz (1000 MHz) AMD Athlon processor in Table 21,
“Valid Ordering Part Number Combinations for Model 2,” on page 55.
■
March 2000
K
Added information about the 900-MHz and 1-GHz (1000 MHz) AMD Athlon processor in the
following chapters:
■
February 2000
J
■
■
In Chapter 1, “Overview” on page 3.
In Chapter 6, “Electrical Data” on page 23 in the following tables:
■
Table 8, “Operating Ranges,” on page 28
■
Table 10, “VCC_CORE Power and Current for Model 1, Model 2, and Model 4,” on page 30
■
Table 11, “DC Characteristics,” on page 32
Chapter 8, “Ordering Information” on page 53.
Added information about the 850-MHz AMD Athlon processor in the following chapters:
In Chapter 1, “Overview” on page 3.
■
In Chapter 6, “Electrical Data” on page 23 in the following tables:
■
Table 8, “Operating Ranges,” on page 28
■
Table 10, “Typical and Maximum Power Dissipation for Model 2—Part One,” on page 31
■
Table 11, “DC Characteristics,” on page 32
■
Chapter 8, “Ordering Information” on page 53.
Reorganized entire book by merging Part One and Part Two together to integrate Model 2 and
Model 1 information.
■
February 2000
I
Revised Power Supply Current Maximum values for 550-MHz through 800-MHz Model 2
processors in Table 11, “DC Characteristics,” on page 32.
Revised Power Supply Current Maximum values Model 1processors in Table 14, “DC
Characteristics for Model 1,” on page 34.
Revision History
ix
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
Date
Rev
21016M/0—June 2000
Description
Added information about the 800-MHz AMD Athlon processor in the following chapters:
In Chapter 14, “Electrical Data” on page 65 in the following tables:
■
Table 23, “Operating Ranges,” on page 68
■
Table 25, “Typical and Maximum Power Dissipation (Model 2),” on page 69
■
Table 26, “DC Characteristics (Model 2),” on page 70
■
In Chapter 16, “Ordering Information” on page 81.
Changed the value of pullup resistors from 68-ohms to 47-ohms in the “Termination” section
starting on page 24, Table 7, “Signal and Clock Layout and Termination Requirements,” on page
24, and Figure 8, “Test Circuit” on page 31.
■
January 2000
H
Revised the maximum thermal power values for all Model 2 processors in Table 25, “Typical and
Maximum Power Dissipation (Model 2),” on page 69.
Divided book into Part One and Part Two. Part One provides information about the AMD Athlon™
processor family (Model 1 and Model 2), and Part Two provides information specific to the
AMD Athlon processor Model 2 (0.18-micron process technology).
Revisions to Part One:
In Chapter 6, “Electrical Data” on page 21:
Expanded information in the “Termination” section starting on page 24, including the addition
of Table 7, “Signal and Clock Layout and Termination Requirements”.
■
Revised maximum rating in Table 9, “Absolute Ratings,” on page 26.
■
Revised Stop Grant values in Table 10, “Typical and Maximum Power Dissipation (Model 1),” on
page 27.
■
Added ICC values and notes 7 and 8 to Table 11, “DC Characteristics (Model 1),” on page 28.
In Chapter 7, “Mechanical Data” on page 33, added # to SCHECK[2]# and SCHECK[7]# in signal
Tables 15, 16, and 17 starting on page 39.
■
December 1999
October 1999
G
F
Added the 700 MHz AMD Athlon™ processor to Table 10, “Typical and Maximum Power
Dissipation (Model 1),” on page 27 and Table 18, “Valid Ordering Part Number Combinations,” on
page 47.
Revised Table 11, “DC Characteristics (Model 1),” on page 28 and Table 12, “AC Characteristics,” on
page 30.
Revised VCC_CORE minimum value from 1.4V to 1.5V in Table 8, “Operating Ranges,” on page 26.
August 1999
E
Revised information in Table 9, “Absolute Ratings,” on page 26.
Revised information in Table 10, “Typical and Maximum Power Dissipation (Model 1),” on page 27.
August 1999
x
D
Initial public release
Revision History
Preliminary Information
21016M/0—June 2000
AMD Athlon™ Processor Module Data Sheet
About This Data Sheet
This AMD Athlon™ processor data sheet describes the technical specifications of the
AMD Athlon processor family designed for the Slot A mechanical connector. The
processor module may include either the AMD Athlon processor Model 1, Model 2, or
Model 4. For more information about determining the Model number and features of
an AMD Athlon processor module, see the AMD Processor Recognition Application
Note, order# 20734 and the AMD Athlon Processor Revision Guide, order# 22557.
For information about the PGA versions of the AMD Athlon processor, see the
AMD Athlon™ Processor PGA Data Sheet, order#23792.
About This Data Sheet
1
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
2
21016M/0—June 2000
About This Data Sheet
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
1
Overview
The AMD Athlon™ processor powers the next generation in
computing platforms, delivering the ultimate performance for
cutting-edge applications and an unprecedented computing
experience.
The AMD Athlon™ processor family continues to deliver
leading-edge processor performance for high-performance
desktop systems, workstations, and servers. The newest
member of the AMD Athlon processor family integrates a
high-performance, full-speed 256-Kbyte Level-Two (L2) cache.
Achieving frequencies of 1-GHz (1000 MHz), the AMD Athlon
processor is the world’s most powerful x86 processor, delivering
the highest integer, floating-point and 3D multimedia
performance for applications running on x86 system platforms.
All AMD Athlon processors provide industry-leading processing
power for cutting-edge software applications, including digital
content creation, digital photo editing, digital video, image
compression, video encoding for streaming over the internet,
sof t DVD, c ommerc ial 3D modeling, workstation-class
computer-aided design (CAD), commercial desktop publishing,
and speech recognition. It also offers the scalability and
‘peace-of-mind’ reliability that IT managers and business users
require for enterprise computing.
The AMD Athlon processor family features the industry's first
seventh-generation x86 microarchitecture, which is designed to
support the g rowing processo r and system bandwidt h
requirements of emerging software, graphics, I/O, and memory
te chnologies. The A MD Athlon processor' s nine -issue
superpipelined microarchitecture includes multiple full x86
instruction decoders, a high-performance cache architecture,
three independent integer units, three address calculation
units, and the x86 industry's first superscalar, fully pipelined,
out-of-order, three-way floating-point unit. The floating-point
u n i t i s c a p ab l e o f d e l ive r i n g 4 g i g a f l o p s ( G f l o p s ) o f
single-precision and more than 2 Gflops of double-precision
floating-point results at 1 GHz, for superior performance on
numerically complex applications.
Chapter 1
Overview
3
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Only the AMD Athlon processor microarchitecture incorporates
Enhanced 3DNow!™ technology and the industry’s first
200-MHz, 1.6-Gigabyte per second front-side bus (FSB) — the
fastest system bus for x86 platforms.
AMD’s Enhanced 3DNow! technology includes additional
instructions to the popular 3DNow! instruction set. It consists of
new integer multimedia instructions and software-directed
data movement instructions for optimizing such applications as
digital content creation and streaming video for the internet, as
well as new inst ruct ions for digit al s ig nal process ing
(DSP)/communications applications.
Based on the high-performance Alpha™ EV6 interface protocol
licensed from Digital Equipment Corporation, the AMD Athlon
system bus combines the latest technological advances, such as
point-to-point topology, source-synchronous packet-based
transfers, and low-voltage signaling, to provide the most
powerful, scalable bus available for any x86 processor.
The AMD Athlon processor is binary-compatible with existing
x86 software and backwards compatible with applications
optimized for MMX™ and 3DNow! instructions. Using a data
format and single-instruction multiple-data (SIMD) operations
based on the MMX instruction model, the AMD Athlon
processor can produce as many as four, 32-bit, single-precision
floating-point results per clock cycle, potentially resulting in
4 Gflops at 1 GHz (fully scalable).
The AMD Athlon processors are implemented in AMD’s
advanced 0.18-micron process technology to achieve maximum
performance and scalability.
For information about the PGA versions of the AMD Athlon
processor, see the AMD Athlon™ Processor PGA Data Sheet,
order#23792.
4
Overview
Chapter 1
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
1.1
AMD Athlon™ Processor Microarchitecture Summary
The following features summarize the AMD Athlon processor
microarchitecture:
■
■
■
■
■
■
■
■
■
Nine-issue, superpipelined, superscalar x86 processor
microarchitecture designed to achieve high clock
frequencies
Multiple full x86 instruction decoders
Three
out-of-order,
superscalar,
fully
pipelined
floating-point execution units, which execute all x87
(floating-point), MMX, 3DNow!, and Enhanced 3DNow!
instructions
Three out-of-order, superscalar, pipelined integer units and
and three address calculation units
72-entry instruction control unit
Advanced dynamic branch prediction
Enhanced 3DNow! technology
A 200-MHz AMD Athlon system bus (scalable beyond 400
MHz) enabling leading-edge system bandwidth for data
movement-intensive applications
High-performance cache architecture including a split
128-Kbyte L1 cache, an integrated 256-Kbyte L2 cache
(external 512-Kbyte L2 cache for Model 1 and Model 2), and
a large dual-level, split Translation Look-aside Buffer (TLB)
AMD is committed to delivering reliable, high-performance,
and cost-effective solutions to its customers for all applications
and configurations. The AMD Athlon processor continues to
deliver superior system performance for systems from desktops
to servers. Figure 1 on page 6 shows a typical AMD Athlon
processor system block diagram.
Chapter 1
Overview
5
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
AMD Athlon™
Processor
AGP Bus
AGP
Memory Bus
System
Controller
(Northbridge)
DRAM
PCI Bus
Peripheral Bus
Controller
(Southbridge)
LAN
System
Management
SCSI
ISA Bus
USB
Dual EIDE
BIOS
Figure 1. Typical AMD Athlon™ Processor System Block Diagram
6
Overview
Chapter 1
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
2
2.1
Interface Signals
Overview
The AMD Athlon™ system bus architecture is designed to
de liver unprecede nt ed da ta m oveme nt bandw idth fo r
next-generation x86 platforms, as well as the high performance
required by enterprise-class application software. The system
bus architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 72-bit bidirectional data channel,
including 8-bit error code correction [ECC] protection),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use a HSTL-like,
low-voltage swing signaling technology contained within the
Slot A mechanical connector, which is mechanically compatible
with the industry-standard SC242 connector.
2.2
Signaling Technology
The AMD Athlon system bus uses a variation of the low-voltage,
JEDEC HSTL signaling technology, which has been enhanced
to provide larger noise margins, reduced ringing, and variable
voltage levels. The signals are open-drained and require
termination to a supply that provides the High signal level. The
HSTL+ inputs use differential receivers, which require a
reference voltage (VREF). The reference signal is used by the
receivers to determine if a signal is asserted or deasserted by
the source. Termination resistors are placed at both ends of the
interface and are used to provide the High signal level and to
control reflections on the interface.
Chapter 2
Interface Signals
7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
2.3
21016M/0—June 2000
AMD Athlon™ System Bus Signals
Table 2 on page 8 shows the AMD Athlon system bus signals
and legacy interface signals. Table 1 shows the pin-type
definitions used in the Type column of Table 2. Signals with
pound signs (#) are active Low.
Table 1.
Pin-Type Definitions
Mnemonic
Table 2.
Definition
I
Standard input pin to the processor
O
Standard output pin from the processor
I/O
Bidirectional, three-state input/output pin
OD
Open-drain structure that allows multiple devices to share the
pin in a wired-OR configuration
PP
Push/Pull structure driven by a single source
AMD Athlon™ System Bus and Legacy Interface Signals
Type
Level
Number
of Pins
A20M#
I
OD
1
A20M# is an input from the system used to simulate address
wrapping around in the 20-bit 8086.
CLKFWDRST
I
OD
1
CLKFWDRST resets clock-forward circuitry for both the system
and processor.
CONNECT
I
OD
1
CONNECT is an input from the system used for power
management and clock-forward initialization at reset.
O
PP
2
COREFB+ and COREFB– are outputs to the system that provide
AMD Athlon processor core voltage feedback to the system.
FERR
O
OD
1
FERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0.
FID[3:0]
O
OD
4
The FID[3:0] signals are outputs to the system that report the
multiplier used on the system clock (SYSCLK) producing the
AMD Athlon processor core clock.
IGNNE#
I
OD
1
IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
I
OD
1
INIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0FFFF FFF0h.
Signal Name
COREFB+
COREFB–
INIT#
Description
Note:
*
8
The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
Interface Signals
Chapter 2
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 2.
AMD Athlon™ System Bus and Legacy Interface Signals (continued)
Type
Level
Number
of Pins
Description
INTR
I
OD
1
INTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the
8-bit interrupt vector and starts execution at that location.
NMI
I
OD
1
NMI is an input from the system that causes a non-maskable
interrupt.
PICCLK*
I
PP
1
PICCLK is an input clock that is required for operation of the
APIC bus.
PICD[1:0]#*
I
OD
2
PICD[1:0]# are bidirectional signals that are used by the APIC
bus, and must be connected to all APIC data pins on all devices
of the APIC bus.
PROCRDY
O
OD
1
PROCRDY is an output to the system and is used for power
management and source-synchronous clock initialization at
reset.
PWROK
I
OD
1
PWROK is an input from the system indicating that the core
power is within specified limits.
RESET#
I
OD
1
RESET# is an input from the system that initializes and resets
the processor and invalidates cache blocks.
SADDIN[14:2]#
I
OD
13
SADDIN[14:2]# is the unidirectional system probe and data
movement command channel from the system.
SADDINCLK#
I
OD
1
SADDINCLK# is the single-ended source-synchronous clock for
SADDIN[14:2]# and is driven by the system.
SADDOUT[14:2]#
O
OD
13
SADDOUT[14:2]# is the unidirectional processor request
channel to the system. It is used to transfer processor requests
or probe responses to the system.
SADDOUTCLK#
O
OD
1
SADDOUTCLK# is the single-ended source-synchronous clock
for SADDOUT[14:2]# driven by the processor.
SCHECK[7:0]#
I/O
OD
8
SCHECK[7:0]# contain the ECC bits for data transfers on
SDATA[63:0]#.
SDATA[63:0]#
I/O
OD
64
SDATA[63:0]# is the bidirectional channel between the
processor and system for data movement.
SDATAINCLK[3:0]#
I
OD
4
SDATAINCLK[3:0]# is the single-ended forwarded clock driven
by the system to transfer data on SDATA[63:0]#. Each 16-bit
data word is skewed-aligned with this clock.
SDATAINVAL#
I
OD
1
SDATAINVAL# is driven by the system to pace the data into the
processor. SDATAINVAL# can be used to introduce an arbitrary
number of cycles between octawords into the processor.
Signal Name
Note:
*
The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
Chapter 2
Interface Signals
9
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
Table 2.
21016M/0—June 2000
AMD Athlon™ System Bus and Legacy Interface Signals (continued)
Signal Name
SDATAOUTCLK[3:0]#
SDATAOUTVAL#
Type
O
I
Level
OD
OD
Number
of Pins
Description
4
SDATAOUTCLK[3:0]# is the single-ended source-synchronous
clock driven by the processor to transfer data on
SDATA[63:0]#. Each 16-bit data word on SDATA[63:0]# is
skewed-aligned with this clock.
1
SDATAOUTVAL# is driven by the system to pace the data from
the processor. SDATAOUTVAL# can be used to introduce an
arbitrary number of cycles between quadwords from the
processor.
SFILLVAL#
I
OD
1
SFILLVAL# validates a data transfer to the processor. The
system may tie this pin to the asserted state (validating all fills).
The processor samples SFILLVAL# at the first or second data
beat.
SMI#
I
OD
1
SMI# is an input that causes the processor to enter the system
management mode.
STPCLK#
I
OD
1
STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
SYSCLK
SYSCLK#
I
2
SYSCLK and SYSCLK# are differential input clock signals
provided to the processor’s PLL from a system-clock generator.
VCC2SEL
O
OD
1
VCC2SEL is an output to the system that indicates the required
core voltage for the L2 SRAM. High=2.5V, Low=3.3V.
VID[3:0]
O
OD
4
The VID[3:0] signals are outputs to the motherboard that
indicate the required VCC_CORE voltage for the processor.
Note:
*
10
The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
Interface Signals
Chapter 2
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
3
Logic Symbol Diagram
Clock
SYSCLK
Data
SYSCLK#
SDATA[63:0]#
SDATAINCLK[3:0]#
SDATAOUTCLK[3:0]#
SCHECK[7:0]#
VID[3:0]
COREFB+
COREFB–
PWROK
VCC2SEL
SDATAINVAL#
SDATAOUTVAL#
SFILLVAL#
Probe/SysCMD
Request
Power
Management
and Initialization
SADDIN[14:1]#
SADDINCLK#
AMD Athlon™
Processor
SADDOUT[14:0]#
SADDOUTCLK#
PROCRDY
CLKFWDRST
CONNECT
STPCLK#
RESET#
Voltage
Control
FID[3:0]
Frequency
Control
FERR
IGNNE#
INIT#
INTR
NMI
A20M#
SMI#
Legacy
*PICCLK
*PICD[1:0]#
APIC*
Note:
*
The industry-standard APIC signals, PICCLK and
PICD[1:0]#, are not available on Model 1.
Figure 2. Logic Symbol Diagram for AMD Athlon™ Processor
Chapter 3
Logic Symbol Diagram
11
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
12
Logic Symbol Diagram
21016M/0—June 2000
Chapter 3
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
4
Power Management
4.1
Power Management States
The AMD Athlon™ processor uses multiple advanced power
states to place the processor in reduced power modes. These
power states are used to enhance processor performance,
minimize power dissipation, and provide a balance between
performance and power (see “Power Dissipation” on page 30
for more information). In addition, these power states conform
to the industry-standard Advanced Configuration and Power
Interface (ACPI) requirements for processor power states.
(ACPI is a specification for system hardware and software to
support OS-oriented power management.) Each state has a
specific mechanism that allows the processor to enter the
respective state. Figure 3 shows the power management states
of the AMD Athlon processor. The figure includes the ACPI
power states for the processor, labeled as Cx.
C1
Auto Halt
Execute HLT and Special Cycle
SMI#, INTR, NMI, INIT#, RESET#
LK
#d
eas
ser
#a
ted
sse
rte
d
Incoming Probe
Probe Serviced
STPCLK# deasserted
STP
C
STPCLK# asserted
Probe Serviced
Incoming Probe
STP
CL
K
Read PLVL2 register
Note *
Probe
State
C0
Normal /
Full-On
ST
PC
ST
PC LK#
LK
de
#
ass
Re
a
s
ad
ser erte
d
PL
ted
VL
3r
eg
ist
er
C3
Sleep
C2
Stop Grant
Legend:
Hardware transitions
Software transitions
Note: The C1 to C2 transition by way of the STPCLK# assertion/deassertion is not defined for ACPI-compliant systems.
Figure 3. AMD Athlon™ Processor Power Management States
Chapter 4
Power Management
13
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
The following sections describe each of the low-power states.
Note: In all power management states, the system must not
disable the system clock (SYSCLK/SYSCLK#) to the
processor.
Full-On
The Full-on or normal state refers to the default power state
and means that all functional units are operating at full
processor clock speed.
Halt State
When the AMD Athlon processor executes the HLT instruction,
the processor issues a Halt special cycle to the system bus. The
phase-lock loop (PLL) continues to run, enabling the processor
to monitor bus activity and provide a quick resume from the
Halt state. The processor may enter a lower power state.
The Halt state is exited when the processor samples INIT#,
INTR (if interrupts are enabled), NMI, RESET#, or SMI#.
Stop Grant and Sleep
States
After recognizing the assertion of STPCLK#, the AMD Athlon
processor completes all pending and in-progress bus cycles and
acknowledges the STPCLK# assertion by issuing a Stop Grant
special bus cycle to the system bus. The processor may enter a
lower power state.
From a software standpoint, the Sleep/Stop Grant state is
e n t e re d by re a d in g t h e P LV L re g i s t e rs l o c a t e d i n a n
ACPI-compliant peripheral bus controller. The difference
between the Stop Grant state and the Sleep state is determined
by which PLVL register software reads from the peripheral bus
controller. If the software reads the PLVL_2 register, the
processor enters the Stop Grant state. In this state, probes are
allowed, as shown in Figure 3 on page 13. If the software reads
the PLVL_3 register, the processor enters the Sleep state, where
probes are not allowed. This action is accomplished by disabling
snoops within an ACPI-compliant system controller.
The Sleep/Stop Grant state is exited upon the deassertion of
STPCLK# or the assertion of RESET#. After the processor
enters the Full-on state, it resumes execution at the instruction
boundary where STPCLK# was initially recognized.
The processor latches INIT#, INTR (if interrupts are enabled),
NMI, and SMI#, if they are asserted during the Stop Grant or
Sleep state. However, the processor does not exit this state until
the deassertion of STPCLK#. When STPCLK# is deasserted,
14
Power Management
Chapter 4
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
any pending interrupts are recognized after returning to the
Normal state.
If RESET# is sampled asserted during the Stop Grant or Sleep
state, the processor immediately returns to the Full-on state
and the reset process begins.
Probe State
The Probe state is entered when the system requires the
processor to service a probe. When in the Probe state, the
processor responds to a probe cycle in the same manner as
when it is in the Full-on state.
When the probe has been serviced, the processor returns to the
same state as when it entered the Probe state.
4.2
Connection and Disconnection Protocol
The AMD Athlon processor enhances power savings in each of
t h e p owe r m a n a g e m e n t s t a t e s w h e n t h e s y s t e m l og i c
disconnects the processor from the system bus and slows down
the internal clocks. Entering the lowest power state is
accomplished with a connection protocol between the processor
and system logic. The system can initiate a bus disconnection
upon the receipt of a Stop Grant special cycle. If required by the
system, the processor disconnects from the system bus and
slows down its internal clocks before entering the Stop Grant or
Sleep state. If the system requires the processor to service a
probe while it is in the Stop Grant state, it must first request
that the processor increase its clocks to full speed and
reconnect to the system bus. Table 3 on page 16 describes the
AMD Athlon processor power states using the connection
protocol as described on page 16.
AMD Athlon system bus connections and disconnections are
controlled by an enable bit within the system controller.
Chapter 4
Power Management
15
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
Table 3.
21016M/0—June 2000
AMD Athlon™ Processor Power Management States
State Name
Full-On / Normal
Entered
Exited
This is the full-on running state of the
processor
Initiates either a Halt instruction or STPCLK#
assertion.
The processor exits and returns to the Run state upon
the occurrence of INIT#, INTR, NMI, SMI# or RESET#.
Halt
Execution of the Halt instruction. A special
cycle is issued. The processor may enter a
lower power state.
Stop Grant
The processor transitions to the Stop Grant
state with the assertion of STPCLK# (as a The processor transitions to the Full-on or Halt state
result of a read to the PLVL_2 register). A upon STPCLK# deassertion.
Stop Grant special cycle is issued. The
processor may enter a lower power state. RESET# asserted initializes the processor but, if
STPCLK# is asserted, the processor returns to the
Note: While in this state, interrupts are
Stop Grant state.
latched and serviced when the processor
transitions to the Full-on state.
Probe
A transition to the Probe state occurs when
the system asserts CONNECT. The
processor remains in this state until the
probe is serviced and any data is
transferred.
Sleep
The processor can enter its lowest power
state, Sleep, from the Full-on state with the
The processor transitions to the Run state upon
assertion of STPCLK# (as a result of a read
STPCLK# deassertion. Asserting RESET# initializes the
to the PLVL_3 register).
processor but, if STPCLK# is asserted, the processor
Note: While in this state, interrupts are
returns to the Sleep state.
latched and serviced when the processor
transitions to the Full-on state.
Connection Protocol
The processor transitions to the Stop Grant state if
STPCLK# is asserted and returns to the Halt state
upon STPCLK# deassertion.
The processor returns to the Halt or Stop Grant state
when the probe has been serviced and the system
deasserts CONNECT. If the processor was
disconnected from the bus in the previous state, bus
disconnection occurs and the internal frequency of
the processor is again slowed down.
In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Athlon system bus connection
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Athlon system bus disconnects are initiated by the system
controller in response to the receipt of a Stop Grant special
cycle. Reconnections are initiated by the processor in response
to an interrupt or STPCLK# deassertion, or by the system to
service a probe.
A disconnect request is implicit, if enabled, in the processor
Stop Grant special cycle request. It is expected that the system
controller provides a BIOS-programmable register in which it
16
Power Management
Chapter 4
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
can disconnect the processor from the AMD Athlon system bus
upon the occurrence of a Stop Grant special cycle. The system
receives the special cycle request from the processor and, if
there are no outstanding probes or data movements, the system
deasserts CONNECT to the processor. The processor detects the
deassertion of CONNECT on a rising edge of SYSCLK, and
deasserts PROCRDY to the system. In return, the system
asserts CLKFWDRST in anticipation of reestablishing a
connection at some later point.
Note: The system must disconnect the processor from the
AMD Athlon system bus before issuing the Stop Grant
special cycle to the PCI bus.
The processor can receive an interrupt or STPCLK# deassertion
after it sends a Stop Grant special cycle to the system but
before the disconnection actually occurs. In this case, the
processor sends the Connect special cycle to the system, rather
than continuing with the disconnect sequence. The system
cancels the disconnection. Figure 4 shows the sequence of
events from a system perspective, which leads to disconnecting
the processor from the AMD Athlon system bus and placing the
processor in the Stop Grant state.
STPCLK#
System Bus
Stop Grant SBC
CONNECT
PROCRDY
CLKFWDRST
PCI Bus
Stop Grant SBC
Figure 4. Example System Bus Disconnection Sequence
The following sequence of events describes how the processor is
placed in the Stop Grant state when bus disconnection is
enabled within the system controller:
1. The peripheral controller asserts STPCLK# to place the
processor in the Stop Grant state.
2. When the processor receives STPCLK#, it acknowledges the
system by sending out a Stop Grant special bus cycle on the
AMD Athlon system bus.
Chapter 4
Power Management
17
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
3. When the special cycle is received by the system controller,
the system controller deasserts CONNECT, initiating a bus
disconnect to the processor.
4. The processor replies to the system controller by
deasserting PROCRDY, approving the bus disconnect
request.
5. The system controller asserts CLKFWDRST to complete the
bus disconnection sequence.
6. After the processor is disconnected from the bus, the
system controller passes the Stop Grant special cycle along
to the peripheral controller via the PCI bus, notifying it that
the processor is in the Stop Grant state.
Figure 5 shows the signal sequence of events that take the
processor out of the Stop Grant state, reconnect the processor
to the AMD Athlon system bus, and put the processor into the
Full-on state.
STPCLK#
PROCRDY
CONNECT
CLKFWDRST
Figure 5. Exiting Stop Grant State/Bus Reconnection Sequence
The following sequence of events removes the processor from
the Stop Grant state and reconnects it to the AMD Athlon
system bus:
1. The peripheral controller deasserts STPCLK#, informing
the processor of a wake event.
2. When the processor receives STPCLK#, it asserts
PROCRDY, notifying the system controller to reconnect to
the bus.
3. The system controller asserts CONNECT, telling the
processor that it is connected to the AMD Athlon system
bus.
4. The system controller finally deasserts CLKFWDRST, which
synchronizes the forwarded clocks between the processor
and the system controller.
18
Power Management
Chapter 4
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Connection State
Machines
Figure 6 and Figure 7 on page 20 describe the system and
processor connection state machines, respectively.
4/A
1
2/A
Disconnect
Pending
Disconnect
Requested
Connect
3
3/C
5/B
8
8
Reconnect
Pending
Disconnect
Probe
Pending 2
7/D,C
6/C
7/D
Probe
Pending 1
Condition
Action
1 A disconnect is requested and probes are still pending
2 A disconnect is requested and no probes are pending
A
Deassert CONNECT 8 SYSCLK periods after
last probe/command sent
3 A CONNECT special cycle from the processor
B Assert CLKFWDRST
4 No probes are pending
C Assert CONNECT
5 PROCRDY is deasserted
D Deassert CLKFWDRST
6 A probe needs service
7 PROCRDY is asserted
3 SYSCLK periods after CLKFWDRST is deasserted.
Although reconnected to the system interface, the
8 system must not issue any non-NOP SysDC commands
for a minimum of four SYSCLK periods after
deasserting CLKFWDRST.
Figure 6. System Connection States
Chapter 4
Power Management
19
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Connect
6/B
1
2/B
Connect
Pending 2
Disconnect
Pending
5
Connect
Pending 1
3/A
Disconnect
4/C
Condition
1
Action
CONNECT is deasserted by the system (for a previously
sent Halt or Stop Grant special cycle).
Processor receives a wake-up event and must cancel
2
the disconnect request.
A CLKFWDRST is asserted by the system.
B Issue a CONNECT special cycle.
C
Assert PROCRDY and return internal clocks to
full speed
3 Deassert PROCRDY and slow down internal clocks.
4
Processor wake-up event or CONNECT asserted by
system.
5 CLKFWDRST is deasserted by the system
6
Forward clocks start 3 SYSCLK periods after
CLKFWDRST is deasserted.
Figure 7. Processor Connection States
20
Power Management
Chapter 4
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
5
Thermal Design
For information about thermal design for the AMD Athlon™
processor module, including layout and airflow considerations,
see the AMD Thermal, Mechanical, and Chassis Cooling Design
G u i d e , o rd e r # 2 3 7 9 4 a n d t h e c o o l i n g g u i d e l i n e s o n
www.amd.com.
Chapter 5
Thermal Design
21
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
22
21016M/0—June 2000
Thermal Design
Chapter 5
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
6
6.1
Electrical Data
The AMD Athlon™ System Bus
The AMD Athlon™ system bus architecture is designed to
de liver unprecede nt ed da ta m oveme nt bandw idth fo r
next-generation x86 platforms, as well as the high performance
required by enterprise-class application software. The system
bus architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
snoop channel, and a 72-bit bidirectional data channel,
including 8-bit error code correction [ECC] protection),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use a HSTL-like,
low-voltage swing signaling technology contained within the
Slot A mechanical connector, which is mechanically compatible
with the industry-standard SC242 connector. For more
i n fo r m a t i o n o n t h e A M D A t h l o n s y s t e m b u s , s e e t h e
AMD Athlon™ System Bus Specification, order# 21902.
6.2
Signal Groupings
The AMD Athlon system bus is the processor connection to a
memory and I/O controller or a shared multiprocessor
controller. The system interface can be categorized into four
signal groups plus power and ground connections. These groups
are listed in Table 4 on page 24. The first group connects the
AMD Athlon processor to the system controller and uses a
source-synchronous, or clock-forwarded clocking scheme. Using
this technique, the clocks and data travel in the same direction
down the transmission line and arrive together. The second
group connects the AMD Athlon processor to the peripheral
bus controller, but unlike the system controller group, these
signals do not use a source-synchronous scheme. The third
group is the control group, which contains signals that interface
with the power supply of the system. The fourth group contains
the system clock. This is the input clock for the AMD Athlon
processor and is the source for all other clocks generated by the
AMD Athlon processor module.
Chapter 6
Electrical Data
23
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
Table 4.
21016M/0—June 2000
AMD Athlon™ Processor Interface Signal Groupings
Name
Buffer Type
System Controller
(Northbridge)
Open-Drain
Signals
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#,
SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#,
SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, SCHECK[7:0]#, FID[3:0],
CLKFWDRST, PROCRDY, CONNECT
Peripheral Bus
Controller
(Southbridge)
RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#,
PICD[1:0]#*, PICCLK*
Control
VID[3:0], VCC2SEL, COREFB+, COREFB–, PWROK
Clock
SYSCLK, SYSCLK#
Power
VCC_CORE, VCC_SRAM, GND
Note:
*
The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
Clock Forwarding
Table 5.
Group
The signals in the system controller group can be divided into
six source-synchronous groups, as shown in Table 5. Groups that
contain two clocks are bidirectional, source-synchronous
groups. These groups use a different clock, based on the
operation being performed. For example, when data is sent
from the AMD Athlon processor to the system controller,
SDATAOUTCLK# is used, and when data is sent from the
system controller to the AMD Athlon processor, SDATAINCLK#
is used. The topology is point-to-point and active terminations.
Source-Synchronous Clock Signal Groups
Signals in Group
Clock
SData0
SDATA[15:0]#, SCHECK[0:1]#
SDATAINCLK[0]#,
SDATAOUTCLK[0]#
SData1
SDATA[31:16]#, SCHECK[2:3]#
SDATAINCLK[1]#,
SDATAOUTCLK[1]#
SData2
SDATA[47:32]#, SCHECK[4:5]#
SDATAINCLK[2]#,
SDATAOUTCLK[2]#
SData3
SDATA[63:48]#, SCHECK[6:7]#
SDATAINCLK[3]#,
SDATAOUTCLK[3]#
SAddIn
SADDIN[14:2]#, SFILLVAL#, SDATAINVAL#,
SDATAOUTVAL#
SADDINCLK#
SAddOut
SADDOUT[14:2]#
SADDOUTCLK#
24
Electrical Data
Chapter 6
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
6.3
Voltage Identification
The AMD Athlon processor provides four voltage ID lines back
to the system for proper configuration of the processor core
voltage. The processor either connects a VID to VSS, or has an
o p e n va lu e . I f re q u i re d by t h e vo lt a g e reg u la t o r, t h e
motherboard pulls up these four signals up to TTL levels. The
motherboard is required to pull VID[4] Low for the voltage
regulator to supply voltage in the appropriate range for the
AMD Athlon processor. These voltage ID values are defined in
Table 6. The pullup resistors used on the motherboard must
have a value of at least 10 kΩ.
Table 6. Voltage ID Values
VID[3] VID[2] VID[1] VID[0] VCC_CORE (V)
0
0
0
0
2.05
0
0
0
1
2.00
0
0
1
0
1.95
0
0
1
1
1.90
0
1
0
0
1.85
0
1
0
1
1.80
0
1
1
0
1.75
0
1
1
1
1.70
1
0
0
0
1.65
1
0
0
1
1.60
1
0
1
0
1.55
1
0
1
1
1.50
1
1
0
0
1.45
1
1
0
1
1.40
1
1
1
0
1.35
1
1
1
1
1.30
In addition, the AMD Athlon processor provides the VCC2SEL
signal to identify the core voltage of the L2 cache SRAMs. Like
the VID signals, the AMD Athlon processor either connects the
VCC2SEL to VSS or has an open value, with a pullup resistor on
the motherboard. An open value indicates that a voltage of 2.5V
is required for VCC_SRAM, while a VSS indicates a required
voltage of 3.3V.
Chapter 6
Electrical Data
25
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
6.4
21016M/0—June 2000
Frequency Identification
The AMD Athlon processor provides four frequency ID signals
(FID[3:0]) to the system controller to indicate the SYSCLK
multiplie r at which the pro cesso r core o pera tes. This
mechanism is automatic, using the system controller and the
BIOS without jumpers on the motherboard to set the operating
frequency of the AMD Athlon processor.
6.5
Decoupling
See the AMD Athlon™ Processor Voltage Regulation Design
Application Note, order# 22651, or contact your local AMD office
for information about t he decoupling required on the
motherboard for use with the AMD Athlon processor.
6.6
Termination
Table 7 lists the layout and termination for Slot A signals and
clocks. For additional information concerning termination
design guidelines for AMD Athlon processor-based systems,
contact your local AMD representative to obtain detailed
documentation available under a non-disclosure agreement.
Table 7.
Signal and Clock Layout and Termination Requirements
Group/Name
SYSCLK, SYSCLK#
SDATA0, SDATA1, SDATA2, SDATA3,
SADDIN, SADDOUT1
CLKFWDRST, CONNECT, PROCRDY
PICCLK2
PICD[1:0]2
NMI, INTR, SMI#, INIT#, A20M#,
IGNNE#, STPCLK#, CPURESET#
Termination Requirements
Differential clock inputs to the system controller (Northbridge) and Slot A.
Point-to-point system clocks driven by the central system clock generator. See
“SYSCLK, SYSCLK#” on page 27.
47 ohm pullup resistors must be kept with 1” of Northbridge. See “OD
Termination” on page 27.
These signals must be pulled to 2.5 V on the motherboard using a 330-ohm
resistor to Vcc3 and a 1.0-kohm resistor to VSS.
Route to minimum length where possible. HSTL-like inputs. Point-to-point signals
driven by the peripheral bus controller (Southbridge) to the Slot A connector.
These signals are pulled to VCC_CORE on the Slot A card and do not require
termination on the motherboard.
Notes:
1. See Table 5, “Source-Synchronous Clock Signal Groups,” on page 24.
2. The industry-standard APIC signals, PICCLK and PICD[1:0]#, are not available on Model 1.
26
Electrical Data
Chapter 6
Preliminary Information
21016M/0—June 2000
AMD Athlon™ Processor Module Data Sheet
OD Termination
Both the processor and Northbridge use HSTL-like open-drain
outputs and HSTL-like inputs. Therefore, the bus signals must
be terminated both at the source and the destination with 47-Ω
pullup resistors to VCC_CORE. Pullups at the processor are
located on the processor module and need not be considered
d u r i n g m o t h e r b o a rd l ayo u t . C o n s e q u e n t ly, t h e o n ly
terminations required on the motherboard are the pullup
resistors at the Northbridge. These pullup termination resistors
must be located 1 inch from the Northbridge.
For systems that do not support ECC, SCHECK[7:0]# should be
tied to VCC_CORE with a 47-ohm pullup, with minimal routing
where possible.
CLKFWD Signal
Groups
The termination scheme for all clock forward signals, both
signal and clock, involves having each end terminated by a
47-ohm pullup resistor located 1 inch from each device. Pullups
at the processor are located on the processor module and need
not be considered during motherboard layout.
Note: The data bus, SDATA[63:0], drives in both directions and,
therefore, must have a unidirectional clock for each data
group travelling each way.
SYSCLK, SYSCLK#
Chapter 6
Each of the two SYSCLK pairs from the clock generator to the
processor, SYSCLK and SYSCLK# (true and complimentary),
are series terminated at the source with a 47-ohm resistor
located a maximum distance of 0.5 inch from the clock
generator and parallel terminated at the end with a 47-ohm
resistor to VCC_CORE. Parallel termination occurs on the
processor module and need not be cons idered dur ing
motherboard layout.
Electrical Data
27
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
6.7
21016M/0—June 2000
Operating Ranges
The AMD Athlon processor is designed to provide functional
operation if the voltage and temperature parameters are within
the limits defined in Table 8.
Table 8.
Operating Ranges
Parameter
VCC_CORE
Description
Min
Nominal
Max
AMD Athlon™ processor Model 1 core supply 500–700 MHz
1.5 V
1.6 V
1.7 V
550–750 MHz
1.5 V
1.6 V
1.7 V
800–850 MHz
1.6 V
1.7 V
1.8 V
900–1000 MHz
1.7 V
1.8 V
1.9 V
650–850 MHz
1.6 V
1.7 V
1.8 V
900–1000 MHz
1.65 V
1.75 V
1.85 V
1.2 V
1.3 V
1.4 V
2
2.5 V SRAM core supply
2.475 V
2.5 V
2.625 V
3
3.3 V SRAM core supply
3.15 V
3.3 V
3.45 V
4
AMD Athlon processor Model 2 core supply
AMD Athlon processor Model 4 core supply
VCC_CORESLEEP AMD Athlon processor core supply in Sleep state
VCC_SRAM
TPLATE
Temperature of thermal plate
Notes
1
70º C
Notes:
1.
2.
3.
4.
28
Normal operating conditions
For Sleep state operating conditions
Value of VCC_SRAM when VCC2SEL is High
Value of VCC_SRAM when VCC2SEL is Low
Electrical Data
Chapter 6
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
6.8
Absolute Ratings
The AMD Athlon processor should not be subjected to
conditions exceeding the absolute ratings listed in Table 9, as
such conditions may adversely affect long term reliability or
result in functional damage.
Table 9.
Absolute Ratings
Parameter
Description
Min
Max
Notes
VCC_CORE
AMD Athlon™ processor core supply
–0.5 V
nominal + 0.5 V
VCC_SRAM
2.5 V SRAM core supply
–0.5 V
3.0 V
1
VCC_SRAM
3.3 V SRAM core supply
–0.5 V
4.0 V
2
VPIN
Voltage on any system bus pin
TBD
TBD
TSTORAGE
Storage temperature of processor
–40º C
85º C
Notes:
1. Value of VCC_SRAM when VCC2SEL is Low
2. Value of VCC_SRAM when VCC2SEL is High
Chapter 6
Electrical Data
29
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
6.9
21016M/0—June 2000
Power Dissipation
Table 10 shows the power and current of the AMD Athlon
processor Model 1, Model 2, and Model 4 during normal and
reduced power states.
Table 10. VCC_CORE Power and Current for Model 1, Model 2, and Model 4
Frequency
(MHz)
Maximum Thermal
Power
Typical Thermal
Power
Stop Grant
(Maximum)4
Maximum ICC (Power
Supply Current)
Notes
Model 1
500
42 W
38 W
6W
25 A
1, 6
550
46 W
41 W
6W
30 A
1, 6
600
50 W
45 W
6W
33 A
1, 6
650
54 W
48 W
6W
36 A
1, 6
700
50 W
45 W
6W
33 A
1, 6
Model 2
550
31 W
28 W
6W
20 A
1, 6
600
34 W
30 W
6W
21 A
1, 6
650
36 W
32 W
6W
22 A
1, 6
700
39 W
34 W
6W
24 A
1, 6
750
40 W
35 W
7W
25 A
1, 6
800
48 W
43 W
7W
29 A
2, 7
850
50 W
45 W
8W
30 A
2, 7
900
60 W
53 W
9W
34 A
4, 9
950
62 W
55 W
9W
35 A
4, 9
1000
65 W
60 W
9W
37 A
4, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
30
Power measured at 1.6V nominal
Power measured at 1.7V nominal
Power measured at 1.75V nominal
Power measured at 1.8V nominal
Sleep state operating conditions measured at 1.3V
ICC measured at maximum VCC_CORE = 1.7V—Power supply designs must take into account the maximum power supply current.
ICC measured at maximum VCC_CORE = 1.8V—Power supply designs must take into account the maximum power supply current.
ICC measured at maximum VCC_CORE = 1.85V—Power supply designs must take into account the maximum power supply current.
ICC measured at maximum VCC_CORE = 1.9V—Power supply designs must take into account the maximum power supply current.
Electrical Data
Chapter 6
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 10. VCC_CORE Power and Current for Model 1, Model 2, and Model 4 (continued)
Frequency
(MHz)
Maximum Thermal
Power
Typical Thermal
Power
Stop Grant
(Maximum)4
Maximum ICC (Power
Supply Current)
Notes
Model 4
650
36.1 W
32.4 W
5W
23.8 A
2, 7
700
38.3 W
34.4 W
5W
25.2 A
2, 7
750
40.4 W
36.3 W
5W
26.6 A
2, 7
800
42.6 W
38.3 W
5W
28.0 A
2, 7
850
44.8 W
40.2 W
5W
29.4 A
2, 7
900
49.7 W
44.6 W
5W
31.7 A
3, 8
950
52.0 W
46.7 W
5W
33.2 A
3, 8
1000
54.3 W
48.7 W
5W
34.6 A
3, 8
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Power measured at 1.6V nominal
Power measured at 1.7V nominal
Power measured at 1.75V nominal
Power measured at 1.8V nominal
Sleep state operating conditions measured at 1.3V
ICC measured at maximum VCC_CORE = 1.7V—Power supply designs must take into account the maximum power supply current.
ICC measured at maximum VCC_CORE = 1.8V—Power supply designs must take into account the maximum power supply current.
ICC measured at maximum VCC_CORE = 1.85V—Power supply designs must take into account the maximum power supply current.
ICC measured at maximum VCC_CORE = 1.9V—Power supply designs must take into account the maximum power supply current.
Chapter 6
Electrical Data
31
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
6.10
21016M/0—June 2000
DC Characteristics
The DC characteristics of the AMD Athlon processor are shown
in Table 11. These values are defined at the card edge of the
AMD Athlon processor module.
Table 11. DC Characteristics
Symbol
Parameter
VREF
DC Input Reference Voltage
IVREF
VREF Input Pin Current
VIH-DC
Condition
Min
Max
(0.47*VCC_CORE) (0.47*VCC_CORE)
–50
+50
Units Notes
mV
1
2
–250
+250
µA
DC Input High Voltage
VREF + 325
VCC_CORE + 300
mV
VIL-DC
DC Input Low Voltage
–300
VREF + 75
mV
VIH-AC
AC Input High Voltage
VREF + 450
VCC_CORE + 500
mV
VIL-AC
AC Input Low Voltage
–500
VREF – 50
mV
VOH-DC
DC Output High Voltage
VCC_CORE
VCC_CORE + 300
mV
3
VOL-DC
DC Output Low Voltage
–300
+300
mV
3
VOH-AC
AC Output High Voltage
VCC_CORE
VCC_CORE + 500
mV
3
VOL-AC
AC Output Low Voltage
–500
400
mV
3
IOL-DC
DC Output Current Low
VOUT= VOL-DC-MAX
–
33
mA
ILEAK
Tristate Leakage
0 < VIN < VCC_CORE
–100
+100
µA
IIH
Input High Current
VIN=VIH-DC-MIN
0
500
µA
IIL
Input Low Current
VIN=VIL-DC-MAX
0
500
µA
CIN
Input Pin Capacitance
4
12
pF
0 < VIN < VCC_CORE
IOUT= IOL-DC-MAX
4
5, 6
Notes:
1. VREF:
– VREF is nominally set by a (1%) resistor divider from VCC_CORE.
– The suggested divider resistor values are 90.9 ohms over 80.6 ohms to produce a divisor of 0.47.
– The internal VREF (VREF-INT) is the external VREF scaled by 0.80 (VREF-INT = (VREF/0.80)). (Processor pin SysVrefMode = High)
– Example: VCC_CORE = 1.6V, VREF = 752mV (1.6 * 0.47), VREF-INT = 940mV (752mV/0.8).
– Peak-to-Peak AC noise on VREF (AC) should not exceed 2% of VREF (DC).
2. IVREF should be measured at nominal VREF.
3. VOL-DC-MAX, VOL-AC-MAX, VOH-DC-MIN and VOH-AC-MIN are specified at T = 100°C and VCC_CORE = 1.4V.
4. Does not apply to VREF.
5. The SYSCLK and SYSCLK# signals have twice the capacitance because they connect to two input pads. SYSCLK connects to
CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
6. The following information pertains only to Model 1 and Model 2. The SDATAINCLK[3:0]# signals have twice the capacitance
because they connect to two input pads. SDATAINCLK[3:0]# connects two byte clocks to form a word sized clock.
32
Electrical Data
Chapter 6
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
6.11
AC Characteristics
Table 12 shows the AC characteristics for the AMD Athlon
processor. The parameters are grouped based on the source or
destination of the signals involved. All parameters are defined
at the card edge of the AMD Athlon processor module.
Table 12. AC Characteristics
Group
Sync *4
Clock Forward
All Signals
Symbol
Parameter
Min
Max
Units
Notes
TRISE
Output Rise Slew Rate
1
3
V/ns
1
TFALL
Output Fall Slew Rate
1
3
V/ns
1
TSKEWSAMEEDGE
Output skew with respect to
the same clock edge
–
385
ps
2
TSKEWDIFFEDGE
Output skew with respect to a
different clock edge
–
770
ps
2
TSU
Input Data Setup Time
300
–
ps
3
THD
Input Data Hold Time
300
–
ps
3
CIN
Capacitance on input Clocks
4
12
pF
COUT
Capacitance on output Clocks
4
12
pF
T VAL
RstClk to Output Valid
250
2000
ps
5
TSU
Setup to RstClk
500
–
ps
6
THD
Hold from RstClk
1000
–
ps
6
Notes:
– Test Circuit used—See Figure 8 on page 34.
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TK7-SKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal
and its forward clock, as measured at the package, with respect to the same clock edge.
TK7-SKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal
and its forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include PROCRDY, CONNECT, CLKFWDRST.
5. T VAL is RstClk rising edge to output valid for PROCRDY. Test Load—25pf.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge
of RSTCLK.
Chapter 6
Electrical Data
33
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
VCC_CORE
VCC_CORE
Component
Component
47Ω
Device
Under
Test
47Ω
Package
Package
50Ω
1 max
50Ω
8 max
Device
Under
Test
50Ω
1 max
Figure 8. Test Circuit
34
Electrical Data
Chapter 6
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
6.12
Southbridge AC and DC Characteristics
Tab le 13 sh ow s the AC and D C cha racte r isti cs o f the
AMD Athlon processor Southbridge pins.
Table 13. Southbridge AC and DC Characteristics*
Symbol
Parameter Description
Min
Nominal
Max
Units
Notes
VIH
Input High Voltage
VCC_CORE Min
VCC_CORE Max
V
1,2
VIL
Input Low Voltage
–300
400
mV
1,2
180
250
mV
Delta VRB Hysteresis change in VIX
VOH
Output High Voltage
VCC_CORE – 400
VCC_CORE + 300
mV
VOL
Output Low Voltage
–300
400
mV
ILEAK
Tristate Leakage
–100
100
uA
IIH
Input High Current
–100
100
uA
IIL
Input Low Current
–100
100
uA
IOH
Output High Current
–21
mA
4
IOL
Output Low Current
27
mA
4
TSU
Sync Input Setup Time
2.0
nS
5,6
THD
Sync Input Hold Time
0.0
pS
5,6
TDELAY
Output Delay with respect to RSTCLK
0.0
nS
6
TBIT
Input Time to Acquire
20.0
nS
8,9
TRPT
Input Time to Reacquire
40.0
nS
10–14
VIN
DC Input Voltage
–300
6.1
VCC_CORE + 300
mV
Notes:
*
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
These parameters pertain to the Southbridge signals listed in Table 4 on page 24.
Characterized across DC supply voltage range.
Values specified at nominal VCC_CORE. Scale parameters with VCC_CORE.
Hysteresis values refer to the difference between initial and return switching points.
IOL and IOH are measured at VOL max and VOH min, respectively.
Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
These are aggregate numbers. The specific pins vary widely within this window.
Edge rates indicate the range over which inputs were characterized.
In asynchronous operation, the signal must persist for this time to guarantee capture.
This value assumes RSTCLK frequency is 10ns ==> TBIT = 2*fRST.
The approximate value for standard case in normal mode operation.
This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency.
Reassertions of the signal within this time are not guaranteed to be seen by the core.
This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other configurations.
Chapter 6
Electrical Data
35
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 13. Southbridge AC and DC Characteristics* (continued)
Symbol
Parameter Description
Min
Nominal
Max
Units
Notes
TRISE
Signal Rise Time
1.0
3.0
V/nS
7
TFALL
Signal Fall Time
1.0
3.0
V/nS
7
CPIN
Pin Capacitance
4
12
pF
Notes:
*
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
36
These parameters pertain to the Southbridge signals listed in Table 4 on page 24.
Characterized across DC supply voltage range.
Values specified at nominal VCC_CORE. Scale parameters with VCC_CORE.
Hysteresis values refer to the difference between initial and return switching points.
IOL and IOH are measured at VOL max and VOH min, respectively.
Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
These are aggregate numbers. The specific pins vary widely within this window.
Edge rates indicate the range over which inputs were characterized.
In asynchronous operation, the signal must persist for this time to guarantee capture.
This value assumes RSTCLK frequency is 10ns ==> TBIT = 2*fRST.
The approximate value for standard case in normal mode operation.
This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency.
Reassertions of the signal within this time are not guaranteed to be seen by the core.
This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other configurations.
Electrical Data
Chapter 6
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
6.13
APIC Pin AC and DC Characteristics
Tab le 14 sh ow s the AC and D C cha racte r isti cs o f the
AMD Athlon processor APIC pins.
Table 14. APIC Pin AC and DC Characteristics
Symbol
Parameter Description
Min
Nominal
Max
Units
Notes
VIH
Input High Voltage
1.7
2.625
V
1,3
VIL
Input Low Voltage
–300
700
mV
1,2
VOH
Output High Voltage
2.625
V
3
VOL
Output Low Voltage
–300
400
mV
ILEAK
Tristate Leakage
–100
100
uA
IIH
Input High Current
–100
100
uA
IIL
Input Low Current
–100
100
uA
IOL
Output Low Current
27
TRISE
Signal Rise Time
1.0
TFALL
Signal Fall Time
CPIN
Pin Capacitance
mA
4
3.0
V/nS
5
1.0
3.0
V/nS
5
4
12
pF
Notes:
1.
2.
3.
4.
5.
Characterized across DC supply voltage range
Values specified at nominal VDD (1.5V). Scale parameters with VDD
2.625V = 2.5V + 5% maximum
IOL is measured at VOL max
Edge rates indicate the range over which inputs were characterized
6.14
Signal and Power-Up Requirements
For information about the signal and power-up requirements
for the AMD Athlon processor module, see the AMD Athlon™
Processor Module Signal and Power-Up Requirements Application
Note, order#23811.
Chapter 6
Electrical Data
37
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
38
21016M/0—June 2000
Electrical Data
Chapter 6
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
7
7.1
Mechanical Data
Introduction
The AMD Athlon™ processor module is comprised of a
processor, L2 cache, passive components, a thermal plate, and a
cover plate. The AMD Athlon processor connects to the
motherboard through insertion into a connector known as
Slot A.
7.2
Module Dimensions
Table 15 shows the dimensions of the AMD Athlon processor
module.
Table 15. AMD Athlon™ Processor Module Dimensions
Description
Min
Max
Figure
Module Length
5.505 inches
5.515 inches
10 on page 41
Module Height
2.451 inches
2.483 inches
10
Module Depth
0.637 inch
0.657 inch
10
Thermal Plate Length
5.331 inches
5.351 inches
11 on page 42
Thermal Plate Height
1.917 inches
1.927 inches
11
Figures 10 through 14 starting on page 41 show the critical
dimensions of t he AMD Athlon processor module. All
dimensions in the drawings are in inches and are not to scale.
Table 16 lists the notes that pertain to the dimension drawings.
Table 16. Notes for Dimension Drawings
Note
Chapter 7
Description
6
Area for part number and traceability information
7
Rivscrew attach hole. Maximum insertion depth: 0.269”
8
Heatsink clip attach hole. Maximum insertion depth: 0.233”
9
Thermal grease centered on SRAM pedestal
Mechanical Data
39
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Figure 9. AMD Athlon™ Processor Module Dimensions—Front View
40
Mechanical Data
Chapter 7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Figure 10. AMD Athlon™ Processor Module Dimensions—Plate Side View
Chapter 7
Mechanical Data
41
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Figure 11. AMD Athlon™ Processor Module Dimensions—Side View
This dimension is to
the daughtercard
centerline
Figure 12. AMD Athlon™ Processor Module Dimensions—Edge View
42
Mechanical Data
Chapter 7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Figure 13. Card Edge Dimensions—Thermal Plate Side View
Chapter 7
Mechanical Data
43
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Figure 14. Card Edge Dimensions (Detail)
44
Mechanical Data
Chapter 7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
7.3
AMD Athlon™ Processor Card-Edge Signal Listing
Tables 17 through 19 shows the Slot A signals and pins ordered
by pin number, pin name, and their physical position on the
slot, respectively. The High and Low designation in the Pin
Name column in Table 19 refers to the staggered high/low
arrangement of the pins on the slot.
Three additional APIC-related signals have been designated
(PICD[1:0]# and PICCLK), which are detailed in Tables 17
through 19. On Model 1, these pins are reserved.
Table 17. AMD Athlon™ Processor Signals Ordered by Pin Number
Pin No.
A1
Pin Name
VCC2SEL
Pin No.
Pin Name
B1
SADDOUT[14]#
A2
VCC_SRAM[7]
B2
GND[10]
A3
PICCLK (Not present on Model 1)
B3
SADDOUT[13]#
A4
VCC_SRAM[6]
B4
SADDOUT[7]#
A5
PICD[0] (Not present on Model 1)
B5
GND[51]
A6
VCC_SRAM[5]
B6
SADDOUTCLK#
A7
PICD[1] (Not present on Model 1)
B7
GND[7]
A8
VCC_SRAM[4]
B8
SADDOUT[12]#
A9
SMI#
B9
GND[21]
A10
VCC_SRAM[3]
B10
SADDOUT[9]#
A11
FERR
B11
SADDOUT[8]#
A12
INIT#
B12
GND[20]
A13
NMI
B13
SADDOUT[5]#
A14
VCC_SRAM[2]
B14
SADDOUT[6]#
A15
INTR
B15
GND[30]
A16
VCC_SRAM[1]
B16
SADDOUT[2]#
A17
RESET#
B17
GND[44]
A18
STPCLK#
B18
SADDOUT[3]#
A19
IGNNE#
B19
GND[19]
A20
VCC_SRAM[8]
B20
SDATAOUTCLK[3]#
A21
A20M#
B21
GND[40]
A22
VCC_CORE[41]
B22
SCHECK[6]#
A23
SADDOUT[10]#
B23
SDATA[53]#
A24
VCC_CORE[1]
B24
GND[8]
A25
SADDOUT[11]#
B25
SDATA[49]#
A26
VCC_CORE[19]
B26
SDATA[63]#
A27
SADDOUT[4]#
B27
GND[32]
A28
VCC_CORE[44]
B28
SDATAINCLK[3]#
A29
SDATA[55]#
B29
GND[3]
A30
VCC_CORE[10]
B30
SDATA[62]#
A31
SDATA[54]#
B31
GND[1]
A32
VCC_CORE[11]
B32
SDATA[60]#
Chapter 7
Mechanical Data
45
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 17. AMD Athlon™ Processor Signals Ordered by Pin Number (continued)
Pin No.
Pin Name
Pin No.
Pin Name
A33
SDATA[52]#
B33
GND[13]
A34
VCC_CORE[35]
B34
SCHECK[7]#
A35
SDATA[61]#
B35
SDATA[59]#
A36
VCC_CORE[25]
B36
GND[2]
A37
SDATA[50]#
B37
SDATA[58]#
A38
VCC_CORE[4]
B38
SDATA[57]#
A39
SDATA[51]#
B39
GND[16]
A40
VCC_CORE[26]
B40
SDATA[39]#
GND[39]
A41
SDATA[48]#
B41
A42
VCC_CORE[34]
B42
SDATA[56]#
A43
SDATA[36]#
B43
GND[38]
A44
VCC_CORE[16]
B44
SDATA[47]#
A45
SDATA[46]#
B45
SDATA[38]#
A46
VCC_CORE[38]
B46
GND[41]
A47
SDATA[37]#
B47
SDATA[45]#
A48
VCC_CORE[20]
B48
SDATA[44]#
A49
SDATA[35]#
B49
GND[37]
A50
VCC_CORE[30]
B50
SDATAINCLK[2]#
A51
SCHECK[4]#
B51
GND[34]
A52
VCC_CORE[3]
B52
SCHECK[5]#
A53
SDATA[34]#
B53
GND[33]
A54
VCC_CORE[31]
B54
SDATA[43]#
A55
SDATA[33]#
B55
SDATA[42]#
A56
VCC_CORE[29]
B56
GND[22]
A57
SDATA[32]#
B57
SDATA[41]#
A58
VCC_CORE[7]
B58
SDATA[40]#
A59
SDATAOUTCLK[2]#
B59
GND[50]
A60
VCC_CORE[18]
B60
SDATAOUTCLK[1]#
GND[31]
A61
SDATA[30]#
B61
A62
VCC_CORE[15]
B62
SDATA[22]#
A63
SDATA[31]#
B63
GND[35]
A64
VCC_CORE[14]
B64
SDATA[23]#
A65
SCHECK[3]#
B65
GND[36]
A66
VCC_CORE[33]
B66
SDATA[21]#
A67
SDATAINCLK[1]#
B67
GND[49]
A68
VCC_CORE[32]
B68
SDATA[20]#
A69
SDATA[29]#
B69
GND[14]
A70
SDATA[28]#
B70
SDATA[19]#
A71
VCC_CORE[9]
B71
SCHECK[2]#
A72
SDATA[26]#
B72
GND[9]
A73
SDATA[27]#
B73
SDATA[18]#
A74
VCC_CORE[42]
B74
SDATA[7]#
A75
SDATA[25]#
B75
GND[23]
A76
VCC_CORE[13]
B76
SDATA[17]#
A77
SDATA[24]#
B77
GND[15]
46
Mechanical Data
Chapter 7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 17. AMD Athlon™ Processor Signals Ordered by Pin Number (continued)
Pin No.
Pin Name
Pin No.
Pin Name
A78
VCC_CORE[27]
B78
SDATA[16]#
A79
SDATA[15]#
B79
GND[27]
A80
VCC_CORE[24]
B80
SDATA[6]#
A81
SDATA[1]#
B81
SDATA[5]#
A82
VCC_CORE[2]
B82
GND[28]
A83
SDATA[12]#
B83
SCHECK[0]#
A84
VCC_CORE[23]
B84
SDATA[4]#
A85
SCHECK[1]#
B85
GND[29]
A86
VCC_CORE[5]
B86
SDATA[2]#
A87
SDATA[8]#
B87
GND[25]
A88
VCC_CORE[39]
B88
SDATAINCLK[0]#
A89
SDATA[10]#
B89
GND[26]
A90
VCC_CORE[22]
B90
SDATA[3]#
A91
SDATAOUTCLK[0]#
B91
GND[6]
A92
VCC_CORE[21]
B92
SDATA[0]#
A93
SADDIN[7]#
B93
GND[5]
A94
VCC_CORE[40]
B94
SDATA[13]#
A95
SADDIN[6]#
B95
SDATA[14]#
A96
VCC_CORE[37]
B96
GND[4]
A97
SADDIN[8]#
B97
SDATA[11]#
A98
VCC_CORE[6]
B98
SDATA[9]#
A99
SDATAOUTVAL#
B99
GND[17]
A100
VCC_CORE[28]
B100
SADDIN[5]#
A101
SDATAINVAL#
B101
GND[18]
SADDIN[11]#
A102
VCC_CORE[36]
B102
A103
CONNECT
B103
GND[45]
A104
VCC_CORE[12]
B104
SADDIN[2]#
A105
CLKFWDRST
B105
GND[48]
A106
PROCRDY
B106
SADDIN[3]#
A107
VCC_CORE[43]
B107
SADDIN[4]#
A108
SYSCLK#
B108
GND[46]
A109
SYSCLK
B109
SADDIN[10]#
A110
VCC_CORE[17]
B110
SADDIN[9]#
A111
PWROK
B111
GND[43]
A112
VID[0]
B112
SADDIN[13]#
A113
VID[1]
B113
GND[42]
A114
VID[2]
B114
SADDINCLK#
A115
VID[3]
B115
GND[11]
A116
FID[3]
B116
SADDIN[14]#
A117
FID[2]
B117
GND[12]
SFILLVAL#
A118
FID[1]
B118
A119
FID[0]
B119
GND[47]
A120
COREFB+
B120
SADDIN[12]#
A121
COREFB–
B121
GND[24]
Chapter 7
Mechanical Data
47
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 18. AMD Athlon™ Processor Signals Ordered by Pin Name
Pin Name
Pin No.
Pin Name
Pin No.
A20M#
A21
GND[25]
B87
CLKFWDRST
A105
GND[26]
B89
CONNECT
A103
GND[27]
B79
COREFB+
A120
GND[28]
B82
COREFB–
A121
GND[29]
B85
FERR
A11
GND[30]
B15
FID[0]
A119
GND[31]
B61
FID[1]
A118
GND[32]
B27
FID[2]
A117
GND[33]
B53
FID[3]
A116
GND[34]
B51
GND[1]
B31
GND[35]
B63
GND[2]
B36
GND[36]
B65
GND[3]
B29
GND[37]
B49
GND[4]
B96
GND[38]
B43
GND[5]
B93
GND[39]
B41
GND[6]
B91
GND[40]
B21
GND[7]
B7
GND[41]
B46
GND[8]
B24
GND[42]
B113
GND[9]
B72
GND[43]
B111
GND[10]
B2
GND[44]
B17
GND[11]
B115
GND[45]
B103
GND[12]
B117
GND[46]
B108
GND[13]
B33
GND[47]
B119
GND[14]
B69
GND[48]
B105
GND[15]
B77
GND[49]
B67
GND[16]
B39
GND[50]
B59
GND[17]
B99
GND[51]
B5
GND[18]
B101
IGNNE#
A19
GND[19]
B19
INIT#
A12
GND[20]
B12
INTR
A15
GND[21]
B9
NMI
A13
GND[22]
B56
PICCLK (Not present on Model 1)
A3
GND[23]
B75
PICD[0] (Not present on Model 1)
A5
GND[24]
B121
PICD[1] (Not present on Model 1)
A7
PROCRDY
A106
SCHECK[3]#
A65
PWROK
A111
SCHECK[4]#
A51
RESET#
A17
SCHECK[5]#
B52
SADDIN[2]#
B104
SCHECK[6]#
B22
SADDIN[3]#
B106
SCHECK[7]#
B34
SADDIN[4]#
B107
SDATA[0]#
B92
SADDIN[5]#
B100
SDATA[1]#
A81
SADDIN[6]#
A95
SDATA[2]#
B86
SADDIN[7]#
A93
SDATA[3]#
B90
SADDIN[8]#
A97
SDATA[4]#
B84
48
Mechanical Data
Chapter 7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 18. AMD Athlon™ Processor Signals Ordered by Pin Name (continued)
Pin Name
Pin No.
Pin Name
Pin No.
SADDIN[9]#
B110
SDATA[5]#
B81
SADDIN[10]#
B109
SDATA[6]#
B80
SADDIN[11]#
B102
SDATA[7]#
B74
SADDIN[12]#
B120
SDATA[8]#
A87
SADDIN[13]#
B112
SDATA[9]#
B98
SADDIN[14]#
B116
SDATA[10]#
A89
SADDINCLK#
B114
SDATA[11]#
B97
SADDOUT[2]#
B16
SDATA[12]#
A83
SADDOUT[3]#
B18
SDATA[13]#
B94
SADDOUT[4]#
A27
SDATA[14]#
B95
SADDOUT[5]#
B13
SDATA[15]#
A79
SADDOUT[6]#
B14
SDATA[16]#
B78
SADDOUT[7]#
B4
SDATA[17]#
B76
SADDOUT[8]#
B11
SDATA[18]#
B73
SADDOUT[9]#
B10
SDATA[19]#
B70
SADDOUT[10]#
A23
SDATA[20]#
B68
SADDOUT[11]#
A25
SDATA[21]#
B66
SADDOUT[12]#
B8
SDATA[22]#
B62
SADDOUT[13]#
B3
SDATA[23]#
B64
SADDOUT[14]#
B1
SDATA[24]#
A77
SADDOUTCLK#
B6
SDATA[25]#
A75
SCHECK[0]#
B83
SDATA[26]#
A72
SCHECK[1]#
A85
SDATA[27]#
A73
SCHECK[2]#
B71
SDATA[28]#
A70
SDATA[29]#
A69
SDATA[63]#
B26
SDATA[30]#
A61
SDATAINCLK[0]#
B88
SDATA[31]#
A63
SDATAINCLK[1]#
A67
SDATA[32]#
A57
SDATAINCLK[2]#
B50
SDATA[33]#
A55
SDATAINCLK[3]#
B28
SDATA[34]#
A53
SDATAINVAL#
A101
SDATA[35]#
A49
SDATAOUTCLK[0]#
A91
SDATA[36]#
A43
SDATAOUTCLK[1]#
B60
SDATA[37]#
A47
SDATAOUTCLK[2]#
A59
SDATA[38]#
B45
SDATAOUTCLK[3]#
B20
SDATA[39]#
B40
SDATAOUTVAL#
A99
SDATA[40]#
B58
SFILLVAL#
B118
SDATA[41]#
B57
SMI#
A9
SDATA[42]#
B55
STPCLK#
A18
SDATA[43]#
B54
SYSCLK
A109
SDATA[44]#
B48
SYSCLK#
A108
SDATA[45]#
B47
VCC2SEL
A1
SDATA[46]#
A45
VCC_CORE[1]
A24
SDATA[47]#
B44
VCC_CORE[2]
A82
SDATA[48]#
A41
VCC_CORE[3]
A52
SDATA[49]#
B25
VCC_CORE[4]
A38
Chapter 7
Mechanical Data
49
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 18. AMD Athlon™ Processor Signals Ordered by Pin Name (continued)
Pin Name
Pin No.
Pin Name
Pin No.
SDATA[50]#
A37
VCC_CORE[5]
A86
SDATA[51]#
A39
VCC_CORE[6]
A98
SDATA[52]#
A33
VCC_CORE[7]
A58
SDATA[53]#
B23
VCC_CORE[9]
A71
SDATA[54]#
A31
VCC_CORE[10]
A30
SDATA[55]#
A29
VCC_CORE[11]
A32
SDATA[56]#
B42
VCC_CORE[12]
A104
SDATA[57]#
B38
VCC_CORE[13]
A76
SDATA[58]#
B37
VCC_CORE[14]
A64
SDATA[59]#
B35
VCC_CORE[15]
A62
SDATA[60]#
B32
VCC_CORE[16]
A44
SDATA[61]#
A35
VCC_CORE[17]
A110
SDATA[62]#
B30
VCC_CORE[18]
A60
VCC_CORE[19]
A26
VCC_CORE[38]
A46
VCC_CORE[20]
A48
VCC_CORE[39]
A88
VCC_CORE[21]
A92
VCC_CORE[40]
A94
VCC_CORE[22]
A90
VCC_CORE[41]
A22
VCC_CORE[23]
A84
VCC_CORE[42]
A74
VCC_CORE[24]
A80
VCC_CORE[43]
A107
VCC_CORE[25]
A36
VCC_CORE[44]
A28
VCC_CORE[26]
A40
VCC_SRAM[1]
A16
VCC_CORE[27]
A78
VCC_SRAM[2]
A14
VCC_CORE[28]
A100
VCC_SRAM[3]
A10
VCC_CORE[29]
A56
VCC_SRAM[4]
A8
VCC_CORE[30]
A50
VCC_SRAM[5]
A6
VCC_CORE[31]
A54
VCC_SRAM[6]
A4
VCC_CORE[32]
A68
VCC_SRAM[7]
A2
VCC_CORE[33]
A66
VCC_SRAM[8]
A20
VCC_CORE[34]
A42
VID[0]
A112
VCC_CORE[35]
A34
VID[1]
A113
VCC_CORE[36]
A102
VID[2]
A114
VCC_CORE[37]
A96
VID[3]
A115
50
Mechanical Data
Chapter 7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 19. AMD Athlon™ Processor Signals Ordered by Physical Location
Pin No.
A121
A119
A117
A115
A113
A111
A109
A107
A105
A103
A101
A99
A97
A95
A93
A91
A89
A87
A85
A83
A81
A79
A77
A75
A73
A71
A69
A67
A65
A63
A61
A59
A57
A55
A53
A51
A49
A47
A45
A43
A41
A39
A37
A35
A33
A31
A29
A27
A25
A23
A21
A19
A17
A15
A13
A11
A9
A7
A5
A3
A1
Pin Name—High
COREFB–
FID[0]
FID[2]
VID[3]
VID[1]
PWROK
SYSCLK
VCC_CORE[43]
CLKFWDRST
CONNECT
SDATAINVAL#
SDATAOUTVAL#
SADDIN[8]#
SADDIN[6]#
SADDIN[7]#
SDATAOUTCLK[0]#
SDATA[10]#
SDATA[8]#
SCHECK[1]#
SDATA[12]#
SDATA[1]#
SDATA[15]#
SDATA[24]#
SDATA[25]#
SDATA[27]#
VCC_CORE[9]
SDATA[29]#
SDATAINCLK[1]#
SCHECK[3]#
SDATA[31]#
SDATA[30]#
SDATAOUTCLK[2]#
SDATA[32]#
SDATA[33]#
SDATA[34]#
SCHECK[4]#
SDATA[35]#
SDATA[37]#
SDATA[46]#
SDATA[36]#
SDATA[48]#
SDATA[51]#
SDATA[50]#
SDATA[61]#
SDATA[52]#
SDATA[54]#
SDATA[55]#
SADDOUT[4]#
SADDOUT[11]#
SADDOUT[10]#
A20M#
IGNNE#
RESET#
INTR
NMI
FERR#
SMI#
PICD[1] (Not present on Model 1)
PICD[0] (Not present on Model 1)
PICCLK (Not present on Model 1)
VCC2SEL
Chapter 7
Pin Name—Low
COREFB+
FID[1]
FID[3]
VID[2]
VID[0]
VCC_CORE[17]
SYSCLK#
PROCRDY
VCC_CORE[12]
VCC_CORE[36]
VCC_CORE[28]
VCC_CORE[6]
VCC_CORE[37]
VCC_CORE[40]
VCC_CORE[21]
VCC_CORE[22]
VCC_CORE[39]
VCC_CORE[5]
VCC_CORE[23]
VCC_CORE[2]
VCC_CORE[24]
VCC_CORE[27]
VCC_CORE[13]
VCC_CORE[42]
SDATA[26]#
SDATA[28]#
VCC_CORE[32]
VCC_CORE[33]
VCC_CORE[14]
VCC_CORE[15]
VCC_CORE[18]
VCC_CORE[7]
VCC_CORE[29]
VCC_CORE[31]
VCC_CORE[3]
VCC_CORE[30]
VCC_CORE[20]
VCC_CORE[38]
VCC_CORE[16]
VCC_CORE[34]
VCC_CORE[26]
VCC_CORE[4]
VCC_CORE[25]
VCC_CORE[35]
VCC_CORE[11]
VCC_CORE[10]
VCC_CORE[44]
VCC_CORE[19]
VCC_CORE[1]
VCC_CORE[41]
VCC_SRAM[8]
STPCLK#
VCC_SRAM[1]
VCC_SRAM[2]
INIT#
VCC_SRAM[3]
VCC_SRAM[4]
VCC_SRAM[5]
VCC_SRAM[6]
VCC_SRAM[7]
Pin No.
A120
A118
A116
A114
A112
A110
A108
A106
A104
A102
A100
A98
A96
A94
A92
A90
A88
A86
A84
A82
A80
A78
A76
A74
A72
A70
A68
A66
A64
A62
A60
A58
A56
A54
A52
A50
A48
A46
A44
A42
A40
A38
A36
A34
A32
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A8
A6
A4
A2
Pin No.
B121
B119
B117
B115
B113
B111
B109
B107
B105
B103
B101
B99
B97
B95
B93
B91
B89
B87
B85
B83
B81
B79
B77
B75
B73
B71
B69
B67
B65
B63
B61
B59
B57
B55
B53
B51
B49
B47
B45
B43
B41
B39
B37
B35
B33
B31
B29
B27
B25
B23
B21
B19
B17
B15
B13
B11
B9
B7
B5
B3
B1
Pin Name—High
GND[24]
GND[47]
GND[12]
GND[11]
GND[42]
GND[43]
SADDIN[10]#
SADDIN[4]#
GND[48]
GND[45]
GND[18]
GND[17]
SDATA[11]#
SDATA[14]#
GND[5]
GND[6]
GND[26]
GND[25]
GND[29]
SCHECK[0]#
SDATA[5]#
GND[27]
GND[15]
GND[23]
SDATA[18]#
SCHECK[2]#
GND[14]
GND[49]
GND[36]
GND[35]
GND[31]
GND[50]
SDATA[41]#
SDATA[42]#
GND[33]
GND[34]
GND[37]
SDATA[45]#
SDATA[38]#
GND[38]
GND[39]
GND[16]
SDATA[58]#
SDATA[59]#
GND[13]
GND[1]
GND[3]
GND[32]
SDATA[49]#
SDATA[53]#
GND[40]
GND[19]
GND[44]
GND[30]
SADDOUT[5]#
SADDOUT[8]#
GND[21]
GND[7]
GND[51]
SADDOUT[13]#
SADDOUT[14]#
Mechanical Data
Pin Name—Low
SADDIN[12]#
SFILLVAL#
SADDIN[14]#
SADDINCLK#
SADDIN[13]#
SADDIN[9]#
GND[46]
SADDIN[3]#
SADDIN[2]#
SADDIN[11]#
SADDIN[5]#
SDATA[9]#
GND[4]
SDATA[13]#
SDATA[0]#
SDATA[3]#
SDATAINCLK[0]#
SDATA[2]#
SDATA[4]#
GND[28]
SDATA[6]#
SDATA[16]#
SDATA[17]#
SDATA[7]#
GND[9]
SDATA[19]#
SDATA[20]#
SDATA[21]#
SDATA[23]#
SDATA[22]#
SDATAOUTCLK[1]#
SDATA[40]#
GND[22]
SDATA[43]#
SCHECK[5]#
SDATAINCLK[2]#
SDATA[44]#
GND[41]
SDATA[47]#
SDATA[56]#
SDATA[39]#
SDATA[57]#
GND[2]
SCHECK[7]#
SDATA[60]#
SDATA[62]#
SDATAINCLK[3]#
SDATA[63]#
GND[8]
SCHECK[6]#
SDATAOUTCLK[3]#
SADDOUT[3]#
SADDOUT[2]#
SADDOUT[6]#
GND[20]
SADDOUT[9]#
SADDOUT[12]#
SADDOUTCLK#
SADDOUT[7]#
GND[10]
Pin No.
B120
B118
B116
B114
B112
B110
B108
B106
B104
B102
B100
B98
B96
B94
B92
B90
B88
B86
B84
B82
B80
B78
B76
B74
B72
B70
B68
B66
B64
B62
B60
B58
B56
B54
B52
B50
B48
B46
B44
B42
B40
B38
B36
B34
B32
B30
B28
B26
B24
B22
B20
B18
B16
B14
B12
B10
B8
B6
B4
B2
51
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
52
21016M/0—June 2000
Mechanical Data
Chapter 7
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
8
Ordering Information
Standard AMD Athlon™ Processor Products
AMD standard products are available in several operating ranges. The ordering part
numbers (OPN) for Model 1 are shown in Table 21 on page 55. The OPNs for Model 2
are shown in Table 20 on page 55. These OPNs are formed by a combination of the
elements shown in Figure 15.
The OPNs for Model 4 are shown in Table 22 on page 56. These OPNs are formed by a
combination of the elements shown in Figure 16 on page 54.
Dynamic Marking Product ID
Product Naming
(Laser Marking)
(Pad Printed)
AMD AthlonTM Processor
AMD-K7750MTR52B A
219927999994
Copyright Info
Serial No.
© 2000 AMD
(Pad Printed)
(Laser Marking)
m
2D Code (44x44)
(Laser Marking)
OPN
AMD-K7 750 M T R 5 2 B
A
Reserved Characters
(3 blank spaces are positioned before this character.)
Max FSB: B = 200 MHz
Cache Divisor: 1 = 2:1, 2 = 2.5:1, 3 = 3:1
Size of Ext. Cache: 5 = 512Kbytes
Case Temperature: R = 70°C
Operating Voltage: T = 1.6V, P = 1.7V, N = 1.8V
Package Type: M = Card Module, P = PGA
Speed: 550MHz–950MHz, 100 = 1000 MHz
Family/Architecture: AMD-K7 Architecture
Note: Spaces are added to the number illustrated
above for viewing clarity only.
Figure 15. OPN Example for the AMD Athlon™ Processor Model 2
Chapter 8
Ordering Information
53
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Dynamic Marking Product ID
Product Naming
(Laser Marking)
(Pad Printed)
AMD-A0850MPR24B A
AMD AthlonTM Processor
219927999994
Copyright Info
Serial No.
© 2000 AMD
(Pad Printed)
(Laser Marking)
m
2D Code (44x44)
(Laser Marking)
OPN
AMD-A 0850 M P R 2 4 B
A
Reserved Characters
(3 blank spaces are positioned before this character.)
Max FSB: B = 200 MHz
Cache Divisor: 4 = 1:1
Size of L2 Cache: 2 = 256Kbytes
Case Temperature: R = 70°C
Operating Voltage: T = 1.6V, P = 1.7V, M = 1.75V, N = 1.8V
Package Type: M = Card Module, P = PGA
Speed: 0850=850 MHz, 0900=900 MHz, 1000=1000 MHz,
1100=1100 MHz, etc.
Family/Architecture: AMD Athlon Architecture
Note: Spaces are added to the number illustrated
above for viewing clarity only.
Figure 16. OPN Example for the AMD Athlon™ Processor Model 4
54
Ordering Information
Chapter 8
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 20. Valid Ordering Part Number Combinations for Model 1
OPN
Package Type
Operating Voltage Plate Temperature
AMD-K7500MTR51B C
Card Module
1.6 V
0°C–70°C
AMD-K7550MTR51B C
Card Module
1.6 V
0°C–70°C
AMD-K7600MTR51B C
Card Module
1.6 V
0°C–70°C
AMD-K7650MTR51B C
Card Module
1.6 V
0°C–70°C
AMD-K7700MTR51B C
Card Module
1.6 V
0°C–70°C
Notes:
This table lists configurations planned to be supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combinations and to check on newly-released combinations.
Table 21. Valid Ordering Part Number Combinations for Model 2
OPN
Package Type
Operating Voltage Plate Temperature
AMD-K7550MTR51B A
Card Module
1.6 V
0°C–70°C
AMD-K7600MTR51B A
Card Module
1.6 V
0°C–70°C
AMD-K7650MTR51B A
Card Module
1.6 V
0°C–70°C
AMD-K7700MTR51B A
Card Module
1.6 V
0°C–70°C
AMD-K7750MTR52B A
Card Module
1.6 V
0°C–70°C
AMD-K7800MPR52B A
Card Module
1.7 V
0°C–70°C
AMD-K7850MPR52B A
Card Module
1.7 V
0°C–70°C
AMD-K7900MNR53B A
Card Module
1.8 V
0°C–70°C
AMD-K7950MNR53B A
Card Module
1.8 V
0°C–70°C
AMD-K7100MNR53B A
Card Module
1.8 V
0°C–70°C
Notes:
This table lists configurations planned to be supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combinations and to check on newly-released combinations.
Chapter 8
Ordering Information
55
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 22. Valid Ordering Part Number Combinations for Model 4
OPN
Package Type
Operating Voltage Plate Temperature
AMD-A0650MPR24B A
Card Module
1.7 V
0°C–70°C
AMD-A0700MPR24B A
Card Module
1.7 V
0°C–70°C
AMD-A0750MPR24B A
Card Module
1.7 V
0°C–70°C
AMD-A0800MPR24B A
Card Module
1.7 V
0°C–70°C
AMD-A0850MPR24B A
Card Module
1.7 V
0°C–70°C
AMD-A0900MMR24B A
Card Module
1.75 V
0°C–70°C
AMD-A0950MMR24B A
Card Module
1.75 V
0°C–70°C
AMD-A1000MMR24B A
Card Module
1.75 V
0°C–70°C
Notes:
This table lists configurations planned to be supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combinations and to check on newly-released combinations.
56
Ordering Information
Chapter 8
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Appendix A
Conventions, Abbreviations,
and References
This section contains information about the conventions and
abbreviations used in this document and a list of related
publications.
Signals and Bits
n
n
n
n
Appendix A
Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and
Low are written with an initial upper case letter.
Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by
a colon (for example, D[63:0]).
Reserved Bits and Signals—Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
Three-State—In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
57
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
n
21016M/0—June 2000
Invalid and Don’t-Care—In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen
pattern.
Data Terminology
The following list defines data terminology:
n
n
n
n
n
n
58
Quantities
• A word is two bytes (16 bits)
• A doubleword is four bytes (32 bits)
• A quadword is eight bytes (64 bits)
• An AMD Athlon™ processor cache line is eight
quadwords (64 bytes)
Addressing—Memory is addressed as a series of bytes on
eight-byte (64-bit) boundaries in which each byte can be
separately enabled.
Abbreviations—The following notation is used for bits and
bytes:
• Kilo (K, as in 4-Kbyte page)
• Mega (M, as in 4 Mbits/sec)
• Giga (G, as in 4 Gbytes of memory space)
See Table 24 for more abbreviations.
Little-Endian Convention—The byte with the address
xx...xx00 is in the least-significant byte position (little end).
In byte diagrams, bit positions are numbered from right to
left—the little end is on the right and the big end is on the
left. Data structure diagrams in memory show low addresses
at the bottom and high addresses at the top. When data
items are aligned, bit notation on a 64-bit data bus maps
directly to bit notation in 64-bit-wide memory. Because byte
addresses increase from right to left, strings appear in
reverse order when illustrated.
Bit Ranges—In text, bit ranges are shown with a dash (for
example, bits 9–1). When accompanied by a signal or bus
name, the highest and lowest bit numbers are contained in
brackets and separated by a colon (for example, AD[31:0]).
Bit Values—Bits can either be set to 1 or cleared to 0.
Appendix A
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
n
Hexadecimal and Binary Numbers—Unless the context
makes interpretation clear, hexadecimal numbers are
followed by an h and binary numbers are followed by a b.
Abbreviations and Acronyms
Table 24 contains the definitions of abbreviations used in this
document.
Table 23.
Abbreviations
Appendix A
Abbreviation
Meaning
A
Ampere
F
Farad
G
Giga-
Gbit
Gigabit
Gbyte
Gigabyte
H
Henry
h
Hexadecimal
K
Kilo-
Kbyte
Kilobyte
M
Mega-
Mbit
Megabit
Mbyte
Megabyte
MHz
Megahertz
m
Milli-
ms
Millisecond
mW
Milliwatt
µ
Micro-
µA
Microampere
µF
Microfarad
µH
Microhenry
µs
Microsecond
µV
Microvolt
n
nano-
nA
nanoampere
nF
nanofarad
nH
nanohenry
ns
nanosecond
59
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
Table 23.
21016M/0—June 2000
Abbreviations (continued)
Abbreviation
Meaning
ohm
Ohm
p
pico-
pA
picoampere
pF
picofarad
pH
picohenry
ps
picosecond
s
Second
V
Volt
W
Watt
Table 24 contains the definitions of acronyms used in this
document.
Table 24.
60
Acronyms
Abbreviation
Meaning
ACPI
Advanced Configuration and Power Interface
AGP
Accelerated Graphics Port
APCI
AGP Peripheral Component Interconnect
API
Application Programming Interface
APIC
Advanced Programmable Interrupt Controller
BIOS
Basic Input/Output System
BIST
Built-In Self-Test
BIU
Bus Interface Unit
DDR
Double-Data Rate
DIMM
Dual Inline Memory Module
DMA
Direct Memory Access
DRAM
Direct Random Access Memory
ECC
Error Correcting Code
EIDE
Enhanced Integrated Device Electronics
EISA
Extended Industry Standard Architecture
EPROM
Enhanced Programmable Read Only Memory
EV6
Digital™ Alpha™ Bus
FIFO
First In, First Out
GART
Graphics Address Remapping Table
Appendix A
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Table 24.
Appendix A
Acronyms (continued)
Abbreviation
Meaning
HSTL
High-Speed Transistor Logic
IDE
Integrated Device Electronics
ISA
Industry Standard Architecture
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LAN
Large Area Network
LRU
Least-Recently Used
LVTTL
Low Voltage Transistor Transistor Logic
MSB
Most Significant Bit
MTRR
Memory Type and Range Registers
MUX
Multiplexer
NMI
Non-Maskable Interrupt
OD
Open Drain
PBGA
Plastic Ball Grid Array
PA
Physical Address
PCI
Peripheral Component Interconnect
PDE
Page Directory Entry
PDT
Page Directory Table
PLL
Phase Locked Loop
PMSM
Power Management State Machine
POS
Power-On Suspend
POST
Power-On Self-Test
RAM
Random Access Memory
ROM
Read Only Memory
RXA
Read Acknowledge Queue
SDI
System DRAM Interface
SDRAM
Synchronous Direct Random Access Memory
SIP
Serial Initialization Packet
SMbus
System Management Bus
SPD
Serial Presence Detect
SRAM
Synchronous Random Access Memory
SROM
Serial Read Only Memory
TLB
Translation Lookaside Buffer
TOM
Top of Memory
61
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
Table 24.
62
21016M/0—June 2000
Acronyms (continued)
Abbreviation
Meaning
TTL
Transistor Transistor Logic
VAS
Virtual Address Space
VPA
Virtual Page Address
VGA
Video Graphics Adapter
USB
Universal Serial Bus
ZDB
Zero Delay Buffer
Appendix A
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
21016M/0—June 2000
Related Publications
The following books discuss various aspects of computer
architecture that may enhance your understanding of AMD
products:
AMD Publications
AMD Athlon™ Processor Technical Brief, order# 22054
AMD Athlon™ Processor Voltage Regulation Application Note,
order# 22651
AMD Athlon™ Processor Thermal Application Note, order# 22439
AMD-751™ System Controller Data Sheet, order# 21910
AMD-756™ Peripheral Bus Controller Data Sheet, order# 22548
AMD Processor Recognition Application Note, order# 20734
A M D A t h l o n ™ P r o c e s s o r M o d u l e S i g n a l a n d Po w e r -U p
Requirements Application Note, order#23811
AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
Websites
Visit the AMD website for documentation of AMD products.
www.amd.com
Other websites of interest include the following:
n
n
n
Appendix A
JEDEC home page—www.jedec.org
IEEE home page—www.computer.org
AGP Forum—www.agpforum.org
63
Preliminary Information
AMD Athlon™ Processor Module Data Sheet
64
21016M/0—June 2000
Appendix A