Features •

Features •

Features

Compatible with MCS

®

51 Products

4K Bytes of Reprogrammable Flash Memory

Endurance: 1,000 Write/Erase Cycles

2.7V to 6V Operating Range

Fully Static Operation: 0 Hz to 24 MHz

Two-level Program Memory Lock

128 x 8-bit Internal RAM

15 Programmable I/O Lines

Two 16-bit Timer/Counters

Six Interrupt Sources

Programmable Serial UART Channel

Direct LED Drive Outputs

On-chip Analog Comparator

Low-power Idle and Power-down Modes

Brown-out Detection

Description

The AT89C4051 is a low-voltage, high-performance CMOS 8-bit microcomputer with

4K bytes of Flash programmable and erasable read-only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C4051 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89C4051 provides the following standard features: 4K bytes of Flash,

128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five-vector, two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C4051 is designed with static logic for operation down to zero frequency and supports two software-selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin Configuration

PDIP/SOIC

RST/VPP

(RXD) P3.0

(TXD) P3.1

XTAL2

XTAL1

(INT0) P3.2

(INT1) P3.3

(TO) P3.4

(T1) P3.5

GND

3

4

5

1

2

8

9

6

7

10

20

19

18

17

16

15

14

13

12

11

VCC

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1 (AIN1)

P1.0 (AIN0)

P3.7

8-bit

Microcontroller with 4K Bytes

Flash

AT89C4051

Rev. 1001D–06/01

1

Block Diagram

2

AT89C4051

1001D–06/01

AT89C4051

Pin Description

VCC

GND

Port 1

Port 3

RST

XTAL1

XTAL2

Supply voltage.

Ground.

Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pullups.

P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input

(AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly.

When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7

are used as inputs and are externally pulled low, they will source current (I

IL

) because of the internal pullups.

Port 1 also receives code data during Flash programming and verification.

Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pullups.

P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I

IL

) because of the pullups.

Port 3 also serves the functions of various special features of the AT89C4051 as listed below:

Port Pin

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

Alternate Functions

RXD (serial input port)

TXD (serial output port)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (timer 0 external input)

T1 (timer 1 external input)

Port 3 also receives some control signals for Flash programming and verification.

Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device.

Each machine cycle takes 12 oscillator or clock cycles.

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

3

1001D–06/01

Oscillator

Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which

can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz

crystal or ceramic resonator may be used. To drive the device from an external clock

source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.

There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Figure 1.

Oscillator Connections

Note: C1, C2= 30 pF

±

10 pF for Crystals

= 40 pF

±

10 pF for Ceramic Resonators

Figure 2.

External Clock Drive Configuration

4

AT89C4051

1001D–06/01

AT89C4051

Special Function

Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below.

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Table 1.

AT89C4051 SFR Map and Reset Values

0F8H 0FFH

0F0H B

00000000

0E8H

0E0H ACC

00000000

0D8H

0D0H PSW

00000000

0C8H

98H

90H

88H

80H

0C0H

0B8H

0B0H

0A8H

IP

XXX00000

P3

11111111

IE

0XX00000

0A0H

SCON

00000000

P1

11111111

TCON

00000000

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

TL0

00000000

DPL

00000000

TL1

00000000

DPH

00000000

TH0

00000000

TH1

00000000

97H

8FH

PCON

0XXX0000

87H

0B7H

0AFH

0A7H

9FH

0D7H

0CFH

0C7H

0BFH

0F7H

0EFH

0E7H

0DFH

5

1001D–06/01

Restrictions on

Certain Instructions

Branching Instructions

MOVX-related

Instructions, Data

Memory

The AT89C4051 is an economical and cost-effective member of Atmel’s growing family of microcontrollers. It contains 4K bytes of Flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device.

All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 4K for the AT89C4051. This should be the responsibility of the software programmer.

For example, LJMP 0FE0H would be a valid instruction for the AT89C4051 (with 4K of memory), whereas LJMP 1000H would not.

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR. These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to FFFH for the 89C4051). Violating the physical space limits may cause unknown program behavior.

CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution.

For applications involving interrupts, the normal interrupt service routine address locations of the 80C51 family architecture have been preserved.

The AT89C4051 contains 128 bytes of internal data memory. Thus, in the AT89C4051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program.

A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly.

Program Memory

Lock Bits

On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table:

Lock Bit Protection Modes

(1)

Program Lock Bits

LB1 LB2

1

2

U

P

U

U

Protection Type

No program lock features

Further programming of the Flash is disabled

Note:

3 P P Same as mode 2, also verify is disabled

1. The Lock Bits can only be erased with the Chip Erase operation.

6

AT89C4051

1001D–06/01

AT89C4051

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.

The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external pullups are used.

It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

Power-down Mode

In the power-down mode the oscillator is stopped and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function

Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V

CC

is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external pullups are used.

Brown-out Detection

When V

CC

drops below the detection threshold, all port pins (except P1.0 and P1.1) are weakly pulled high. When V

CC

goes back up again, an internal Reset is automatically generated after a delay of typically 15 msec. The nominal brown-out detection threshold is 2.1V ± 10%.

V

CC

2.1V

2.1V

PORT PIN

INTERNAL RESET

15 msec.

7

1001D–06/01

8

Programming The

Flash

The AT89C4051 is shipped with the 4K bytes of on-chip PEROM code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time.

Once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically.

Internal Address Counter:

The AT89C4051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1.

Programming Algorithm:

To program the AT89C4051, the following sequence is recommended.

1.

2.

Power-up sequence:

Apply power between VCC and GND pins

Set RST and XTAL1 to GND

Set pin RST to “H”

Set pin P3.2 to “H”

3.

Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations shown in the PEROM Programming Modes table.

To Program and Verify the Array:

4.

Apply data for Code byte at location 000H to P1.0 to P1.7.

5.

6.

Raise RST to 12V to enable programming.

Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write cycle is self-timed and typically takes 1.2 ms.

7.

8.

To verify the programmed data, lower RST from 12V to logic “H” level and set pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port

P1 pins.

To program a byte at the next address location, pulse XTAL1 pin once to advance the internal address counter. Apply new data to the port P1 pins.

9.

Repeat steps 6 through 8, changing data and advancing the address counter for the entire 4K bytes array or until the end of the object file is reached.

10. Power-off sequence: set XTAL1 to “L” set RST to “L”

Turn V

CC

power off

Data Polling:

The AT89C4051 features Data Polling to indicate the end of a write cycle.

During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

Ready/Busy:

The Progress of byte programming can also be monitored by the

RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is pulled High again when programming is done to indicate

READY.

Program Verify:

If lock bits LB1 and LB2 have not been programmed code data can be read back via the data lines for verification:

1.

2.

Reset the internal address counter to 000H by bringing RST from “L” to “H”.

Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins.

AT89C4051

1001D–06/01

AT89C4051

3.

4.

5.

Pulse pin XTAL1 once to advance the internal address counter.

Read the next code data byte at the port P1 pins.

Repeat steps 3 and 4 until the entire array is read.

The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.

Chip Erase:

The entire PEROM array (4K bytes) and the two Lock Bits are erased electrically by using the proper combination of control signals and by holding P3.2 low for

10 ms. The code array is written with all “1”s in the Chip Erase operation and must be executed before any non-blank memory byte can be re-programmed.

Reading the Signature Bytes:

The signature bytes are read by the same procedure as a normal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7

must be pulled to a logic low. The values returned are as follows.

(000H) = 1EH indicates manufactured by Atmel

(001H) = 41H indicates 89C4051

Programming

Interface

Flash Programming Modes

Mode

Write Code Data

(1)(3)

Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.

All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

RST/V

PP

12V

P3.2/PROG P3.3

L

P3.4

H

P3.5

H

P3.7

H

Read Code Data

(1)

Write Lock Bit - 1

H

12V

H L

H

L

H

H

H

H

H

Bit - 2 12V H H L L

Chip Erase 12V H L L L

(2)

Read Signature Byte

Notes:

H H L L L L

1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at

XTAL1 pin.

2. Chip Erase requires a 10-ms PROG pulse.

3. P3.1 is pulled Low during programming to indicate RDY/BSY.

9

1001D–06/01

10

AT89C4051

Figure 3.

Programming the Flash Memory

AT89C4051

P3.1

RDY/BSY

PP

Figure 4.

Verifying the Flash Memory

AT89C4051

1001D–06/01

AT89C4051

Flash Programming and Verification Characteristics

T

A

= 20°C to 30°C, V

CC

= 5.0

±

10%

Symbol Parameter

t

ELQV t

EHQZ t

GHBL t

WC t

BHIH t

IHIL

Note:

V

PP

I

PP t

DVGL t

GHDX t

EHSH t

SHGL t

GHSL t

GLGH

Programming Enable Voltage

Programming Enable Current

Data Setup to PROG Low

Data Hold after PROG

P3.4 (ENABLE) High to V

PP

V

PP

Setup to PROG Low

V

PP

Hold after PROG

PROG Width

ENABLE Low to Data Valid

Data Float after ENABLE

PROG High to BUSY Low

Byte Write Cycle Time

RDY/BSY\ to Increment Clock Delay

Increment Clock High

1. Only used in 12-volt programming mode.

Flash Programming and Verification Waveforms

Min

11.5

1.0

1.0

1.0

10

10

1

0

Max

12.5

250

110

1.0

1.0

50

2.0

1.0

200 ns ms

µs ns

µs

µs

µs

µs

Units

V

µA

µs

µs

µs

µs

11

Absolute Maximum Ratings*

Operating Temperature ................................. -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage ............................................ 6.6V

DC Output Current...................................................... 25.0 mA

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

T

A

= -40°C to 85°C, V

CC

= 2.7V to 6.0V (unless otherwise noted)

I

I

Symbol

V

IL

V

IH

V

IH1

V

OL

V

OH

IL

TL

Parameter

Input Low-voltage

Input High-voltage

Input High-voltage

Output Low-voltage

(1)

(Ports 1, 3)

Output High-voltage

(Ports 1, 3)

Logical 0 Input Current

(Ports 1, 3)

Logical 1 to 0 Transition Current

(Ports 1, 3)

Condition

(Except XTAL1, RST)

(XTAL1, RST)

I

OL

I

OL

= 20 mA, V

CC

= 5V

= 10 mA, V

CC

= 2.7V

I

OH

= -80 µA, V

CC

= 5V

±

10%

I

OH

= -30 µA

I

OH

= -12 µA

V

IN

= 0.45V

V

IN

= 2V, V

CC

= 5V

±

10%

0.2 V

Min

-0.5

CC

0.7 V

2.4

+ 0.9

CC

0.75 V

CC

0.9 V

CC

Max

0.2 V

CC

- 0.1

V

CC

+ 0.5

V

CC

+ 0.5

0.5

-50

-750

Units

V

V

V

V

V

V

V

µA

µA

I

LI

Input Leakage Current

(Port P1.0, P1.1)

0 < V

IN

< V

CC

±

10 µA

V

OS

V

CM

Comparator Input Offset Voltage

Comparator Input Common

Mode Voltage

V

CC

= 5V

0

20

V

CC mV

V

I

RRST

C

IO

CC

Notes:

Reset Pulldown Resistor 50 300 K

Ω pF Pin Capacitance Test Freq. = 1 MHz, T

A

= 25°C

Active Mode, 12 MHz, V

CC

= 6V/3V

10

15/5.5

mA

Power Supply Current

Idle Mode, 12 MHz, V

CC

= 6V/3V

P1.0 & P1.1 = 0V or V

CC

5/1 mA

V

CC

= 6V P1.0 & P1.1 = 0V or V

CC

20 µA

Power-down Mode

(2)

V

CC

= 3V P1.0 & P1.1 = 0V or V

CC

5 µA

1. Under steady state (non-transient) conditions, I

OL

must be externally limited as follows:

Maximum I

OL

per port pin: 20 mA

Maximum total I

OL

for all output pins: 80 mA

If I

OL

exceeds the test condition, V

OL than the listed test conditions.

may exceed the related specification. Pins are not guaranteed to sink current greater

2. Minimum V

CC

for Power-down is 2V.

12

AT89C4051

1001D–06/01

AT89C4051

External Clock Drive Waveforms

External Clock Drive

Symbol

1/t

CLCL t

CLCL t

CHCX t

CLCX t

CLCH t

CHCL

Parameter

Oscillator Frequency

Clock Period

High Time

Low Time

Rise Time

Fall Time

V

CC

= 2.7V to 6.0V

Min Max

0

83.3

12

30

30

20

20

V

CC

= 4.0V to 6.0V

Min Max

0

41.6

24

15

15

20

20

Units

MHz ns ns ns ns ns

13

1001D–06/01

Serial Port Timing: Shift Register Mode Test Conditions

V

CC

= 5.0V

±

20%; Load Capacitance = 80 pF

12 MHz Osc

Symbol Parameter Min Max

t

XLXL t

QVXH t

XHQX t

XHDX t

XHDV

Serial Port Clock Cycle Time

Output Data Setup to Clock Rising Edge

Output Data Hold after Clock Rising Edge

Input Data Hold after Clock Rising Edge

Clock Rising Edge to Input Data Valid

1.0

700

50

0

700

Variable Oscillator

Min Max

12t

CLCL

10t

CLCL

-133

2t

CLCL

-117

0

10t

CLCL

-133

Shift Register Mode Timing Waveforms

Units

µ s ns ns ns ns

AC Testing Input/Output Waveforms

(1)

Note: 1. AC Inputs during testing are driven at V

CC min. for a logic 1 and V

IL

- 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V

max. for a logic 0.

IH

Float Waveforms

(1)

Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change frothe loaded V

OH

/V

OL level occurs.

14

AT89C4051

1001D–06/01

1001D–06/01

AT89C4051

20

I

C

C

15

10

m

A

5

0

0

AT89C4051

TYPICAL ICC - ACTIVE (85˚C)

Vcc=6.0V

Vcc=5.0V

Vcc=3.0V

6 12

FREQUENCY (MHz)

18 24

AT89C4051

TYPICAL ICC - IDLE (85˚C)

3

I

C

C

2

m

A

1

0

0

Vcc=5.0V

Vcc=6.0V

Vcc=3.0V

3 6

FREQUENCY (MHz)

9 12

20

AT89C4051

TYPICAL ICC vs. VOLTAGE- POWER DOWN (85˚C)

I

C

C

15

10

µ

A

5

0

3.0V

4.0V

Vcc VOLTAGE

5.0V

6.0V

Power-Down Mode Notes: 1. XTAL1 tied to GND for I

CC

(power-down)

2. P.1.0 and P1.1 = V

CC

or GND

3. Lock bits programmed

15

Ordering Information

Speed

(MHz)

12

Power

Supply

2.7V to 6.0V

24 4.0V to 6.0V

Ordering Code

AT89C4051-12PC

AT89C4051-12SC

AT89C4051-12PI

AT89C4051-12SI

AT89C4051-24PC

AT89C4051-24SC

AT89C4051-24PI

AT89C4051-24SI

Package

20P3

20S

20P3

20S

20P3

20S

20P3

20S

Operation Range

Commercial

(0

°

C to 70

°

C)

Industrial

(-40

°

C to 85

°

C)

Commercial

(0

°

C to 70

°

C)

Industrial

(-40

°

C to 85

°

C)

20P3

20S

Package Type

20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)

20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

16

AT89C4051

1001D–06/01

AT89C4051

Packaging Information

20P3

, 20-lead, 0.300" Wide, Plastic Dual Inline

Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 AD

1.060(26.9)

.980(24.9)

PIN

1

.280(7.11)

.240(6.10)

.210(5.33)

MAX

SEATING

PLANE

.150(3.81)

.115(2.92)

.110(2.79)

.090(2.29)

.900(22.86) REF

.070(1.78)

.045(1.13)

.015(.381) MIN

.022(.559)

.014(.356)

.325(8.26)

.300(7.62)

0

15

REF

.014(.356)

.008(.203)

.090(2.29)

MAX

.005(.127)

MIN

.430(10.92) MAX

20S

, 20-lead, 0.300" Wide, Plastic Gull WIng Small

Outline (SOIC)

Dimensions in Inches and (Millimeters)

0.020 (0.508)

0.013 (0.330)

0.299 (7.60)

0.291 (7.39)

0.420 (10.7)

0.393 (9.98)

PIN 1

.050 (1.27) BSC

0.513 (13.0)

0.497 (12.6)

0

8

REF

0.035 (0.889)

0.015 (0.381)

0.012 (0.305)

0.003 (0.076)

0.013 (0.330)

0.009 (0.229)

0.105 (2.67)

0.092 (2.34)

17

1001D–06/01

Atmel Headquarters

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Europe

Atmel SarL

Route des Arsenaux 41

Casa Postale 80

CH-1705 Fribourg

Switzerland

TEL (41) 26-426-5555

FAX (41) 26-426-5500

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Operations

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex

France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

Atmel Smart Card ICs

Scottish Enterprise Technology Park

East Kilbride, Scotland G75 0QR

TEL (44) 1355-357-000

FAX (44) 1355-242-743

Atmel Grenoble

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex

France

TEL (33) 4-7658-3000

FAX (33) 4-7658-3480

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

[email protected]

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.

MCS is a registered trademark of Intel Corporation.

Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

1001D–06/01/xM

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