MOTOROLA MC68360 QUad Integrated Communications Controller

MOTOROLA MC68360 QUad Integrated Communications Controller
Freescale Semiconductor, Inc.
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MOTOROLA
MC68360
QUad Integrated
Communications Controller
User’s Manual
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MC68360 USER’S MANUAL
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MOTOROLA
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PREFACE
The complete documentation package for the MC68360 consists of the MC68360UM/AD,
MC68360 QUad Integrated Communications Controller User’s Manual , M68000PM/AD,
MC68000 Family Programmer’s Reference Manual, and the MC68360/D, MC68360 QUad
Integrated Communications Controller Product Brief.
Freescale Semiconductor, Inc...
The MC68360 QUad Integrated Communications Controller User’s Manual describes the
programming, capabilities, registers, and operation of the MC68360 and the MC68EN360;
the MC68000 Family Programmer’s Reference Manual provides instruction details for the
MC68360; and the MC68360 QUad Integrated Communications Controller Product Brief
provides a brief description of the MC68360 capabilities.
This user’s manual is organized as follows:
Section 1
Section 2
Section 3
Section 4
Section 5
Section 6
Section 7
Section 8
Section 9
Section 10
Section 11
Appendix A
Appendix B
Appendix C
Appendix D
MOTOROLA
Introduction
Signal Descriptions
Memory Map
Bus Operation
CPU32+
System Integration Module (SIM60)
Communication Processor Module (CPM)
IEEE 1149.1 Test Access Port
Applications
Electrical Characteristics
Ordering Information and Mechanical Data
Serial Performance
Development Tools and Support
RISC Microcode from RAM
MC68MH360 Product Brief
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Paragraph
Number
1.1
1.2
1.2.1
1.2.2
1.2.3
1.3
1.3.1
1.3.2
1.3.3
1.4
1.5
1.6
1.7
2.1
2.1.1
2.1.1.1
2.1.1.2
2.1.2
2.1.3
2.1.3.1
2.1.3.2
2.1.4
2.1.4.1
2.1.4.2
2.1.4.3
2.1.4.4
2.1.5
2.1.5.1
2.1.5.2
2-6
2.1.5.3
1).
2.1.5.4
2.1.6
2.1.7
2.1.7.1
2.1.7.2
2.1.7.3
2.1.7.4
MOTOROLA
Title
Table of Contents
Page
Number
Section 1
Introduction
QUICC Key Features .............................................................................. 1-1
QUICC Architecture Overview................................................................. 1-4
CPU32+ Core.......................................................................................... 1-5
System Integration Module (SIM60)........................................................ 1-5
Communications Processor Module (CPM) ............................................ 1-6
Upgrading Designs from the MC68302 ................................................... 1-6
Architectural Approach ............................................................................ 1-6
Hardware Compatibility Issues................................................................ 1-7
Software Compatibility Issues ................................................................. 1-7
QUICC Glueless System Design............................................................. 1-8
QUICC Serial Configurations .................................................................. 1-9
QUICC Serial Configuration Examples ................................................. 1-16
QUICC System Bus Configurations ...................................................... 1-17
Section 2
Signal Descriptions
System Bus Signal Index ........................................................................ 2-1
Address Bus ............................................................................................ 2-1
Address Bus (A27–A0)............................................................................ 2-1
Address Bus (A31–A28).......................................................................... 2-1
Function Codes (FC3–FC0) .................................................................... 2-5
Data Bus.................................................................................................. 2-5
Data Bus (D31–D16). .............................................................................. 2-5
Data Bus (D15–D0). ................................................................................ 2-6
Parity ....................................................................................................... 2-6
Parity (PRTY0). ....................................................................................... 2-6
Parity (PRTY1). ....................................................................................... 2-6
Parity (PRTY2). ....................................................................................... 2-6
Parity (PRTY3). ....................................................................................... 2-6
Memory Controller................................................................................... 2-6
Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) ................... 2-6
Chip Select/Row Address Select/Interrupt Acknowledge (CS7/RAS7/IACK7).
Column Address Select/Interrupt Acknowledge (CAS3–CAS0/IACK6, 3, 2,
2-7
Address Multiplex (AMUX). ..................................................................... 2-7
Interrupt Request Level (IRQ7–IRQ1)..................................................... 2-7
Bus Control Signals................................................................................. 2-7
Data and Size Acknowledge (DSACK1–DSACK0). ................................ 2-8
Autovector/Interrupt Acknowledge (AVEC/IACK5).................................. 2-8
Address Strobe (AS). .............................................................................. 2-8
Data Strobe (DS)..................................................................................... 2-8
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Title
Page
Number
2.1.7.5
Transfer Size (SIZ1, SIZ0). ......................................................................2-8
2.1.7.6
Read/Write (R/W).....................................................................................2-8
2.1.7.7
Output Enable/Address Multiplex (OE/AMUX).........................................2-9
2.1.7.8
Byte Write Enable (WE3–WE0). ..............................................................2-9
2.1.8
Bus Arbitration Signals.............................................................................2-9
2.1.8.1
Bus Request (BR). ...................................................................................2-9
2.1.8.2
Bus Grant (BG). .......................................................................................2-9
2.1.8.3
Bus Grant Acknowledge (BGACK). .........................................................2-9
2.1.8.4
Read-Modify-Write Cycle/Initial Configuration (RMC/CONFIG0).............2-9
2.1.8.5
Bus Clear Out/Initial Configuration/Row Address Select Double-Drive (BCLRO/CONFIG1/RAS2DD).2-9
2.1.9
System Control Signals..........................................................................2-10
2.1.9.1
Soft Reset (RESETS). ...........................................................................2-10
2.1.9.2
Hard Reset (RESETH)...........................................................................2-10
2.1.9.3
Halt (HALT). ...........................................................................................2-10
2.1.9.4
Bus Error (BERR). .................................................................................2-10
2.1.10
Clock Signals .........................................................................................2-10
2.1.10.1
System Clock Outputs (CLKO2–CLKO1). .............................................2-10
2.1.10.2
Crystal Oscillator (EXTAL, XTAL). .........................................................2-11
2.1.10.3
External Filter Capacitor (XFC)..............................................................2-11
2.1.10.4
Clock Mode Select (MODCK1–MODCK0).............................................2-11
2.1.11
Instrumentation and Emulation Signals .................................................2-11
2.1.11.1
Instruction Fetch/Development Serial Input (IFETCH/DSI)....................2-11
2.1.11.2
Instruction Pipe/Development Serial Output (IPIPE0/DSO)...................2-11
2.1.11.3
Instruction Pipe/Row Address Select Double-Drive (IPIPE1/RAS1DD).2-11
2.1.11.4
Breakpoint/Development Serial clock (BKPT/DSCLK). .........................2-11
2.1.11.5
Freeze/Initial Configuration (FREEZE/CONFIG2). ................................2-12
2.1.12
Test Signals ...........................................................................................2-12
2.1.12.1
TRI-State Signal (TRIS). ........................................................................2-12
2.1.12.2
Test Reset (TRST).................................................................................2-12
2.1.12.3
Test Clock (TCK). ..................................................................................2-12
2.1.12.4
Test Mode Select (TMS). .......................................................................2-12
2.1.12.5
Test Data In (TDI). .................................................................................2-12
2.1.12.6
Test Data Out (TDO)..............................................................................2-12
2.1.13
Initial Configuration Pins (CONFIG).......................................................2-12
2.1.14
Power Signals ........................................................................................2-13
2.1.14.1
VCCSYN and GNDSYN.........................................................................2-13
2.1.14.2
VCCCLK and GNDCLK. ........................................................................2-13
2.1.14.3
GNDS1 and GNDS2. .............................................................................2-13
2.1.14.4
VCC and GND. ......................................................................................2-13
2.1.14.5
NC4–NC1...............................................................................................2-13
2.2
System Bus Signal Index in Slave Mode ...............................................2-14
2.3
On-Chip Peripherals Signal Index..........................................................2-15
Section 3
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Number
Title
Table of Contents
Page
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3.1
3.2
3.3
3.3.1
3.3.2
QUICC Memory Map
Dual-Port RAM Memory Map .................................................................. 3-2
CPM Sub-Module Base Addresses......................................................... 3-3
Internal Registers Memory Map .............................................................. 3-4
SIM Registers Memory Map.................................................................... 3-4
CPM Registers Memory Map .................................................................. 3-6
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.9.1
4.1.9.2
4.1.9.3
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.4.1
4.4.4.2
4.4.4.3
4.5
4.5.1
4.5.2
4.5.3
4.5.4
Section 4
Bus Operation
Bus Transfer Signals ............................................................................... 4-2
Bus Control Signals................................................................................. 4-3
Function Codes (FC3–FC0) .................................................................... 4-3
Address Bus (A31–A0)............................................................................ 4-4
Address Strobe (AS) ............................................................................... 4-4
Data Bus (D31-D0).................................................................................. 4-4
Data Strobe (DS)..................................................................................... 4-4
Output Enable (OE)................................................................................. 4-4
Byte Write Enable (WE0, WE1, WE2, WE3) ........................................... 4-4
Bus Cycle Termination Signals ............................................................... 4-5
Data transfer and size acknowledge (DSACK1 and DSACK0). .............. 4-5
Bus Error (BERR).................................................................................... 4-5
Autovector (AVEC). ................................................................................. 4-6
Data Transfer Mechanism ....................................................................... 4-6
Dynamic Bus Sizing ................................................................................ 4-6
Misaligned Operands ............................................................................ 4-11
Effects of Dynamic Bus Sizing and Operand Misalignment .................. 4-19
Bus Operation ....................................................................................... 4-20
Synchronous Operation with DSACKx .................................................. 4-21
Fast Termination Cycles........................................................................ 4-21
Data Transfer Cycles............................................................................. 4-22
Read Cycle............................................................................................ 4-23
Write Cycle ............................................................................................ 4-26
Read-Modify-Write Cycle ...................................................................... 4-28
CPU Space Cycles................................................................................ 4-31
Breakpoint Acknowledge Cycle............................................................. 4-31
LPSTOP Broadcast Cycle ..................................................................... 4-35
Module Base Address Register (MBAR) Access .................................. 4-36
Interrupt Acknowledge Bus Cycles........................................................ 4-36
Interrupt Acknowledge Cycle—Terminated Normally............................ 4-36
Autovector Interrupt Acknowledge Cycle. ............................................. 4-38
Spurious Interrupt Cycle........................................................................ 4-40
Bus Exception Control Cycles ............................................................... 4-41
Bus Errors ............................................................................................. 4-42
Retry Operation ..................................................................................... 4-44
Halt Operation ....................................................................................... 4-46
Double Bus Fault................................................................................... 4-48
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Number
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Title
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Number
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.6.1
4.6.6.2
4.6.7
4.6.8
4.7
Bus Arbitration .......................................................................................4-49
Bus Request ..........................................................................................4-52
Bus Grant...............................................................................................4-53
Bus Grant Acknowledge ........................................................................4-53
Bus Arbitration Control...........................................................................4-54
Slave (Disable CPU32+) Mode Bus Arbitration .....................................4-55
Slave (Disable CPU32+) Mode Bus Exceptions ....................................4-59
HALT......................................................................................................4-59
RETRY...................................................................................................4-59
Internal Accesses...................................................................................4-59
Show Cycles ..........................................................................................4-62
Reset Operation.....................................................................................4-63
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
5.3.3.5
5.3.3.6
5.3.3.7
5.3.3.8
5.3.3.9
5.3.3.10
5.3.4
5.3.4.1
5.3.4.2
Section 5
CPU32+
Overview ..................................................................................................5-1
Features...................................................................................................5-2
Loop Mode Instruction Execution.............................................................5-3
Vector Base Register ...............................................................................5-4
Exception Handling ..................................................................................5-4
Addressing Modes ...................................................................................5-5
Architecture Summary .............................................................................5-5
Programming Model.................................................................................5-6
Registers..................................................................................................5-7
Instruction Set ..........................................................................................5-8
M68000 Family Compatibility.................................................................5-10
New Instructions. ...................................................................................5-10
Low-Power Stop (LPSTOP). ..................................................................5-10
Table Lookup and Interpolate (TBL). .....................................................5-10
Unimplemented Instructions. .................................................................5-10
Instruction Format and Notation.............................................................5-10
Instruction Summary ..............................................................................5-13
Condition Code Register........................................................................5-17
Data Movement Instructions ..................................................................5-19
Integer Arithmetic Operations ................................................................5-19
Logic Instructions. ..................................................................................5-21
Shift and Rotate Instructions..................................................................5-22
Bit Manipulation Instructions ..................................................................5-23
Binary-Coded Decimal (BCD) Instructions.............................................5-24
Program Control Instructions .................................................................5-24
System Control Instructions ...................................................................5-25
Condition Tests ......................................................................................5-26
Using the TBL Instructions.....................................................................5-27
Table Example 1: Standard Usage ........................................................5-28
Table Example 2: Compressed Table....................................................5-29
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Paragraph
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5.3.4.3
5.3.4.4
5.3.4.5
5.3.5
5.3.6
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.5.2.4
5.5.2.5
5.5.2.6
5.5.2.7
5.5.2.8
5.5.2.9
5.5.2.10
5.5.2.11
5.5.2.12
5.5.3
5.5.3.1
5.5.3.1.1
5.5.3.1.2
5.5.3.1.3
5.5.3.1.4
5.5.3.2
5.5.3.2.1
5.5.3.2.2
5.5.3.2.3
5.5.3.2.4
5.5.3.2.5
5.5.3.2.6
5.5.3.2.7
5.5.4
MOTOROLA
Title
Table of Contents
Page
Number
Table Example 3: 8-Bit Independent Variable....................................... 5-30
Table Example 4: Maintaining Precision ............................................... 5-32
Table Example 5: Surface Interpolations .............................................. 5-33
Nested Subroutine Calls........................................................................ 5-33
Pipeline Synchronization with the NOP Instruction ............................... 5-34
Processing States ................................................................................. 5-34
State Transitions ................................................................................... 5-34
Privilege Levels ..................................................................................... 5-34
Supervisor Privilege Level..................................................................... 5-35
User Privilege Level .............................................................................. 5-35
Changing Privilege Level....................................................................... 5-35
Exception Processing............................................................................ 5-36
Exception Vectors ................................................................................. 5-36
Types of Exceptions .............................................................................. 5-36
Exception Processing Sequence........................................................... 5-38
Exception Stack Frame ......................................................................... 5-38
Multiple Exceptions ............................................................................... 5-39
Processing of Specific Exceptions ........................................................ 5-40
Reset ..................................................................................................... 5-40
Bus Error ............................................................................................... 5-40
Address Error ........................................................................................ 5-42
Instruction Traps.................................................................................... 5-42
Software Breakpoints ............................................................................ 5-43
Hardware Breakpoints........................................................................... 5-43
Format Error .......................................................................................... 5-43
Illegal or Unimplemented Instructions ................................................... 5-44
Privilege Violations ................................................................................ 5-44
Tracing .................................................................................................. 5-45
Interrupts ............................................................................................... 5-46
Return from Exception........................................................................... 5-47
Fault Recovery ...................................................................................... 5-48
Types of Faults...................................................................................... 5-51
Type I—Released Write Faults ............................................................. 5-51
Type II—Prefetch, Operand, RMW, and MOVEP Faults....................... 5-51
Type III—Faults During MOVEM Operand Transfer ............................. 5-52
Type IV—Faults During Exception Processing ..................................... 5-52
Correcting a Fault.................................................................................. 5-53
Type I—Completing Released Writes via Software .............................. 5-53
Type I—Completing Released Writes via RTE ..................................... 5-53
Type II—Correcting Faults via RTE....................................................... 5-54
Type III—Correcting Faults via Software............................................... 5-54
Type III—Correcting Faults by Conversion and Restart........................ 5-55
Type III—Correcting Faults via RTE...................................................... 5-55
Type IV—Correcting Faults via Software .............................................. 5-55
CPU32+ Stack Frames ......................................................................... 5-56
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5.5.4.1
5.5.4.2
5.5.4.3
5.6
5.6.1
5.6.1.1
5.6.1.2
5.6.1.3
5.6.2
5.6.2.1
5.6.2.2
5.6.2.2.1
5.6.2.2.2
5.6.2.2.3
5.6.2.3
5.6.2.4
5.6.2.5
5.6.2.5.1
5.6.2.5.2
5.6.2.5.3
5.6.2.6
5.6.2.7
5.6.2.7.1
5.6.2.7.2
5.6.2.8
5.6.2.8.1
5.6.2.8.2
5.6.2.8.3
5.6.2.8.4
5.6.2.8.5
5.6.2.8.6
5.6.2.8.7
5.6.2.8.8
5.6.2.8.9
5.6.2.8.10
5.6.2.8.11
5.6.2.8.12
5.6.2.8.13
5.6.2.8.14
5.6.2.8.15
5.6.2.8.16
5.6.3
5.6.3.1
5.6.3.2
5.6.3.3
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Title
Page
Number
Four-Word Stack Frame ........................................................................5-56
Six-Word Stack Frame...........................................................................5-56
Bus Error Stack Frame ..........................................................................5-56
Development Support ............................................................................5-59
CPU32+ Integrated Development Support ............................................5-59
Background Debug Mode (BDM) Overview...........................................5-59
Deterministic Opcode Tracking Overview..............................................5-60
On-Chip Hardware Breakpoint Overview...............................................5-60
Background Debug Mode ......................................................................5-60
Enabling BDM ........................................................................................5-60
BDM Sources.........................................................................................5-61
External BKPT Signal ............................................................................5-62
BGND Instruction ...................................................................................5-62
Double Bus Fault ...................................................................................5-62
Entering BDM.........................................................................................5-62
Command Execution..............................................................................5-62
BDM Registers.......................................................................................5-63
Fault Address Register (FAR)................................................................5-63
Return Program Counter (RPC).............................................................5-63
Current Instruction Program Counter (PCC)..........................................5-63
Returning from BDM ..............................................................................5-63
Serial Interface.......................................................................................5-63
CPU Serial Logic....................................................................................5-65
Development System Serial Logic .........................................................5-66
Command Set ........................................................................................5-68
Command Format ..................................................................................5-68
Command Sequence Diagram...............................................................5-69
Command Set Summary........................................................................5-69
Read A/D Register (RAREG/RDREG)...................................................5-71
Write A/D Register (WAREG/WDREG) .................................................5-71
Read System Register (RSREG)...........................................................5-71
Write System Register (WSREG) ..........................................................5-72
Read Memory Location (READ) ............................................................5-73
Write Memory Location (WRITE) ...........................................................5-74
Dump Memory Block (DUMP)................................................................5-75
Fill Memory Block (FILL) ........................................................................5-76
Resume Execution (GO)........................................................................5-77
Call User Code (CALL) ..........................................................................5-77
Reset Peripherals (RST)........................................................................5-79
No Operation (NOP) ..............................................................................5-79
Future Commands .................................................................................5-80
Deterministic Opcode Tracking..............................................................5-80
Instruction Fetch (IFETCH) ....................................................................5-80
Instruction Pipe (IPIPE1–IPIPE0) ..........................................................5-80
Opcode Tracking during Loop Mode......................................................5-82
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5.7
5.7.1
5.7.1.1
5.7.1.2
5.7.1.3
5.7.1.3.1
5.7.1.3.2
5.7.1.3.3
5.7.1.4
5.7.1.5
5.7.1.6
5.7.1.7
5.7.2
5.7.2.1
5.7.2.2
5.7.2.3
5.7.2.4
5.7.2.5
5.7.2.6
5.7.2.7
5.7.2.8
5.7.2.9
5.7.2.10
5.7.2.11
5.7.2.12
5.7.2.13
5.7.2.14
Instruction Execution Timing ................................................................. 5-82
Resource Scheduling ............................................................................ 5-83
Microsequencer..................................................................................... 5-83
Instruction Pipeline ................................................................................ 5-83
Bus Controller Resources ..................................................................... 5-83
Prefetch Controller ................................................................................ 5-84
Write-Pending Buffer ............................................................................. 5-84
Microbus Controller ............................................................................... 5-85
Instruction Execution Overlap ............................................................... 5-85
Effects of Wait States ............................................................................ 5-86
Instruction Execution Time Calculation ................................................. 5-86
Effects of Negative Tails........................................................................ 5-87
Instruction Timing Tables ...................................................................... 5-88
Fetch Effective Address ........................................................................ 5-90
Calculate Effective Address .................................................................. 5-91
MOVE Instruction .................................................................................. 5-92
Special-Purpose MOVE Instruction....................................................... 5-92
Arithmetic/Logic Instructions ................................................................. 5-93
Immediate Arithmetic/Logic Instructions................................................ 5-95
Binary-Coded Decimal and Extended Instructions................................ 5-95
Single Operand Instructions .................................................................. 5-96
Shift/Rotate Instructions ........................................................................ 5-96
Bit Manipulation Instructions ................................................................. 5-97
Conditional Branch Instructions............................................................. 5-98
Control Instructions ............................................................................... 5-99
Exception-Related Instructions and Operations .................................. 5-100
Save and Restore Operations ............................................................. 5-101
6.1
6.2
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.2.1
6.3.1.2.2
6.3.1.2.3
6.3.1.2.4
6.3.2
6.3.2.1
6.3.2.2
6.3.3
6.3.4
6.4
Section 6
System Integration Module (SIM60)
Module Overview..................................................................................... 6-1
Module Base Address Register (MBAR) ................................................. 6-3
System Configuration and Protection...................................................... 6-3
System Configuration .............................................................................. 6-5
SIM60 Interrupt Generation..................................................................... 6-6
Simultaneous SIM60 Interrupt Sources................................................... 6-8
Bus Monitor ............................................................................................. 6-8
Spurious Interrupt Monitor....................................................................... 6-8
Double Bus Fault Monitor........................................................................ 6-9
Software Watchdog Timer (SWT) ........................................................... 6-9
Periodic Interrupt Timer (PIT)................................................................ 6-10
PIT Period Calculation........................................................................... 6-10
Using the PIT as a Real-Time Clock ..................................................... 6-11
Freeze Support...................................................................................... 6-11
Low-Power Stop Support ...................................................................... 6-11
Low Power in Normal Operation ........................................................... 6-12
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6.5
6.5.1
6.5.2
6.5.3
6.5.3.1
6.5.3.2
6.5.4
6.5.5
6.5.5.1
6.5.5.2
6.5.5.3
6.5.5.4
6.5.5.5
6.5.5.6
6.5.5.7
6.5.6
6.5.6.1
6.5.6.2
6.5.6.3
6.5.7
6.5.7.1
6.5.7.2
6.5.8
6.6
6.7
6.7.1
6.7.2
6.7.3
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.9
6.9.1
6.9.2
6.9.3
6.9.3.1
6.9.3.2
6.9.3.3
6.9.3.4
6.9.3.5
6.9.3.6
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Title
Page
Number
SIM60 System Clock Generation...........................................................6-12
Clock Generation Methods ....................................................................6-12
Oscillator Prescaler (Divide by 128).......................................................6-13
Phase-Locked Loop (PLL) .....................................................................6-14
Frequency Multiplication ........................................................................6-14
Skew Elimination....................................................................................6-15
Low-Power Divider.................................................................................6-15
QUICC Internal Clock Signals................................................................6-15
SPCLK ...................................................................................................6-16
General System Clock ...........................................................................6-16
BRGCLK ................................................................................................6-17
SyncCLK ................................................................................................6-17
SIMCLK..................................................................................................6-18
CLKO1 ...................................................................................................6-18
CLKO2 ...................................................................................................6-18
PLL Power Pins .....................................................................................6-19
VCCSYN ................................................................................................6-19
GNDSYN................................................................................................6-19
XFC........................................................................................................6-19
CLKO Power Pins ..................................................................................6-19
VCCCLK ................................................................................................6-19
GNDCLK ................................................................................................6-19
Configuration Pins (MODCK1–MODCK0) .............................................6-19
Breakpoint Logic ....................................................................................6-20
External Bus Interface Control ...............................................................6-21
Initial Configuration ................................................................................6-22
Port D.....................................................................................................6-22
Port E .....................................................................................................6-23
Slave (Disable CPU32+) Mode ..............................................................6-23
MBAR in a Multiple QUICC System.......................................................6-24
Global Chip Select (CS0) in Slave Mode ...............................................6-25
Bus Clear in Slave Mode .......................................................................6-25
Interrupts in Slave Mode ........................................................................6-26
Pin Differences in Slave Mode...............................................................6-26
Other Functionality in Slave Mode .........................................................6-27
Programmer’s Model..............................................................................6-27
Module Base Address Register (MBAR)................................................6-27
Module Base Address Register Enable (MBARE) .................................6-29
System Configuration and Protection Registers ....................................6-29
Module Configuration Register (MCR)...................................................6-29
Autovector Register (AVR).....................................................................6-34
Reset Status Register (RSR) .................................................................6-34
Software Watchdog Interrupt Vector Register (SWIV)...........................6-35
System Protection Control Register (SYPCR) .......................................6-35
Periodic Interrupt Control Register (PICR).............................................6-37
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Title
Table of Contents
Page
Number
6.9.3.7
6.9.3.8
6.9.3.9
6.9.3.10
6.9.3.11
6.9.3.12
6.9.3.13
6.9.4
6.10
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.11.7
6.11.8
6.11.9
6.12
6.12.1
6.12.2
6.12.3
6.12.4
6.12.5
6.12.6
6.12.7
6.12.8
6.13
6.13.1
6.13.2
6.13.3
6.13.4
6.13.5
Periodic Interrupt Timer Register (PITR)............................................... 6-38
Software Service Register (SWSR)....................................................... 6-39
CLKO Control Register (CLKOCR) ....................................................... 6-39
PLL Control Register (PLLCR) .............................................................. 6-40
Clock Divider Control Register (CDVCR) .............................................. 6-42
Breakpoint Address Register (BKAR) ................................................... 6-44
Breakpoint Control Register (BKCR)..................................................... 6-44
Port E Pin Assignment Register (PEPAR) ............................................ 6-48
Memory Controller................................................................................. 6-50
Memory Controller Key Features .......................................................... 6-50
Memory Controller Overview................................................................. 6-51
General-Purpose Chip-Select Overview (SRAM Banks)....................... 6-56
Associated Registers............................................................................. 6-56
8-, 16-, and 32-Bit Port Size Configuration............................................ 6-56
Write Protect Configuration ................................................................... 6-56
Programmable Wait State Configuration............................................... 6-56
Address and Address Space Checking................................................. 6-57
SRAM Bank Parity................................................................................. 6-57
External Master Support........................................................................ 6-57
Global (Boot) Chip-Select Operation..................................................... 6-58
SRAM Bus Error.................................................................................... 6-58
DRAM Controller Overview (DRAM Banks) .......................................... 6-58
DRAM Normal Access Support ............................................................. 6-60
DRAM Page Mode Support................................................................... 6-60
DRAM Burst Access Support ................................................................ 6-61
DRAM Bank Parity ................................................................................ 6-62
Refresh Operation ................................................................................. 6-62
DRAM Bank External Master Support................................................... 6-63
Double-Drive RAS Lines ....................................................................... 6-63
DRAM Bus Error.................................................................................... 6-63
Programming Model .............................................................................. 6-64
Global Memory Register (GMR)............................................................ 6-64
Memory Controller Status Register (MSTAT)........................................ 6-69
Base Register (BR) ............................................................................... 6-70
Option Register (OR)............................................................................. 6-74
DRAM-SRAM Performance Summary; ................................................. 6-78
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
Section 7
Communication Processor Module (CPM)
Introduction.............................................................................................. 7-1
RISC Controller ....................................................................................... 7-3
RISC Controller Configuration Register (RCCR).................................... 7-4
RISC Microcode Revision Number......................................................... 7-5
Command Set ........................................................................................ 7-5
Command Register Examples................................................................. 7-8
Command Execution Latency ................................................................. 7-8
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7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.5
7.5.1
7.5.2
7.5.2.1
7.5.2.2
7.5.2.3
7.5.2.4
7.5.2.5
7.5.2.6
7.5.2.7
7.5.3
7.6
7.6.1
7.6.2
7.6.2.1
7.6.2.2
7.6.2.3
7.6.2.4
7.6.2.5
7.6.2.6
7.6.2.7
7.6.2.8
7.6.2.9
7.6.3
7.6.3.1
7.6.3.2
7.6.4
7.6.4.1
7.6.4.2
7.6.4.2.1
7.6.4.2.2
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Title
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Number
Dual-Port RAM.........................................................................................7-8
Buffer Descriptors ..................................................................................7-10
Parameter RAM .....................................................................................7-10
RISC Timer Tables ................................................................................7-11
RISC Timer Table Parameter RAM .......................................................7-12
RISC Timer Table Entries ......................................................................7-14
RISC Timer Event Register (RTER) ......................................................7-14
RISC Timer Mask Register (RTMR) ......................................................7-14
SET TIMER Command ..........................................................................7-14
RISC Timer Initialization Sequence .......................................................7-14
RISC Timer Initialization Example .........................................................7-15
RISC Timer Interrupt Handling..............................................................7-16
RISC Timer Table Algorithm .................................................................7-16
RISC Timer Table Application: Track the RISC Loading .......................7-16
Timers ...................................................................................................7-17
Timer Key Features ...............................................................................7-17
General-Purpose Timer Units ...............................................................7-18
Cascaded Mode.....................................................................................7-19
Timer Global Configuration Register (TGCR) ........................................7-20
Timer Mode Register (TMR1, TMR2, TMR3, TMR4).............................7-21
Timer Reference Registers (TRR1, TRR2, TRR3, TRR4) .....................7-22
Timer Capture Registers (TCR1, TCR2, TCR3, TCR4).........................7-22
Timer Counter (TCN1, TCN2, TCN3, TCN4) .........................................7-22
Timer Event Registers (TER1, TER2, TER3, TER4) .............................7-22
Timer Examples .....................................................................................7-23
IDMA Channels......................................................................................7-24
IDMA Key Features;..............................................................................7-25
IDMA Registers.....................................................................................7-26
IDMA Channel Configuration Register (ICCR).......................................7-26
Channel Mode Register (CMR)..............................................................7-28
Source Address Pointer Register (SAPR) .............................................7-30
Destination Address Pointer Register (DAPR).......................................7-31
Function Code Register (FCR) ..............................................................7-31
Byte Count Register (BCR)....................................................................7-31
Channel Status Register (CSR) .............................................................7-32
Channel Mask Register (CMAR)............................................................7-33
Data Holding Register (DHR).................................................................7-33
Interface Signals ...................................................................................7-33
DREQ and DACK...................................................................................7-33
DONEx...................................................................................................7-33
IDMA Operation ....................................................................................7-34
Single Buffer ..........................................................................................7-34
Auto Buffer and Buffer Chaining ............................................................7-34
IDMA Parameter RAM ...........................................................................7-35
IDMA Buffer Descriptors (BDs) ..............................................................7-36
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7.6.4.2.3
7.6.4.3
7.6.4.4
7.6.4.4.1
7.6.4.4.2
7.6.4.4.3
7.6.4.4.4
7.6.4.5
7.6.4.6
7.6.4.6.1
7.6.4.6.2
7.6.4.6.3
7.6.4.6.4
7.6.4.7
7.6.4.7.1
7.6.4.7.2
7.6.4.7.3
7.6.4.8
7.6.4.8.1
7.6.4.8.2
7.6.4.8.3
7.6.5
7.6.5.1
7.6.5.2
7.6.5.3
7.7
7.7.1
7.7.2
7.7.2.1
7.7.2.2
7.7.2.3
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.8.4.1
7.8.4.2
7.8.4.3
7.8.4.4
7.8.4.5
7.8.4.6
7.8.4.7
7.8.5
7.8.5.1
MOTOROLA
Title
Table of Contents
Page
Number
IDMA Commands (INIT_IDMA)............................................................. 7-38
Starting the IDMA .................................................................................. 7-38
Requesting IDMA Transfers .................................................................. 7-39
Internal Maximum Rate ......................................................................... 7-39
Internal Limited Rate ............................................................................. 7-39
External Burst Mode.............................................................................. 7-40
External Cycle Steal .............................................................................. 7-42
IDMA Bus Arbitration............................................................................. 7-43
IDMA Operand Transfers ...................................................................... 7-45
Dual Address Mode............................................................................... 7-45
Single Address Mode (Flyby Transfers) ................................................ 7-48
Fast-Termination Option........................................................................ 7-50
Externally Recognizing IDMA Operand Transfers................................. 7-51
Bus Exceptions...................................................................................... 7-51
Reset ..................................................................................................... 7-51
Bus Error ............................................................................................... 7-51
Retry...................................................................................................... 7-51
Ending the IDMA Transfer..................................................................... 7-52
Single Buffer Mode Termination............................................................ 7-52
Auto Buffer Mode Termination. ............................................................. 7-53
Buffer Chaining Mode Termination........................................................ 7-54
IDMA Examples.................................................................................... 7-55
Single Buffer Examples ......................................................................... 7-55
Buffer Chaining Example....................................................................... 7-55
Auto Buffer Example ............................................................................. 7-56
SDMA Channels.................................................................................... 7-57
SDMA Bus Arbitration and Bus Transfers ............................................. 7-57
SDMA Registers.................................................................................... 7-59
SDMA Configuration Register (SDCR).................................................. 7-59
SDMA Status Register (SDSR) ............................................................. 7-61
SDMA Address Register (SDAR) .......................................................... 7-61
Serial Interface with Time Slot Assigner................................................ 7-62
SI Key Features.................................................................................... 7-62
TSA Overview ...................................................................................... 7-64
Enabling Connections to the TSA ........................................................ 7-67
SI RAM ................................................................................................. 7-68
One Multiplexed Channel with Static Frames ....................................... 7-69
One Multiplexed Channel with Dynamic Frames .................................. 7-69
Two Multiplexed Channels with Static Frames...................................... 7-70
Two Multiplexed Channels with Dynamic Frames................................. 7-71
Programming SI RAM Entries ............................................................... 7-72
SI RAM Programming Example ............................................................ 7-75
SI RAM Dynamic Changes.................................................................... 7-75
SI Registers........................................................................................... 7-77
SI Global Mode Register (SIGMR) ........................................................ 7-77
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7.8.5.2
7.8.5.3
7.8.5.4
7.8.5.5
7.8.5.6
7.8.5.6.1
7.8.5.6.2
7.8.5.6.3
7.8.5.6.4
7.8.6
7.8.6.1
7.8.6.2
7.8.7
7.8.7.1
7.8.7.2
7.8.7.2.1
7.8.7.2.2
7.8.8
7.8.9
7.9
7.9.1
7.9.2
7.9.3
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
7.10.6
7.10.7
7.10.7.1
7.10.7.2
7.10.7.3
7.10.7.4
7.10.7.5
7.10.7.6
7.10.8
7.10.8.1
7.10.8.2
7.10.8.3
7.10.9
7.10.10
7.10.11
7.10.11.1
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Title
Page
Number
SI Mode Register (SIMODE)..................................................................7-78
SI Clock Route Register (SICR).............................................................7-86
SI Command Register (SICMR).............................................................7-87
SI Status Register (SISTR) ....................................................................7-87
SI RAM Pointers (SIRP).........................................................................7-88
SIRP When RDM = 00 (One Static TDM) ..............................................7-89
SIRP When RDM = 01 (One Dynamic TDM) .........................................7-89
SIRP When RDM = 10 (Two Static TDMs) ............................................7-90
SIRP When RDM = 11 (Two Dynamic TDMs) .......................................7-90
SI IDL Interface Support .......................................................................7-90
IDL Interface Example ...........................................................................7-91
IDL Interface Programming....................................................................7-95
SI GCI Support......................................................................................7-96
SI GCI Activation/Deactivation Procedure .............................................7-98
SI GCI Programming..............................................................................7-98
Normal Mode GCI Programming ...........................................................7-98
SCIT Programming ................................................................................7-98
Serial Interface Synchronization ..........................................................7-100
NMSI Configuration..............................................................................7-100
Baud Rate Generators (BRGs) ............................................................7-103
Autobaud Support ...............................................................................7-105
BRG Configuration Register (BRGC)..................................................7-106
UART Baud Rate Examples ...............................................................7-108
Serial Communication Controllers (SCCs)...........................................7-109
SCC Overview .....................................................................................7-110
General SCC Mode Register (GSMR) ................................................7-111
SCC Protocol-Specific Mode Register (PSMR) ..................................7-120
SCC Data Synchronization Register (DSR)........................................7-121
SCC Transmit on Demand Register (TODR)......................................7-121
SCC Buffer Descriptors.......................................................................7-122
SCC Parameter RAM..........................................................................7-124
BD Table Pointer (RBASE, TBASE) ....................................................7-125
SCC Function Code Registers (RFCR, TFCR)....................................7-125
Maximum Receive Buffer Length Register (MRBLR) ..........................7-127
Receiver BD Pointer (RBPTR).............................................................7-127
Transmitter BD Pointer (TBPTR) .........................................................7-127
Other General Parameters...................................................................7-128
Interrupts from the SCCs ....................................................................7-128
SCC Event Register (SCCE) ...............................................................7-128
SCC Mask Register (SCCM) ...............................................................7-129
SCC Status Register (SCCS) ..............................................................7-129
SCC Initialization.................................................................................7-129
SCC Interrupt Handling........................................................................7-130
SCC Timing Control .............................................................................7-130
Synchronous Protocols ........................................................................7-130
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7.10.11.2
7.10.12
7.10.12.1
7.10.12.2
7.10.13
7.10.14
7.10.14.1
7.10.14.2
7.10.14.3
7.10.14.4
7.10.14.5
7.10.15
7.10.16
7.10.16.1
7.10.16.2
7.10.16.3
7.10.16.4
7.10.16.5
7.10.16.6
7.10.16.6.1
7.10.16.6.2
7.10.16.7
7.10.16.8
7.10.16.9
7.10.16.10
7.10.16.11
7.10.16.12
7.10.16.13
7.10.16.14
7.10.16.14.1
7.10.16.14.2
7.10.16.15
7.10.16.16
7.10.16.17
7.10.16.18
7.10.16.19
7.10.16.20
7.10.16.21
7.10.16.22
7.10.17
7.10.17.1
7.10.17.2
7.10.17.3
7.10.17.4
7.10.17.5
MOTOROLA
Title
Table of Contents
Page
Number
Asynchronous Protocols...................................................................... 7-134
Digital Phase-Locked Loop (DPLL) ..................................................... 7-135
Data Encoding..................................................................................... 7-135
DPLL Operation................................................................................... 7-136
Clock Glitch Detection ......................................................................... 7-139
Disabling the SCCs on the Fly ............................................................ 7-139
SCC Transmitter Full Sequence.......................................................... 7-140
SCC Transmitter Shortcut SEQUENCE .............................................. 7-140
SCC Receiver Full Sequence.............................................................. 7-140
SCC Receiver Shortcut Sequence ...................................................... 7-141
Switching Protocols ............................................................................. 7-141
Saving Power ...................................................................................... 7-141
UART Controller .................................................................................. 7-141
UART Key Features ............................................................................ 7-143
Normal Asynchronous Mode ............................................................... 7-143
Synchronous Mode ............................................................................. 7-144
UART Memory Map............................................................................. 7-145
UART Programming Model ................................................................. 7-147
UART Command Set........................................................................... 7-147
Transmit Commands ........................................................................... 7-147
Receive Commands ............................................................................ 7-148
UART Address Recognition (Receiver)............................................... 7-149
UART Control Characters (Receiver).................................................. 7-150
Wake-Up Timer (Receiver).................................................................. 7-151
Break Support (Receiver).................................................................... 7-151
Send Break (Transmitter) .................................................................... 7-153
Sending a Preamble (Transmitter) ...................................................... 7-153
Fractional Stop Bits (Transmitter)........................................................ 7-153
UART Error-Handling Procedure......................................................... 7-154
Transmission Error .............................................................................. 7-155
Reception Errors ................................................................................. 7-155
UART Mode Register (PSMR) ............................................................ 7-156
UART Receive Buffer Descriptor (Rx BD)........................................... 7-159
UART Transmit Buffer Descriptor (Tx BD). ......................................... 7-163
UART Event Register (SCCE)............................................................. 7-164
UART Mask Register (SCCM)............................................................. 7-167
SCC Status Register (SCCS).............................................................. 7-167
SCC UART Example ........................................................................... 7-167
S-Records Programming Example...................................................... 7-169
HDLC Controller .................................................................................. 7-169
HDLC Controller Key Features............................................................ 7-170
HDLC Channel Frame Transmission Processing................................ 7-171
HDLC Channel Frame Reception Processing..................................... 7-172
HDLC Memory Map............................................................................. 7-172
HDLC Programming Model ................................................................. 7-174
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7.10.17.6
7.10.17.6.1
7.10.17.6.2
7.10.17.7
7.10.17.7.1
7.10.17.7.2
7.10.17.8
7.10.17.9
7.10.17.10
7.10.17.11
7.10.17.12
7.10.17.13
7.10.17.14
7.10.17.15
7.10.18
7.10.18.1
7.10.18.2
7.10.18.2.1
7.10.18.2.2
7.10.18.2.3
7.10.18.2.4
7.10.18.3
7.10.18.3.1
7.10.18.3.2
7.10.18.3.3
7.10.19
7.10.19.1
7.10.19.2
7.10.19.3
7.10.19.4
7.10.19.4.1
7.10.19.4.2
7.10.19.4.3
7.10.19.4.4
7.10.20
7.10.20.1
7.10.20.2
7.10.20.3
7.10.20.4
7.10.20.5
7.10.20.5.1
7.10.20.5.2
7.10.20.6
7.10.20.7
7.10.20.8
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Title
Page
Number
HDLC Command Set ...........................................................................7-175
Transmit Commands............................................................................7-175
Receive Commands.............................................................................7-176
HDLC Error-handling Procedure..........................................................7-176
Transmission Errors.............................................................................7-176
Reception Errors ..................................................................................7-177
HDLC Mode Register (PSMR) .............................................................7-178
HDLC Receive Buffer Descriptor (Rx BD) ...........................................7-179
HDLC Transmit Buffer Descriptor (Tx BD)...........................................7-183
HDLC Event Register (SCCE) .............................................................7-184
HDLC Mask Register (SCCM) .............................................................7-186
SCC Status Register (SCCS) ..............................................................7-187
SCC HDLC Example #1.......................................................................7-187
SCC HDLC Example #2.......................................................................7-189
HDLC Bus Controller ...........................................................................7-189
HDLC Bus Key Features......................................................................7-192
HDLC Bus Operation ...........................................................................7-192
Accessing the HDLC Bus.....................................................................7-192
More Performance ...............................................................................7-193
Delayed RTS Mode..............................................................................7-194
Using the TSA......................................................................................7-195
HDLC Bus Memory Map and Programming ........................................7-196
GSMR Programming............................................................................7-196
PSMR Programming ............................................................................7-196
HDLC Bus Controller Example ............................................................7-196
AppleTalk Controller ............................................................................7-196
LocalTalk Bus Operation......................................................................7-197
Appletalk Controller Key Features .......................................................7-198
QUICC AppleTalk Hardware Connection.............................................7-198
AppleTalk Memory Map and Programming Model...............................7-198
GSMR Programming............................................................................7-199
PSMR Programming ............................................................................7-200
TODR Programming ............................................................................7-200
AppleTalk Controller Example .............................................................7-200
BISYNC Controller ...............................................................................7-200
BISYNC Controller Features................................................................7-201
BISYNC Channel Frame Transmission ...............................................7-201
BISYNC Channel Frame Reception.....................................................7-202
BISYNC Memory Map..........................................................................7-203
BISYNC Command Set........................................................................7-204
Transmit Commands............................................................................7-204
Receive Commands.............................................................................7-205
BISYNC Control Character Recognition ..............................................7-206
BSYNC-BISYNC SYNC Register.........................................................7-207
BDLE-BISYNC DLE Register...............................................................7-208
MC68360 USER’S MANUAL
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MOTOROLA
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Freescale Semiconductor, Inc...
Paragraph
Number
7.10.20.9
7.10.20.10
7.10.20.10.1
7.10.20.10.2
7.10.20.11
7.10.20.12
7.10.20.13
7.10.20.14
7.10.20.15
7.10.20.16
7.10.20.17
7.10.20.18
7.10.21
7.10.21.1
7.10.21.2
7.10.21.3
7.10.21.4
7.10.21.4.1
7.10.21.4.2
7.10.21.5
7.10.21.6
7.10.21.6.1
7.10.21.6.2
7.10.21.7
7.10.21.7.1
7.10.21.7.2
7.10.21.8
7.10.21.9
7.10.21.10
7.10.21.11
7.10.21.12
7.10.21.13
7.10.21.14
7.10.22
7.10.23
7.10.23.1
7.10.23.2
7.10.23.3
7.10.23.4
7.10.23.5
7.10.23.6
7.10.23.7
7.10.23.8
7.10.23.9
7.10.23.10
MOTOROLA
Title
Table of Contents
Page
Number
Transmitting and Receiving the Synchronization Sequence ............... 7-208
BISYNC Error-Handling PROCEDURE............................................... 7-209
Transmission Errors ............................................................................ 7-209
Reception Errors ................................................................................. 7-209
BISYNC Mode Register (PSMR)......................................................... 7-209
BISYNC Receive Buffer Descriptor (Rx BD) ....................................... 7-211
BISYNC Transmit Buffer Descriptor (Tx BD)....................................... 7-213
BISYNC Event Register (SCCE) ......................................................... 7-216
BISYNC Mask Register (SCCM) ......................................................... 7-217
SCC Status Register (SCCS).............................................................. 7-217
Programming the BISYNC Controller.................................................. 7-217
SCC BISYNC Example ....................................................................... 7-218
Transparent Controller ........................................................................ 7-220
Transparent Controller Features ......................................................... 7-221
Transparent Channel Frame Transmission Processing ...................... 7-221
Transparent Channel Frame Reception Processing ........................... 7-222
Achieving Synchronization in Transparent Mode ................................ 7-223
In-Line Synchronization Pattern .......................................................... 7-223
Transparent Synchronization Example ............................................... 7-224
Transparent Memory Map ................................................................... 7-225
Transparent Command Set ................................................................. 7-226
Transmit Commands ........................................................................... 7-226
Receive Commands ............................................................................ 7-227
Transparent Error-Handling Procedure ............................................... 7-227
Transmission Errors ............................................................................ 7-227
Reception Errors ................................................................................. 7-228
Transparent Mode Register (PSMR)................................................... 7-228
Transparent Receive Buffer Descriptor (Rx BD) ................................. 7-228
Transparent Transmit Buffer Descriptor (Tx BD)................................. 7-230
Transparent Event Register (SCCE) ................................................... 7-232
Transparent Mask Register (SCCM) ................................................... 7-233
SCC Status Register (SCCS).............................................................. 7-233
SCC Transparent Example ................................................................. 7-233
RAM Microcodes ................................................................................. 7-235
Ethernet Controller .............................................................................. 7-235
Ethernet On QUICC—MC68EN360 .................................................... 7-236
Ethernet Key Features ........................................................................ 7-237
Learning Ethernet on the QUICC ........................................................ 7-238
Connecting QUICC to Ethernet ........................................................... 7-239
Ethernet Channel Frame Transmission............................................... 7-241
Ethernet Channel Frame Reception.................................................... 7-242
CAM Interface ..................................................................................... 7-243
Ethernet Memory Map......................................................................... 7-246
Ethernet Programming Model ............................................................. 7-250
Ethernet Command Set....................................................................... 7-250
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xv
Table of Contents
Freescale Semiconductor, Inc...
Paragraph
Number
7.10.23.10.1
7.10.23.10.2
7.10.23.10.3
7.10.23.11
7.10.23.12
7.10.23.13
7.10.23.14
7.10.23.15
7.10.23.16
7.10.23.16.1
7.10.23.16.2
7.10.23.17
7.10.23.18
7.10.23.19
7.10.23.20
7.10.23.21
7.10.23.22
7.10.23.23
7.11
7.11.1
7.11.2
7.11.3
7.11.4
7.11.4.1
7.11.4.2
7.11.4.3
7.11.4.4
7.11.4.5
7.11.4.6
7.11.5
7.11.5.1
7.11.5.2
7.11.5.3
7.11.5.4
7.11.5.5
7.11.6
7.11.7
7.11.7.1
7.11.7.2
7.11.7.3
7.11.7.4
7.11.7.5
7.11.7.6
7.11.7.7
7.11.7.7.1
xvi
Freescale Semiconductor, Inc.
Title
Page
Number
Transmit Commands............................................................................7-250
Receive Commands.............................................................................7-251
SET GROUP ADDRESS Command....................................................7-251
Ethernet Address Recognition .............................................................7-252
Hash Table Algorithm ..........................................................................7-253
Interpacket Gap Time ..........................................................................7-254
Collision Handling ................................................................................7-254
Internal and External Loopback ...........................................................7-255
Ethernet Error-handling Procedure ......................................................7-255
Transmission Errors.............................................................................7-255
Reception Errors ..................................................................................7-256
Ethernet Mode Register (PSMR) .........................................................7-256
Ethernet Receive Buffer Descriptor (Rx BD)........................................7-258
Ethernet Transmit Buffer Descriptor (Tx BD) .......................................7-261
Ethernet Event Register (SCCE) .........................................................7-264
Ethernet Mask Register (SCCM) .........................................................7-265
Ethernet Status Register (SCCS) ........................................................7-265
SCC Ethernet Example........................................................................7-266
Serial Management Controllers (SMCs) ..............................................7-268
SMC Overview .....................................................................................7-268
General SMC Mode Register (SMCMR)..............................................7-270
SMC Buffer Descriptors .......................................................................7-270
SMC Parameter RAM ..........................................................................7-270
BD Table Pointer (RBASE, TBASE) ....................................................7-271
SMC Function Code Registers (RFCR, TFCR) ...................................7-272
Maximum Receive Buffer Length Register (MRBLR) ..........................7-273
Receiver Buffer Descriptor Pointer (RBPTR).......................................7-273
Transmitter Buffer Descriptor Pointer (TBPTR) ...................................7-274
Other General Parameters...................................................................7-274
Disabling the SMCs on the Fly.............................................................7-274
SMC Transmitter Full Sequence..........................................................7-275
SMC Transmitter Shortcut Sequence ..................................................7-275
SMC Receiver Full Sequence..............................................................7-275
SMC Receiver Shortcut Sequence ......................................................7-276
Switching Protocols..............................................................................7-276
Saving Power.......................................................................................7-276
SMC as a UART ..................................................................................7-276
SMC UART Key Features....................................................................7-276
SMC UART Comparison......................................................................7-276
SMC UART Memory Map ....................................................................7-277
SMC UART Transmission Processing .................................................7-278
SMC UART Reception Processing ......................................................7-279
SMC UART Programming Model.........................................................7-279
SMC UART Command Set ..................................................................7-279
Transmit Commands............................................................................7-279
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Freescale Semiconductor, Inc...
Paragraph
Number
7.11.7.7.2
7.11.7.8
7.11.7.9
7.11.7.10
7.11.7.10.1
7.11.7.10.2
7.11.7.10.3
7.11.7.10.4
7.11.7.10.5
7.11.7.11
7.11.7.12
7.11.7.13
7.11.7.14
7.11.7.15
7.11.8
7.11.9
7.11.10
7.11.10.1
7.11.10.2
7.11.10.3
7.11.10.4
7.11.10.5
7.11.10.6
7.11.10.7
7.11.10.8
7.11.10.8.1
7.11.10.8.2
7.11.10.9
7.11.10.9.1
7.11.10.9.2
7.11.10.10
7.11.10.11
7.11.10.12
7.11.10.13
7.11.10.14
7.11.11
7.11.12
7.11.13
7.11.14
7.11.14.1
7.11.14.1.1
7.11.14.1.2
7.11.14.2
7.11.14.2.1
7.11.14.2.2
MOTOROLA
Title
Table of Contents
Page
Number
Receive Commands ............................................................................ 7-280
Send Break (Transmitter) .................................................................... 7-280
Sending a Preamble (Transmitter) ...................................................... 7-280
SMC UART Error-Handling Procedure................................................ 7-281
Overrun Error ...................................................................................... 7-281
Parity Error .......................................................................................... 7-281
Idle Sequence Receive ....................................................................... 7-281
Framing Error ...................................................................................... 7-281
Break Sequence.................................................................................. 7-281
SMC UART Mode Register (SMCMR) ................................................ 7-281
SMC UART Receive Buffer Descriptor (Rx BD).................................. 7-283
SMC UART Transmit Buffer Descriptor (Tx BD) ................................. 7-286
SMC UART Event Register (SMCE) ................................................... 7-288
SMC UART Mask Register (SMCM) ................................................... 7-290
SMC UART Example........................................................................... 7-290
SMC Interrupt Handling....................................................................... 7-291
SMC as a Transparent Controller........................................................ 7-291
SMC Transparent Controller KEY Features ........................................ 7-291
SMC Transparent Comparison............................................................ 7-292
SMC Transparent Memory Map .......................................................... 7-292
SMC Transparent Transmission Processing....................................... 7-292
SMC Transparent Reception Processing ............................................ 7-293
Using the SMSYNx Pin for Synchronization........................................ 7-293
Using the TSA for Synchronization ..................................................... 7-295
SMC Transparent Command Set ........................................................ 7-297
Transmit Commands ........................................................................... 7-297
Receive Commands ............................................................................ 7-297
SMC Transparent Error-Handling Procedure ...................................... 7-298
Transmission Error (Underrun)............................................................ 7-298
Reception Error (Overrun)................................................................... 7-298
SMC Transparent Mode Register (SMCMR)....................................... 7-298
SMC Transparent Receive Buffer Descriptor (Rx BD) ........................ 7-299
SMC Transparent Transmit Buffer Descriptor (Tx BD)........................ 7-300
SMC Transparent Event Register (SMCE).......................................... 7-302
SMC Transparent Mask Register (SMCM).......................................... 7-303
SMC Transparent NMSI Example ....................................................... 7-303
SMC Transparent TSA Example ......................................................... 7-304
SMC Interrupt Handling....................................................................... 7-305
SMC as a GCI Controller..................................................................... 7-305
SMC GCI Memory Map ....................................................................... 7-306
SMC Monitor Channel Transmission................................................... 7-306
SMC Monitor Channel Reception........................................................ 7-307
SMC C/I Channel Handling ................................................................. 7-307
SMC C/I Channel Transmission .......................................................... 7-307
SMC C/I Channel Reception ............................................................... 7-307
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xvii
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Paragraph
Number
7.11.14.3
7.11.14.4
7.11.14.5
7.11.14.6
7.11.14.7
7.11.14.8
7.11.14.9
7.11.14.10
7.12
7.12.1
7.12.2
7.12.3
7.12.4
7.12.4.1
7.12.4.2
7.12.4.3
7.12.5
7.12.5.1
7.12.5.2
7.12.5.3
7.12.5.3.1
7.12.5.3.2
7.12.5.3.3
7.12.5.3.4
7.12.5.3.5
7.12.5.3.6
7.12.5.4
7.12.5.4.1
7.12.5.4.2
7.12.5.4.3
7.12.5.5
7.12.5.5.1
7.12.5.5.2
7.12.5.6
7.12.5.7
7.12.6
7.12.7
7.12.8
7.13
7.13.1
7.13.2
7.13.3
7.13.4
7.13.5
7.13.5.1
xviii
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Title
Page
Number
SMC Commands in GCI Mode ............................................................7-307
SMC GCI Mode Register (SMCMR) ....................................................7-308
SMC Monitor Channel Rx BD ..............................................................7-309
SMC Monitor Channel Tx BD...............................................................7-310
SMC C/I Channel Receive Buffer Descriptor (Rx BD) .........................7-310
SMC C/I Channel Transmit Buffer Descriptor (Tx BD).........................7-311
SMC Event Register (SMCE)...............................................................7-311
SMC Mask Register (SMCM)...............................................................7-312
Serial Peripheral Interface (SPI) ..........................................................7-312
Overview ..............................................................................................7-312
SPI Key Features.................................................................................7-313
SPI Clocking and Pin Functions...........................................................7-314
SPI Transmit/Receive Process ............................................................7-315
SPI Master Mode .................................................................................7-315
SPI Slave Mode ...................................................................................7-316
SPI Multi-Master Operation..................................................................7-316
SPI Programming Model......................................................................7-317
SPI Mode Register (SPMODE)............................................................7-317
SPI Command Register (SPCOM).......................................................7-319
SPI Parameter RAM Memory Map ......................................................7-320
BD Table Pointer (RBASE, TBASE) ....................................................7-320
SPI Function Code Registers (RFCR, TFCR)......................................7-321
Maximum Receive Buffer Length Register (MRBLR) ..........................7-322
Receiver Buffer Descriptor Pointer (RBPTR).......................................7-322
Transmitter Buffer Descriptor Pointer (TBPTR) ...................................7-323
Other General Parameters...................................................................7-323
SPI Commands....................................................................................7-323
INIT TX PARAMETERS Command .....................................................7-323
CLOSE Rx BD Command....................................................................7-323
INIT RX PARAMETERS Command.....................................................7-323
SPI Buffer Descriptor Ring...................................................................7-324
SPI Receive Buffer Descriptor (Rx BD) ...............................................7-324
SPI Transmit Buffer Descriptor (Tx BD)...............................................7-326
SPI Event Register (SPIE) ...................................................................7-328
SPI Mask Register (SPIM) ...................................................................7-329
SPI Master Example ............................................................................7-329
SPI Slave Example ..............................................................................7-330
SPI Interrupt Handling..........................................................................7-331
Parallel Interface Port (PIP) .................................................................7-331
PIP Key Features.................................................................................7-331
PIP Overview .......................................................................................7-332
General-Purpose I/O Pins (Port B) ......................................................7-333
Interlocked Data Transfers...................................................................7-333
Pulsed Data Transfers .........................................................................7-334
Busy Signal ..........................................................................................7-335
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7.13.5.2
7.13.6
7.13.7
7.13.7.1
7.13.7.2
7.13.7.3
7.13.7.4
7.13.7.5
7.13.7.6
7.13.8
7.13.8.1
7.13.8.2
7.13.8.3
7.13.8.4
7.13.8.5
7.13.8.6
7.13.8.7
7.13.8.8
7.13.8.9
7.13.8.9.1
7.13.8.9.2
7.13.8.9.3
7.13.8.10
7.13.8.10.1
7.13.8.10.2
7.13.8.10.3
7.13.8.10.4
7.13.8.10.5
7.13.8.11
7.13.8.12
7.13.8.13
7.13.8.14
7.13.8.15
7.13.8.16
7.13.8.17
7.13.8.18
7.13.8.19
7.13.8.20
7.13.8.20.1
7.13.8.20.2
7.13.8.21
7.13.8.21.1
7.13.8.22
7.13.8.23
7.13.9
MOTOROLA
Title
Table of Contents
Page
Number
Pulsed Handshake Timing .................................................................. 7-336
Transparent Data Transfers ................................................................ 7-338
Programming Model ............................................................................ 7-338
Parameter RAM................................................................................... 7-338
PIP Configuration Register (PIPC) ...................................................... 7-339
PIP Timing Parameters Register (PTPR)............................................ 7-341
PIP Buffer Descriptors......................................................................... 7-341
PIP Event Register (PIPE) .................................................................. 7-341
PIP Mask Register (PIPM) .................................................................. 7-342
Centronics Controller Overview........................................................... 7-342
Centronics Controller Key Features .................................................... 7-344
Centronics Channel Transmission ...................................................... 7-345
Centronics Transmitter Memory Map .................................................. 7-345
Buffer Descriptor Table Pointer (TBASE)............................................ 7-346
Status Mask Register (SMASK) .......................................................... 7-346
Centronics Function Code Register (CFCR) ....................................... 7-346
Transmitter Buffer Descriptor Pointer (TBPTR)................................... 7-347
Centronics Transmitter Programming Model....................................... 7-347
Centronics Transmitter Command Set ................................................ 7-347
STOP TRANSMIT Command.............................................................. 7-347
RESTART TRANSMIT Command....................................................... 7-347
INIT TX PARAMETERS Command..................................................... 7-348
Transmission Errors ............................................................................ 7-348
Buffer Descriptor Not Ready ............................................................... 7-348
Printer Off-Line Error ........................................................................... 7-348
Printer Fault......................................................................................... 7-348
Paper Error.......................................................................................... 7-348
Centronics Transmitter Buffer Descriptor ............................................ 7-348
Centronics Transmitter Event Register (PIPE).................................... 7-349
Centronics Channel Reception............................................................ 7-350
Centronics Receiver Memory Map ...................................................... 7-350
Buffer Descriptor Table Pointer (RBASE) ........................................... 7-351
Centronics Function Code Register (CFCR) ....................................... 7-351
Receiver Buffer Descriptor Pointer (RBPTR) ...................................... 7-352
Centronics Receiver Programming Model........................................... 7-352
Centronics Control Characters ............................................................ 7-352
Centronics Silence Period ................................................................... 7-354
Centronics Receiver Command Set .................................................... 7-354
INIT RX PARAMETERS Command .................................................... 7-354
CLOSE RX BD Command................................................................... 7-354
Receiver Errors ................................................................................... 7-354
Buffer Descriptor Busy ........................................................................ 7-354
Centronics Receive Buffer Descriptor ................................................. 7-354
Centronics Receiver Event Register (PIPE)........................................ 7-355
Port B Registers .................................................................................. 7-356
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Paragraph
Number
7.13.9.1
7.13.9.2
7.13.9.3
7.13.9.4
7.14
7.14.1
7.14.2
7.14.3
7.14.4
7.14.4.1
7.14.4.2
7.14.4.3
7.14.4.4
7.14.5
7.14.6
7.14.7
7.14.7.1
7.14.7.2
7.14.7.3
7.14.7.4
7.14.8
7.14.9
7.14.10
7.14.10.1
7.14.10.2
7.14.10.3
7.14.10.4
7.14.10.5
7.15
7.15.1
7.15.2
7.15.2.1
7.15.2.2
7.15.2.3
7.15.3
7.15.4
7.15.5
7.15.5.1
7.15.5.2
7.15.5.3
7.15.5.4
7.15.6
7.15.6.1
7.15.6.2
xx
Freescale Semiconductor, Inc.
Title
Page
Number
Port B Assignment Registers (PBPAR) ...............................................7-356
Data Direction Register (PBDIR) .........................................................7-356
Data Register (PBDAT)........................................................................7-356
Open-Drain Register (PBODR)............................................................7-356
Parallel I/O Ports..................................................................................7-356
Parallel I/O Key Features.....................................................................7-357
Parallel I/O Overview ...........................................................................7-357
Port A Pin Functions ............................................................................7-357
Port A Registers...................................................................................7-359
Port A Open-Drain Register (PAODR).................................................7-359
Port A Data Register (PADAT).............................................................7-359
Port A Data Direction Register (PADIR) ..............................................7-359
Port A Pin Assignment Register (PAPAR) ...........................................7-359
Port A Examples ..................................................................................7-360
Port B Pin Functions ............................................................................7-362
Port B Registers...................................................................................7-363
Port B Open-Drain Register (PBODR).................................................7-363
Port B Data Register (PBDAT).............................................................7-364
Port B Data Direction Register (PBDIR) ..............................................7-364
Port B Pin Assignment Register (PBPAR) ...........................................7-364
Port B Example ....................................................................................7-365
Port C Pin Functions ............................................................................7-365
Port C Registers...................................................................................7-367
Port C Data Register (PCDAT) ............................................................7-368
Port C Data Direction Register (PCDIR) ..............................................7-368
Port C Pin Assignment Register (PCPAR)...........................................7-368
Port C Special Options (PCSO) ...........................................................7-368
Port C Interrupt Control Register (PCINT) ...........................................7-369
CPM Interrupt Controller (CPIC) ..........................................................7-369
Overview ..............................................................................................7-370
CPM Interrupt Source Priorities ...........................................................7-372
SCC Relative Priority ...........................................................................7-372
Highest Priority Interrupt ......................................................................7-372
Nested Interrupts .................................................................................7-373
Masking Interrupt Sources in the CPM ................................................7-374
Interrupt Vector Generation and Calculation........................................7-375
CPIC Programming Model ...................................................................7-377
CPM Interrupt Configuration Register (CICR)......................................7-377
CPM Interupt Pending Register (CIPR) ...............................................7-379
CPM Interrupt Mask Register (CIMR) ..................................................7-380
CPM Interrupt In-Service Register (CISR) ...........................................7-380
Interrupt Handler Examples .................................................................7-381
Example 1—PC6 Interrupt Handler .....................................................7-381
Example 2—SCC1 Interrupt Handler...................................................7-381
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Freescale Semiconductor, Inc...
Paragraph
Number
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.6
9.1
9.1.1
9.1.1.1
9.1.1.2
9.1.1.3
9.1.1.4
9.1.1.5
9.1.1.6
9.1.1.7
9.1.1.8
9.1.1.9
9.1.1.10
9.1.1.11
9.1.1.12
9.1.2
9.1.2.1
9.1.2.2
9.1.2.3
9.1.2.4
9.1.2.5
9.1.2.6
9.1.2.7
9.1.3
9.1.3.1
9.1.3.2
9.1.3.3
9.2
MOTOROLA
Title
Table of Contents
Page
Number
Section 8
Scan Chain Test Access Port
Overview ................................................................................................. 8-1
TAP Controller......................................................................................... 8-2
Boundary Scan Register ......................................................................... 8-3
Instruction Register ............................................................................... 8-10
EXTEST ................................................................................................ 8-10
SAMPLE/PRELOAD.............................................................................. 8-10
BYPASS ................................................................................................ 8-11
CLAMP .................................................................................................. 8-11
HI-Z ....................................................................................................... 8-11
QUICC Restrictions ............................................................................... 8-11
Non-Scan Chain Operation ................................................................... 8-12
Section 9
Applications
Minimum System Configuration .............................................................. 9-1
QUICC Hardware Configuration.............................................................. 9-1
QUICC Basic Accesses........................................................................... 9-1
Clocking Strategy. ................................................................................... 9-3
Resetting the QUICC............................................................................... 9-3
Interrupts. ................................................................................................ 9-3
Bus Arbitration......................................................................................... 9-3
Breakpoint Generation. ........................................................................... 9-3
Bus Monitor Function. ............................................................................. 9-3
Spurious Interrupt Monitor....................................................................... 9-3
Software Watchdog. ................................................................................ 9-3
Double Bus Fault..................................................................................... 9-4
JTAG and Three-State. ........................................................................... 9-4
QUICC Serial Ports. ................................................................................ 9-4
Memory Interfaces................................................................................... 9-4
QUICC Memory Interface Pins................................................................ 9-4
Regular EPROM...................................................................................... 9-5
Flash EPROM. ........................................................................................ 9-5
SRAM ...................................................................................................... 9-6
EEPROM................................................................................................. 9-7
DRAM SIMM. .......................................................................................... 9-8
DRAM Devices. ....................................................................................... 9-9
Software Configuration.......................................................................... 9-10
Basic Initialization.................................................................................. 9-10
Configuring the Memory Controller. ...................................................... 9-11
Using the QUICC in 16-Bit Data Bus Mode........................................... 9-12
How to take A QUICC Software Test-Drive........................................... 9-13
Step 1: Decide on Reset Stack Pointer and Initial Program Counter .... 9-13
Step 2: Stay in Supervisor Mode........................................................... 9-13
Step 3: Write the VBR ........................................................................... 9-14
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Paragraph
Number
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.4.1
9.3.4.1.1
9.3.4.1.2
9.3.4.2
9.3.4.2.1
9.3.4.2.2
9.3.4.2.3
9.3.4.3
9.3.4.4
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.1.4
9.4.2
9.4.2.1
9.4.2.2
9.4.2.3
9.4.2.4
9.4.2.5
9.4.2.6
xxii
Freescale Semiconductor, Inc.
Title
Page
Number
Step 4: Write the MBAR.........................................................................9-14
Step 5: Verify a Dual-Port RAM Location...............................................9-14
Step 6: Is This a Power-Up Reset?........................................................9-14
Step 7: Deal with the Clock Synthesizer ................................................9-14
Step 8: Initialize System Protection .......................................................9-15
Step 9: Clear Entire Dual-Port RAM ......................................................9-15
Step 10: Write the PEPAR .....................................................................9-15
Step 11: Remap Chip Select 0...............................................................9-15
Step 12: Initialize the System RAM........................................................9-15
Step 13: Copy the EVT to System RAM ................................................9-16
Step 14: Initialize All Other Memory and Peripherals ............................9-16
Step 15: Initialize the Rest of the SIM60................................................9-16
Step 16: Generate a SIM60 Interrupt.....................................................9-16
Step 17: Test the CPM...........................................................................9-17
Step 18: Generate Interrupts with the CPM ...........................................9-17
Step 19: Enable External Interrupts .......................................................9-17
Step 20: Enable External Bus Masters ..................................................9-18
Step 21: Off to the Races.......................................................................9-18
Porting MC68302 IMP Code to the MC68360 QUICC...........................9-18
CPU and Compilers ...............................................................................9-18
Differences/Similarities ..........................................................................9-18
Notes About Porting...............................................................................9-19
How To Port MC68302 Functions..........................................................9-19
System Configuration Registers. ...........................................................9-19
Base Address Register (BAR). ..............................................................9-19
System Control Register (SCR). ............................................................9-20
System RAM. .........................................................................................9-21
Buffer Descriptors. .................................................................................9-21
Protocol-Independent Parameter RAM Values......................................9-21
Protocol-Dependent Parameter RAM Values. .......................................9-22
Internal Registers (System Integration Block)........................................9-23
Internal Registers (Communication Processor). ....................................9-26
Using the QUICC MC68040 Companion Mode .....................................9-31
MC68EC040 to QUICC Interface...........................................................9-32
MC68EC040 Reads And Writes to QUICC............................................9-32
Clocking Strategy...................................................................................9-34
Reset Strategy. ......................................................................................9-34
Interrupts................................................................................................9-34
Memory Interfaces .................................................................................9-37
QUICC Memory Interface Pins. .............................................................9-37
Regular EPROM. ...................................................................................9-38
Burst EPROM. .......................................................................................9-38
Flash EPROM. .......................................................................................9-41
Regular SRAM. ......................................................................................9-41
Burst SRAM. ..........................................................................................9-41
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Paragraph
Number
9.4.2.7
9.4.2.8
9.4.2.9
9.4.3
9.4.3.1
9.4.3.2
9.4.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
9.6.5.1
9.6.5.2
9.6.5.3
9.6.5.4
9.6.5.5
9.6.5.6
9.6.6
9.6.7
9.6.7.1
9.6.7.2
9.7
9.7.1
9.7.2
9.7.3
9.7.4
9.8
9.8.1
9.8.1.1
9.8.1.2
9.8.1.3
9.8.1.4
9.8.1.5
9.8.1.6
9.8.1.7
9.8.1.8
9.8.1.9
9.8.1.10
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Title
Table of Contents
Page
Number
EEPROM............................................................................................... 9-45
DRAM SIMM ......................................................................................... 9-45
DRAM Devices. ..................................................................................... 9-46
Software Configuration.......................................................................... 9-48
Basic Initialization.................................................................................. 9-49
Configuring the Memory Controller. ...................................................... 9-49
Interfacing Multiple QUICCs to an MC68EC040 ................................... 9-51
Selecting Cache Modes on the MC68EC040........................................ 9-51
The Algorithm ........................................................................................ 9-52
Protection .............................................................................................. 9-52
MC68EC040 Cache Behavior ............................................................... 9-53
Enabling the Caching Modes ................................................................ 9-53
Interfacing the QUICC to the 53C90 scsi controller .............................. 9-54
SCSI General Overview ........................................................................ 9-54
Physical Interface .................................................................................. 9-54
Logical Interface .................................................................................... 9-59
Functional Description........................................................................... 9-61
Hardware Configuration ........................................................................ 9-62
Clocking Strategy. ................................................................................. 9-62
Reset Strategy....................................................................................... 9-62
Read/Write timing.................................................................................. 9-62
Interrupt Handling.................................................................................. 9-62
IDMA1 Setup and Timing. ..................................................................... 9-64
QUICC I/O Ports.................................................................................... 9-65
Active SCSI Terminations ..................................................................... 9-65
Software Configuration.......................................................................... 9-65
Configuring IDMA1. ............................................................................... 9-65
Configuring The Memory Controller. ..................................................... 9-66
Using the QUICC as a TAP Controller for Board Self-Test ................... 9-66
Board Layout ......................................................................................... 9-67
Board Testing ........................................................................................ 9-68
Microcontroller Interface........................................................................ 9-70
Test Pattern Generation ........................................................................ 9-72
Interfacing an MC68EC030 Master to the QUICC In Slave Mode ........ 9-74
MC68EC030 to QUICC Interface .......................................................... 9-74
MC68EC030 Reads and Writes to QUICC............................................ 9-75
Clocking Strategy. ................................................................................. 9-75
Reset Strategy....................................................................................... 9-77
Interrupts ............................................................................................... 9-77
Bus Arbitration....................................................................................... 9-78
Breakpoint Generation .......................................................................... 9-78
Bus Monitor Function ............................................................................ 9-78
Spurious Interrupt Monitor..................................................................... 9-78
Software Watchdog ............................................................................... 9-79
Periodic Interval Timer .......................................................................... 9-79
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Paragraph
Number
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Title
Page
Number
9.8.1.11
9.8.1.12
9.8.1.13
9.8.1.14
9.8.2
9.8.2.1
9.8.2.2
9.8.2.3
9.8.2.4
9.8.2.5
9.8.2.6
9.8.3
9.8.3.1
9.8.3.2
9.8.4
9.8.5
9.9
MC68EC030 Caching Configuration......................................................9-79
Double Bus Fault ...................................................................................9-79
JTAG and Three-State...........................................................................9-79
QUICC Serial Ports................................................................................9-79
Memory Interfaces .................................................................................9-79
QUICC Memory Interface Pins ..............................................................9-80
Regular EPROM or Flash EPROM ........................................................9-80
Regular SRAM .......................................................................................9-82
EEPROM ...............................................................................................9-84
DRAM SIMM ..........................................................................................9-84
DRAM Devices.......................................................................................9-86
Software Configuration ..........................................................................9-86
Basic Initialization ..................................................................................9-86
Configuring the Memory Controller ........................................................9-87
Interfacing Multiple QUICCs to an MC68EC030....................................9-89
Using a Higher Speed MC68EC030 Master with the QUICC ................9-89
Putting a Background Debug Mode Connector on a Target Board .......9-90
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.9
10.9
10.9
10.10
10.11
tions
10.12
Section 10
Electrical Characteristics
Maximum Ratings ..................................................................................10-1
Thermal Characteristics .........................................................................10-2
Power Considerations............................................................................10-2
AC Electrical Specification Definitions ...................................................10-3
DC Electrical Specifications ...................................................................10-5
AC Power Dissipation ............................................................................10-6
AC Electrical Specifications Control Timing...........................................10-7
External Capacitor for PLL.....................................................................10-8
Bus Operation AC Timing Specifications ...............................................10-9
Bus Operation AC Timing Specifications (Continued) .........................10-10
Bus Operation AC Timing Specifications (Continued) ........................10-11
Bus Operation AC Timing Specifications (Continued ..........................10-12
Bus Operation—DRAM Accesses AC Timing Specifications .............10-28
030/QUICC Bus Type Slave Mode Bus Arbitration AC Electrical Specifica10-33
030/QUICC Bus Type Slave Mode Internal Read/Write/IACK
Asynchronous Cycles AC Electrical Specifications..............................10-36
030/QUICC Bus Type SRAM/DRAM Cycles AC Electrical Specifications10-
10.14
44
10.15
040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications10-49
10.16
040 Bus Type Slave Mode Internal Read/write/IACK Cycles AC Electrical
Specifications10-51
10.17
040 Bus Type SRAM/DRAM Cycles Ac Electrical Specifications .......10-56
10.18
IDMA AC Electrical Specifications ......................................................10-62
10.19
PIP/PIO AC Electrical Specifications ...................................................10-64
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Paragraph
Number
Title
Table of Contents
Page
Number
10.20
10.21
10.22
10.23
10.24
10.25
10.26
10.27
10.28
10.29
10.30
Interrupt Controller AC Electrical Specifications.................................. 10-66
Baud Rate Generator AC Electrical Specifications ............................. 10-67
Timer Electrical Specifications ............................................................ 10-68
SI Electrical Specifications .................................................................. 10-69
SCC in NMSI Mode—External Clock Electrical Specifications .......... 10-75
SCC in NMSI MODE—Internal Clock Electrical Specifications.......... 10-75
Ethernet Electrical Specifications ....................................................... 10-77
SMC Transparent Mode Electrical Specifications .............................. 10-80
SPI Master Electrical Specifications................................................... 10-82
SPI Slave Electrical Specifications..................................................... 10-83
JTAG Electrical Specifications ............................................................ 10-85
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Section 11
Ordering Information and Mechanical Data
Standard Ordering Information.............................................................. 11-1
Pin Assignment—240-Lead Quad Flat Pack (QFP) .............................. 11-2
Pin Assignment—241-Lead Pin Grid Array (PGA) ................................ 11-4
Pin Assignment—357-Lead BALL Grid Array (BGA) ............................ 11-5
Package Dimensions—CQFP (FE Suffix) ............................................. 11-6
Package Dimensions—PGA (RC Suffix)............................................... 11-7
Package Dimensions—BGA (ZP Suffix) ............................................... 11-8
Appendix A
Serial Performance
B.1
B.2
B.3
B.4
B.5
B.6
Appendix B
Development Tools and Support
Motorola Software Modules.................................................................... B-1
Other protocol Software Support............................................................ B-5
Third-Party Software Support................................................................. B-6
M68360QUADS Development System ................................................... B-6
Other Development Boards..................................................................B-10
Direct Target Development ..................................................................B-10
C.1
C.1.1
C.2
C.2.1
C.2.2
C.2.3
C.3
C.3.1
C.3.2
Appendix C
RISC Microcode from RAM
Signaling System #7 Controller ..............................................................C-1
Performance............................................................................................C-2
Multiple GCI Controller ............................................................................C-3
Typical Application ..................................................................................C-3
MGCI Controller Key Features ................................................................C-3
Performance............................................................................................C-4
ATOM1/ATM Controller...........................................................................C-4
Key Features ...........................................................................................C-4
Performance............................................................................................C-5
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Paragraph
Number
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Title
Page
Number
C.4
C.4.1
C.4.2
C.5
C.5.1
C.6
C.6.1
C.6.2
Asynchronous HDLC for PPP ................................................................. C-6
Key Features........................................................................................... C-6
Performance ........................................................................................... C-7
PROFIBUS Controller ............................................................................. C-7
Key Features........................................................................................... C-7
Enhanced Ethernet Filtering ................................................................... C-8
Key Features........................................................................................... C-8
Performance ........................................................................................... C-8
D.1
D.1.1
D.1.2
D.1.3
D.2
D.2.1
D.2.2
D.2.3
4.2.3.1
D.2.4
D.2.5
D.2.6
D.2.7
D.2.8
D.2.9
Appendix D
MC68MH360 Product Brief
QUICC32 Key Features .......................................................................... D-1
General ................................................................................................... D-1
Serial Interface........................................................................................ D-2
System Interface ..................................................................................... D-2
QUICC Architecture Overview ................................................................ D-2
CPU32+ Core.......................................................................................... D-3
System Integration Module (SIM60) ....................................................... D-4
Communications Processor Module (CPM)............................................ D-4
QUICC32 Serial Configurations .............................................................. D-5
The QMC Microcode............................................................................... D-7
Data Flow................................................................................................ D-8
Data Management .................................................................................. D-8
Performance ........................................................................................... D-9
Development Support ........................................................................... D-10
Ordering Information ............................................................................. D-10
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SECTION 1
INTRODUCTION
The MC68360 QUad Integrated Communication Controller (QUICC ) is a versatile onechip integrated microprocessor and peripheral combination that can be used in a variety of
controller applications. It particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a next-generation MC68302 with higher performance
in all areas of device operation, increased flexibility, major extensions in capability, and
higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device; however, there are actually seven serial channels:
four SCCs, two serial management controllers (SMCs), and one serial peripheral interface
(SPI).
The purpose of this document is to describe the operation of all QUICC functionality.
Although this document has an overview of the CPU32+, the M68000PM/AD M68000 Family Programmer's Reference Manual should be used in addition to this document. The
CPU32RM/AD, M68300 Family CPU32 Reference Manual, also provides information on the
CPU32.
1.1 QUICC KEY FEATURES
The following list summarizes the key MC68360 QUICC features:
• CPU32+ Processor (4.5 MIPS at 25 MHz)
—32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
—Background Debug Mode
—Byte-Misaligned Addressing
• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
• Up to 32 Address Lines (At Least 28 Always Available)
• Complete Static Design (0–25-MHz Operation)
• Slave Mode To Disable CPU32+ (Allows Use with External Processors)
—Multiple QUICCs Can Share One System Bus (One Master)
—MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion
Chip and Intelligent Peripheral (22 MIPS at 25 MHz)
—Also Supports External MC68030-Type Bus Masters
—All QUICC Features Usable in Slave Mode
• Memory Controller (Eight Banks)
—Contains Complete Dynamic Random-Access Memory (DRAM) Controller
—Each Bank Can Be a Chip Select or Support a DRAM Bank
—Up to 15 Wait States
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M k 404
1-1
Introduction
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—Glueless Interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access Memory (SRAM), Electrically Programmable Read-Only Memory
(EPROM), Flash EPROM, etc.
—Four CAS lines, Four WE lines, One OE line
—Boot Chip Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory)
—Special Features for MC68040 Including Burst Mode Support
• Four General-Purpose Timers
—Superset of MC68302 Timers
—Four 16-Bit Timers or Two 32-Bit Timers
—Gate Mode Can Enable/Disable Counting
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• Two Independent DMAs (IDMAs)
—Single Address Mode for Fastest Transfers
—Buffer Chaining and Auto Buffer Modes
—Automatically Performs Efficient Packing
—32-Bit Internal and External Transfers
• System Integration Module (SIM60)
—Bus Monitor
—Double Bus Fault Monitor
—Spurious Interrupt Monitor
—Software Watchdog
—Periodic Interrupt Timer
—Low Power Stop Mode
—Clock Synthesizer
—Breakpoint Logic Provides On-Chip Hardware Breakpoints
—External Masters May Use On-Chip Features Such As Chip Selects
—On-Chip Bus Arbitration with No Overhead for Internal Masters
—IJTAG Test Access Port
• Interrupts
—Seven External IRQ Lines
—12 Port Pins with Interrupt Capability
—16 Internal Interrupt Sources
—Programmable Priority Between SCCs
—Programmable Highest Priority Request
• Communications Processor Module (CPM)
—RISC Controller
—Many New Commands (e.g., Graceful Stop Transmit, Close RxBD)
—224 Buffer Descriptors
—Supports Continuous Mode Transmission and Reception on All Serial Channels
—2.5 Kbytes of Dual-Port RAM
—14 Serial DMA (SDMA) Channels
—Three Parallel I/O Registers with Open-Drain Capability
—Each Serial Channel Can Have Its Own Pins (NMSI Mode)
• Four Baud Rate Generators
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Introduction
—Independent (Can Be Connected to Any SCC or SMC)
—Allows Changes During Operation
—Autobaud Support Option
• Four SCCs
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—Ethernet/IEEE 802.3 Optional on SCC1 (Full 10-Mbps Support)
—HDLC/SDLC1 (All Four Channels Supported at 2 Mbps)
—HDLC Bus (Implements an HDLC-Based Local Area Network (LAN))
—AppleTalk2
—Signaling System #7
—Universal Asynchronous Receiver Transmitter (UART)
—Synchronous UART
—Binary Synchronous Communication (BISYNC)
—Totally Transparent (Bit Streams)
—Totally Transparent (Frame Based with Optional Cyclic Redundancy Check (CRC))
—Profibus (RAM Microcode Option)
—Asynchronous HDLC (RAM Microcode Option)
—DCMP3 (RAM Microcode Option)
—V.14 (RAM Microcode Option)
—X.21 (RAM Microcode Option)
• Two SMCs
—UART
—Transparent
—General Circuit Interface (GCI) Controller
—Can Be Connected to the Time-Division Multiplexed (TDM) Channels
• One SPI
—Superset of the MC68302 SCP
—Supports Master and Slave Modes
—Supports Multimaster Operation on the Same Bus
• Time-Slot Assigner
• Supports Two TDM Channels
—Each TDM Channel Can Be T1, CEPT, PCM Highway, ISDN Basic Rate,
ISDN Primary Rate, User Defined
—1- or 8-Bit Resolution
—Allows Independent Transmit and Receive Routing, Frame Syncs, Clocking
—Allows Dynamic Changes
—Can Be internally Connected to Six Serial Channels (Four SCCs and
Two SMCs)
1.
SDLC is a trademark of International Business Machines.
2.
AppleTalk is a registered trademark of Apple Computer, Inc.
3.
DDCMP is a trademark of Digital Equipment Corporation.
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Introduction
• Parallel Interface Port
—Centronics4 Interface Support
—Supports Fast Connection Between QUICCs
• 240 Pins Defined: 241-Lead Pin Grid Array (PGA) and 240-Lead Plastic Quad Flat Pack
(PQFP)
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1.2 QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the Motorola
M68300 family. Like other members of the M68300 family, the QUICC incorporates the intermodule bus (IMB). (The MC68302 is an exception, having an M68000 bus on chip.) The IMB
provides a common interface for all modules of the M68300 family, which allows Motorola
to develop new devices more quickly by using the library of existing modules. Although the
IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first
device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM.
Each module utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure
1-1.
SIM 60
CPU32+
CORE
SYSTEM
PROTECTION
JTAG
PERIODIC
TIMER
BREAKPOINT
LOGIC
CLOCK
GENERATION
OTHER
FEATURES
DRAM
CONTROLLER
AND
CHIP SELECTS
EXTERNAL
BUS
INTERFACE
IMB (32 BIT)
SYSTEM
I/F
CPM
COMMUNICATIONS PROCESSOR
2.5-KBYTE
DUAL-PORT
RAM
RISC
CONTROLLER
TWO
IDMAs
FOURTEEN SERIAL
DMAs
SEVEN
SERIAL
CHANNELS
TIMER SLOT
ASSIGNER
INTERRUPT
CONTROLLER
FOUR
GENERALPURPOSE
TIMERS
OTHER
FEATURES
Figure 1-1. QUICC Block Diagram
4.
Centronics is a trademark of Centronics, Inc.
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Introduction
1.2.1 CPU32+ Core
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The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB
and apply the larger bus width. Although the original CPU32 core had a 32-bit internal data
path and 32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core
can operate on 32-bit external operands with one bus cycle. This allows the CPU32+ core
to fetch a long-word instruction in one bus cycle and to fetch two word-length instructions in
one bus cycle, filling the internal instruction queue more quickly. The CPU32+ core can also
read and write 32-bits of data in one bus cycle.
Although the CPU32+ instruction timings are improved, its instruction set is identical to that
of the CPU32. It will also execute the entire M68000 instruction set. It contains the same
background debug mode (BDM) features as the CPU32. No new compilers, assemblers, or
other software support tools need be implemented for the CPU32+; standard CPU32 tools
can be used.
The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted)
assumption that a 10-MHz M68000 delivers 1 VAX MIPS. If an application requires more
performance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an
intelligent peripheral to a faster processor. The QUICC provides a special mode called
MC68040 companion mode to allow it to conveniently interface to members of the M68040
family. This two-chip solution provides a 22-MIPS performance at 25 MHz.
The CPU32+ also offers automatic byte alignment features that are not offered on the
CPU32. These features allow 16 or 32-bit data to be read or written at an odd address. The
CPU32+ automatically performs the number of bus cycles required.
1.2.2 System Integration Module (SIM60)
The SIM60 integrates general-purpose features that would be useful in almost any 32-bit
processor system. The term “SIM60” is derived from the QUICC part number, MC68360.
The SIM60 is an enhanced version of the SIM40 that exists on the MC68340 and MC68330
devices.
First, new features, such as a DRAM controller and breakpoint logic, have been added. Second, the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus.
Third, new configurations, such as slave mode and internal accesses by an external master,
are supported.
Although the QUICC is always a 32-bit device internally, it may be configured to operate with
a 16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is
supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system
bus mode.
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1.2.3 Communications Processor Module (CPM)
The CPM contains features that allow the QUICC to excel in communications and control
applications. These features may be divided into three sub-groups:
• Communications Processor (CP)
• Two IDMA Controllers
• Four General-Purpose Timers
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The CP provides the communication features of the QUICC. Included are a RISC processor,
four SCCs, two SMCs, one SPI, 2.5 Kbytes of dual-port RAM, an interrupt controller, a time
slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and fourteen serial DMA channels to support the SCCs, SMCs, and SPI.
The IDMAs provide two channels of general-purpose DMA capability. They offer highspeed transfers, 32-bit data movement, buffer chaining, and independent request and
acknowledge logic. The RISC controller may access the IDMA registers directly in the buffer
chaining modes. The QUICC IDMAs are similar to, yet enhancements of, the two DMA channels found on the MC68340 and the one IDMA channel found on the MC68302.
The four general-purpose timers on the QUICC are functionally similar to the two generalpurpose timers found on the MC68302. However, they offer some minor enhancements,
such as the internal cascading of two timers to form a 32-bit timer. The QUICC also contains
a periodic interval timer in the SIM60, bringing the total to five on-chip timers.
1.3 UPGRADING DESIGNS FROM THE MC68302
Since the QUICC is a next-generation MC68302, many designers currently using the
MC68302 may wish to use the QUICC in a follow-on design. The following paragraphs
briefly discuss this endeavor in terms of architectural approach, hardware issues, and software issues. See Section 9 Applications for further information.
1.3.1 Architectural Approach
The QUICC is the logical extension of the MC68302, but the overall architecture and philosophy of the MC68302 design remains intact in the QUICC. The QUICC keeps the best features of the MC68302, while making the changes required to provide for the increased
flexibility, integration, and performance requested by customers. Because the CPM is probably the most difficult module to learn, anyone who has used the MC68302 can easily
become familiar with the QUICC since the CPM architectural approach remains intact.
The most significant architectural change made on the QUICC was the translation of the
design into the standard M68300 family IMB architecture, resulting in a faster CPU and different system integration features.
Although the features of the SIM60 do not exactly correspond to those of the MC68302 SIM,
they are very similar. The QUICC SIM60 combines the best MC68302 SIM features with the
best MC68340 SIM features for improved performance.
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Introduction
Because of the similarity of the QUICC SIM60 and CPU to other members of the M68300
family, such as the MC68332 and the MC68340, previous users of these devices will be
comfortable with these same features on the QUICC.
1.3.2 Hardware Compatibility Issues
The following list summarizes the hardware differences between the MC68302 and the
QUICC:
• Pinout—The pinout is not the same. The QUICC has 240 pins; the MC68302 has 132
pins.
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• Package—Both devices offer PGA and PQFP packages. However, the QUICC
PQFP package has a 20-mil pitch; whereas, the MC68302 PQFP package has a
25-mil pitch.
• System Bus—The system bus signals now look like those of the MC68030 as opposed
to those of the M68000. It is still possible to interface M68000 peripherals to the QUICC,
utilizing the same techniques used to interface them to an MC68020 or MC68030.
• System Bus in Slave Mode—A number of QUICC pins take on new functionality in slave
mode to support an external MC68EC040. On the MC68302, the pin names generally
remained the same in slave mode.
• Peripheral Timing—The external timings of the peripherals (SCCs, timers, etc.) are very
similar (if not identical) to corresponding peripherals on the MC68302.
• Pin Assignments—The assignment of peripheral functions to I/O pins is different in several ways. First, the QUICC contains more general-purpose parallel I/O pins than the
MC68302. However, the QUICC offers many more functions than even a 240-pin package would normally allow, resulting in more multifunctional pins than the MC68302.
1.3.3 Software Compatibility Issues
The following list summarizes the major software differences between the MC68302 and the
QUICC:
• Since the CPU32+ is a superset of the M68000 instruction set, all previously written
code will run. However, if such code is accessing the MC68302 peripherals, it will require some modification.
• The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block
on the MC68302. The register addresses within that memory map are different.
• The code used to initialize the system integration features of the MC68302 has
to be modified to write the corresponding features on the QUICC SIM60. Code written
for the MC68340 may be adapted in large part.
• As much as possible, QUICC CPM features were made identical to those of the
MC68302 CP. The most important benefit is that the code flow (if not the code itself) will
port easily from the MC68302 to the QUICC. The nuances learned from the MC68302
will still be useful in the QUICC.
• Although the registers used to initialize the QUICC CPM are new (for example, the SCM
on the MC68302 is replaced with the GSMR and PSMR on the QUICC), most registers
retain their original purpose such as the SCC event, SCC mask, SCC status, and com-
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mand registers. The parameter RAM of the SCCs is very similar, and most parameter
RAM register names and usage are retained. More importantly, the basic structure of a
buffer descriptor (BD) on the QUICC is identical to that of the MC68302, except for a
few new bit functions that were added. (In a few cases, a bit in a BD status word had to
be shifted.)
• When porting code from the MC68302 CP to the QUICC CPM, the software writer may
find that the QUICC has new options to simplify what used to be a more code-intensive
process. For specific examples, see the INIT TX AND RX PARAMETERS, GRACEFUL
STOP TRANSMIT, and CLOSE BD commands.
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1.4 QUICC GLUELESS SYSTEM DESIGN
A fundamental design goal of the QUICC was ease of interface to other system components.
An example of this goal is a minimal QUICC design using EPROM and DRAM, shown in Figure 1-2. This system interfaces gluelessly to an EPROM and a DRAM SIMM module. It also
offers parity support for the DRAM.
8-BIT BOOT
EPROM
(FLASH OR REGULAR)
QUICC
MC68360
CS0
CE (ENABLE)
OE
OE (OUTPUT ENABLE)
WE0
DATA
ADDRESS
WE (WRITE)
DATA
ADDRESS
16- OR 32-BIT
DRAM SIMM
(OPTIONAL PARITY)
RAS1
CAS3–CAS0
R/W
RAS
CAS3–CAS0
W (WRITE)
DATA
ADDRESS
PRTY3–PRTY0
PARITY
Figure 1-2. Minimum QUICC System Configuration
Figure 1-3 shows a larger system configuration. This system offers one EPROM, one flash
EPROM, and supports two DRAM SIMMs. Depending on the capacitance on the system
bus, external buffers may be required. From a logic standpoint, however, a glueless system
is maintained.
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Introduction
8-BIT BOOT
EPROM
(FLASH OR REGULAR)
QUICC
MC68360
CS0
CE (ENABLE)
OE
OE (OUTPUT ENABLE)
WE (WRITE)
WE0
DATA
DATA
ADDRESS
ADDRESS
8-, 16-, OR 32-BIT SRAM
E (ENABLE)
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CS7
G (OUTPUT ENABLE)
WE3–WE0
W (WRITE)
DATA
ADDRESS
16- OR 32-BIT
TWO DRAM SIMMs
(OPTIONAL PARITY)
RAS2
RAS
RAS1
BUFFER
CAS3–CAS0
R/W
RAS
CAS3–CAS0
W (WRITE)
DATA
ADDRESS
PRTY3–PRTY0
PARITY
Figure 1-3. Larger QUICC System Configuration
1.5 QUICC SERIAL CONFIGURATIONS
The QUICC offers an extremely flexible set of communications capabilities. Although a full
understanding of the possibilities requires reading the appropriate sections, some of the
possibilities are shown in the following diagrams. They show possible connections between
QUICC devices. In addition, connections are often shown between QUICCs and the
MC68302 to show the compatibility between these devices.
For readability, transceivers are usually omitted in the following diagrams. For local onboard communications, however, transceivers are often optional and depend on the protocol used.
Figure 1-4 shows the Ethernet LAN capability of the QUICC. An external SIA transceiver is
required to complete the interface to the media. This functionality is implemented in the
MC68160 enhanced Ethernet serial transceiver (EEST ). The MC68160 EEST supports
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connections to the attachment unit interface (AUI) or twisted-pair Ethernet formats and provides a glueless interface to the QUICC.
ETHERNET
QUICC
SCC1
MC68160
EEST
SCC1
MC68160
EEST
SCC1
MC68160
EEST
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QUICC
QUICC
Figure 1-4. Ethernet LAN Capability
Figure 1-5 shows the AppleTalk LAN capability of the QUICC. Note that the MC68302
requires an extra device, the MC68195 LocalTalk adapter, to interface to AppleTalk.
QUICC
SCC
RS422
XCVR
SCC
RS422
XCVR
QUICC
MC68302
SCC
MC68195
LA
RS422
XCVR
NOTE: The QUICC implements the AppleTalk LAN
protocol without the need for the MC68195.
Figure 1-5. AppleTalk LAN Capability
Figure 1-6 shows the implementation of a LAN structure of HDLC called HDLC bus. This
protocol is the fastest, easiest way to interface multiple QUICCs in an HDLC-based protocol.
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Introduction
QUICC
SCC
QUICC
SCC
HDLC BUS
QUICC
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SCC
NOTES:
1. HDLC bus—any node can obtain
mastership.
2. The QUICC handles collisions
without external glue.
Figure 1-6. HDLC Bus LAN
Figure 1-7 shows the original SDLC application, which can be implemented by both QUICCs
and MC68302s.
QUICC
SCC
QUICC
SCC
SDLC BUS
MC68302
SCC
NOTE: No collisions are allowed in this
master-slave approach. Also
available on the MC68302.
Figure 1-7. FSDLC Bus Implementation
Figure 1-8 shows a UART LAN configuration that is supported by both the QUICC and the
MC68302, as well as many other industry UARTs.
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QUICC
SCC
QUICC
SCC
MULTI-DROP
UART
MC68302
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SCC
NOTES:
1. Simple LAN based on UART mode.
2. Ninth bit is an "address" bit.
Figure 1-8. UART LAN Implementation
Figure 1-9 shows how the SPIs on the QUICC can be used to connect devices together into
a local bus. The SPI exists on many other Motorola devices, such as the MC68HC11 microcontroller, and a number of peripherals such as A/D and D/A converters, LED drivers, LCD
drivers, real-time clocks, serial EEPROM, PLL frequency synthesizers, and shift registers.
QUICC
SPI
MASTER/SLAVE
QUICC
SPI
MASTER/SLAVE
SPI BUS
QUICC
SPI
MASTER/SLAVE
NOTE: SPI bus configuration—each QUICC
can be the master in turn.
Figure 1-9. SPI Local Bus Implementation
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Figure 1-10 shows how the SCP on the MC68302 can be used to interface to the QUICC
SPI.
MC68302
QUICC
SPI BUS
SPI
SLAVE
SCP
MASTER
EEPROMS
ETC.
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SPI
SLAVE
NOTE: The MC68302 SCP can communicate with the QUICC SPI.
Figure 1-10. SPI Implementation Using SCP
Figure 1-11 shows how the SPI on the QUICC can interface to another QUICC or SPI-based
peripherals.
QUICC
QUICC
SPI
MASTER
SPI BUS
SPI
SLAVE
EEPROMS
ETC.
SPI
SLAVE
NOTE: Two QUICCs configured for a master-slave SPI connection.
Figure 1-11. SPI Master-Slave Implementation
Figure 1-12 shows how the parallel interface port (PIP) can be used to implement the Centronics interface connection. The QUICC may be the peripheral or the host.
QUICC
CENTRONICS
INTERFACE
PIP
8 DATA LINES
HOST
COMPUTER
OR PRINTER
NOTE: The QUICC can communicate over a Centronics Interface.
Figure 1-12. Centronics Interface Implementation
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Figure 1-13 shows how the PIP can also be used to implement a fast parallel connection
between devices.
QUICC
QUICC
PARALLEL
INTERFACE
PIP
8 DATA LINES
PIP
NOTE: Fast parallel connection between QUICCs.
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Figure 1-13. Fast Parallel Connection Implementation
Figure 1-14 shows which SCC protocols may be used to connect SCCs on the QUICC and
the MC68302.
HDLC/SDLC
BISYNC
UART
TRANSPARENT
QUICC
SCC
MC68302
SCC
Figure 1-14. SCC Protocol Implementation
Figure 1-15 shows which SCC protocols may be used to connect SCCs on multiple QUICCs
or to other devices supporting such protocols.
HDLC/SDLC
BISYNC UART
TRANSPARENT
SYNCHRONOUS UART
SS#7
QUICC
SCC
QUICC
SCC
NOTE: Point-to-point (WAN) configurations are available on the QUICC.
Figure 1-15. Multiple QUICC Point-to-Point Implementation
Figure 1-16 shows other point-to-point options that are possible with the QUICC and the
MC68302.
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QUICC
Introduction
MC68302
SMC
UART
TRANSPARENT
SCC
QUICC
MC68302
SMC
SCP
TRANSPARENT
QUICC
QUICC
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SMC
UART
TRANSPARENT
SMC
Figure 1-16. Other Point-to-Point Implementations
Figure 1-17 shows how up to six of the serial channels can connect to a TDM interface. The
QUICC provides a built-in time-slot assigner for access to the TDM time slots. Other channels can work with their own set of pins, allowing possibilities like an Ethernet to T1 bridge,
etc.
QUICC
SCC
SCC
SCC
SCC
SMC
SMC
TIME
SLOT
ASSIGNER
TIME DIVISION MULTIPLEXED BUS
T1, CEPT, IDL, GCI, ISDN,
PRIMARY RATE,
USER-DEFINED
ANY COMBINATION OF SCCs
AND SMCs MAY BE
CONNECTED TO THE TDM.
NOTE: Independent receive and transmit clocking, routing,
and syncs are supported.
Figure 1-17. Serial Channel to TDM Bus Implementation
Figure 1-18 shows that the QUICC time-slot assigner can support two TDM buses. Each
TDM bus can be of a different format—for example, one TDM can be a T1 line, and one can
be a CEPT line. Also this technique could be used to bridge frames from basic rate ISDN to
a T1/CEPT line, etc.
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QUICC
SCC
SCC
SCC
SCC
SMC
SMC
TIME
SLOT
ASSIGNER
TDM BUS 1
TDM BUS 2
ANY COMBINATION OF SCCs
AND SMCs MAY BE
CONNECTED TO ANY TDM.
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NOTE: Two TDM buses may be simultaneously supported
with the time slot assigner.
Figure 1-18. Dual TDM Bus Implementation
1.6 QUICC SERIAL CONFIGURATION EXAMPLES
Figure 1-19 shows a situation where multiple QUICCs can communicate over a TDM line.
This can be used, for instance, to implement an 8-channel line card. The SCCs implement
the line interfaces, and the SMCs provide the local on-board communication between the
QUICCs. The additional SMC on each QUICC can be used as a serial debug port. The SPI
can be used to interface to peripherals, such as a serial EEPROM.
QUICC
SCC
SCC
SCC
SCC
SMC
SMC
TIME
SLOT
ASSIGNER
TDM BUS
TWO SMCs ARE
USED TO
COMMUNICATE
LOCALLY
BETWEEN QUICCs
OVER A TIME SLOT.
QUICC
SCC
SCC
SCC
SCC
SMC
SMC
TIME
SLOT
ASSIGNER
NOTE: The eight SCCs and two SMCs support 10 time slots on the TDM bus.
The length and position of the time slots are made with time slot assigners.
Figure 1-19. Multiple QUICC TDM Bus Implementation
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Figure 1-20 shows a general-purpose application that includes Ethernet, AppleTalk, an
HDLC connection to a T1 line, an HDLC connection to frame relay, a UART debug monitor
port, a totally transparent data stream port, and an SPI connection to a serial EEPROM.
QUICC
SYSTEM
BUS
SERIAL
EEPROM
SPI
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SCC3
SCC1
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SIA
TRANSCEIVER
SCC2
RS-422
TIME
SLOT
ASSIGNER
ETHERNET
APPLE TALK
X.25 (HDLC)
T1 LINE
TRANSCEIVER
SCC4
RS-232
SMC1
RS-232
FRAME RELAY (HDLC)
UART
RS-232
SMC2
DEBUG
PORT
TRANSPARENT DATA
Figure 1-20. General-Purpose Application
1.7 QUICC SYSTEM BUS CONFIGURATIONS
Figure 1-21 shows a master-slave QUICC configuration. This system gives eight SCCs, four
SMCs, two SPIs, four IDMAs, etc. Each QUICC uses its own DMA capability, but the
CPU32+ is the only processor in the system. More QUICCs can be easily supported on the
system bus, if desired.
QUICC SYSTEM BUS
QUICC
MASTER
QUICC
SLAVE
CPU32+
CPU32+
SCC
SCC
SCC
SCC
SMC
SMC
SPI
SCC
SCC
SCC
SCC
SMC
SMC
SPI
Figure 1-21. Master-Slave QUICC Implementation
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The QUICC has special features in slave mode to support the M68040 family. When the
QUICC is used in this way, it is said to be in MC68040 companion mode. Figure 1-22 shows
how a QUICC in slave mode can interface to a MC68EC040. (The MC68EC040 is a lowcost version of the MC68040 with identical integer performance, but without the memory
management unit (MMU) and the floating-point unit (FPU).) The DRAM controller on the
QUICC will control the accesses of the MC68EC040 (including the burst modes). This configuration does require external address multiplexers, but the QUICC controls the multiplexers. The QUICC supports the MC68EC040 in other ways, such as interrupt handling and
system protection features. When it is in slave mode, the QUICC can also be interfaced to
any MC68030-type bus master instead of the MC68EC040.
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QUICC SLAVE
MC68EC040
SUPPORT
FUNCTIONS
MC68EC040
CPU32+
SYSTEM BUS
CONTROL
MEMORY
CONTROLLER
SCC
SCC
SCC
SCC
SMC
SMC
SPI
EPROM
DRAM
ADDRESS
MUXs
SRAM
Figure 1-22. MC68040 Companion Mode
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SECTION 2
SIGNAL DESCRIPTIONS
This section contains brief descriptions of the QUICC input and output signals in their functional groups as shown in Figure 2-1.
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2.1 SYSTEM BUS SIGNAL INDEX
The QUICC system bus signals consist of two groups. The first group, listed in Table 2-1,
consists of system bus signals that exist when the QUICC is in the normal mode (CPU32+
enabled). The second group consists of system bus signals that exist when the QUICC is in
the slave mode (CPU32+ disabled). They are listed in Table 2-7 and may also be identified
in Figure 2-1 as those with an italic font. In Table 2-1, the signal name, mnemonic, and a
brief functional description are presented. For more detail on each signal, refer to the paragraphs that discuss each signal.
2.1.1 Address Bus
The address bus consists of the following two groups. Refer to Section 4 Bus Operation for
information on the address bus and its relationship to bus operation.
2.1.1.1 ADDRESS BUS (A27–A0). This three-state bidirectional bus (along with A31–A28)
provides the address for the current bus cycle, except in the CPU address space. Refer to
Section 4 Bus Operation for more information on the CPU address space. A27 is the most
significant address signal in this group.
2.1.1.2 ADDRESS BUS (A31–A28). These pins can be programmed as the most significant four address bits or as four byte write enables.
A31–A28—These pins can function as the most significant 4 address bits. A31 is the
most significant address signal in this group.
WE3–WE0—On a write cycle, these active-low signals indicates which byte of the 32bit data bus contains valid data.
WE0—Corresponds to A31 and selects data bits 31–24. Also may be referred to as UUWE.
WE1—Corresponds to A30 and selects data bits 23–16. Also may be referred to as UMWE.
WE2—Corresponds to A29 and selects data bits 15–8. Also may be referred to as LMWE.
WE3—Corresponds to A28 and selects data bits 7–0. Also may be referred to as LLWE.
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Thi d
t
t d ith F
M k 404
2-1
Signal Descriptions
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NOTE
Write enable does not have the capability to follow dynamic bus
sizing with external assertion of DSACK. Write enable will always follow the port size that is programed in GMR and the OR.
For more information see 6.10 Memory Controller.
ADDRESS BUS
A27–A0
PORT A
A31–A28/WE3–WE0
RXD1/PA0
TXD1/PA1
FC2–FC0/TM2–TM0
RXD2/PA2
TXD2/PA3
FC3/TT0
DATA BUS
D31–D16
L1TXDB/RXD3/PA4
L1RXDB/TXD3/PA5
D15–D0
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L1TXDA/RXD4/PA6
L1RXDA/TXD4/PA7
TIMERs/SCCs/SIs/CLOCKs/BRG
TIN1/L1RCLKA/BRGO1/CLK1/PA8
BRGCLK1/TOUT1/CLK2/PA9
TIN2/L1TCLKA/BRGO2/CLK3/PA10
TOUT2/CLK4/PA11
TIN3/BRGO3/CLK5/PA12
BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13
TIN4/BRGO4/CLK7/PA14
L1TCLKB/TOUT4/CLK8/PA15
PORT B (PIP)
RRJCT1/SPISEL/PB0
RSTRT2/SPICLK/PB1
RRJCT2/SPIMOSI(SPITXD)/PB2
BRGO4/SPIMISO(SPIRXD)/PB3
DREQ1/BRGO1/PB4
DACK1/BRGO2/PB5
DONE1/SMTXD1/PB6
DONE2/SMRXD1/PB7
DREQ2/SMSYN1/PB8
DACK2/SMSYN2/PB9
L1CLKOB/SMTXD2/PB10
L1CLKOA/SMRXD2/PB11
L1ST1/RTS1/PB12
L1ST2/RTS2/PB13
L1ST3/L1RQB/RTS3/PB14
L1ST4/L1RQA/RTS4/PB15
STRBO/BRGO3/PB16
STRBI/RSTRT1/PB17
PORT C (INTERRUPT PARALLEL I/O)
L1ST1/RTS1/PC0
L1ST2/RTS2/PC1
L1ST3/L1RQB/RTS3/PC2
L1ST4/L1RQA/RTS4/PC3
CTS1/PC4
TGATE1/CD1/PC5
CTS2/PC6
TGATE2/CD2/PC7
SDACK2/L1TSYNCB/CTS3/PC8
L1RSYNCB/CD3/PC9
SDACK1/L1TSYNCA/CTS4/PC10
L1RSYNCA/CD4/PC11
QUICC
MC68360
240 PINS
PRTY1–PRTY0/IOUT1–IOUT2
PRTY2/IOUT0/RQOUT
PRTY3/16BM
BUS CONTROL
SIZ0
SIZ1
DSACK0/TBI
DSACK1/TA
R/W
AS
DS/TT1
OE/AMUX
BUS ARBITRATION
RMC/CONFIG0/LOCK
BR
BG
BGACK/BB
BCLRO/CONFIG1/RAS2DD
SYSTEM CONTROL
RESETH
RESETS
HALT
BERR/TEA
PERR
INTERRUPT CONTROL
IRQ1/IOUT0/RQOUT
IRQ4/IOUT1
IRQ6/IOUT2
IRQ2,3,5,7
AVEC/IACK5/AVECO
MEMORY CONTROLLER
CS6–CS0/RAS6–RAS0
CS/RAS7/IACK7
CAS3–CAS0/IACK6,3,2,1
TEST
TRIS/TS
BKPT/BKPTO/DSCLK
FREEZE/CONFIG2/MBARE
IPIPE1/RAS1DD/BCLRI
IPIPE0/BADD2/DSO
IFETCH/BADD3/DSI
TCK
TMS
TDI
TDO
TRST
CLOCK
XTAL
EXTAL
XFC
MODCK1–MODCK0
CLKO2–CLKO1
Figure 2-1. QUICC Functional Signal Groups
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Signal Descriptions
Table 2-1. System Bus Signal Index (Normal Operation)
Group
Address
Data
Parity
Signal Name
Address Bus
A27–A0
Upper four bits of address bus (I/O), or byte write enable signals (O) for accesses to external memory or peripherals.
Function Codes
FC3–FC0
Identifies the processor state and the address space of the
current bus cycle. (I/O)
Data Bus 31–16
D31–D16
Upper 16-bit data bus used to transfer byte or word data.
Used in 16-bit bus mode (I/O).
Data Bus 15–0
D15–D0
Lower 16-bit data bus used to transfer 3-byte or long-word
data (I/O). Not used in 16-bit bus mode.
PRTY2–PRTY0
Parity signals for byte writes/reads from/to external memory
module (I/O).
PRTY3/16BM
Parity signals for byte writes/reads from/to external memory
module or defines 16-bit bus mode. (I/O)
Parity 2–0
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PERR
CS/RAS7/IACK7
Enables peripherals or DRAMs at programmed addresses
(O) or interrupt level 7 acknowledge line (O).
Chip Select 6–0/
Row Address Select
6–0
CS6–CS0/
RAS6–RAS0
Enables peripherals or DRAMs at programmed addresses.
(O)
Column Address Select 3–0/Interrupt Acknowledge 1, 2, 3, 6
CAS3-CAS0/
IACK6,3,2,1
DRAM column address select or interrupt level acknowledge
lines. (O)
BR
Indicates that an external device requires bus mastership. (I)
BG
Indicates that the current bus cycle is complete and the
QUICC has relinquished the bus. (O)
Bus Grant
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership. (I)
Read-Modify-Write
Cycle/Initial Configuration 0
RMC/CONFIG0
Identifies the bus cycle as part of an indivisible read-modifywrite operation (I/O) or initial QUICC configuration select (I).
Bus Clear Out/
Initial Configuration
1/Row Address Select 2 Double-Drive
that an internal device requires the external bus
BCLRO/CONFIG1/ Indicates
(Open-Drain O) or initial QUICC configuration select (I) or
RAS2DD
row address select 2 double-drive output (O).
Data and Size Acknowledge
Provides asynchronous data transfer acknowledgement and
DSACK1–DSACK0 dynamic bus sizing (open-drain I/O but driven high before
three-stated).
Address Strobe
AS
Indicates that a valid address is on the address bus. (I/O)
Data Strobe
DS
During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write cycle,
DS indicates that valid data is on the data bus. (I/O)
SIZ1–SIZ0
Indicates the number of bytes remaining to be transferred for
this cycle. (I/O)
Size
Read/Write
R/W
Indicates the direction of data transfer on the bus. (I/O)
Output Enable/
Address Multiplex
OE/AMUX
Active during a read cycle indicates that an external device
should place valid data on the data bus (O) or provides a
strobe for external address multiplexing in DRAM accesses
if internal multiplexing is not used (O).
Interrupt Request
Level 7–1
IRQ7–IRQ1
Provides external interrupt requests to the CPU32+ at priority levels 7–1. (I)
Autovector/Interrupt
Acknowledge 5
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Indicates a parity error during a read cycle. (O)
Chip Select/Row Address Select 7/
Interrupt Acknowledge 7
Bus Arbitration Bus Request
Interrupt
Control
Lower 27 bits of address bus. (I/O)
A31–A28/
WE0–WE3
Parity Error
Bus Control
Function
Address Bus/Byte
Write Enables
Parity3/16BM
Memory
Controller
Mnemonic
AVEC/IACK5
Autovector request during an interrupt acknowledge cycle
(open-drain I/O) or interrupt level 5 acknowledge line (O).
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)
Table 2-1. System Bus Signal Index (Normal Operation)(Continued)
Group
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System
Control
Signal Name
Mnemonic
Function
Soft Reset
RESETS
Sft system reset. (open-drain I/O)
Hard Reset
RESETH
Hard system reset. (open-drain I/O)
Halt
HALT
Suspends external bus activity. (open-drain I/O)
Bus Error
BERR
Indicates an erroneous bus operation is being attempted.
(open-drain I/O)
Clock and Test System Clock Out 1
CLKO1
Internal system clock output 1. (O)
System Clock Out 2
CLKO2
Internal system clock output 2—normally 2x CLKO1. (O)
Crystal Oscillator
EXTAL,
XTAL
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O).
External Filter Capacitor
XFC
Connection pin for an external capacitor to filter the circuit of
the PLL (I).
Clock Mode Select
1–0
Instruction Fetch/
Development Serial
Input
IFETCH/DSI
Indicates when the CPU32+ is performing an instruction
word prefetch (O) or input to the CPU32+ background debug
mode (I).
Instruction Pipe 0/
Development Serial
Output
IPIPE0/DSO
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode (O).
Instruction Pipe 1/
Row Address Select
1 Double-Drive
IPIPE1/RAS1DD
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O).
BKPT/DSCLK
Signals a hardware breakpoint to the QUICC (open-drain I/
O), or clock signal for CPU32+ background debug mode (I).
FREEZE/
CONFIG2
Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I).
Three-State
TRIS
Used to three-state all pins if QUICC is configured as a master. Sampled during system reset. (I)
Test Clock
TCK
Provides a clock for Scan test logic. (I)
Test Mode Select
TMS
Controls test mode operations. (I)
Test Data In
TDI
Serial test instructions and test data signal. (I)
Test Data Out
TDO
Serial test instructions and test data signal. (O)
Test Reset
TRST
Provides an asynchronous reset to the test controller. (I)
Clock and Test Breakpoint/
Development Serial
(Cont'd)
Clock
Freeze/Initial Configuration 2
Power
—
the source of the internal system clock. (I) THESE
MODCK1–MODCK0 Selects
PINS SHOULD NOT BE SET TO 00
Clock Synthesizer
Power
VCCSYN
Power supply to the PLL of the clock synthesizer.
Clock Synthesizer
Ground
GNDSYN
Ground supply to the PLL of the clock synthesizer.
Clock Out Power
VCCCLK
Power supply to clock out pins.
Clock Out Ground
GNDCLK
Ground supply to clock out pins.
Special Ground 1
GNDS1
Special ground for fast AC timing on certain system bus signals.
Special Ground 2
GNDS2
Special ground for fast AC timing on certain system bus signals.
System Power Supply and Return
VCC, GND
Power supply and return to the QUICC.
No Connect
NC4–NC1
Four no-connect pins.
NOTE: I denotes input, 0 denotes output, and I/O is input/output.
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Signal Descriptions
2.1.2 Function Codes (FC3–FC0)
These three-state bidirectional signals identify the processor state and the address space
of the current bus cycle as noted in Table 2-2. The function code pins provide the purpose
of each bus cycle to external logic.
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Other bus masters besides the QUICC may also output function codes during their bus
cycles. On the QUICC, this capability is provided for each potential internal bus master (i.e.,
the IDMA, SDMA, and DRAM refresh units). Provision is also made for the decoding of function codes that are output from external bus masters (e.g., in the memory controller chipselect generation logic).
In computer design, function code information can be used to protect certain portions of the
address map from unauthorized access or to extend the addressable range beyond the
address limit. However, in controller applications, function codes are most often used as a
debugging aid. Furthermore, in most controller applications, the QUICC stays continuously
in the supervisor state.
Refer to Section 4 Bus Operation for more information.
Table 2-2. Address Space Encoding
Function Code Bits
3
2
1
0
Address Space
0
0
0
0
Reserved (Motorola)
0
0
0
1
User Data Space
0
0
1
0
User Program Space
0
0
1
1
Reserved (User)
0
1
0
0
Reserved (Motorola)
0
1
0
1
Supervisor Data Space
0
1
1
0
Supervisor Program Space
0
1
1
1
Supervisor CPU Space
1
x
x
x
DMA Space
NOTE
FC3-0 may not be set to 0xF
2.1.3 Data Bus
The data bus consists of the following two groups. Refer to Section 4 Bus Operation for information on the data bus and its relationship to bus operation.
2.1.3.1 DATA BUS (D31–D16). These three-state bidirectional signals (along with D15–
D0) provide the general-purpose data path between the QUICC and all other devices.
Although the data path is a maximum of 32 bits wide, it can be dynamically sized to support
8-, 16-, or 32-bit transfers. D31 is the MSB of the data bus. Byte and word operations occur
on D31–D16. Additionally, if the QUICC is configured into 16-bit bus mode, the D31–D16
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pins are the only data pins used. Refer to Section 4 Bus Operation for information on the
data bus and its relationship to bus operation.
2.1.3.2 DATA BUS (D15–D0). These pins can function as 16 additional data pins used in
long-word and 3-byte transfers. They are three-stated and not used if the QUICC is configured into 16-bit bus mode.
2.1.4 Parity
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These three-state bidirectional signals provide parity generation/checking for the data path
between the QUICC or external masters and other devices. There are four parity lines—one
for every eight data bits. The parity lines consists of two groups. Refer to Section 6 System
Integration Module (SIM60) for more information on parity generation/checking.
2.1.4.1 PARITY (PRTY0). This pin is the parity value for data bits 31–24.
2.1.4.2 PARITY (PRTY1). This pin is the parity value for data bits 23–16.
2.1.4.3 PARITY (PRTY2). This pin is the parity value for data bits 15–8.
2.1.4.4 PARITY (PRTY3). This pin has two functions. During total system reset, it is the
16BM pin to determine whether 16-bit data bus mode is to be enabled. After system reset,
it functions as the parity line 3.
PRTY3—This pin is the parity value for data bits 0–7.
16BM—This pin selects the 16-bit data bus mode. To choose a 32-bit data bus during total
system reset, this pin can be left floating (it has an internal pullup resistor) or can be driven/
pulled high. To choose a 16-bit data bus during total system reset, this pin should be driven/
pulled low.
2.1.5 Memory Controller
The following signals are used to control an external memory device.
2.1.5.1 CHIP SELECT/ROW ADDRESS SELECT (CS6–CS0/RAS6–RAS0). The
chipselect output signals enable peripherals or memory arrays at programmed addresses. CS0
is the global chip select for the boot ROM containing the user’s reset vector and initialization
program. Refer to Section 6 System Integration Module (SIM60) for more information on
chip selects.
NOTE
In addition, RAS1 can be simultaneously output on the RAS1DD
pin to increase the RAS1 line drive capability, and RAS2 can be
simultaneously output on the RAS2DD pin to increase the RAS2
line drive capability.
2.1.5.2 CHIP SELECT/ROW ADDRESS SELECT/INTERRUPT ACKNOWLEDGE (CS7/
RAS7/IACK7). This pin can be programmed as a CS7/RAS7 pin or as the IACK7 line. See
Section 6 System Integration Module (SIM60) for more information on this selection.
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RAS7/CS7—Row address select 7 or chip select 7 output signal.
IACK7—The QUICC asserts this pin to indicate a level 7 external interrupt during an interrupt acknowledge cycle. Peripherals can use the IACKx strobes instead of monitoring the
address bus and function codes to determine that an interrupt acknowledge cycle is in
progress and to obtain the current interrupt level. IACKx lines need not be used when the
vector is generated internally by the QUICC. See Section 4 Bus Operation for more information.
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2.1.5.3 COLUMN ADDRESS SELECT/INTERRUPT ACKNOWLEDGE (CAS3–CAS0/
IACK6, 3, 2, 1). These pins can be programmed as four column address selects for
DRAMs or as interrupt acknowledge lines.
CAS3–CAS0—The DRAM column address select output signal enables the DRAM columns:
CAS0 selects data bits 31–24.
CAS1 selects data bits 23–16.
CAS2 selects data bits 15–8.
CAS3 selects data bits 7–0.
IACK1, IACK2, IACK3, IACK6—The QUICC asserts one of these pins to indicate the level
of an external interrupt during an interrupt acknowledge cycle. Peripherals can use the
IACKx strobes instead of monitoring the address bus and function codes to determine that
an interrupt acknowledge cycle is in progress and to obtain the current interrupt level. IACKx
lines need not be used when the vector is generated internally by the QUICC. See Section
4 Bus Operation for more information.
IACK1 corresponds to CAS0.
IACK2 corresponds to CAS1.
IACK3 corresponds to CAS2.
IACK6 corresponds to CAS3.
2.1.5.4 ADDRESS MULTIPLEX (AMUX). See 2.1.7.7 Output Enable/Address Multiplex
(OE/AMUX) for more information.
2.1.6 Interrupt Request Level (IRQ7–IRQ1)
These pins are prioritized interrupt request lines. IRQ7, the highest priority, is nonmaskable;
IRQ6–IRQ1 are internally maskable interrupts. Refer to Section 5 CPU32+ for more information on the interrupt request lines.
2.1.7 Bus Control Signals
These signals control the bus transfer operations of the QUICC. Refer to Section 4 Bus
Operation for more information on these signals.
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2.1.7.1 DATA AND SIZE ACKNOWLEDGE (DSACK1–DSACK0). These two active-low
bidirectional signals allow asynchronous data transfers and dynamic data bus sizing
between the QUICC and external devices (see Table 2-3).
Table 2-3. DSACKx Encoding
DSACK1
DSACK0
Result
1 (Negated)
1 (Negated)
Insert wait states in current bus cycle.
1 (Negated)
0 (Asserted)
Complete cycle—data bus port size is 8 bits.
0 (Asserted)
1 (Negated)
Complete cycle—data bus port size is 16 bits.
0 (Asserted)
0 (Asserted)
Complete cycle—data bus port size is 32 bits.
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2.1.7.2 AUTOVECTOR/INTERRUPT ACKNOWLEDGE (AVEC/IACK5). This pin can be
programmed to be an autovector input or the interrupt acknowledge 5 line output.
AVEC—This signal requests an automatic vector during an interrupt acknowledge cycle.
Refer to Section 6 System Integration Module (SIM60) for more information on the autovector function. AVEC need not be used if the QUICC supplies the vector internally.
IACK5—The QUICC asserts this pin to indicate the level of an external interrupt during an
interrupt acknowledge cycle at level 5. Peripherals can use the IACKx strobes instead of
monitoring the address bus and function codes to determine that an interrupt acknowledge
cycle is in progress and to obtain the current interrupt level. IACKx lines need not be used
when the vector is generated internally by the QUICC.
2.1.7.3 ADDRESS STROBE (AS). This bidirectional signal is driven by the bus master to
indicate a valid address on the address bus. The function code, size, and read/write signals
are also valid when AS is asserted.
2.1.7.4 DATA STROBE (DS). During a read cycle, this input/output signal is driven by the
bus master to indicate that an external device should place valid data on the data bus. During a write cycle, the data strobe indicates that valid data is on the data bus.
2.1.7.5 TRANSFER SIZE (SIZ1, SIZ0). These bidirectional signals are driven by the bus
master to indicate the number of operand bytes remaining to be transferred in the current
bus cycle (see Table 2-4).
Table 2-4. SIZx Encoding
SIZ1
SIZ0
Transfer Size
0
1
Byte
1
0
Word
1
1
3 Bytes
0
0
Long Word
2.1.7.6 READ/WRITE (R/W). This active-high bidirectional signal is driven by the bus master to indicate the direction of data transfer on the bus. A logic one indicates a read from a
slave device; a logic zero indicates a write to a slave device.
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Signal Descriptions
2.1.7.7 OUTPUT ENABLE/ADDRESS MULTIPLEX (OE/AMUX). This pin can be programmed as the output enable (OE) output or as the address multiplex output.
OE—During a read cycle, this output signal is driven by the bus master to indicate that an
external device should place valid data on the data bus. OE may used to save an external
inversion of the R/W signal.
AMUX—This output signal is driven by the DRAM controller to the external address multiplexer. AMUX need not be used if the DRAM addresses are multiplexed internally by the
QUICC.
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2.1.7.8 BYTE WRITE ENABLE (WE3–WE0). See 2.1.1.2 Address Bus (A31–A28) for the
description.
2.1.8 Bus Arbitration Signals
The following signals are the four bus arbitration control signals used to determine the bus
master. Refer to Section 4 Bus Operation for more information concerning these signals.
2.1.8.1 BUS REQUEST (BR). This active-low input signal indicates that an external device
needs to become the bus master. This input is typically wire-ORed.
2.1.8.2 BUS GRANT (BG). Assertion of this active-low output signal indicates that the bus
master has relinquished the bus.
2.1.8.3 BUS GRANT ACKNOWLEDGE (BGACK). Assertion of this active-low input indicates that an external device has become the bus master.
2.1.8.4 READ-MODIFY-WRITE CYCLE/INITIAL CONFIGURATION (RMC/CONFIG0).
This pin can be programmed as the read-modify-write cycle output or as the initial configuration pin 0 input signal during system reset.
RMC—This output signal identifies the bus cycle as part of an indivisible read-modify-write
operation; it remains asserted during all bus cycles of the read-modify-write operation to
indicate that bus ownership cannot be transferred.
NOTE
RMC is muxed with a CONFIG0 pin. RMC only functions when
the CPU32+ is enabled, and is an output unless an external
master ownes the bus, in which case it is an input.
CONFIG0—See 2.1.13 Initial Configuration Pins (CONFIG) for the description.
2.1.8.5 BUS CLEAR OUT/INITIAL CONFIGURATION/ROW ADDRESS SELECT
DOUBLE-DRIVE (BCLRO/CONFIG1/RAS2DD). This pin can be programmed as the bus
clear out output or as the initial configuration pin 1 input signal during system reset or as the
RAS2DD output double-drive signal.
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BCLRO—This active-low open-drain output indicates that one of the QUICC internal bus
masters is requesting the external bus master to release the bus.
CONFIG1—See 2.1.13 Initial Configuration Pins (CONFIG) for the description.
RAS2—See 2.1.5.1 Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) for the
description.
2.1.9 System Control Signals
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The QUICC uses these signals to recover from an exception. Refer to Section 4 Bus Operation for more information on these signals.
2.1.9.1 SOFT RESET (RESETS). This active-low, open-drain, bidirectional signal is used to
initiate reset. An external reset signal (as well as a reset from the SIM60) resets the QUICC
as well as all external devices. A reset signal from the CPU32+ (asserted as part of the
RESET instruction) resets external devices only—the internal state of the CPU32+ is not
affected; other on-chip modules are reset, but the configuration is not altered. When
asserted by the QUICC, this signal is guaranteed to be asserted for a minimum of 512 clock
cycles. For more information see 4.7 Reset Operation.
2.1.9.2 HARD RESET (RESETH). This active-low, open-drain, bidirectional signal is used
to initiate reset. An external hard reset signal (as well as an hard reset from the SIM60)
resets the QUICC as well as all external devices and the internal state of the CPU32+; other
on-chip modules are reset as well as the QUICC configuration. When asserted by the
QUICC, this signal is guaranteed to be asserted for a minimum of 512 clock cycles. For more
information see 4.7 Reset Operation.
During a hard reset, the address, data, and bus control pins are all three-stated. The BG pin
output is the same as that on the BR input. The general-purpose I/O pins are all configured
as inputs. The NC4–NC1 pins are undefined outputs. The XTAL, CLKO1, and CLKO2 pins
are active outputs, except for CLKO1 which does not oscillate while the on-chip PLL is
attaining a lock. The RESETS pin is an output.
2.1.9.3 HALT (HALT). This active-low, open-drain, bidirectional signal is asserted to suspend external bus activity, to request a retry when used with BERR, or to perform a singlestep operation. As an output, HALT indicates a double bus fault by the CPU32+.
2.1.9.4 BUS ERROR (BERR). This active-low, open-drain, bidirectional signal indicates
that an invalid bus operation is being attempted or, when used with HALT, that the bus master should retry the current cycle.
2.1.10 Clock Signals
These signals are used by the QUICC for controlling or generating the system clocks. Refer
to Section 6 System Integration Module (SIM60) for more information on these clock signals.
2.1.10.1 SYSTEM CLOCK OUTPUTS (CLKO2–CLKO1). These output signals reflect the
general system clock and are used as the bus timing reference by external devices. CLKO1
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Signal Descriptions
is the general system clock. CLKO2 is 2× CLKO1 if the on-chip clock synthesizer PLL is
used, and is 1× CLKO1 otherwise.
2.1.10.2 CRYSTAL OSCILLATOR (EXTAL, XTAL). These two pins are the connections
for an external crystal to the internal oscillator circuit. If an external oscillator is used, it
should be connected to EXTAL, with XTAL left open.
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2.1.10.3 EXTERNAL FILTER CAPACITOR (XFC). This pin is used to add an external
capacitor to the filter circuit of the PLL. The capacitor should be connected between XFC
and VCCSYN.
2.1.10.4 CLOCK MODE SELECT (MODCK1–MODCK0). The state of these active-high
input signals during reset selects the type of external clock that is used by the PLL in the
clock synthesizer to generate the system clocks. Table 2-5 lists the default values of the
PLL.
Table 2-5. Default Operation Mode of the PLL
MODCK
1–0
PLL
Prescaled by
128
Multi. Factor
(MF + 1)
EXTAL Freq.
(examples)
CLKIN to the
PLL
Initial Freq.
(VCO/2)
001
Disabled
Reserved
Reserved
Reserved
Reserved
Reserved
01
Enabled
No
1
>10 MHz
=EXTAL
=EXTAL
10
Enabled
Yes
401
4.192 MHz
32.75 kHz
13.14 MHz
11
Enabled
No
401
32.768 kHz
32.768 kHz
13.14 MHz
1This mode is reserved.
2.1.11 Instrumentation and Emulation Signals
These signals are used for test or software debugging. Refer to Section 5 CPU32+ for more
information on these signals.
2.1.11.1 INSTRUCTION FETCH/DEVELOPMENT SERIAL INPUT (IFETCH/DSI). This
active-low output signal indicates when the CPU32+ is performing an instruction word
prefetch and when the instruction pipeline has been flushed. Additionally, this signal is the
serial input to the CPU32+ in its background debug mode to issue background commands,
etc.
2.1.11.2 INSTRUCTION PIPE/DEVELOPMENT SERIAL OUTPUT (IPIPE0/DSO). This
active-low output signal is used to track movement of words through the instruction pipeline.
Additionally, this signal is the serial output from the CPU32+ in its background debug mode
to issue background status, etc.
2.1.11.3 INSTRUCTION PIPE/ROW ADDRESS SELECT DOUBLE-DRIVE (IPIPE1/
RAS1DD). This active-low output signal is used to track movement of words through the
instruction pipeline. This signal also functions as a second output of the RAS1 signal to
increase fanout capability.
2.1.11.4 BREAKPOINT/DEVELOPMENT SERIAL CLOCK (BKPT/DSCLK). This activelow input signal is used to signal a hardware breakpoint to the CPU32+. Additionally, this
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signal is the serial clock used to transfer commands/status to and from the CPU32+ during
background debug mode.
2.1.11.5 FREEZE/INITIAL CONFIGURATION (FREEZE/CONFIG2). This pin can be programmed as the freeze output or as the initial configuration pin 2 input signal during system
reset.
FREEZE—Assertion of this active-high output signal indicates that the CPU32+ has
acknowledged a breakpoint and has initiated background mode operation.
CONFIG2—See 2.1.13 Initial Configuration Pins (CONFIG) for the description.
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2.1.12 Test Signals
The following signals are used with the on-board test logic . See Section 8 Scan Chain Test
Access Port for more information on the use of these signals.
2.1.12.1 TRI-STATE SIGNAL (TRIS). TThe TRIS pin is enabled as a tristate control pin
only when the CPU32+ is enabled, and it is not sampled during reset. When asserted, TRIS
immediately tristates the pins.
2.1.12.2 TEST RESET (TRST). This input provides asynchronous reset to the test logic.
2.1.12.3 TEST CLOCK (TCK). This input provides a clock for on-board test logic.
2.1.12.4 TEST MODE SELECT (TMS). This input controls test mode operations for onboard test logic.
2.1.12.5 TEST DATA IN (TDI). This input is used for serial test instructions and test data
for on-board test logic.
2.1.12.6 TEST DATA OUT (TDO). This output is used for serial test instructions and test
data for on-board test logic.
2.1.13 Initial Configuration Pins (CONFIG)
The CONFIG2–CONFIG0 pins select the QUICC initial configuration during reset (see Table
2-6). They decide whether the CPU32+ core will be enabled or disabled, the global chip
select port will be 8-, 16-, or 32-bits, and the MBAR address will be $003FF00 or
$0033FF04. After reset, these pins may be programmed to their other function. The
CONFIG2–CONFIG0 lines have internal pullup resistors so that if they are left floating, the
default selection will be 111. See Section 6 System Integration Module (SIM60) for more
information.
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Table 2-6. Initial Configuration
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Configuration Pins
CONFIG2/
FREEZE
CONFIG1/
BCLRO
CONFIG0/
RMC
0
0
0
Slave mode; global CS 8-bit size; MBAR at $003FF00.
0
0
1
Slave mode; global CS 32-bit size; MBAR at $003FF00; not MC68040 companion mode; BR output, BG input.
0
1
0
Slave mode; global CS 16-bit size; MBAR at $003FF00.
0
1
1
MC68040 companion mode; global CS 32-bit size; MBAR at $003FF00; BR
input, BG output.
1
0
0
CPU enabled; global CS 32-bit size; MBAR at $003FF00.
1
0
1
CPU enabled; global CS 16-bit size; MBAR at $003FF00.
1
1
0
Slave mode; global CS disabled; MBAR at $003FF04.
1
1
1
CPU enabled; global CS 8-bit size; MBAR at $003FF00. (Default)
Result
NOTE
All CONFIG pins do have an internal pull-up resistor during reset. If a configuration other than the default (CONFIG2-1 = 111)
is desired, these pins should be driven by an active open collector device during the assertion of RESETH.
2.1.14 Power Signals
The following signals are used for power and ground to the QUICC.
2.1.14.1 VCCSYN AND GNDSYN. These pins provide power and ground to the clock synthesizer. They should be bypassed to each other with a 0.1-µF capacitor. See the system
clock generation description in Section 6 System Integration Module (SIM60) for more
details.
2.1.14.2 VCCCLK AND GNDCLK. These pins provide power and ground to the clock output pins (CLKO1 and CLKO2). They should be bypassed to each other with a 0.1-µF capacitor. See the system clock generation description in Section 6 System Integration Module
(SIM60) for more detail.
2.1.14.3 GNDS1 AND GNDS2. These two pins are special ground pins that, if used properly, allow more aggressive timing to be provided on certain system bus pins. These pins
include AS, CASx, and IPIPE. Section 10 Electrical Characteristics already shows the
aggressive timing; the user does not need to modify any values in the section. GNDS1 and
GNDS2 should be connected to a quiet ground source or to a low-noise ground plane.
2.1.14.4 VCC AND GND. These pins are the rest of the power and ground connections for
the QUICC.
2.1.14.5 NC4–NC1. These four pins should not be connected on the QUICC package. They
are reserved for future enhancements.
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Signal Descriptions
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2.2 SYSTEM BUS SIGNAL INDEX IN SLAVE MODE
The CONFIG2–CONFIG0 pins are used to cause the QUICC to enter the slave mode. The
signal name, mnemonic, and a brief functional description are presented in Table 2-7. The
rest of the QUICC pins maintain their functionality in slave mode. See Section 4 Bus Operation for details.
Additionally, the QUICC provides special support for the MC68EC040 bus (or other
MC68040 family members) during slave mode. The MC68EC040 signals are marked in
boldface in the table. For more information on MC68EC040 bus operation, see M68040UM/
AD, M68040 User's Manual. The QUICC MC68EC040 support is described in Section 4 Bus
Operation and Section 6 System Integration Module (SIM60).
Freescale Semiconductor, Inc...
Table 2-7. System Bus Signal Index (Slave Mode)
Master Mode
Mnemonic
Slave Mode
Signal Name
Slave Mode
Mnemonic
Slave Mode Function
FC2–FC0
Function Codes/
Transfer Modifier
FC2–FC0/
TM2–TM0
Identifies the processor state and the address space of the current bus cycle (I/O), or indicates the MC68EC040 supplement
information about the access (I).
FC3
Function Code/
Transfer Type
FC3/TT0
Identifies the DMA address space of the current bus cycle (I/O),
or indicates the MC68EC040 general transfer type: normal,
MOVE16, alternate logical function code, and acknowledge
(I).
DS
Data Strobe/
Transfer Type
DS/TT1
Data strobe (I/O), or indicates the MC68EC040 general transfer type: normal, MOVE16, alternate logical function code,
and acknowledge (I).
DSACK1
Data and Size Acknowledge/
Transfer Acknowledge
DSACK1/TA
Provides asynchronous data transfers and dynamic bus sizing;
for the MC68EC040, asserted to acknowledge bus transfer.
(Both are open-drain I/O but driven high before three-stated.)
DSACK0
Data and Size Acknowledge/
Transfer Burst Inhibit
DSACK0/
TBI
Provides asynchronous data transfers and dynamic bus sizing;
for the MC68EC040, indicates that a slave cannot handle a
line burst access. (Both are open-drain I/O but driven high before three-stated.)
BERR
Bus Error/
Transfer Error
Acknowledge
BERR/
TEA
BERR indicates an erroneous bus operation is being attempted
by the QUICC (open-drain I/O); TEA indicates the same for
the MC68EC040 (open-drain I/O)
TRIS
Transfer Start
TS
IPIPE0/IFETCH
Burst Address
BR
Bus Request
BR
BR
Asserted by the QUICC to request bus mastership (O.D. O), or
bus request input from the MC68040. (I)
BG
Bus Grant
BG
BG
Asserted by external logic to grant bus mastership to the QUICC
(I), or bus grant output to the MC68040. (O)
BGACK
Bus Grant Acknowledge
Bus Busy
BGACK
BB
Indicates that an external device or the QUICC has assumed
bus mastership. (Open-drain I/O but driven high before threestated).
RMC/CONFIG0
040 Lock Cycle/
Configuration 0
LOCK/
CONFIG0
An MC68040 LOCK signal input to prevent the QUICC from
obtaining the system bus during locked cycles (I), and the
initial QUICC configuration select (I).
BKPT
Breakpoint Out
BKPTO
FREEZE/
CONFIG2
Freeze/Initial
Configuration Pin 2
MBARE/
CONFIG2
IRQ1,4,6
Interrupt Request/
Interrupt Outputs
2-14
Indicates the beginning of an MC68040 bus transfer. (I)
lines 2,3 generated by the QUICC on behalf of the
BADD3–BADD2 Address
MC68EC040, for MC68EC040 burst memory cycles. (O)
Signals a hardware breakpoint to the external CPU. (O)
Provides an MBAR access enable (I), or the initial QUICC configuration select. (I)
Provides an interrupt request to the QUICC interrupt controller
IRQ6,4,1/
IOUT2–IOUT0/ (I), or interrupt output signals (O) (either RQOUT as a single reIRQOUT
quest or IOUT2–IOUT0 encoded).
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Signal Descriptions
Table 2-7. System Bus Signal Index (Slave Mode) (Continued)
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Master Mode
Mnemonic
Slave Mode
Signal Name
Slave Mode
Mnemonic
Slave Mode Function
PRTY0
Parity 0/Interrupt Out- PRTY0/IOUT2 Parity signals for D31–D24 writes/reads from/to external memput 2
ory bank (I/O), or interrupt output 2 signal (O).
PRTY1
Parity 1/Interrupt Out- PRTY1/IOUT1 Parity signals for D23–D16 writes/reads from/to external memory bank (I/O) or interrupt output 1 signal. (O)
put 1
signals for D15–D8 writes/reads from/to external memory
PRTY2/IOUT0/ Parity
bank (I/O), or interrupt output 0 signal (O), or RQOUT as a sinRQOUT
gle interrupt request output (O).
PRTY2
Parity 2/
Interrupt Output 0/
Request Output
AVEC/IACK5
Autovector Output
AVECO
Signal output to the external processor to generate an internal
vector number during an interrupt acknowledge cycle. (threestated O)
IPIPE1/
RAS1DD
Bus Clear Input/
Row Address Select 1
Double-Drive
BCLRI/
RAS1DD
Signals that an external device requests the QUICC to release
the external bus (I), or row address select 1 double-drive (O).
2.3 ON-CHIP PERIPHERALS SIGNAL INDEX
The input and output system signals for the QUICC peripherals are listed in Table 2-8. The
signal name, mnemonic, and a brief functional description are presented. For more detail on
each signal, refer to the specific module section. The peripherals pins are divided into three
ports: A, B, and C.
Port A has 16 pins, port B has 18 pins, and port C has 12 pins. All the following signals are
multiplexed with either port A, B, or C. All pins may be inputs or outputs; in addition, some
pins may be configured to be open-drain. See 7.14 Parallel I/O Ports for further details.
Table 2-8. Peripherals Signal Index
Group
Signal Name
Mnemonic
SCC
Receive Data
RXD4–RXD1
Serial receive data input to the SCCs. (I)
Transmit Data
TXD4–TXD1
Serial transmit data output from the SCCs. (O)
Request to Send
RTS4–RTS1
Request to send outputs indicate that the SCC is ready to transmit
data. (O)
Clear to Send
CTS4–CTS1
Clear to send inputs indicate to the SCC that data transmission may
begin. (I)
Carrier Detect
CD4–CD1
Carrier detect inputs indicate that the SCC should begin reception of
data. (I)
Receive Start
RSTRT1
This output from SCC1 identifies the start of a receive frame. Can be
used by an Ethernet CAM to perform address matching. (O)
Receive Reject
RRJCT1
This input to SCC1 allows a CAM to reject the current Ethernet frame
after it determines the frame address did not match. (I)
Clocks
CLK8–CLK1
Input clocks to the SCCs, SMCs, SI, and the baud rate generators. (I)
DMA Request
DREQ2–DREQ1
A request (input) to an IDMA channel to start an IDMA transfer. (I)
DMA Acknowledge
DACK2–DACK1
An acknowledgement (output) by the IDMA that an IDMA transfer is
in progress. (O)
DMA Done
DONE2–DONE1
A bidirectional signal that indicates the last IDMA transfer in a block
of data. (I/O)
IDMA
TIMER
Timer Gate
Timer Input
MOTOROLA
Function
TGATE2–TGATE1 An input to a timer that enables/disables the counting function. (I)
TIN4–TIN1
Time reference input to the timer that allows it to function as a
counter. (I)
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Signal Descriptions
Table 2-8. Peripherals Signal Index (Continued)
Group
SPI
SMC
Signal Name
Mnemonic
Function
Timer Output
TOUT4–TOUT1
Output waveform (pulse or toggle) from the timer as a result of a reference value being reached. (O)
SPI Master-In SlaveOut
SPIMISO
Serial data input to the SPI master (I); serial data output from an SPI
slave (O).
SPI Master-Out
Slave-In
SPIMOSI
Serial data output from the SPI master (O).; serial data input to an
SPI slave (I).
SPI Clock
SPICLK
Output clock from the SPI master (O); input clock to the SPI slave (I).
SPI Select
SPISEL
SPI slave select input. (I)
SMC Receive Data SMRXD2–SMRXD1 Serial data input to the SMCs. (I)
SMC Transmit Data SMTXD2–SMTXD1 Serial data output from the SMCs. (O)
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SMC Sync
SI
SMSYN2–SMSYN1 SMC synchronization signal. (I)
SI Receive Data
input to the time division multiplexed (TDM) channel A or
L1RXDA, L1RXDB Serial
channel B.
SI Transmit Data
L1TXDA, L1TXDB Serial output from the TDM channel A or channel B.
SI Receive Clock
L1RCLKA,
L1RCLKB
Input receive clock to TDM channel A or channel B.
SI Transmit Clock L1TCLKA, L1TCLKB Input transmit clock to TDM channel A or channel B.
BRG
PIP
SDMA
2-16
SI Transmit
Sync Signals
L1TSYNCA,
L1TSYNCB
Input transmit data sync signal to the TDM channel A or channel B.
SI Receive
Sync Signals
L1RSYNCA,
L1RSYNCB
Input receive data sync signal to TDM channel A or channel B.
IDL Interface Request
L1RQA, L1RQB
IDL interface request to transmit on the D channel. Output from the
SI.
SI Output Clock
L1CLKOA,
L1CLKOB
Output serial data rate clock. Can output a data rate clock when the
input clock is 2x the data rate.
SI Data Strobes
L1ST4– L1ST1
Serial data strobe outputs can be used to gate clocks to external devices that do not have a built-in time slot assigner (TSA).
Baud Rate Generator Out 4–1
rate generator output clock allows baud rate generator to be
BRGO4–BRGO1 Baud
used externally.
Baud rate generator input clock from which BRG will derive the baud
rates.
BRG Input Clock
CLK2, CLK6
Port B 15–0
PB15–PB0
Strobe Out
STRBO
This input causes the PIP output data to be placed on the PIP data
pins.
Strobe In
STRBI
This input causes data on the PIP data pins to be latched by the PIP
as input data.
SDMA Acknowledge 2–1
PIP Data I/O Pins
output signals used in RISC receiver to mark fields in the
SDACK2–SDACK1 SDMA
Ethernet receive frame.
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Signal Descriptions
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Signal Descriptions
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SECTION 3
QUICC MEMORY MAP
The following tables present a programmer’s model (register map) of all registers in the
QUICC. For more information about a particular register, refer to the description for the module or sub-module indicated in the right column. The address column indicates the offset of
the register from the address stored in the module base address register (MBAR). This register in the SIM block controls the location of all internal memory/registers as well as their
supervisor/user access space (see Section 6 System Integration Module (SIM60)). Bold letters mark registers that are restricted to supervisor access. Other registers are programmable to exist in either supervisor or user space. Registers that are reset only by hard reset are
marked with an H in the reset value column. All of the registers are memory-mapped.
All internal memory and registers occupy a single 8-Kbyte memory block that is relocatable
along 8-Kbyte boundaries. The location is fixed by writing the desired base address of the
8-Kbyte memory block to the MBAR using the MOVES instruction. The MBAR is the only
exception since it resides at a fixed location in $03FF00.
The 8-Kbyte block is divided into two 4-Kbyte sections. The RAM occupies the first section;
the internal registers occupy the second section. The location of the QUICC registers is
shown in Figure 3-1.
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Thi d
t
t d ith F
M k 404
3-1
QUICC Memory Map
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MBAR (SIM)
DPRBASE (DUAL-PORT RAM BASE)
DUAL-PORT RAM
4KB
REGB (REGISTER BASE) = DPRBASE + 4K
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4KB
INTERNAL
REGISTERS
Figure 3-1. QUICC Memory Map
3.1 DUAL-PORT RAM MEMORY MAP
The internal 2816-byte (2560-byte on REV A and B mask) dual-port RAM is partitioned to
1792 bytes (1536 bytes on REV A and B mask) of system RAM, 256-byte microcode scratch
area, and 768 bytes of parameter RAM (see Table 3-1). Its base address, called dual-port
RAM base (DPRBASE), is the address pointed to by the MBAR.
NOTE
Rev A mask is C63T, Rev B mask are C69T, and F35G
The system RAM may be used for microcode program area, data area, and buffer descriptors (BDs). It may be partitioned in several ways, allowing programmable partition sizes to
fit the system requirements. This is described in Section 7 Communication Processor Module (CPM).
3-2
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QUICC Memory Map
The parameter RAM contains the protocol-specific parameters. For detailed information
about the use of the buffer descriptors and protocol parameters in a specific protocol, see
Section 7 Communication Processor Module (CPM).
Table 3-1. Dual-Port RAM Map
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Address
Size
Block
Description
DPRBASE + 0
DPRBASE + 3FF
1024 Bytes
Dual-Port RAM
User Data / BDs /
Microcode Program
DPRBASE + 400
DPRBASE + 5FF
512 Bytes
Dual-Port RAM
User Data / BDs
DPRBASE + 600
DPRBASE + 6FF
256 Bytes
Dual-Port RAM
User Data / BDs /
Microcode Scratch
DPRBASE + 700
DPRBASE + BFF
256 Bytes
Dual-Port RAM
User Data / BDs
DPRBASE + C00
DPRBASE + CBF
192 Bytes
Dual-Port RAM
Parameter RAM
Page 1
Reserved
Reserved
Dual-Port RAM
Parameter RAM
Page 2
Reserved
Reserved
Dual-Port RAM
Parameter RAM
Page 3
Reserved
Reserved
Dual-Port RAM
Parameter RAM
Page 4
Reserved
Reserved
DPRBASE + CC0
DPRBASE + CFF
DPRBASE + D00
DPRBASE + DBF
192 Bytes
DPRBASE + DC0
DPRBASE + DFF
DPRBASE + E00
DPRBASE + EBF
192 Bytes
DPRBASE + EC0
DPRBASE + EFF
DPRBASE + F00
DPRBASE + FBF
DPRBASE + FC0
DPRBASE + FFF
192 Bytes
3.2 CPM SUB-MODULE BASE ADDRESSES
Within the four parameter RAM pages are the base addresses for the CPM sub-modules
such as the SCCs, SMCs, etc. The base addresses for the sub-modules are shown in Table
3-2. See the particular sub-module description within Section 7 Communication Processor
Module (CPM) for further information.
Table 3-2. CPM Sub-Module Base Addresses
MOTOROLA
Parameter
RAM Page
Sub-Module
Base Address
1
SCC1 Base
DPRBASE + $C00
1
Misc Base
DPRBASE + $CB0
2
SCC2 Base
DPRBASE + $D00
2
SPI Base
DPRBASE + $D80
2
Timer Base
DPRBASE + $DB0
3
SCC3 Base
DPRBASE + $E00
3
IDMA1 Base
DPRBASE + $E70
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Table 3-2. CPM Sub-Module Base Addresses
3
SMC1 Base
DPRBASE + $E80
4
SCC4 Base
DPRBASE + $F00
4
IDMA2 Base
DPRBASE + $F70
4
SMC2 Base
DPRBASE + $F80
3.3 INTERNAL REGISTERS MEMORY MAP
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In addition to the internal dual-port RAM, there are a number of internal registers to support
the functions of the various CPU32+ core peripherals. The internal registers (see Table 3-3
and Table 3-4) are memory-mapped registers offset from the register base (REGBASE)
pointer. REGBASE (abbreviated REGB) = DPRBASE + 4K. All registers are located on the
internal IMB.
NOTES
All registers that are underlined in the following tables are special registers called event registers. In these registers, bits are
set by the QUICC and cleared by the user. To clear a bit, the
user must write a one to that bit. For example, to clear bit 2 in
SCCE1, the MOVE.B #$04,SCCE1 instruction may be used. Do
NOT use read-modify-write instructions (such as BSET, BCLR,
AND, OR, etc.) with these registers, or ALL bits in that register
will inadvertently be cleared. See the individual register descriptions for more information.
All undefined and reserved bits within registers and parameter
RAM values written by the user should be written with zero to allow for future enhancements to the device.
Bold letters mark registers that are restricted to supervisor access.
3.3.1 SIM Registers Memory Map
Table 3-3 lists the SIM registers memory map.
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QUICC Memory Map
Table 3-3. QUICC SIM Registers Memory Map
Address
Name
Width
REGB + 0000
MCR
32
Module Configuration Register
32
Reserved
REGB + 0004
REGB + 0008
AVR
8
Autovector Register
REGB + 0009
RSR
8
Reset Status Register
16
Reserved
8
CLKO Control Register
REGB + 000a
REGB + 000c
CLKOCR
REGB + 000d
REGB + 0010
Reset Value
Block
0000 7cff
H
00
H
H/S
f(MODCK1)
H
PLLCR
16
PLL Control Register
f(MODCK1–0)
H
16
Reserved
REGB + 0014
CDVCR
16
Clock Divider Control Register
0000
H
REGB + 0016
PEPAR
16
Port E Pin Assignment Register
0000
H
REGB + 0018
to
REGB + 0021
Reserved
REGB + 0022
SYPCR
8
System Protection Control
f(MODCK1–0)
H
REGB + 0023
SWIV
8
Software Interrupt Vector
0F
H
16
Reserved
16
Periodic Interrupt Control Register
000F
H
16
Reserved
16
Periodic Interrupt Timing Register
0000/0300
H
24
Reserved
REGB + 0024
REGB + 0026
PICR
REGB + 0028
REGB + 002a
PITR
REGB + 002c
REGB + 002f
SWSR
8
Software Service Register
00
H
REGB + 0030
BKAR
32
Breakpoint Address Register
XXXX
—
REGB + 0034
BKCR
32
Breakpoint Control Register
0000 0000
H
REGB + 0038
to
REGB + 003f
Reserved
REGB + 0040
GMR
32
Global Memory Register
0000 1200
H
REGB + 0044
MSTAT
16
Memory Controller Status Register
0000
H
REGB + 0046
to
REGB + 004f
MEMC
Reserved
REGB + 0050
BR0
32
Base Register 0
0000 0051
H
REGB + 0054
OR0
32
Option Register 0
F000 0000
H
REGB + 0058
to
REGB + 005f
Reserved
REGB + 0060
BR1
32
Base Register 1
0000 0050
H
REGB + 0064
OR1
32
Option Register 1
F000 000x
H
REGB + 0068
to
REGB +006f
Reserved
REGB + 0070
BR2
32
Base Register 2
0000 0050
H
REGB + 0074
OR2
32
Option Register 2
F000 000x
H
MOTOROLA
SIM
Reserved
REGB + 0012
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QUICC Memory Map
Table 3-3. QUICC SIM Registers Memory Map
REGB + 0078
to
REGB + 007f
Reserved
REGB + 0080
BR3
32
Base Register 3
0000 0050
H
REGB + 0084
OR3
32
Option Register 3
F000 000x
H
REGB + 0088
to
REGB + 008f
Reserved
REGB + 0090
BR4
32
Base Address Register 4
0000 0050
H
REGB + 0094
OR4
32
Option Register 4
F000 000x
H
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REGB + 0098
to
REGB + 009f
Reserved
REGB + 00a0
BR5
32
Base Address Register 5
0000 0050
H
REGB + 00a4
OR5
32
Option Register 5
F000 000x
H
REGB + 00a8
to
REGB + 00af
Reserved
REGB + 00b0
BR6
32
Base Address Register 6
0000 0050
H
REGB + 00b4
OR6
32
Option Register 6
F000 000x
H
REGB + 00b8
to
REGB + 00bf
Reserved
REGB + 00c0
BR7
32
Base Address Register 7
0000 0050
H
REGB + 00c4
OR7
32
Option Register 7
F000 000x
H
REGB + 00c8
to
REGB + 00ef
Reserved
REGB + 00f0
to
REGB + 00ff
Reserved
3.3.2 CPM Registers Memory Map
Table 3-4 lists the CPM registers memory map.
Table 3-4. QUICC CPM Registers Memory Map
Address
Name
Width
REGB + 400
to
REGB + 4ff
REGB + 500
Reset Value
ICCR
CMR1
REGB + 506
16
Channel Configuration Register
16
Reserved
16
IDMA1 Mode Register
16
Reserved
0000
H
IDMA1
0000
REGB + 508
SAPR1
32
IDMA1 Source Address Pointer
0000 0000
REGB + 50C
DAPR1
32
IDMA1 Destination Address Pointer
0000 0000
REGB + 510
BCR1
32
IDMA1 Byte Count Register
0000 0000
REGB + 514
FCR1
8
IDMA1 Function Code Register
00
3-6
Block
Reserved
REGB + 502
REGB + 504
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QUICC Memory Map
Table 3-4. QUICC CPM Registers Memory Map
REGB + 515
REGB + 516
CMAR1
REGB + 517
REGB + 518
CSR1
REGB + 519
REGB + 51C
SDSR
REGB + 51D
Reserved
8
Channel Mask Register
8
Reserved
8
IDMA1 Channel Status Register
24
Reserved
8
SDMA Status Register
8
Reserved
00
00
00
REGB + 51E
SDCR
16
SDMA Configuration Register
0000
REGB + 520
SDAR
32
SDMA Address Register
XXXX XXXX
16
Reserved
REGB + 524
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8
CMR2
16
IDMA2 Mode Register
0000
REGB + 528
SAPR2
32
IDMA2 Source Address Pointer
0000 0000
REGB + 52C
DAPR2
32
IDMA2 Destination Address Pointer
0000 0000
REGB + 530
BCR2
32
IDMA2 Byte Count Register
0000 0000
REGB + 534
FCR2
8
IDMA2 Function Code Register
00
8
Reserved
8
Channel Mask Register
8
Reserved
8
IDMA2 Channel Status Register
REGB + 536
CMAR2
REGB + 537
REGB + 538
CSR2
REGB + 539
to
REGB + 53F
H
IDMA2
REGB + 526
REGB + 535
SDMA
00
00
Reserved
REGB + 540
CICR
24
CP Interrupt Configuration Register
xx00 0000
H
CPIC
REGB + 544
CIPR
32
CP Interrupt Pending Register
0000 0000
REGB + 548
CIMR
32
CP Interrupt Mask Register
0000 0000
REGB + 54C
CISR
32
CP In-Service Register
0000 0000
REGB + 550
PADIR
16
Port A Data Direction Register
0000
H
Parallel
I/O
REGB + 552
PAPAR
16
Port A Pin Assignment Register
0000
H
REGB + 554
PAODR
16
Port A Open Drain Register
0000
H
REGB + 556
PADAT
16
Port A Data Register
XXXX
REGB + 558
to
REGB + 55f
Reserved
REGB + 560
PCDIR
16
Port C Data Direction Register
0000
H
REGB + 562
PCPAR
16
Port C Pin Assignment Register
0000
H
REGB + 564
PCSO
16
Port C Special Options
0000
H
REGB + 566
PCDAT
16
Port C Data Register
XXXX
REGB + 568
PCINT
16
Port C Interrupt Control Register
0000
H
0000
H
REGB + 56a
to
REGB + 57f
REGB + 580
MOTOROLA
Reserved
TGCR
16
Timer Global Configuration Register
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QUICC Memory Map
Table 3-4. QUICC CPM Registers Memory Map
Freescale Semiconductor, Inc...
REGB + 582
to
REGB + 58f
Reserved
REGB + 590
TMR1
16
Timer1 Mode Register
0000
REGB + 592
TMR2
16
Timer2 Mode Register
0000
REGB + 594
TRR1
16
Timer1 Reference Register
FFFF
REGB + 596
TRR2
16
Timer2 Reference Register
FFFF
REGB + 598
TCR1
16
Timer1 Capture Register
0000
REGB + 59A
TCR2
16
Timer2 Capture Register
0000
REGB + 59C
TCN1
16
Timer1 Counter
0000
REGB + 59E
TCN2
16
Timer2 Counter
0000
REGB + 5A0
TMR3
16
Timer3 Mode Register
0000
REGB + 5A2
TMR4
16
Timer4 Mode Register
0000
REGB + 5A4
TRR3
16
Timer3 Reference Register
FFFF
REGB + 5A6
TRR4
16
Timer4 Reference Register
FFFF
REGB + 5A8
TCR3
16
Timer3 Capture Register
0000
REGB + 5AA
TCR4
16
Timer4 Capture Register
0000
REGB + 5AC
TCN3
16
Timer3 Counter
0000
REGB + 5AE
TCN4
16
Timer4 Counter
0000
REGB + 5B0
TER1
16
Timer1 Event Register
0000
REGB + 5B2
TER2
16
Timer2 Event Register
0000
REGB + 5B4
TER3
16
Timer3 Event Register
0000
REGB + 5B6
TER4
16
Timer4 Event Register
0000
REGB + 5b8
to
REGB + 5bf
Reserved
REGB + 5CO
CR
16
Command Register
0000
REGB + 5C4
RCCR
16
RISC Configuration Register
0000
REGB + 5c6
to
REGB + 5d5
CP
H
Reserved
REGB + 5D6
RTER
16
RISC Timers Event Register
0000
REGB + 5DA
RTMR
16
RISC Timers Mask Register
0000
REGB + 5dc
to
REGB + 5ef
Reserved
REGB + 5F0
BRGC1
24
BRG1 Configuration Register
xx00 0000
H
REGB + 5F4
BRGC2
24
BRG2 Configuration Register
xx00 0000
H
REGB + 5F8
BRGC3
24
BRG3 Configuration Register
xx00 0000
H
REGB + 5FC
BRGC4
24
BRG4 Configuration Register
xx00 0000
H
REGB + 600
GSMR_L1
32
SCC1 General Mode Register
0000 0000
REGB + 604
GSMR_H1
32
SCC1 General Mode Register
0000 0000
REGB + 608
PSMR1
16
SCC1 Protocol-Specific Mode Register
0000
REGB + 60c
TODR1
16
SCC1 Transmit on Demand
0000
3-8
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BRG
SCC1
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QUICC Memory Map
Table 3-4. QUICC CPM Registers Memory Map
REGB + 60e
DSR1
16
SCC1 Data Sync. Register
7E7E
REGB + 610
SCCE1
16
SCC1 Event Register
0000
REGB + 614
SCCM1
16
SCC1 Mask Register
0000
REGB + 617
SCCS1
8
SCC1 Status Register
00
Freescale Semiconductor, Inc...
REGB + 618
to
REGB + 61f
Reserved
REGB + 620
GSMR_L2
32
SCC2 General Mode Register
0000 0000
REGB + 624
GSMR_H2
32
SCC2 General Mode Register
0000 0000
REGB + 628
PSMR2
16
SCC2 Protocol-Specific Mode Register
0000
REGB + 62c
TODR2
16
SCC2 Transmit on Demand
0000
REGB + 62e
DSR2
16
SCC2 Data Sync. Register
7E7E
REGB + 630
SCCE2
16
SCC2 Event Register
0000
REGB + 634
SCCM2
16
SCC2 Mask Register
0000
REGB + 637
SCCS2
8
SCC2 Status Register
00
REGB + 638
to
REGB + 63f
Reserved
REGB + 640
GSMR_L3
32
SCC3 General Mode Register
0000 0000
REGB + 644
GSMR_H3
32
SCC3 General Mode Register
0000 0000
REGB + 648
PSMR3
16
SCC3 Protocol-Specific Mode Register
0000
REGB + 64c
TODR3
16
SCC3 Transmit on Demand
0000
REGB + 64e
DSR3
16
SCC3 Data Sync. Register
7E7E
REGB + 650
SCCE3
16
SCC3 Event Register
0000
REGB + 654
SCCM3
16
SCC3 Mask Register
0000
REGB + 657
SCCS3
8
SCC3 Status Register
00
REGB + 658
to
REGB + 65f
GSMR_L4
32
SCC4 General Mode Register
0000 0000
REGB + 664
GSMR_H4
32
SCC4 General Mode Register
0000 0000
REGB + 668
PSMR4
16
SCC4 Protocol-Specific Mode Register
0000
REGB + 66c
TODR4
16
SCC4 Transmit on Demand
0000
REGB + 66e
DSR4
16
SCC4 Data Sync. Register
7E7E
REGB + 670
SCCE4
16
SCC4 Event Register
0000
REGB + 674
SCCM4
16
SCC4 Mask Register
0000
REGB + 677
SCCS4
8
SCC4 Status Register
00
REGB + 678
to
REGB + 681
SCC4
Reserved
REGB + 682
SMCMR1
16
SMC1 Mode Register
0000
REGB + 686
SMCE1
8
SMC1 Event Register
00
REGB + 68a
SMCM1
8
SMC1 Mask Register
00
MOTOROLA
SCC3
Reserved
REGB + 660
REGB + 68C
SCC2
SMC1
Reserved
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QUICC Memory Map
Table 3-4. QUICC CPM Registers Memory Map
REGB + 692
SMCMR2
16
SMC2 Mode Register
0000
REGB + 696
SMCE2
8
SMC2 or PIP Event Register
00
REGB + 69a
SMCM2
8
SMC2 Mask Register
00
Freescale Semiconductor, Inc...
REGB + 69C
SMC2
Reserved
REGB + 6A0
SPMODE
16
SPI Mode Register
0000
REGB + 6A6
SPIE
8
SPI Event Register
00
REGB + 6AA
SPIM
8
SPI Mask Register
00
REGB + 6AD
SPCOM
8
SPI Command Register
00
REGB + 6B2
PIPC
16
PIP Configuration Register
0000
REGB + 6B6
PTPR
16
PIP Timing Parameters Register
0000
REGB + 6B8
PBDIR
18
Port B Data Direction Register
xxx0 0000
H
REGB + 6BC
PBPAR
18
Port B Pin Assignment Register
xxx0 0000
H
REGB + 6C2
PBODR
16
Port B Open Drain Register
0000
H
REGB + 6C4
PBDAT
18
Port B Data Register
xxxX XXXX
REGB + 6c8
to
REGB + 6df
H
SPI
H
PIP
Reserved
REGB + 6E0
SIMODE
32
SI Mode Register
0000 0000
H
REGB + 6E4
SIGMR
8
SI Global Mode Register
00
H
REGB + 6E6
SISTR
8
SI Status Register
00
H
REGB + 6E7
SICMR
8
SI Command Register
00
32
Reserved
REGB + 6E8
REGB+ 6EC
SICR
32
SI Clock Route
0000 0000
REGB + 6F2
SIRP
32
SI RAM Pointers
0000 0000
REGB + 6F6
to
REGB + 6FF
RES
Reserved
REGB + 700
to
REGB + 7ff
SIRAM
256
Bytes SI Routing RAM
SI
H
XXXX
Notes:
1.Reset value field.
2.H=Effected only upon RESETH assertion
3.S=Effected only upon RESETS assertion
4.Blank field = Effected by both RESETH or RESETS assertion.
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SECTION 4
BUS OPERATION
This section provides a functional description of the system bus, the signals that control it,
and the bus cycles provided for data transfer operations. It also describes the error and halt
conditions, bus arbitration, and reset operation. Operation of the external bus is the same
whether the QUICC or an external device is the bus master; the names and descriptions of
bus cycles are from the viewpoint of the bus master. For exact timing specifications, refer to
Section 10 Electrical Characteristics.
NOTE
The bus operation of the QUICC is very similar to the bus operation of the MC68030 and the MC68340. Much of the text and
figures of the bus operation of those devices is common to this
section.
The QUICC also supports the MC68EC040 (or other M68040 family members) as an external bus master. The MC68EC040 can access QUICC registers and use QUICC peripherals.
The QUICC has a glueless MC68EC040 interface and special logic for acting as the
MC68EC040 memory controller, interrupt controller, and the provider of system protection
logic. The MC68EC040 bus operation is described in the M68040 User Manual. When the
QUICC is the bus master of an M68040 system, its bus operation remains the same when
it is the only bus master in the system. See 4.6.7 Internal Accesses for a description and
timing diagram of the MC68EC040 internal read/write cycles (i.e., MC68EC040 reading/writing the QUICC) and interrupt acknowledge cycles. See 6.11 General-Purpose Chip-Select
Overview (SRAM Banks) and 6.12 DRAM Controller Overview (DRAM Banks) for more
information on the timing diagrams of MC68EC040 DRAM and SRAM accesses.
The QUICC architecture supports byte, word, and long-word operands allowing access to
8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by the size
outputs (SIZ1, SIZ0) and data size acknowledge inputs (DSACK1, DSACK0).
The QUICC allows byte, word, and long-word operands to be located in memory on any byte
boundary. For a misaligned transfer, more than one bus cycle may be required to complete
the transfer, regardless of port size. For a port less than 32 bits wide, multiple bus cycles
may be required for an operand transfer due to either misalignment or a port width smaller
than the operand size. Instruction words and their associated extension words must be
aligned on word boundaries. The user should be aware that misalignment of word or longword operands can cause the CPU32+ to perform multiple bus cycles for operand transfers;
therefore, processor performance is optimized if word and long-word memory operands are
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4-1
Bus Operation
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aligned on word or long-word boundaries, respectively. The QUICC IDMAs, when used,
reduce the misalignment overhead to a minimum.
4.1 BUS TRANSFER SIGNALS
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The bus transfers information between the QUICC and external memory or a peripheral
device. External devices can accept or provide 8, 16, or 32 bits in parallel and must follow
the handshake protocol described in this section. The maximum number of bits accepted or
provided during a bus transfer is defined as the port width. The QUICC contains an address
bus that specifies the address for the transfer and a data bus that transfers the data. Control
signals indicate the beginning and type of the cycle as well as the address space and size
of the transfer. The selected device then controls the length of the cycle with the signal(s)
used to terminate the cycle. Strobe signals, one for the address bus and another for the data
bus, indicate the validity of the address and provide timing information for the data.
Both asynchronous and synchronous operation is possible for any port width. In asynchronous operation, the bus and control input signals are internally synchronized to the QUICC
clock, introducing a delay. This delay is the time required for the QUICC to sample an input
signal, synchronize the input to the internal clocks, and determine whether it is high or low.
In synchronous mode, the bus and control input signals must be timed to setup and hold
times. Since no synchronization is needed, bus cycles can be completed in three clock
cycles in this mode. Additionally, using the fast-termination option of the chip-select signals,
two-clock operation is possible.
Furthermore, for all inputs, the QUICC latches the level of the input during a sample window
around the falling edge of the clock signal. This window is illustrated in Figure 4-1, where tsu
and th are the input setup and hold times, respectively. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample
window. If an input makes a transition during the window time period, the level recognized
by the QUICC is not predictable; however, the QUICC always resolves the latched level to
either a logic high or low before using it. In addition to meeting input setup and hold times
for deterministic operation, all input signals must obey the protocols described in this section.
t su
th
CLK
EXT
SAMPLE WINDOW
Figure 4-1. Input Sample Window
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Bus Operation
4.1.1 Bus Control Signals
The QUICC initiates a bus cycle by driving the address, size, function code, and read/write
outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with the FC signals. SIZ1
and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles). Table 4-3 lists the encoding of SIZ1 and SIZ0. These
signals are valid while AS is asserted.
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The R/W signal determines the direction of the transfer during a bus cycle. Driven at the
beginning of a bus cycle, R/W is valid while AS is asserted. R/W only transitions when a write
cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive
write cycles.
The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write
operation and remains asserted until completion of the final bus cycle of the operation.
4.1.2 Function Codes (FC3–FC0)
The FCx signals are outputs that indicate one of 16 address spaces to which the address
applies. Fifteen of these spaces are designated as either a normal or DMA cycle, user or
supervisor, and program or data spaces. One other address space is designated as CPU
space to allow the CPU32+ to acquire specific control information not normally associated
with read or write bus cycles. The FCx signals are valid while AS is asserted.
Function codes (see Table 4-1) can be considered as extensions of the 32-bit address that
can provide up to eight different 4-Gbyte address spaces. Function codes are automatically
generated by the CPU32+ to select address spaces for data and program at both user and
supervisor privilege levels, and a CPU address space for processor functions. User programs access only their own program and data areas to increase protection of system integrity and can be restricted from accessing other information. The S-bit in the CPU32+ status
register is set for supervisor accesses and cleared for user accesses to provide differentiation. Refer to 4.4 CPU Space Cycles for more information.
Table 4-1. Address Space Encoding
Function Code Bits
MOTOROLA
3
2
1
0
Address Spaces
0
0
0
0
Reserved (Motorola)
0
0
0
1
User Data Space
0
0
1
0
User Program Space
0
0
1
1
Reserved (User)
0
1
0
0
Reserved (Motorola)
0
1
0
1
Supervisor Data Space
0
1
1
0
Supervisor Program Space
0
1
1
1
Supervisor CPU Space
1
x
x
x
DMA space
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Bus Operation
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4.1.3 Address Bus (A31–A0)
The address bus signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The QUICC places the address on the bus
at the beginning of a bus cycle. The address is valid while AS is asserted.
4.1.4 Address Strobe (AS)
AS is an output timing signal that indicates the validity of an address on the address bus and
of many control signals. AS is asserted approximately one-half clock cycle after the beginning of a bus cycle.
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4.1.5 Data Bus (D31-D0)
The data bus is a bidirectional, nonmultiplexed, parallel bus that contains the data being
transferred to or from the QUICC. A read or write operation may transfer 8, 16, 24, or 32 bits
of data (one, two, three, or four bytes) in one bus cycle. During a read cycle, the data is
latched by the QUICC on the last falling edge of the clock for that bus cycle. For a write cycle,
all 32 bits of the data bus are driven, regardless of the port width or operand size. The
QUICC places the data on the data bus approximately one-half clock cycle after AS is
asserted in a write cycle.
4.1.6 Data Strobe (DS)
DS is an output timing signal that applies to the data bus. For a read cycle, the QUICC
asserts DS and AS simultaneously to signal the external device to place data on the bus.
For a write cycle, DS signals to the external device that the data to be written is valid. The
QUICC asserts DS approximately one clock cycle after the assertion of AS during a write
cycle.
4.1.7 Output Enable (OE)
OE is an output timing signal that applies to the data bus. On a read cycle, the QUICC
asserts OE to signal the external device to place data on the bus. OE is asserted during read
cycles with timing similar to AS.
OE is not shown in the diagrams in this section. Use AS timing instead during read cycles.
4.1.8 Byte Write Enable (WE0, WE1, WE2, WE3)
The upper upper write enable (WE0) indicates that the upper eight bits of the data bus (D31–
D24) contain valid data during a write cycle. The upper middle write enable (WE1) indicates
that the upper middle eight bits of the data bus (D23–D16) contain valid data during a write
cycle. The lower middle write enable (WE2) indicates that the lower middle eight bits of the
data bus (D15–D8) contain valid data during a write cycle. The lower write enable (WE3)
indicates that the lower eight bits of the data bus contain valid data during a write cycle.
4-4
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Bus Operation
The equations of the byte write enables for 32-bit port (16BM = 1) are as follows:
WE0 = R/W + AS + A0 + A1
WE1 = R/W + AS + not {(A1 * SIZ0) + (A0 * A1) + (A1 * SIZ1)}
WE2 = R/W + AS + not {(A0 * A1) + (A1 * SIZ0 * SIZ1) + (A1 * SIZ0 * SIZ1) +
(A0 * A1 * SIZ0)}
WE3 = R/W + AS + not {(A0 * SIZ0 * SIZ1) + (SIZ0 * SIZ1) + (A0 * A1) + (A1 *
SIZ1)}
These signals have the same timing as AS. The equations are valid only for a 32-bit port.
The equations of the byte write enables for 16-bit port (B16M = 0) are as follows:
Freescale Semiconductor, Inc...
WE0 = R/W + AS + A0
WE1 = R/W + AS + (A0 * SIZ0 * SIZ1)
These signals have the same timing as AS. The equations are valid only for a 16-bit port.
WEx signals are not shown in the diagrams in this section. Use AS timing instead during
write cycles. The particular WEx signals that are active in a given bus cycle depend on which
bytes are being written.
NOTE
Note that the WE signals are not affected by dynamic bus sizing.
External assertion of DSACKx will have no effect on which WEx
signal gets asserted.
When 16-bit mode is selected and Bit 7 of PEPAR is set, WE2
and WE3 are used as address lines A29 and A28 respectively.
4.1.9 Bus Cycle Termination Signals
The following signals can terminate a bus cycle.
4.1.9.1 DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACK1 AND DSACK0). During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol.
During a read cycle, this signals the QUICC to terminate the bus cycle and to latch the data.
During a write cycle, this indicates that the external device has successfully stored the data
and that the cycle may terminate. These signals also indicate to the QUICC the size of the
port for the bus cycle just completed (see Table 4-3). Refer to 4.3.1 Read Cycle for timing
relationships of DSACK1 and DSACK0.
Additionally, the system integration module (SIM60) can be programmed to internally generate DSACK1 and DSACK0 for external accesses, eliminating logic required to generate
these signals. The SIM60 can alternatively be programmed to generate a fast termination,
providing a two-cycle external access. Refer to 4.2.6 Fast Termination Cycles for additional
information on these cycles.
4.1.9.2 BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can
be used in the absence of DSACKx to indicate a bus error condition. BERR can also be
asserted in conjunction with DSACKx to indicate a bus error condition, provided it meets the
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Bus Operation
appropriate timing described in this section and in Section 10 Electrical Characteristics.
Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer
to 4.5 Bus Exception Control Cycles for additional information on the use of these signals.
See the memory controller description in Section 6 System Integration Module (SIM60) for
precautions about asserting BERR externally too early during DRAM and SRAM cycles controlled by the memory controller.
Freescale Semiconductor, Inc...
The internal bus monitor can be used to generate the BERR signal for internal and external
transfers in all the following descriptions.
4.1.9.3 AUTOVECTOR (AVEC). This signal can be used to terminate interrupt acknowledge cycles, indicating that the QUICC should internally generate a vector (autovector)
number to locate an interrupt handler routine. AVEC can be generated either externally or
internally by the SIM60 (refer to Section 6 System Integration Module (SIM60) for additional
information). AVEC is ignored during all other bus cycles.
4.2 DATA TRANSFER MECHANISM
The QUICC supports byte, word, and long-word operands, allowing access to 8-,16-, and
32-bit data ports through the use of asynchronous cycles controlled by DSACK1 and
DSACK0. The QUICC also supports byte, word, and long-word operands, allowing access
to 8-, 16, and 32-bit data ports through the use of synchronous cycles controlled by the fasttermination capability of the SIM60.
4.2.1 Dynamic Bus Sizing
The QUICC dynamically interprets the port size of the addressed device during each bus
cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. During an operand
transfer cycle, the slave device signals its port size (byte, word, or long word) and indicates
completion of the bus cycle to the QUICC through the use of the DSACKx inputs. Refer to
Table 4-2 for DSACKx encoding.
Table 4-2. DSACKx Encoding
DSACK1
DSACK0
Result
1
1
Insert Wait States in Current Bus Cycle
1
0
Complete Cycle—Data Bus Port Size is 8 Bits
0
1
Complete Cycle—Data Bus Port Size is 16 Bits
0
0
Complete Cycle—Data Bus Port Size is 32 Bits
For example, if the QUICC is executing an instruction that reads a long-word operand from
a long-word aligned address, it attempts to read 32 bits during the first bus cycle. (Refer to
4.2.2 Misaligned Operands for the case of a word or byte address.) If the port responds that
it is 32 bits wide, the QUICC latches all 32 bits of data and continues with the next operation.
If the port responds that it is 16 bits wide, the QUICC latches the 16 bits of valid data and
runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar,
but requires four read cycles. The addressed device uses the DSACKx signals to indicate
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Bus Operation
the port width. For instance, a 32-bit device always returns DSACKx for a 32-bit port (regardless of whether the bus cycle is a byte, word, or long-word operation).
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Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a
particular port size be fixed. A 32-bit port must reside on data bus bits 0–31, a 16-bit port
must reside on data bus bits 16–32, and an 8-bit port must reside on data bus bits 24–31.
This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16bit ports and ensures that the QUICC correctly transfers valid data. The QUICC always
attempts to transfer the maximum amount of data on all bus cycles; for a long-word operation, it always assumes that the port is 32 bit wide when beginning the bus cycle.
The bytes of operands are designated as shown in Figure 4-2. The most significant byte of
a long-word operand is OP0, and OP3 is the least significant byte. The two bytes of a wordlength operand are OP2 (most significant) and OP3. The single byte of a byte-length operand is OP3. These designations are used in the figures and descriptions that follow.
31
LONG-WORD OPERAND
0
0P0
0P1
0P2
0P3
15
WORD OPERAND
0
0P2
0P3
7
BYTE OPERAND
0
0P3
Figure 4-2. Internal Operand Representation
Figure 4-3 shows the required organization of data ports on the QUICC bus for 8, 16, and
32-bit devices. The four bytes shown are connected through the internal data bus and data
multiplexer to the external data bus. This path is the means through which the QUICC supports dynamic bus sizing and operand misalignment. Refer to 4.2.2 Misaligned Operands
for the definition of misaligned operand. The data multiplexer establishes the necessary
connections for different combinations of address and data sizes.
The multiplexer takes the four bytes of the 32-bit bus and routes them to their required positions. For example, OP0 can be routed to D24–D31, as would be the normal case, or it can
be routed to any other byte position to support a misaligned transfer. The same is true for
any of the operand bytes. The positioning of bytes is determined by the size and address
outputs.
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Bus Operation
0P0
REGISTER
0P1
0
1
MULTIPLEXER
Freescale Semiconductor, Inc...
INCREASING
MEMORY
ADDRESSES
0P2
0P3
2
3
ROUTING AND DUPLICATION
EXTERNAL
DATA BUS
D31–D24
D23–D16
ADDRESS
xxxxxxxx0
BYTE 0
BYTE 1
xxxxxxxx0
BYTE 0
BYTE 1
2
BYTE 2
BYTE 3
xxxxxxxx0
BYTE 0
1
BYTE 1
2
BYTE 2
3
BYTE 3
D7–D0
D15–D8
BYTE 2
BYTE 3
INTERNAL TO
THE MC68360
EXTERNAL BUS
32-BIT PORT
16-BIT PORT
8-BIT PORT
Figure 4-3. QUICC Interface to Various Port Sizes
The SIZ0 and SIZ1 outputs indicate the remaining number of bytes to be transferred during
the current bus cycle (see Table 4-3).
Table 4-3. SIZx Encoding
SIZ1
SIZ0
Size
0
1
Byte
1
0
Word
1
1
3 Bytes
0
0
Long Word
The number of bytes transferred during a write or read bus cycle is equal to or less than the
size indicated by the SIZx outputs, depending on port width and operand alignment. For
example, during the first bus cycle of a long-word transfer to a word port, the SIZx outputs
indicate that four bytes are to be transferred, although only two bytes are moved on that bus
cycle.
A0 and A1 also affect operation of the data multiplexer. During an operand transfer, A2-A31
indicate the long-word base address of that portion of the operand to be accessed; A0 and
A1 indicate the byte offset from the base. Table 4-4 lists the encoding of A0 and A1 and the
corresponding byte offset from the long-word base.
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Bus Operation
Table 4-4. Address Offset Encoding
A1
A0
Offset
0
0
+0 Byte
0
1
+1 Byte
1
0
+2 Bytes
1
1
+3 Bytes
Table 4-5 lists the bytes required on the data bus for read cycles. The entries shown as OPx
are portions of the requested operand that are read during that bus cycle and are defined
by SIZ0, SIZ1, A0, and A1 for the bus cycle. Bytes labeled x are “don’t cares” and are not
required during that read cycle.
Freescale Semiconductor, Inc...
Table 4-5. Data Bus Requirements for Read Cycles
Transfer
Size
Size
Address
SIZ1 SIZ0
Byte
Word
3 Bytes
Long
Word
A1
A0
Long-Word Port
External Data Bytes Required
Word Port External
Data Bytes Required
D31:D24 D23:D16 D15:D8 D7:D0 D31:D24 D23:D16
Byte Port
External Data
Bytes Required
D31:D24
0
1
0
0
OP3
x
x
x
OP3
x
OP3
0
1
0
1
x
OP3
x
x
x
OP3
OP3
0
1
1
0
x
x
OP3
x
OP3
x
OP3
0
1
1
1
x
x
x
OP3
x
OP3
OP3
1
0
0
0
OP2
OP3
x
x
OP2
OP3
OP2
1
0
0
1
x
OP2
OP3
x
x
OP2
OP2
1
0
1
0
x
x
OP2
OP3
OP2
OP3
OP2
1
0
1
1
x
x
x
OP2
x
OP2
OP2
1
1
0
0
OP1
OP2
OP3
x
OP1
OP2
OP1
1
1
0
1
x
OP1
OP2
OP3
x
OP1
OP1
1
1
1
0
x
x
OP1
OP2
OP1
OP2
OP1
1
1
1
1
x
x
x
OP1
x
OP1
OP1
0
0
0
0
OP0
OP1
OP2
OP3
OP0
OP1
OP0
0
0
0
1
x
OP0
OP1
OP2
x
OP0
OP0
0
0
1
0
x
x
OP0
OP1
OP0
OP1
OP0
0
0
1
1
x
x
x
OP0
x
OP0
OP0
Table 4-6 lists the combinations of SIZ0, SIZ1, A0, and A1 and the corresponding pattern of
the data transfer for write cycles from the internal multiplexer of the QUICC to the external
data bus. Bytes labeled x are “don't care.”
Figure 4-4 shows the transfer of a long-word operand to a word port. In the first bus cycle,
the QUICC places the four operand bytes on the external bus. Since the address is longword aligned in this example, the multiplexer follows the pattern in the entry of Table 4-6 corresponding to SIZ0, SIZ1, A0, A1 = 0000. The port latches the data on bits D16–D31 of the
data bus, asserts DSACK1 (DSACK0 remains negated), and the QUICC terminates the bus
cycle. It then starts a new bus cycle with SIZ0, SIZ1, A0, A1 = 1010 to transfer the remaining
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Bus Operation
16 bits. SIZ0 and SIZ1 indicate that a word remains to be transferred; A0 and A1 indicate
that the word corresponds to an offset of two from the base address. The multiplexer follows
the pattern corresponding to this configuration of the size and address signals and places
the two least significant bytes of the long word on the word portion of the bus (D16–D31).
The bus cycle transfers the remaining bytes to the word-size port. Figure 4-5 shows the timing of the bus transfer signals for this operation.
Table 4-6. QUICC Internal to External Data Bus Multiplexer—Write Cycle
Transfer Size
Size
Freescale Semiconductor, Inc...
Byte
Word
3 Bytes
Long Word
Address
External Data Bus Connection
SIZ1
SIZ0
A1
A0
D31:D24
D23:D16
D15:D8
D7:D0
0
1
0
0
OP3
x
x
x
0
1
0
1
OP3
OP3
x
x
0
1
1
0
OP3
x
OP3
x
0
1
1
1
OP3
OP3
x
OP3
1
0
0
0
OP2
OP3
x
x
1
0
0
1
OP2
OP2
OP3
x
1
0
1
0
OP2
OP3
OP2
OP3
1
0
1
1
OP2
OP2
x
OP2
1
1
0
0
OP1
OP2
OP3
x
1
1
0
1
OP1
OP1
OP2
OP3
1
1
1
0
OP1
OP2
OP1
OP2
1
1
1
1
OP1
x
OP2
OP1
0
0
0
0
OP0
OP1
OP2
OP3
0
0
0
1
OP0
OP0
OP1
OP2
0
0
1
0
OP0
OP1
OP0
OP1
0
0
1
1
OP0
OP0
x
OP0
31
LONG-WORD OPERAND
0P0
0P1
D31
DATA BUS
0
0P2
0P3
D16
WORD MEMORY
MC68360
MSB
LSB
SIZ1
0P0
0P1
0
0
0P3
1
0
0P2
SIZ0
A1
MEMORY CONTROL
A0
DSACK1
DSACK0
0
0
L
H
1
0
L
H
Figure 4-4. Example of Long-Word Transfer to Word Port
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S0
S2
S4
S0
S2
Bus Operation
S4
CLKO1
A31–A2
A1
A0
FC3–FC0
SIZ1
Freescale Semiconductor, Inc...
SIZ0
R/W
AS
DS
DSACK1
DSACK0
D31–D24
0P0
0P2
D23–D16
0P1
0P3
WORD WRITE
WORD WRITE
LONG-WORD OPERAND WRITE TO 16-BIT PORT
Figure 4-5. Long-Word Operand Write Timing (16-Bit Data Port)
Figure 4-6 shows a word transfer to an 8-bit bus port. Like the preceding example, this
example requires two bus cycles. Each bus cycle transfers a single byte. The size signals
for the first cycle specify two bytes; for the second cycle, they specify one byte. Figure 4-7
shows the associated bus transfer signal timing.
4.2.2 Misaligned Operands
Since operands may reside at any byte boundaries, they may be misaligned. A byte operand
is properly aligned at any address; a word operand is misaligned at an odd address; a long
word is misaligned at an address that is not evenly divisible by four. The MC68302,
MC68000/MC68008, MC68010, and MC68340 implementations allow long-word transfers
on odd-word boundaries but force exceptions if word or long-word operand transfers are
attempted at odd-byte addresses. Although the QUICC does not enforce any alignment
restrictions for data operands (including PC relative data addresses), some performance
degradation occurs when additional bus cycles are required for long-word or word operands
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Bus Operation
that are misaligned. For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries.
Attempting to prefetch an instruction word at an odd address causes an address error
exception.
15
WORD OPERAND
0P2
0
0P3
D31 DATA BUS D24
Freescale Semiconductor, Inc...
BYTE MEMORY
MC68360
MEMORY CONTROL
SIZ1
1
SIZ0
0
A1
0
A0
DSACK1
DSACK0
0P2
0
H
L
0P3
0
1
0
1
H
L
Figure 4-6. Example of Word Transfer to Byte Port
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S0
S2
S4
S0
S2
Bus Operation
S4
CLKO1
A31–A2
A1
A0
FC3–FC0
SIZ1
Freescale Semiconductor, Inc...
SIZ0
R/W
AS
DS
DSACK1
DSACK0
D31–D24
OP2
OP3
D23–D16
OP3
OP3
D15–D8
OP2
OP3
D7–D0
OP3
OP3
BYTE WRITE
BYTE WRITE
WORD OPERAND WRITE
Figure 4-7. Word Operand Write Timing (8-Bit Data Port)
Figure 4-8 shows the transfer of a long-word operand to an odd address in word-organized
memory, which requires three bus cycles. For the first cycle, the SIZx signals specify a longword transfer, and the address offset (A2–A0) is 001. Since the port width is 16 bits, only the
first byte of the long word is transferred. The slave device latches the byte and acknowledges the data transfer, indicating that the port is 16 bits wide. When the processor starts
the second cycle, the SIZx signals specify that three bytes remain to be transferred with an
address offset (A2–A0) of 010. The next two bytes are transferred during this cycle. The processor then initiates the third cycle, with the SIZx signals indicating one byte remaining to
be transferred. The address offset (A2–A0) is now 100; the port latches the final byte, and
the operation is complete. Figure 4-9 shows the associated bus transfer signal timing.
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Bus Operation
31
LONG-WORD OPERAND
0P0
0P1
DATA BUS
D31
0
0P2
0P3
D16
Freescale Semiconductor, Inc...
WORD MEMORY
MC68360
MEMORY CONTROL
MSB
LSB
SIZ1
SIZ0
A2
A1
A0
DSACK1
DSACK0
XXX
0P0
0
0
0
0
1
L
H
0P1
0P2
1
1
0
1
0
L
H
OP3
XXX
0
1
1
0
0
L
H
Figure 4-8. Misaligned Long-Word Transfer to Word Port Example
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S0
S2
S4
S0
S2
S4
S0
Bus Operation
S2
S4
CLKO1
A31–A2
A1
A0
FC3–FC0
Freescale Semiconductor, Inc...
SIZ1
SIZ0
R/W
AS
DS
DSACK1
DSACK0
D31–D24
0P0
0P1
0P3
D23–D16
0P0
0P2
0P3
D15–D8
0P1
0P1
0P3
D7–D0
0P2
0P2
0P3
BYTE WRITE
WORD WRITE
BYTE WRITE
LONG-WORD OPERAND WRITE
Figure 4-9. Misaligned Long-Word Transfer to Word Port Timing
Figure 4-10 and Figure 4-11 show a word transfer to an odd address in word-organized
memory. This example is similar to the one shown in Figure 4-8 and Figure 4-9 except that
the operand is word sized and the transfer requires only two bus cycles.
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Bus Operation
WORD OPERAND
15
OP2
0
OP3
D31
DATA BUS
D16
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WORD MEMORY
MC68360
SIZ1 SIZ0
MSB
LSB
XXX
0P2
1
0P3
XXX
0
MEMORY CONTROL
A2
A1 A0
DSACK1
DSACK0
0
0
0
1
0
1
1
L
H
0
L
H
Figure 4-10. Misaligned Word Transfer to Word Port Example
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S0
S2
S4
S0
Bus Operation
S4
S2
CLKO1
A31–A2
A1
A0
FC3–FC0
Freescale Semiconductor, Inc...
SIZ1
SIZ0
R/W
AS
DS
DSACK1
DSACK0
D31–D24
0P2
0P3
D23–D16
0P2
0P3
D15–D8
0P3
0P3
D7–D0
0P2
0P3
WORD WRITE
BYTE WRITE
WORD OPERAND WRITE TO A1/A0 = 01
Figure 4-11. Misaligned Word Transfer to Word Port Timing
Figure 4-12 and Figure 4-13 show an example of a long-word transfer to an odd address in
long-word-organized memory. In this example, a long-word access is attempted beginning
at the least significant byte of a long-word-organized memory. Only one byte can be transferred in the first bus cycle. The second bus cycle then consists of a three-byte access to a
long-word boundary. Since the memory is long-word organized, no further bus cycles are
necessary.
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Bus Operation
LONG-WORD OPERAND
15
0P0
0P2
0P1
D31
0
0P3
D0
DATA BUS
Freescale Semiconductor, Inc...
LONG-WORD MEMORY
MC68EC030
MEMORY CONTROL
MSB
UMB
LMB
LSB
A2
A1 A0
DSACK1
DSACK0
XXX
XXX
0P0
0P0
0
0
0
1
1
L
L
0P1
0P2
0P3
XXX
1
1
1
0
0
L
L
SIZ1 SIZ0
Figure 4-12. Misaligned Long-Word Transfer to Long-Word Port Example
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S0
S2
S4
S0
S2
Bus Operation
S4
CLKO1
A31–A2
A1
A0
FC2–FC0
Freescale Semiconductor, Inc...
SIZ1
SIZ0
R/W
AS
DS
DSACK1
DSACK0
D31–D24
0P0
0P1
D23–D16
0P0
0P2
D15–D8
0P1
0P3
D7–D0
0P0
0P1
BYTE WRITE
3-BYTE WRITE
LONG-WORD OPERAND WRITE
Figure 4-13. Misaligned Long-Word Transfer to Long-Word Port Timing
4.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment
The combination of operand size, operand alignment, and port size determines the number
of bus cycles required to perform a particular memory access. Table 4-7 lists the number of
bus cycles required for different operand sizes to different port sizes with all possible alignment conditions for write cycles and read cycles.
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Bus Operation
Table 4-7. Memory Alignment and Port Size Influence
on Write Bus Cycles
Number of Bus Cycles
A1–A0
00
01
10
11
Instruction1
1:2:4
N/A
N/A
N/A
Byte Operand
1:1:1
1:1:1
1:1:1
1:1:1
Word Operand
1:1:2
1:2:2
1:1:2
2:2:2
Long-Word Operand
1:2:4
2:3:4
2:2:4
2:3:4
Freescale Semiconductor, Inc...
Notes:
1. Data Port Size—32 Bits:16 Bits:8 Bits
2. Instruction reads can either be two words from an
even-word boundary, or one word from an odd-word boundary.
This table verifies that bus cycle throughput is significantly affected by port size and alignment. The QUICC system designer and programmer should be aware of and account for
these effects, particularly in time-critical applications.
If the required instruction begins at an even-word boundary, the processor prefetches a long
word (up to two instructions) by reading a long word from a long-word address (A1–A0 = 00),
regardless of port size. When the required instruction begins at an odd-word boundary, the
processor reads 16-bits only, from the odd-word boundary. Refer to Section 5 CPU32+ for
a complete description of the pipeline operation.
4.2.4 Bus Operation
The QUICC bus is asynchronous, allowing external devices connected to the bus to operate
at clock frequencies different from the clock for the QUICC. Bus operation uses the handshake lines (AS, DS, DSACK1, DSACK0, BERR, and HALT) to control data transfers. AS
signals a valid address on the address bus, and DS is used as a condition for valid data on
a write cycle. Decoding the SIZx outputs and lower address lines (A1–A0) provides strobes
that select the active portion of the data bus. The slave device (memory or peripheral)
responds by placing the requested data on the correct portion of the data bus for a read
cycle or by latching the data on a write cycle; the slave asserts the DSACK1/DSACK0 combination that corresponds to the port size to terminate the cycle.
Alternatively, the SIM60 can be programmed to assert the DSACK1/DSACK0 combination
internally and respond for the slave. If no slave responds or the access is invalid, external
control logic may assert BERR or BERR with HALT to abort or retry the bus cycle, respectively. DSACKx can be asserted before the data from a slave device is valid on a read cycle.
The length of time that DSACKx may precede data must not exceed a specified value in any
asynchronous system to ensure that valid data is latched into the QUICC. (See Section 10
Electrical Characteristics for timing parameters.)
Note that no maximum time is specified from the assertion of AS to the assertion of
DSACKx. Although the QUICC can transfer data in a minimum of three clock cycles when
the cycle is terminated with DSACKx, the QUICC inserts wait cycles in clock-period increments until DSACKx is recognized. BERR and/or HALT can be asserted after DSACKx is
asserted. BERR and/or HALT must be asserted within the time specified after DSACKx is
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Bus Operation
asserted in any asynchronous system. If this maximum delay time is violated, the QUICC
may exhibit erratic behavior.
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4.2.5 Synchronous Operation with DSACKx
Although cycles terminated with DSACKx are classified as asynchronous, cycles terminated
with DSACKx can also operate synchronously in that signals are interpreted relative to clock
edges. The devices that use these cycles must synchronize the response to the QUICC
clock (CLKO1) to be synchronous. Since the devices terminate bus cycles with DSACKx,
the dynamic bus sizing capabilities of the QUICC are available. The minimum cycle time for
these cycles is also three clocks. To support systems that use the system clock to generate
DSACKx and other asynchronous inputs, the asynchronous input setup time and the asynchronous input hold time are given. If the setup and hold times are met for the assertion or
negation of a signal, such as DSACKx, the QUICC is guaranteed to recognize that signal
level on that specific falling edge of the system clock. If the assertion of DSACKx is recognized on a particular falling edge of the clock, valid data is latched into the QUICC (for a read
cycle) on the next falling clock edge if the data meets the data setup time. In this case, the
parameter for asynchronous operation can be ignored. The timing parameters are described
in Section 10 Electrical Characteristics.
If a system asserts DSACKx for the required window around the falling edge of S2 and
obeys the proper bus protocol by maintaining DSACKx (and/or BERR/HALT) until and
throughout the clock edge that negates AS (with the appropriate asynchronous input hold
time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles
terminated with DSACKx (three clocks per cycle). When BERR (or BERR and HALT) is
asserted after DSACKx, BERR (and HALT) must meet the appropriate setup time prior to
the falling clock edge one clock cycle after DSACKx is recognized. This setup time is critical,
and the QUICC may exhibit erratic behavior if it is violated. When operating synchronously,
the data-in setup and hold times for synchronous cycles may be used instead of the timing
requirements for data relative to DS.
4.2.6 Fast Termination Cycles
With an external device that has a fast access time, the memory controller circuits can provide a two-clock external bus transfer. Since the memory controller circuits are driven from
the system clock, the bus cycle termination is inherently synchronized with the system clock.
Refer to Section 6 System Integration Module (SIM60) for more information on chip selects
and the DRAM controller. To use the fast termination (cycle length is two clocks) option, an
external device should be fast enough to have data ready, within the specified setup time,
by the falling edge of S4. Figure 4-14 shows the DSACKx timing for a read with two wait
states, followed by a fast termination read and write.
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Bus Operation
S0 S1 S2 S3 SW SW* SW SW* S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0
CLKO1
AS
DS
R/W
DSACKx
Freescale Semiconductor, Inc...
D31–D0
TWO WAIT STATES IN READ
FAST
TERMINATION
READ
FAST
TERMINATION
WRITE
* DSACKx only internally asserted for fast termination cycles.
Figure 4-14. Fast Termination Timing
NOTES
When using the fast termination option (cycle length is two
clocks), DS is asserted only in a read cycle, not in a write cycle.
DSACKx is only internally asserted for fast termination cycles.
4.3 DATA TRANSFER CYCLES
The transfer of data between the QUICC and other devices involves the following signals:
• Address Bus A31–A0
• Data Bus D31–D0
• Control Signals
The address and data buses are both parallel, nonmultiplexed buses. The bus master
moves data on the bus by issuing control signals, and the bus uses a handshake protocol
to ensure correct movement of the data. In all bus cycles, the bus master is responsible for
deskewing all signals it issues at both the start and end of the cycle. In addition, the bus master is responsible for deskewing the acknowledge and data signals from the slave devices.
The following paragraphs define read, write, and read-modify-write cycle operations. Each
bus cycle is defined as a succession of states that apply to the bus operation. These states
are different from the QUICC states described for the CPU32+. The clock cycles used in the
descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states.
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Bus Operation
4.3.1 Read Cycle
During a read cycle, the QUICC receives data from a memory or peripheral device. If the
instruction specifies a long-word operation, the QUICC attempts to read four bytes at once.
For a word operation, the QUICC attempts to read two bytes at once. For a byte operation,
the QUICC reads one byte. The section of the data bus from which each byte is read
depends on the operand size, address signals (A1, A0), and the port size. Refer to 4.2.1
Dynamic Bus Sizing and 4.2.2 Misaligned Operands for more information.
Figure 4-15 shows a long-word read cycle flowchart and Figure 4-16 illustrates a byte read
cycle flowchart. Figure 4-17 and Figure 4-18 show functional read cycles timing diagrams
specified in terms of clock periods.
Freescale Semiconductor, Inc...
BUS MASTER
SLAVE
ADDRESS DEVICE
1)
2)
3)
4)
5)
SET R/W TO READ
DRIVE ADDRESS ON A31–A0
DRIVE FUNCTION CODE ON FC3–FC0
DRIVE SIZx PINS FOR FOUR BTYES
ASSERT AS, OE AND DS
ACQUIRE DATA
1) LATCH DATA
2) NEGATE AS, OE AND DS
START NEXT CYCLE
PRESENT DATA
1) DECODE ADDRESS
2) PLACE DATA ON D31–D0
3) DRIVE DSACKx SIGNALS
TERMINATE CYCLE
1) REMOVE DATA FROM D31–D0
2) NEGATE DSACKx
Figure 4-15. Long-Word Read Cycle Flowchart
BUS MASTER
EXTERNAL DEVICE
ADDRESS DEVICE
1)
2)
3)
4)
5)
SET R/W TO READ
DRIVE ADDRESS ON A31–A0
DRIVE FUNCTION CODE ON FC3–FC0
DRIVE SIZE (SIZ1–SIZ0) (ONE BYTE)
ASSERT AS, DS, AND OE
PRESENT DATA
1) DECODE ADDRESS
2) PLACE DATA ON D31–D24, OR D23–16, OR
D15–D8, OR D7–D0.
3) ASSERT DSACKx
TERMINATE OUTPUT TRANSFER
1) LATCH DATA
2) NEGATE AS, DS, AND OE
TERMINATE CYCLE
START NEXT CYCLE
1) REMOVE DATA FROM D31–D0
2) NEGATE DSACKx
Figure 4-16. Byte Read Cycle Flowchart
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Bus Operation
S0
S2
S4
S0
S2
S4
S0
S2
S4
CLKO1
A31–A2
A1
A0
FC3–FC0
SIZ1
BYTE
Freescale Semiconductor, Inc...
WORD
SIZ0
R/W
AS
OE
DS
DSACK1
DSACK0
D31–D24
0P2
D23–D16
0P3
D15–D8
0P3
D7–D0
0P3
WORD READ
BYTE READ
BYTE READ
Figure 4-17. Byte and Word Read Cycles—32-Bit Port Timing
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S0
S2
S4
S0
S4
S2
S0
Bus Operation
S2
S4
CLKO1
A31–A2
A1
A0
FC3–FC0
Freescale Semiconductor, Inc...
SIZ1
LONG WORD
WORD
LONG WORD
SIZ0
R/W
AS
OE
DS
DSACK1
DSACK0
D31–D24
0P0
0P2
0P0
D23–D16
0P1
0P3
0P1
D15–D8
0P2
D7–D0
0P3
WORD READ
WORD READ
LONG-WORD READ
FROM 32-BIT PORT
LONG-WORD OPERAND READ FROM 16-BIT PORT
Figure 4-18. Long-Word Read—16-Bit and 32-Bit Port Timing
State 0—The read cycle starts in state 0 (S0). During S0, the QUICC places a valid address
on A31–A0 and valid function codes on FC3–FC0. The function codes select the address
space for the cycle. The QUICC drives R/W high for a read cycle. SIZ1 and SIZ0 become
valid, indicating the number of bytes requested for transfer.
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Bus Operation
State 1—One-half clock later, in state 1 (S1), the QUICC asserts AS indicating a valid
address on the address bus. The QUICC also asserts DS and OE during S1. The selected
device uses R/W, SIZ1 or SIZ0, A0, A1, DS, and OE to place its information on the data bus.
Any or all of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are selected by SIZ1,
SIZ0, A1, and A0. Concurrently, the selected device asserts DSACKx.
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State 2—As long as at least one of the DSACKx signals is recognized on the falling edge of
S2 (meeting the asynchronous input setup time requirement), data is latched on the falling
edge of S4, and the cycle terminates.
State 3—If DSACKx is not recognized by the start of state 3 (S3), the QUICC inserts wait
states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both
DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and
hold times around the end of S2. If wait states are added, the QUICC continues to sample
DSACKx on the falling edges of the clock until one is recognized.
State 4—At the falling edge of state 4 (S4), the QUICC latches the incoming data and samples DSACKx to get the port size.
State 5—The QUICC negates AS, DS, and OE during state 5 (S5). It holds the address valid
during S5 to provide address hold time for memory systems. R/W, SIZ1, SIZ0, and FC3–
FC0 also remain valid throughout S5. The external device keeps its data and DSACKx signals asserted until it detects the negation of AS, DS, or OE (whichever it detects first). The
device must remove its data and negate DSACKx within approximately one clock period
after sensing the negation of AS, DS, or OE. DSACKx signals that remain asserted beyond
this limit may be prematurely detected for the next bus cycle.
4.3.2 Write Cycle
During a write cycle, the QUICC transfers data to memory or a peripheral device. Figure 419 is a flowchart of a write cycle operation for a long-word transfer. Figure 4-20 shows the
functional write cycle timing diagram specified in clock periods for two write cycles (between
two read cycles with no idle time) for a 32-bit port.
PROCESSOR
EXTERNAL DEVICE
ADDRESS DEVICE
1)
2)
3)
4)
5)
6)
7)
SET R/W TO WRITE
DRIVE ADDRESS ON A31–A0
DRIVE FUNCTION CODE ON FC3–FC0
DRIVE SIZE (SIZ1–SIZ0)
ASSERT ADDRESS STROBE (AS) AND WEx
DRIVE DATA LINES D31–D0
ASSERT DATA STROBE (DS)
ACQUIRE DATA
1) NEGATE AS AND DS AND WEx
2) REMOVE DATA FROM D31–D0
PRESENT DATA
1) DECODE ADDRESS
2) PLACE DATA ON D31–D0
3) ASSERT DATA TRANSFER AND SIZE
ACKNOWLEDGE (DSACKx)
TERMINATE CYCLE
1) NEGATE DSACKx
START NEXT CYCLE
Figure 4-19. Write Cycle Flowchart
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S0
S2
S4
S0
S2
S4
S0
S2
S4
S0
S2
Bus Operation
Sw
Sw
S4
CLKO1
A31–A2
A1
A0
FC3–FC0
Freescale Semiconductor, Inc...
SIZ1
LONG WORD
SIZ0
R/W
AS
DS
DSACK1
DSACK0
D31–D0
READ
WRITE
WRITE
READ WITH WAIT STATES
NOTE: WE3–WE0 is not shown.
Figure 4-20. Read-Write-Read Cycles—32-Bit Port
State 0—The write cycle starts in S0. During S0, the QUICC places a valid address on A31–
A0 and valid function codes on FC3–FC0. The function codes select the address space for
the cycle. The QUICC drives R/W low for a write cycle. SIZ1 and SIZ0 become valid, indicating the number of bytes to be transferred.
State 1—One-half clock later during S1, the QUICC asserts AS, indicating a valid address
on the address bus. During this state, any or all of the byte write enables (WE0, WE1, WE2,
and WE3) are asserted simultaneously with AS.
State 2—During S2, the QUICC places the data to be written onto D31–D0 and samples
DSACKx at the end of S2.
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State 3—The QUICC asserts DS during S3, indicating that data is stable on the data bus.
As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the
asynchronous input setup time requirement), the cycle terminates one clock later. If
DSACKx is not recognized by the start of S3, the QUICC inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0
must remain negated throughout the asynchronous input setup and hold times around the
end of S2. If wait states are added, the QUICC continues to sample DSACKx on the falling
edges of the clock until one is recognized. The selected device uses the four write enables
lines or R/W, SIZ1, SIZ0, A1, and A0 to latch data from the appropriate byte(s) of the data
bus (D31–D24, D23–D16, D15–D8, and D7–D0). WE3–WE0 or SIZ1, SIZ0, A1, and A0
select the bytes of the data bus. If it has not already done so, the device asserts DSACKx
to signal that it has successfully stored the data.
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State 4—The QUICC issues no new control signals during S4.
State 5—The QUICC negates WE3–WE0, AS, and DS during S5. It holds the address and
data valid during S5 to provide address hold time for memory systems. R/W, SIZ1, SIZ0,
and FC3–FC0 also remain valid throughout S5. The external device must keep DSACKx
asserted until it detects the negation of AS or DS (whichever it detects first). The device must
negate DSACKx within approximately one clock period after sensing the negation of AS or
DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected
for the next bus cycle.
4.3.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the QUICC, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire readmodify-write sequence, the QUICC asserts RMC to indicate that an indivisible operation is
occurring. The QUICC does not issue a bus grant (BG) signal in response to a bus request
(BR) signal during this operation. Figure 4-21 is an example of a functional timing diagram
of a read-modify-write instruction specified in terms of clock periods.
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S0
S2
S0
S4
S2
S4
Bus Operation
S0
CLK O1
A31–A0
FC3–FC0
SIZ1–SIZ0
R/W
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RMC
AS
DS
DSACKx
D31–D0
READ
WRITE
INDIVISIBLE
CYCLE
NOTE: OE and WE3–WE0 are not shown.
Figure 4-21. Read-Modify-Write Cycle Timing
State 0—The QUICC asserts RMC in S0 to identify a read-modify-write cycle. The QUICC
places a valid address on A31–A0 and valid function codes on FC3–FC0. The function
codes select the address space for the operation. SIZ1 and SIZ0 become valid in S0 to indicate the operand size. The QUICC drives R/W high for the read cycle.
State 1—One-half clock later in S1, the QUICC asserts AS, indicating a valid address on the
address bus. The QUICC also asserts OE and DS during S1.
State 2—The selected device uses OE, R/W, SIZ1, SIZ0, A0, and DS to place information
on the data bus. Any of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are selected
by SIZ1, SIZ0, A1, and A0. Concurrently, the selected device may assert DSACKx.
State 3—As long as at least one of the DSACKx signals is recognized by the end of S2
(meeting the asynchronous input setup time requirement), data is latched on the next falling
edge of the clock, and the cycle terminates. If DSACKx is not recognized by the start of S3,
the QUICC inserts wait states instead of proceeding to S4 and S5. To ensure that wait states
are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchro-
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Bus Operation
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nous input setup and hold times around the end of S2. If wait states are added, the QUICC
continues to sample DSACKx on the falling edges of the clock until one is recognized.
State 4—At the end of S4, the QUICC latches the incoming data.
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State 5—The QUICC negates OE, AS, and DS during S5. If more than one read cycle is
required to read in the operand(s), S0–S5 are repeated for each read cycle. When finished
reading, the QUICC holds the address, R/W, and FC3–FC0 valid in preparation for the write
portion of the cycle. The external device keeps its data and DSACKx signals asserted until
it detects the negation of AS or DS (whichever it detects first). The device must remove the
data and negate DSACKx within approximately one clock period after sensing the negation
of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely
detected for the next portion of the operation.
Idle States—The QUICC does not assert any new control signals during the idle states, but
it may internally begin the modify portion of the cycle at this time. S0–S5 are omitted if no
write cycle is required. If a write cycle is required, R/W remains in the read mode until S0 to
prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven
until S2.
State 0—The QUICC drives R/W low for a write cycle. Depending on the write operation to
be performed, the address lines may change during S0.
State 1—In S1, the QUICC asserts AS, indicating a valid address on the address bus. During this state, WE0, WE1, WE2, and/or WE3 assert simultaneously with AS.
State 2—During S2, the QUICC places the data to be written onto D31–D0.
State 3—The QUICC asserts DS during S3, indicating stable data on the data bus. As long
as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACKx is
not recognized by the start of S3, the QUICC inserts wait states instead of proceeding to S4
and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain
negated throughout the asynchronous input setup and hold times around the end of S2. If
wait states are added, the QUICC continues to sample DSACKx on the falling edges of the
clock until one is recognized. The selected device uses WE3–WE0 or R/W, DS, SIZ1, SIZ0,
A1, and A0 to latch data from the appropriate section(s) of the data bus (D31–D24, D23–
D16, D15–D8, and D7–D0). WE3–WE0 or SIZ1, SIZ0, A1, and A0 select the data bus sections. If it has not already done so, the device asserts DSACKx when it has successfully
stored the data.
State 4—The QUICC issues no new control signals during S4.
State 5—The QUICC negates WE3–WE0, AS, and DS during S5. It holds the address and
data valid during S5 to provide address hold time for memory systems. R/W and FC3–FC0
also remain valid throughout S5. If more than one write cycle is required, S0–S5 are
repeated for each write cycle. The external device keeps DSACKx asserted until it detects
the negation of AS or DS (whichever it detects first). The device must remove its data and
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Bus Operation
negate DSACKx within approximately one clock period after sensing the negation of AS or
DS.
4.4 CPU SPACE CYCLES
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FC2–FC0 select user and supervisor program and data areas. The area selected by function
code FC3–FC0 = $7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP
broadcast, module base address register access, and interrupt acknowledge cycles
described in the following paragraphs use CPU space. The CPU space type, which is
encoded on A19–A16 during a CPU space operation, indicates the function that the QUICC
is performing. On the QUICC, four of the encodings are implemented as shown in Figure 422. All unused values are reserved by Motorola for additional CPU space types.
CPU SPACE CYCLES
ADDRESS BUS
FUNCTION
CODE
BREAKPOINT
ACKNOWLEDGE
LOW-POWER
STOP BROADCAST
MODULE BASE
ADDRESS
REGISTER ACCESS
INTERRUPT
ACKNOWLEDGE
3
0
0 1 1 1
19
16
0
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0
3
0
0 1 1 1
19
16
0
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
3
0
0 1 1 1
31
19
0
16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
3
31
0
19
16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
0
0 1 1 1
CPU SPACE
TYPE FIELD
Figure 4-22. CPU Space Address Encoding
4.4.1 Breakpoint Acknowledge Cycle
The breakpoint acknowledge cycle allows external hardware to insert an instruction directly
into the instruction pipeline as the program executes. The breakpoint acknowledge cycle is
generated by the execution of the BKPT instruction, the internal breakpoint logic, or the
assertion of the BKPT pin. The T-bit state (shown in Figure 4-22) differentiates a software
breakpoint cycle (T = 0) from a hardware breakpoint cycle (T = 1).
When a software BKPT is executed, the QUICC performs a word read from CPU space, type
0, at an address corresponding to the breakpoint number (bits [2–0] of the BKPT opcode)
on A4–A2, and the T-bit (A1) is cleared. If this bus cycle is terminated with BERR (i.e., no
instruction word is available), the QUICC then performs illegal instruction exception processing. If the bus cycle is terminated by DSACKx, the QUICC uses the data on the bus to
replace the BKPT instruction in the internal instruction pipeline and then begins execution
of that instruction.
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Bus Operation
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When the CPU32+ acknowledges hardware breakpoint (BKPT pin assertion or internal
breakpoint logic) with background mode disabled, the CPU32+ performs a word read from
CPU space, type 0, at an address corresponding to all ones on A4–A2 (BKPT#7), and the
T-bit (A1) is set. If this bus cycle is terminated by BERR, the QUICC performs hardware
breakpoint exception processing. If this bus cycle is terminated by DSACKx, the QUICC
ignores data on the data bus and continues execution of the next instruction.
Freescale Semiconductor, Inc...
NOTE
The BKPT pin is sampled on the same clock phase as data and
is latched with data as it enters the CPU32+ pipeline. If BKPT is
asserted for only one bus cycle and a pipeline flush occurs before BKPT is detected by the CPU32+, BKPT is ignored. To ensure detection of BKPT by the CPU32+, BKPT can be asserted
until a breakpoint acknowledge cycle is recognized.
When the QUICC is configured for a 32-bit bus, the CPU32+ can
fetch two instructions simultaneously. Since there is only one
BKPT pin, the external user cannot break individually on those
instructions, but rather must break on both, causing the BKPT
exception to be taken after the first instruction and before the
second instruction. The internal breakpoint logic, however, can
individually assert a breakpoint for either instruction. (See the
BKAR and BKCR discussion in Section 6 System Integration
Module (SIM60) for details).
The breakpoint operation flowchart is shown in Figure 4-23. Figure 4-24 and Figure 4-25
show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes
supplied on the cycle and with an exception signaled, respectively.
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PROCESSOR
Bus Operation
EXTERNAL DEVICE
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BREAKPOINT ACKNOWLEDGE
IF BREAKPOINT INSTRUCTION EXECUTED:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON A19–A16
4) PLACE BREAKPOINT NUMBER ON A4–A2
5) CLEAR T-BIT (A1)
6) SET SIZx TO WORD
7) ASSERT AS AND DS
IF BKPT PIN OR INTERNAL LOGIC ASSERTED BKPT
INTERNALLY:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON A19–A16
4) PLACE ALL ONES ON A4–A2
5) SET T-BIT (A1) TO ONE
6) SET SIZx TO WORD
7) ASSERT AS AND DS
IF BREAKPOINT INSTRUCTION EXECUTED AND
DSACKx IS ASSERTED:
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO (A)
IF BKPT PIN ASSERTED AND DSACKx IS ASSERTED:
1) NEGATE AS AND DS
2) GO TO (A)
IF BERR ASSERTED:
1) NEGATE AS AND DS
2) GO TO (B)
(A)
IF BREAKPOINT INSTRUCTION EXECUTED:
1) PLACE REPLACEMENT OPCODE ON DATA BUS
2) ASSERT DSACKx
-OR1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
IF BKPT PIN ASSERTED:
1) ASSERT DSACKx
-OR1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
(B)
IF BREAKPOINT INSTRUCTION EXECUTED:
1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
2) CONTINUE PROCESSING
IF BKPT PIN ASSERTED:
1) CONTINUE PROCESSING
1) NEGATE DSACKx or BERR
IF BREAKPOINT INSTRUCTION EXECUTED:
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
IF BKPT PIN ASSERTED:
1) INITIATE HARDWARE BREAKPOINT PROCESSING
Figure 4-23. Breakpoint Operation Flowchart
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Bus Operation
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
CLKO1
A31–A20
A19–A16
BREAKPOINT ENCODING (0000)
A4–A1
BREAKPOINT NUMBER/T-BIT
A15–A5, A0
Freescale Semiconductor, Inc...
FC3–FC0
CPU SPACE
SIZ0
SIZ1
AS
DS
R/W
DSACKx
D23–D16
D31–D24
BERR
HALT
BKPT
BREAKPOINT
OCCURS
READ
BREAKPOINT
ACKNOWLEDGE
INSTRUCTION WORD FETCH
FETCHED
INSTRUCTION
EXECUTION
Figure 4-24. Breakpoint Acknowledge Cycle Timing (Opcode Returned)
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S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
S0
S1
S2
Bus Operation
S3
S4
S5
S0
CLKO1
A31–A20
BREAKPOINT ENCODING (0000)
A19–A16
BREAKPOINT NUMBER/T-BIT
A4–A1
Freescale Semiconductor, Inc...
A15–A5, A0
FC3–FC0
CPU SPACE
SIZ0
SIZ1
AS
DS
R/W
DSACKx
D23–D16
D31–D24
BERR
HALT
BKPT
BREAKPOINT
OCCURS
READ
BREAKPOINT
ACKNOWLEDGE
BUS ERROR ASSERTED
EXCEPTION
STACKING
Figure 4-25. Breakpoint Acknowledge Cycle Timing (Exception Signaled)
4.4.2 LPSTOP Broadcast Cycle
The LPSTOP broadcast cycle is generated by the CPU32+ executing the LPSTOP instruction. The external bus interface must get a copy of the interrupt mask level from the CPU32+,
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Bus Operation
so the CPU32+ performs a CPU space type 3 write with the interrupt mask level (I2–I0)
encoded on bits 2–0 of the data bus, as shown in the following figure. The CPU space type
3 cycle waits for the bus to be available, and is shown externally to indicate to external
devices that the QUICC is going into LPSTOP mode. If an external device requires additional time to prepare for entry into LPSTOP mode, entry can be delayed by asserting HALT.
The SIM60 provides internal DSACKx response to this cycle. For more information on how
the SIM60 responds to LPSTOP mode, see Section 6 System Integration Module (SIM60)
for details.
15
14
13
12
11
10
9
—
8
7
6
5
4
3
2
I2
1
I1
0
I0
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4.4.3 Module Base Address Register (MBAR) Access
All internal module registers, including the SIM60, occupy a single 8-kbyte block that is locatable along 8-kbyte boundaries. The location is fixed by writing the desired base address of
the SIM60 block to the MBAR using the MOVES instruction. The MBAR is only accessible
in CPU space at address $0003FF00. The SFC or DFC register must indicate CPU space
(FC2–FC0 = $7), using the MOVEC instruction, before accessing MBAR. Refer to Section
6 System Integration Module (SIM60) for additional information on the MBAR.
4.4.4 Interrupt Acknowledge Bus Cycles
The CPU32+ makes an interrupt pending in three cases. The first case occurs when a
peripheral device signals the CPU32+ (with the IRQ7–IRQ1 signals) that the device requires
service and the internally synchronized value on these signals indicates a higher priority
than the interrupt mask in the status register. The second case occurs when a transition has
occurred in the case of a level 7 interrupt. A recognized level 7 interrupt must be removed
for one clock cycle before a second level 7 can be recognized. The third case occurs if, upon
returning from servicing a level 7 interrupt, the request level stays at 7 and the processor
mask level changes from 7 to a lower level, a second level 7 is recognized. The CPU32+
takes an interrupt exception for a pending interrupt within one instruction boundary (after
processing any other pending exception with a higher priority). The following paragraphs
describe the various kinds of interrupt acknowledge bus cycles that can be executed as part
of interrupt exception processing.
4.4.4.1 INTERRUPT ACKNOWLEDGE CYCLE—TERMINATED NORMALLY. When the
CPU32+ processes an interrupt exception, it performs an interrupt acknowledge cycle to
obtain the number of the vector that contains the starting location of the interrupt service routine. Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt
acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply
a vector number and use the autovector cycle described in 4.4.4.2 Autovector Interrupt
Acknowledge Cycle.
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The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in
4.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences
are as follows:
1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space.
2. A3, A2, and A1 are set to the interrupt request level, and the IACKx strobe corresponding to the current interrupt level is asserted. (Either the function codes and address signals or the IACKx strobes can be monitored to determine that an interrupt
acknowledge cycle is in progress and the current interrupt level.)
3. The CPU32+ space type field (A19–A16) is set to $F (interrupt acknowledge).
4. Other address signals (A31–A20, A15–A4, and A0) are set to one.
Freescale Semiconductor, Inc...
The responding device places the vector number on the data bus during the interrupt
acknowledge cycle. Beyond this, the cycle is terminated normally with DSACKx.
Figure 4-26 is a flowchart of the interrupt acknowledge cycle; Figure 4-27 shows the timing
for an interrupt acknowledge cycle terminated with DSACKx.
INTERRUPTING DEVICE
QUICC
REQUEST INTERRUPT
GRANT INTERRUPT
PROVIDE VECTOR NUMBER
1) PLACE VECTOR NUMBER ON LEAST SIGNIFICANT
BYTE OF DATA PORT (DEPENDS ON
PORT SIZE)
2) ASSERT DSACKx (OR AVEC IF NO VECTOR
NUMBER)
RELEASE
1) SYNCHRONIZE IRQ7–IRQ1
2) COMPARE IRQ7–IRQ1 TO MASK LEVEL AND
WAIT FOR INSTRUCTION TO COMPLETE
3) ASSERT BCLRO
4) PLACE INTERRUPT LEVEL ON A1–A3;
TYPE FIELD (A19–A16) = $F
5) SET R/W TO READ
6) SET FC3–FC0 TO 0111
7) DRIVE SIZx PINS TO INDICATE A ONE-BYTE
TRANSFER
8) NEGATE BCLRO.
9) ASSERT AS, DS, AND OE
ACQUIRE VECTOR NUMBER
1) LATCH VECTOR NUMBER
2) NEGATE AS, DS, AND OE
1) NEGATE DSACKx
START NEXT CYCLE
Figure 4-26. Interrupt Acknowledge Cycle Flowchart
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Bus Operation
S0
S2
S4
S0
0–2 CLOCKS*
S1 S2
S4
S0
S2
CLKO1
A31–A4
A3–A1
INTERRUPT LEVEL
A0
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FC3–FC0
CPU SPACE
SIZ0
1 BYTE
SIZ1
R/W
AS
DS
DSACKx
VECTOR FROM 16-BIT PORT
D23–D16
VECTOR FROM 8-BIT PORT
D31–D24
IRQ7–IRQ1
IACK7–IACK1
READ
CYCLE
WRITE
STACK
INTERNAL
ARBITRATION
IACK CYCLE
* Internal arbitration may take between 0–2 clock cycles.
Figure 4-27. Interrupt Acknowledge Cycle Timing
4.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting
device cannot supply a vector number, it requests an automatically generated vector
(autovector). Instead of placing a vector number on the data bus and asserting DSACKx,
the device asserts AVEC to terminate the cycle. The DSACKx signals may not be asserted
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during an interrupt acknowledge cycle terminated by AVEC. The vector number supplied in
an autovector operation is derived from the interrupt level of the current interrupt. When the
AVEC signal is asserted instead of DSACKx during an interrupt acknowledge cycle, the
QUICC ignores the state of the data bus and internally generates the vector number (the
sum of the interrupt level plus 24 ($18)).
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AVEC is multiplexed with IACK5. The AVEC bit in the port E pin assignment register
(PEPAR) controls whether the AVEC/IACK5 pin is used as an autovector input or as IACK5
(see Section 6 System Integration Module (SIM60) for additional information). AVEC is only
sampled during an interrupt acknowledge cycle; during all other cycles, AVEC is ignored.
Additionally, AVEC can be internally generated for external devices by programming the
autovector register (note that in this case AVEC pin will not be asserted externally). Seven
distinct autovectors can be used, corresponding to the seven levels of interrupt available
with signals IRQ7–IRQ1. Figure 4-28 shows the timing for an autovector operation.
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S0
S2
S4
S0
0–2 CLOCKS*
S1 S2
S4
S0
S2
CLKO1
A31–A4
A3–A1
INTERRUPT LEVEL
A0
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FC3–FC0
CPU SPACE
SIZ0
1 BYTE
SIZ1
R/W
AS
DS
DSACKx
D31–D0
AVEC
IRQ7–IRQ1
IACK7–IACK1
READ
CYCLE
WRITE
STACK
INTERNAL
ARBITRATION
IACK CYCLE
* Internal Arbitration may take between 0–2 clock cycles.
Figure 4-28. Autovector Operation Timing
4.4.4.3 SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or external, are arbitrated internally. When no internal module (including the SIM60, which responds
for external requests) responds during an interrupt acknowledge cycle by arbitrating for the
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interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal
bus error signal to terminate the vector acquisition. The QUICC automatically generates the
spurious interrupt vector number, 24, instead of the interrupt vector number in this case.
When an external device does not respond to an interrupt acknowledge cycle with AVEC or
DSACKx, a bus monitor must assert BERR, which results in the CPU32+ taking the spurious
interrupt vector. If HALT is also asserted, the QUICC retries the interrupt acknowledge cycle
instead of using the spurious interrupt vector.
4.5 BUS EXCEPTION CONTROL CYCLES
The bus architecture requires assertion of DSACKx from an external device to signal that a
bus cycle is complete. Neither DSACKx nor AVEC is asserted in the following cases:
Freescale Semiconductor, Inc...
1. DSACKx in fast-termination cycles.
2. AVEC when programmed to respond internally.
3. The external device does not respond.
4. Various other application-dependent errors occur.
The QUICC provides BERR when no device responds by asserting DSACKx/AVEC within
an appropriate period of time after the QUICC asserts AS. This mechanism allows the cycle
to terminate and the QUICC to enter exception processing for the error condition. HALT is
also used for bus exception control. This signal can be asserted by an external device for
debugging purposes to cause single bus cycle operation or, in combination with BERR, a
retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus
error condition, DSACKx, BERR, and HALT can be asserted and negated with the rising
edge of the QUICC clock. This assures that when two signals are asserted simultaneously,
the required setup and hold time for both is met for the same falling edge of the QUICC
clock. This or an equivalent precaution should be designed into the external circuitry to provide these signals. Alternatively, the internal bus monitor could be used. The acceptable bus
cycle terminations for asynchronous cycles are summarized in relation to DSACKx assertion
as follows (case numbers refer to Table 4-8):
1. Normal Termination: DSACKx is asserted; BERR and HALT remain negated (case 1).
2. Halt Termination: HALT is asserted at the same time or before DSACKx, and BERR
remains negated (case 2).
3. Bus Error Termination: BERR is asserted in lieu of, at the same time, or before
DSACKx (case 3) or after DSACKx (case 4), and HALT remains negated; BERR is negated at the same time or after DSACKx.
4. Retry Termination: HALT and BERR are asserted in lieu of, at the same time, or before
DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the same time or after DSACKx, and HALT may be negated at the same time or after BERR.
Table 4-8 shows various combinations of control signal sequences and the resulting bus
cycle terminations. To ensure predictable operation, BERR and HALT should be negated
according to the specifications in Section 10 Electrical Characteristics. DSACKx, BERR, and
HALT may be negated after AS. If DSACKx or BERR remain asserted into S2 of the next
bus cycle, that cycle may be terminated prematurely.
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EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated
address space. The timer asserts BERR after timeout (case 3).
EXAMPLE B: A system uses error detection and correction on RAM contents. The designer
may:
1. Delay DSACKx until data is verified and assert BERR and HALT simultaneously to indicate to the QUICC to automatically retry the error cycle (case 5), or, if data is valid,
assert DSACKx (case 1).
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2. Delay DSACKx until data is verified and assert BERR with or without DSACKx if data
is in error (case 3). This initiates exception processing for software handling of the condition.
3. Return DSACKx prior to data verification; if data is invalid, BERR is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
4. Return DSACKx prior to data verification; if data is invalid, assert BERR and HALT on
the next clock cycle (case 6). The memory controller can then correct the RAM prior
to or during the automatic retry.
Table 4-8. DSACKx, BERR, and HALT Assertion Results
Case
Num
Control
Signal
1
Asserted on Rising
Edge of State
Result
N
N+2
DSACKx
BERR
HALT
A
NA
NA
S
NA
X
Normal cycle terminate and continue.
2
DSACKx
BERR
HALT
A
NA
A/S
S
NA
S
Normal cycle terminate and halt; continue when HALT negated.
3
DSACKx
BERR
HALT
NA/A
A
NA
X
S
NA
Terminate and take bus error exception, possibly deferred.
4
DSACKx
BERR
HALT
A
NA
NA
X
A
NA
Terminate and take bus error exception, possibly deferred.
5
DSACKx
BERR
HALT
NA/A
A
A/S
X
S
S
Terminate and retry when HALT negated.
6
DSACKx
BERR
HALT
A
NA
NA
X
A
A
Terminate and retry when HALT negated.
NOTES:
N —The number of current even bus state (e.g., S2, S4, etc.)
A —Signal is asserted in this bus state
NA —Signal is not asserted in this state
X —Don't care
S —Signal was asserted in previous state and remains asserted in this state
4.5.1 Bus Errors
BERR can be used to abort the bus cycle and the instruction being executed. BERR takes
precedence over DSACKx provided it meets the timing constraints described in Section 10
Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredict-
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Bus Operation
able operation of the QUICC. If BERR remains asserted into the next bus cycle, it may cause
incorrect operation of that cycle. When BERR is issued to terminate a bus cycle, the QUICC
may enter exception processing immediately following the bus cycle, or it may defer processing the exception.
The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them. If a bus error occurs on an instruction fetch, the QUICC does
not take the exception until it attempts to use that instruction word. Should an intervening
instruction cause a branch or should a task switch occur, the bus error exception does not
occur. The bus error condition is recognized during a bus cycle in any of the following cases:
1. DSACKx and HALT are negated, and BERR is asserted.
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2. HALT and BERR are negated, and DSACKx is asserted. BERR is then asserted within
one clock cycle (HALT remains negated).
When the QUICC recognizes a bus error condition, it terminates the current bus cycle in the
normal way. Figure 4-29 shows the timing of a bus error for the case in which DSACKx is
not asserted. Figure 4-30 shows the timing for a bus error that is asserted after DSACKx.
Exceptions are taken in both cases. (Refer to Section 5 CPU32+ for details of bus error
exception processing.)
S0
S2
SW
SW
S4
S0
S2
S4
CLKO1
A31–A0
FC3–FC0
R/W
AS
DS
DSACKx
D31–D0
BERR
READ CYCLE WITH BUS
ERROR
INTERNAL
PROCESSING
STACK
WRITE
Figure 4-29. Bus Error without DSACKx
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S0
S2
S4
S0
S2
S4
CLKO1
A31–A0
FC3–FC0
R/W
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AS
DS
DSACKx
D31–D0
BERR
WRITE
CYCLE
INTERNAL
PROCESSING
STACK
WRITE
Figure 4-30. Late Bus Error with DSACKx
In the second case, in which BERR is asserted after DSACKx is asserted, BERR must be
asserted within the time specified for purely asynchronous operation, or it must be asserted
and remain stable during the sample window around the next falling edge of the clock after
DSACKx is recognized. If BERR is not stable at this time, the QUICC may exhibit erratic
behavior. BERR has priority over DSACKx. In this case, data may be present on the bus but
may not be valid. This sequence can be used by systems that have memory error detection
and correction logic and by external cache memories.
4.5.2 Retry Operation
When both BERR and HALT are asserted by an external device during a bus cycle, the
QUICC enters the retry sequence shown in Figure 4-31. A delayed retry, which is similar to
the delayed bus error signal described previously, can also occur (see Figure 4-32). The
QUICC terminates the bus cycle, places the control signals in their inactive state, and does
not begin another bus cycle until the BERR and HALT signals are negated by external logic.
After a synchronization delay, the QUICC retries the previous cycle using the same access
information (address, function code, size, etc.). BERR should be negated before S2 of the
retried cycle to ensure correct operation of the retried cycle.
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S0
S2
SW
SW
S4
S0
S2
Bus Operation
S4
CLKO1
A31–A0
FC3–FC0
R/W
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AS
DS
DSACKx
D31–D0
DATA
IGNORED
BERR
HALT
HALT
READ CYCLE WITH
RETRY
READ RERUN
Figure 4-31. Retry Sequence
The QUICC retries any read or write cycle of a read-modify-write operation separately; RMC
remains asserted during the entire retry sequence.
Asserting BR at the same time as BERR and HALT provides a relinquish and retry operation. The QUICC does not relinquish the bus during a read-modify-write cycle, but may relinquish the bus between any other bus cycles. (i.e. relinquish-and-retry has priority over bus
coherency, except in the case of read-modify-write cycles). Any device that requires the
QUICC to give up the bus and retry a bus cycle during a read-modify-write cycle must assert
BERR and BR only (HALT must not be included). The bus error handler software should
examine the read-modify-write bit in the special status word (refer to Section 5 CPU32+) and
take the appropriate action to resolve this type of fault when it occurs.
NOTE
When the relinquish and retry is asserted during an internal master's word access to an 8-bit port, and the external master that
takes the bus performs an external-to-internal bus cycle, the en-
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tire word access will be retried. This is true even if the relinquish
and retry was asserted on the second access and the first 8-bit
access was completed normally.
S0
S2
S4
S0
S2
S4
CLKO1
A31–A0
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FC3–FC0
R/W
AS
DS
DSACKx
D31–D10
BERR
HALT
WRITE
CYCLE
HALT
WRITE
RERUN
Figure 4-32. Late Retry Sequence
4.5.3 Halt Operation
When HALT is asserted and BERR is not asserted, the QUICC halts external bus activity at
the next bus cycle boundary (see Figure 4-33). HALT by itself does not terminate a bus
cycle. HALT affects external bus cycles only; thus, a program that does not require use of
the external bus may continue executing until it requires use of the external bus.
Negating and reasserting HALT in accordance with the correct timing requirements provides
a single step (bus cycle to bus cycle) operation. The single-cycle mode allows the user to
proceed through (and debug) external QUICC operations, one bus cycle at a time. Since the
occurrence of a bus error while HALT is asserted causes a retry operation, the user must
anticipate retry cycles while debugging in the single-cycle mode. The single-step operation
and the software trace capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow.
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When the QUICC completes a bus cycle with HALT asserted, D31–D0 is placed in the highimpedance state, and bus control signals are driven inactive (not high-impedance state); the
address, function code, size, and read/write signals remain in the same state. The halt operation has no effect on bus arbitration (refer to 4.6 Bus Arbitration). When bus arbitration
occurs while the QUICC is halted, the address and control signals are also placed in the
high-impedance state. Once bus mastership is returned to the QUICC, if HALT is still
asserted, the address, function code, size, and read/write signals are again driven to their
previous states. The QUICC does not service interrupt requests while it is halted.
NOTES
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In Figure 4-33, note that BR is not asserted until after the halt operation is complete. If BR is asserted at the same time as HALT,
the user should note that the BG signal may not be asserted immediately (as in other M68000 family devices) but rather after
the full operand transfer is complete. This difference in behavior
is due to the coherency rules imposed by the QUICC and other
IMB-based M68300 family members. Refer to 4.6 Bus Arbitration for more details. To override the coherency rules, a relinquish and retry cycle may be used.
In the MCR of the SIM60, if the show cycles enable bits SHEN1SHEN0 = 1x to enable show cycles mode, and HALT is asserted
externally, the following behavior is possible. It is possible that
the QUICC may not show the last bus cycle externally, if that bus
cycle happens to be an internal-to-internal bus cycle. This is due
to a pipelining characteristic of the QUICC coupled with the
HALT signal being asserted late into an internal-to-external bus
cycle. Note that show cycles mode is not the normal configuration for the QUICC.
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S0
S2
S0
S4
S2
S4
S0
CLKO1
A31–A0
FC3–FC0
R/W
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AS
DS
DSACKx
D31–D0
HALT
BR
BG
BGACK
READ
HALT
(ARBITRATION PERMITTED
WHILE THE PROCESSOR IS
HALTED)
READ
Figure 4-33. HALT Timing
4.5.4 Double Bus Fault
A double bus fault results when a bus error or an address error occurs during the exception
processing sequence for any of the following:
1. A previous bus error
2. A previous address error
3. A reset
For example, the QUICC attempts to stack several words containing information about the
state of the machine while processing a bus error exception. If a bus error exception occurs
during the stacking operation, the second error is considered a double bus fault. When a
double bus fault occurs, the QUICC halts and drives the HALT line low. Only a reset operation can restart a halted QUICC. However, bus arbitration can still occur (refer to 4.6 Bus
Arbitration). A second bus error or address error that occurs after exception processing has
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completed (during execution of the exception handler routine or later) does not cause a double bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault. The QUICC continues to retry the same bus cycle as long as the external
hardware requests it.
Reset can also be generated internally by the halt monitor (see Section 5 CPU32+).
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4.6 BUS ARBITRATION
The bus design of the QUICC provides for a single bus master at any one time, either the
QUICC or an external device. One or more of the external devices on the bus can have the
capability of becoming bus master for the external bus and the QUICC internal bus. Bus
arbitration is the protocol by which an external device becomes bus master; the bus controller in the QUICC manages the bus arbitration signals so that the QUICC has the lowest priority.
NOTE
The QUICC may assert the BCLRO signal for one or more of its
internal bus masters, IDMA, SDMA, or DRAM refresh cycle, or
when an interrupt request is pending on a level that is greater
than a programmable level. The user can use BCLRO to negate
the BR line asserted by an external master to reduce the interrupt latency for programmable interrupt levels and to increase
the QUICC internal master arbitration priority over external masters.
External devices that need to obtain the bus must assert the bus arbitration signals in the
sequences described in the following paragraphs. Systems that include several devices that
can become bus master require external circuitry to assign priorities to the devices, so that
when two or more external devices attempt to become bus master at the same time, the one
having the highest priority becomes bus master first. The sequence of the protocol is as follows:
1. An external device asserts BR.
2. The QUICC asserts BG to indicate that the bus is available.
3. The external device asserts BGACK to indicate that it has assumed bus mastership.
BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to BR. To guarantee operand coherency, BG is only asserted at the end of an
operand transfer. (For example if any internal master such as the CPU, SDMA or IDMA on
the QUICC is writing a 32-bit operand to an 8-bit port size, BG is not asserted until the fourth
byte is written.) Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal. When the requesting device
receives BG and more than one external device can be bus master, the requesting device
should begin whatever arbitration is required. When it assumes bus mastership, the external
device asserts BGACK and maintains BGACK during the entire bus cycle (or cycles) for
which it is bus master. The following conditions must be met for an external device to
assume mastership of the bus through the normal bus arbitration procedure: it must have
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received BG through the arbitration process, and BGACK must be inactive, indicating that
no other bus master has claimed ownership of the bus.
Figure 4-34 is a flowchart showing the detail involved in bus arbitration for a single device.
This technique allows processing of bus requests during data transfer cycles.
QUICC
REQUESTING DEVICE
REQUEST THE BUS
GRANT BUS ARBITRATION
1) ASSERT BR
1) ASSERT BG
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ACKNOWLEDGE BUS MASTERSHIP
TERMINATE ARBITRATION
1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED
3) NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
RELEASE BUS MASTERSHIP
RE-ARBITRATE OR RESUME
PROCESSOR OPERATION
1) NEGATE BGACK
Figure 4-34. Bus Arbitration Flowchart for Single Request
The QUICC has a synchronous arbitration timing mode to reduce the BR to BG delay to one
clock in the idle bus case (see Figure 4-35). Figure 4-36 illustrates the active bus case.
BR is negated at the time that BGACK is asserted. This type of operation applies to a system
consisting of the QUICC and one device capable of bus mastership. In a system having a
number of devices capable of bus mastership, BR from each device can be wire-ORed to
the QUICC. In such a system, more than one bus request could be asserted simultaneously.
BG is negated a few clock cycles after the transition of BGACK. However, if bus requests
are still pending after the negation of BG, the QUICC asserts another BG within a few clock
cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus.
The following paragraphs provide additional information about the three steps in the arbitration process. Bus arbitration requests are recognized during normal processing, HALT
assertion, and when the CPU32+ has halted due to a double bus fault.
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CLKO1
A31–A0
D31–D0
AS
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DS
DSACK1–DSACK0
BR
BG
BGACK
NOTE:
BR has synchronous timing.
BR has asynchronous timing.
Figure 4-35. Bus Arbitration Timing Diagram—Idle Bus Case
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S0
S1
S2
S3
S4
S5
CLKO1
A31–A0
D31–D0
AS
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DS
R/W
DSACK1–DSACK0
BR (IN)
BG (OUT)
BGACK (IN)
NOTE:
BR has synchronous timing.
BR has synchronous timing.
Figure 4-36. Bus Arbitration Timing Diagram—Active Bus Case
4.6.1 Bus Request
External devices capable of becoming bus masters request the bus by asserting BR. This
signal can be wire-ORed to indicate to the QUICC that some external device requires control
of the bus. The QUICC is effectively at a lower bus priority level than the external device and
relinquishes the bus after it has completed the current bus cycle (if one has started). If no
BGACK is received while the BR is active, the QUICC remains bus master once BR is
negated. This prevents unnecessary interference with ordinary processing if the arbitration
circuitry inadvertently responds to noise or if an external device determines that it no longer
requires use of the bus before it has been granted mastership.
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Bus Operation
4.6.2 Bus Grant
The QUICC supports operand coherency; thus, if an operand transfer requires multiple bus
cycles, the QUICC does not release the bus until the entire transfer is complete. The assertion of BG is therefore subject to the following constraints:
• The minimum time for BG assertion after BR is asserted depends on internal synchronization.
• When working in synchronous mode (ASTM bit in the MCR is set), the minimum time
can be one clock.
Freescale Semiconductor, Inc...
• During an external operand transfer, the QUICC does not assert BG until after the last
cycle of the transfer (determined by SIZx and DSACKx).
• During an external operand transfer, the QUICC does not assert BG as long as RMC is
asserted.
• If the show cycle bits SHEN1–SHEN0 = 1x and if one of the QUICC internal masters is
making internal accesses, the QUICC does not assert BG until the transfer is terminated.
• If SHEN1–SHEN0 = 00 and if one of the QUICC internal masters is making internal accesses, the external bus is granted away, and the QUICC continues to execute internal
bus cycles. In this case, the arbitration overhead (external bus idle time) is minimal.
• If SHEN1–SHEN0 = 01, the QUICC does not assert BG to an external master.
Externally, the BG signal can be routed through a daisy-chained network or a priorityencoded network. The QUICC is not affected by the method of arbitration as long as the protocol is obeyed.
4.6.3 Bus Grant Acknowledge
An external device cannot request and be granted the external bus while another device is
the active bus master. A device that asserts BGACK remains the bus master until it negates
BGACK. BGACK should not be negated until all required bus cycles are completed. Bus
mastership is terminated at the negation of BGACK. When no other device requests the bus
after BGACK is negated, the QUICC will regain bus mastership.
The minimum time for the first bus cycle after BGACK negation depends on internal synchronization and internal bus arbitration. This timing is therefore subject to the following constraints:
• When working in synchronous mode (ASTM bit in the MCR is set) and SHEN0–SHEN1
= 00 and one of the QUICC internal masters requests an external accesses, the minimum time can be one clock.
• When working in asynchronous mode (ASTM bit in the MCR is cleared) and SHEN0–1
= 00 and one of the QUICC internal masters requests an external accesses, the minimum time depends on internal synchronization plus one clock.
• If SHEN1–SHEN0 = 1×, another clock is added for internal bus arbitration.
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Once an external device receives the bus and asserts BGACK, it should negate BR. If BR
remains asserted after BGACK is asserted, the QUICC assumes that another device is
requesting the bus and prepares to issue another BG.
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4.6.4 Bus Arbitration Control
The bus arbitration control unit in the QUICC is implemented with a finite state machine. As
discussed previously, all asynchronous inputs to the QUICC are internally synchronized in
a maximum of two cycles of the clock. As shown in Figure 4-37, input signals labeled R and
A are internally synchronized versions of BR and BGACK, respectively. The BG output is
labeled G, and the internal high-impedance control signal is labeled T. If T is true, the
address, data, and control buses are placed in the high-impedance state after the next rising
edge following the negation of AS and RMC. All signals are shown in positive logic (active
high), regardless of their true active voltage level. The state machine shown in Figure 4-37
does not have a state 1 or state 4.
State changes occur on the next rising edge of the clock after the internal signal is valid. The
BG signal transitions on the rising edge of the clock after a state is reached during which G
changes. The bus control signals (controlled by T) are driven by the QUICC immediately following a state change, when bus mastership is returned to the QUICC. State 0, in which G
and T are both negated, is the state of the bus arbiter while the QUICC is bus master. R and
A keep the arbiter in state 0 as long as they are both negated.
The QUICC does not allow arbitration of the external bus during the RMC sequence. For the
duration of this sequence, the QUICC ignores the BR input. If mastership of the bus is
required during an RMC operation, BERR must be used to abort the RMC sequence.
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Bus Operation
RA + B
GTV
AB
STATE 0
RA
RAB
RA
G TV
RA
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STATE 3
R+A
G TV
STATE 2
R A +A
G TV
R
R
STATE 5
RA
RA
G TV
STATE 6
RA
R—BUS REQUEST
A—BUS GRANT ACKNOWLEDGE
B—BUS CYCLE IN PROGRESS
G—BUS GRANT
T —THREE-STATE SIGNAL TO BUS CONTROL
V—BUS AVAILABLE TO BUS CONTROL
Figure 4-37. Bus Arbitration State Diagram
4.6.5 Slave (Disable CPU32+) Mode Bus Arbitration
When configured in the slave mode, the QUICC follows the bus arbitration mechanism described in 4.6 Bus Arbitration. When acting as one or more of the QUICC internal masters
(refresh cycles, IDMA, and SDMA), the QUICC will output the BR signal. Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus
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Bus Operation
master at the same time, the one having the highest priority becomes bus master first. The
sequence of the protocol in normal slave mode is as follows:
1. The QUICC asserts BR.
2. The QUICC waits for the assertion of BG and the negation of BGACK to indicate that
the bus is available.
3. The QUICC asserts BGACK to indicate that it has assumed the bus.
The state machine for the normal slave mode arbitration is shown in Figure 4-38.
EXTERNAL
BUS IDLE
BG = 1
EXTERNAL MASTER ACCESS TO DUAL PORT RAM
Freescale Semiconductor, Inc...
IDLE
BR
NEGATED
QUICC REQUIRES EXTERNAL BUS
HALT IS ASSERTED AND DRAM REFRESH
DOES NOT REQUIRE EXTERNAL BUS
QUICC NO LONGER NEEDS BUS
OR
HALT ASSERTED AND DRAM
REFRESH DOES NOT NEED BUS
QUICC
WAITING FOR
BUS
BR
ASSERTED
BG = 0
QUICC
OWNS BUS
BR NEGATED
BGACK
ASSERTED
QUICC STILL NEEDS BUS
NOTE: BGACK is only asserted by QUICC during the state "QUICC Owns Bus", otherwise BGACK is
three-stated by the QUICC.
Figure 4-38. Slave Mode Bus Arbitration State Machine
In 68040 companion mode, the QUICC changes its bus arbitration sequence to match that
needed by the 68040. It is as follows:
1. The QUICC asserts BG continuously whenever the QUICC does not need the bus.
2. When the QUICC needs the bus, and the 68040 is not requesting the bus, it will deassert BG from the 68040 and assert BB to indicate that it has assumed the bus. If the
68040 then requests the bus using the BR pin, while the QUICC is asserting BB, the
BR040ID bits in the MCR will be used to determine if the 68040 has a high enough bus
request priority to cause the QUICC to give up the bus (i.e. deassert BB and assert
BG.)
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Bus Operation
3. If the 68040 requests the bus at the same time that a QUICC internal master is requesting the bus, the BR040ID bits are used to determine who will acquire the bus first.
4. When the QUICC no longer needs the bus, it deasserts BB and asserts BG.
The state machine for the MC68040 companion mode arbitration is shown in Figure 4-39.
040 STILL NEEDS BUS
040 OWNS
BUS
Freescale Semiconductor, Inc...
BG
ASSERTED
QUICC INTERNAL MASTER OF HIGHER
PRIORITY THAN THE 68040 REQUIRES
EXTERNAL BUS
040 REQUESTS BUS
040 FINISHES
USE OF BUS
EXTERNAL
BUS IDLE
IDLE
BB = 0
INTERNAL MASTER (IDMA, SDMA, OR DRAM
REFRESH) REQUESTS BUS
BG
ASSERTED
HALT IS ASSERTED AND DRAM REFRESH
DOES NOT REQUIRE EXTERNAL BUS
QUICC NO LONGER NEEDS BUS
OR
HALT ASSERTED AND DRAM
REFRESH DOES NOT NEED BUS
BR IS ASSERTED BY 040 AND 040 HAS
PRIORITY OVER CURRENT QUICC
INTERNAL BUS MASTER
QUICC
WAITING FOR
BUS
BG
NEGATED
BB = 1
QUICC
OWNS BUS
BG NEGATED
BB ASSERTED
QUICC STILL NEEDS BUS
NOTES:
1. If the 68040 and the QUICC Internal Master requests the bus at the same time, the highest priority requester wins.
2. The transition from "040 Owns Bus" to "QUICC Waiting for Bus" may be delayed, until the write portion of an 040
locked cycle if an 040 locked cycle is in progress when the higher priority QUICC internal master requests the bus.
3. BB is only asserted by QUICC during the state "QUICC Owns Bus", otherwise BB is three-stated by the QUICC.
Figure 4-39. MC68040 Companion Mode Bus Arbitration State Machine
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Bus Operation
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The QUICC has another mechanism to assign priorities to the bus masters. A new pin called
bus clear in (BCLRI) is defined. BCLRI indicates to the QUICC that a request is being made
for the QUICC to release the system bus. The QUICC will then clear all internal bus masters
with an arbitration ID smaller than the programmed value of the bus clear in ID (BCLRIID)
in the MCR.
Slave (disable CPU32+) mode bus arbitration has fewer arbitration modes than exist in a
normal mode, since in slave mode, the SHEN1-SHEN0 bits are forced to be "00":
• In synchronous mode (ASTM bit in the MCR is set), BG and BGACK have synchronous
timing, and the minimal delay between the assertion of BG (negation of BGACK) and
the assertion of BGACK is one clock.
• In asynchronous mode, the minimum time for BGACK assertion after BG is asserted
(BGACK is negated) depends on internal synchronization.
• The QUICC will not request the external bus (assert BR) when one of its internal masters is making an internal access. The QUICC will request the external bus only when
one of its internal masters is beginning an external access. In this case, the arbitration
overhead (external bus idle time is minimal).
See Figure 4-40 for the slave mode bus arbitration timing diagram.
S0
S1
S2
S3
S4
S5
CLKO1
A31–A0
D31–D0
AS
DS
R/W
DSACK1-DSACK0
BR (OUT)
BG (IN)
BGACK
(IN/OUT)
NOTES:
1. Synchronous arbitration with SHEN1–SHEN0 = 00.
2. Minimum bus idle time.
Figure 4-40. Slave Mode Bus Arbitration Timing Diagram
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Bus Operation
4.6.6 Slave (Disable CPU32+) Mode Bus Exceptions
The reset and bus error master mode support also applies to the slave mode. There is a
difference, however, in supporting halt and retry as explained in the following paragraphs.
4.6.6.1 HALT. The QUICC transfer operation may be suspended at any time by asserting
HALT to the QUICC. In response, any bus cycle in progress is completed (after DSACKx is
asserted), and bus ownership is released. No further bus cycles will be started while HALT
remains asserted. When the QUICC is in the middle of an operand transfer when halted and
when a new transfer request is pending, the QUICC will arbitrate for the bus and continue
normal operation.
Freescale Semiconductor, Inc...
NOTE
When the QUICC is doing a word access to an 8-bit port and
HALT is asserted during the first access to an 8-bit port, the
QUICC will access this byte again after bus ownership is granted
to the QUICC.
NOTE
In slave mode HALT has more priority than bus coherency,
whereas in normal mode (CPU32+ is enabled) HALT has less
priority than bus coherency.
4.6.6.2 RETRY. When HALT and BERR are asserted during a bus cycle, the QUICC terminates the bus cycle, releases the bus, and suspends any further operation until these signals
are negated. The QUICC will then arbitrate for the bus, re-execute the previous bus cycle,
and continue normal operation. Thus, in slave mode, a retry is actually a relinquish and retry.
NOTE
When the relinquish and retry is asserted during a word access
to an 8-bit port, and the external master that takes the bus performs an external-to-internal bus cycle, the entire word access
will be retried. This is true even if the relinquish and retry was
asserted on the second access and the first 8-bit access was
completed normally.
4.6.7 Internal Accesses
The QUICC supports an external-master access to its internal registers with a glueless interface. The QUICC internal register port size is always 32 bits. External QUICC/MC68EC030
accesses have the same bus operation as the QUICC (see 4.3 Data Transfer Cycles). The
QUICC supports the interrupt acknowledge cycles presented in 4.4.4 Interrupt Acknowledge
Bus Cycles. The QUICC also supports the MC68EC040 read and write accesses and interrupt acknowledge cycles (see Figure 4-41–Figure 4-44).
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C1
C2
CW
CW
CW
CLKO1
A31–A0
SIZ1–SIZ0
TT1–TT0
TM2–TM0
R/W
TS
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TA
TBI
D31–D0
Figure 4-41. MC68EC040 Internal Registers Read Cycle
C1
C2
CW
CW
CW
CLKO1
A31–A0
SIZ1–SIZ0
TT1–TT0
TM2–TT0
R/W
TS
TA
TBI
D31–D0
Figure 4-42. MC68EC040 Internal Registers Write Cycle
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C1
C2
CW
CW
CW
CW
Bus Operation
CW
CLKO1
A31–A0
SIZ1–SIZ0
TT1–TT0
TM2–TM0
INTERRUPT LEVEL
R/W
TS
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TA
TBI
D31–D0
AVECO
IACK7
IACK1
INTERNAL ARBITRATION
Figure 4-43. MC68EC040 Autovector Operation Timing
C1
C2
CW
CW
CW
CW
CW
CLKO1
A31–A0
SIZ1–SIZ0
TT1–TT0
TM2–TM0
INTERRUPT LEVEL
R/W
TS
TA
TBI
D31–D8
VECTOR#
D7–D0
IACK7
IACK1
INTERNAL ARBITRATI0N
Figure 4-44. MC68EC040 Interrupt Acknowledge Cycle
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4.6.8 Show Cycles
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The QUICC can perform data transfers with its internal modules without using the external
bus, but when debugging, it is desirable to have address and data information appear on the
external bus. These external bus cycles, called show cycles, are distinguished by the fact
that AS is not asserted externally. DS is used to signal address strobe timing in show cycles.
After reset, show cycles are disabled and must be enabled by writing to the SHEN bits in the
module configuration register. When show cycles are disabled, the address bus, function
codes, size, and read/write signals continue to reflect internal bus activity. However, AS and
DS are not asserted externally, and the external data bus remains in a high impedance
state. When show cycles are enabled, DS indicates address strobe timing and the external
data bus contains data. The following paragraphs are a state-by-state description of show
cycles, and Figure 4-45 illustrates a show cycle timing diagram. Refer to Section 10 Electrical Characteristics for specific timing information.
State 0 – During state 0, the address and function codes become valid, R/W is driven to indicate a show read or write cycle, and the size pins indicate the number of bytes to transfer.
During a read, the addressed peripheral is driving the data bus, and the user must take care
to avoid bus conflicts.
State 41 – One-half clock cycle later, DS (rather than AS) is asserted to indicate that address
information is valid.
State 42– No action occurs in state 42. The bus controller remains in state 42 (wait states
will be inserted) until the internal read cycle is complete.
State 43– When DS is negated, show data is valid on the next falling edge of the system
clock. The external data bus drivers are enabled so that data becomes valid on the external
bus as soon as it is available on the internal bus.
State 0 – The address, function codes, read/write, and size pins change to begin the next
cycle. Data from the preceding cycle is valid through state 0.
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S0
S41
S42
S43
S0
S1
Bus Operation
S2
CLKO1
A31–A0
FC3–FC0
SIZ1–SIZ0
R/W
AS, CS
DS
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D31–D0
BKPT
SHOW CYCLE
START OF
EXTERNAL CYCLE
Figure 4-45. Show Cycle Timing Diagram
4.7 RESET OPERATION
The QUICC has reset control logic to determine the cause of reset, synchronize it if necessary, and assert the appropriate reset lines. The reset control logic can independently drive
five different internal lines:
1. EXTSYSRST (external system reset) drives the external hard and soft reset pins (RESETH and RESETS).
2. EXTRST (external reset) drives the external soft reset pin (RESETS).
3. CLKRST (clock reset) resets the clock module.
4. INTSYSRST (internal system reset) resets the memory controller, system protection
logic, serial interface, interrupt controller, and parallel I/O modules.
5. INTRST (internal reset) goes to all other internal circuits.
Table 4-9 summarizes the result of each reset source. Synchronous reset sources are not
asserted until the end of the current bus cycle, regardless of whether RMC is asserted. The
internal bus monitor is automatically enabled for synchronous resets; therefore, if the current
bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or
word transfers are guaranteed valid for synchronous resets. Asynchronous reset sources
indicate a catastrophic failure, and the reset controller logic immediately resets the system.
Resetting the QUICC causes any bus cycle in progress to terminate as if DSACKx or BERR
had been asserted. In addition, the QUICC appropriately initializes registers for a reset
exception.
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Bus Operation
Table 4-9. Reset Source Summary
Type
Source
Timing
External Hard Reset (RESETH)
External
Asynchronous
INTRST
INTSYSRST
CLKRST
EXTSYSRST
External Soft Reset (RESETS)
External
Synchronous
INTRST
—
—
EXTRST
EBI
Asynchronous
INTRST
INTSYSRST
CLKRST
EXTSYSRST
Software Watchdog
Sys Prot
Asynchronous
INTRST
INTSYSRST
—
EXTSYSRST
Double Bus Fault
Sys Prot
Asynchronous
INTRST
INTSYSRST
CLKRST
EXTSYSRST
Clock
Asynchronous
INTRST
INTSYSRST
CLKRST
EXTSYSRST
CPU32+
Asynchronous
INTRST2
—
—
EXTRST
Power-Up
Loss of Clock1
Reset Instruction
Reset Lines Asserted by Controller
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NOTES:
1.The reset behavior is this case is dependent on the PLL programming (see 6.9.3.9 CLKO Control Register (CLKOCR)).
2.Doesn't cause a CPU32 reset exception nor does it affect any of its internal registers.
If an external device drives RESETS or RESETH low, they should be asserted for at least
32 clock periods to ensure that the QUICC resets. When the reset control logic detects that
an external device drives RESETS low, it starts driving both internal and external RESETS
low for 512 cycles to guarantee this length of reset to the entire system. When the reset control logic detects that an external device drives RESETH low, it starts driving both internal
and external RESETS and RESETH low for 512 cycles to guarantee this length of reset to
the entire system. The external and the internal resets are released after the external device
stops driving the external reset signal low or after the 512 cycles, whatever is later. Figure
4-46 shows the reset timing.
512 CYCLES
T ≤ 14 CLKS
RESETS OR
RESETH
T ≥ 32 CLKS
PULLED EXTERNAL
Figure 4-46. Timing for External Devices Driving RESET
NOTE
RESETS signal will always be negated after 512 cycles after assertion.
If reset is asserted from any other source, the reset control logic asserts a reset for a minimum of 512 cycles and until the source of reset is negated.
After any internal reset occurs, a 14-cycle rise time is allowed before testing for the presence
of an external reset. If no external reset is detected, the CPU32+ begins its vector fetch.
Figure 4-47 is a timing diagram of the power-up reset operation, showing the relationships
between RESETH, RESETS, VCC, and bus signals. During the reset period, the entire bus
three-states (except for non-three-statable signals, which are driven to their inactive state).
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Once RESETH and RESETS negate, all control signals are driven to their inactive state, the
data bus is in read mode, and the address bus is driven. After this, the first bus cycle of the
reset exception processing begins.
CLKO1
VCO
LOCK
VCC
512 ×
CLKOUT
≤ 14 CLOCKS
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RESETH
BUS
CYCLES
BUS STATE
UNKNOWN
ADDRESS AND
CONTROL SIGNALS
THREE-STATED
1
2
3
4
NOTES:
1. Internal start-up time.
2. SSP read here.
3. PC read here.
4. First instruction fetched here.
5. This figure is true when MODCK is 11 or 10.
When MODCK is 01 CLKO1 will be driven high at power up.
Figure 4-47. Initial Reset Operation Timing
NOTE
The PLL samples the MODCLK pins while in the first 512 clocks
of RESET. The process starts with RESET being asserted, then
MODCLK pins are sampled and the PLL is initialized according
to the MODCLK pins. For the next 500-2000 EXTAL cycles the
PLL is synchronizing. 512 clocks after the PLL synchronizes, the
QUICC no longer drives RESET and does not sample the MODCLK pins.
User should make suer the ramp up time of Vcc will never be
faster than 4mSec to ensure proper power on reset sequence.
When a RESET instruction is executed, the QUICC drives the RESETS signal for 512 clock
cycles. In this case, the QUICC resets the external devices of the system, and many of the
internal registers of the QUICC (see Section 3 QUICC Memory Map for a list of registers
affected by each type of reset).
The bus arbitration circuitry is only reset during a power-on reset. It may be used during all
other resets.
In QUICC slave mode (disable CPU32+) the reset operates the same as in the normal (master) mode except that the RESET instruction does not exist.
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NOTE
RESETS does not restore the Boot CS0 since the intent of RESETS is to not reset the memory controller. Note that the CPU
will still fetch the SP and PC from $0 and $4, therefore a system
implementing RESETS must have a device or register mapped
to 0 and 4 at all times.
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In the case where the CP32+ excutes a RESET command, the
QUICC drives RESETS pin. In that case RESETS will be driven
from CLOCK low (not CLOCK high as in all other cases). This
requires a special AC timing parameter which is spec 58A in
10.9 Bus Operation AC Timing Specifications.
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SECTION 5
CPU32+
The CPU32+, the second instruction processing module of the M68300 family, is based on
the industry-standard MC68000 core processor. Like the original CPU32, it has many features of the MC68010 and MC68020 as well as unique features suited for high-performance
processor applications. The CPU32+ provides a significant performance increase over the
MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000
family.
The CPU32+ differs from the original CPU32 in two ways: it allows an option of a 32-bit data
interface and allows byte-misaligned accesses to data operands.
5.1 OVERVIEW
The CPU32+ is designed to interface to the intermodule bus (IMB), allowing interaction with
other IMB submodules. In this manner, integrated processors can be developed that contain
useful peripherals on chip. This integration provides high-speed accesses among the IMB
submodules, increasing system performance.
The CPU32+ core is a CPU32 core with its bus interface unit modified to connect directly to
the 32-bit IMB and take advantage of the larger bus width. Although the original CPU32 core
already had a 32-bit internal data path and 32-bit arithmetic hardware, its external interface
(i.e., to the internal IMB) was 16 bits. The CPU32+ core, however, can operate on 32-bit
external operands with one bus cycle. This capability allows the CPU32+ core to fetch a
long-word instruction or two word-length instructions in one bus cycle, allowing the internal
instruction queue to be filled more quickly. The CPU32+ core can also read and write 32bits of data in one bus cycle. The CPU32+ has an additional word in its instruction pipeline
when fetching from a 32-bit port. When fetching from a 16-bit port, this additional word is
disabled. The performance of the CPU32+ on a 16-bit bus is the same as the CPU32 performance.
The CPU32+ also supports byte-misaligned operands. Since operands can reside at any
byte boundary, they may occasionally become misaligned. A byte operand is properly
aligned at any address; a word operand is misaligned at a odd address; a long-word operand is misaligned at an address that is not evenly divisible by four. Devices such as the
MC68302, MC68000/8, MC68010, and CPU32-based MC68300 allow long-word operand
transfers at odd-word addresses, but force exceptions if word or long-word operand transfers are attempted at odd-byte addresses. Although the CPU32+ does not enforce any alignment restrictions for data operands (including PC relative data addresses), some
performance degradation occurs when additional bus cycles are required for long-word or
word operands that are misaligned. For maximum performance, data items should be
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Thi d
t
t d ith F
M k 404
5-1
CPU32+
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aligned on their natural boundaries. All instruction words and extension words must reside
on word boundaries. Attempting to prefetch an instruction word at an odd address causes
an address error exception.
The CPU32+ has four bits (SZ1, SZ0 and SZC1, SCZ0) in the software status word (SSW)
that are new or have changed definitions.
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The CPU32+ offers low power consumption. The CPU32+ is implemented in high-speed
complementary metal-oxide semiconductor (HCMOS) technology, providing low power use
during normal operation. During periods of inactivity, the low-power stop (LPSTOP) instruction can be executed, shutting down the CPU32+ and other IMB modules, greatly reducing
power consumption.
Ease of programming is an important consideration when using an integrated processor.
The CPU32+ instruction format reflects a predominant register-memory interaction philosophy. All data resources are available to operations that require them. The programming
model includes eight multifunction data registers and seven general-purpose addressing
registers. The data registers support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand lengths for all operations. Address manipulation is supported by word and long-word
operations. Although the program counter (PC) and stack pointers (SP) are special-purpose
registers, they are also available for most data addressing activities. Ease of program checking and diagnosis is enhanced by trace and trap capabilities at the instruction level.
As processor applications become more complex and programs become larger, high-level
languages (HLLs) become the system designer's choice in programming languages. HLLs
aid in the rapid development of complex algorithms with less error and are readily portable.
The CPU32+ instruction set efficiently support HLLs.
5.1.1 Features
Features of the CPU32+ are as follows:
• Fully Upward Object-Code Compatible with M68000 Family
• Loop Mode of Instruction Execution
• Fast Multiply, Divide, and Shift Instructions
• Fast Bus Interface with Dynamic Bus Port Sizing
• Improved Exception Handling
• Additional Addressing Modes
—Scaled Index
—Address Register Indirect with Base Displacement and Index
—Expanded PC Relative Modes
—32-Bit Branch Displacements
• Instruction Set Additions
—High-Precision Multiply and Divide
—Trap on Condition Codes
—Upper and Lower Bounds Checking
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• Enhanced Breakpoint Instruction
• Trace on Change of Flow
• Table Lookup and Interpolate (TBL) Instruction
• LPSTOP Instruction
• Hardware BKPT Signal, Background Mode
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• Fully Static Implementation
A block diagram of the CPU32+ is shown in Figure 5-1. The major blocks depicted operate
in a highly independent fashion that maximizes concurrences of operation while managing
the essential synchronization of instruction execution and bus operation. The bus controller
loads instructions from the data bus into the decode unit. The sequencer and control unit
provide overall chip control by managing the internal buses, registers, and functions of the
execution unit.
SEQUENCER
CONTROL
UNIT
DATA BUS
ADDRESS
BUS
16
EXECUTION
UNIT
INSTRUCTION
PREFETCH
AND
DECODE
BUS
CONTROL
BUS CONTROL
32
Figure 5-1. CPU32+ Block Diagram
5.1.2 Loop Mode Instruction Execution
The CPU32+ has several features that provide efficient execution of program loops. One of
these features is the DBcc looping primitive instruction. To increase the performance of the
CPU32+, a loop mode has been added to the processor. The loop mode is used by any single-word instruction that does not change the program flow. Loop mode is implemented in
conjunction with the DBcc instruction. Figure 5-2 shows the required form of an instruction
loop for the processor to enter loop mode.
The loop mode is entered when the DBcc instruction is executed and the loop displacement
is –4. Once in loop mode, the processor performs only the data cycles associated with the
instruction and suppresses all instruction fetches. The termination condition and count are
checked after each execution of the data operations of the looped instruction. The CPU32+
automatically exits the loop mode during interrupts or other exceptions.
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ONE-WORD INSTRUCTION
DBcc
DBcc DISPLACEMENT
$FFFC = 4
Figure 5-2. Loop Mode Instruction Sequence
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5.1.3 Vector Base Register
The vector base register (VBR) contains the base address of the 1024-byte exception vector
table, which consists of 256 exception vectors. Exception vectors contain the memory
addresses of routines that begin execution at the completion of exception processing. These
routines perform a series of operations appropriate for the corresponding exceptions.
Because the exception vectors contain memory addresses, each vector consists of one long
word, except the reset vector. The reset vector consists of two long words: the address used
to initialize the supervisor stack pointer (SSP) and the address used to initialize the PC.
The address of an interrupt exception vector is derived from an 8-bit vector number and the
VBR. The vector numbers for some exceptions are obtained from an external device; other
numbers are supplied automatically by the processor. The processor multiplies the vector
number by 4 to calculate the vector offset, which is added to the VBR. The sum is the memory address of the vector. All exception vectors are located in supervisor data space, except
the reset vector, which is located in supervisor program space. Only the initial reset vector
is fixed in the processor's memory map; once initialization is complete, there are no fixed
assignments. Since the VBR provides the base address of the vector table, the vector table
can be located anywhere in memory; it can even be dynamically relocated for each task that
is executed by an operating system. Refer to 5.5 Exception Processing for additional details.
31
0
VECTOR BASE REGISTER (VBR)
5.1.4 Exception Handling
The processing of an exception occurs in four steps, with variations for different exception
causes. During the first step, a temporary internal copy of the status register (SR) is made,
and the SR is set for exception processing. During the second step, the exception vector is
determined. During the third step, the current processor context is saved. During the fourth
step, a new context is obtained, and the processor then proceeds with instruction processing.
Exception processing saves the most volatile portion of the current context by pushing it on
the supervisor stack. This context is organized in a format called the exception stack frame.
This information always includes the SR and PC context of the processor when the exception occurred. To support generic handlers, the processor places the vector offset in the
exception stack frame. The processor also marks the frame with a frame format. The format
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field allows the return-from-exception (RTE) instruction to identify what information is on the
stack so that it may be properly restored.
5.1.5 Addressing Modes
Addressing in the CPU32+ is register oriented. Most instructions allow the results of the
specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory.
The seven basic addressing modes are as follows:
• Register Direct
• Register Indirect
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• Register Indirect with Index
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Absolute
• Immediate
Included in the register indirect addressing modes are the capabilities to postincrement, predecrement, and offset. The PC relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the SR, SP
and/or PC. Addressing is explained fully in the M68000PM/AD, M68000 Family Programmer’s Reference Manual.
5.2 ARCHITECTURE SUMMARY
The CPU32+ is upward source- and object-code compatible with the MC68000 and
MC68010. It is downward source- and object-code compatible with the MC68020. Within the
M68000 family, architectural differences are limited to the supervisory operating state. User
programs can be executed unchanged on upward-compatible devices.
The major CPU32+ features are as follows:
• 32-Bit Internal Data Path and Arithmetic Hardware
• 32-Bit Address Bus Supported by 32-Bit Calculations
• Rich Instruction Set
• Eight 32-Bit General-Purpose Data Registers
• Seven 32-Bit General-Purpose Address Registers
• Separate User and Supervisor Stack Pointers (USP and SSP)
• Separate User and Supervisor Address Spaces
• Separate Program and Data Address Spaces
• Many Data Types
• Flexible Addressing Modes
• Full Interrupt Processing
• Expansion Capability
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5.2.1 Programming Model
The CPU32+ programming model consists of two groups of registers that correspond to the
user and supervisor privilege levels. User programs can only use the registers of the user
model. The supervisor programming model, which supplements the user programming
model, is used by CPU32+ system programmers who wish to protect sensitive operating
system functions. The supervisor model is identical to that of MC68010 and later processors.
The CPU32+ has eight 32-bit data registers, seven 32-bit address registers, a 32-bit PC,
separate 32-bit SSP and USP, a 16-bit SR, two alternate function code registers, and a 32bit VBR (see Figure 5-3 and Figure 5-4).
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31
16 15
8 7
0
D0
D1
D2
D3
D4
DATA REGISTERS
D5
D6
D7
31
16 15
0
A0
A1
A2
A3
ADDRESS REGISTERS
A4
A5
A6
31
16 15
0
31
A7 (USP)
USER STACK POINTER
PC
PROGRAM COUNTER
CCR
CONDITION CODE
REGISTER
0
15
8 7
0
Figure 5-3. User Programming Model
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31
16 15
0
8 7
A7′ (SSP)
SUPERVISOR STACK
POINTER
SR
STATUS REGISTER
VBR
VECTOR BASE
REGISTER
CPU32+
0
(CCR)
31
0
31
3 2
0
SFC
DFC
ALTERNATE
FUNCTION CODE
REGISTERS
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Figure 5-4. Supervisor Programming Model Supplement
5.2.2 Registers
Registers D7–D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32bit), and quad-word (64-bit) operations. Registers A6 to A0 and the USP and SSP are
address registers that may be used as software SPs or base address registers. Register A7
(shown as A7 and A7' in Figure 5-3 and Figure 5-4) is a register designation that applies to
the USP in the user privilege level and to the SSP in the supervisor privilege level. In addition, address registers may be used for word and long-word operations. All 16 general-purpose registers (D7–D0, A7–A0) may be used as index registers.
The Program Counter (PC) contains the address of the next instruction to be executed by
the CPU32+. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate.
The Status Register (SR) (see Figure 5-5) contains condition codes, an interrupt priority
mask (three bits), and three control bits. Condition codes reflect the results of a previous
operation. The codes are contained in the low byte (CCR) of the SR. The interrupt priority
mask determines the level of priority an interrupt must have to be acknowledged. The control
bits determine trace mode and privilege level. At user privilege level, only the CCR is available. At supervisor privilege level, software can access the full SR.
The Vector Base Register (VBR) contains the base address of the exception vector table in
memory. The displacement of an exception vector is added to the value in this register to
access the vector table.
Alternate source and destination function code registers (SFC and DFC) contain 3-bit function codes. The CPU32+ generates a function code each time it accesses an address. Specific codes are assigned to each type of access. The codes can be used to select eight
dedicated 4-Gbyte address spaces. The MOVEC instruction can use registers SFC and
DFC to specify the function code of a memory address.
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USER BYTE
(CONDITION CODE REGISTER)
SYSTEM BYTE
15
T1
14
T0
13
S
12
0
11
0
10
I2
TRACE
ENABLE
9
I1
8
I0
7
0
6
0
5
0
INTERRUPT
PRIORITY MASK
4
X
3
N
2
Z
1
V
0
C
EXTEND
NEGATIVE
ZERO
SUPERVISOR/USER
STATE
OVERFLOW
CARRY
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Figure 5-5. Status Register
5.3 INSTRUCTION SET
The following paragaphs describe the CPU32+ instruction set. A description of the instruction format, the operands used by the instructions, and a summary of the instructions by category are included. Complete programming information is provided in the M68000PM/AD,
M68000 Family Programmer’s Reference Manual.
The CPU32+ instructions include machine functions for all the following operations:
• Data Movement
• Arithmetic Operations
• Logical Operations
• Shifts and Rotates
• Bit Manipulation
• Conditionals and Branches
• System Control
The large instruction set encompasses a complete range of capabilities and, combined with
the enhanced addressing modes, provides a flexible base for program development.
The instruction set of the CPU32+ is very similar to that of the MC68020 (see Table 5-1).
The following M68020 instructions are not implemented on the CPU32+:
BFxx
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
BFFFO, BFINS, BFSET, BFTST)
CALLM, RTM — Call Module, Return Module
CAS, CAS2 — Compare and Set (Read-Modify-Write Instructions)
cpxxx
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
cpSAVE, cpScc, cpTRAPcc)
PACK, UNPK — Pack, Unpack BCD Instructions
The CPU32+ traps on unimplemented instructions or illegal effective addressing modes,
allowing user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented
instruction operation codes for future M68000 core enhancements.
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Table 5-1. Instruction Set
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Mnemonic
Description
Mnemonic
Description
ABCD
Add Decimal with Extend
MOVEA
Move Address
ADD
Add
MOVE CCR
Move Condition Code Register
ADDA
Add Address
MOVE SR
Move to/from Status Register
ADDI
Add Immediate
MOVE USP
Move User Stack Pointer
ADDQ
Add Quick
MOVEC
Move Control Register
AND
Logical AND
MOVEM
Move Multiple Registers
ANDI
Logical AND Immediate
MOVEP
Move Peripheral Data
ASL
Arithmetic Shift Left
MOVEQ
Move Quick
ASR
Arithmetic Shift Right
MOVES
Move Alternate Address Space
Bcc
Branch Conditionally (16 Tests)
MULS
Signed Multiply
BCHG
Bit Test and Change
MULU
Unsigned Multiply
BCLR
Bit Test and Clear
NBCD
Negate Decimal with Extend
BGND
Enter Background Mode
NEG
Negate
BKPT
Breakpoint
NEGX
Negate with Extend
BRA
Branch Always
NOP
No Operation
BSET
Bit Test and Set
NOT
Ones Complement
BSR
Branch to Subroutine
OR
Logical Inclusive OR
BTST
Bit Test
ORI
Logical Inclusive OR Immediate
CHK
Check Register against Bounds
PEA
Push Effective Address
CHK2
Check Register against Upper and
RESET
Reset External Devices
ROL, ROR
Rotate Left and Right
CLR
Clear Operand
ROXL, ROXR
Rotate with Extend Left and Right
CMP
Compare
RTD
Return and Deallocate
CMPA
Compare Address
RTE
Return from Exception
CMPI
Compare Immediate
RTR
Return and Restore
CMPM
Compare Memory
RTS
Return from Subroutine
CMP2
Compare Register against Upper
Lower Bounds
and Lower Bounds
DBcc
Test Condition, Decrement and
Branch (16 Tests)
SBCD
Subtract Decimal with Extend
Scc
Set Conditionally
STOP
Stop
SUB
Subtract
DIVS, DIVSL
Signed Divide
SUBA
Subtract Address
DIVU, DIVUL
Unsigned Divide
SUBI
Subtract Immediate
EOR
Logical Exclusive OR
SUBQ
Subtract Quick
EORI
Logical Exclusive OR Immediate
SUBX
Subtract with Extend
EXG
Exchange Registers
SWAP
Swap Data Register Halves
EXT, EXTB
Sign Extend
TAS
Test and Set Operand
ILLEGAL
Take Illegal Instruction Trap
TBLS, TBLSN
Table Lookup and Interpolate,
JMP
Jump
JSR
Jump to Subroutine
LEA
Load Effective Address
LINK
Link and Allocate
TRAPcc
Trap Conditionally (16 Tests)
LPSTOP
Low-Power Stop
TRAPV
Trap on Overflow
Signed
TBLU, TBLUN Table Lookup and Interpolate,
Unsigned
LSL, LSR
Logical Shift Left and Right
TST
Test
MOVE
Move
UNLK
Unlink
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5.3.1 M68000 Family Compatibility
It is the philosophy of the M68000 Family that all user-mode programs should execute
unchanged on a more advanced processor and that supervisor-mode programs and exception handlers should require only minimal alteration.
The CPU32+ can be thought of as an intermediate member of the M68000 family. Object
code from an MC68000 or MC68010 may be executed on the CPU32+, and many of the
instruction and addressing mode extensions of the MC68020 are also supported.
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5.3.1.1 NEW INSTRUCTIONS. Two instructions have been added to the M68000 instruction set: LPSTOP and TBL.
5.3.1.2 LOW-POWER STOP (LPSTOP). In applications where power consumption is a
consideration, the CPU32+ can force the device into a low-power standby mode when
immediate processing is not required. The low-power mode is entered by executing the
LPSTOP instruction. The processor remains in this mode until a user-specified or higher
level interrupt or a reset occurs.
5.3.1.3 TABLE LOOKUP AND INTERPOLATE (TBL). To maximize throughput for realtime applications, reference data is often precalculated and stored in memory for quick
access. The storage of sufficient data points can require an inordinate amount of memory.
The TBL instruction uses linear interpolation to recover intermediate values from a sample
of data points, thus conserving memory.
When the TBL instruction is executed, the CPU32+ looks up two table entries bounding the
desired result and performs a linear interpolation between them. Byte, word, and long-word
operand sizes are supported. The result can be rounded according to a round-to-nearest
algorithm or returned unrounded along with the fractional portion of the calculated result
(byte and word results only). This extra precision can be used to reduce cumulative error in
complex calculations. See 5.3.4 Using the TBL Instructions for examples.
5.3.1.4 UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instructions allows user-supplied code to emulate unimplemented capabilities or to define specialpurpose functions. However, Motorola reserves the right to use all currently unimplemented
instruction operation codes for future M68000 enhancements. See 5.5.2.8 Illegal or Unimplemented Instructions for more details.
5.3.2 Instruction Format and Notation
All instructions consist of at least one word. Some instructions can have as many as seven
words, as shown in Figure 5-6. The first word of the instruction, called the operation word,
specifies instruction length and the operation to be performed. The remaining words, called
extension words, further specify the instruction and operands. These words may be immediate operands, extensions to the effective address mode specified in the operation word,
branch displacements, bit number, special register specifications, trap operands, or argument counts.
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15
CPU32+
0
OPERATION WORD
(ONE WORD, SPECIFIES OPERATION AND MODES)
SPECIAL OPERAND SPECIFIERS
(IF ANY, ONE OR TWO WORDS)
IMMEDIATE OPERAND OR SOURCE ADDRESS EXTENSION
(IF ANY, ONE TO THREE WORDS)
DESTINATION EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE TO THREE WORDS)
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Figure 5-6. Instruction Word General Format
Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location
in one of three ways:
• Register Specification
A register field of the instruction contains the number of the register.
• Effective Address
An effective address field of the instruction contains address mode information.
• Implicit Reference
The definition of an instruction implies the use of
specific registers.
The register field within an instruction specifies the register to be used. Other fields within
the instruction specify whether the register is an address or data register and how it is to be
used. The M68000PM/AD, M68000 Family Programmer’s Reference Manual, contains
detailed register information.
Except where noted, the following notation is used in this section:
Data
Immediate data from an instruction
Destination Destination contents
Source
Source contents
Vector
Location of exception vector
An
Any address register (A7–A0)
Ax, Ay
Address registers used in computation
Dn
Any data register (D7–D0)
Rc
Control register (VBR, SFC, DFC)
Rn
Any address or data register
Dh, Dl
Data registers, high- and low-order 32 bits of product
Dr, Dq
Data registers, division remainder, division quotient
Dx, Dy
Data registers, used in computation
Dym, Dyn
Data registers, table interpolation values
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Xn
Index register
[An]
Address extension
cc
Condition code
d#
Displacement
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Example: d16 is a 16-bit displacement
〈ea〉
Effective address
#〈data〉
Immediate data; a literal integer
label
Assembly program label
list
List of registers
Example: D3–D0
[...]
Bits of an operand
Examples: [7] is bit 7; [31:24] are bits 31–24
(...)
Contents of a referenced location
Example: (Rn) refers to the contents of Rn
CCR
Condition code register (lower byte of SR)
X—extend bit
N—negative bit
Z—zero bit
V—overflow bit
C—carry bit
PC
Program counter
SP
Active stack pointer
SR
Status register
SSP
Supervisor stack pointer
USP
User stack pointer
FC
Function code
DFC
Destination function code register
SFC
Source function code register
+
Arithmetic addition or postincrement
–
Arithmetic subtraction or predecrement
/
Arithmetic division or conjunction symbol
×
Arithmetic multiplication
=
Equal to
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≠
Not equal to
>
Greater than
≥
Greater than or equal to
<
Less than
≤
Less than or equal to
Λ
Logical AND
V
Logical OR
⊕
Logical exclusive OR
~
Invert; operand is logically complemented
BCD
Binary-coded decimal, indicated by subscript
Example: Source10 is a BCD source operand.
LSW
Least significant word
MSW
Most significant word
{R/W}
Read/write indicator
CPU32+
In a description of an operation, a destination operand is placed to the right of source operands and is indicated by an arrow (⇒).
5.3.3 Instruction Summary
The instructions form a set of tools to perform the following operations:
Data Movement
Bit Manipulation
Integer Arithmetic
Binary-Coded Decimal Arithmetic
Logic
Program Control
Shift and Rotate
System Control
The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32+ instructions
are summarized in Table 5-2.
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Table 5-2. Instruction Set Summary
Opcode
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Syntax
Source10 + Destination10 + X ⇒ Destination
ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD
Source + Destination ⇒ Destination
ADD 〈ea〉,Dn
ADD Dn,〈ea〉
ADDA
Source + Destination ⇒ Destination
ADDA 〈ea〉,An
ADDI
Immediate Data + Destination ⇒ Destination
ADDI #〈data〉,〈ea〉
ADDQ
Immediate Data + Destination ⇒ Destination
ADDQ #〈data〉,〈ea〉
ADDX
Source + Destination + X ⇒ Destination
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND
Source Λ Destination ⇒ Destination
AND 〈ea〉,Dn
AND Dn,〈ea〉
ANDI
Immediate Data Λ Destination ⇒ Destination
ANDI #〈data〉,〈ea〉
Source Λ CCR ⇒ CCR
ANDI #〈data〉,CCR
If supervisor state
the Source Λ SR ⇒ SR
else TRAP
ANDI #〈data〉,SR
Destination Shifted by 〈count〉 ⇒ Destination
ASd Dx,Dy
ASd #〈data〉,Dy
ASd 〈ea〉
If (condition true) then PC + d ⇒ PC
Bcc 〈label〉
BCHG
~(〈number〉 of Destination) ⇒ Z;
~(〈number〉 of Destination) ⇒ 〈bit number〉 of
Destination
BCHG Dn,〈ea〉
BCHG #data〉,〈ea〉
BCLR
~(〈number〉 of Destination) ⇒ Z;
0 ⇒ 〈bit number〉 of Destination
BCLR Dn,〈ea〉
BCLR #〈data〉,〈ea〉
BGND
If (background mode enabled) then
enter background mode
else Format/Vector offset ⇒ –(SSP)
PC ⇒ –(SSP)
SR ⇒ –(SSP)
(Vector) ⇒ PC
BGND
BKPT
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
BKPT #〈data〉
BRA
PC + d ⇒ PC
BRA 〈label〉
BSET
~(〈number〉 of Destination) ⇒ Z;
1 ⇒ 〈bit number〉 of Destination
BSET Dn,〈eaÒ
BSET #〈data〉,〈ea〉
BSR
SP – 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC
BSR 〈label〉
BTST
– (〈number〉 of Destination) ⇒ Z;
BTST Dn,〈ea〉
BTST #〈data〉,〈ea〉
CHK
If Dn < 0 or Dn > Source then TRAP
CHK 〈ea〉,Dn
CHK2
If Rn < lower bound or
If Rn > upper bound
then TRAP
CHK2 〈ea〉,Rn
CLR
0 ⇒ Destination
CLR 〈ea〉
CMP
Destination Source ⇒ cc
CMP 〈ea〉,Dn
CMPA
Destination — Source
CMPA 〈ea〉,An
CMPI
Destination — Immediate Data
CMPI #〈data〉,〈ea〉
CMPM
Destination — Source ⇒ cc
CMPM (Ay)+,(Ax)+
ABCD
ANDI to CCR
ANDI to SR
ASL,ASR
Bcc
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Table 5-2. Instruction Set Summary (Continued)
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Opcode
Operation
Syntax
CMP2
Compare Rn < lower-bound or
Rn > upper-bound
and Set Condition Codes
CMP2 〈ea〉,Rn
DBcc
If condition false then (Dn – 1 ⇒ Dn;
If Dn ≠ –1 then PC + d ⇒ PC)
DBcc Dn,〈label〉
DIVS
DIVSL
Destination/Source ⇒ Destination
DIVS.W 〈ea〉,Dn 32/16 ⇒ 16r:16q
DIVS.L 〈ea〉,Dq 32/32 ⇒ 32q
DIVS.L 〈ea〉,Dr:Dq 64/32 ⇒ 32r:32q
DIVSL.L 〈ea〉,Dr:Dq 32/32 ⇒ 32r:32q
DIVU
DIVUL
Destination/Source ⇒ Destination
DIVU.W 〈ea〉,Dn 32/16 ⇒ 16r:16q
DIVU.L 〈ea〉,Dq 32/32 ⇒ 32q
DIVU.L 〈ea〉,Dr:Dq 64/32 ⇒ 32r:32q
DIVUL.L 〈ea〉,Dr:Dq 32/32 ⇒ 32r:32q
EOR
Source ⊕ Destination ⇒ Destination
EOR Dn,〈ea〉
EORI
Immediate Data ⊕ Destination ⇒ Destination
EORI #〈data〉,〈ea〉
Source ⊕ CCR ⇒ CCR
EORI #〈data〉,CCR
EORI
to SR
If supervisor state
the Source ⊕ SR ⇒ SR
else TRAP
EORI #〈data〉,SR
EXG
Rx ⇔ Ry
EXG Dx,Dy
EXG Ax,Ay
EXG Dx,Ay
EXG Ay,Dx
EXT
EXTB
Destination Sign-Extended ⇒ Destination
EXT.W Dn extend byte to word
EXT.L Dn extend word to long word
EXTB.L Dn extend byte to long word
LLEGAL
SSP – 2 ⇒ SSP; Vector Offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP);
SSp – 2 ⇒ SSP; SR ⇒ (SSP);
Illegal Instruction Vector Address ⇒ PC
ILLEGAL
JMP
Destination Address ⇒ PC
JMP 〈ea〉
JSR
SP – 4 ⇒ SP; PC ⇒ (SP)
Destination Address ⇒ PC
JSR 〈ea〉
LEA
〈ea〉 ⇒ An
LEA 〈ea〉,An
LINK
SP – 4 ⇒ SP; An ⇒ (SP)
SP ⇒ An, SP + d ⇒ SP
LINK An,#〈displacement〉
LPSTOP
If supervisor state
Immediate Data ⇒ SR
Interrupt Mask ⇒ External Bus Interface (EBI)
STOP
else TRAP
LPSTOP #〈data〉
LSL,LSR
Destination Shifted by 〈count〉 ⇒ Destination
LSd1 Dx,Dy
LSd1 #〈data〉,Dy
LSd1 〈ea〉
MOVE
Source ⇒ Destination
MOVE 〈ea〉,〈ea〉
MOVEA
Source ⇒ Destination
MOVEA 〈ea〉,An
EORI
to CCR
MOVE from CCR CCR ⇒ Destination
MOVE CCR,〈ea〉
MOVE to CCR
Source ⇒ CCR
MOVE 〈ea〉,CCR
MOVE from SR
If supervisor state
then SR ⇒ Destination
else TRAP
MOVE SR,〈ea〉
If supervisor state
then Source ⇒ SR
else TRAP
MOVE 〈ea〉,SR
MOVE to SR
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Table 5-2. Instruction Set Summary (Continued)
Opcode
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Syntax
If supervisor state
then USP ⇒ An or An ⇒ USP
else TRAP
MOVE USP,An
MOVE An,USP
MOVEC
If supervisor state
then Rc ⇒ Rn or Rn ⇒ Rc
else TRAP
MOVEC Rc,Rn
MOVEC Rn,Rc
MOVEM
Registers ⇒ Destination
Source ⇒ Registers
MOVEM register list,〈ea〉
MOVEM 〈ea〉,register list
MOVEP
Source ⇒ Destination
MOVEP Dx,(d,Ay)
MOVEP (d,Ay),Dx
MOVEQ
Immediate Data ⇒ Destination
MOVEQ #〈data〉,Dn
MOVES
If supervisor state
then Rn ⇒ Destination [DFC] or Source
[SFC] ⇒ Rn
else TRAP
MOVES Rn,〈ea〉
MOVES 〈ea〉,Rn
MULS
Source × Destination ⇒ Destination
MULS.W 〈ea〉,Dn 16 × 16 ⇒ 32
MULS.L 〈ea〉,Dl 32 × 32 ⇒ 32
MULS.L 〈ea〉,Dh:Dl 32 × 32 ⇒ 64
MULU
Source × Destination ⇒ Destination
MULU.W 〈ea〉,Dn 16 × 16 ⇒ 32
MULU.L 〈ea〉,Dl 32 × 32 ⇒ 32
MULU.L 〈ea〉,Dh:Dl 32 × 32 ⇒ 64
NBCD
0 – (Destination10) – X ⇒ Destination
NBCD 〈ea〉
0 – (Destination) ⇒ Destination
NEG 〈ea〉
0 – (Destination) – X ⇒ Destination
NEGX 〈ea〉
NOP
None
NOP
NOT
~Destination ⇒ Destination
NOT 〈ea〉
OR
Source V Destination ⇒ Destination
OR 〈ea〉,Dn
OR Dn,〈ea〉
ORI
Immediate Data V Destination ⇒ Destination
ORI #〈data〉,〈ea〉
Source V CCR ⇒ CCR
ORI #〈data〉,CCR
ORI to SR
If supervisor state
then Source V SR ⇒ SR
else TRAP
ORI #〈data〉,SR
PEA
Sp – 4 ⇒ SP; 〈ea〉 ⇒ (SP)
PEA 〈ea〉
If supervisor state
then Assert RESET
else TRAP
RESET
Destination Rotated by 〈count 〉⇒ Destination
ROd1 Rx,Dy
ROd1 #〈data〉,Dy
ROd1 〈ea〉
MOVE USP
NEG
NEGX
ORI to CCR
RESET
ROL,ROR
ROXL,ROXR
5-16
Operation
ROXd1 Rx,Dy
Destination Rotated with X by 〈count〉 ⇒ Destination ROXd1 #〈data〉,Dy
ROXd1 〈ea〉
RTD
(SP) ⇒ PC; SP + 4 + d ⇒ SP
RTE
If supervisor state
the (SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC;
SP + 4 ⇒ SP;
RTE
restore state and deallocate stack according to (SP)
else TRAP
RTR
(SP) ⇒ CCR; SP + 2 ⇒ SP;
(SP) ⇒ PC; SP + 4 ⇒ SP
RTD #〈displacement〉
RTR
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Table 5-2. Instruction Set Summary (Concluded)
Opcode
Syntax
(SP) ⇒ PC; SP + 4 ⇒ SP
RTS
Destination10 – Source10 – X ⇒ Destination
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
If Condition True
then 1s ⇒ Destination
else 0s ⇒ Destination
Scc 〈ea〉
STOP
If supervisor state
then Immediate Data ⇒ SR; STOP
else TRAP
STOP #〈data〉
SUB
Destination – Source ⇒ Destination
SUB 〈ea〉,Dn
SUB Dn,〈ea〉
SUBA
Destination – Source ⇒ Destination
SUBA 〈ea〉,An
SUBI
Destination – Immediate Data ⇒ Destination
SUBI #〈data〉,〈ea〉
SUBQ
Destination – Immediate Data ⇒ Destination
SUBQ #〈data〉,〈ea〉
SUBX
Destination – Source – X ⇒ Destination
SUBX Dx,Dy
SUBX –(Ax),–(Ay)
SWAP
Register [31:16] ⇔ Register [15:0]
SWAP Dn
TAS
Destination Tested ⇒ Condition Codes;
1 ⇒ bit 7 of Destination
TAS 〈ea〉
TBLS
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) × Dx[7:0]} / TBLS.〈size〉 〈ea〉, Dx
TBLS.〈size〉 Dym:Dyn, Dx
256 ⇒ Dx
RTS
SBCD
Scc
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Operation
TBLSN
TBLU
ENTRY(n) × 256 + {(ENTRY(n + 1) – ENTRY(n)) × Dx TBLSN.〈size〉 〈ea〉,Dx
[7:0]} ⇒ Dx
TBLSN.〈size〉 Dym:Dyn, Dx
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) × Dx[7:0]} / TBLU.〈size〉 〈ea〉,Dx
256 ⇒ Dx
TBLU.〈size〉 Dym:Dyn, Dx
ENTRY(n) × 256 + {(ENTRY(n + 1) – ENTRY(n)) ×
Dx[7:0]} ⇒ Dx
TBLUN.〈size〉 〈ea〉,Dx
TBLUN.〈size〉 Dym:Dyn,Dx
SSP – 2 ⇒ SSP; Format/Offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP); SSP – 2 ⇒ SSP;
SR ⇒ (SSP); Vector Address ⇒ PC
TRAP #〈vector〉
TRAPcc
If cc then TRAP
TRAPcc
TRAPcc.W #〈data〉
TRAPcc.L #〈data〉
TRAPV
If V then TRAP
TRAPV
Destination Tested ⇒ Condition Codes
TST 〈ea〉
An ⇒ SP; (SP) ⇒ An; SP + 4 ⇒ SP
UNLK An
TBLUN
TRAP
TST
UNLK
NOTE 1: d is direction, L or R.
5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that
indicate the result of a processor operation. Table 5-2 lists the effect of each instruction on
these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family
to simplify programming techniques that use them. Refer to Table 5-3 as an example.
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Table 5-3. Condition Code Computations
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Operations
X
N
Z
V
C
Special Definition
ABCD
*
U
?
U
?
C = Decimal Carry
Z = Z Λ Rm Λ ... Λ R0
ADD, ADDI, ADDQ
*
*
*
?
?
V = Sm Λ Dm Λ Rm V Sm Λ Dm Λ Rm
C = Sm Λ Dm V Rm Λ Dm V Sm Λ Rm
ADDX
*
*
?
?
?
V = Sm Λ Dm Λ Rm V Sm Λ Dm Λ Rm
C = Sm Λ Dm V Rm Λ Dm V Sm Λ Rm
Z = Z Λ Rm Λ ... Λ R0
AND, ANDI, EOR, EORI,
MOVEQ, MOVE, OR, ORI,
CLR, EXT, NOT, TAS, TST
—
*
*
0
0
CHK
—
*
U
U
U
CHK2, CMP2
—
U
?
U
?
Z = (R = LB) V (R = UB)
C=
(LB < UB) Λ (IR < LB) V (R > UB) V
(UB < LB) Λ (R > UB) Λ (R < LB)
SUB, SUBI, SUBQ
*
*
*
?
?
V = Sm Λ Dm Λ Rm V Sm Λ Dm Λ Rm
C = Sm Λ Dm V Rm Λ Dm V Sm Λ Rm
SUBX
*
*
?
?
?
V = Sm Λ Dm Λ Rm V Sm Λ Dm Λ Rm
C = Sm Λ Dm V Rm Λ Dm V Sm Λ Rm
Z = Z Λ Rm Λ ... Λ R0
CMP, CMPI, CMPM
—
*
*
?
?
V = Sm Λ Dm Λ Rm V Sm Λ Dm Λ Rm
C = Sm Λ Dm V Rm Λ Dm V Sm Λ Rm
DIVS, DIVU
—
*
*
?
0
V = Division Overflow
MULS, MULU
—
*
*
?
0
V = Multiplication Overflow
SBCD, NBCD
*
U
?
U
?
C = Decimal Borrow
Z = Z Λ Rm Λ ... Λ R0
NEG
*
*
*
?
?
V = Dm Λ Rm
C = Dm V Rm
NEGX
*
*
?
?
?
V = Dm Λ Rm
C = Dm V Rm
Z = Z Λ Rm Λ ... Λ R0
ASL
*
*
*
?
?
V = Dm Λ (Dm – 1 V ... V Dm – r) V Dm Λ
(Dm – 1 V ... + Dm – r)
C = Dm – r + 1
ASL (r = 0)
—
*
*
0
0
LSL, ROXL
*
*
*
0
?
LSR (r = 0)
—
*
*
0
0
ROXL (r = 0)
—
*
*
0
?
C=X
ROL
—
*
*
0
?
C = Dm – r + 1
ROL (r = 0)
—
*
*
0
0
ASR, LSR, ROXR
*
*
*
0
?
ASR, LSR (r = 0)
—
*
*
0
0
ROXR (r = 0)
—
*
*
0
?
ROR
—
*
*
0
?
ROR (r = 0)
—
*
*
0
0
C = Dm – r + 1
C = Dr – 1
C=X
)
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Table 5-3. Condition Code Computations (Continued)
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Note: The following notations apply to this table only.
—
=
Not affected
Sm
= Source operand MSB
U
=
Undefined
Dm
= Destination operand MSB
?
=
See special definition
Rm
= Result operand MSB
∗
=
General case
R
= Register tested
X
=
C
n
= Bit Number
N
=
Rm
r
= Shift count
Z
=
Rm Λ ... Λ R0
LB
= Lower bound
Λ
=
Boolean AND
UB
= Upper bound
V
=
Boolean OR
Rm
= NOT Rm
5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of
transferring and storing address and data. MOVE instructions transfer byte, word, and longword operands from memory to memory, memory to register, register to memory, and register to register. Address movement instructions (MOVE or MOVEA) transfer word and longword operands and ensure that only valid address manipulations are executed.
In addition to the general MOVE instructions, there are several special data movement
instructions—move multiple registers (MOVEM), move peripheral data (MOVEP), move
quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective
address (PEA), link stack (LINK), and unlink stack (UNLK). Table 5-4 is a summary of the
data movement operations.
Table 5-4. Data Movement Operations
Instruction
Operand
Syntax
Operand
Size
EXG
Rn, Rn
32
Rn ⇒ Rn
LEA
〈ea〉, An
32
〈ea〉 ⇒ An
LINK
An, #〈d〉
16, 32
MOVE
〈ea〉, 〈ea〉
8, 16, 32
Source ⇒ Destination
MOVEA
〈ea〉, An
16, 32 ⇒ 32
Source ⇒ Destination
MOVEM
list, 〈ea〉
〈ea〉, list
16, 32
16, 32 ⇒ 32
Listed registers ⇒ Destination
Source ⇒ Listed registers
Operation
SP – 4 ⇒ SP, An ⇒ (SP); SP ⇒ An, SP + d ⇒ SP
(d16, An), Dn
16, 32
Dn [31:24] ⇒ (An + d); Dn [23:16] ⇒ (An + d + 2);
Dn [15:8] ⇒ (An + d + 4); Dn [7:0] ⇒ (An + d + 6)
(An + d) ⇒ Dn [31:24]; (An + d + 2) ⇒ Dn [23:16];
(An + d + 4) ⇒ Dn [15:8]; (An + d + 6) ⇒ Dn [7:0]
MOVEQ
#〈data〉, Dn
8 ⇒ 32
Immediate Data ⇒ Destination
PEA
〈ea〉
32
SP – 4 ⇒ SP; 〈ea〉 ⇒ SP
UNLK
An
32
An ⇒ SP; (SP) ⇒ An, SP + 4 ⇒ SP
Dn, (d16, An)
MOVEP
5.3.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four
basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as
arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction
set includes ADD, CMP, and SUB instructions for both address and data operations with all
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operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The clear
and negate instructions apply to all sizes of data operands.
Signed and unsigned MUL and DIV instructions include:
• Word multiply to produce a long-word product
• Long-word multiply to produce a long-word or quad-word product
• Division of a long-word dividend by a word divisor (word quotient and word remainder)
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• Division of a long-word or quad-word dividend by a long-word divisor (long-word quotient and long-word remainder)
A set of extended instructions provides multiprecision and mixed-size arithmetic. These
instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and
negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arithmetic operations.
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Table 5-5. Integer Arithmetic Operations
Operand
Syntax
Operand
Size
ADD
Dn, 〈ea〉
〈ea〉, Dn
8, 16, 32
8, 16, 32
Source + Destination ⇒ Destination
ADDA
〈ea〉, An
16, 32
Source + Destination ⇒ Destination
ADDI
#〈data〉, 〈ea〉
8, 16, 32
Immediate Data + Destination ⇒ Destination
ADDQ
#〈data〉, 〈ea〉
8, 16, 32
Immediate Data + Destination ⇒ Destination
ADDX
Dn, Dn
– (An), – (An)
8, 16, 32
8, 16, 32
Source + Destination + X ⇒ Destination
CLR
〈ea〉
8, 16, 32
0 ⇒ Destination
CMP
〈ea〉, Dn
8, 16, 32
(Destination – Source), CCR shows results
CMPA
〈ea〉, An
16, 32
(Destination – Source), CCR shows results
CMPI
#〈data〉, 〈ea〉
8, 16, 32
(Destination – Immediate Data), CCR shows results
CMPM
(An) +, (An) +
8, 16, 32
(Destination – Source), CCR shows results
CMP2
〈ea〉, Rn
8, 16, 32
Lower bound ≤ Rn ≤ Upper Bound, CCR shows results
DIVS/DIVU
DIVSL/DIVUL
〈ea〉, Dn
ea〉, Dr:Dq
〈ea〉, Dq
〈ea〉, Dr:Dq
EXT
Dn
Dn
8 ⇒ 16
16 ⇒ 32
Sign Extended Destination ⇒ Destination
EXTB
Dn
8 ⇒ 32
Sign Extended Destination ⇒ Destination
MULS/MULU
〈ea〉, Dn
〈ea〉, Dl
〈ea〉, Dh:Dl
16 × 16 ⇒ 32
32 × 32 ⇒ 32
32 × 32 ⇒ 64
NEG
〈ea〉
8, 16, 32
0 – Destination ⇒ Destination
NEGX
〈ea〉
8, 16, 32
0 – Destination – X ⇒ Destination
SUB
〈ea〉, Dn
Dn, 〈ea〉
8, 16, 32
Destination – Source ⇒ Destination
SUBA
〈ea〉, An
16, 32
Destination – Source ⇒ Destination
SUBI
#〈data〉, 〈ea〉
8, 16, 32
Destination – Immediate Data ⇒ Destination
SUBQ
#〈data〉, 〈ea〉
8, 16, 32
Destination – Immediate Data ⇒ Destination
SUBX
Dn, Dn
– (An), – (An)
8, 16, 32
8, 16, 32
Destination – Source – X ⇒ Destination
TBLS/TBLU
〈ea〉, Dn
Dym:Dyn, Dn
8, 16, 32
Dyn – Dym ⇒ Temp
(Temp × Dn [7:0]) ⇒ Temp
(Dym × 256) + Temp ⇒ Dn
TBLSN/TBLUN
〈ea〉, Dn
Dym:Dyn, Dn
8, 16, 32
Dyn – Dym ⇒ Temp
(Temp × Dn [7:0]) / 256 ⇒ Temp
Dym + Temp ⇒ Dn
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Instruction
Operation
32/16 ⇒ 16:16
64/32 ⇒ 32:32 Destination/Source ⇒ Destination (signed or un32/32 ⇒ 32 signed)
32/32 ⇒ 32:32
Source × Destination ⇒ Destination (signed or unsigned)
5.3.3.4 LOGIC INSTRUCTIONS. The logical operation instructions (AND, OR, EOR, and
NOT) perform logical operations with all sizes of integer data operands. A similar set of
immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes
of immediate data. The test (TST) instruction arithmetically compares the operand with zero,
placing the result in the CCR. Table 5-6 summarizes the logical operations.
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Table 5-6. Logic Operations
Operand
Syntax
Operand
Size
AND
〈ea〉, Dn
Dn, 〈ea〉
8, 16, 32
8, 16, 32
Source Λ Destination ⇒ Destination
ANDI
#〈data〉, 〈ea〉
8, 16, 32
Immediate Data Λ Destination ⇒ Destination
EOR
Dn, 〈ea〉
8, 16, 32
Source ⊕ Destination ⇒ Destination
EORI
#〈data〉, 〈ea〉
8, 16, 32
Immediate Data ⊕ Destination ⇒ Destination
NOT
〈ea〉
8, 16, 32
Destination ⇒ Destination
OR
〈ea〉, Dn
Dn, 〈ea〉
8, 16, 32
8, 16, 32
Source V Destination ⇒ Destination
ORI
#〈data〉, 〈ea〉
8, 16, 32
Immediate Data V Destination ⇒ Destination
TST
〈ea〉
8, 16, 32
Source – 0, to set condition codes
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Instruction
Operation
5.3.3.5 SHIFT AND ROTATE INSTRUCTIONS. The arithmetic shift instructions, ASR and
ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions.
The ROR, ROL, ROXR, and ROXL instructions perform rotate (circular shift) operations,
with and without the extend bit. All shift and rotate operations can be performed on either
registers or memory.
Register shift and rotate operations shift all operand sizes. The shift count may be specified
in the instruction operation word (to shift from 1 to 8 places) or in a register (modulo 64 shift
count).
Memory shift and rotate operations shift word-length operands one bit position only. The
SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate
instructions is enhanced so that use of the ROR and ROL instructions with a shift count of
eight allows fast byte swapping. Table 5-7 is a summary of the shift and rotate operations.
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Table 5-7. Shift and Rotate Operations
Operand
Syntax
Operand
Size
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
ASR
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
LSL
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
LSR
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
ROL
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
Dn, Dn
#〈data〉, Dn
〈ea〉
8, 16, 32
8, 16, 32
16
Dn
16
Instruction
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ASL
ROR
ROXL
ROXR
SWAP
Operation
X/C
0
X/C
0
X/C
0
X/C
C
C
C
X
X
C
MSW
LSW
5.3.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and
clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be performed on either registers or memory. The bit number is specified as immediate data or in
a data register. Register operands are 32 bits, and memory operands are 8 bits. Table 5-8
is a summary of bit manipulation instructions.
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Table 5-8. Bit Manipulation Operations
Operand
Syntax
Operand
Size
BCHG
Dn, 〈ea〉
#〈data〉, 〈ea〉
8, 32
8, 32
~(〈bit number〉 of destination) ⇒ Z ⇒ bit of
destination
BCLR
Dn, 〈ea〉
#〈data〉, 〈ea〉
8, 32
8, 32
~(〈bit number〉 of destination) ⇒ Z; 0 ⇒ bit of
destination
BSET
Dn, 〈ea〉
#〈data〉, 〈ea〉
8, 32
8, 32
~(〈bit number〉 of destination) ⇒ Z; 1 ⇒ bit of
destination
BTST
Dn, 〈ea〉
#〈data〉, 〈ea〉
8, 32
8, 32
~(〈bit number〉 of destination) ⇒ Z
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Instruction
Operation
5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support
operations on BCD numbers. The arithmetic operations on packed BCD numbers are add
decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with
extend (NBCD). Table 5-9 is a summary of the BCD operations.
Table 5-9. Binary-Coded Decimal Operations
Instruction
Operand
Syntax
Operand
Size
ABCD
Dn, Dn
– (An), – (An)
8
8
Source10 + Destination10 + X ⇒ Destination
NBCD
〈ea〉
8
8
0 – Destination10 – X ⇒ Destination
SBCD
Dn, Dn
– (An), – (An)
8
8
Destination10 – Source10 – X ⇒ Destination
Operation
5.3.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return
instructions and conditional and unconditional branch instructions perform program control
operations. Table 5-10 summarizes these instructions.
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Table 5-10. Program Control Operations
Instruction
Operand
Syntax
Operand
Size
Operation
Conditional
Bcc
〈label〉
8, 16, 32
If condition true, then PC + d ⇒ PC
DBcc
Dn, 〈label〉
16
If condition false, then Dn – 1 ⇒ PC;
if Dn ≠ (– 1), then PC + d ⇒ PC
Scc
〈ea〉
8
If condition true, then destination bits are set to 1;
else destination bits are cleared to 0
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Unconditional
BRA
〈label〉
8, 16, 32
PC + d ⇒ PC
BSR
〈label〉
8, 16, 32
SP – 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC
JMP
〈ea〉
none
Destination ⇒ PC
JSR
〈ea〉
none
SP – 4 ⇒ SP; PC ⇒ (SP); destination ⇒ PC
NOP
none
none
PC + 2 ⇒ PC
Returns
(SP) ⇒ PC; SP + 4 + d ⇒ SP
RTD
#〈d〉
16
RTR
none
none
(SP) ⇒ CCR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒ SP
RTS
none
none
(SP) ⇒ PC; SP + 4 ⇒ SP
To specify conditions for change in program control, condition codes must be substituted for
the letters "cc" in conditional program control opcodes. Condition test mnemonics are given
below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes.
—CC — Carry clear
—CS — Carry set
—EQ — Equal
—F
— False*
—GE — Greater or equal
—GT — Greater than
—HI — High
—LE — Less or equal
—*Not applicable to the Bcc instruction
LS
LT
MI
NE
PL
T
VC
VS
—
—
—
—
—
—
—
—
Low or same
Less than
Minus
Not equal
Plus
True
Overflow clear
Overflow set
5.3.3.9 SYSTEM CONTROL INSTRUCTIONS. Privileged instructions, trapping instructions, and instructions that use or modify the CCR provide system control operations. All of
these instructions cause the processor to flush the instruction pipeline. Table 5-11 summarizes the instructions. The preceding list of condition tests also applies to the TRAPcc
instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes.
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Table 5-11. System Control Operations
Instruction
Operand
Syntax
Operand
Size
Operation
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Privileged
ANDI
#〈data〉, SR
16
Immediate Data Λ SR ⇒ SR
EORI
#〈data〉, SR
16
Immediate Data ⊕ SR ⇒ SR
MOVE
〈ea〉, SR
SR, 〈ea〉
16
16
Source ⇒ SR
SR ⇒ Destination
MOVEA
USP, An
An, USP
32
32
USP ⇒ An
An ⇒ USP
MOVEC
Rc, Rn
Rn, Rc
32
32
Rc ⇒ Rn
Rn ⇒ Rc
MOVES
Rn, 〈ea〉
〈ea〉, Rn
8, 16, 32
Rn ⇒ Destination using DFC
Source using SFC ⇒ Rn
ORI
#〈data〉, SR
16
Immediate Data V SR ⇒ SR
RESET
none
none
Assert RESET line
RTE
none
none
(SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒ SP;
restore stack according to format
STOP
#〈data〉
16
LPSTOP
#〈data〉
none
Immediate Data ⇒ SR; STOP
Immediate Data ⇒ SR; interrupt mask ⇒ EBI; STOP
Trap Generating
BKPT
#〈data〉
none
If breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction.
BGND
none
none
If background mode enabled, then enter background
mode, else format/vector offset ⇒ – (SSP);
PC ⇒ – (SSP); SR ⇒ – (SSP); (vector) ⇒ PC
CHK
〈ea〉, Dn
16, 32
If Dn < 0 or Dn < (ea), then CHK exception
CHK2
〈ea〉, Rn
8, 16, 32
ILLEGAL
none
none
SSP – 2 ⇒ SSP; vector offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP);
SSP – 2 ⇒ SSP; SR ⇒ (SSP);
llegal instruction vector address ⇒ PC
TRAP
#〈data〉
none
SSP – 2 ⇒ SSP; format/vector offset ⇒ (SSP);
SSP – 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP);
vector address ⇒ PC
TRAPcc
none
#〈data〉
none
16, 32
If cc true, then TRAP exception
TRAPV
none
none
If V set, then overflow TRAP exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
Condition Code Register
ANDI
#〈data〉, CCR
8
Immediate Data Λ CCR ⇒ CCR
EORI
#〈data〉, CCR
8
Immediate Data ⊕ CCR ⇒ CCR
MOVE
〈ea〉, CCR
CCR, 〈ea〉
16
16
Source ⇒ CCR
CCR ⇒ Destination
ORI
#〈data〉, CCR
8
Immediate Data V CCR ⇒ CCR
5.3.3.10 CONDITION TESTS. Conditional program control instructions and the TRAPcc
instruction execute on the basis of condition tests. A condition test is the evaluation of a logical expression related to the state of the CCR bits. If the result is 1, the condition is true. If
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the result is 0, the condition is false. For example, the T condition is always true, and the EQ
condition is true only if the Z-bit condition code is true. Table 5-12 lists each condition test.
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Table 5-12. Condition Tests
Mnemonic
Condition
Encoding
Test
T
True
0000
1
F*
False
0001
0
HI
High
0010
C•Z
LS
Low or Same
0011
C+Z
CC
Carry Clear
0100
C
CS
Carry Set
0101
C
NE
Not Equal
0110
Z
EQ
Equal
0111
Z
VC
Overflow Clear
1000
V
VS
Overflow Set
1001
V
PL
Plus
1010
N
MI
Minus
1011
N
GE
Greater or Equal
1100
N•V+N•V
LT
Less Than
1101
N•V+N•V
GT
Greater Than
1110
N•V•Z+N•V•Z
LE
Less or Equal
1111
Z+N•V+N•V
* Not available for the Bcc instruction.
•=Boolean AND
+=Boolean OR
N=Boolean NOT
5.3.4 Using the TBL Instructions
There are four TBL instructions. TBLS returns a signed, rounded byte, word, or long-word
result. TBLSN returns a signed, unrounded byte, word, or long-word result. TBLU returns an
unsigned, rounded byte, word, or long-word result. TBLUN returns an unsigned, unrounded
byte, word, or long-word result. All four instructions support two types of interpolation data:
an n-element table stored in memory and a two-element range stored in a pair of data registers. The latter form provides a means of performing surface (3D) interpolation between
two previously calculated linear interpolations.
The following examples show how to compress tables and use fewer interpolation levels
between table entries. Example 1 (see Figure 5-7) demonstrates TBL for a 257-entry table,
allowing up to 256 interpolation levels between entries. Example 2 (see Figure 5-8) reduces
table length for the same data to four entries. Example 3 (see Figure 5-9) demonstrates use
of an 8-bit independent variable with an instruction.
Two additional examples show how TBLSN can reduce cumulative error when multiple table
lookup and interpolation operations are used in a calculation. Example 4 demonstrates addition of the results of three table interpolations. Example 5 illustrates use of TBLSN in surface
interpolation.
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5.3.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries.
As shown in Figure 5-7, the function is linear within the range 32768 ≤ X ≤ 49152. Table
entries within this range are as given in Table 5-13 .
Table 5-13. Standard Usage Entries
Entry Number
X-Value
Y-Value
128*
32768
1311
162
41472
1659
163
41728
1669
164
41984
1679
165
42240
1690
192*
49152
1966
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*These values are the end points of the range.
All entries between these points fall on the line.
DEPENDENT VARIABLE
Y
16384
32768
49152
65536
X
INDEPENDENT VARIABLE
Figure 5-7. Table Example 1
The table instruction is executed with the following bit pattern in Dx:
31
16
NOT USED
15
1
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
Table Entry Offset ⇒ Dx [8:15] = $A3 = 163
Interpolation Fraction ⇒ Dx [0:7] = $80 = 128
Using this information, the table instruction calculates dependent variable Y:
Y = 1669 + (128 (1679 – 1669)) / 256 = 1674
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5.3.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE. In Example 2 (see Figure 5-8), the
data from Example 1 has been compressed by limiting the maximum value of the independent variable. Instead of the range 0 ≤ X = 65535, X is limited to 0 ≤ X ≤ 1023. The table has
been compressed to only five entries, but up to 256 levels of interpolation are allowed
between entries.
DEPENDENT VARIABLE
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Y
256
512
786
1024
X
INDEPENDENT VARIABLE
Figure 5-8. Table Example 2
NOTE
Extreme table compression with many levels of interpolation is
possible only with highly linear functions. The table entries within
the range of interest are listed in Table 5-14.
Table 5-14. Compressed Table Entries
Entry Number
X-Value
Y-Value
2
512
1311
3
786
1966
Since the table is reduced from 257 to 5 entries, independent variable X must be scaled
appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruction:
LSR.W #6,Dx
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Thus, Dx now contains the following bit pattern:
31
16
NOT USED
15
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
Table Entry Offset ⇒ Dx [8:15] = $02 = 2
Interpolation Fraction ⇒ Dx [0:7] = $8E = 142
Using this information, the table instruction calculates dependent variable Y:
Y = 1331 + (142 (1966 – 1311)) / 256 = 1674
5.3.4.3 TABLE EXAMPLE 3: 8-BIT INDEPENDENT VARIABLE. This example shows
how to use a table instruction within an interpolation subroutine. Independent variable X is
calculated as an 8-bit value, allowing 16 levels of interpolation on a 17-entry table. X is
passed to the subroutine, which returns an 8-bit result. The subroutine uses the data listed
in Table 5-15, based on the function shown in Figure 5-9.
INDEPENDENT VARIABLE
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The function chosen for Examples 1 and 2 is linear between data points. If another function
had been used, interpolated values might not have been identical.
Y
1024
2048
3072
4096
X
INDEPENDENT VARIABLE
Figure 5-9. Table Example 3
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Table 5-15. T8-Bit Independent Variable Entries
X
(Subroutine)
X
(Instruction)
Y
0
0
0
1
256
16
2
512
32
3
768
48
4
1024
64
5
1280
80
6
1536
96
7
1792
112
8
2048
128
9
2304
112
10
2560
96
11
2816
80
12
3072
64
13
3328
48
14
3584
32
15
3840
16
16
4096
0
The first column is the value passed to the subroutine, the second column is the value
expected by the table instruction, and the third column is the result returned by the subroutine.
The following value has been calculated for independent variable X:
31
16
NOT USED
15
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
1
Since X is an 8-bit value, the upper four bits are used as a table offset, and the lower four
bits are used as an interpolation fraction. The following results are obtained from the subroutine:
Table Entry Offset ⇒ Dx [4:7] = $B = 11
Interpolation Fraction ⇒ Dx [0:3] = $D = 13
Thus, Y is calculated as follows:
Y = 80 + (13 (64 – 80)) / 16 = 67
If the 8-bit value for X were used directly by the table instruction, interpolation would be incorrectly performed between entries 0 and 1. Data must be shifted to the left four places before use:
LSL.W #4, Dx
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The new range for X is 0 ≤ X ≤ 4096; however, since a left shift fills the least significant digits
of the word with zeros, the interpolation fraction can only have one of 16 values.
After the shift operation, Dx contains the following value:
31
16
15
0
NOT USED
0
0
0
1
0
1
1
1
1
0
1
0
0
0
0
0
Execution of the table instruction using the new value in Dx yields:
Table Entry Offset ⇒ Dx [8:15] = $0B = 11
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Interpolation Fraction ⇒ Dx [0:7] = $D0 = 208
Thus, Y is calculated as follows:
Y = 80 + (208 (64 – 80)) / 256 = 67
5.3.4.4 TABLE EXAMPLE 4: MAINTAINING PRECISION. In this example, three TBL
operations are performed and the results are summed. The calculation is done once with
the result of each TBL rounded before addition and once with only the final result rounded.
Assume that the result of the three interpolations are as follows (a ".'' indicates the binary
radix point).
TBL # 1
0010 0000 . 0111 0000
TBL# 2
0011 1111 . 0111 0000
TBL # 3
0000 0001 . 0111 0000
First, the results of each TBL are rounded with the TBLS round-to-nearest-even algorithm.
The following values would be returned by TBLS:
TBL # 1
0010 0000 .
TBL # 2
0011 1111 .
TBL # 3
0000 0001 .
Summing, the following result is obtained:
0010 0000 .
0011 1111 .
0000 0001 .
0110 0000 .
Now, using the same TBL results, the sum is first calculated and then rounded according to
the same algorithm:
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0010 0000 . 0111 0000
0011 1111 . 0111 0000
0000 0001 . 0111 0000
0110 0001 . 0101 0000
Rounding yields:
0110 0001 .
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The second result is preferred. The following code sequence illustrates how addition of a
series of table interpolations can be performed without loss of precision in the intermediate
results:
L0:
TBLSN.B
TBLSN.B
TBLSN.B
ADD.L
ADD.L
ASR.L
BCC.B
ADDQ.B
L1: . . .
〈ea〉, Dx
〈ea〉, Dx
〈ea〉, Dl
Dx, Dm
Dm, Dl
#8, Dl
L1
#1, Dl
Long addition avoids problems with carry
Move radix point
Fraction MSB in carry
5.3.4.5 TABLE EXAMPLE 5: SURFACE INTERPOLATIONS. The various forms of table
can be used to perform surface (3D) TBLs. However, since the calculation must be split into
a series of 2D TBLs, it is possible to lose precision in the intermediate results. The following
code sequence, incorporating both TBLS and TBLSN, eliminates this possibility.
L0:
MOVE.W
TBLSN.B
TBLSN.B
TBLS.W
ASR.L
BCC.B
ADDQ.B
L1: . . .
Dx, Dl
〈ea〉, Dx
〈ea〉, Dl
Dx:Dl, Dm
#8, Dm
L1
#1, Dl
Copy entry number and fraction number
Surface interpolation, with round
Read just the result
No round necessary
Half round up
Before execution of this code sequence, Dx must contain fraction and entry numbers for the
two TBL, and Dm must contain the fraction for surface interpolation. The 〈ea〉 fields in the
TBLSN instructions point to consecutive columns in a 3D table. The TBLS size parameter
must be word if the TBLSN size parameter is byte, and must be long word if TBLSN is word.
Increased size is necessary because a larger number of significant digits is needed to
accommodate the scaled fractional results of the 2D TBL.
5.3.5 Nested Subroutine Calls
The LINK instruction pushes an address onto the stack, saves the stack address at which
the address is stored, and reserves an area of the stack for use. Using this instruction in a
series of subroutine calls will generate a linked list of stack frames.
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The UNLK instruction removes a stack frame from the end of the list by loading an address
into the SP and pulling the value at that address from the stack. When the instruction operand is the address of the link address at the bottom of a stack frame, the effect is to remove
the stack frame from both the stack and the linked list.
5.3.6 Pipeline Synchronization with the NOP Instruction
Although the no operation (NOP) instruction performs no visible operation, it does force synchronization of the instruction pipeline, since all previous instructions must complete execution before the NOP begins.
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5.4 PROCESSING STATES
This section describes the processing states of the CPU32+. It includes a functional description of the bits in the supervisor portion of the SR and an overview of actions taken by the
processor in response to exception conditions.
5.4.1 State Transitions
The processor is always in one of four processing states: normal, background, exception, or
halted.
When the processor fetches instructions and operands or executes instructions, it is in the
normal processing state. The stopped condition, which the processor enters when a STOP
or LPSTOP instruction is executed, is a variation of the normal state in which no further bus
cycles are generated.
Background state is an alternate operational mode used for system debugging. Refer to 5.6
Development Support for more information.
Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes the stack operations, the exception vector fetch, and
the filling of the instruction pipeline caused by an exception. Exception processing ends
when execution of an exception handler routine begins. Refer to 5.5 Exception Processing
for comprehensive information.
A catastrophic system failure occurs if the processor detects a bus error or generates an
address error while in the exception processing state. This type of failure halts the processor. For example, if a bus error occurs during exception processing caused by another bus
error, the CPU32+ assumes that the system is not operational and halts.
The halted condition should not be confused with the stopped condition. After the processor
executes a STOP or LPSTOP instruction, execution of instructions can resume when a
trace, interrupt, or reset exception occurs.
5.4.2 Privilege Levels
To protect system resources, the processor can operate with either of two levels of access—
user or supervisor. Supervisor level is more privileged than user level. All instructions are
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available at the supervisor level, but execution of some instructions is not permitted at the
user level. There are separate SPs for each level. The S-bit in the SR indicates privilege
level and determines which SP is used for stack operations. The processor identifies each
bus access (supervisor or user mode) via function codes to enforce supervisor and user
access levels.
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In a typical system, most programs execute at the user level. User programs can access
only their own code and data areas and are restricted from accessing other information. The
operating system executes at the supervisor privilege level, has access to all resources, performs the overhead tasks for the user level programs, and coordinates their activities.
5.4.2.1 SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the SR is set, supervisor privilege
level applies, and all instructions are executable. The bus cycles generated for instructions
executed in supervisor level are normally classified as supervisor references, and the values
of the function codes on FC2–FC0 refer to supervisor address spaces.
All exception processing is performed at the supervisor level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the SSP.
Instructions that have important system effects can only be executed at supervisor level. For
instance, user programs are not permitted to execute STOP, LPSTOP, or RESET instructions. To prevent a user program from gaining privileged access, except in a controlled manner, instructions that can alter the S-bit in the SR are privileged. The TRAP #n instruction
provides controlled user access to operating system services.
5.4.2.2 USER PRIVILEGE LEVEL. If the S-bit in the SR is cleared, the processor executes
instructions at the user privilege level. The bus cycles for an instruction executed at the user
privilege level are classified as user references, and the values of the function codes on
FC2–FC0 specify user address spaces. While the processor is at the user level, implicit references to the system SP and explicit references to address register seven (A7) refer to the
USP.
5.4.2.3 CHANGING PRIVILEGE LEVEL. To change from user privilege level to supervisor
privilege level, a condition that causes exception processing must occur. When exception
processing begins, the current values in the SR, including the S-bit, are saved on the supervisor stack, and then the S-bit is set to enable supervisor access. Execution continues at
supervisor privilege level until exception processing is complete.
To return to user access level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE. These instructions execute
only at supervisor privilege level and can modify the S-bit of the SR. After these instructions
execute, the instruction pipeline is flushed, then refilled from the appropriate address space.
The RTE instruction causes a return to a program that was executing when an exception
occurred. When RTE is executed, the exception stack frame saved on the supervisor stack
can be restored in either of two ways.
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If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the SR
and PC are restored to the values saved on the supervisor stack, and execution resumes at
the restored PC address, with access level determined by the S-bit of the restored SR.
If the frame was generated by a bus error or an address error exception, the entire processor
state is restored from the stack.
5.5 EXCEPTION PROCESSING
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An exception is a special condition that pre-empts normal processing. Exception processing
is the transition from normal mode program execution to execution of a routine that deals
with an exception. The following paragraphs discuss system resources related to exception
handling, exception processing sequence, and specific features of individual exception processing routines.
5.5.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. The VBR contains
the base address of a 1024-byte exception vector table, which consists of 256 exception
vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for
user definition as interrupt vectors. Except for the reset vector, which is two long words, each
vector in the table is one long word. Refer to Table 5-16 for information on vector assignment.
All exception vectors, except the reset vector, are located in supervisor data space. The
reset vector is located in supervisor program space. Only the initial reset vector is fixed in
the processor memory map. When initialization is complete, there are no fixed assignments.
Since the VBR stores the vector table base address, the table can be located anywhere in
memory. It can also be dynamically relocated for each task executed by an operating system.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained
from an external device; others are supplied by the processor. The processor multiplies the
vector number by 4 to calculate vector offset, then adds the offset to the contents of the VBR.
The sum is the memory address of the vector.
5.5.1.1 TYPES OF EXCEPTIONS. An exception can be caused by internal or external
events.
An internal exception can be generated by an instruction or by an error. The TRAP, TRAPcc,
TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal
execution. Illegal instructions, instruction fetches from odd addresses, word or long-word
operand accesses from odd addresses, and privilege violations also cause internal exceptions.
Sources of external exception include interrupts, breakpoints, bus errors, and reset
requests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access control
and processor restart.
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Table 5-16. Exception Vector Assignments
Vector Offset
Dec
Hex
Space
0
0
000
SP
Reset: Initial Stack Pointer
1
4
004
SP
Reset: Initial Program Counter
2
8
008
SD
Bus Error
3
12
00C
SD
Address Error
4
16
010
SD
Illegal Instruction
5
20
014
SD
Zero Division
6
24
018
SD
CHK, CHK2 Instructions
7
28
01C
SD
TRAPcc, TRAPV Instructions
8
32
020
SD
Privilege Violation
9
36
024
SD
Trace
10
40
028
SD
Line 1010 Emulator
11
44
02C
SD
Line 1111 Emulator
12
48
030
SD
Hardware Breakpoint
13
52
034
SD
(Reserved for Coprocessor Protocol Violation)
14
56
038
SD
Format Error
15
60
03C
SD
Uninitialized Interrupt
16–23
64
92
040
05C
SD
(Unassigned, Reserved)
—
24
96
060
SD
Spurious Interrupt
25
100
064
SD
Level 1 Interrupt Autovector
26
104
068
SD
Level 2 Interrupt Autovector
27
108
06C
SD
Level 3 Interrupt Autovector
28
112
070
SD
Level 4 Interrupt Autovector
29
116
074
SD
Level 5 Interrupt Autovector
30
120
078
SD
Level 6 Interrupt Autovector
31
124
07C
SD
Level 7 Interrupt Autovector
32–47
128
188
080
0BC
SD
Trap Instruction Vectors (0–15)
—
48–58
192
232
0C0
0E8
SD
(Reserved for Coprocessor)
—
59–63
236
252
0EC
0FC
SD
(Unassigned, Reserved)
—
64–255
256
1020
100
3FC
SD
User-Defined Vectors (192)
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Vector Number
Assignment
CAUTION
Because there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal
purposes. This practice is strongly discouraged.
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5.5.1.2 EXCEPTION PROCESSING SEQUENCE. For all exceptions other than a reset
exception, exception processing occurs in the following sequence. Refer to 5.5.2.1 Reset
for details of reset processing.
As exception processing begins, the processor makes an internal copy of the SR. After the
copy is made, the processor state bits in the SR are changed—the S-bit is set, establishing
supervisor access level, and bits T1 and T0 are cleared, disabling tracing. For reset and
interrupt exceptions, the interrupt priority mask is also updated.
Next, current processor status is saved. An exception stack frame is created and placed on
the supervisor stack. All stack frames contain copies of the SR and the PC for use by RTE.
The type of exception and the context in which the exception occurs determine what other
information is stored in the stack frame.
Finally, the processor prepares to resume normal execution of instructions. The exception
vector offset is determined by multiplying the vector number by 4, and the offset is added to
the contents of the VBR to determine displacement into the exception vector table. The
exception vector is loaded into the PC. If no other exception is pending, the processor will
resume normal execution at the new address in the PC.
5.5.1.3 EXCEPTION STACK FRAME. During exception processing, the most volatile portion of the current context is saved on the top of the supervisor stack. This context is organized in a format called the exception stack frame.
The exception stack frame always includes the contents of SR and PC at the time the exception occurred. To support generic handlers, the processor also places the vector offset in the
exception stack frame and marks the frame with a format code. The format field allows an
RTE instruction to identify stack information so that it can be properly restored.
The general form of the exception stack frame is illustrated in Figure 5-10. Although some
formats are peculiar to a particular M68000 family processor, format 0000 is always legal
and always indicates that only the first four words of a frame are present. See 5.5.4 CPU32+
Stack Frames for a complete discussion of exception stack frames.
15
0
SP
STATUS REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
FORMAT
VECTOR OFFSET
OTHER PROCESSOR STATE INFORMATION,
DEPENDING ON EXCEPTION
(0, 2, OR 8 WORDS)
STACKING ORDER
HIGHER ADDRESSES
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Next, the exception number is obtained. For interrupts, the number is fetched from CPU
space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal logic
provides a vector number.
Figure 5-10. Exception Stack Frame
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5.5.1.4 MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on
its relative importance to system operation. Priority assignments are shown in Table 5-17.
Group 0 exceptions have the highest priorities; group 4 exceptions have the lowest priorities.
Exception processing for exceptions that occur simultaneously is done by priority, from highest to lowest.
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It is important to be aware of the difference between exception processing mode and execution of an exception handler. Each exception has an assigned vector that points to an
associated handler routine. Exception processing includes steps described in 5.5.1.2
Exception Processing Sequence, but does not include execution of handler routines, which
is done in normal mode.
When the CPU32+ completes exception processing, it is ready to begin either exception
processing for a pending exception or execution of a handler routine. Priority assignment
governs the order in which exception processing occurs, not the order in which exception
handlers are executed.
Table 5-17. Exception Priority Groups
Group/
Priority
Exception and
Relative Priority
Characteristics
Reset
Aborts all processing (instruction or exception); does not save old context.
Address Error
Bus Error
Suspends processing (instruction or exception); saves internal context.
2
BKPT#n, CHK, CHK2,
Division by Zero, RTE,
TRAP#n, TRAPcc, TRAPV
Exception processing is a part of instruction
execution.
3
Illegal Instruction, Line A,
Unimplemented Line F,
Privilege Violation
Exception processing begins before instruction execution.
Trace
Hardware Breakpoint
Interrupt
Exception processing begins when current instruction or previous exception processing is
complete.
0
1.1
1.2
4.1
4.2
4.3
As a general rule, when simultaneous exceptions occur, the handler routines for lower priority exceptions are executed before the handler routines for higher priority exceptions. For
example, consider the arrival of an interrupt during execution of a TRAP instruction while
tracing is enabled. Trap exception processing (2) is done first, followed immediately by
exception processing for the trace (4.1), and then by exception processing for the interrupt
(4.3). Each exception places a new context on the stack. When the processor resumes normal instruction execution, it is vectored to the interrupt handler, which returns to the trace
handler that returns to the trap handler.
There are special cases to which the general rule does not apply. The reset exception will
always be the first exception handled since reset clears all other exceptions. It is also possible for high-priority exception processing to begin before low-priority exception processing
is complete. For example, if a bus error occurs during trace exception processing, the bus
error will be processed and handled before trace exception processing has completed.
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5.5.2 Processing of Specific Exceptions
The following paragraphs provide details concerning sources of specific exceptions, how
each arises, and how each is processed.
5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception. The reset exception has the
highest priority of any exception. Reset is used for system initialization and for recovery from
catastrophic failure. When the reset exception is recognized, it aborts any processing in
progress, and that processing cannot be recovered. Reset performs the following operations:
1. Clears T0 and T1 in the SR to disable tracing
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2. Sets the S-bit in the SR to establish supervisor privilege
3. Sets the interrupt priority mask to the highest priority level (%111)
4. Initializes the VBR to zero ($00000000)
5. Generates a vector number to reference the reset exception vector
6. Loads the first long word of the vector into the interrupt SP
7. Loads the second long word of the vector into the PC
8. Fetches and initiates decode of the first instruction to be executed
Figure 5-11 is a flowchart of the reset exception
After initial instruction prefetches, normal program execution begins at the address in the
PC. The reset exception does not save the value of either the PC or the SR.
If a bus error or address error occurs during reset exception processing, a double bus fault
occurs, the processor halts, and the HALT signal is asserted to indicate the halted condition.
Execution of the RESET instruction does not cause a reset exception nor does it affect any
internal CPU register. The SIM60 registers and the module control register in each internal
peripheral module (DMA, timers, and serial modules) are not affected. All other internal
peripheral module registers are reset the same as for a hardware reset. The external
devices connected to the RESET signal are reset at the completion of the reset instruction
5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal
is acknowledged. The BERR signal can be asserted by one of three sources:
1. External logic by assertion of the BERR input pin
2. Direct assertion of the internal BERR signal by an internal module
3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog
after detecting a no-response condition
Bus error exception processing begins when the processor attempts to use information from
an aborted bus cycle.
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.
ENTRY
1➧
0➧
$7➧
$0➧
S
T0,T1
I2:IO
VBR
FETCH VECTOR # 0
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OTHERWISE
(VECTOR # 0) ➧ SP
BUS ERROR
FETCH VECTOR # 1
OTHERWISE
(VECTOR # 1) ➧ PC
BUS ERROR
PREFETCH 3 WORDS
OTHERWISE BEGIN
INSTRUCTION
EXECUTION
BUS ERROR/
ADDRESS
ERROR
(DOUBLE BUS FAULT)
ASSERT HALT
EXIT
EXIT
Figure 5-11. Reset Operation Flowchart
When the aborted bus cycle is an instruction prefetch, the processor will not initiate exception processing unless the prefetched information is used. For example, if a branch instruction flushes an aborted prefetch, that word is not accessed, and no exception occurs.
When the aborted bus cycle is a data access, the processor initiates exception processing
immediately, except in the case of released operand writes. Released write bus errors are
delayed until the next instruction boundary or until another operand access is attempted.
Exception processing for bus error exceptions follows the regular sequence, but context
preservation is more involved than for other exceptions because a bus exception can be ini-
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tiated while an instruction is executing. Several bus error stack format organizations are utilized to provide additional information regarding the nature of the fault.
First, any register altered by a faulted-instruction EA calculation is restored to its initial value.
Then a special status word (SSW) is placed on the stack. The SSW contains specific information about the aborted access—size, type of access (read or write), bus cycle type, and
function code. Finally, fault address, bus error exception vector number, PC value, and a
copy of the SR are saved.
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If a bus error occurs during exception processing for a bus error, an address error, a reset,
or while the processor is loading stack information during RTE execution, the processor
halts. This simplifies isolation of catastrophic system failure by preventing processor interaction with stacks and memory. Only assertion of RESET can restart a halted processor.
5.5.2.3 ADDRESS ERROR. Address error exceptions occur when the processor attempts
to access an instruction, word operand, or long-word operand at an odd address. The effect
is much the same as an internally generated bus error. The exception processing sequence
is the same as that for bus error, except that the vector number refers to the address error
exception vector.
Address error exception processing begins when the processor attempts to use information
from the aborted bus cycle. If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the case of a released
operand write. Released write exceptions are delayed until the next instruction boundary or
attempted operand access.
An address exception on a branch to an odd address is delayed until the PC is changed. No
exception occurs if the branch is not taken. In this case, the fault address and return PC
value placed in the exception stack frame are the odd address, and the current instruction
PC points to the instruction that caused the exception.
If an address error occurs during exception processing for a bus error, another address
error, or a reset, the processor halts.
5.5.2.4 INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise
from either processor recognition of abnormal conditions during instruction execution or
from use of specific trapping instructions. Traps are generally used to handle abnormal conditions that arise in control routines.
The TRAP instruction, which always forces an exception, is useful for implementing system
calls for user programs. The TRAPcc, TRAPV, CHK, and CHK2 instructions force exceptions when a program detects a run-time error. The DIVS and DIVU instructions force an
exception if a division operation is attempted with a divisor of zero.
Exception processing for traps follows the regular sequence. If tracing is enabled when an
instruction that causes a trap begins execution, a trace exception will be generated by the
instruction, but the trap handler routine will not be traced. (The trap exception will be processed first, then the trace exception.)
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The vector number for the TRAP instruction is internally generated—part of the number
comes from the instruction itself. The trap vector number, PC value, and a copy of the SR
are saved on the supervisor stack. The saved PC value is the address of the instruction that
follows the instruction that generated the trap. For all instruction traps other than TRAP, a
pointer to the instruction causing the trap is also saved in the fifth and sixth words of the
exception stack frame.
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5.5.2.5 SOFTWARE BREAKPOINTS. To support hardware emulation, the CPU32+ must
provide a means of inserting breakpoints into target code and of announcing when a breakpoint is reached.
The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint when
the processor fetches from the illegal instruction exception vector location. Since the VBR
on the CPU32+ allows relocation of exception vectors, the exception vector address is not
a reliable indication of a breakpoint. CPU32+ breakpoint support is provided by extending
the function of a set of illegal instructions ($4848–$484F).
When a breakpoint instruction is executed, the CPU32+ performs a read from CPU space
$0, at a location corresponding to the breakpoint number. If this bus cycle is terminated by
BERR, the processor performs illegal instruction exception processing. If the bus cycle is
terminated by DSACKx, the processor uses the data returned to replace the breakpoint in
the instruction pipeline and begins execution of that instruction. See Section 4 Bus Operation for a description of CPU space operations.
5.5.2.6 HARDWARE BREAKPOINTS. The CPU32+ recognizes hardware breakpoint
requests. Hardware breakpoint requests do not force immediate exception processing, but
are left pending. An instruction breakpoint is not made pending until the instruction corresponding to the request is executed.
A pending breakpoint can be acknowledged between instructions or at the end of exception
processing. To acknowledge a breakpoint, the CPU performs a read from CPU space $0 at
location $1E (see Section 4 Bus Operation).
If the bus cycle terminates normally, instruction execution continues with the next instruction
as if no breakpoint request occurred. If the bus cycle is terminated by BERR, the CPU
begins exception processing. Data returned during this bus cycle is ignored.
Exception processing follows the regular sequence. Vector number 12 (offset $30) is internally generated. The PC of the executing instruction, the PC of the next instruction to be executed, and a copy of the SR are saved on the supervisor stack.
5.5.2.7 FORMAT ERROR. The processor checks certain data values for control operations.
The validity of the stack format code and, in the case of a bus cycle fault format, the version
number of the processor that generated the frame are checked during execution of the RTE
instruction. This check ensures that the program does not make erroneous assumptions
about information in the stack frame.
If the format of the control data is improper, the processor generates a format error exception. This exception saves a four-word format exception frame and then vectors through vec-
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tor table entry number 14. The stacked PC is the address of the RTE instruction that
discovered the format error.
5.5.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal
CPU32+ instruction, if it is a MOVEC instruction that contains an undefined register specification field in the first extension word, or if it contains an indexed addressing mode extension word with bits 5–4 = 00 or bits 3–0 ≠ 0000.
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If an illegal instruction is fetched during instruction execution, an illegal instruction exception
occurs. This facility allows the operating system to detect program errors or to emulate
instructions in software.
Word patterns with bits 15–12 = 1010 (referred to as A-line opcodes) are unimplemented
instructions. A separate exception vector (vector 10, offset $28) is given to unimplemented
instructions to permit efficient emulation.
Word patterns with bits 15–12 = 1111 (referred to as F-line opcodes) are used for M68000
family instruction set extensions. They can generate an unimplemented instruction exception caused by the first extension word of the instruction or by the addressing mode extension word. A separate F-line emulation vector (vector 11, offset $2C) is used for the
exception vector.
All unimplemented instructions are reserved for use by Motorola for enhancements and
extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal
on all M68000 family members. Those customers requiring the use of an unimplemented
opcode for synthesis of "custom instructions," operating system calls, etc., should use this
opcode.
Exception processing for illegal and unimplemented instructions is similar to that for traps.
The instruction is fetched and decoding is attempted. When the processor determines that
execution of an illegal instruction is being attempted, exception processing begins. No registers are altered.
Exception processing follows the regular sequence. The vector number is generated to refer
to the illegal instruction vector or in the case of an unimplemented instruction, to the corresponding emulation vector. The illegal instruction vector number, current PC, and a copy of
the SR are saved on the supervisor stack, with the saved value of the PC being the address
of the illegal or unimplemented instruction.
5.5.2.9 PRIVILEGE VIOLATIONS. To provide system security, certain instructions can be
executed only at the supervisor access level. An attempt to execute one of these instructions
at the user level will cause an exception. The privileged exceptions are as follows:
• AND Immediate to SR
• EOR Immediate to SR
• LPSTOP
• MOVE from SR
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• MOVE to SR
• MOVE USP
• MOVEC
• MOVES
• OR Immediate to SR
• RESET
• RTE
• STOP
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Exception processing for privilege violations is nearly identical to that for illegal instructions.
The instruction is fetched and decoded. If the processor determines that a privilege violation
has occurred, exception processing begins before instruction execution.
Exception processing follows the regular sequence. The vector number (8) is generated to
reference the privilege violation vector. Privilege violation vector offset, current PC, and SR
are saved on the supervisor stack. The saved PC value is the address of the first word of
the instruction causing the privilege violation.
5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility
to allow tracing of instruction execution. CPU32+ tracing also has the ability to trap on
changes in program flow. In trace mode, a trace exception is generated after each instruction executes, allowing a debugging program to monitor the execution of a program under
test. The T1 and T0 bits in the supervisor portion of the SR are used to control tracing.
When T1–T0 = 00, tracing is disabled, and instruction execution proceeds normally (see
Table 5-18).
Table 5-18. Tracing Control
T1
T0
Tracing Function
0
0
No tracing
0
1
Trace on change of flow
1
0
Trace on instruction execution
1
1
Undefined; reserved
When T1–T0 = 01 at the beginning of instruction execution, a trace exception will be generated if the PC changes sequence during execution. All branches, jumps, subroutine calls,
returns, and SR manipulations can be traced in this way. No exception occurs if a branch is
not taken.
When T1–T0 = 10 at the beginning of instruction execution, a trace exception will be generated when execution is complete. If the instruction is not executed, either because an interrupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception
is not generated.
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At the present time, T1–T0 = 11 is an undefined condition. It is reserved by Motorola for
future use.
Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction. Exception processing follows the regular
sequence; tracing is disabled so that the trace exception itself is not traced. A vector number
is generated to reference the trace exception vector. The address of the instruction that
caused the trace exception, the trace exception vector offset, the current PC, and a copy of
the SR are saved on the supervisor stack. The saved value of the PC is the address of the
next instruction to be executed.
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A trace exception can be viewed as an extension to the function of any instruction. If a trace
exception is generated by an instruction, the execution of that instruction is not complete
until the trace exception processing associated with it is also complete.
If an instruction is aborted by a bus error or address error exception, trace exception processing is deferred until the suspended instruction is restarted and completed normally. An
RTE from a bus error or address error will not be traced because of the possibility of continuing the instruction from the fault.
If an instruction is executed and an interrupt is pending on completion, the trace exception
is processed before the interrupt exception.
If an instruction forces an exception, the forced exception is processed before the trace
exception.
If an instruction is executed and a breakpoint is pending upon completion of the instruction,
the trace exception is processed before the breakpoint.
If an attempt is made to execute an illegal, unimplemented, or privileged instruction while
tracing is enabled, no trace exception will occur because the instruction is not executed. This
is particularly important to an emulation routine that performs an instruction function, adjusts
the stacked PC to beyond the unimplemented instruction, and then returns. The SR on the
stack must be checked to determine if tracing is on before the return is executed. If tracing
is on, trace exception processing must be emulated so that the trace exception handler can
account for the emulated instruction.
Tracing also affects normal operation of the STOP and LPSTOP instructions. If either
instruction begins execution with T1 set, a trace exception will be taken after the instruction
loads the SR. Upon return from the trace handler routine, execution will continue with the
instruction following STOP (LPSTOP), and the processor will not enter the stopped condition.
5.5.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable
interrupt vectors within each exception vector table. Careful use of multiple vector tables and
hardware chaining will permit a virtually unlimited number of peripherals to interrupt the processor.
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Interrupt recognition and subsequent processing are based on internal interrupt request signals (IRQ7–IRQ1) and the current priority set in SR priority mask I2–I0. Interrupt request
level 0 (IRQ7–IRQ1 negated) indicates that no service is requested. When an interrupt of
level 1 through 6 is requested via IRQ6–IRQ1, the processor compares the request level
with the interrupt mask to determine whether the interrupt should be processed. Interrupt
requests are inhibited for all priority levels less than or equal to the current priority. Level 7
interrupts are nonmaskable.
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IRQ7–IRQ1 are synchronized and debounced by input circuitry on two consecutive rising
edges of the processor clock.
Interrupt requests do not force immediate exception processing, but are left pending. A
pending interrupt is detected between instructions or at the end of exception processing—
all interrupt requests must be held asserted until they are acknowledged by the CPU. If the
priority of the interrupt is greater than the current priority level, exception processing begins.
Exception processing occurs as follows. First, the processor makes an internal copy of the
SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is set,
establishing supervisor access level, and bits T1 and T0 are cleared, disabling
tracing. Priority level is then set to the level of the interrupt, and the processor fetches a vector number from the interrupting device (CPU space $F). The fetch bus cycle is classified as
an interrupt acknowledge, and the encoded level number of the interrupt is placed on the
address bus.
If an interrupting device requests automatic vectoring, the processor generates a vector
number (25 to 31) determined by the interrupt level number.
If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken
to be spurious, and the spurious interrupt vector number (24) is generated.
The exception vector number, PC, and SR are saved on the supervisor stack. The saved
value of the PC is the address of the instruction that would have executed if the interrupt had
not occurred.
Priority level 7 interrupt is a special case. Level 7 interrupts are nonmaskable interrupts
(NMI). IRQ7 is a level sensitive input and must remain low until CPU32+ returns a n interrupt
acknowledge cycle for level 7 interrupt.
Many M68000 peripherals provide for programmable interrupt vector numbers to be used in
the system interrupt request/acknowledge mechanism. If the vector number is not initialized
after reset and if the peripheral must acknowledge an interrupt request, the peripheral
should return the uninitialized interrupt vector number (15).
See Section 4 Bus Operation for detailed information on interrupt acknowledge cycles.
5.5.2.12 RETURN FROM EXCEPTION. When exception stacking operations for all pending exceptions are complete, the processor begins execution of the handler for the last
exception processed. After the exception handler has executed, the processor must restore
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the system context in existence prior to the exception. The RTE instruction is designed to
accomplish this task.
When RTE is executed, the processor examines the stack frame on top of the supervisor
stack to determine if it is valid and determines what type of context restoration must be performed. See 5.5.4 CPU32+ Stack Frames for a description of stack frames.
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For a normal four-word frame, the processor updates the SR and PC with data pulled from
the stack, increments the SSP by 8, and resumes normal instruction execution. For a sixword frame, the SR and PC are updated from the stack, the active SSP is incremented by
12, and normal instruction execution resumes.
For a bus fault frame, the format value on the stack is first checked for validity. In addition,
the version number on the stack must match the version number of the processor that is
attempting to read the stack frame. The version number is located in the most significant
byte (bits 15–8) of the internal register word at location SP + $14 in the stack frame. The
validity check ensures that stack frame data will be properly interpreted in multiprocessor
systems.
If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus error exception is taken. Otherwise, the processor reads the entire frame into the proper internal registers, de-allocates the stack (12 words), and resumes normal processing. Bus error frames
for faults during exception processing require the RTE instruction to rewrite the faulted stack
frame. If an error occurs during any of the bus cycles required by rewrite, the processor
halts.
If a format error occurs during RTE execution, the processor creates a normal four-word
fault stack frame below the frame that it was attempting to use. If a bus error occurs, a buserror stack frame will be created. The faulty stack frame remains intact, so that it may be
examined and repaired by an exception handler or used by a different type of processor
(e.g., MC68010, MC68020, or future M68000 processor) in a multiprocessor system.
5.5.3 Fault Recovery
There are four phases of recovery from a fault: recognizing the fault, saving the processor
state, repairing the fault (if possible), and restoring the processor state. Saving and restoring
the processor state are described in the following paragraphs.
The stack contents are identified by the special status word (SSW). In addition to identifying
the fault type represented by the stack frame, the SSW contains the internal processor state
corresponding to the fault.
15
TP
5-48
14
MV
13
SZC1
12
TR
11
B1
10
B0
9
RR
8
RM
7
IN
6
RW
5
SZC0
4
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SIZ
2
1
FUNC
0
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TP—BERR Frame Type
The TP field defines the class of the faulted bus operation. Two bus error exception frame
types are defined. One is for faults on prefetch and operand accesses, and the other is
for faults during exception frame stacking.
0 = Operand or prefetch bus fault
1 = Exception processing bus fault
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MV—MOVEM in Progress
MV is set when the operand transfer portion of the MOVEM instruction is in progress at
the time of a bus fault. If a prefetch bus fault occurs while prefetching the MOVEM opcode
and extension word, both the MV and IN bits will be set.
0 = MOVEM was not in progress when fault occurred
1 = MOVEM was in progress when fault occurred
SZC1,SCZ0—Original Operand Size
The SZC1,SZC0 field specifies the size of the original bus cycle (i.e., the size bits of the
first cycle, when a transaction is divided into two or three cycles due to bus size or operand
address).
00 = Original operand size was long word
01 = Original operand size was byte
10 = Original operand size was word
11 = Unused, reserved
TR—Trace Pending
TR indicates that a trace exception was pending when a bus error exception was processed. The instruction that generated the trace will not be restarted upon return from the
exception handler. This includes MOVEM and released write bus errors indicated by the
assertion of either MV or RR in the SSW.
0 = Trace not pending
1 = Trace pending
B1—Breakpoint Channel 1 Pending
B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint
source) when a bus error exception was processed. Pending breakpoint status is stacked,
regardless of the type of bus error exception.
0 = Breakpoint not pending
1 = Breakpoint pending
B0—Breakpoint Channel 0 Pending
B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint
source) when the bus error exception was processed. Pending breakpoint status is
stacked, regardless of the type of bus error exception.
0 = Breakpoint not pending
1 = Breakpoint pending
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RR—Rerun Write Cycle after RTE
RR will be set if the faulted bus cycle was a released write. A released write is one that is
overlapped. If the write is completed (rerun) in the exception handler, the RR bit should
be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set upon return from the exception handler.
0 = Faulted cycle was read, RMW, or unreleased write
1 = Faulted cycle was a released write
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RM—Faulted Cycle Was Read-Modify-Write
Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking.
0 = Faulted cycle was non-RMW cycle
1 = Faulted cycle was either the read or write of an RMW cycle
IN—Instruction/Other
Instruction prefetch faults are distinguished from operand (both read and write) faults by
the IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was on
an instruction prefetch. IN is ignored during unstacking.
0 = Operand
1 = Prefetch
RW—Read/Write of Faulted Bus Cycle
Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this
bit, and write bus cycles will clear it. RW is reloaded into the bus controller if the RR bit is
set during unstacking.
0 = Faulted cycle was an operand write
1 = Faulted cycle was a prefetch or operand read
SIZ—Remaining Size of Faulted Bus Cycle
The SIZ field shows operand size remaining when a fault was detected. This field does
not indicate the initial size of the operand, nor does it necessarily indicate the proper status of a dynamically sized bus cycle. Dynamic sizing occurs on the external bus and is
transparent to the CPU. Byte size is shown only when the original operand was a byte.
The field is reloaded into the bus controller if the RR bit is set during unstacking. The SIZ
field is encoded as follows:
00 = Long word
01 = Byte
10 = Word
11 = Unused, reserved
FUNC—Function Code of Faulted Bus Cycle
The function code for the faulted cycle is stacked in the FUNC field of the SSW, which is
a copy of FC2–FC0 for the faulted bus cycle. This field is reloaded into the bus controller
if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored
during unstacking. Further discussion of the SSW is included in 5.5.3.1 Types of Faults.
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5.5.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that
faults on some bus cycles be treated differently than faults on other bus cycles. The CPU32+
defines four fault types: released write faults, faults during exception processing, faults during MOVEM operand transfer, and faults on any other bus cycle.
5.5.3.1.1 Type I—Released Write Faults. CPU32+ instruction pipelining can cause a final
instruction write to overlap the execution of a following instruction. A write that is overlapped
is called a released write. A released write fault occurs when a bus error or some other fault
occurs on the released write.
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Released write faults are taken at the next instruction boundary. The stacked PC is that of
the next unexecuted instruction. If a subsequent instruction attempts an operand access
while a released write fault is pending, the instruction is aborted and the write fault is
acknowledged. This action prevents the instruction from using stale data.
The SSW for a released write fault contains the following bit pattern:
15
14
13
12
11
10
9
8
7
6
5
0
0
SZC1
TR
B1
B0
1
0
0
0
SZC0
4
3
2
SIZ
0
FUNC
TR , B1, and B0 are set if the corresponding exception is pending when the bus error exception is taken. Status regarding the faulted bus cycle is reflected in the SZCx, SIZ, and FUNC
fields.
The remainder of the stack contains the PC of the next unexecuted instruction, the current
SR, the address of the faulted memory location, and the contents of the data buffer that was
to be written to memory. This data is written on the stack in the format depicted in Figure 515. When a released write fault exception handler executes, the machine will complete the
faulted write and then continue executing instructions wherever the PC indicates.
5.5.3.1.2 Type II—Prefetch, Operand, RMW, and MOVEP Faults. The majority of bus
error exceptions are included in this category—all instruction prefetches, all operand reads,
all RMW cycles, and all operand accesses resulting from execution of MOVEP (except the
last write of a MOVEP Rn,〈ea〉 or the last write of MOVEM, which are type I faults). The TAS,
MOVEP, and MOVEM instructions account for all operand writes not considered released
write faults.
All type II faults cause an immediate exception that aborts the current instruction. Any registers that were altered as the result of an EA calculation (i.e., postincrement or predecrement) are restored prior to processing the bus cycle fault.
The SSW for faults in this category contains the following bit pattern:
15
14
13
12
11
10
9
8
7
6
5
0
0
SZC1
0
B1
B0
0
RM
IN
RW
SZC0
4
3
SIZ
2
0
FUNC
The trace pending bit is always cleared since the instruction will be restarted upon return
from the handler. Saving a pending exception on the stack causes a trace exception to be
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taken prior to restarting the instruction. If the exception handler does not alter the stacked
SR trace bits, the trace is requeued when the instruction is started.
The breakpoint pending bits are stacked in the SSW, even though the instruction is restarted
upon return from the handler. This avoids problems with bus state analyzer equipment that
has been programmed to breakpoint only the first access to a specific location or to count
accesses to that location. If this response is not desired, the exception handler can clear the
bits before return. The RM, IN, RW, SZCx, FUNC, and SIZ fields reflect the type of bus cycle
that caused the fault. If the bus cycle was an RMW, the RM bit will be set, and the RW bit
will show whether the fault was on a read or write.
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5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer. Bus faults that occur as a
result of MOVEM operand transfer are classified as type III faults. MOVEM instruction
prefetch faults are type II faults.
Type III faults cause an immediate exception that aborts the current instruction. Registers
altered during execution of the faulted instruction are not restored prior to execution of the
fault handler. This includes any register predecremented as a result of the effective address
calculation or any register overwritten during instruction execution. Since postincremented
registers are not updated until the end of an instruction, the register retains its pre-instruction
value unless overwritten by operand movement.
The SSW for faults in this category contains the following bit pattern:
15
14
13
12
11
10
9
8
7
6
5
0
1
SZC1
TR
B1
B0
RR
0
IN
RW
SZC0
4
3
SIZ
2
0
FUNC
MV is set, indicating that MOVEM should be continued from the point where the fault
occurred upon return from the exception handler. TR, B1, and B0 are set if a corresponding
exception is pending when the bus error exception is taken. IN is set if a bus fault occurs
while prefetching an opcode or an extension word during instruction restart. RW, SZCx, SIZ,
and FUNC all reflect the type of bus cycle that caused the fault. All write faults have the RR
bit set to indicate that the write should be rerun upon return from the exception handler.
The remainder of the stack frame contains sufficient information to continue MOVEM with
operand transfer following a faulted transfer. The address of the next operand to be transferred, incremented or decremented by operand size, is stored in the faulted address location ($08). The stacked transfer counter is set to 16 minus the number of transfers attempted
(including the faulted cycle). Refer to Figure 5-12 for the stacking format.
5.5.3.1.4 Type IV—Faults During Exception Processing. The fourth type of fault occurs
during exception processing. If this exception is a second address or bus error, the machine
halts in the double bus fault condition. However, if the exception is one that causes a fouror six-word stack frame to be written, a bus cycle fault frame is written below the faulted
exception stack frame.
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The SSW for a fault within an exception contains the following bit pattern:
15
14
13
12
11
10
9
8
7
6
5
1
0
SZC1
TR
B1
B0
0
0
0
1
SZC0
4
3
SIZ
2
0
FUNC
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TR, B1, and B0 are set if a corresponding exception is pending when the bus error exception
is taken.
The contents of the faulted exception stack frame are included in the bus fault stack frame.
The pre-exception SR and the format/vector word of the faulted frame are stacked. The type
of exception can be determined from the format/vector word. If the faulted exception stack
frame contains six words, the PC of the instruction that caused the initial exception is also
stacked. This data is placed on the stack in the format shown in Figure 5-13. The return
address from the initial exception is stacked for RTE .
5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write
bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via
RTE.
Type II fault handlers must terminate with RTE, but specific requirements must also be met
before an instruction is restarted.
There are three varieties of type III operand fault recovery. The first is completion of an
instruction in software. The second is conversion to type II with restart via RTE. The third is
continuation from the fault via RTE.
5.5.3.2.1 Type I—Completing Released Writes via Software. To complete a bus cycle in
software, a handler must first read the SSW function code field to determine the appropriate
address space, access the fault address pointer on the stack, and then transfer data from
the stacked image of the output buffer to the fault address.
If the CPU32+ is configured to 16-bit operation, rather than 32-bit operation, on the internal
data bus, long operands require two bus accesses. A fault during the second access of a
long operand causes the SZCx bits in the SSW to be set to long word. The SIZ field indicates
remaining operand size. If operand coherency is important, the complete operand must be
rewritten. After a long operand is rewritten, the RR bit must be cleared. Failure to clear the
RR bit can cause the RTE instruction to rerun the bus cycle. Following rewrite, it is not necessary to adjust the PC (or other stack contents) before executing RTE.
5.5.3.2.2 Type I—Completing Released Writes via RTE. An exception handler can use
the RTE instruction to complete a faulted bus cycle. When RTE executes, the fault address,
data output buffer, PC, and SR are restored from the stack. Any pending breakpoint or trace
exceptions, as indicated by TR, B1, and B0 in the stacked SSW, are requeued during SSW
restoration. The RR bit in the SSW is checked during the unstacking operation; if it is set,
the RW, FUNC, and SIZ fields are restored and the released write cycle is rerun.
To maintain long-word operand coherence, stack contents must be adjusted prior to the
RTE execution. The fault address must be decremented by 2 if the SZCx bits are set to long
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word and SIZ indicates a remaining byte or word. SIZ must be set to long. All other fields
should be left unchanged. The bus controller uses the modified fault address and SIZ field
to rerun the complete released write cycle.
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Manipulating the stacked SSW can cause unpredictable results because RTE checks only
the RR bit to determine if a bus cycle must be rerun. Inadvertent alteration of the control bits
could cause the bus cycle to be a read instead of a write or could cause access to a different
address space than the original bus cycle. If the rerun bus cycle is a read, returned data will
be ignored.
5.5.3.2.3 Type II—Correcting Faults via RTE. Instructions aborted because of a type II
fault are restarted upon return from the exception handler. A fault handler must establish
safe restart conditions. If a fault is caused by a nonresident page in a demand-paged virtual
memory configuration, the fault address must be read from the stack, and the appropriate
page retrieved. An RTE instruction terminates the exception handler. After unstacking the
machine state, the instruction is refetched and restarted.
5.5.3.2.4 Type III—Correcting Faults via Software. Sufficient information is contained in
the stack frame to complete MOVEM in software. After the cause of the fault is corrected,
the faulted bus cycle must be rerun. Perform the following procedures to complete an
instruction through software:
A. Set Up for Rerun
1. Read the MOVEM opcode and extension from locations pointed to by stack frame PC
and PC + 2. The EA need not be recalculated since the next operand address
is saved in the stack frame. However, the opcode EA field must be examined to determine how to update the address register and PC when the instruction is complete.
2. Adjust the mask to account for operands already transferred. Subtract the stacked operand transfer count from 16 to obtain the number of operands transferred. Scan the
mask using this count value. Each time a set bit is found, clear it and decrement the
counter. When the count is zero, the mask is ready for use.
3. Adjust the operand address. If the predecrement addressing mode is in effect, subtract
the operand size from the stacked value; otherwise, add the operand size to the
stacked value.
B. Rerun Instruction
1. Scan the mask for set bits. Read/write the selected register from/to the operand address as each bit is found.
2. As each operand is transferred, clear the mask bit and increment (decrement) the operand address. When all bits in the mask are cleared, all operands have been transferred.
3. If the addressing mode is predecrement or postincrement, update the register to complete the execution of the instruction.
4. If TR is set in the stacked SSW, create a six-word stack frame and execute the trace
handler. If either B1 or B0 is set in the SSW, create another six-word stack frame and
execute the hardware breakpoint handler.
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5. De-allocate the stack and return control to the faulted program.
5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart. In some situations it
may be necessary to rerun all the operand transfers for a faulted instruction rather than continue from a faulted operand. Clearing the MV bit in the stacked SSW converts a type III fault
into a type II fault. Consequently, MOVEM, like all other type II exceptions, will be restarted
upon return from the exception handler. When a fault occurs after an operand has transferred, that transfer is not "undone". However, these memory locations are accessed a second time when the instruction is restarted. If a register used in an EA calculation is
overwritten before a fault occurs, an incorrect EA is calculated upon instruction restart.
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5.5.3.2.6 Type III—Correcting Faults via RTE. The preferred method of MOVEM bus fault
recovery is to correct the cause of the fault and then execute an RTE instruction without
altering the stack contents.
The RTE recognizes that MOVEM was in progress when a fault occurred, restores the
appropriate machine state, refetches the instruction, repeats the faulted transfer, and continues the instruction.
MOVEM is the only instruction continued upon return from an exception handler. Although
the instruction is refetched, the EA is not recalculated, and the mask is rescanned the same
number of times as before the fault. Modifying the code prior to RTE can cause unexpected
results.
5.5.3.2.7 Type IV—Correcting Faults via Software. Bus error exceptions can occur during exception processing while the processor is fetching an exception vector or while it is
stacking. The same stack frame and SSW are used in both cases, but each has a distinct
fault address. The stacked faulted exception format/vector word identifies the type of faulted
exception and the contents of the remainder of the frame. A fault address corresponding to
the vector specified in the stacked format/vector word indicates that the processor could not
obtain the address of the exception handler.
A bus error exception handler should execute RTE after correcting a fault. RTE restores the
internal machine state, fetches the address of the original exception handler, recreates the
original exception stack frame, and resumes execution at the exception handler address.
If the fault is intractable, the exception handler should rewrite the faulted exception stack
frame at SP + $14 + $06 and then jump directly to the original exception handler. The stack
frame can be generated from the information in the bus error frame: the pre-exception SR
(SP + $0C), the format/vector word (SP + $0E), and, if the frame being written is a six-word
frame, the PC of the instruction causing the exception (SP + $10). The return PC value is
available at SP + $02.
A stacked fault address equal to the current SP may indicate that, although the first exception received a bus error while stacking, the bus error exception stacking successfully completed. This occurrence is extremely improbable, but the CPU32+ supports recovery from it.
Once the exception handler determines that the fault has been corrected, recovery can proceed as described previously. If the fault cannot be corrected, move the supervisor stack to
another area of memory, copy all valid stack frames to the new stack, create a faulted
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exception frame on top of the stack, and resume execution at the exception handler
address.
5.5.4 CPU32+ Stack Frames
The CPU32+ generates three different stack frames: four-word frames, six-word frames,
and twelve-word bus error frames.
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5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format
error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation
exceptions. Depending on the exception type, the PC value is either the address of the next
instruction to be executed or the address of the instruction that caused the exception (see
Figure 5-12).
15
0
SP ⇒
STATUS REGISTER
+$02
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
+$06
0
0
0
0
VECTOR OFFSET
Figure 5-12. Format $0—Four-Word Stack Frame
5.5.4.2 SIX-WORD STACK FRAME. This stack frame (see Figure 5-13) is created by
instruction-related traps, which include CHK, CHK2, TRAPcc, TRAPV, and divide-by-zero,
and by trace exceptions. The faulted instruction PC value is the address of the instruction
that caused the exception. The next PC value (the address to which RTE returns) is the
address of the next instruction to be executed.
15
0
SP ⇒
STATUS REGISTER
NEXT INSTRUCTION PROGRAM COUNTER HIGH
+$02
NEXT INSTRUCTION PROGRAM COUNTER LOW
+$06
+$08
0
0
1
0
VECTOR OFFSET
FAULTED INSTRUCTION PROGRAM COUNTER HIGH
FAULTED INSTRUCTION PROGRAM COUNTER LOW
Figure 5-13. Format $2—Six-Word Stack Frame
Hardware breakpoints also utilize this format. The faulted instruction PC value is the address
of the instruction executing when the breakpoint was sensed. Usually this is the address of
the instruction that caused the breakpoint, but, because released writes can overlap following instructions, the faulted instruction PC may point to an instruction following the instruction that caused the breakpoint. The address to which RTE returns is the address of the next
instruction to be executed.
5.5.4.3 BUS ERROR STACK FRAME. This stack frame is created when a bus cycle fault
is detected. The CPU32+ bus error stack frame differs significantly from the equivalent stack
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frames of other M68000 family members. The only internal machine state required in the
CPU32+ stack frame is the bus controller state at the time of the error and a single register.
Bus operation in progress at the time of a fault is conveyed by the SSW.
15
TP
14
MV
13
SZC1
12
TR
11
B1
10
B0
9
RR
8
RM
7
IN
6
RW
5
SZC0
4
3
SIZ
2
1
FUNC
0
The bus error stack frame is 12 words in length. There are three variations of the frame, each
distinguished by different values in the SSW TP and MV fields.
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An internal transfer count register appears at location SP + $14 in all bus error stack frames.
The register contains an 8-bit microcode revision number and, for type III faults, an 8-bit
transfer count. Register format is shown in Figure 5-14.
15
8
MICROCODE REVISION NUMBER
7
0
TRANSFER COUNT
Figure 5-14. Internal Transfer Count Register
The microcode revision number is checked before a bus error stack frame is restored via
RTE. In a multiprocessor system, this check ensures that a processor using stacked information is at the same revision level as the processor that created it.
The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit is
set, the least significant byte of the internal register is reloaded into the MOVEM transfer
counter during RTE execution.
For faults occurring during normal instruction execution (both prefetches and non-MOVEM
operand accesses), SSW TP,MV = 00. Stack frame format is shown in Figure 5-15.
Faults that occur during the operand portion of the MOVEM instruction are identified by SSW
TP,MV = 01. Stack frame format is shown in Figure 5-16.
When a bus error occurs during exception processing, SSW TP,MV = 10. The frame shown
in Figure 5-17 is written below the faulting frame. Stacking begins at the address pointed to
by SP – 6 (SP value is the value before initial stacking on the faulted frame).
The frame can have either four or six words, depending on the type of error. Four-word stack
frames do not include the faulted instruction PC. (The internal transfer count register is
located at SP + $10 and the SSW is located at SP + $12.)
The fault address of a dynamically sized bus cycle is the address of the upper byte, regardless of the byte that caused the error.
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15
0
SP ⇒
STATUS REGISTER
+$02
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
+$06
1
1
0
0
+$08
VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
+$0C
DBUF HIGH
DBUF LOW
+$10
CURRENT INSTRUCTION PROGRAM COUNTER HIGH
CURRENT INSTRUCTION PROGRAM COUNTER LOW
+$14
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+$16
INTERNAL TRANSFER COUNT REGISTER
0
0
SPECIAL STATUS WORD
Figure 5-15. Format $C—BERR Stack for Prefetches and Operands
15
0
SP ⇒
+$02
+$06
+$08
1
1
0
1
0
0
+$0C
+$10
+$14
+$16
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUF HIGH
DBUF LOW
CURRENT INSTRUCTION PROGRAM COUNTER HIGH
CURRENT INSTRUCTION PROGRAM COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
SPECIAL STATUS WORD
Figure 5-16. Format $C—BERR Stack on MOVEM Operand
15
0
SP ⇒
STATUS REGISTER
+$02
NEXT INSTRUCTION PROGRAM COUNTER HIGH
NEXT INSTRUCTION PROGRAM COUNTER LOW
+$06
1
1
+$08
0
0
VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
+$0C
PRE-EXCEPTION STATUS REGISTER
FAULTED EXCEPTION FORMAT/VECTOR WORD
+$10
FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY)
FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY)
+$14
+$16
INTERNAL TRANSFER COUNT REGISTER
1
0
SPECIAL STATUS WORD
Figure 5-17. Format $C—Four- and Six-Word BERR Stack
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CPU32+
5.6 DEVELOPMENT SUPPORT
All M68000 family members have the following special features that facilitate applications
development.
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Trace on Instruction Execution—All M68000 processors include an instruction-by-instruction tracing facility to aid in program development. The MC68020, MC68030, and CPU32+
can also trace those instructions that change program flow. In trace mode, an exception is
generated after each instruction is executed, allowing a debugger program to monitor execution of a program under test. See 5.5.2.10 Tracing for more information.
Breakpoint Instruction—An emulator can insert software breakpoints into target code to indicate when a breakpoint occurs. On the MC68010, MC68020, MC68030, and CPU32+, this
function is provided via illegal instructions ($4848–$484F) that serve as breakpoint instructions. See 5.5.2.5 Software Breakpoints for more information.
Unimplemented Instruction Emulation—When an attempt is made to execute an illegal
instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, Aline) utilize separate exception vectors to permit efficient emulation of unimplemented
instructions in software. See 5.5.2.8 Illegal or Unimplemented Instructions for more information.
5.6.1 CPU32+ Integrated Development Support
In addition to standard MC68000 family capabilities, the CPU32+ has features to support
advanced integrated system development. These features include background debug
mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a single-chip environment.
5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor
systems
generally provide a debugger, implemented in software, for system analysis at the lowest
level. The BDM on the CPU32+ is unique because the debugger is implemented in CPU
microcode.
BDM incorporates a full set of debug options—registers can be viewed and/or altered, memory can be read or written, and test features can be invoked.
A resident debugger simplifies implementation of an in-circuit emulator. In a common setup
(see Figure 5-18), emulator hardware replaces the target system processor. A complex,
expensive pod-and-cable interface provides a communication path between target system
and emulator.
IN-CIRCUIT
EMULATOR
TARGET
SYSTEM
TARGET
MCU
Figure 5-18. In-Circuit Emulator Configuration
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By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for in-circuit
emulation. The processor remains in the target system (see Figure 5-19), and the interface
is simplified. The BSA monitors target processor operation and the on-chip debugger controls the operating environment. Emulation is much closer to target hardware; thus, many
interfacing problems (i.e., limitations on high-frequency operation, AC and DC parametric
mismatches, and restrictions on cable length) are minimized.
TARGET
SYSTEM
BUS STATE
ANALYZER
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TARGET
MCU
Figure 5-19. Bus State Analyzer Configuration
5.6.1.2 DETERMINISTIC OPCODE TRACKING OVERVIEW. CPU32+ function code outputs are augmented by three supplementary signals that monitor the instruction pipeline.
The IFETCH output signal identifies bus cycles in which data is loaded into the pipeline and
signals pipeline flushes. The IPIPE1, IPIPE0 output signals indicate when each mid-instruction pipeline advance occurs and when instruction execution begins. These signals allow a
BSA to synchronize with instruction stream activity. Refer to 5.6.3 Deterministic Opcode
Tracking for complete information.
5.6.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input
and an on-chip hardware breakpoint capability permit breakpoint trap on any memory
access. Off-chip address comparators will not detect breakpoints on internal accesses
unless show cycles are enabled. Breakpoints on prefetched instructions, which are flushed
from the pipeline before execution, are not acknowledged, but operand breakpoints are
always acknowledged. Acknowledged breakpoints can initiate either exception processing
or BDM. See 5.5.2.6 Hardware Breakpoints for more information.
5.6.2 Background Debug Mode
BDM is an alternate CPU32+ operating mode. During BDM, normal instruction execution is
suspended, and special microcode performs debugging functions under external control.
Figure 5-20 is a BDM block diagram.
BDM can be initiated in several ways—by externally generated breakpoints, by internal
peripheral breakpoints, by the background instruction (BGND), or by catastrophic exception
conditions. While in BDM, the CPU32+ ceases to fetch instructions via the parallel bus and
communicates with the development system via a dedicated, high-speed, SPI-type serial
command interface.
5.6.2.1 ENABLING BDM. Accidentally entering BDM in a nondevelopment environment
could lock up the CPU32+ since the serial command interface would probably not be available. For this reason, BDM is enabled during reset via the BKPT signal.
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BDM operation is enabled when BKPT is asserted (low) at the rising edge of RESET. BDM
remains enabled until the next system reset. A high BKPT on the trailing edge of RESET
disables BDM. BKPT is relatched on each rising transition of RESET. BKPT is synchronized
internally and must be held low for at least two clock(four clocks for RESETS)cycles prior to
negation of RESETH.
SERIAL
INTERFACE
IPIPE/DSO
MICROCODE
SEQUENCER
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IFETCH/DSI
IRC
IRB
IR
BERR
BERR
BERR
BKPT
BKPT
BKPT
BKPT/DSCLK
BUS
CONTROL
DATA BUS
BERR
FREEZE
EXECUTION
UNIT
ADDRESS BUS
Figure 5-20. BDM Block Diagram
BDM enable logic must be designed with special care. If hold time on BKPT (after the trailing
edge of RESET) extends into the first bus cycle following reset, this bus cycle could be
tagged with a breakpoint. Refer to Section 4 Bus Operation for timing information.
5.6.2.2 BDM SOURCES. When BDM is enabled, any of several sources can cause the transition from normal mode to BDM. These sources include external BKPT hardware, the
BGND instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not
enabled when an exception condition occurs, the exception is processed normally. Table 519 summarizes the processing of each source for both enabled and disabled cases. Note
that the BKPT instruction never causes a transition into BDM.
Table 5-19. BDM Source Summary
Source
MOTOROLA
BDM Enabled
BDM Disabled
BKPT
Background
Breakpoint Exception
Double Bus Fault
Background
Halted
BGND Instruction
Background
Illegal Instruction
BKPT Instruction
Opcode Substitution/
Illegal Instruction
Opcode Substitution/
Illegal Instruction
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5.6.2.2.1 External BKPT Signal. Once enabled, BDM is initiated whenever assertion of
BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has the same timing relationship to the data strobe trailing edge as
read cycle data. There is no breakpoint acknowledge bus cycle when BDM is entered.
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5.6.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32+ defines $4AFA (BGND) to be a BDM entry point when BDM is
enabled. If BDM is disabled, an illegal instruction trap is acknowledged. Illegal instruction
traps are discussed in 5.5.2.8 Illegal or Unimplemented Instructions.
5.6.2.2.3 Double Bus Fault. The CPU32+ normally treats a double bus fault (two bus faults
in succession) as a catastrophic system error and halts. When this condition occurs during
initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected. In BDM, the fault can be temporarily bypassed so that its origin can be isolated and eliminated.
5.6.2.3 ENTERING BDM. When the processor detects a BKPT or a double bus fault or
decodes a BGND instruction, it suspends instruction execution and asserts the FREEZE
output. FREEZE assertion is the first indication that the processor has entered BDM. Once
FREEZE has been asserted, the CPU enables the serial communication hardware and
awaits a command.
The CPU writes a unique value indicating the source of BDM transition into temporary register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP and determine the source (see Table 5-20) by issuing a read system register command (RSREG).
ATEMP is used in most debugger commands for temporary storage—it is imperative that
the RSREG command be the first command issued after transition into BDM.
Table 5-20. Polling the BDM Entry Source
Source
ATEMP 31–16
ATEMP 15–0
Double Bus Fault
SSW*
$FFFF
BGND Instruction
$0000
$0001
Hardware Breakpoint
$0000
$0000
*SSW is described in detail in 5.5.3 Fault Recovery.
A double bus fault during initial SP/PC fetch sequence is distinguished by a value of
$FFFFFFFF in the current instruction PC. At no other time will the processor write an odd
value into this register.
5.6.2.4 COMMAND EXECUTION. Figure 5-21 summarizes BDM command execution.
Commands consist of one 16-bit operation word and can include one or more 16-bit extension words. Each incoming word is read as it is assembled by the serial interface. The microcode routine corresponding to a command is executed as soon as the command is
complete. Result operands are loaded into the output shift register to be shifted out as the
next command is read. This process is repeated for each command until the CPU returns to
normal operating mode.
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5.6.2.5 BDM REGISTERS. BDM processing uses three special-purpose registers to track
program context during development. A description of each register follows.
5.6.2.5.1 Fault Address Register (FAR). The FAR contains the address of the faulting bus
cycle immediately following a bus or address error. This address remains available until
overwritten by a subsequent bus cycle. Following a double bus fault, the FAR contains the
address of the last bus cycle. The address of the first fault (if one occurred) is not visible to
the user.
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5.6.2.5.2 Return Program Counter (RPC). The RPC points to the location where fetching
will commence after transition from BDM to normal mode. This register should be accessed
to change the flow of a program under development. Changing the RPC to an odd value will
cause an address error when normal mode prefetching begins.
5.6.2.5.3 Current Instruction Program Counter (PCC). The PCC holds a pointer to the
first word of the last instruction executed prior to transition into BDM. Due to instruction pipelining, the instruction pointed to may not be the instruction that caused the transition. An
example is a breakpoint on a released write. The bus cycle may overlap as many as two
subsequent instructions before stalling the instruction sequencer. A BKPT asserted during
this cycle will not be acknowledged until the end of the instruction executing at completion
of the bus cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immediately out of reset.
5.6.2.6 RETURNING FROM BDM. BDM is terminated when a resume execution (GO) or
call user code (CALL) command is received. Both GO and CALL flush the instruction pipeline and prefetch instructions from the location pointed to by the RPC.
The return PC and the memory space referred to by the SR SUPV bit reflect any changes
made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation of
FREEZE, the serial subsystem is disabled, and the signals revert to IPIPE and IFETCH
functionality.
5.6.2.7 SERIAL INTERFACE. Communication with the CPU32+ during BDM occurs via a
dedicated serial interface, which shares pins with other development features. The BKPT
signal becomes the DSCLK; DSI is received on IFETCH, and DSO is transmitted on IPIPE.
The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral
interface (SPI) protocol. The development system serves as the master of the serial link
since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32+
system clock, development system serial logic is unhindered by the operating frequency of
the target processor. Operable frequency range of the serial clock is from DC to one-half the
processor system clock frequency
The serial interface operates in full-duplex mode—i.e., data is transmitted and received
simultaneously by both master and slave devices. In general, data transitions occur on the
falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted MSB first and is latched on the rising edge of DSCLK.
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.
CPU32 ACTIVITY
DEVELOPMENT SYSTEM ACTIVITY
ENTER (BDM)
• ASSERT FREEZE SIGNAL
• WAIT FOR COMMAND
SEND INITIAL COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT OUT 17 BITS
• DISABLE SHIFT CLOCK
EXECUTE COMMAND
• LOAD: NOT READY/ RESPONSE
• PERFORM COMMAND
• STORE RESULTS
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READ RESULTS/NEW COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT IN/OUT 17 BITS
• DISABLE SHIFT CLOCK
• READ RESULT REGISTER
YES
IF RESULTS =
"NOT READY"
NO
CONTINUE
Figure 5-21. BDM Command Execution Flowchart
The serial data word is 17 bits wide—16 data bits and a status/control (S/C) bit.
16
15
0
S/C
DATA FIELD
Bit 16 indicates the status of CPU-generated messages as listed in Table 5-21
Command and data transfers initiated by the development system should clear bit 16. The
current implementation ignores this bit; however, Motorola reserves the right to use this bit
for future enhancements.
Table 5-21. CPU Generated Message Encoding
5-64
Encoding
Data
Message Type
0
xxxx
Valid Data Transfer
0
FFFF
Command Complete; Status OK
1
0000
Not Ready with Response; Come Again
1
0001
BERR Terminated Bus Cycle; Data Invalid
1
FFFF
Illegal Command
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5.6.2.7.1 CPU Serial Logic. CPU32+ serial logic, shown in the left-hand portion of Figure
5-22, consists of transmit and receive shift registers and of control logic that includes synchronization, serial clock generation circuitry, and a received bit counter.
Both DSCLK and DSI are synchronized to on-chip clocks, thereby minimizing the chance of
propagating metastable states into the serial state machine. Data is sampled during the high
phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made available to
internal logic. If there is no synchronization between CPU32+ and development system
hardware, the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT.
CPU
DEVELOPMENT SYSTEM
INSTRUCTION
REGISTER BUS
DATA
16
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16
0
RCV DATA LATCH
SERIAL IN
PARALLEL OUT
COMMAND LATCH
DSI
PARALLEL IN
SERIAL OUT
DSO
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
16
STATUS
RESULT LATCH
EXECUTION
UNIT
16
STATUS
SYNCHRONIZE
MICROSEQUENCER
CONTROL
LOGIC
DSCLK
DATA
CONTROL
LOGIC
SERIAL
CLOCK
Figure 5-22. Debug Serial I/O Block Diagram
The serial state machine begins a sequence of events based on the rising edge of the synchronized DSCLK (see Figure 5-23). Synchronized serial data is transferred to the input shift
register, and the received bit counter is decremented. One-half clock period later, the output
shift register is updated, bringing the next output bit to the DSO signal. DSO changes relative to the rising edge of DSCLK and does not necessarily remain stable until the falling edge
of DSCLK.
One clock period after the synchronized DSCLK has been seen internally, the updated
counter value is checked. If the counter has reached zero, the receive data latch is updated
from the input shift register. At this same time, the output shift register is reloaded with the
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“not ready/come again” response. Once the receive data latch has been loaded, the CPU is
released to act on the new data. Response data overwrites the “not ready” response when
the CPU has completed the current operation.
Data written into the output shift register appears immediately on the DSO signal. In general,
this action changes the state of the signal from a high (“not ready” response status bit) to a
low (valid data status bit) logic level. However, this level change only occurs if the command
completes successfully. Error conditions overwrite the “not ready” response with the appropriate response that also has the status bit set.
CLKOUT
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FREEZE
DSCLK
DSI
SAMPLE
WINDOW
INTERNAL
SYNCHRONIZED
DSCLK
INTERNAL
SYNCHRONIZED
DSI
DSO
CLKOUT
Figure 5-23. Serial InterfaceTiming Diagram
A user can use the state change on DSO to signal hardware that the next serial transfer may
begin. A timeout of sufficient length to trap error conditions that do not change the state of
DSO should also be incorporated into the design. Hardware interlocks in the CPU prevent
result data from corrupting serial transfers in progress.
5.6.2.7.2 Development System Serial Logic. The development system, as the master of
the serial data link, must supply the serial clock. However, normal and BDM operations
could interact if the clock generator is not properly designed.
Breakpoint requests are made by asserting BKPT to the low state in either of two ways. The
primary method is to assert BKPT during a single bus cycle for which an exception is
desired. Another method is to assert BKPT, then continue to assert it until the CPU32+
responds by asserting FREEZE. This method is useful for forcing a transition into BDM when
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the bus is not being monitored. Each method requires a slightly different serial logic design
to avoid spurious serial clocks.
Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle.
SHIFT_CLK
FORCE_BGND
BKPT_TAG
BKPT
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FREEZE
Figure 5-24. BKPT Timing for Single Bus Cycle
Figure 5-25 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock
is left high after the final shift of each transfer. This technique eliminates the possibility of
accidentally tagging the prefetch initiated at the conclusion of a BDM session. As mentioned
previously, all timing within the CPU is derived from the rising edge of the clock; the falling
edge is effectively ignored.
SHIFT_CLK
FORCE_BGND
BKPT_TAG
BKPT
FREEZE
Figure 5-25. BKPT Timing for Forcing BDM
Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As the
name implies, FORCE_BGND is used to force a transition into BDM by the assertion of
BKPT. FORCE_BGND can be a short pulse or can remain asserted until FREEZE is
asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is
applied.
BKPT_TAG
SHIFT_CLK
BKPT/DSCLK
S1
RESET
FORCE_BGND
Q
S2
R
Q
Figure 5-26. BKPT/DSCLK Logic Diagram
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BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the
assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32+ as the first
DSCLK.
DSCLK, the gated serial clock, is normally high, but it pulses low for each bit to be transferred. At the end of the seventeenth clock period, it remains high until the start of the next
transmission. Clock frequency is implementation dependent and may range from DC to the
maximum specified frequency. Although performance considerations might dictate a hardware implementation, software solutions can be used provided serial bus timing is maintained.
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5.6.2.8 COMMAND SET. The following paragraphs describe the command set available in
BDM.
5.6.2.8.1 Command Format. The following standard bit .command format is utilized by all
BDM commands.
15
10
OPERATION
9
8
0
R/W
7
6
OP SIZE
5
4
3
0
0
A/D
2
0
REGISTER
EXTENSION WORD(S)
Bits 15–10—Operation Field
The operation field specifies the commands. This 6-bit field provides for a maximum of 64
unique commands.
R/W Field
The R/W field specifies the direction of operand transfer. When the bit is set, the transfer
is from theCPU to the development system. When the bit is cleared, data is written to the
CPU or to memory from the development system.
Operand Size
For sized operations, this field specifies the operand data size. All addresses are expressed as 32-bit absolute values. The size field is encoded as listed in Table 5-22..
Table 5-22. Size Field Encoding
Encoding
Operand Size
00
Byte
01
Word
10
Long
11
Reserved
Address/Data (A/D) Field
The A/D field is used by commands that operate on address and data registers. It determines whether the register field specifies a data or address register. One indicates an address register; zero indicates a data register. For other commands, this field may be
interpreted differently.
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Register Field:
In most commands, this field specifies the register number for operations performed on
an address or data register.
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Extension Word(s) (as required):
At this time, no command requires an extension word to specify fully the operation to be
performed, but some commands require extension words for addresses or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Immediate data can be either one or two words in length—byte and word data
each require a single extension word; long-word data requires two words. Both operands
and addresses are transferred most significant word first.
5.6.2.8.2 Command Sequence Diagram. A command sequence diagram (see Figure 527) illustrates the serial bus traffic for each command. Each bubble in the diagram represents a single 17-bit transfer across the bus. The top half in each diagram corresponds to
the data transmitted by the development system to the CPU; the bottom half corresponds to
the data returned by the CPU in response to the development system commands. Command and result transactions are overlapped to minimize latency.
The cycle in which the command is issued contains the development system command
mnemonic (in this example, "read memory location"). During the same cycle, the CPU
responds with either the lowest order results of the previous command or with a command
complete status (if no results were required).
During the second cycle, the development system supplies the high-order 16 bits of the
memory address. The CPU returns a "not ready" response unless the received command
was decoded as unimplemented, in which case the response data is the illegal command
encoding. If an illegal command response occurs, the development system should retransmit the command.
NOTE
The “not ready” response can be ignored unless a memory bus
cycle is in progress. Otherwise, the CPU can accept a new serial
transfer with eight system clock periods.
In the third cycle, the development system supplies the low-order 16 bits of a memory
address. The CPU always returns the “not ready” response in this cycle. At the completion
of the third cycle, the CPU initiates a memory read operation. Any serial transfers that begin
while the memory access is in progress return the “not ready” response.
Results are returned in the two serial transfer cycles following the completion of memory
access. The data transmitted to the CPU during the final transfer is the opcode for the following command. Should a memory access generate either a bus or address error, an error
status is returned in place of the result data.
5.6.2.8.3 Command Set Summary. The BDM command set is summarized in Table 5-23.
Subsequent paragraphs contain detailed descriptions of each command.
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COMMANDS TRANSMITTED TO THE CPU32
COMMAND CODE TRANSMITTED DURING THIS CYCLE
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
LOW-ORDER 16 BITS OF MEMORY ADDRESS
NONSERIAL-RELATED ACTIVITY
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
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READ (LONG)
???
MS ADDR
"NOT READY"
LS ADDR
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
READ
MEMORY
LOCATION
XXX
"NOT READY"
NEXT
COMMAND
CODE
XXX
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR/AERR
NEXT CMD
"NOT READY"
DATA UNUSED FROM
THIS TRANSFER
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY CPU32
RESULTS FROM PREVIOUS COMMAND
SEQUENCE TAKEN IF BUS ERROR
OR ADDRESS ERROR OCCURS ON
MEMORY ACCESS
HIGH- AND LOW-ORDER
16 BITS OF RESULT
RESPONSES FROM THE CPU
Figure 5-27. Command Sequence Diagram
Table 5-23. BDM Command Summary
Command
Mnemonic
Description
Read A/D Register
the selected address or data register and return the results via the seRAREG/RDREG Read
rial interface.
Write A/D Register
WAREG/WDREG The data operand is written to the specified address or data register.
The specified system control register is read. All registers that can be read
in supervisor mode can be read in BDM.
Read System Register
Write System Register
WSREG
Read Memory Location
READ
Read the sized data at the memory location specified by the long-word address. The SFC register determines the address space accessed.
Write Memory Location
WRITE
Write the operand data to the memory location specified by the long-word
address. The DFC register determines the address space accessed.
Dump Memory Block
DUMP
Used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block
and to retrieve the first result. Subsequent operands are retrieved with the
DUMP command.
Fill Memory Block
FILL
Used in conjunction with the WRITE command to fill large blocks of memory.
An initial WRITE is executed to set up the starting address of the block and
to supply the first operand. Subsequent operands are written with the FILL
command.
Resume Execution
GO
The pipeline is flushed and refilled before resuming instruction execution at
the return PC.
Call User Code
CALL
Current PC is stacked at the location of the current SP. Instruction execution
begins at user patch code.
Reset Peripherals
RST
Asserts RESET for 512 clock cycles. The CPU is not reset by this command.
Synonymous with the CPU RESET instruction.
No Operation
NOP
NOP performs no operation and may be used as a null command.
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The operand data is written into the specified system control register.
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5.6.2.8.4 Read A/D Register (RAREG/RDREG). Read the selected address or data register and return the results via the serial interface.
Command Format:
15
0
14
0
13
1
12
0
11
0
10
0
9
0
8
1
7
1
6
0
5
0
4
0
3
A/D
2
1
REGISTER
0
Command Sequence:
RDREG/RAREG
???
XXX
MS RESULT
NEXT CMD
LS RESULT
Freescale Semiconductor, Inc...
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
Operand Data:
None
Result Data:
The contents of the selected register are returned as a long-word value. The data is returned most significant word first.
5.6.2.8.5 Write A/D Register (WAREG/WDREG). The operand (long-word) data is written
to the specified address or data register. All 32 bits of the register are altered by the write.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
1
0
0
0
0
0
1
0
0
0
A/D
2
0
REGISTER
Command Sequence:
WDREG/WAREG
???
MS DATA
"NOT READY"
LS DATA
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
NEXT CMD
"CMD COMPLETE"
Operand Data:
Long-word data is written into the specified address or data register. The data is supplied
most significant word first.
Result Data:
Command complete status ($0FFFF) is returned when register write is complete.
5.6.2.8.6 Read System Register (RSREG). The specified system control register is read.
All registers that can be read in supervisor mode can be read in BDM. Several internal temporary registers are also accessible.
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Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
0
0
1
0
0
1
0
0
1
0
0
0
3
0
REGISTER
Command Sequence:
Freescale Semiconductor, Inc...
RSREG
???
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
Operand Data:
None
Result Data:
Always returns 32 bits of data, regardless of the size of the register being read. If the register is less than 32 bits, the result is returned zero extended.
Register Field:
The system control register is specified by the register field (see Table 5-24).
Table 5-24. Register Field for RSREG and WSREG
System Register
Select Code
Return Program Counter (RPC)
0000
Current Instruction Program Counter (PCC)
0001
Status Register (SR)
1011
User Stack Pointer (USP)
1100
Supervisor Stack Pointer (SSP)
1101
Source Function Code Register (SFC)
1110
Destination Function Code Register (DFC)
1111
Temporary Register A (ATEMP)
1000
Fault Address Register (FAR)
1001
Vector Base Register (VBR)
1010
5.6.2.8.7 Write System Register (WSREG). Operand data is written into the specified system control register. All registers that can be written in supervisor mode can be written in
BDM. Several internal temporary registers are also accessible.
Command Format:
15
14
13
12
11
10
9
8
7
6
5
4
0
0
1
0
0
1
0
0
1
0
0
0
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3
0
REGISTER
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Command Sequence:
WSREG
???
MS DATA
"NOT READY"
LS DATA
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
NEXT CMD
"CMD COMPLETE"
Operand Data:
The data to be written into the register is always supplied as a 32-bit long word. If the register is less than 32 bits, the least significant word is used.
Freescale Semiconductor, Inc...
Result Data:
“Command complete” status is returned when register write is complete.
Register Field:
The system control register is specified by the register field (see Table 5-24). The FAR is
a read-only register—any write to it is ignored.
5.6.2.8.8 Read Memory Location (READ). Read the sized data at the memory location
specified by the long-word address. Only absolute addressing is supported. The SFC register determines the address space accessed. Valid data sizes include byte, word, or long
word.
Command Format:
15
0
14
0
13
0
12
1
11
1
10
0
9
0
8
1
7
6
OP SIZE
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
READ (B/W)
???
MS ADDR
"NOT READY"
LS ADDR
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
READ
MEMORY
LOCATION
XXX
"NOT READY"
NEXT CMD
RESULT
XXX
BERR/AERR
READ (LONG)
???
MS ADDR
"NOT READY"
LS ADDR
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
READ
MEMORY
LOCATION
NEXT CMD
"NOT READY"
XXX
"NOT READY"
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR/AERR
NEXT CMD
"NOT READY"
Operand Data:
The single operand is the long-word address of the requested memory location.
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Result Data:
The requested data is returned as either a word or long word. Byte data is returned in the
least significant byte of a word result, with the upper byte cleared. Word results return 16
bits of significant data; long-word results return 32 bits.
A successful read operation returns data bit 16 cleared. If a bus or address error is encountered, the returned data is $10001.
5.6.2.8.9 Write Memory Location (WRITE). Write the operand data to the memory location specified by the long-word address. The DFC register determines the address space
accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and
long word.
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Command Format:
15
0
14
0
13
0
12
1
11
1
10
0
9
0
8
0
7
6
OP SIZE
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
WRITE (B/W)
???
MS ADDR
"NOT READY"
LS ADDR
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
DATA
"NOT READY"
WRITE
MEMORY
LOCATION
XXX
"NOT READY"
XXX CMD
NEXT
"CMD COMPLETE"
XXX
BERR/AERR
NEXT CMD
"NOT READY"
WRITE (LONG)
???
MS ADDR
"NOT READY"
XXX
"ILLEGAL"
LS ADDR
"NOT READY"
MS DATA
"NOT READY"
NEXT CMD
"NOT READY"
LS DATA
"NOT READY"
WRITE
MEMORY
LOCATION
XXX
"NOT READY"
NEXT
XXX CMD
"CMD COMPLETE"
XXX
BERR/AERR
NEXT CMD
"NOT READY"
Operand Data:
Two operands are required for this instruction. The first operand is a long-word absolute
address that specifies a location to which the operand data is to be written. The second
operand is the data. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively.
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Result Data:
Successful write operations return a status of $0FFFF. Bus or address errors on the write
cycle are indicated by the assertion of bit 16 in the status message and by a data pattern
of $0001.
5.6.2.8.10 Dump Memory Block (DUMP). DUMP is used in conjunction with the READ
command to dump large blocks of memory. An initial READ is executed to set up the starting
address of the block and to retrieve the first result. Subsequent operands are retrieved with
the DUMP command. The initial address is incremented by the operand size (1, 2, or 4) and
saved in a temporary register. Subsequent DUMP commands use this address, increment
it by the current operand size, and store the updated address back in the temporary register.
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NOTE
The DUMP command does not check for a valid address in the
temporary register—DUMP is a valid command only when preceded by another DUMP or by a READ command. Otherwise,
the results are undefined. The NOP command can be used for
intercommand padding without corrupting the address pointer.
The size field is examined each time a DUMP command is given, allowing the operand size
to be altered dynamically.
Command Format:
15
0
14
0
13
0
12
1
11
1
10
1
9
0
8
1
7
6
OP SIZE
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
DUMP (LONG)
???
READ
MEMORY
LOCATION
XXX
"NOT READY"
NEXT CMD
RESULT
DUMP (LONG)
???
READ
MEMORY
LOCATION
XXX
BERR/AERR
NEXT CMD
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
XXX
"NOT READY"
NEXT CMD
MS RESULT
MOTOROLA
NEXT CMR
LS RESULT
XXX
BERR/AERR
NEXT CMD
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
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Operand Data:
None
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Result Data:
Requested data is returned as either a word or long word. Byte data is returned in the least
significant byte of a word result. Word results return 16 bits of significant data; long-word
results return 32 bits. Status of the read operation is returned as in the READ command:
$0xxxx for success, $10001 for bus or address errors.
5.6.2.8.11 Fill Memory Block (FILL). FILL is used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting
address of the block and to supply the first operand. Subsequent operands are written with
the FILL command. The initial address is incremented by the operand size (1, 2, or 4) and
is saved in a temporary register. Subsequent FILL commands use this address, increment
it by the current operand size, and store the updated address back in the temporary register.
NOTE
The FILL command does not check for a valid address in the
temporary register—FILL is a valid command only when preceded by another FILL or by a WRITE command. Otherwise, the results are undefined. The NOP command can be used for
intercommand padding without corrupting the address pointer.
The size field is examined each time a FILL command is given, allowing the operand size to
be altered dynamically.
Command Format:
15
0
14
0
13
0
12
1
11
1
10
1
9
0
8
0
7
6
OP SIZE
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
FILL (B/W)
???
MS DATA
"NOT READY"
XXX
"ILLEGAL"
LS DATA
"NOT READY"
WRITE
MEMORY
LOCATION
XXX
"NOT READY"
NEXT CMD
"CMD COMPLETE"
NEXT CMD
"NOT READY"
XXX
BERR/AERR
FILL (LONG)
???
DATA
"NOT READY"
WRITE
MEMORY
LOCATION
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
XXX
"NOT READY"
NEXT CMD
"CMD COMPLETE"
XXX
BERR/AERR
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"NOT READY"
NEXT CMD
"NOT READY"
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Operand Data:
A single operand is data to be written to the memory location. Byte data is transmitted as
a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted
as 16 and 32 bits, respectively.
Result Data:
Status is returned as in the WRITE command: $0FFFF for a successful operation and
$10001 for a bus or address error during write.
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5.6.2.8.12 Resume Execution (GO). The pipeline is flushed and refilled before normal
instruction execution is resumed. Prefetching begins at the return PC and current privilege
level. If either the PC or SR is altered during BDM, the updated value of these registers is
used when prefetching commences.
NOTE
The processor exits BDM when a bus error or address error occurs on the first instruction prefetch from the new PC—the error
is trapped as a normal mode exception. The stacked value of the
current PC may not be valid in this case, depending on the state
of the machine prior to entering BDM. For address error, the PC
does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC.
Command Format:
15
0
14
0
13
0
12
0
11
1
10
1
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
GO
???
NORMAL
MODE
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
Operand Data:
None
Result Data:
None
5.6.2.8.13 Call User Code (CALL). This instruction provides a convenient way to patch
user code. The return PC is stacked at the location pointed to by the current SP. The stacked
PC serves as a return address to be restored by the RTS command that terminates the
patch routine. After stacking is complete, the 32-bit operand data is loaded into the PC. The
pipeline is flushed and refilled from the location pointed to by the new PC, BDM is exited,
and normal mode instruction execution begins.
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NOTE
If a bus error or address error occurs during return address
stacking, the CPU returns an error status via the serial interface
and remains in BDM.
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If a bus error or address error occurs on the first instruction
prefetch from the new PC, the processor exits BDM and the error is trapped as a normal mode exception. The stacked value of
the current PC may not be valid in this case, depending on the
state of the machine prior to entering BDM. For address error,
the PC does not reflect the true return PC. Instead, the stacked
fault address is the (odd) return PC.
Command Format:
15
0
14
0
13
0
12
0
11
1
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
CALL
???
MS ADDR
"NOT READY"
LS ADDR
"NOT READY"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
STACK
RETURN PC
FREEZE
NEGATED
PREFETCH
STARTED
NORMAL
MODE
XXX
BERR/AERR
NEXT CMD
"NOT READY"
Operand Data:
The 32-bit operand data is the starting location of the patch routine, which is the initial PC
upon exiting BDM.
Result Data:
None
As an example, consider the following code segment. It outputs a character from the
MC68340 serial module channel A.
CHKSTAT:
MISSING:
MOVE.B
BNE.B
MOVE.B
ANDI.B
RTS
SRA,D0Move serial status to D0
CHKSTATLoop until condition true
TBA,OUTPUTTransmit character
#3,D0Check for TxEMP flag
BDM and the CALL command can be used to patch the code as follows:
1. Breakpoint user program at CHKSTAT
2. Enter BDM
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3. Execute CALL command to MISSING
4. Exit BDM
5. Execute MISSING code
6. Return to user program
5.6.2.8.14 Reset Peripherals (RST). RST asserts RESET for 512 clock cycles. The CPU is
not reset by this command. This command is synonymous with the CPU RESET instruction.
Command Format:
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15
0
14
0
13
0
12
0
11
0
10
1
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
RESET
???
ASSERT
RESET
XXX
"NOT READY"
NEXT CMD
"CMD COMPLETE"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
Operand Data:
None
Result Data:
The “command complete” response ($0FFFF) is loaded into the serial shifter after negation of RESET.
5.6.2.8.15 No Operation (NOP). NOP performs no operation and may be used as a null
command where required.
Command Format:
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Command Sequence:
NOP
???
NEXT CMD
"CMD COMPLETE"
XXX
"ILLEGAL"
NEXT CMD
"NOT READY"
Operand Data:
None
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Result Data:
The “command complete” response ($0FFFF) is returned during the next shift operation.
5.6.2.8.16 Future Commands. Unassigned command opcodes are reserved by Motorola
for future expansion. All unused formats within any revision level will perform a NOP and
return the ILLEGAL command response.
5.6.3 Deterministic Opcode Tracking
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The CPU32+ utilizes deterministic opcode tracking to trace program execution. Two signals,
IPIPE and IFETCH, provide all information required to analyze instruction pipeline operation.
5.6.3.1 INSTRUCTION FETCH (IFETCH). IFETCH indicates which bus cycles are accessing data to fill the instruction pipeline. IFETCH is pulse-width modulated to multiplex two indications on a single pin. Asserted for a single clock cycle, IFETCH indicates that the data
from the current bus cycle is to be routed to the instruction pipeline. IFETCH held low for two
clock cycles indicates that the instruction pipeline has been flushed. The data from the bus
cycle is used to begin filling the empty pipeline. Both user and supervisor mode fetches are
signaled by IFETCH.
Proper tracking of bus cycles via IFETCH on a fast bus requires a simple state machine. On
a two-clock bus, IFETCH may signal a pipeline flush with associated prefetch followed
immediately by a second prefetch. That is, IFETCH remains asserted for three clocks, two
clocks indicating the flush/fetch and a third clock signaling the second fetch. These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of
CLKO1, which follow the AS (DS during show cycles) falling edge. Three-clock and slower
bus cycles allow time for negation of the signal between consecutive indications and do not
experience this operation.
5.6.3.2 INSTRUCTION PIPE (IPIPE1–IPIPE0). The internal instruction pipeline can be
modeled as a three-stage FIFO (see Figure 5-28). Stage A is an input buffer—data can be
used out of stages B and C. The IPIPE1–IPIPE0 signals indicate the advance of instructions
in the pipeline.
The 16-bit instruction register A (IRA) and 16-bit instruction register L (IRL) hold incoming
words as they are prefetched. No decoding occurs in IRA or IRL. Instruction register B (IRB)
provides initial decoding of the opcode and decoding of extension words; it is a source of
immediate data. Instruction register C (IRC) supplies residual opcode decoding during
instruction execution.
IRA is of higher priority than IRL. IRL is only loaded from the IMB when a 32-bit instruction
fetch is performed. IRA is loaded during every instruction fetch.
IRB is loaded from the contents of IRA or IRL, depending on which one is currently valid. If
both IRA and IRL are valid, then IRA is loaded into IRB before IRL is loaded into IRB.
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DATA
BUS
(31–16)
DATA
BUS
(15–0)
I
I
I
R
R
R
A
B
C
I
EXTENSION
WORDS
OPCODES
RESIDUAL
CPU32+
R
Freescale Semiconductor, Inc...
L
Figure 5-28. Functional Model of Instruction Pipeline
When IPIPE1 is low during a clock cycle, it indicates the use of data from IRB on that clock
cycle. IPIPE1 should be sampled by the user on the falling edge of CLKO1. Regardless of
the presence of valid data in IRA or IRL, the contents of IRB are invalidated when IPIPE1 is
asserted. If IRA or IRL contain valid data, the data is copied into IRB (IRA/IRL ⇒ IRB), and
the IRB stage is revalidated.
When IPIPE0 is low during a clock cycle, it indicates the start of a new instruction and subsequent replacement of data in IRC. This action causes a full advance of the pipeline (IRB
⇒ IRC and IRA/IRL ⇒ IRB). IRA and/or IRL is refilled during the next instruction fetch bus
cycle.
Data loaded into IRA and IRL propagates automatically through subsequent empty pipeline
stages. Signals that show the progress of instructions through IRB and IRC are necessary
to accurately monitor pipeline operation. These signals are provided by IRA, IRL and IRB
validity bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set,
and the validity bit of the stage supplying the data is negated.
Because instruction execution is not timed to bus activity, IPIPE1–IPIPE0 are synchronized
with the system clock and not the bus. Figure 5-29 illustrates the timing in relation to the system clock.
IRB IRC
IRA/IRL
IRB
IRA/IRL
IRB
IRA/IRL
IRB
IRB IRC
IRA/IRL
IRB
CLKO1
IPIPE0
INSTRUCTION
START
IPIPE1
EXTENSION
LONG WORD
USED
INSTRUCTION
START
Figure 5-29. Instruction Pipeline Timing Diagram
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IPIPE1–IPIPE0 should be sampled on the falling edge of the clock. Loading IRC always indicates that an instruction is beginning execution — the opcode is loaded into IRC by the
transfer. In BDM mode, the data output DSO is connected to IPIPE0. The IPIPE1 pin is
unused in BDM mode.
5.6.3.3 OPCODE TRACKING DURING LOOP MODE. IPIPE and IFETCH continue to work
normally during loop mode. IFETCH indicates all instruction fetches up through the point that
data begins recirculating within the instruction pipeline. IPIPE continues to signal the start
of instructions and the use of extension words even though data is being recirculated internally. IFETCH returns to normal operation with the first fetch after exiting loop mode.
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5.7 INSTRUCTION EXECUTION TIMING
This section describes the instruction execution timing of the CPU32+. External clock cycles
are used to provide accurate execution and operation timing guidelines, but not exact timing
for every possible circumstance. This approach is used because exact execution time for an
instruction or operation depends on concurrence of independently scheduled resources, on
memory speeds, and on other variables.
An assembly language programmer or compiler writer can use the information in this section
to predict the performance of the CPU32+. Additionally, timing for exception processing is
included so that designers of multitasking or real-time systems can predict task-switch overhead, maximum interrupt latency, and similar timing parameters. Instruction timing is given
in clock cycles to eliminate clock frequency dependency.
Most instruction timing information in the following subsections is taken from the CPU32
documentation. It applies to the CPU32+ when it is executing in 16-bit mode. However, a
summary of experiments run on the CPU32+ and the CPU32 is given in Table 5-25. The
tests show general indications of performance improvement of the CPU32+ over the
CPU32. Actual results on real applications may vary.
Table 5-25. CPU32+ Performance Improvement over the CPU32
Bus Cycle Length
Conditions
2
3
5
PI/BU (see Note)
16-Bit Data Bus
0/78
0/89
0/95
32-Bit Data Bus with 16-Bit Operands Only
(e.g., MOVE.W, CLR.W, etc.)
6/52
13/65
24/76
32-Bit Data Bus with 32-Bit Operands Only
(e.g., MOVE.L, MOVEA.L, MOVEM.L etc.)
13/50
40/62
58/73
NOTE:
PI = % Performance Increase over a CPU32 in the same conditions
BU = % Bus Utilization taken by the processor in the experiment
Note that the CPU32+ gains a significant performance advantage (58%) over the original
CPU32 when using long operands on a slow external bus. (Most compilers generate code
using long operands where possible.) Thus, the CPU32+ performance in 32-bit mode "falls
off" less rapidly than does the original CPU32.
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Also, note that the use of a 32-bit data bus reduces external bus utilization by 19 to 28 percentage points (e.g., 78–50 = 28%). This reduction gives more time for peripherals, such as
DMA channels, to use the bus without adversely affecting overall system performance. In
the best case, the CPU32+ can use as little as 50% of the bus, even though instructions execute continuously.
5.7.1 Resource Scheduling
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The CPU32+ contains several independently scheduled resources. The organization of
these resources within the CPU32+ is shown in Figure 5-30. Some variation in instruction
execution timing results from concurrent resource utilization. Because resource scheduling
is not directly related to instruction boundaries, it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within
which the instruction is executing.
5.7.1.1 MICROSEQUENCER. The microsequencer either executes microinstructions or
awaits completion of accesses necessary to continue microcode execution. The microsequencer supervises the bus controller, instruction execution, and internal processor operations such as calculation of EA and setting of condition codes. It also initiates instruction
word prefetches after a change of flow and controls validation of instruction words in the
instruction pipeline.
5.7.1.2 INSTRUCTION PIPELINE. The CPU32+ contains a two-word instruction pipeline
where instruction opcodes are decoded. Each stage of the pipeline is initially filled under
microsequencer control and subsequently refilled by the prefetch controller as it empties.
Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus before stage
B empties are temporarily stored in this buffer. Instruction words (instruction operation
words and all extension words) are decoded at stage B. Residual decoding and execution
occur in stage C.
Each pipeline stage has an associated status bit that shows whether the word in that stage
was loaded with data from a bus cycle that terminated abnormally.
5.7.1.3 BUS CONTROLLER RESOURCES. The bus controller consists of the instruction
prefetch controller, the write pending buffer, and the microbus controller. These three
resources transact all reads, writes, and instruction prefetches required for instruction execution.
The bus controller and microsequencer operate concurrently. The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls EA calculation
or sets condition codes.
The microsequencer can also request a bus cycle that the bus controller cannot perform
immediately. When this happens, the bus cycle is queued, and the bus controller runs the
cycle when the current cycle has completed.
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INSTRUCTION PIPELINE
MICROSEQUENCER AND CONTROL
STAGE
B
STAGE
C
CONTROL STORE
CONTROL LOGIC
EXECUTION UNIT
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PROGRAM
COUNTER
SECTION
DATA
SECTION
WRITE-PENDING
BUFFER
DATA
BUS
PREFETCH
CONTROLLER
ADDRESS
BUS
MICROBUS
CONTROLLER
BUS CONTROL
SIGNALS
Figure 5-30. Block Diagram of Independent Resources
5.7.1.3.1 Prefetch Controller. The instruction prefetch controller receives an initial request
from the microsequencer to initiate prefetching at a given address. Subsequent prefetches
are initiated by the prefetch controller whenever a pipeline stage is invalidated, either
through instruction completion or through use of extension words. Prefetch occurs as soon
as the bus is free of operand accesses previously requested by the microsequencer. Additional state information permits the controller to inhibit prefetch requests when a change in
instruction flow (e.g., a jump or branch instruction) is anticipated.
In a typical program, 10 to 25 percent of the instructions cause a change of flow. Each time
a change occurs, the instruction pipeline must be flushed and refilled from the new instruction stream. If instruction prefetches, rather than operand accesses, were given priority,
many instruction words would be flushed unused, and necessary operand cycles would be
delayed. To maximize available bus bandwidth, the CPU32+ will schedule a prefetch only
when the next instruction is not a change-of-flow instruction and when there is room in the
pipeline for the prefetch.
5.7.1.3.2 Write-Pending Buffer. The CPU32+ incorporates a single-operand write-pending
buffer. The buffer permits the microsequencer to continue execution after a request for a
write cycle is queued in the bus controller. The time needed for a write at the end of an
instruction can overlap the head cycle time for the following instruction, thus reducing overall
execution time. Interlocks prevent the microsequencer from overwriting the buffer.
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5.7.1.3.3 Microbus Controller. The microbus controller performs bus cycles issued by the
microsequencer. Operand accesses always have priority over instruction prefetches. Word
and byte operands are accessed in a single CPU-initiated bus cycle, although the external
bus interface may be required to initiate a second cycle when a word operand is sent to a
byte-sized external port. If long operands are accessed from a 16-bit port, they are accessed
in two bus cycles, most significant word first.
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The instruction pipeline is capable of recognizing instructions that cause a change of flow.
It informs the bus controller when a change of flow is imminent, and the bus controller
refrains from starting prefetches that would be discarded due to the change of flow.
5.7.1.4 INSTRUCTION EXECUTION OVERLAP. Overlap is the time, measured in clock
cycles, that an instruction executes concurrently with the previous instruction. As shown in
Figure 5-31, portions of instructions A and B execute simultaneously, reducing total execution time. Because portions of instructions B and C also overlap, overall execution time for
all three instructions is also reduced.
Each instruction contributes to the total overlap time. The portion of execution time at the
end of instruction A that can overlap the beginning of instruction B is called the tail of instruction A. The portion of execution time at the beginning of instruction B that can overlap the
end of instruction A is called the head of instruction B. The total overlap time between instructions A and B is the smaller tail of A and the head of B.
INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
OVERLAP
Figure 5-31. Simultaneous Instruction Execution
The execution time attributed to instructions A, B, and C after considering the overlap is illustrated in Figure 5-32. The overlap time is attributed to the execution time of the completing
instruction. The following equation shows the method for calculating the overlap time:
Overlap = min (TailN, HeadN+1)
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INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
PERIOD
OVERLAP
PERIOD
(ABSORBED BY
INSTRUCTION A)
(ABSORBED BY
INSTRUCTION B)
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Figure 5-32. Attributed Instruction Times
5.7.1.5 EFFECTS OF WAIT STATES. The CPU32+ access time for on-chip peripherals is
two clocks. While two-clock external accesses are possible when the bus is operated in a
synchronous mode, a typical external memory speed is three or more clocks.
All instruction times listed in this section are for word access only (unless an explicit exception is given), and are based on the assumption that both instruction fetches and operand
cycles are to a two-clock memory. Wait states due to slow external memory must be added
to the access time for each bus cycle.
A typical application has a mixture of bus speeds—program execution from an off-chip
ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and
accesses to external peripherals with speeds ranging from moderate to very slow. To arrive
at an accurate instruction time calculation, each bus access must be individually considered.
Many instructions have a head cycle count, which can overlap the cycles of an operand fetch
to slower memory started by a previous instruction. In these cases, an increase in access
time has no effect on the total execution time of the pair of instructions.
To trace instruction execution time by monitoring the external bus, note that the order of
operand accesses for a particular instruction sequence is always the same provided bus
speed is unchanged and the interleaving of instruction prefetches with operands within each
sequence is identical.
5.7.1.6 INSTRUCTION EXECUTION TIME CALCULATION. The overall execution time for
an instruction depends on the amount of overlap with previous and subsequent instructions.
To calculate an instruction time estimate, the entire code sequence must be analyzed. To
derive the actual instruction execution times for an instruction sequence, the instruction
times listed in the tables must be adjusted to account for overlap.
The formula for this calculation is as follows:
C1 − min (T1, H2) + C2 − min (T2, H3) + C3 − min (T3, H4) + . . .
where:
CN is the number of cycles listed for instruction N
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TN is the tail time for instruction N
HN is the head time for instruction N
min (TN, HM) is the minimum of parameters TN and HM
The number of cycles for the instruction (CN) can include one or two EA calculations in addition to the raw number in the cycles column. In these cases, calculate overall instruction time
as if it were for multiple instructions, using the following equation:
〈CEA〉 − min (Tea, Hop) + Cop
where:
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〈CEA〉 is the instruction’s EA time
Cop is the instruction’s operation time
Tea is the EA’s tail time
Hop is the instruction operation’s head time
min (Tn, Hm) is the minimum of parameters Tn and Hm
The overall head for the instruction is the head for the EA, and the overall tail for the instruction is the tail for the operation. Therefore, the actual equation for execution time becomes:
Cop1 − min (Top1, Hea2) + 〈CEA〉2 − min (Tea2, Hop2) + Cop2 − min (Top2, Hea3) + . . .
Every instruction must prefetch to replace itself in the instruction pipe. Usually, these
prefetches occur during or after an instruction. A prefetch is permitted to begin in the first
clock of any indexed EA mode operation.
Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of
an instruction provided the bus is not being used. If the bus is being used, then the prefetch
occurs at the next available time when the bus would otherwise be idle.
5.7.1.7 EFFECTS OF NEGATIVE TAILS. When the CPU32+ changes instruction flow, the
instruction decode pipeline must begin refilling before instruction execution can resume.
Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This idle
period can be used to prefetch an additional word on the new instruction path. Because of
the stipulation that each instruction must prefetch to replace itself, the concept of negative
tails has been introduced to account for these free clocks on the bus.
On a two-clock bus, it is not necessary to adjust instruction timing to account for the potential
extra prefetch. The cycle times of the microsequencer and bus are matched, and no additional benefit or penalty is obtained. In the instruction execution time equations, a zero
should be used instead of a negative number.
Negative tails are used to adjust for slower fetches on slower buses. Normally, increasing
the length of prefetch bus cycles directly affects the cycle count and tail values found in the
tables.
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In the following equations, negative tail values are used to negate the effects of a slower
bus. The equations are generalized, however, so that they may be used on any speed bus
with any tail value.
NEW_TAIL = OLD_TAIL + (NEW_CLOCK – 2)
IF ((NEW_CLOCK – 4) > 0) THEN
NEW_CYCLE = OLD_CYCLE + (NEW_CLOCK – 2) + (NEW_CLOCK – 4)
ELSE
NEW_CYCLE = OLD_CYCLE + (NEW _CLOCK – 2)
where:
NEW_TAIL/NEW_CYCLE
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OLD_TAIL/OLD_CYCLE
NEW_CLOCK
is the adjusted tail/cycle at the slower speed
is the value listed in the instruction timing tables
is the number of clocks per cycle at the slower speed
Note that many instructions listed as having negative tails are change-of-flow instructions
and that the bus speed used in the calculation is that of the new instruction stream.
5.7.2 Instruction Timing Tables
The following assumptions apply to the times shown in the subsequent tables:
1. A 16-bit data bus is used for all memory accesses (CPU32+ in 16-bit mode).
2. Memory access times are based on two-clock bus cycles with no wait states.
3. The instruction pipeline is full at the beginning of the instruction and is refilled by the
end of the instruction.
Three values are listed for each instruction and addressing mode:
Head:
The number of cycles available at the beginning of an instruction to complete a
previous instruction write or to perform a prefetch.
Tail:
The number of cycles an instruction uses to complete a write.
Cycles: Four numbers per entry, three contained in parentheses. The outer number is the
minimum number of cycles required for the instruction to complete. Numbers
within the parentheses represent the number of bus accesses performed by the
instruction. The first number is the number of operand read accesses performed
by the instruction. The second number is the number of instruction fetches performed by the instruction, including all prefetches that keep the instruction and the
instruction pipeline filled. The third number is the number of write accesses performed by the instruction.
As an example, consider an ADD.L (12, A3, D7.W ∗ 4), D2 instruction.
Paragraph 5.7.2.5 Arithmetic/Logic Instructions shows that the instruction has a head = 0, a
tail = 0, and cycles = 2 (0/1/0). However, in indexed address register indirect addressing
mode, additional time is required to fetch the EA. Paragraph 5.7.2.1 Fetch Effective Address
gives addressing mode data. For (d8, An, Xn.Sz ∗ Scale), head = 4, tail = 2, cycles = 8 (2/1/
0). Because this example is for a long access and the fetch EA table lists data for word
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accesses, add two clocks to the tail and to the number of cycles (“X” in table notation) to
obtain head = 4, tail = 4, cycles = 10 (2/1/0).
Assuming that no trailing write exists from the previous instruction, EA calculation requires
six clocks. Replacement fetch for the EA occurs during these six clocks, leaving a head of
four. If there is no time in the head to perform a prefetch due to a previous trailing write, then
additional time to perform the prefetches must be allotted in the middle of the instruction or
after the tail.
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8 (2 /1 /0)
TOTAL NUMBER OF CLOCKS
NUMBER OF READ CYCLES
NUMBER OF INSTRUCTION ACCESS CYCLES
NUMBER OF WRITE CYCLES
The total number of clocks for bus activity is as follows:
(2 Reads × 2 Clocks/Read) + (1 Instruction Access × 2 Clocks/Access) +
(0 Writes × 2 Clocks/Write) = 6 Clocks of Bus Activity
The number of internal clocks (not overlapped by bus activity) is as follows:
10 Clocks Total − 6 Clocks Bus Activity = 4 Internal Clocks
Memory read requires two bus cycles at two clocks each. This read time, implied in the tail
figure for the EA, cannot be overlapped with the instruction because the instruction has a
head of zero. An additional two clocks are required for the ADD instruction itself. The total
is 6 + 4 + 2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an
appropriate number of clocks to each memory access.
The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an example
of overlapped execution. The MOVE instruction has a head of zero and a tail of four because
it is a long write. The LSL instruction has a head of four. The trailing write from the MOVE
overlaps the LSL head completely. Thus, the two-instruction sequence has a head of zero,
a tail of zero, and a total execution of 8 rather than 12 clocks.
General observations regarding calculation of execution time are as follows:
• Any time the number of bus cycles is listed as "X", substitute a value of one for byte and
word cycles and a value of two for long cycles. For long bus cycles, usually add a value
of two to the tail.
• The time calculated for an instruction on a three-clock (or longer) bus is usually longer
than the actual execution time. All times shown are for two-clock bus cycles.
• If the previous instruction has a negative tail, then a prefetch for the current instruction
can begin during the execution of that previous instruction.
• Certain instructions requiring an immediate extension word (immediate word EA, absolute word EA, address register indirect with displacement EA, conditional branches with
word offsets, bit operations, LPSTOP, TBL, MOVEM, MOVEC, MOVES, MOVEP,
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MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin until the extension
word has been in the instruction pipeline for at least one cycle. This does not apply to
long offsets or displacements.
5.7.2.1 FETCH EFFECTIVE ADDRESS. The fetch EA table indicates the number of clock
periods needed for the processor to calculate and fetch the specified EA. The total number
of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
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Instruction
Head
Tail
Cycles
Notes
Dn
–
–
0(0/0/0)
–
An
–
–
0(0/0/0)
–
(An)
1
1
3(X/0/0)
1
(An)+
1
1
3(X/0/0)
1
−(An)
2
2
4(X/0/0)
1
(d16,An) or (d16,PC)
1
3
5(X/1/0)
1,3
(xxx).W
1
3
5(X/1/0)
1
(xxx).L
1
5
7(X/2/0)
1
#〈data〉.B
1
1
3(0/1/0)
1
#〈data〉.W
1
1
3(0/1/0)
1
#〈data〉.L
1
3
5(0/2/0)
1
(d8,An,Xn.Sz × Sc) or (d8,PC,Xn.Sz × Sc)
4
2
8(X/1/0)
1,2,3,4
(0) (All Suppressed)
2
2
6(X/1/0)
1,4
(d16)
1
3
7(X/2/0)
1,4
(d32)
1
5
9(X/3/0)
1,4
(An)
1
1
5(X/1/0)
1,2,4
(Xm.Sz × Sc)
4
2
8(X/1/0)
1,2,4
(An,Xm.Sz × Sc)
4
2
8(X/1/0)
1,2,3,4
(d16,An) or (d16,PC)
1
3
7(X/2/0)
1,3,4
(d32,An) or (d32,PC)
1
5
9(X/3/0)
1,3,4
(d16,An,Xm) or (d16,PC,Xm)
2
2
8(X/2/0)
1,3,4
(d32,An,Xm) or (d32,PC,Xm)
1
3
9(X/3/0)
1,3,4
(d16,An,Xm.Sz × Sc) or (d16,PC,Xm.Sz × Sc)
2
2
8(X/2/0)
1,2,3,4
(d32,An,Xm.Sz × Sc) or (d32,PC,Xm.Sz × Sc)
1
3
9(X/3/0)
1,2,3,4
X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands.
For long-word bus cycles, add two clocks to the tail and to the number of cycles.
NOTES:
1. The read of the EA and replacement fetches overlap the head of the operation by the amount
specified in the tail.
2. Size and scale of the index register do not affect execution time.
3. The PC may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the
head until the head reaches zero, at which time additional clocks must be added to both the tail
and cycle counts.
5. Timing is calculated with the CPU32+ in 16-bit mode.
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5.7.2.2 CALCULATE EFFECTIVE ADDRESS. The calculate EA table indicates the number of clock periods needed for the processor to calculate a specified EA. The timing is
equivalent to fetch EA except there is no read cycle. The tail and cycle time are reduced by
the amount of time the read would occupy. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
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Instruction
Head
Tail
Cycles
Notes
Dn
–
–
0(0/0/0)
–
An
–
–
0(0/0/0)
–
(An)
1
0
2(0/0/0)
–
(An)+
1
0
2(0/0/0)
–
−(An)
2
0
2(0/0/0)
–
(d16,An) or (d16,PC)
1
1
3(0/1/0)
1,3
(xxx).W
1
1
3(0/1/0)
1
(xxx).L
1
3
5(0/2/0)
1
(d8,An,Xn.Sz × Sc) or (d8,PC,Xn.Sz × Sc)
4
0
6(0/1/0)
2,3,4
(0) (All Suppressed)
2
0
4(0/1/0)
4
(d16)
1
1
5(0/2/0)
1,4
(d32)
1
3
7(0/3/0)
1,4
(An)
1
0
4(0/1/0)
4
(Xm.Sz × Sc)
4
0
6(0/1/0)
2,4
(An,Xm.Sz × Sc)
4
0
6(0/1/0)
2,4
(d16,An) or (d16,PC)
1
1
5(0/2/0)
1,3,4
(d32,An) or (d32,PC)
1
3
7(0/3/0)
1,3,4
(d16,An,Xm) or (d16,PC,Xm)
2
0
6(0/2/0)
3,4
(d32,An,Xm) or (d32,PC,Xm)
1
1
7(0/3/0)
1,3,4
(d16,An,Xm.Sz × Sc) or (d16,PC,Xm.Sz × Sc)
2
0
6(0/2/0)
2,3,4
(d32,An,Xm.Sz × Sc) or (d32,PC,Xm.Sz × Sc)
1
1
7(0/3/0)
1,2,3,4
NOTES:
1. Replacement fetches overlap the head of the operation by the amount specified in the tail.
2. Size and scale of the index register do not affect execution time.
3. The PC may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head
until the head reaches zero, at which time additional clocks must be added to both the tail and cycle
counts.
5. Timing is calculated with the CPU32+ in 16-bit mode
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5.7.2.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock
periods needed for the processor to calculate the destination EA and to perform a MOVE or
MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate
that portion of the instruction time.
Destination EAs are divided by their formats (see CPU32 Reference Manual). The total
number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w)
are included in the total clock cycle number. All timing data assumes two-clock reads and
writes.
When using this table, begin at the top and move downward. Use the first entry that matches
both source and destination addressing modes.
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Instruction
Head
Tail
Cycles
MOVE
Rn, Rn
0
0
2(0/1/0)
MOVE
〈FEA〉, Rn
0
0
2(0/1/0)
MOVE
Rn, (Am)
0
2
4(0/1/X)
MOVE
Rn, (Am)+
1
1
5(0/1/X)
MOVE
Rn, −(Am)
2
2
6(0/1/X
MOVE
Rn, 〈CEA〉
1
3
5(0/1/X)
MOVE
〈FEA〉, (An)
2
2
6(0/1/X
MOVE
〈FEA〉, (An)+
2
2
6(0/1/X)
MOVE
〈FEA〉, −(An)
2
2
6(0/1/X)
MOVE
#, 〈CEA〉
2
2
6(0/1/X∗
MOVE
〈CEA〉, 〈FEA〉
2
2
6(0/1/X)
X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles.
Timing is calculated with the CPU32+ in 16-bit mode.
∗ = An # fetch EA time must be added for this instruction: 〈FEA〉 +〈CEA〉 + 〈OPER〉
NOTE: For instructions not explicitly listed, use the MOVE 〈CEA〉, 〈FEA〉 entry. The source
EA is calculated by the calculate EA table, and the destination EA is calculated by the fetch EA
table, even though the bus cycle is for the source EA.
5.7.2.4 SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruction table indicates the number of clock periods needed for the processor to fetch, calculate,
and perform the special-purpose MOVE operation on control registers or a specified EA.
Footnotes indicate when to account for the appropriate EA times. The total number of clock
cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in
the total clock cycle number. All timing data assumes two-clock reads and writes.
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Instruction
Head
Tail
Cycles
2
0
4(0/1/0)
MOVEC Cr, Rn
10
0
14(0/2/0)
MOVEC Rn, Cr
12
0
14-16(0/1/0)
MOVE
CCR, Dn
2
0
4(0/1/0)
MOVE
CCR, 〈CEA〉
0
2
4(0/1/1)
MOVE
Dn, CCR
2
0
4(0/1/0)
MOVE
〈FEA〉, CCR
0
0
4(0/1/0)
MOVE
SR, Dn
2
0
4(0/1/0)
MOVE
SR, 〈CEA〉
0
2
4(0/1/1)
MOVE
Dn, SR
4
−2
10(0/3/0)
MOVE
〈FEA〉, SR
0
−2
10(0/3/0)
MOVEM.W〈CEA〉, RL
1
0
8 + n × 4(n + 1, 2, 0)∗
MOVEM.WRL, 〈CEA〉
1
0
8 + n × 4(0, 2, n)∗
MOVEM.L〈CEA〉, RL
1
0
12 + n × 4(2n + 2, 2, 0)
MOVEM.LRL, 〈CEA〉
1
2
10 + n × 4 (0, 2, 2n)
MOVEP.WDn, (d16, An)
2
0
10(0/2/2)
MOVEP.W(d16, An), Dn
1
2
11(2/2/0)
MOVEP.LDn, (d16, An)
2
0
14(0/2/4)
MOVEP.L(d16, An), Dn
1
2
19(4/2/0)
MOVES (Save)〈CEA〉, Rn
1
1
3(0/1/0)
MOVES (Op)〈CEA〉, Rn
7
1
11(X/1/0)
MOVES (Save)Rn, 〈CEA〉
1
1
3(0/1/0)
MOVES (Op)Rn, 〈CEA〉
9
2
12(0/1/X)
MOVE
USP, An
0
0
2(0/1/0)
MOVE
An, USP
0
0
2(0/1/0)
SWAP
Dn
4
0
6(0/1/0)
EXG
Freescale Semiconductor, Inc...
CPU32+
Rn, Rm
X = There is one bus cycle for byte and word operands and two bus cycles for long
operands. For long bus cycles, add two clocks to the tail and to the number of
cycles.
∗ = Each bus cycle may take up to four clocks without increasing total execution time.
Cr = Control registers USP, VBR, SFC, and DFC
n = Number of registers to transfer
RL = Register List
< = Maximum time (certain data or mode combinations may execute faster).
NOTES:
1. The MOVES instruction has an additional save step that other instructions do not have. To
calculate the total instruction time, calculate the save, the EA, and the operation execution
times, and combine in the order listed, using the equations given in 5.7.1 Resource Scheduling.
2. Timing is calculated with the CPU32+ in 16-bit mode.
5.7.2.5 ARITHMETIC/LOGIC INSTRUCTIONS. The arithmetic/logic instruction table indicates the number of clock periods needed to perform the specified arithmetic/logical instruction using the specified addressing mode. Footnotes indicate when to account for the
appropriate EA times. The total number of clock cycles is outside the parentheses. The num-
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bers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data
assumes two-clock reads and writes.
Freescale Semiconductor, Inc...
Instruction
Head
Tail
Cycles
ADD(A) Rn, Rm
0
0
2(0/1/0)
ADD(A) 〈FEA〉, Rn
0
0
2(0/1/0)
ADD
Dn, 〈FEA〉
0
3
5(0/1/x)
AND
Dn, Dm
0
0
2(0/1/0)
AND
〈FEA〉, Dn
0
0
2(0/1/0)
AND
Dn, 〈FEA〉
0
3
5(0/1/x)
EOR
Dn, Dm
0
0
2(0/1/0)
EOR
Dn, 〈FEA〉
0
3
5(0/1/x)
OR
Dn, Dm
0
0
2(0/1/0)
OR
〈FEA〉, Dn
0
0
2(0/1/0)
OR
Dn, 〈FEA〉
0
3
5(0/1/x)
SUB(A) Rn, Rm
0
0
2(0/1/0)
SUB(A) 〈FEA〉, Rn
0
0
2(0/1/0)
Dn, 〈FEA〉
0
3
5(0/1/x)
CMP(A) Rn, Rm
0
0
2(0/1/0)
CMP(A) 〈FEA〉, Rn
0
0
2(0/1/0)
CMP2 (Save)*〈FEA〉, Rn
1
1
3(0/1/0)
CMP2 (Op)〈FEA〉, Rn
2
0
16-18(X/1/0)
MUL(su).W〈FEA〉, Dn
0
0
26(0/1/0)
MUL(su).L (Save)*〈FEA〉, Dn
1
1
3(0/1/0)
MUL(su).L (Op)〈FEA〉, Dl
2
0
46-52(0/1/0)
MUL(su).L (Op)〈FEA〉, Dn:Dl
2
0
46(0/1/0)
DIVU.W 〈FEA〉, Dn
0
0
32(0/1/0)
DIVS.W 〈FEA〉, Dn
0
0
42(0/1/0)
DIVU.L (Save)*〈FEA〉, Dn
1
1
3(0/1/0)
DIVU.L (Op)〈FEA〉, Dn
2
0
<46(0/1/0)
DIVS.L (Save)*〈FEA〉, Dn
1
1
3(0/1/0)
DIVS.L (Op)〈FEA〉, Dn
2
0
<62(0/1/0)
TBL(su) Dn:Dm, Dp
26
0
28-30(0/2/0)
TBL(su) (Save)*〈CEA〉, Dn
1
1
3(0/1/0)
TBL(su) (Op)〈CEA〉, Dn
6
0
33-35(2X/1/0)
TBLSN Dn:Dm, Dp
30
0
30-34(0/2/0)
TBLSN (Save)*〈CEA〉, Dn
1
1
3(0/1/0)
TBLSN (Op)〈CEA〉, Dn
6
0
35-39(2X/1/0)
TBLUN Dn:Dm, Dp
30
0
34-40(0/2/0)
TBLUN (Save)*〈CEA〉, Dn
1
1
3(0/1/0)
TBLUN (Op)〈CEA〉, Dn
6
0
39-45(2X/1/0)
SUB
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X = There is one bus cycle for byte and word operands and two bus cycles for long operands.
For long bus cycles, add two clocks to the tail and to the number of cycles.
Timing is calculated with the CPU32+ in 16-bit mode.
< = Maximum time (certain data or mode combinations may execute faster).
su = The execution time is identical for signed or unsigned operands.
Freescale Semiconductor, Inc...
*
= These instructions have an additional save operation that other instructions do not have.
To calculate total instruction time, calculate save, 〈ea〉, and operation execution times,
then combine in the order listed, using equations in 5.7.1.6 Instruction Execution Time
Calculation. A save operation is not run for long-word divide and multiply instructions
when 〈FEA〉 = Dn.
5.7.2.6 IMMEDIATE ARITHMETIC/LOGIC INSTRUCTIONS. The immediate arithmetic/
logic instruction table indicates the number of clock periods needed for the processor to
fetch the source immediate data value and to perform the specified arithmetic/logic instruction using the specified addressing mode. Footnotes indicate when to account for the appropriate fetch effective or fetch immediate EA times. The total number of clock cycles is
outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total
clock cycle number. All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Cycles
MOVEQ#, Dn
0
0
2(0/1/0)
ADDQ
#, Rn
0
0
2(0/1/0)
ADDQ
#, 〈FEA〉
0
3
5(0/1/x)
SUBQ
#, Rn
0
0
2(0/1/0)
SUBQ
#, 〈FEA〉
0
3
5(0/1/x)
ADDI
#, Rn
0
0
2(0/1/0)∗
ADDI
#, 〈FEA〉
0
3
5(0/1/x)∗
ANDI
#, Rn
0
0
2(0/1/0)∗
ANDI
#, 〈FEA〉
0
3
5(0/1/x)∗
EORI
#, Rn
0
0
2(0/1/0)∗
EORI
#, 〈FEA〉
0
3
5(0/1/x)∗
ORI
#, Rn
0
0
2(0/1/0)∗
ORI
#, 〈FEA〉
0
3
5(0/1/x)∗
SUBI
#, Rn
0
0
2(0/1/0)∗
SUBI
#, 〈FEA〉
0
3
5(0/1/x)∗
CMPI
#, Rn
0
0
2(0/1/0)∗
CMPI
#, 〈FEA〉
0
3
5(0/1/x)∗
X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles.
Timing is calculated with the CPU32+ in 16-bit mode.
∗ = An # fetch EA time must be added for this instruction: 〈FEA〉 + 〈FEA〉 + 〈OPER〉
5.7.2.7 BINARY-CODED DECIMAL AND EXTENDED INSTRUCTIONS. The BCD and
extended instruction table indicates the number of clock periods needed for the processor
to perform the specified operation using the specified addressing mode. No additional tables
are needed to calculate total effective execution time for these instructions. The total number
of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
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Freescale Semiconductor, Inc...
Instruction
Head
Tail
Cycles
ABCD
Dn, Dm
2
0
4(0/1/0)
ABCD
−(An), −(Am)
2
2
12(2/1/1)
SBCD
Dn, Dm
2
0
4(0/1/0)
SBCD
−(An), −(Am)
2
2
12(2/1/1)
ADDX
Dn, Dm
0
0
2(0/1/0)
ADDX
−(An), −(Am)
2
2
10(2/1/1)
SUBX
Dn, Dm
0
0
2(0/1/0)
SUBX
−(An), −(Am)
2
2
10(2/1/1)
CMPM (An)+, (Am)+
1
0
8(2/1/0)
5.7.2.8 SINGLE OPERAND INSTRUCTIONS. The single operand instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Cycles
CLR
Dn
0
0
2(0/1/0)
CLR
〈CEA〉
0
2
4(0/1/X)
NEG
Dn
0
0
2(0/1/0)
NEG
〈FEA〉
0
3
5(0/1/X)
NEGX
Dn
0
0
2(0/1/0)
NEGX
〈FEA〉
0
3
5(0/1/X)
NOT
Dn
0
0
2(0/1/0)
NOT
〈FEA〉
0
3
5(0/1/X)
EXT
Dn
0
0
2(0/1/0)
NBCD
Dn
2
0
4(0/1/0)
NBCD
〈FEA〉
0
2
6(0/1/1)
Scc
Dn
2
0
4(0/1/0)
Scc
〈CEA〉
2
2
6(0/1/1)
TAS
Dn
4
0
6(0/1/0)
TAS
〈CEA〉
1
0
10(0/1/1)
TST
〈FEA〉
0
0
2(0/1/0)
X = There is one bus cycle for byte and word operands and two bus cycles for long-word
operands. For long-word bus cycles, add two clocks to the tail and to the number of
cycles.
Timing is calculated with the CPU32+ in 16-bit mode
5.7.2.9 SHIFT/ROTATE INSTRUCTIONS. The shift/rotate instruction table indicates the
number of clock periods needed for the processor to perform the specified operation on the
given addressing mode. Footnotes indicate when to account for the appropriate EA times.
The number of bits shifted does not affect the execution time, unless noted. The total num-
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CPU32+
ber of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Freescale Semiconductor, Inc...
Instruction
Head
Tail
Cycles
Note
LSd
Dn, Dm
−2
0
(0/1/0)
1
LSd
#, Dm
4
0
6(0/1/0)
—
LSd
〈FEA〉
0
2
6(0/1/1)
—
ASd
Dn, Dm
−2
0
(0/1/0)
1
ASd
#, Dm
4
0
6(0/1/0)
—
ASd
〈FEA〉
0
2
6(0/1/1)
—
ROd
Dn, Dm
−2
0
(0/1/0)
1
ROd
#, Dm
4
0
6(0/1/0)
—
ROd
〈FEA〉
0
2
6(0/1/1)
—
ROXd
Dn, Dm
−2
0
(0/1/0)
2
ROXd
#, Dm
−2
0
(0/1/0)
3
ROXd
〈FEA〉
0
2
6(0/1/1)
—
d = Direction (left or right)
NOTES:
1. Head and cycle times can be derived from the following table or calculated as follows:
Max (3 + (n/4) + mod(n,4) + mod (((n/4) + mod (n,4) + 1,2), 6)
2. Head and cycle times are calculated as follows: (count ≤ 63): max (3 + n + mod (n + 1,2), 6).
3. Head and cycle times are calculated as follows: (count ≤ 8): max (2 + n + mod (n,2), 6).
4. Timing is calculated with the CPU32+ in 16-bit mode.
Clocks
Shift Counts
6
0
1
2
3
4
5
6
8
8
7
10
11
13
14
16
17
20
10
15
18
19
21
22
24
25
28
12
23
26
27
29
30
32
33
36
14
31
34
35
37
38
40
41
44
16
39
42
43
45
46
48
49
52
18
47
50
51
53
54
56
57
60
20
55
58
59
61
62
22
63
9
12
5.7.2.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
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Freescale Semiconductor, Inc...
Instruction
Head
Tail
Cycles
BCHG
#, Dn
2
0
6(0/2/0)∗
BCHG
Dn, Dm
4
0
6(0/1/0)
BCHG
#, 〈FEA〉
1
2
8(0/2/1)∗
BCHG
Dn, 〈FEA〉
2
2
8(0/1/1)
BCLR
#, Dn
2
0
6(0/2/0)∗
BCLR
Dn, Dm
4
0
6(0/1/0)
BCLR
#, 〈FEA〉
1
2
8(0/2/1)∗
BCLR
Dn, 〈FEA〉
2
2
8(0/1/1)
BSET
#, Dn
2
0
6(0/2/0)∗
BSET
Dn, Dm
4
0
6(0/1/0)
BSET
#, 〈FEA〉
1
2
8(0/2/1)∗
BSET
Dn, 〈FEA〉
2
2
8(0/1/1)
BTST
#, Dn
2
0
4(0/2/0)∗
BTST
Dn, Dm
2
0
4(0/1/0)
BTST
#, 〈FEA〉
1
0
4(0/2/0)∗
BTST
Dn, 〈FEA〉
2
0
8(0/1/0)
∗ = An # fetch EA time must be added for this instruction: 〈FEA〉 + 〈FEA〉 + 〈OPER〉
Timing is calculated with the CPU32+ in 16-bit mode.
5.7.2.11 CONDITIONAL BRANCH INSTRUCTIONS. The conditional branch instruction
timing table indicates the number of clock periods needed for the processor to perform the
specified branch on the given branch size, with complete execution times given. No additional tables are needed to calculate total effective execution time for these instructions. The
total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/
p/w) are included in the total clock cycle number. All timing data assumes two-clock reads
and writes.
Instruction
Head
Tail
Cycles
Bcc
(taken)
2
−2
8(0/2/0)
Bcc.B
(not taken)
2
0
4(0/1/0)
Bcc.W
(not taken)
0
0
4(0/2/0)
Bcc.L
(not taken)
0
0
6(0/3/1)
DBcc
(T, not taken)
1
1
4(0/2/0)
DBcc
(F, −1, not taken)
2
0
6(0/2/0)
DBcc
(F, not −1, taken)
6
−2
10(0/2/0)
DBcc
(T, not taken)
4
0
6(0/1/0)∗
DBcc
(F, −1, not taken)
6
0
8(0/1/0)∗
DBcc
(F, not −1, taken)
6
0
10(0/0/0)∗
∗ = In loop mode
Timing is calculated with the CPU32+ in 16-bit mode.
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5.7.2.12 CONTROL INSTRUCTIONS. The control instruction table indicates the number of
clock periods needed for the processor to perform the specified operation on the given
addressing mode. Footnotes indicate when to account for the appropriate EA times. The
total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/
p/w) are included in the total clock cycle number. All timing data assumes two-clock reads
and writes.
Freescale Semiconductor, Inc...
Instruction
Head
Tail
Cycles
ANDI
#, SR
0
−2
12(0/2/0)
EORI
#, SR
0
−2
12(0/2/0)
ORI
#, SR
0
−2
12(0/2/0)
ANDI
#, CCR
2
0
6(0/2/0)
EORI
#, CCR
2
0
6(0/2/0)
ORI
#, CCR
2
0
6(0/2/0)
BSR.B
3
−2
13(0/2/2)
BSR.W
3
−2
13(0/2/2)
BSR.L
1
−2
13(0/2/2)
CHK
〈FEA〉, Dn (no ex)
2
0
8(0/1/0)
CHK
〈FEA〉, Dn (ex)
2
−2
42(2/2/6)
CHK2 (Save)〈FEA〉, Dn (no ex)
1
1
3(0/1/0)
CHK2 (Op)〈FEA〉, Dn (no ex)
2
0
18(X/0/0)
CHK2 (Save)〈FEA〉, Dn (ex)
1
1
3(0/1/0)
CHK2 (Op)〈FEA〉, Dn (ex)
2
−2
52(X + 2/1/6)
JMP
〈CEA〉
0
−2
6(0/2/0)
JSR
〈CEA〉
3
−2
13(0/2/2)
LEA
〈CEA〉, An
0
0
2(0/1/0)
LINK.W An, #
2
0
10(0/2/2)
LINK.L An, #
0
0
10(0/3/2)
NOP
0
0
2(0/1/0)
PEA
〈CEA〉
0
0
8(0/1/2)
RTD
#
1
−2
12(2/2/0)
RTR
1
−2
14(3/2/0)
RTS
1
−2
12(2/2/0)
1
0
9(2/1/0)
UNLK
X
=
An
There is one bus cycle for byte and word operands and two bus cycles for long-word
operands. For long-word bus cycles, add two clocks to the tail and to the number of
cycles.
Timing is calculated with the CPU32+ in 16-bit mode.
NOTE: The CHK2 instruction involves a save step that other instructions do not have. To calculate the total instruction time, calculate the save, the EA, and the operation execution times;
then combine in the order listed using the equations given in 5.7.1 Resource Scheduling.
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5.7.2.13 EXCEPTION-RELATED INSTRUCTIONS AND OPERATIONS. The exceptionrelated instructions and operations table indicates the number of clock periods needed for
the processor to perform the specified exception-related actions. No additional tables are
needed to calculate total effective execution time for these instructions. The total number of
clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Freescale Semiconductor, Inc...
Instruction
Head
Tail
Cycles
BKPT (Acknowledged)
0
0
14(1/0/0)
BKPT (Bus Error)
0
−2
35(3/2/4)
Breakpoint (Acknowledged)
0
0
10(1/0/0)
Breakpoint (Bus Error)
0
−2
42(3/2/6)
Interrupt
0
−2
30(3/2/4)∗
RESET
0
0
518(0/1/0)
STOP
2
0
12(0/1/0)
LPSTOP
3
−2
25(0/3/1)
Divide-by-Zero
0
−2
36(2/2/6)
Trace
0
−2
36(2/2/6)
TRAP #
4
−2
29(2/2/4)
ILLEGAL
0
−2
25(2/2/4)
A-line
0
−2
25(2/2/4)
F-line (First word illegal)
0
−2
25(2/2/4)
F-line (Second word illegal) ea = Rn
1
−2
31(2/3/4)
F-line (Second word illegal) ea ≠ Rn (Save)
1
1
3(0/1/0)
F-line (Second word illegal) ea ≠ Rn (Op)
4
−2
29(2/2/4)
Privileged
0
−2
25(2/2/4)
TRAPcc (trap)
2
−2
38(2/2/6)
TRAPcc (no trap)
2
0
4(0/1/0)
TRAPcc.W (trap)
2
−2
38(2/2/6)
TRAPcc.W (no trap)
0
0
4(0/2/0)
TRAPcc.L (trap)
0
−2
38(2/2/6)
TRAPcc.L (no trap)
0
0
6(0/3/0)
TRAPV (trap)
2
−2
38(2/2/6)
TRAPV (no trap)
2
0
4(0/1/0)
∗ = Minimum interrupt acknowledge cycle time is assumed to be three clocks.
Timing is calculated with the CPU32+ in 16-bit mode.
NOTE: The F-line (second word illegal) operation involves a save step which other
operations do not have. To calculate the total operation time, calculate the save, the calculate
EA, and the operation execution times, and combine in the order
listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation.
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5.7.2.14 SAVE AND RESTORE OPERATIONS. The save and restore operations table
indicates the number of clock periods needed for the processor to perform the specified
state save or return from exception. Complete execution times and stack length are given.
No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside
parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes
two-clock reads and writes.
Freescale Semiconductor, Inc...
Instruction
Head
Tail
Cycles
BERR on instruction
0
−2
<58(2/2/12)
BERR on exception
0
−2
48(2/2/12)
RTE (four-word frame)
1
−2
24(4/2/0)
RTE (six-word frame)
1
−2
26(4/2/0)
RTE (BERR on instruction)
1
−2
50(12/12/Y)
RTE (BERR on four-word frame)
1
−2
66(10/2/4)
RTE (BERR on six-word frame)
1
−2
70(12/2/6)
Y = If a bus error occurred during a write cycle, the cycle is rerun by the RTE.
< = Maximum time is indicated (certain data or mode combinations execute faster).
Timing is calculated with the CPU32+ in 16-bit mode.
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SECTION 6
SYSTEM INTEGRATION MODULE (SIM60)
The QUICC's system integration module (SIM60) consists of a number of functions that control system startup, system initialization, the external system bus, and the external system
peripherals. The SIM60 functions include the following:
Freescale Semiconductor, Inc...
• Module Base Address Register (MBAR)
• System Configuration and Protection
• New Low-Power Standby Modes with Slow-Go Option
• Clock Synthesizer with Skew Elimination
• Breakpoint Logic
• Slave Mode Including MC68040 Companion Mode
• External Bus Interface (EBI) Control
• Memory Controller Supports Eight Banks of DRAM, SRAM, EPROM, or Peripherals
• Dynamic Bus Sizing
• External Master Support
• Bus Arbitration
• IEEE 1149.1 Test Access Port
6.1 MODULE OVERVIEW
The SIM60 on the QUICC device is an enhanced version of the SIM40 that is implemented
on another M68300 family device called the MC68340. The italicized items show the main
areas of enhancement. To a large extent, the other features are still compatible with the
older SIM40.
The MBAR provides the base address for all accesses to the SIM60 and every other on-chip
resource.
The system configuration and protection function controls the overall system configuration
and provides various monitors and timers, including the internal bus monitor, double bus
fault monitor, spurious interrupt monitor, software watchdog timer, periodic interrupt timer,
low-power stop support, and freeze support.
The clock synthesizer generates the clock signals used by the SIM60 as well as other modules and external devices. This circuitry can generate the system clock from an inexpensive
32.768-khz watch crystal.
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The SIM60 has additional support of low-power modes. The clock synthesizer provides system clocks to the SIM60 and other modules. This clock scheme supports low-power modes
for applications that use the baud rate generators and/or serial ports during the standby
mode. The main system clock can be changed dynamically (the slow-go option) while the
baud rate generators and serial ports work with a fixed frequency.
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The breakpoint logic provides an internal breakpoint address register that allows hardware
breakpoints in a QUICC system. This function is especially useful during in-field debugging
activity when it is difficult to connect an in-circuit emulator or logic analyzer to the target
board.
The QUICC supports the slave mode. In this mode, the CPU32+ core on the QUICC is disabled, and the QUICC functions as an intelligent peripheral. For instance, if the application
requires more serial channels than the QUICC provides, multiple QUICCs may be configured onto the same system bus, one with its CPU enabled and the rest in slave mode. Alternatively, if the application needs additional CPU performance, the QUICC may function as
a companion chip to an MC68EC040 (or other M68040 family member). This is called
MC68040 companion mode. In this mode, the QUICC's glueless interface to the
MC68EC040 provides a two-chip MC68EC040 system solution. The MC68EC040 can also
control multiple QUICCs in slave mode. Finally, the QUICC slave mode may also support
an external MC68EC030 or other M68030 family member.
The EBI handles the transfer of information between the internal CPU32+ core and memory,
peripherals, or other processing elements in the external address space, or between an
external master and the QUICC RAM and registers. Section 4 Bus Operation describes the
bus operation, but the configuration control of the EBI is contained in this section.
The following functions are physically part of the SIM60, but are described in other places
in this manual.
The memory controller module provides glueless interfaces to many types of memory and
peripherals. It contains up to 8 general-purpose chip selects with up to 15 wait states each
and a full DRAM controller that controls up to 8 DRAM banks. See 6.10 Memory Controller
for further information.
The QUICC dynamically interprets the bus port size of an addressed device during each bus
cycle, allowing operand transfers to/from 8-, 16-, and 32-bit ports. The DSACK signals are
used to signify the data port size. Dynamic bus sizing can result in reduced system cost. For
instance, an 8-bit boot EPROM may be used with 16-bit peripherals and 32-bit DRAM.
Dynamic bus sizing also allows a programmer to write code that is not bus-width specific.
For a discussion on dynamic bus sizing see Section 4 Bus Operation.
The QUICC is designed to allow external bus masters the opportunity to access the intermodule bus (IMB). This design has two main purposes. First, the RAM and peripherals on
the QUICC can be directly accessed, if desired, by an external master. Second, the external
master can use QUICC resources, such as the chip-select generation logic and DRAM controller. See Section 4 Bus Operation for further discussion.
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System
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The QUICC also provides the ability to request and obtain mastership of the system bus.
This logic is only reset during a power-on reset and is active at all other times. See Section
4 Bus Operation for further discussion.
The QUICC includes dedicated user-accessible test logic that is fully compliant with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. This standard
was developed under the sponsorship of the IEEE Test Technology Committee and Joint
Test Action Group (JTAG). The QUICC implementation supports circuit-board test strategies based on this standard. Refer to Section 8 Scan Chain Test Access Port for additional
information.
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The following paragraphs describe the operation of the MBAR, system configuration and
protection, clock synthesizer, breakpoint logic, slave mode, and EBI control.
6.2 MODULE BASE ADDRESS REGISTER (MBAR)
The MBAR controls the location of all module registers (see 6.9.1 Module Base Address
Register (MBAR)). The address stored in this register is the base address (starting location)
for the internal module registers. All internal module registers and RAM occupy a single 8kbyte memory block (see Figure 6-1) that is relocatable along 8-Kbyte boundaries. The location of the internal registers is fixed by writing the desired base address of the 8-Kbyte block
to the MBAR using the MOVES instruction to address $0003FF00 in CPU space. The
source function code (SFC) and destination function code (DFC) registers contain the
address space values (FC2–FC0) for the read or write operand of the MOVES instruction
(see Section 5 CPU32+ or M68000PM/AD, Programmer’s Reference Manual). Therefore,
the SFC or DFC register must indicate CPU space (FC2–FC0 = $7), using the MOVEC
instruction, before accessing the MBAR.
6.3 SYSTEM CONFIGURATION AND PROTECTION
The SIM60 allows the user to control certain features of system configuration by writing bits
in the module configuration register (MCR).
All M68000 family members are designed to provide maximum system safeguards. As an
extension of the family, the QUICC promotes the same basic concepts of safeguarded
design present in all M68000 members. In addition, many functions that normally must be
provided in external circuits are incorporated in this device. The following features are provided in the system configuration and protection sub-module:
SIM60 Configuration
The SIM60 allows the user to configure the system according to the particular requirements. The functions include control of slave mode (disable CPU32+) operation, freeze
and show cycle operation, the access privilege of the supervisor/user registers, the level
of interrupt arbitration, and automatic autovectoring for external interrupts.
Reset Status
The reset status register provides the user with information on the cause of the most recent reset. The possible causes include external, power-up, software watchdog, double
bus fault, loss of clock, and the RESET instruction.
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MBAR (SIM60)
DPRBASE (DUAL-PORT RAM BASE)
DUAL-PORT RAM
4 KB
REGB (REGISTER BASE) = DPRBASE + 4K
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4 KB
INTERNAL
REGISTERS
Figure 6-1. QUICC Memory Map
Bus Monitor
The SIM60 provides a bus monitor to monitor the data and size acknowledge (DSACK)
response time for all bus accesses (internal-to-internal, internal-to-external, external-tointernal, and external-to-external). Four selectable response times allow for variations in
response speed of memory and peripherals used in the system. A bus error signal is asserted if the DSACK response limit is exceeded. This function can be disabled.
NOTE
On the MC68302, this function is called the hardware watchdog.
Double Bus Fault Monitor
The double bus fault monitor causes a reset to occur if the internal HALT signal is asserted by the CPU32+, indicating a double bus fault. A double bus fault results when a bus or
address error occurs during the exception processing sequence for a previous bus or address error, a reset, or while the CPU32+ is loading information from a bus error stack
frame during an RTE instruction. This function can be disabled. See Section 4 Bus Operation for more information.
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Spurious Interrupt Monitor
If no interrupt arbitration occurs during an interrupt acknowledge cycle, the bus error signal is asserted internally.
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Software Watchdog Timer (SWT)
The SWT asserts a reset or level 7 interrupt (as selected by the system protection control
register (SYPCR)) if the software fails to service the SWT for a designated period of time
(i.e., because the software is trapped in a loop or lost). There are eight selectable timeout
periods. After a system reset, this function is enabled, selects a timeout of approximately
1 second, and asserts a system reset if the timeout is reached. The SWT may be disabled,
or its timeout period may be changed in the SYPCR; however, once SYPCR is written, it
cannot be written again until a system reset. This mechanism is used to ensure the proper
operation of the SWT.
Periodic Interrupt Timer (PIT)
The SIM60 provides a timer to generate periodic interrupts for use with a real-time operating system or the application software. The PIT period can vary from 122 ms to 15.94 s
(assuming a 32.768-kHz crystal is used to generate the general system clock). This function can be disabled.
Freeze Support
The SIM60 allows control of whether the SWT and PIT should continue to run during
freeze mode.
Low-Power Stop Support
When executing the LPSTOP instruction, the QUICC can provide reduced power consumption with only the SIM60 remaining active.
Low-Power Standby Support
In addition to the low-power stop support, the QUICC can provide low power consumption
while other modules or sub-modules are functioning. In this mode, the baud rate generators and serial ports run with a fixed frequency while the rest of the chip (including the
SIM60) runs with a divided clock.
Figure 6-2 shows a block diagram of the system configuration and protection logic.
6.3.1 System Configuration
Many aspects of the system configuration are controlled by the MCR.
For debug purposes, accesses to internal peripherals can be shown on the external bus.
This function is called show cycles. The SHEN1, SHEN0 bits in the MCR control the show
cycles. External bus arbitration can be either enabled or disabled during show cycles.
The SIM60 provides eight bus arbitration levels for determining the priority of bus access (0–
7). The SIM60 is fixed at the highest level (level 7). The CPU32+ is fixed at the lowest level
(level 0). Only the SIM60, the CPU32+, the two-channel independent direct memory access
(IDMA), and the serial direct memory access (SDMA) can be bus masters and arbitrate for
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the bus. (The IDMA and SDMA have the ability to configure their bus arbitration level as
described in Section 7 Communication Processor Module (CPM)).
MODULE
CONFIGURATION
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RESET
STATUS
DOUBLE BUS
FAULT MONITOR
SYSTEM RESET
BUS
MONITOR
INTERNAL BERR
IS SIGNALED
SPURIOUS
INTERRUPT MONITOR
SOFTWARE
WATCHDOG
CLOCK
29
PRESCALER
PERIODIC
INTERRUPT TIMER
SYSTEM RESET
OR LEVEL 7
INTERRUPT
LEVEL 1 TO 7
INTERRUPT
Figure 6-2. System Configuration and Protection Logic
6.3.1.1 SIM60 INTERRUPT GENERATION. An overview of the QUICC interrupt structure
is shown in Figure 6-3. The lower half of the figure shows the SIM60. The SIM60 receives
interrupts from internal sources, such as the SWT and PIT, and external sources, such as
the IRQ7–IRQ1 lines.
If it generates an interrupt, the SWT always uses level 7; the PIT may use any level. The
IRQx pins choose the interrupt level associated with the pin (i.e., IRQ1 generates a level 1
interrupt, etc.). In addition, the CPM block may choose any level (1–7) for its interrupts.
The IMB architecture allows multiple interrupt sources to safely exist at the same level, a
process called interrupt arbitration. Once an interrupt acknowledge cycle occurs at the interrupt level that matches a pending interrupt request, interrupt arbitration begins on the IMB.
The interrupt arbitration process is designed to choose between multiple requests at the
same level. For instance, if the PIT request is at level 4 but the CPM simultaneously is
requesting an interrupt at level 4, an interrupt arbitration process is required to decide who
wins the interrupt. (The interrupt arbitration process does not affect users who assign all
interrupt sources in the system to a unique interrupt level (1–7)).
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System
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COMMUNICATION PROCESSOR MODULE (CPM)
12
32-BIT CPM INTERRUPT PENDING REGISTER (CPIR)
PORT C11–PORT C0
TIMER1
TIMER2
TIMER3
TIMER4
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
PIP
IDMA1
IDMA2
SDMA BUS ERROR
RISC TIMER TABLE
CPM PRIORITY RESOLVER
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INTERRUPT
SOURCES
CPM
VECTOR
GENERATION
LOGIC
8-BIT INTERRUPT
VECTOR (LOWER
5 BITS FIXED,
UPPER 3 BITS
PROGRAMMABLE)
INTERRUPT
ARBITRATION
ID IS FIXED AT
LEVEL 8
REQUEST
TO THE IMB AT
PROGRAMMABLE
LEVEL (1–7)
8
INTERMODULE BUS (IMB)
AVEC
SIGNAL
8-BIT INTERRUPT
VECTOR
8
SWT
VECTOR
GENERATION
INTERRUPT
ARBITRATION ID IS
INITIALLY 15
(PROGRAMMABLE)
PIT
VECTOR
GENERATION
QUICC SLAVE
MODE
INTERRUPT
LOGIC
REQUEST
TO THE IMB
LEVEL (1–7)
SIM60
INTERRUPT
CONTROL
AUTOVECTOR
GENERATION
PERIODIC
INTERRUPT TIMER
(PIT)
3
SOFTWARE
WATCHDOG
TIMER (SWT)
7
6
SYSTEM INTEGRATION MODULE (SIM60)
EXTERNAL TO QUICC
AVECO
IOUT2–IOUT0 RQOUT
AVEC
IRQ7–IRQ1
IACK7–IACK1
Figure 6-3. QUICC Interrupt Structure
In the interrupt arbitration process, the module places its arbitration ID on the IMB. The arbitration ID ranges in value from 0 to 15. The SIM60 interrupt controller arbitration ID is initialized to 15 (the highest value), but may be lowered if desired. The higher arbitration value
always wins.
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NOTES
At system reset, the SIM60 has a higher priority (at the same interrupt level) than the CPM. This priority can be changed if the
SIM60 value is written to be less than 8, the level of the CPM.
No two modules are allowed to have the same interrupt arbitration value.
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Assuming that the PIT wins the arbitration process, the SIM60 places the PIT 8-bit vector on
the bus. The SWT also has a user-defined interrupt vector. The PIT and SWT interrupts do
not allow autovectors. The IRQx lines can be vectored (externally supplied) or autovectored.
Arbitration for servicing interrupts is controlled by the value programmed into the interrupt
arbitration (IARB) field of the MCR. Because no two modules are allowed to share the same
IARB value and the only other module that generates interrupts (the CPM) has a fixed IARB
value (IARB = 8), the SIM60 IARB value should be programmed to a value between 1 and
7 or between 9 and 15.
The autovector register (AVR) contains bits that correspond to external interrupt levels that
require an autovector response. The SIM60 supports up to seven discrete external interrupt
requests. If the bit corresponding to an interrupt level is set in the AVR, the SIM60 returns
an internal autovector in response to the interrupt acknowledge cycle servicing that external
interrupt request. Otherwise, external circuitry must either return an interrupt vector or externally assert the external AVEC signal.
See 6.8.4 Interrupts in Slave Mode for more information.
6.3.1.2 SIMULTANEOUS SIM60 INTERRUPT SOURCES. If the possible level 7 interrupt
sources in the SIM60 are simultaneously asserted, the SIM60 will prioritize and service the
interrupts in the following order: 1) SWT, 2) PIT, and 3) external interrupts. At level 6 or less,
the PIT is higher than an external interrupt request asserted at the same level as the PIT.
6.3.1.2.1 Bus Monitor. The bus monitor ensures that each bus cycle is terminated within a
reasonable period of time. It continually checks the duration of the internal/external AS line
(TS for 68040). AS is normally negated by DSACKx, BERR, (TA or TEA for 68040).or HALT
(or AVEC during an interrupt acknowledge cycle) The bus monitor asserts BERR if the
response time is excessive on any bus cycle including interrupt acknowledge cycles. The
BME bit in the SYPCR enables the bus monitor.
The bus cycle termination response time is measured in clock cycles, and the maximumallowable response time is programmable. The bus monitor response time period ranges
from 128 to 1K system clocks (see Table 6-5). The value chosen by the user should be
larger than the longest possible response time of the slowest peripheral in the system.
6.3.1.2.2 Spurious Interrupt Monitor. In normal interrupt handling, one or more internal
sub-modules recognize the CPU32+ interrupt acknowledge cycle as a signal that the
CPU32+ is responding to their interrupt requests. The sub-modules then arbitrate for the
privilege of returning a vector or asserting AVEC to the CPU32+. (The SIM60 also performs
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internal interrupt arbitration on behalf of any IRQx pins that are asserted externally.) If, however, no internal sub-module participates in the internal interrupt arbitration process, the
spurious interrupt monitor takes action by issuing the BERR signal internally. This causes
the CPU32+ to terminate the cycle with a spurious interrupt vector. This feature cannot be
disabled.
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6.3.1.2.3 Double Bus Fault Monitor. A double bus fault is caused by a bus error or
address error during the exception processing sequence. The double bus fault monitor
responds to an assertion of HALT on the internal bus by initiating a system reset. Refer to
Section 4 Bus Operation for more information. The DBF bit in the reset status register indicates that the last reset was caused by the double bus fault monitor. The double bus fault
monitor reset can be enabled by the DBFE bit in the SYPCR.
6.3.1.2.4 Software Watchdog Timer (SWT). The SIM60 provides the SWT option to prevent system lockup in case the software becomes trapped in loops with no controlled exit.
The SWT is enabled after system reset to cause a system reset if it times out. If SWT is not
desired, the user must clear the SWE bit in the SYPCR to disable it. If used, the SWT
requires a special service sequence to be executed on a periodic basis. If this periodic servicing action does not occur, the SWT times out and issues a reset or a level 7 interrupt (as
programmed by the SWRI bit in the SYPCR). Once the SYPCR is written by software, the
state of the SWT (enabled or disabled) cannot be changed. The address of the interrupt service routine for the SWT interrupt is stored in the software interrupt vector register (SWIV).
Figure 6-4 shows a block diagram of the SWT as well as the clock control circuits for the PIT.
The SWT clock rate is determined by the SWP bit in the periodic interrupt timer register
(PITR) and the SWT bits in the SYPCR. When MODCK1 is low (an external oscillator is
used), the 512 (29) prescaler is enabled, and the SWP and PTP bits in the PITR are set.
See Table 6-4 for a list of SWT timeout periods.
The SWT service sequence consists of the following two steps: write $55 to the software
service register (SWSR) and write $AA to the SWSR. Both writes must occur in the order
listed prior to the SWT timeout, but any number of instructions or accesses to the SWSR
can be executed between the two writes. This allows interrupts and exceptions to occur, if
necessary, between the two writes.
PITR
SWP
PTP
FRZ1
SPCLK
FROM
CLOCK
SYNTHESIZER
PIT
INTERRUPT
CLOCK
DISABLE
PRESCALER (2 9 )
CLOCK
MUX
÷4
PITCLK
MODULUS COUNTER
PRECLK
RESET OR
LEVEL 7
INTERRUPT
SWCLK
LPSTOP
15 STAGE DIVIDER CHAIN (215 )
29
2 11
213
215
Figure 6-4. SWT and PIT Block Diagram
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6.3.2 Periodic Interrupt Timer (PIT)
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The PIT consists of an 8-bit modulus counter that is loaded with the value contained in the
PITR (see Table 6-4). The modulus counter is clocked by the SPCLK signal derived from
the EXTAL pin (either EXTAL or EXTAL divided by 128 as determined by the MODCK1–
MODCK0 pins). When MODCK1 is low (an external oscillator is used), the 512 (29) prescaler is enabled, and the SWP and PTP bits in the PITR are set.
The clock source is divided by 4 before driving the modulus counter (PITCLK). When the
modulus counter value reaches zero, an interrupt is generated. The level of the generated
interrupt is programmed into the PIRQL bits in the periodic interrupt control register (PICR).
During the interrupt acknowledge cycle, the SIM60 places the periodic interrupt vector, programmed into the PIV bits in the PICR, onto the bus. The value of bits 7–0 in the PITR is
then loaded again into the modulus counter, and the counting process starts over. If a new
value is written to the PITR, this value is loaded into the modulus counter when the current
count is complete.
6.3.2.1 PIT PERIOD CALCULATION. The period of the PIT can be calculated using the following equation:
PITR count value
PIT period =
SPCLK / prescaler value
22
Solving the equation using a crystal frequency of 32.768-kHz with the prescaler disabled
gives:
PITR count value
PIT period =
32768/1
22
PIT period
=
PITR count value
8192
This gives a range from 122 µs, with a PITR value of $01 (00000001 binary), to 31.128 ms,
with a PITR value of $FF (11111111 binary).
Solving the equation with the prescaler enabled (PTP = 1) gives the following values:
PITR count value
PIT period =
32768/512
22
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PIT period
=
PITR count value
16
This gives a range from 62.5 ms, with a PITR value of $01, to 15.94 s, with a PITR value of
$FF.
For a fast calculation of PIT period using a 32.768-kHz crystal, the following equations can
be used:
With prescaler disabled:
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PIT period = PITR (122 µs)
With prescaler enabled:
PIT period = PITR (62.5 ms)
6.3.2.2 USING THE PIT AS A REAL-TIME CLOCK. The PIT can be used as a real-time
clock interrupt by setting it up to generate an interrupt with a 1-second period. When using
a 32.768-kHz (or 4.192-MHz) crystal, the PITR should be loaded with a value of 16 decimal
($10) with the prescaler enabled to generate interrupts at a 1-sec rate.
6.3.3 Freeze Support
FREEZE is asserted by the CPU32+ if a breakpoint is encountered with background mode
enabled. Refer to Section 5 CPU32+ for more information on the background mode. When
FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue
to operate normally. However, the SWT, the bus monitor, and the PIT may be affected. Setting the FRZ1 bit in the MCR disables the SWT and the PIT when FREEZE is asserted. Setting the FRZ0 bit in the MCR disables the bus monitor when FREEZE is asserted.
If the CONFIG pins are configured with the CPU32+ core enabled, then one clock after reset
is complete, the CONFIG2 pin will become the FREEZE output. Thus, the pin will start driving low one clock after reset. It will then be asserted (high) if the freeze condition occurs. If
the CONFIG pins configure the QUICC to slave mode, then the FREEZE output is not available.
6.3.4 Low-Power Stop Support
Executing the LPSTOP instruction provides reduced power consumption when the QUICC
is idle, with only the SIM remaining active. Operation of the SIM60 is controlled by the
PLLCR. LPSTOP disables the clock to the SWT in the low state. The SWT, which remains
stopped until the LPSTOP mode is ended, begins to run again on the next rising clock edge.
NOTE
When the CPU32+ executes the STOP instruction (as opposed
to LPSTOP), the SWT continues to run. If the SWT is enabled,
it issues a reset or interrupt when its timeout occurs.
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The PIT does not respond to an LPSTOP instruction; thus, it can be used to exit LPSTOP
as long as the interrupt request level is higher than the CPU32+ interrupt mask level. To stop
the PIT while in LPSTOP, the PITR must be loaded with a zero value before LPSTOP is executed. The bus monitor, double bus fault monitor, and spurious interrupt monitor are all inactive during LPSTOP.
If an external device requires additional time to prepare for entry into LPSTOP mode, entry
can be delayed by asserting HALT (see 4.4.2 LPSTOP Broadcast Cycle).
NOTE
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The IDMA channels should be disabled prior to issuing the LPSTOP instruction.
6.4 LOW POWER IN NORMAL OPERATION
In addition to the LPSTOP mode, the SIM60 supports methods to minimize power consumption in normal operation. In normal operation, the QUICC provides several options to reduce
power consumption:
• The sub-block clock generators are automatically disabled when the sub-block is not
active. For example, when the RISC controller is idle (no pending request is present
from the serial channels), its clock generator is automatically stopped.
• In most of the IMB sub-modules, there is a bit (e.g., STOP or RESET), that can disable
the clock generator in that module (except for its IMB interface unit).
The SIM60 also supports methods to reduce power by dividing the clocks internally. This is
called slow-go mode and is described in 6.5 SIM60 System Clock Generation.
6.5 SIM60 SYSTEM CLOCK GENERATION
The QUICC has an on-chip oscillator, a clock synthesizer, and a low-power divider, which
allow a comprehensive set of choices in generating system clocks (see Figure 6-5). The
choices offer many opportunities to save power and system cost, without sacrificing flexibility and control.
The operation of the clocks is determined by three registers: the clock out control register
(CLKOCR), the phase-locked loop control register (PLLCR), and the clock divider control
register (CDVCR). Each register has a protection mechanism to prevent accidental writing.
The clock generation features are discussed in the following paragraphs.
6.5.1 Clock Generation Methods
The first method drives the system clock at the desired system frequency (10–25 MHz),
directly onto the EXTAL pin. A second method drives the EXTAL pin with a selected frequency which is pre-scaled and multiplied by the PLL. With these two methods, the XTAL
pin should be left floating. A third method uses a reference crystal frequency which can also
be pre-scaled and multiplied. This can be any frequency from 25 kHz to 6.0 MHz. Figure 66 shows external connections required for the on-chip oscillator as well as the other clockrelated VCC and GND connections.
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MULTIPLICATION FACTOR (MF11–MF0)
MODCK1–MODCK0
VCO
OUT (2x)
EXTAL
MUX
EXTAL
DIVIDE VALUES IN CDVCR
OSC.
XTAL
CLKIN
SyncCLK
BRGCLK
PLL
LOW-POWER
DIVIDERS
(NORMALLY
50 MHz)
DIVIDE
BY 128
CLKO2 PIN
(NORMALLY 50 MHz)
GENERAL SYSTEM
CLOCK
(NORMALLY 25 MHz)
EXTAL/128
MUX
EXTAL
CLKO1 PIN
÷ 2 MUX
MODCK1–MODCK0
SIMCLK
(NORMALLY 25 MHz)
Freescale Semiconductor, Inc...
STSIM BIT
SOFTWARE WATCHDOG AND PIT CLOCK (SPCLK)
CLKIN
PHASE
DETECTOR
LOOP
FILTER
VCO
VCO OUT
(TWICE THE
SYSTEM
FREQUENCY)
MULTIPLICATION
FACTOR
1 TO 4096
MF11–MF0
PLL
Figure 6-5. System Clocks Schematic
NOTE
User must select the proper MODCK configuration as well as
correct XFC capacitor value when selecting the input clock frequency and desired system frequency.
For more information on MODCK see 6.5.8 Configuration Pins
(MODCK1–MODCK0). For more information on XFC see 10.8
External Capacitor for PLL.
6.5.2 Oscillator Prescaler (Divide by 128)
In some applications, the use of a ~ 32-kHz crystal is attractive because of cost and low
power, but is not attractive due to the extra startup time required for such a slow frequency
crystal. Therefore, the SIM60 has an option for the user to provide a higher frequency crystal
(for instance, in the ~ 4-MHz range) and divide it by 128 (back down to the 32-kHz range)
before it is used by the QUICC. This results in much faster startup time than a 32-kHz crystal, plus low cost (if a common 4.192-MHz frequency is chosen), with only a small impact on
power consumption during low-power modes (since the ~4-MHz frequency is immediately
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divided prior to being used by any QUICC on-chip module). Furthermore, the divide-by-128
function allows the value of the final system frequency to be chosen with much greater precision, since it is a multiple of ~32 kHz rather than a multiple of ~4 MHz.
The choice of whether to use the divide-by-128 function is made with the MODCK1–
MODCK0 pins. This resulting frequency is called CLKIN.
CRYSTAL 2
330 K
20 pF
VCCSYN
XFC 1
20 pF
390nF
20 M
Freescale Semiconductor, Inc...
EXTAL
XTAL
0.1 µF
XFC PIN
VCCSYN
0.01 µF
GNDSYN
CRYSTAL
OSCILLATOR
CLKO1
CLOCK
GENERATION
CLKO2
VCCCLK
0.1 µF
GNDCLK
NOTE:
1. Must be low-leakage capacitor. See Section 10 Electrical Characteristics for recommended values.
2. Values are for 32 kHz crystal and may vary due to capacitance on PCB.
Figure 6-6. External Components
6.5.3 Phase-Locked Loop (PLL)
The PLL takes the CLKIN frequency and outputs a high-frequency source used to derive the
general system frequency of the QUICC. The PLL is comprised of a phase detector, loop
filter, voltage-controlled oscillator (VCO), and multiplication block. The VCO output can be
as high as 50 MHz for a 25-MHz QUICC.
The PLL’s main functions are frequency multiplication and skew elimination.
6.5.3.1 FREQUENCY MULTIPLICATION. The PLL can multiply the CLKIN input frequency
by any integer between 1 and 4096. The output of the VCO is twice the QUICC system frequency after reset.
If a low frequency crystal is chosen (e.g., ~32 kHz), the multiplier defaults to 401, giving a
2× VCO output of ~26 MHz and an initial general system clock of ~13 MHz. The multiplication factor may then be changed to the desired value by writing the MF11–MF0 bits in the
PLLCR. When the PLL multiplier is modified in software, the PLL will lose lock, and the
clocking to the QUICC will stop until lock is regained (worst case is 2500 clocks; typical case
is 500 clocks). See 6.5.4 Low-Power Divider for methods of reducing clock rates without losing lock.
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If the actual system clock is placed on the EXTAL pin (rather than an external crystal), the
multiplier defaults to 2, giving a 2× VCO output of 2× the EXTAL frequency. The multiplier
bits should not be modified by the user in this case. See 6.5.4 Low-Power Divider for methods of reducing clock rates.
NOTE
Freescale Semiconductor, Inc...
If the PLL is used, the resulting 2× VCO output should be a minimum of 20 MHz, meaning that the minimum QUICC system frequency should be 10 MHz (i.e., EXTAL × (MF + 1) >= 10 MHz.)
Use the clock divider control register (CDVCR) to divide the system clock by more than 1 if fully functional operation at less than
10 MHz is desired.
6.5.3.2 SKEW ELIMINATION. The PLL is capable of eliminating the skew between the
external clock entering the chip (EXTAL) and the internal clock phases. The PLL also eliminates the skew between EXTAL and the CLKO2–CLKO1 pins, providing advantages in
generating low-skew clocking outputs.
The skew is less than 2 ns. Without the PLL enabled, the clock skew could be much larger.
This significant reduction of the clock skew is useful for synchronous clocking of multiple
system components. For instance, a 25-MHz QUICC may generate clocks for the
MC68040—both the 25-MHz BCLK (EXTAL) and the 50-MHz PCLK (CLKO2) may be
obtained from a single 25-MHz system clock input to the QUICC.
6.5.4 Low-Power Divider
The output of the PLL is sent to a low-power divider block. This block generates all other
clocks in normal operation, but has the ability to divide the output frequency of the VCO
before it generates the SyncCLK, BRGCLK, and general system clock to the rest of the
QUICC.
The purpose of the low-power divider block is to allow the user to reduce and restore the
operating frequencies of different sections of the QUICC without losing the PLL lock. Using
the low-power divider block, the user can still obtain full chip operation, but at a slower frequency. This configuration is called slow-go mode. The selection and speed of the slow-go
mode may be changed at any time, with changes occurring immediately.
The low-power divider block is controlled in the CDVCR. The default state of the low-power
divider is to divide all clocks by 1. Thus, for a 25-MHz system, the SyncCLK, BRGCLK, and
general system clock are each 25 MHz.
If the low-power divider block is not used and the user is concerned that errant software
could accidentally write the CDVCR, the user may set a write protection bit in CDVCR to prevent further writes to the register.
6.5.5 QUICC Internal Clock Signals
The internal logic of the QUICC uses five internal clock lines: general system clock, BRGCLK, SyncCLK, SIMCLK, and SPCLK. The QUICC also generates two external clock lines
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(CLKO1 and CLKO2). The PLL synchronizes these clock signals to each other. These clock
signals are discussed in the following paragraphs.
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6.5.5.1 SPCLK. SPCLK is supplied to the PIT and SWT sub-modules in the SIM60. SPCLK
is always the EXTAL frequency or EXTAL/128, depending on the configuration of the divideby-128 prescaler. When EXTAL frequency > 10 MHz is selected by configuration pins
(MODCK1-MODCK0 = 01), then the PLL is clocked with the EXTAL frequency and SPCLK
is EXTAL/128. (i1616.e. When MODCK is 11 --> SPCLK is equal to EXTAL).
6.5.5.2 GENERAL SYSTEM CLOCK. This basic clock is supplied to all other modules and
sub-modules on the QUICC, including the CPU32+, the RISC controller, and most other features in the communication processor module (CPM). The general system clock also supplies the SIMCLK to the SIM60 in normal device operation. The general system clock is the
same as the CLKO1 frequency, and the CLKO2 signal is 2× the general system clock in normal device operation. The general system clock defaults to VCO/2 = 25 MHz (assuming a
25-MHz system frequency).
The frequency of the general system clock can be changed dynamically with the CDVCR,
as shown in Figure 6-7. This configuration is called slow-go mode.
DFNH = 0
VCO/2 (25 MHz)
NORMAL
GENERAL SYSTEM
CLOCK
DFNH DIVIDER
DFNH <> 00
LOW POWER
DFNL DIVIDER
NOTES:
1. NORMAL = (CSRC = 0) OR (INTEN2–INTEN0 < INTERRUPT) OR (RRQEN & RISC NOT IDLE)
2. LOW POWER = NORMAL
Figure 6-7. General System Clock Select
The general system clock can be operated at three frequencies. Normal operation is the
highest frequency (25 MHz in a 25-MHz system). The general system clock can also be
operated at a low frequency and a high frequency. The definition of low is made in the DFNL
value in CDVCR; the definition of high is made in the DFNH value in CDVCR.
The frequency of the general system clock can be changed dynamically by software. The
user may simply cause the general system clock to switch to its low frequency. However, in
some applications, there is a need for high frequency during certain periods. An example is
in interrupt routines, etc., that need more performance than the low frequency operation, but
must consume less power than in normal operation. The SIM60 allows a method to automatically switch between low and high frequency operation.
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The general system clock can switch automatically from low to high frequency whenever
one of the following conditions exists:
• The level of the pending or current interrupt is higher than the INTEN bits in CDVCR.
• The CPM RISC controller has a pending request or is currently executing a routine (i.e.,
it is not idle). This option is maskable by the RRQEN bit in CDVCR.
When neither of these conditions exists, the general system clock automatically switches
back to the low frequency.
Freescale Semiconductor, Inc...
When the general system clock is divided, its duty cycle is changed. One phase remains the
same (e.g., 20 ns @ 25 MHz); the other becomes longer. Note that the CLKO1 and CLKO2
pins no longer have a 50% duty cycle when the general system clock is divided (see Figure
6-8).
DIVIDE BY 1
DIVIDE BY 2
DIVIDE BY 4
Figure 6-8. Divided Clocks
6.5.5.3 BRGCLK. The BRGCLK is used by the five CPM baud rate generators. There are
four SCC/SCM baud rate generators and one SPI baud rate generator. BRGCLK defaults
to VCO/2 = 25 MHz (assuming a 25-MHz system frequency). The purpose of BRGCLK is to
allow the five baud rate generators to continue to operate at a fixed frequency, even when
the rest of the QUICC is operating at a reduced frequency (i.e., the general system clock is
divided). See 7.9 Baud Rate Generators (BRGs) for more information on how to save power
using the BRGCLK.
NOTES
During early board prototyping, the user should leave BRGCLK
at its standard frequency (e.g., 25 MHz) for the sake of simplicity.
Within the four SCC/SMC baud rate generators, the user should
not use a baud rate generator divider equal to 1, unless the
BRGCLK is at the maximum frequency.
6.5.5.4 SYNCCLK. The SyncCLK is used by the serial synchronization circuitry in the serial
ports of the CPM, including the SI, SCCs, and SMCs. The SyncCLK performs the function
of synchronizing externally generated clocks before they are used internally. SyncCLK
defaults to VCO/2 = 25 MHz (assuming a 25-MHz system frequency).
The purpose of SyncCLK is to allow the SI, SCCs, and SMCs to continue to operate at a
fixed frequency, even when the rest of the QUICC is operating at a reduced frequency.
Thus, SyncCLK allows the user to maintain the serial synchronization circuitry at the desired
rate, while lowering the general system clock to the lowest possible rate. However, the SyncCLK frequency must always be at least as high as the general system clock frequency.
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The SyncCLK must always be at least 2× the desired serial clock rate, and at least 2.5× the
desired serial clock rate if the time slot assigner (TSA) in the SI is used. See 7.8 Serial Interface with Time Slot Assigner for more information on how to select an appropriate frequency
for the SyncCLK.
Freescale Semiconductor, Inc...
NOTE
Since SyncCLK does not clock very much logic on the QUICC,
SyncCLK is normally left at its full frequency (25 MHz). However,
to temporarily lower the value of SyncCLK during an application
to save more power, SyncCLK must remain at its highest frequency (e.g., 25 MHz) until the general system clock is reduced.
Only then can SyncCLK be lowered, and it must never be lowered to a frequency less than the general system clock frequency.
6.5.5.5 SIMCLK. SIMCLK is supplied to the SIM60 module. SIMCLK defaults to VCO/2 = 25
MHz (assuming a 25-MHz system frequency). The SIMCLK is the same as the general system clock when slow-go mode is programmed in the CDVCR, but can operate differently
from the general system clock when the LPSTOP instruction is executed. The SIMCLK is
controlled in the PLLCR.
During the LPSTOP instruction, the PLL can be left enabled or can be disabled to conserve
power. This option is determined by the STSIM bit in PLLCR. If the PLL is disabled, the SIMCLK is either the EXTAL/2 or the EXTAL/128/2 frequency, depending on the divide-by-128
option.
NOTE
The SIMCLK is always the same frequency as CLKO1.
6.5.5.6 CLKO1. CLKO1 is the same as the general system clock frequency. CLKO1
defaults to VCO/2 = 25 MHz (assuming a 25-MHz system frequency). CLKO1 can drive full
strength, 2/3 strength, 1/3 strength, or be disabled. This option is controlled in the CLKOCR.
Disabling or decreasing the strength of CLKO1 can reduce power consumption, noise, and
electromagnetic interference on the printed circuit board.
During the LPSTOP instruction, the PLL can be left enabled or can be disabled to conserve
power. This option is determined by the STSIM bit in PLLCR. If the PLL is disabled, CLKO1
is either the EXTAL/2 or EXTAL/128/2 frequency, depending on the divide-by-128 option.
NOTE
CLKO1 is always the same frequency as the SIMCLK.
6.5.5.7 CLKO2. CLKO2 is 2× general system clock frequency in normal operation. The
CLKO2 VCO normally equals 50 MHz (assuming a 25-MHz system frequency). CLKO2 can
drive full strength, 2/3 strength, 1/3 strength, or be disabled. This option is controlled in the
CLKOCR. Disabling or decreasing the strength of CLKO2 can reduce power consumption,
noise, and electromagnetic interference on the printed circuit board.
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CLKO2 is always 2× CLKO1 except when the PLL is acquiring lock. When the PLL is acquiring lock, the CLKO2 signal is the EXTAL or EXTAL/128 frequency, as determined by the
divide-by-128 option.
For more information see 6.9.3.9 CLKO Control Register (CLKOCR).
6.5.6 PLL Power Pins
The following pins are dedicated to the PLL operation.
Freescale Semiconductor, Inc...
6.5.6.1 VCCSYN. This pin is the VCC dedicated to the analog PLL circuits. The voltage
should be well regulated, and the pin should be provided with an extremely low-impedance
path to the VCC power rail. VCCSYN should be bypassed to GNDSYN by a 0.1-µF capacitor
located as close as possible to the chip package.
6.5.6.2 GNDSYN. This pin is the GND dedicated to the analog PLL circuits. The pin should
be provided with an extremely low-impedance path to ground. GNDSYN should be
bypassed to VCCSYN by a 0.1-µF capacitor located as close as possible to the chip package. The user should also bypass GNDSYN to VCCSYN with a 0.01-µF capacitor as close
as possible to the chip package.
6.5.6.3 XFC. This pin connects to the off-chip capacitor for the PLL filter. One terminal of the
capacitor is connected to XFC; the other terminal is connected to VCCSYN.
6.5.7 CLKO Power Pins
The following pins are dedicated to the CLKO operation.
6.5.7.1 VCCCLK. This pin is the VCC for the CLKO1 and CLKO2 output pins. The voltage
should be well regulated and the pin should be provided with an extremely low-impedance
path to the VCC power rail. VCCCLK should be bypassed to GNDCLK by a 0.1-µF capacitor
located as close as possible to the chip package.
6.5.7.2 GNDCLK. This pin is the GND for the CLKO1 and CLKO2 output pins. The pin
should be provided with an extremely low-impedance path to ground. GNDCLK should be
bypassed to VCCCLK by a 0.1-µF capacitor located as close as possible to the chip package.
6.5.8 Configuration Pins (MODCK1–MODCK0)
MODCK1–MODCK0 specifies whether the PLL is enabled and what the initial VCO frequency is after a hardware reset. During the assertion of RESET, the value of the MODCK1–
MODCK0 input pins causes the PLLEN bit and the MF bits of the PLLCR to be appropriately
written. MODCK1–MODCK0 also determines if the oscillator’s prescaler is used. After
RESET is negated, the MODCK1–MODCK0 pins are ignored. Table 6-1 lists the default values of the PLL. These pins have an internal pullup during a hardware reset.
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Table 6-1. Default Operation Mode of the PLL
MODCK
1–0
PLL
Prescaled by
128
Multi. Factor
(MF + 1)
EXTAL Freq.
(Examples)
CLKIN to the
PLL
Initial Freq.
(VCO/2)
00
Disabled
Reserved
Reserved
Reserved
Reserved
Reserved
01
Enabled
No
1
>10 MHz
=EXTAL
=EXTAL
10
Enabled
Yes
401
4.192 MHz
32.75 kHz
13.14 MHz
11
Enabled
No
401
32.768 kHz
32.768 kHz
13.14 MHz
NOTE: If the PLL is enabled and the multiplication factor is less than or equal to 4, then CLKO2–CLKO1 is
synchronized to EXTAL.
Freescale Semiconductor, Inc...
6.6 BREAKPOINT LOGIC
The breakpoint logic provides an internal breakpoint address register (BKAR) and a breakpoint control register (BKCR) that allow hardware breakpoints in a QUICC system. This
function is especially useful during in-field debugging activity when it is difficult to connect
an in-circuit emulator or logic analyzer to the target board. The use of the background mode
of the CPU32+, in combination with the breakpoint logic, provides a convenient and powerful
debugging capability.
NOTE
Emulator manufacturers use the QUICC breakpoint logic in their
QUICC emulator designs. Customers using emulators should
leave the breakpoint logic available for use by the emulator manufacturer, and should not configure the breakpoint logic in their
application programs.
When a breakpoint match occurs, the BKPT line is asserted. This can cause a BKPT exception to the CPU32+, and will set a status bit in the IDMA or SDMA that can be used to generate a maskable interrupt. The maskable interrupt may or may not terminate IDMA or
SDMA activity, depending on the bus arbitration priority of the IDMA or SDMA as compared
to the interrupt level asserted.
NOTE
When the QUICC is configured for a 32-bit bus, the CPU32+ can
fetch two instructions simultaneously. Since there is only one
BKPT pin, the user cannot break on each instruction, but rather
must break on both, causing the BKPT exception to be taken after the first instruction and before the second. The internal
breakpoint logic, however, can assert a breakpoint for either instruction individually.
The breakpoint logic allows a great deal of flexibility in what constitutes a breakpoint match.
If more than one hardware breakpoint is required, then additional breakpoints may be generated externally in hardware and assert the BKPT pin.
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32-Bit Address Decode
The BKAR allows a full 32-bit address to be loaded. This address is qualified in various
ways using the BKCR. If no address is desired, the V-bit in the BKCR may be cleared.
Address Space Checking
The BKCR allows the user to check many combinations of function codes before causing
a breakpoint match. Nine bits in the BKCR allow such possibilities as excluding the IDMA
and SDMA function codes and the user and supervisor programs, but including user and
supervisor data.
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Read/Write Checking
The breakpoint logic can cause a breakpoint match for read accesses only, write accesses only, or both read and write accesses.
8, 16, 24 and 32 Bit Sizes
The breakpoint logic can cause a breakpoint match for accesses to the specified address
with a size of byte, word, three byte, long word, or any size.
Variable Block Sizes
If desired, the breakpoint match can occur in a region larger than just one address. Block
sizes may be defined to be the block of memory in which the address resides. The blocks
sizes may be 2K, 8K, or 32K bytes.
Additionally, the breakpoint match can be defined to occur at every address except the
address or address block that is specified. This feature allows the user to single step all
his program code. The breakpoint logic is then used to mask off the user’s monitor/debugger. The monitor/debugger thus resides within the programmable block specified by the
breakpoint logic.
External Masters
The breakpoint logic can also work with external masters, such as an external MC68040,
MC68030, or QUICC. The BKPT pin is asserted when a match is detected.
In the case of an external MC68040, the user may have to set the TSS40 bit in the GMR
to allow enough setup time for the address comparison logic. Also, in the case of an external MC68040, the comparison is only made on the first accesses of an MC68040 burst
access (i.e., the address comparison of the breakpoint logic is performed only when the
MC68040 TS pin is asserted).
6.7 EXTERNAL BUS INTERFACE CONTROL
This subsection describes the method by which the EBI is configured, which includes the
data bus size (either 32 or 16 bits), port D, and port E. Refer to Section 4 Bus Operation for
more information about the EBI.
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NOTE
All accesses to the QUICC internal RAM and registers (including
MBAR) by an external master are asynchronous to the QUICC
clock. Read and write accesses are with three wait states, and
DSACK is asserted by the QUICC assuming three-wait-state accesses.
6.7.1 Initial Configuration
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The QUICC has three configuration (CONFIG) pins that are sampled during system (or
power-up) reset to select the initial size of the global chip select and whether the QUICC is
in the normal (CPU32+ enabled) mode or the slave (CPU32+ disabled) mode (see Table 62).
See 6.10 Memory Controller for a description of the global chip select and 6.8 Slave (Disable
CPU32+) Mode for a description of slave mode. In normal mode, the global chip select can
initially assume the boot ROM port size to be either 8, 16, or 32 bits. In the slave mode, the
global chip select can be enabled with 8, 16, or 32 bits, or the global chip select can be disabled. The global chip select would normally be disabled if another QUICC or processor was
providing the boot ROM chip select function.
Table 6-2. QUICC Initial Configuration
Configuration Pins
CONFIG2
/FREEZE
CONFIG1
/BCLRO
CONFIG0
/RMC
0
0
0
Slave mode; global chip select 8-bit size; MBAR at $003FF00.
0
0
1
Slave mode; global chip select 32-bit size; MBAR at $003FF00; not
MC68040 companion mode; BR output, BG input.
0
1
0
Slave mode; global chip select 16-bit size; MBAR at $003FF00.
0
1
1
MC68040 companion mode; global chip select 32-bit size; MBAR at
$003FF00; BR input, BG output.
1
0
0
CPU32+ enabled; global chip select 32-bit size; MBAR at $003FF00.
1
0
1
CPU32+ enabled; global chip select 16-bit size; MBAR at $003FF00.
1
1
0
Slave mode; global chip select disabled; MBAR at $003FF04.
1
1
1
CPU32+ enabled; global chip select 8-bit size; MBAR at $003FF00.
Result
6.7.2 Port D
If the user configures a 16-bit data bus by driving a zero voltage on the PRTY3 pin during
system reset, then the D0–D15 pins are not used as a data bus, but are referred to as port
D. At this time, port D is not available for general-purpose I/O or any other alternate function
on the QUICC. In the future, these pins may be defined to have an additional function in 16bit data bus mode.
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NOTES
The 16-bit data bus is available on the D16–D31 pins. Dynamic
bus sizing for 8- and 16-bit ports is possible with a 16-bit data
bus.
PRTY3 has a small internal pullup to pull a floating PRTY3 signal
high. Thus, the default condition of the QUICC provides a full 32bit data bus, with 8-, 16-, and 32-bit dynamic bus sizing possible.
Freescale Semiconductor, Inc...
6.7.3 Port E
Port E pins can be independently programmed to select a number of system bus signal alternatives, including CAS lines, WE lines, OE lines, IACK lines, etc. The port E pin assignment
register controls the function of the port E pins. See 6.9.4 Port E Pin Assignment Register
(PEPAR).
6.8 SLAVE (DISABLE CPU32+) MODE
In this mode, the CPU32+ core on the QUICC is disabled, and the QUICC functions as an
intelligent peripheral. Slave mode is enabled during system (or power-up) reset by the configuration of the CONFIG pins. In slave mode, the IDMAs and SDMAs on a QUICC can still
obtain ownership of the system bus, even through the CPU32+ core is disabled. The slave
mode has several common uses:
1. A multiple QUICC system. One QUICC in the system works normally with its CPU32+
enabled. It is called the system master. The rest of the QUICCs are used in slave
mode as peripherals, with their CPUs disabled. The slaves would have their CONFIG
pins configured to 110.
2. MC68040 companion mode. The QUICC operates solely as a peripheral to the
MC68EC040 processor (or other M68040 family member). In this case, the QUICC
provides a two-chip MC68EC040 system solution. One benefit of this configuration is
that the QUICC memory controller can provide DRAM control for the MC68EC040 that
includes MC68EC040 bursting support. In an MC68EC040+QUICC system, the
QUICC’s CONFIG pins would normally be set to 011 for a 32-bit boot ROM.
3. MC68040 companion mode with multiple QUICCs. In this case, multiple QUICCs can
be slaves to a single MC68EC040. The user then chooses one of the QUICCs to provide the DRAM control for the MC68EC040 as well as the other QUICCs. In this case,
the MC68EC040 access to the DRAM is not slowed down by the relatively slower
QUICC accesses. The first QUICC in the system would have its CONFIG pins set to
011, and the other QUICCs added to that system would have their CONFIG pins set
to 110.
4. QUICC is a slave to the MC68030. The QUICC operates as a peripheral to the
MC68EC030 processor (or other MC68030 family member). The QUICC's standard
slave mode is used since its bus is an MC68030-type bus. The QUICC does not support MC68030 burst accesses. In an MC68EC030+QUICC system, the QUICC's
CONFIG pins could be set to 000, 001, or 010, depending on the boot ROM size.
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NOTES
When used in slave mode, the QUICC must be configured with
a 32-bit data bus.
Even without the use of the slave mode, another processor can
be granted access to the QUICC's on-chip peripherals by requesting the bus with the BR pin.
6.8.1 MBAR in a Multiple QUICC System
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The module base address register (MBAR) is used to configure the location of the QUICC's
block of on-chip RAM and registers. In a multiple QUICC system, a technique must be provided to allow multiple MBARs on multiple QUICCs to be programmed with unique values.
The QUICC has several provisions to support this.
First, any QUICC that is configured into slave mode with its global chip select disabled
(CONFIG pins = 110) automatically has its MBAR location changed from $0003FF00 to
$0003FF04. Second, the MBAR, newly located at address $0003FF04, can only be enabled
for access after a keyed write operation is performed (see Figure 6-9). The keyed write
allows the user to program the MBARs of multiple QUICC slaves without adding any external glue logic.
NOTES
If the QUICC is configured into slave mode with its global chip
select enabled, the MBAR location does not change, and the
keyed write is not required. Thus, a single QUICC configured as
a slave to an MC68EC040 or MC68EC030 does not require a
keyed write for its MBAR.
If there are N QUICCs sharing a bus, N–1 QUICCs would normally have their CONFIG pins configured as 110.
$0003FF04; FC = 111
MBAR
MBAR SELECT BIT (BIT 31)
4 KB
DUAL-PORT
RAM
$0003FF08; FC = 111
MBARE
4 KB
INTERNAL
REGISTERS
MBARE PIN
Figure 6-9. MBAR Access to a Multiple QUICC Slave System
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The keyed write uses the MBAR enable (MBARE) register at address $0003FF08 and the
MBARE pin. Both the newly located MBAR and the MBARE are located in the CPU address
space FC = 111.
Freescale Semiconductor, Inc...
With multiple QUICCs configured in slave mode, the following keyed write is used to enable
the MBAR programming: the user writes the MBAR select bit of MBARE with a 1 while the
MBARE pin is a logic zero. Once this is accomplished, the MBAR may be written at its new
location (using the standard MBAR writing techniques). Once MBAR is written (in particular,
the low-order byte of MBAR), then the MBAR select bit in MBARE is cleared, and further
accesses to MBAR are impossible until the keyed write technique is used again. There is no
time limit imposed between the keyed write and the MBAR write; however, once the keyed
write for a particular QUICC slave has occurred, the MBAR of that slave should be written
before performing another keyed write to another QUICC slave.
The keyed write may be performed gluelessly to multiple QUICC slaves in the following way.
Connect (in hardware) the MBARE pin of QUICC slave #1 to bit zero of the data bus(D0).
Connect the MBARE pin of QUICC slave #2 to D1, etc. Then perform the following operations in software:
1. Write the MBARE of QUICC slave #1 at $0003FF08 with value $FFFFFFFE. This sets
the MBAR select bit (bit 31) and places a low voltage on only the MBARE pin of QUICC
slave #1.
2. Now the MBAR of QUICC slave #1 can be accessed at $0003FF04 and written using
normal MBAR writing procedures.
3. Write the MBARE of QUICC slave #2 with the value $FFFFFFFD.
4. Now the MBAR of QUICC slave #2 can be written.
This technique will work for up to 31 QUICC slaves in the system, using no glue or parallel
I/O pins.
6.8.2 Global Chip Select (CS0) in Slave Mode
When the QUICC is in slave mode, the user may choose whether to enable the global chipselect operation of CS0. (The global chip select is used for boot ROMs and is described in
6.10 Memory Controller.) The global chip select can be either enabled or disabled by the
configuration on the CONFIG pins during power-up reset and system reset (RESETH
asserted). When the global chip select function is disabled, CS0 can still be enabled later
and used as a normal chip select, if desired.
6.8.3 Bus Clear in Slave Mode
The bus clear out (BCLRO) pin can be selected to signify to the external logic that the DRAM
refresh controller, IDMA channels, or SDMA channels are requesting the bus. However, in
slave mode, the BCLRO pin may become the RAS2DD double drive pin, and a new pin
called bus clear in (BCLRI) is defined (at another location in the pinout). BCLRI indicates to
that QUICC that a request is being made for the QUICC to release the system bus. The EBI
will then clear all internal bus masters with an arbitration ID smaller than the programmed
value of the bus clear in ID (BCLRIID) in the MCR.
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6.8.4 Interrupts in Slave Mode
The SIM60 interrupt controller continues to function in slave mode and can present interrupts from the PIT, SWT, and external interrupt sources on the IRQx pins to the processor.
The highest priority request is output as an encoded value on the IOUTx pins or is output on
a single RQOUT pin.
The CPM will also generate interrupts in slave mode. The CPM always generates unique
vectors for its sub-modules in slave mode. The CPM also offers a number of individual interrupt request inputs (port C pins) that may be used in slave mode.
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When the SIM60 is in slave mode, the PIT and SWT must also generate interrupt vectors.
For the IRQx pins, no vector is output in slave mode; rather, the AVECO pin is asserted if
the corresponding bit in the AVR is set.
One important restriction must be adhered to in slave mode. The user should not utilize an
IRQx pin that is on the same level as the CPM, PIT, or SWT. The level of the CPM is programmed in the CICR. The level of the PIT is programmed in the PICR. The level of the SWT
is 7 if it generates interrupts. Note that CPM port C pins operate similarly to the IRQx pins
and may still be used.
6.8.5 Pin Differences in Slave Mode
A number of signals change functionality in slave mode. See Section 2 Signal Descriptions
for a full listing. A partial list of functionality changes is as follows:
1. BR will be an output from the QUICC (refresh cycles, IDMA, and SDMA) to the external
bus.
NOTE
BR is still an input in MC68040 companion mode.
2. BG will be an input to the QUICC (refresh cycles, IDMA, and SDMA) from the external
bus.
NOTE
BG is still an output in MC68040 companion mode.
3. BGACK will be asserted during the QUICC external bus cycles.
4. The QUICC interrupt controller will output its interrupt requests on the IOUT2–IOUT0
pins, which normally would be sent to the CPU32+ core, and will reflect internally the
interrupt acknowledge cycle. The three IOUTx pins reflect the seven interrupt request
levels. The IOUTx pins can be output on the IRQ1, IRQ4, and IRQ6 pins or on the parity PRTY2–PRTY0 pins as programmed in the port E pin assignment register. Additionally, the QUICC interrupt controller can output its interrupt requests on one
interrupt request pin (RQOUT) instead of three pins.
5. An AVEC output (AVECO) function is supported instead of the AVEC input pin.
6. The breakpoint logic may monitor the external bus instead of the internal bus and assert the BKPTO pin.
7. The three-state (TRIS) pin becomes the transfer start (TS) pin in slave mode. Anytime
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the QUICC is in slave mode, assertion of the TS pin notifies the QUICC that an external MC68040 cycle is beginning. Although the user typically configures the CONFIGx
pins for MC68040 companion mode, this configuration is not required. It is possible for
the QUICC to recognize an MC68040 cycle in any of the slave mode variations. (The
reason for the MC68040 companion mode configuration of the CONFIGx pins is to allow the bus arbitration pins to have their directions reversed while still in slave mode.)
6.8.6 Other Functionality in Slave Mode
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Although the slave mode does enable a number of different pins on the system bus and
causes functional activities such as bus arbitration and interrupt handling to occur differently, if a feature is not cited as changing its behavior in slave mode (i.e., 98% of the features
on QUICC), then it is not impacted by slave mode and continues to operate normally.
6.9 PROGRAMMER’S MODEL
The SIM60 contains a number of registers, described in the following paragraphs. Their
locations and initial values may be found in Section 3 QUICC Memory Map.
6.9.1 Module Base Address Register (MBAR)
The MBAR is a 32-bit, memory-mapped, read-write register consisting of the high address
bits. Upon a total system reset, its value may be read as $0. The address of this register is
fixed at $03FF00 in CPU space (except in slave mode where it is located at $03FF04). See
6.8 Slave (Disable CPU32+) Mode for details.
31
BA31
RESET:
0
30
BA30
29
BA29
28
BA28
27
BA27
26
BA26
25
BA25
24
BA24
23
BA23
22
BA22
21
BA21
20
BA20
19
BA19
18
BA18
17
BA17
16
BA16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
BA15
RESET:
0
14
BA14
13
BA13
12
0
11
0
10
0
9
AS8
8
AS7
7
AS6
6
AS5
5
AS4
4
AS3
3
AS2
2
AS1
1
AS0
0
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU SPACE ONLY
BA31–BA13—Base Address
The base address field is the upper 19 bits of the MBAR, providing for block starting locations in increments of 8 Kbytes.
AS8–AS0—Address Space
The address space field allows particular address spaces to be masked, placing the 8K
module block into a particular address space(s). If an address space is masked, an access to the register block location in that address space becomes an external access. The
module block is not accessed. The address space bits for non-040 type master are:
1. AS8—mask DMA space address space (FC3–FC0=1xxx)
2. AS7—mask CPU space address space (FC3–FC0=0111)
3. AS6—mask supervisor program address space (FC3–FC0=0110)
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4. AS5—mask supervisor data address space (FC3–FC0=0101)
5. AS4—mask Motorola reserved address space (FC3–FC0=0100)
6. AS3—mask user reserved address space (FC3–FC0=0011)
7. AS2—mask user program address space (FC3–FC0=0010)
8. AS1—mask user data address space (FC3–FC0=0001)
9. AS0—mask Motorola reserved address space (FC3–FC0=0000)
The address space bits for 040 type MPU are:
1. AS8—no relevance for 040 cycles
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2. AS7—acknowledge access (TT1-TT0=11)
3. AS6—supervisor code access (TT1-TT0=00, TM2-TM0=110)
4. AS5—supervisor data access (TT1-TT0=00, TM2-TM0=101)
5. AS4—MMU table search code access (TT1-TT0=00, TM2-TM0=100)
6. AS3—MMU table search data access (TT1-TT0=00, TM2-TM0=011)
7. AS2—user code access (TT1-TT0=00, TM2-TM0=010)
8. AS1—user data access (TT1-TT0=00, TM2-TM0=001)
9. AS0—data cache push access (TT1-TT0=00, TM2-TM0=000)
NOTE
The user should mask off AS7, AS4, AS3 and AS1 to prevent
unwanted access to the QUICC internal dual port RAM (DPR).
For example, AS7 should be masked out so that the IACK cycle
will not cause an access to the DPR.
For each address space bit:
1 = Mask this address space from the internal module selection. The bus cycle goes
external.
0 = Decode for the internal module block.
V—Valid
This bit indicates when the contents of the MBAR are valid. The base address value is not
used; therefore, all internal module registers are not accessible until the V-bit is set.
0 = Contents not valid.
1 = Contents valid.
NOTE
When working in the CPU enable mode, an access to this register does not affect external space since the cycle is not run externally.
MBAR can be read using the following code. Register D0 will contain the value of MBAR.
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MOVE
MOVEC
MOVEC
LEA
MOVES.L
#7,D0
D0,SFC
D0,DFC
$3FF00,A0
(A0),D0
load
load
load
load
load
D0 with the CPU space function code
SFC to indicate CPU space
DFC to indicate CPU space
A0 with the address of MBAR
D0 with the contents of MBAR
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MBAR can be written to using the following code. Address $0003FF00 in CPU space
(MBAR) will be loaded with the value $FFFF F001. This will set the base address of the internal registers to $FFFFF.
MOVE
MOVEC
MOVEC
LEA
MOVE.L
MOVES.L
#7,D0
D0,SFC
D0,DFC
$3FF00,A0
#$FFFFF001,D0
D0,(A0)
load D0 with the CPU space function code
load SFC to indicate CPU space
load DFC to indicate CPU space
load A0 with the address of MBAR
load D0 with the value to be written into MBAR
write the value contained in D0 into MBAR
6.9.2 Module Base Address Register Enable (MBARE)
The MBARE is a 32-bit, memory-mapped, read-write register. Upon a total system reset, its
value may be read as $0. The address of this register is fixed at $03FF08 in CPU space. It
is used to enable the MBAR to be programmed when multiple QUICCs are in slave mode.
(See 6.8.1 MBAR in a Multiple QUICC System for details.)
31
MBS
RESET:
0
30
—
29
—
28
—
27
—
26
—
25
—
24
—
23
—
22
—
21
—
20
—
19
—
18
—
17
—
16
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
—
RESET:
0
14
—
13
—
12
—
11
—
10
—
9
—
8
—
7
—
6
—
5
—
4
—
3
—
2
—
1
—
0
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CPU SPACE ONLY
MBS—MBAR Select
0 = No operation.
1 = The MBAR is now ready to be programmed on this slave QUICC device if the
MBARE pin was low during the write to this bit.
6.9.3 System Configuration and Protection Registers
The following paragraphs provide descriptions of the system configuration and protection
registers.
6.9.3.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the
SIM60 configuration, can be read or written at any time.
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31
30
29
BR040ID2–BR040ID0
0
0
0
28
—
0
27
—
0
26
—
0
25
—
0
24
—
0
23
—
0
15
12
11
10
9
8
7
ASTM
0
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14
13
FRZ1–FRZ0
1
1
BCLROID2–BCLROID0
1
1
1
SHEN1–SHEN0
0
0
SUPV
1
22
—
0
21
—
0
20
—
0
19
—
0
18
—
0
17
—
0
16
BSTM
0
6
5
4
3
2
1
0
BCLRISM2–BCLRISM0 or
BCLRIID2–BCLRIID0
1
1
1
IARB3–IARB0
1
1
1
1
BR040ID2–BR040ID0—Bus Request MC68040 Arbitration ID
These bits contain the arbitration priority level for the MC68040 BR signal when the
QUICC is in MC68040 companion mode; otherwise, this value is ignored. The MC68040
BR signal in companion mode) is reflected on the IMB with the bus arbitration level corresponding to these bits. This method gives the user a choice of where to place the arbitration level of the MC68040 (and other external masters in this system) relative to the IDMA,
SDMA, or DRAM refresh cycles generated by the QIUCC.
NOTE
In a typical configuration, the user would program this value to a
3 to give the MC68040 priority over the IDMAs, but not over the
SDMAs and the DRAM refresh cycle. If the SDMAs, however,
are not of extremely high priority, the user may choose this value
to be 5. User should never program this field to be 7.
Bits 28–17—Reserved
BSTM—Bus Synchronous Timing Mode
This bit determines whether the EBI will synchronize the AS and DS bus signals used for
an external master’s access into the QUICC peripherals and for CS and RAS generation
by the QUICC. The synchronization will add a one-clock delay to the RAS/CS assertion
for an external master. The MC68EC040 signals must always be synchronized to the
QUICC clock, regardless of the setting of this bit. See 6.10 Memory Controller for recommendations on the setting of BSTM in certain situations.
0 = Asynchronous timing on the bus signals may be used. The bus signals are synchronized internally by the QUICC and do not have to meet any timings relative to
the system clock.
1 = Synchronous timing on the bus signals must be used. The bus control signals will
not be synchronized internally and therefore must meet the system clock setup and
hold timings.
NOTE
BCLRI, Address, Data, DSACK, BERR, HALT, RESETH, and
RESETS are always asynchronous.
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ASTM—Arbitration Synchronous Timing Mode
This bit determines whether the EBI will synchronize the arbitration signals: BR, BG, and
BGACK. The synchronization will add a one-clock delay to the external bus arbitration.
0 = Asynchronous timing on the arbitration signals may be used. The arbitration signals will be synchronized internally by the QUICC and do not have to meet any timings relative to the system clock.
1 = Synchronous timing on the arbitration signals must be used. The arbitration control
signals will not be synchronized internally and therefore must meet the system
clock setup and hold timings.
FRZ1—Freeze SWT and PIT Enable
0 = When FREEZE is asserted, the SWT and the PIT counters continue to run. See
6.3.3 Freeze Support for more information.
1 = When FREEZE is asserted, the SWT and the PIT counters are disabled, preventing interrupts from occurring during software debugging.
FRZ0—Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate as programmed.
1 = When FREEZE is asserted, both the internal and external bus monitors are disabled.
BCLROID2–BCLROID0—Bus Clear Out Arbitration ID
These bits contain the arbitration priority level for the assertion of the BCLRO signal.
When internal masters (IDMA, SDMA, or DRAM refresh cycle) request the bus and the
arbitration level on the IMB is greater than the bus clear out arbitration ID, the BCLRO signal will be asserted until the arbitration level is less than or equal to the bus clear out arbitration ID. BCLRO can be used to clear an external master from the external bus when
a refresh cycle is pending. It may also be used to clear an external master from the bus
when an SDMA or IDMA channel requests the external bus.
NOTE
Program this value to 3 in a normal system to allow the SDMA
and DRAM refresh controller to clear other bus masters off the
external bus.
SHEN1–SHEN0—Show Cycle Enable
These two control bits determine what the EBI does with the external bus during internal
transfer operations (see Table 6-3). A show cycle allows internal transfers to be externally
monitored. The address, data, and control signals (except for AS) are driven externally.
DS is used to signal address strobe timing for show cycles. Data is valid on the next falling
clock edge after DS is negated. However, data is not driven externally and AS and DS are
not asserted externally for internal accesses unless show cycles are enabled.
If external bus arbitration is disabled, the EBI will not recognize an external bus request
until arbitration is enabled again. When SHEN1 is set, an external bus request causes an
internal master to stop its current cycle and relinquish the internal bus. The internal master
resumes running cycles on the bus after BR and BGACK are negated. To prevent bus
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conflicts, external peripherals must not attempt to initiate cycles during show cycles with
arbitration disabled.
Table 6-3. Show Cycle Control Bits
SHEN1
SHEN0
Action
0
0
Normal operation. Split buses mode. Show cycles is disabled and external arbitration is
enabled.
0
1
Show cycles enabled. External arbitration is disabled and BG is never asserted.
1
x
Show cycles enabled. External arbitration is enabled and internal activity is halted when
BG is asserted by the QUICC.
NOTE
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During normal operation, BERR and DSACKx for internal cycles
will not appear as an external cycle in master mode.
For fast termination cycles, DSACKx is never asserted externally regardless of the show cycle bit settings.
In slave mode, these bits default to 00, and writes by the user
have no effect on operation.
In case 00 (show cycles disabled), if the external bus is available
when an internal-to-internal access occurs, the address and
function code pins will reflect the internal access.
Case 01 may be used as a debugging aid to eliminate the external bus master as a possible cause of the problem or to prevent
interference in a user debug session.
Although case 00 is recommended for normal operation, case 1x
may be used during initial development for visibility on the internal bus, at the expense of performance. Moving from 1x to 00 increases performance for two reasons: 1) both the internal and
external buses may be used simultaneously and 2) the external
bus master will obtain the BG signal assertion more quickly after
asserting BR.
SUPV—Supervisor/User Data Space
The SUPV bit defines the SIM60 global registers as either supervisor data space or user
(unrestricted) data space. It is a don’t care on the SIM60 and is reserved for future expansion.
0 = The SIM60 registers defined as supervisor/user data are unrestricted (FC2 is a
don’t care).
1 = The SIM60 registers defined as supervisor/user are restricted to supervisor data
access (FC3–FC0 = $5). Any attempted user space write is ignored and returns
BERR.
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NOTE
This bit is “don’t care” in the SIM60 since no user space registers
exist. It is reserved for future expansions.
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BCLRISM2–BCLRISM0—Bus Clear Interrupt Service Mask (Normal Mode Only)
These bits contain the interrupt service mask. When the interrupt service level on the IMB
is greater than the interrupt service mask, the BCLRO signal will be asserted until the interrupt level is less than or equal to the interrupt service mask. This feature can be used
to clear an external master from the external bus to reduce the interrupt latency for a certain interrupt level and above.
NOTES
This value should be programmed to 7 in a typical system unless
the user needs to give certain interrupt routines priority over external bus masters.
In slave mode (disable CPU32+), these bits are not used and
have a different definition.
BCLRIID2–BCLRIID0—Bus Clear In Arbitration ID (Slave Mode Only)
These bits contain the arbitration priority level for the BCLRI signal. If BCLRI is asserted
when the internal master (IDMA, SDMA, or DRAM refresh cycle) is requesting or using
the bus, and if the arbitration level on the IMB is lower than the bus clear in arbitration ID
bits, the internal master will release the bus until the BCLRI signal is negated. Thus, BCLRI can be used to clear an internal master from the external bus when the bus is needed
for a higher priority task.
NOTES
Program the arbitration IDs of the QUICC as follows: SDMA = 4,
IDMAx = 2, IDMAy = 0. The DRAM refresh controller is always
6. Thus, the user may choose 3 for this value to give the external
master priority over the IDMA channels only.
In the case of the MC68040 companion mode, the BG pin is also
negated by the QUICC when an internal master has released
the bus.
In normal operation (CPU32+ enabled), these bits are not used
and have a different definition.
This field should never be programmed to be 7.
IARB3–IARB0—Interrupt Arbitration
The reset value of IARB is $F, allowing the SIM60 to win interrupt arbitrations during an
interrupt acknowledge cycle immediately after reset. The system software should initialize
the IARB field to a value from $F (highest priority) to $1 (lowest priority).
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NOTE
If, a SIM60 interrupt source shares a level with the CPM, write
either $F or $1 to this register. Since the CPM interrupt arbitration ID is always 8, the $F gives the SIM60 source higher priority
than the CPM source(s), and a $1 gives the interrupt source lower priority than the CPM source(s). This field should never be
programed to 0.
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6.9.3.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to external interrupt levels that require an autovector response. Setting a bit allows the SIM60 to
assert an internal AVEC during the interrupt acknowledge cycle in response to the specified
interrupt request level. This register can be read and written at any time.
7
AV7
RESET:
0
6
AV6
5
AV5
4
AV4
3
AV3
2
AV2
0
0
0
0
0
1
AV1
0
-
0
0
SUPERVISOR ONLY
NOTE
The IARB field in the MCR must contain a value other than $0
for the SIM60 to produce an autovector for external interrupts.
6.9.3.3 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source
to the SIM60. A set bit indicates the last type of reset that occurred. The RSR is updated by
the reset control logic when the reset is complete. After power-up reset, the POW bit and
the EXT bit are set. Other bits may be set after different kinds of reset occur. Since this register is only cleared upon a power-up reset, the user should clear this register after every
reset so that the cause of the most recent reset may be easily determined.
A bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one
bit may be cleared at a time. The register may be read at any time. For more information,
see Section 4 Bus Operation.
7
EXT
6
POW
5
SW
4
DBF
3
—
2
LOC
1
SRST
0
SRSTP
SUPERVISOR ONLY
EXT—External Total System Reset (Hard Reset)
1 = The last reset was caused by an external signal driving RESETH. This will reset all
the QUICC's peripherals to the state they had at power-up reset. This reset, which
is also referred to as system reset or hardware reset, has the same effect in the
system as a power-up reset.
POW—Power-Up Reset
1 = The last reset was caused by the power-up reset circuit.
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SW—Software Watchdog Reset
1 = The last reset was caused by the software watchdog circuit.
DBF—Double Bus Fault Monitor Reset
1 = The last reset was caused by the double bus fault monitor.
Bit 3—Reserved
Freescale Semiconductor, Inc...
LOC—Loss of Clock Reset
1 = The last reset was caused by a loss of frequency reference to the clock sub-module. This reset can only occur if the RSTEN bit in the clock sub-module is set and
the VCO is enabled.
SRST—Soft Reset
1 = The last reset was caused by the CPU32+ executing a RESET instruction. The RESET instruction does not load a reset vector or affect any internal CPU32+ registers or SIM60 configuration registers, but does reset external devices and other
internal modules. See Section 3 QUICC Memory Map for a listing of registers affected by the hard reset. This bit is not valid in CPU disable mode.
SRSTP—Soft Reset Pin
1 = The last reset was caused by an external signal driving RESETS. See Section 3
QUICC Memory Map for a listing of registers affected by the soft reset.
6.9.3.4 SOFTWARE WATCHDOG INTERRUPT VECTOR REGISTER (SWIV). The SWIV
contains the 8-bit vector that is returned by the SIM60 during an interrupt acknowledge cycle
in response to an interrupt generated by the SWT. This register can be read or written at any
time. This register is set to the uninitialized vector, $0F, at reset.
7
SWIV7
RESET:
0
6
SWIV6
5
SWIV5
4
SWIV4
3
SWIV3
2
SWIV2
0
0
0
1
1
1
SWIV1
0
SWIV0
1
1
SUPERVISOR ONLY
6.9.3.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls
the system monitors, the prescaler for the SWT, and the bus monitor timing. This register
can be read at any time, but can be written only once after system reset.
7
SWE
RESET:
1
6
SWRI
1
5
4
SWT1 SWT0
MODCK MODCK
1
1
3
DBFE
2
BME
1
BMT1
0
BMT0
0
0
0
0
SUPERVISOR ONLY
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SWE—Software Watchdog Enable
This bit should be cleared by software after a system reset to disable the SWT. See
6.3.1.2.4 Software Watchdog Timer (SWT) for more information.
0 = SWT is disabled.
1 = SWT is enabled. (This is the default value after system reset.)
SWRI—Software Watchdog Reset/Interrupt Select
0 = SWT causes a level 7 interrupt to the CPU32+.
1 = SWT causes a system reset. (This is the default value after system reset.)
NOTE
Freescale Semiconductor, Inc...
For more information on reset see 4.7 Reset Operation.
SWT1–SWT0—Software Watchdog Timing
These bits, along with the SWP bit in the PITR, control the divide ratio used to establish
the timeout period for the SWT. The default value (11) yields the maximum timeout period.
The SWT timeout period is given by the following formula:
1
(EXTALDIV)/(divide count)
or
divide count
EXTALDIV
The SWT timeout period listed in Table 6-4 gives the formula to derive the SWT timeout for
any clock frequency. The timeout periods are listed for various input frequencies. Note that
the input frequency to the SWT is called EXTALDIV in the formulas and is the EXTAL frequency divided by 1 or by 128, depending on the MODCK1–MODCK0 pins.
Table 6-4. Deriving SWT Timeout
SWP
SWT1–SWT0 Software Timeout Period
32.768 kHz1
16.677 MHz
25 MHz
33.354 MHz
0
00
29/Input frequency2
15.6 ms
3.9 ms
2.6 ms
1.9 ms
0
01
211/Input frequency
62.5 ms
15.7 ms
10.5 ms
7.9 ms
0
10
213/Input frequency
250 ms
62.9 ms
41.9 ms
31.4 ms
0
11
215/Input frequency
1s
251.5 ms
167.7 ms
125.7 ms
1
00
218/Input frequency
8s
2.0 s
1.3 s
1.0 s
1
01
220/Input frequency
32 s
8.0 s
5.4 s
4.0 s
1
10
222/Input frequency
128 s
32.2 s
21.5 s
16.1 s
1
11
224/Input frequency
512 s
128.8 s
85.9 s
64.4 s
NOTES:
1. Note that a 4.192-MHz oscillator produces the same 32.768 input frequency (the 4.192 MHz is divided by 128 in the
oscillator circuit).
2. Programming for this timeout period must be done after the programming of the PLL. See also 6.9.3.10 PLL Control
Register (PLLCR).
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NOTE
When the SWP and SWT bits are modified to select a software
timeout other than the default, the software service sequence
($55 followed by $AA written to the software service register)
must be performed before the new timeout period takes effect.
Freescale Semiconductor, Inc...
DBFE—Double Bus Fault Monitor Enable
1 = Enable the double bus fault monitor function. (Default)
0 = Disable the double bus fault monitor function.
For more information, see 6.3.1.2.3 Double Bus Fault Monitor and Section 5 CPU32+.
BME—Bus Monitor External Enable
0 = Enable bus monitor function for the external bus cycles.
1 = Disable bus monitor function for the external bus cycles. (Default)
For more information see 6.3.1.2.1 Bus Monitor.
BMT1–BMT0—Bus Monitor Timing
These bits select the timeout period for the bus monitor (see Table 6-5).
Table 6-5. BMT Encoding
BMT1
BMT0
Bus Monitor Timeout Period
0
0
1K System Clocks (CLKO1 Clocks)
0
1
512 System Clocks
1
0
256 System Clocks
1
1
128 System Clocks
6.9.3.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the
interrupt level and the vector number for the periodic interrupt request. This register can be
read or written at any time. Bits 15–11 are unimplemented and always return zero; a write
to these bits has no effect.
15
0
RESET:
0
14
0
13
0
12
0
11
0
0
0
0
0
10
9
8
PIRQL2 PIRQL1 PIRQL0
0
0
0
7
PIV7
6
PIV6
5
PIV5
4
PIV4
3
PIV3
2
PIV2
1
PIV1
0
PIV0
0
0
0
0
1
1
1
1
SUPERVISOR ONLY
PIRQL2–PIRQL0—Periodic Interrupt Request Level
These bits contain the periodic interrupt request level. Table 6-6 lists which interrupt request level is asserted during an interrupt acknowledge cycle when a periodic interrupt is
generated. The PIT continues to run when the interrupt is disabled.
NOTE
Use caution with a level 7 interrupt encoding due to the SIM60
interrupt servicing order. See 6.3.1.2 Simultaneous SIM60 Interrupt Sources for the servicing order.
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Table 6-6. Periodic Interrupt Request Level Encoding
PIRQL2
PIRQL1
PIRQL0
Interrupt Request Level
0
0
0
PIT Disabled
0
0
1
Interrupt Request Level 1
0
1
0
Interrupt Request Level 2
0
1
1
Interrupt Request Level 3
1
0
0
Interrupt Request Level 4
1
0
1
Interrupt Request Level 5
1
1
0
Interrupt Request Level 6
1
1
1
Interrupt Request Level 7
PIV7–PIV0—Periodic Interrupt Vector
These bits contain the value of the vector generated during an interrupt acknowledge cycle in response to an interrupt from the PIT. When the SIM60 responds to the interrupt
acknowledge cycle, the periodic interrupt vector from the PICR is placed on the bus. This
vector number is multiplied by 4 to form the vector offset, which is added to the VBR in
the CPU32+ to obtain the address of the vector.
6.9.3.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for
prescaling the SWT and PIT as well as the count value for the PIT. This register can be read
or written at any time. Bits 15–10 are not implemented and always return zero when read.
A write does not affect these bits.
15
0
RESET:
0
14
0
13
0
12
0
11
0
10
0
0
0
0
0
0
9
8
SWP
PTP
MODCK MODCK
1
1
7
PITR7
6
PITR6
5
PITR5
4
PITR4
3
PITR3
2
PITR2
0
0
0
0
0
0
1
PITR1
0
PITR0
0
0
SUPERVISOR ONLY
SWP—Software Watchdog Prescaler Control
This bit controls the SWT clock source as shown in 6.9.3.5 System Protection Control
Register (SYPCR). The SWP reset value is the inverse of the MODCK1 pin state on the
rising edge of reset.
0 = SWT clock is not prescaled.
1 = SWT clock is prescaled by a value of 512.
PTP—Periodic Timer Prescaler Control
This bit contains the prescaler control for the PIT. The PTP reset value is the inverse of
the MODCK1 pin state on the rising edge of reset.
0 = PIT clock is not prescaled.
1 = PIT clock is prescaled by a value of 512.
PITR7–PITR0—Periodic Interrupt Timer Register
These bits contain the remaining bits of the PITR count value for the PIT. A zero value
turns off the PIT. These bits may be written at any time to modify the PIT count value.
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NOTE
If the PIT is enabled with the PTP bit set, then the first interrupt
can be up to 512 clocks early.
6.9.3.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which
the SWT servicing sequence is written. To prevent an SWT timeout, the user should write a
$55 followed by a $AA to this register. The SWT can be disabled by clearing the SWE bit in
the SYPCR. The SWSR can be written at any time, but returns all zeros when read.
7
SWSR7
6
SWSR6
5
SWSR5
4
SWSR4
3
SWSR3
2
SWSR2
1
SWSR1
0
SWSR0
Freescale Semiconductor, Inc...
SUPERVISOR ONLY
6.9.3.9 CLKO CONTROL REGISTER (CLKOCR). The CLKOCR controls the operation of
the CLKO2-1 pins. CLKOWP bit in CLKOCR is used as a protect mechanism to prevent
erroneous writing. CLKOCR can be read or written only in supervisor mode.
7
CLKOWP
RESET:
0
6
—
5
—
4
—
3
0
0
0
0/1
2
1
COM2
0
COM1
0/1
0/1
0/1
CLKOWP—CLKOCR Write Protect
This bit protects accidental writing into the CLKOCR. After reset, this bit defaults to zero
to enable writing. Setting this bit prevents further writing (excluding the first write that sets
this bit).
Bits 6 -4—Reserved
COM2—Clock Output 2 Mode
The COM2 bits control the output buffer strength of the CLKO2 pin. When both bits are
set, the CLKO2 pin is held in the high (1) state. These bits can be dynamically changed
without generating spikes on the CLKO2 pin. If the CLKO2 pin is not connected to external
circuits, set both bits (disabling the clock output) to minimize noise and power dissipation.
The COM2 bits are set to ones at system reset, unless MODCK = 01, in which case they
are cleared. This causes CLKO2 to be disabled at system reset, unless MODCK = 01.
(This causes CLKO2 to default to a quiet state, unless it is needed in an MC68040 companion mode system.)
00 = Clock Out Enabled, Full-Strength Output Buffer
01 = Clock Out Enabled, 2/3-Strength Output Buffer
10 = Clock Out Enabled, 1/3-Strength Output Buffer
11 = Clock Out Disabled (Driving 1)
COM1—Clock Output 1 Mode
The COM1 bits control the output buffer strength of the CLKO1 pin. When both bits are
set, the CLKO1 pin is held in the high (1) state. These bits can be dynamically changed
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without generating spikes on the CLKO1 pin. If the CLKO1 pin is not connected to external
circuits, set both bits (disabling the clock output) to minimize noise and power dissipation.
The COM1 bits are cleared at system reset, unless MODCK = 01, in which case they are
ones. This prevents CLKO1 and CLKO2 from both defaulting to an active state after reset,
for all four combinations of the MODCK1-0 pins. This reduces the potential for system
noise at reset. CLKO1 may be enabled later, if desired.
00 =
01 =
10 =
11 =
Clock Out Enabled, Full-Strength Output Buffer
Clock Out Enabled, 2/3-Strength Output Buffer
Clock Out Enabled, 1/3-Strength Output Buffer
Clock Out Disabled (Driving 1).
NOTE
Freescale Semiconductor, Inc...
If a continuous clock source is needed by the user when MODCK = 01, then the user should use the output of the external oscillator instead of the CLKO1 pin.
The sum of strength of CLKO1 and CLKO2 should not exceed
1. (If COM2 is set to 2/3 drive configuration, then COM1 cannot
be greater than 1/3 drive configuration)
When MODCK is set to 01, CLOCKO1 is disabled at reset until
the COM1 bit is changed.
The CLKO1 logic is as follows:
when COM1 bits in the CLKOCR = 11, CLKO1 is driven high;
when COM1 bits in the CLKOCR ≠11, CLKO1 is driven according to the following conditions:
a. Driven low if the PLL is NOT locked AND RESETH is
asserted.
b. Driven with the same frequency as EXTAL clock if the
PLL is locked.
c. Driven low if the PLL unlocked due to MF change.
6.9.3.10 PLL CONTROL REGISTER (PLLCR). The PLLCR controls the operation of the
PLL. It can be read or written only in supervisor mode. Writing into this register is allowed
only if the PLLWP bit is zero. The reset state of PLLCR produces an operating frequency of
13.14 MHz when the PLL is referenced to a 32.768-kHz crystal or to 4.192 MHz. Two pins
(MODCK1–MODCK0) are sampled during hardware reset (see Table 6-1).
15
14
13
PLLEN PLLWP PREEN
RESET:
1*
0
0
12
STSIM
11
MF11
10
MF10
9
MF9
0
0
0
0
8
MF8
7
MF7
MODCK1 MODCK1
6
MF6
5
MF5
4
MF4
3
MF3
2
MF2
1
MF1
0
MF0
0
0
MODCK1
0
0
0
0
Note:
The default value is one unless MODCK1-MODCK0 pins are tdriven with 00 during reset.
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PLLEN—PLL Enable Bit
The QUICC does not support disabled PLL. The bit is always set to one on reset unless the
MODCK1-MODCK0 pins are driven with 00 during reset. This mode of MODCK (00) is
reserved as indicated in 2.1.10.4 Clock Mode Select (MODCK1–MODCK0).
Freescale Semiconductor, Inc...
PLLWP—PLLCR Write Protect
This bit protects accidental writing of the PLLCR. After reset, this bit defaults to zero to
enable writing. Setting this bit prevents further writing (excluding the first write that sets
this bit).
PREEN—Prescaler Enable
This bit controls the divide-by-128 prescaler on the EXTAL signal. This bit is set during
hardware reset only if the MODCK1–MODCK0 pins specify that the divide-by-128 prescaler is used. It may be read thereafter as a status. If it is ever modified by software, it
should be changed at the same time that the corresponding change in the MF bits is performed.
0 = The divide-by-128 prescaler is disabled. CLKIN = EXTAL—the PLL input clock frequency is the EXTAL frequency.
1 = The divide-by-128 prescaler is enabled. CLKIN = EXTAL/128—the PLL input clock
frequency is the EXTAL frequency divided by 128.
STSIM—Stop Mode SIMCLK
0 = When the LPSTOP instruction is executed, the SIMCLK is driven from the crystal.
The frequency is either EXTAL/2 or EXTAL/256, depending on the divide-by-128
option. The PLL is disabled to conserve power.
1 = When the LPSTOP instruction is executed, the SIM60 clock is driven from the
VCO.
MF11–MF0—Multiplication Factor
These bits define the multiplication factor that will be applied to the PLL input frequency. The
multiplication factor can be any integer from 1 to 4096. The system frequency is ((MF bits +
1) × EXTALDIV), where EXTALDIV is either EXTAL or EXTAL/128, depending on the
MODCK bit configuration. The multiplication factor must be chosen to ensure that the resulting VCO output frequency will be in the range from 10 MHz to the maximum allowed clock
input frequency (e.g., 25 MHz for a 25-MHz device). In addition, the VCO outputs a 2× frequency signal, which is 2× the multiplied value configured in the MF bits. This frequency is
not used in any of the MF calculations.
The value 000 results in a multiplier value of 1; the value $FFF results in a multiplier value
of 4096.
Anytime a new value is written into the MF11–MF0 bits, the PLL will lose the lock condition
and, after a delay, will relock. When the PLL loses its lock condition, all clocks generated by
the PLL are disabled. After a hardware reset, the MF11–MF0 bits default to either 0 or 400
($190 hex), depending on the MODCK1–MODCK0 pins (giving a multiplication factor of 1 or
401). If the multiplication factor is 401, then a standard 32.768-kHz crystal generates an ini-
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tial general system clock of 13.14 MHz. The user would then write the MF bits to raise this
frequency to the desired frequency.
NOTE
SWT clocking does not stop when the PLL is in the process of
acquiring a lock. Therefore, the user should service the SWT (reset its count) before and after changing the MF bits.
Freescale Semiconductor, Inc...
6.9.3.11 CLOCK DIVIDER CONTROL REGISTER (CDVCR). The CDVCR controls the
operation of the low-power divider for the various clocks on the QUICC. It can be read or
written only in supervisor mode. Writing this register is allowed only if the CDVWP bit is zero.
The reset state of CDVCR produces the maximum frequency for all the clocks that it affects.
15
CDVWP
0
14
13
12
DFSY
0
11
10
0
0
DFTM
0
0
9
INTEN
0
8
0
7
RRQEN
0
6
0
5
DFNL
0
4
3
0
0
2
DFNH
0
1
0
0
CSRC
0
CDVWP—CDVCR Write Protect
This bit protects accidental writing of the CDVCR. After reset, this bit defaults to zero to
enable writing. Setting this bit prevents further writing (excluding the first write that sets
this bit).
DFSY—Division Factor for the SyncCLK
These bits define the SyncCLK frequency. Changing the value of the these bits will not
result in a loss-of-lock condition. These bits are cleared by a hardware reset. The default
value is divide by 1 (VCO/2) which is 25 MHz in a 25-MHz system.
00 = Divide by 1 (normal operation)
01 = Divide by 4
10 = Divide by 16
11 = Divide by 64
DFTM—Division Factor for the BRGCLK
These bits define the BRGCLK frequency. Changing the value of the these bits will not
result in a loss-of-lock condition. These bits are cleared by a hardware reset. The default
value is divide by 1 (VCO/2) which is 25 MHz in a 25-MHz system.
00 = Divide by 1 (normal operation)
01 = Divide by 4
10 = Divide by 16
11 = Divide by 64
INTEN—Interrupt Enable
These bits specify if the general system clock returns to high frequency (defined by the
DFNH bits) while the CPU32+ either has a pending interrupt or an interrupt routine in process, either of which has a level higher than INTEN2–INTEN0. To prevent interrupts from
causing the general system clock to automatically switch to high frequency, write INTEN
with 111.
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RRQEN—RISC Request Enable
This bit specifies if the general system clock returns to high frequency (defined by the
DFNH bits) while the CPM RISC controller is not idle.
0 = Remain in lower frequency (defined by DFNL) even if the RISC controller is not
idle.
1 = Switch to the high frequency (defined by DFNH) when the RISC controller needs
to execute a routine.
DFNL—Division Factor Lowest Frequency
These bits are required in two cases: 1) to reduce the general system clock to a frequency
lower than that which can be obtained in DFNH and 2) to automatically switch between
the DFNL rate and the DFNH rate. See 6.5.5 QUICC Internal Clock Signals for details on
how to automatically switch between the DFNH rate and the DFNL rate.
The user may load these bits with the desired divide value, and then set the CSRC bit to
change the frequency. Changing the value of the these bits will never cause a loss-of-lock
condition. These bits are cleared by a hardware reset.
000 = Divide by 2
001 = Divide by 4
010 = Divide by 8
011 = Divide by 16
100 = Divide by 32
101 = Divide by 64
110 = Reserved
111 = Divide by 256
DFNH—Division Factor High Frequency
Changing the value of these bits will never cause a loss-of-lock condition. These bits are
cleared (divide by 1) by a hardware reset. The default value is divide by 1 (VCO/2), which
is 25 MHz in a 25-MHz system. The user may write the DFNH bits at any time to change
the general system clock rate.
See 6.5.5 QUICC Internal Clock Signals for details on how to automatically switch between the DFNH rate and the DFNL rate.
000 = Divide by 1 (normal operation of general system clock when CSRC = 0)
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Reserved
CSRC—Clock Source Bit
The CSRC bit specifies whether the general system clock is determined by the DFNH or
the DFNL bits. Setting this bit switches the general system clock to the DFNL value (i.e.,
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for entering into low-power mode). Clearing this bit switches the general system clock to
the DFNH value. CSRC is cleared at hardware reset.
0 = General system clock is determined by the DFNH value.
1 = General system clock is determined by the DFNL value.
Freescale Semiconductor, Inc...
6.9.3.12 BREAKPOINT ADDRESS REGISTER (BKAR). This register contains the 32-bit
breakpoint address used in the breakpoint address match function. Its contents are only
valid if the valid bit is set in the BKCR. BKAR is undefined at reset.
31
BA31
U
30
BA30
U
29
BA29
U
28
BA28
U
27
BA27
U
26
BA26
U
25
BA25
U
24
BA24
U
23
BA23
U
22
BA22
U
21
BA21
U
20
BA20
U
19
BA19
U
18
BA18
U
17
BA17
U
16
BA16
U
15
BA15
U
14
BA14
U
13
BA13
U
12
BA12
U
11
BA11
U
10
BA10
U
9
BA9
U
8
BA8
U
7
BA7
U
6
BA6
U
5
BA5
U
4
BA4
U
3
BA3
U
2
BA2
U
1
BA1
U
0
BA0
U
6.9.3.13 BREAKPOINT CONTROL REGISTER (BKCR). This register contains miscellaneous bits required for the breakpoint address match function. BKCR is cleared at reset.
31
—
30
—
29
—
28
—
27
—
26
—
25
—
24
—
23
—
22
—
21
—
20
—
19
BAS
0
18
BUSS
0
17
RW1
0
16
RW0
0
15
SIZM
0
14
SIZ1
0
13
SIZ0
0
12
NEG
0
11
MA1
0
10
MA0
0
9
AS8
0
8
AS7
0
7
AS6
0
6
AS5
0
5
AS4
0
4
AS3
0
3
AS2
0
2
AS1
0
1
AS0
0
0
V
0
Bits 31–20—Reserved
BAS—Breakpoint Acknowledge Support
This bit determines whether to support the CPU32+ breakpoint acknowledge cycle by asserting BERR or ignore the breakpoint acknowledge cycle by allowing it to be handled by
the external bus.
0 = No action taken during CPU32+ breakpoint acknowledge cycles.
1 = Assert BERR during CPU32+ breakpoint acknowledge cycles.
NOTE
Do not assert this bit if the QUICC is in slave mode.
BUSS—Bus Select
This bit determines whether the breakpoint logic will use the IMB value or the external bus
value to detect breakpoint match.
0 = Use the IMB.
1 = Use the external bus. A0 and A1 are masked from the comparison.
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NOTES
This mode is used in QUICC slave operation to assert either the
BKPTO line for the external CPU or the internal IMB BKPT line
for an internal-to-internal IDMA/SDMA access. When the external bus is used, the breakpoint line will be asserted as if the
SIZM bit is set.
In the case of an external MC68040 burst, only the first address
of the burst is checked.
Freescale Semiconductor, Inc...
When the QUICC is in master mode this bit should be zero to
prevent external breakpoint from being ignored.
RW1–RW0—Read/Write Selection
Assert a breakpoint match on read cycles only, write cycles only, or on both.
00 = Assert breakpoint on read cycles.
01 = Assert breakpoint on write cycles.
10 = Assert breakpoint on read or write cycles.
11 = Reserved.
SIZM—Size Mask
This bit determines whether the breakpoint logic will use the SIZ bits to determine whether
a breakpoint match has occurred.
0 = Compare the size lines as programmed in the SIZ bits to determine whether a
breakpoint match has occurred.
NOTE
This mode would normally be used to break on an access to a
location that contains data.
1 = Mask the size lines. The size of the access is not used in determining whether a
breakpoint match has occurred. The breakpoint logic will assert the break signal
when the address and size overlaps the programmable value. For example if the
programmable address is xxx2, the breakpoint line for the low word will be asserted
when the access address is xxx2 with a word size or when the address is xxx0 with
a long-word size.
NOTE
This mode would normally be used to break on an instruction
fetch.
SIZ1–SIZ10—Size Bits
The breakpoint logic can cause a breakpoint match for accesses that correspond to the
size of the access. Set the SIZM bit to disable this feature.
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NOTES
The breakpoint logic will assert the break signal only when the
address and size match the programmable value. For example,
if the programmable address is xxx2 with word size, the breakpoint will be asserted only when the access address is xxx2 with
word size, not when the address is xxx0 with long-word size.
The MA bits must be 00 for the size comparison to occur.
Freescale Semiconductor, Inc...
00 =
01 =
10 =
11 =
Long Word
Byte
Word
3 Byte
Table 6-7. Breakpoint and Size Pin
Programmed BA1-BA0 (BKAR Reg)
00
01
10
11
6-46
IMB/EXT A1-A0
IMB/EXT SIZ1-SIZ0
Assert BKPT
00
x
Yes
01
x
No
10
x
No
11
x
No
00
00
Yes
00
01
No
00
1x
Yes
01
x
Yes
1x
x
Yes
00
00
Yes
00
01
No
00
10
No
00
11
Yes
01
00
Yes
01
01
No
01
1x
Yes
10
x
Yes
11
x
No
00
00
Yes
00
01
No
00
1x
No
01
00
Yes
01
01
No
01
10
No
01
11
Yes
10
00
Yes
10
01
No
10
1x
Yes
11
x
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NOTE
The table is true for the case SIZM=1.
Breakpoint will be asserted ONLY if the programmed address is
actually accessed.
Freescale Semiconductor, Inc...
Table 6-7 shows which combinations of A0-A1 and SIZ1-SIZ0, on eitherthe external bus or
the IMB bus, assert the BKPT pin.
NEG—Negative Breakpoint Match
This bit allows the breakpoint match to occur, using negative address matching logic,
when a block address is selected. If this bit is set, the rest of the address and address
match logic define when a breakpoint match is not to occur. The R/W, size, and FC compare logic are not affected by the NEG bit.
0 = Assert a breakpoint when the memory cycle matches the programmed values.
1 = Assert a breakpoint when the memory cycle does not match the programmed block
address. NEG is ignored if the MA bits are 00.
MA1–MA0—Mask Address
The address mask bits allow the breakpoint logic to assert the breakpoint on a memory
block boundary.
00 = No address bits are masked, 32 address bits are compared.
01 = Mask address bits 10–0; the block size is 2K.
10 = Mask address bits 12–0; the block size is 8K.
11 = Mask address bits 14–0; the block size is 32K.
NOTE
Using the NEG bit, the breakpoint can be asserted for accesses
that fall into the block range or for those that fall out of the block
range.
AS8–AS0—Address Space Bits
The address space field allows particular address spaces (function code combinations) to
be masked during the breakpoint match decision. If an address space is masked, an access to this space will NOT assert the BKPT pin. To ignore function codes in the breakpoint match decision, program these bits to zero. The address space bits are:
AS8—Mask DMA space address space (FC3–FC0 = 1xxx)
AS7—Mask CPU space address space (FC3–FC0 = 0111)
AS6—Mask supervisor program address space (FC3–FC0 = 0110)
AS5—Mask supervisor data address space (FC3–FC0 = 0101)
AS4—Mask [Motorola reserved] address space (FC3–FC0 = 0100)
AS3—Mask [user reserved] address space (FC3–FC0 = 0011)
AS2—Mask user program address space (FC3–FC0 = 0010)
AS1—Mask user data address space (FC3–FC0 = 0001)
AS0—Mask [Motorola reserved] address space (FC3–FC0 = 0000)
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The address space bits for 040 type MPU are:
AS8—Not Relevant for 040 Cycles
AS7—Acknowledge Access(TT1-TT0=11)
AS6—Supervisor Code Access(TT1-TT0=00, TM2-TM0=110)
AS5—Supervisor Data Access(TT1-TT0=00, TM2-TM0=101)
AS4—MMU Table search Code Access (TT1-TT0=00, TM2-TM0=100)
AS3—MMU Table search Data Access(TT1-TT0=00, TM2-TM0=011)
AS2—User Code Access(TT1-TT0=00, TM2-TM0=010)
AS1—User Data Access(TT1-TT0=00, TM2-TM0=001)
AS0—Data Cache Push Access(TT1-TT0=00, TM2-TM0=000)
For each address space bit:
0 = A breakpoint match can occur for this address space.
1 = Mask this address space from the breakpoint match logic. No breakpoint match will
occur if this address space is used on a bus access.
V—Valid
This bit indicates when the contents of the breakpoint address register and breakpoint
control register pair are valid. BKPT signal will not be asserted unless the valid bit is set.
0 = Contents not valid.
1 = Contents valid.
6.9.4 Port E Pin Assignment Register (PEPAR)
The PEPAR controls the I/O pins associated with the EBI. Refer to Section 4 Bus Operation
for more information about the EBI. Port E pins can be independently programmed to be
either CAS3–CAS0 or IACK6 and IACK3–IACK1; AVEC (or AVECO) or IACK5; CS3 or
IACK7; AMUX or OE; A31–A28 or WE3–WE0.
Until the low byte of PEPAR is written, the WE3–WE0/A31–A28 pins are three-stated. The
PWW bit indicates whether the low byte of PEPAR was written. PEPAR may be read or written at any time.
15
14
13
—
12
11
10
—
SINTOUT
9
8
IPIPE1/
RAS1DD
0
0
CF1MODE
0
7
0
6
0
5
0
4
0
3
0
2
0
1
A28–A31
WE0–WE3
OE/
AMUX
PWW
CAS2, 3
IACK3, 6
—
CAS0, 1
IACK1, 2
CS7
IACK7
0
0
0
0
0
0
0
AVEC or
(AVECO)/
IACK5
0
Bits 15, 11, and 3—Reserved
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Bits 14–12—SINTOUT
These bits should only be modified from its default when the QUICC is configured in slave
(disable CPU32+) mode. They are used to program the way the interrupt controller will
assert its interrupt requests to the external logic.
000 = Default (Used only in CPU enable mode).
001 = Reserved.
010 = The QUICC interrupt request is the RQOUT output function on the IRQ1 pin.
011 = The QUICC interrupt request is the IOUT2–IOUT0 outputs with the standard
M68000 family interrupt level encoding on the IRQ6, IRQ4, and IRQ1 pin, respectively.
100 = The QUICC interrupt request is the RQOUT output function on the PRTY2 pin.
101 = The QUICC interrupt request is the IOUT2–IOUT0 outputs with the standard
M68000 family interrupt level encoding on the PRTY0–PRTY2 pins, respectively.
110 = Reserved.
111 = Reserved.
NOTE
Until the low byte of PEPAR is written, the parity lines will be
three-stated. The user should write the high byte of PEPAR at
the same time that the low byte is written to avoid selecting a reserved combination of the SINTOUT bits.
Bits 10–9—CF1MODE
These bits are used to control the CONFIG1/BCLRO/RAS2DD pin functionality.
00 = CONFIG1 input pin function is chosen.
01 = CONFIG1 input pin function is chosen.
10 = The BCLRO output function is chosen instead of the CONFIG1 pin.
11 = RAS2DD output function (RAS2 double-drive) is chosen instead of the CONFIG1
pin.
Bit 8—IPIPE1/RAS1DD
0 = If the QUICC is in normal mode, the IPIPE1 output function is selected. If the
QUICC is in slave mode, the BCLRI input function is selected.
1 = The RAS1DD output function (RAS1 double-drive) is selected.
Bit 7—A31–A28/WE0–WE3
0 = The A31–A28 input/output functions are selected.
1 = The WE0–WE3 output functions are selected.
NOTE
Until the low byte of PEPAR is written, the WE3–WE0/A31-28
pins are three-stated.
Bit 6—OE/AMUX
0 = The OE output function is selected.
1 = The AMUX output function is selected.
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Bit 5—PWW
This read-only bit is used to indicate if the WE/ADDR and the PRTY lines have been programmed by the user or are still in the three-state condition because the PEPAR register
has not been written.
0 = PEPAR has not been written. The WE/ADDR and the PRTY lines are still being
three-stated.
1 = PEPAR was written. The WE/ADDR and the PRTY lines have been programmed
in the PEPAR, so the configuration choices of these pins in the PEPAR are valid.
Freescale Semiconductor, Inc...
Bit 4—CAS2, CAS3/IACK3, IACK6
0 = The CAS2 and CAS3 output functions are selected.
1 = The IACK3 and IACK6 output functions are selected.
Bit 2—CAS0, CAS1/IACK1, IACK2
0 = The CAS0 and CAS1 output functions are selected.
1 = The IACK1 and IACK2 output functions are selected.
Bit 1—CS7/IACK7
0 = The CS7 output function is selected.
1 = The IACK7 output function is selected.
Bit 0—AVEC (AVECO)/IACK5
0 = The AVEC input function is selected in normal operation, or AVECO is selected in
slave mode.
1 = The IACK5 output function is selected.
6.10 MEMORY CONTROLLER
The memory controller is a sub-block of the SIM60 that is responsible for up to eight generalpurpose chip-select lines and the DRAM controller. The DRAM controller itself can control
up to eight memory banks.
6.10.1 Memory Controller Key Features
The key features of the memory controller are as follows:
• All Eight Memory Banks Support the Following:
—32-Bit Address Decode with 17 Bits of Address Masking
—Various Block Sizes—2 Kbytes up to 256 Mbytes
—From 0 to 15 Wait States Programmable with DSACK Generation
—Memory Bank Can Be Used by an External Master
—Supports Burst Accesses of the MC68040
—Byte Parity Generation/Checking
—Write-Protect Capability
—Four Byte-Write Enable (WE) Signals
—Output Enable (OE) Signal
—Special Options for Interfacing to Slow Peripherals
—Function Code Match with Mask Can Qualify Memory Bank Accesses
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• General-Purpose Chip Selects (SRAM Banks)
—May Be Used with SRAM, EPROM, FEPROM, and Peripherals
—Global (Boot) Chip Select Available at System Reset
—Two-Clock Accesses to External SRAM
—Programmable Port Size of 8, 16, and 32 Bits for Each Chip Select
Freescale Semiconductor, Inc...
• DRAM Controller (DRAM Banks)
—Supports up to Eight Banks of DRAM of Size 128K × X, 256K × X, 512K × X,
1M × X, 2M × X, 4M × X, 8M × X or 16M × X
—Supports a DRAM Port Size of 16 or 32 Bits
—Internal Address Multiplexing for 16- and 32-Bit DRAM Systems Available for all OnChip Bus Masters
—Glueless Interface to One Bank of DRAM SIMMs (Only External Buffers Are Required for Additional SIMM Banks)
—Four CAS Lines
—Two of the Eight RAS Lines May Be Output on Two Pins Each for Double-Drive Capability
—Page Mode with Page Switch Detection Logic
—Page Mode Supports 128K, 256K, 512K, 1M, 2M, 4M, 8M, and 16M Page Banks
—Supports Page Mode Normal, Page Hit, and Page Miss
—Burst Support for the MC68040 Accesses to DRAM
• DRAM Controller Also Contains a Refresh Unit with:
—CAS Before RAS Refresh Support
—A Programmable Refresh Timer
—Refresh Active During External Reset
—Disable Refresh Mode
—Stacking of up to Seven Refresh Cycles
• DRAM Controller Also Supports External Masters
—Supports MC68EC040 with 3,2,2,2 Line Fill (60-ns DRAMs)
—Supports DRAM for External QUICC or MC68030-Type Accesses (Page Support
Available in this Mode)
—Supports DRAM Control for System Bus Containing External MC68EC040 and Multiple QUICCs
—Synchronous and Asynchronous External Masters Possible
—Special Options for External Master to Improve DRAM Performance
6.10.2 Memory Controller Overview
The block diagram of the QUICC memory controller is shown in Figure 6-10. The generalpurpose chip selects provide a glueless interface to EPROM, SRAM, flash EPROM
(FEPROM), and other peripherals. The general-purpose chip selects are available on lines
CS0–CS7. CS0 also functions as the global (boot) chip select for accessing the boot
EPROM. The chip selects allow 0 to 15 wait states.
The flexible memory controller allows a glueless DRAM interface to single in-line memory
modules (SIMMs) as well as a grid array of DRAMs on a board. The DRAM controller controls the address multiplexing, access mode, refresh operation, and the timing generation
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for up to eight banks of DRAMs. The DRAM controller provides eight RAS lines for up to
eight DRAM banks, four CAS lines and four parity (PRTY) lines (one for each data byte on
the QUICC system bus), and a parity error signal (PERR). The DRAM controller also provides multiplexed address lines for on-chip bus masters and an address mux signal (AMUX)
to support an external address muxing for external masters that wish to use the QUICC
DRAM controller for their accesses to DRAM. The DRAM controller also fully supports an
external MC68EC040 (or other MC68040 family variations) with the signals BADD2,
BADD3, TA, TS, and TBI.
Alternatively, a general-purpose chip select may be used instead of any DRAM bank.
Freescale Semiconductor, Inc...
NOTE
When one of the eight banks of memory is configured to control
DRAM, it is referred to as a DRAM bank. When one of the eight
banks of memory is configured to control standard memory
(such as SRAM and EPROM) or a peripheral, it is referred to as
an SRAM bank. Thus, the term “SRAM bank” is used to mean
“non-DRAM” in this description.
Some features are common to all eight memory banks. First, a full 32-bit address decode
for each memory bank is possible, with 17 bits having address masking. The full 32-bit
decode is available, even if all 32 address bits are not brought outside the QUICC. Each
memory bank includes a variable block size from 2 Kbytes up to 256 Mbytes). From 0 to 15
wait states may be programmed with DSACK generation. The memory bank can be used
by an external master, including the MC68EC040, in which case burst accesses are also
supported. Parity may be generated and checked for any memory bank (SRAM, DRAM,
etc.). Each memory bank may be selected for read-only or read/write operation. Byte-write
enable (WE) signals are available for each byte that is written to memory. Also, an output
enable (OE) signal is provided to eliminate external glue logic. Finally, the access to a memory bank may be restricted to only certain function codes for system protection. The function
code comparison occurs with a mask option also.
The memory controller functionality allows QUICC-based systems to be built very easily. For
instance, a minimal QUICC system may require no glue logic as shown in Figure 6-11. In
this example, CS0 is used for the boot EPROM, and RAS1 is used for the DRAM SIMM. The
WE signals are used to simplify the interface to the DRAM SIMM, and the OE signal is used
to simplify the interface to the EPROM. Byte parity is supported in this configuration.
NOTE:
If the WE signal of the QUICC is used to control memory write
operation, unless the memory width is 32 bit, the user must
specify the correct memory width with the SPS0-1 bits of the option register. For example, if the SPS is programed for a 16 bit
port size, only WE0 and WE1 will be asserted. If external assertion of DSACK is used due to the algorithm of dynamic bus sizing, the first bus cycle assumes a 32 bit port size and will output
WE for 32bit regardless of external DSACK encoding.
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.
BURST
COUNTER
ADDRESS
LATCH
AND
MUX
EXT/IMB—FC/TM,TT; A31–A0
SDBADD3–SDBADD2
SDMADD1–SDMADD13
BASE REGISTER (BR)
BASE REGISTER (BR)
GAMX BIT
PAGE
LOGIC
Freescale Semiconductor, Inc...
OPTION REGISTER (OR)
OPTION REGISTER (OR)
PAGE_MISS
BANK_MISS
RAS7/CS7
RAS6/CS6
RAS5/CS5
RAS4/CS4
RAS3/CS3
RAS2/CS2
RAS1/CS1
RAS0/CS0
ENCODER
REF_REQ (BR8)
REFRESH
COUNTERS (3, 12 BITS)
REF_ACK.
GLOBAL MEMORY REGISTER (GMR)
OE
WE3–WE0
CHIP SELECT ATTRIBUTES
EXPIRED
WAIT-STATE
COUNTER (4 BIT)
SELECT LOAD
TIMING
GENERATOR
AND LOGIC
CONTROL
CAS3–CAS0
RAS7–RAS0/CS7–CS0
AMUX
AS, TS, SIZE, BREQ, RD/WR
MEMORY CONTROLLER STATUS
(MSTAT)
D31–D0, PRTY3–PRTY0
DSACK1–DSACK0
TA, TBI
WP
PERR
PARITY
LOGIC
PERR
PRTY3–PRTY0
Figure 6-10. Memory Controller Block Diagram
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8-BIT BOOT
EPROM
(FLASH OR REGULAR)
QUICC
MC68360
CS0
CE (ENABLE)
OE
OE (OUTPUT ENABLE)
WE0
DATA
ADDRESS
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WE (WRITE)
DATA
ADDRESS
16- OR 32-BIT
DRAM SIMM
(OPTIONAL PARITY)
RAS1
CAS3–CAS0
R/W
RAS
CAS3–CAS0
W (WRITE)
DATA
ADDRESS
PRTY3–PRTY0
PARITY
Figure 6-11. Minimum QUICC System Configuration
If a larger system is required, the only additional glue logic that may be needed is external
buffers (see Figure 6-12). In this case, a boot EPROM and a flash EPROM are supported.
Also, two DRAM SIMMs are supported using RAS1 and RAS2.
Each of the eight memory banks may be used by an external master such as an
MC68EC040, MC68030, or even another QUICC. Whenever an external master accesses
DRAM, SRAM, or a peripheral within one of the regions of the memory banks, the memory
controller will control the access for that external master.
If DRAM is accessed by an external master, an external multiplexer must be provided. In
that case, the QUICC AMUX signal can be used to control the multiplexing. The DRAM controller supports use by an MC68EC040 and another QUICC or MC68030-type device. In
such a case, the MC68EC040 and QUICC/MC68030-type device can access the DRAM in
different modes and at different rates. For instance, the MC68EC040 can access the DRAM
using two-clock bursts, while an external QUICC accesses the DRAM using page mode with
three-clock page hits, four-clock page normal, and five-clock page miss accesses. Thus, the
MC68EC040 access to DRAM is not slowed by the presence of other slower masters on the
system bus. In addition, the MC68EC040 is not slowed by the performance of the DRAM
accesses by the QUICC's internal bus masters (CPU32+, IDMAs, SDMAs, etc.) All
accesses may occur at different rates, with the MC68EC040 parameters being programmed
independently and the external QUICC/MC68030-type master being up to one wait state
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slower than the QUICC's internal bus masters. The external master may be either synchronous or asynchronous with respect to the QUICC system clock, with the exception of the
MC68EC040, which must always be synchronous with respect to the QUICC system clock.
Thus, if a 25-MHz QUICC is used, a 25-MHz MC68EC040 should also be used.
If an external MC68040 master does not use the memory controller at all, then the QUICC
can operate asynchronously to the MC68040, but the QUICC MC68040 companion mode
signals cannot be used, and the MC68040 bus signals must be converted to MC68030-type
bus signals before the MC68040 accesses the QUICC's internal RAM and peripherals.
8-BIT BOOT
EPROM
(FLASH OR REGULAR)
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QUICC
MC68360
CS0
CE (ENABLE)
OE
OE (OUTPUT ENABLE)
WE (WRITE)
WE0
DATA
DATA
ADDRESS
ADDRESS
8-, 16-, OR 32-BIT SRAM
E (ENABLE)
CS7
G (OUTPUT ENABLE)
WE3–WE0
W (WRITE)
DATA
ADDRESS
16- OR 32-BIT
TWO-DRAM SIMMs
(OPTIONAL PARITY)
RAS2
RAS
RAS1
BUFFER
CAS3–CAS0
R/W
RAS
CAS3–CAS0
W (WRITE)
DATA
ADDRESS
PRTY3–PRTY0
PARITY
Figure 6-12. Larger QUICC System Configuration
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6.11 GENERAL-PURPOSE CHIP-SELECT OVERVIEW (SRAM BANKS)
Any memory bank that is not used to control DRAM may be used as a general-purpose chip
select, including pins CS0–CS7. This bank is called an SRAM bank. These pins may be
used to support external memory such as SRAM, EPROM, flash EPROM, EEPROM, and
peripherals.
Freescale Semiconductor, Inc...
The SRAM banks also have some unique features not available in the DRAM banks. First,
upon system reset, a global (boot) chip select is available. This provides a boot ROM chip
select before the system is fully configured. Second, the SRAM banks offer two-clock
accesses to external SRAM. Finally, each SRAM bank supports a choice of the port size of
its memory or peripheral to be 8, 16, or 32 bits with proper DSACK generation for those port
sizes. Thus, an 8-bit EPROM may be used with a 32-bit SRAM, etc.
6.11.1 Associated Registers
The general-purpose chip selects are controlled by the global memory register (GMR) and
the memory controller status register (MSTAT). There is one GMR and MSTAT in the memory controller. Additionally, each SRAM bank has a base register (BR) and an option register
(OR).
The GMR is used to control global parameters for both SRAM and DRAM banks.
The MSTAT reports write protect violations and parity errors for both SRAM and DRAM
banks.
The BR and the OR for each of the general-purpose chip selects program most of the features. The BR contains a valid (V) bit to indicate that the register information for that chip
select is valid.
6.11.2 8-, 16-, and 32-Bit Port Size Configuration
The general-purpose chip selects support dynamic bus sizing. Defined 8-bit ports are accessible on both odd and even addresses when connected to data bus bits 31–24; defined 16bit ports can be accessed as odd bytes, even bytes, or even words when connected to data
bus bits 31–16; and defined 32-bit ports can be accessed as odd bytes, even bytes, odd
words, and even words or long words on long-word boundaries. The port size is specified
by the SPS bits in the OR.
6.11.3 Write Protect Configuration
The WP bit in each BR can restrict write access to its range of addresses. Any attempt to
write this area will result in the WPER bit being set in the MSTAT.
6.11.4 Programmable Wait State Configuration
The general-purpose chip selects support internal DSACKx generation. They allow fast twoclock accesses to external memory by an internal bus master; from zero-wait-state
accesses (3 clocks) up to 14-wait-state accesses (17 clocks) are allowed for internal bus
masters. For external bus masters, two-clock accesses are not allowed, but 14 wait states
may be programmed. Additionally, if the EMWS bit is set in the GMR, the chip selects can
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provide one additional wait state for external masters, giving up to 15 wait states by the chip
selects. This is programmed using the TCYC bits in the OR.
6.11.5 Address and Address Space Checking
The defined base address is written to the BR. The address mask bits for that address are
written to the OR. The function code access value, if desired, is written to FC bits in the BR.
The FCM bits in the OR may be used to mask this selection. If the address space (function
code) checking is not desired, program the FCM bits to zero. Also, the chip select can be
configured not to assert during CPU space (i.e., interrupt acknowledge) cycles that have a
function code value 0111. This option is decided with the NCS bit in the GMR.
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6.11.6 SRAM Bank Parity
Parity can be configured for any SRAM bank. Parity is generated and checked on a per-byte
basis using PRTY3–PRTY0 if the PAREN bit is set in the BR. The OPAR bit in the GMR
determines the type of parity (odd or even), and the PBEE bit in the GMR determines if an
internal master should generate an error as a result of a parity error. Any parity error activates the PERR pin until the associated PERx bit in the MSTAT is cleared.
NOTE
Asynchronous external masters do not have parity support.
DW40 bit in the GMR must be set to support parity with external
040 master.
Parity is not supported for bus cycles terminated with external
assertion of DSACK or TA.
6.11.7 External Master Support
The SRAM banks support the internal bus masters, such as the CPU32+, IDMAs, and
SDMAs, as well as external bus masters, such as the QUICC, MC68030, or MC68EC040.
In the case of an external master, an additional wait state may be programmed into the
SRAM bank to compensate for the additional decoding time. This capability is programmed
in the EMWS bit of the GMR.
The MC68EC040 must always be synchronous to the QUICC clock. The SRAM bank supports bursting by the MC68EC040 if the BACK40 bit in the BR is set. During this access, CS,
PRTYx, PERR, DSACK/TA/TBI, and BADDR3–BADDR2 are all valid signals. The SRAM
bank waits for the MC68EC040 TS line to be asserted before starting any MC68EC040
access. Burst (line fill) transfers are also supported.
The chip-select logic supports MC68030/QUICC external masters in two modes. In the
asynchronous mode, the logic asserts the CS and DSACK lines as soon as an address
match is detected from the external master. The chip select in this mode is waiting for the
external master’s AS line to be asserted. In the synchronous mode, the CS and DSACK
assertion and negation timings are synchronous. The synchronous mode is programmed in
the SYNC bit of the GMR.
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When more wait states are programmed into the TCYC bits of the OR, the external AS (or
TS line) is synchronized internally.
The BADDR3–BADDR2 signals equal the A3–A2 signals when a burst is not in progress.
This configuration allows a non-bursting master to access the same memory as a bursting
external master by using the BADDR3–BADDR2 signals.
6.11.8 Global (Boot) Chip-Select Operation
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Global (boot) chip-select operation allows address decoding for a boot ROM before system
initialization occurs. CS0 is the global chip-select output. Its operation differs from the other
external chip-select outputs following a system reset. When the CPU32+ begins accessing
memory after a system reset, CS0 is asserted for every address, unless the MBAR is
accessed or an internal peripheral on the IMB is accessed.
The global chip select provides a programmable port size at system reset using the CONFIG
pins. This capability allows a boot ROM to be located anywhere in the address space (with
up to 14 wait states), while still providing the stack pointer and program counter values at
$00000000 and $00000004, respectively. The global chip select does not provide write protection and responds to all function codes. CS0 operates in this manner until the first write
to the CS0 option register (OR0). CS0 can be programmed to continue decoding a range of
addresses after this write, provided the desired address range is first loaded into base register 0. After the first write to the OR0, the global chip select can only be restarted with a
system reset.
6.11.9 SRAM Bus Error
The BERR signal may be asserted by the SRAM controller in the case of a parity error or by
the bus monitor of the SIM60 as a result of a write-protect violation. In addition, if the BERR
signal is asserted externally, it should not be asserted until at least S2 of the bus cycle.
6.12 DRAM CONTROLLER OVERVIEW (DRAM BANKS)
The DRAM controller supports a glueless interface to 16-bit (18 bit with parity) or 32-bit (36
bit with parity) DRAM or DRAM SIMMs from an internal QUICC master (CPU32+, IDMAs,
SDMAs). Many different DRAM bank sizes are supported: 128K, 256K, 512K, 1M, 2M, 4M,
8M, and 16M; thus, DRAMs such as 128K x 8, and 16M x 4 are supported. The DRAM controller performs the address multiplexing for internal masters using the low-order address
lines.
Table 6-8 lists the physical address lines of the DRAM (row and column). In the case of a
16-bit DRAM port size with a 512K DRAM device (e.g., two 512K x 8 devices for a total of
16 bits wide), the row address to the DRAM bank will be A19–A10, and the column address
to the DRAM bank will be A9–A1. However, these signals will be internally multiplexed on
the A10–A1 pins; thus, the user should connect A10–A1 to the address pins on each 512K
DRAM device.
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Table 6-8. Address Multiplexing
Address Lines (32-Bit Port)
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Physical Address
Address Lines (16-Bit Port)
Physical Address
DRAM Size
Column
Row
DRAM Address
Column
Row
DRAM Address
128K
A2–9
A10–18
A2–10
A1–8
A9–17
A1–9
256K
A2–10
A11–19
A2–10
A1–9
A10–18
A1–9
512K
A2–10
A11–20
A2–11
A1–9
A10–19
A1–10
1M
A2–11
A12–21
A2–11
A1–10
A11–20
A1–10
2M
A2–11
A12–22
A2–12
A1–10
A11–21
A1–11
4M
A2–12
A13–23
A2–12
A1–11
A12–22
A1–11
8M
A2–12
A13–24
A2–13
A1–11
A12–23
A1–12
16M
A2–13
A14–25
A2–13
A1–12
A13–24
A1–12
When there are external masters on the system bus, an external multiplexer should be used
for the DRAM banks that are accessed by the external masters. The DRAM controller provides this timing with the AMUX line.
The DRAM controller supports byte-level parity for any DRAM bank.
The DRAM controller use CAS-before-RAS refresh cycles. The refresh cycles are timed
using a dedicated refresh timer. The refresh operation can be disabled.
The DRAM controller supports normal access mode and several fast access modes:
• Normal Access Mode. In this mode, each access to DRAM is handled independently
using conventional DRAM timing.
• Page Mode. In this mode, the DRAM controller first establishes a constant row address,
and then strobes a series of column addresses into the DRAM. The DRAM controller
strobes both a row and a column address into the DRAM on the first access, but from
that point on, it strobes only column addresses into the DRAM during access periods to
the same DRAM page. After each access, the CAS signal is negated. The RAS line remains asserted until a different DRAM bank is accessed.
NOTE
This mode is not supported for external MC68040 masters.
• Burst Mode. In this mode, the DRAM controller detects the MC68EC040 line transfer
and strobes both a row and a column address into the DRAM on the first access, but
from that point on, it strobes only column addresses into the DRAM. For this access,
the DRAMC internally generates address lines 2 and 3 on the BADD3–BADD2 pins.
NOTE
Burst mode is supported for the MC68XX040 type master only.
During all DRAM accesses, RAS, CAS, R/W and DSACK/TA are valid signals. The following
paragraphs detail the operation of each DRAM controller access type.
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6.12.1 DRAM Normal Access Support
When accessing a DRAM, the DRAM controller uses the RAS and CAS pins. When an
access to a DRAM memory bank is made, a normal cycle occurs when DSSEL = 1 in the
OR, PGME = 0 in the OR, and BACK40 = 0 in the BR. The timing of the cycle is programmable using the TCYC bits in the OR.
A normal DRAM access can also be made by an external MC68EC040. In this case, the
WBT40 bit determines the RAS precharge time, and the TSS40 bit determines how TS is
sampled.
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A normal DRAM access can also be made by an external MC68030/QUICC. In this case,
the WBTQ bit determines the RAS precharge time.
The DRAM controller initiates a transaction by driving the row address on the low address
lines. After the value on the address pins is the row address, the DRAM controller asserts
RAS. One clock phase later, the column address is driven on the low address lines as
defined by the programmed DRAM size, and a clock phase later, the CAS signal is asserted.
If the cycle is a write transfer, then data is output at that point. The DRAM controller then
waits for the expiration of the TCYC length attribute and completes the cycle. The next cycle
will begin only after the value programmed in the WBTQ field expires.
The assertion of RAS can be delayed by one clock phase to relax the address to RAS timing
by setting the TRLXQ bit in the BR. When this bit is set the column address is driven one
clock later, and CAS is delayed by one clock (see Figure 6-16).
The DRAM controller may also generate and check four parity lines (PRTY3–PRTY0). The
parity can be either odd or even as programmed with the OPAR bit in the GMR. During write
cycles, the DRAM controller generates the parity on the four parity lines. During a read cycle,
the DRAM controller checks the parity. If the PAREN bit in the BR is set when a parity error
occurs, the DRAM controller asserts the PERR line and sets the PERx bit in the MSTAT.
For internal cycles, the DRAM controller will assert BERR when a parity error occurs and
the PBEE bit in the GMR is set.
NOTE
Read-modify-write cycles may be performed using the DRAM
controller. These are implemented as a read cycle followed by a
write cycle. Some DRAMs offer a special read-modify-write access using special timing. This access timing is not supported by
the QUICC's DRAM controller.
6.12.2 DRAM Page Mode Support
The DRAM banks supports a page mode memory access to DRAMs for the internal masters
and for an external QUICC/MC68030-type master. A memory bank is configured to page
mode if its DSSEL and PGME bits in the OR are set.
Many DRAMs support a page mode operation that reduces access time if multiple accesses
are performed within the same page. In this mode, the DRAM controller continues to assert
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the RAS signal of the DRAM bank. This RAS signal will remain active until another DRAM
bank is accessed. The page size is determined by the PGS bits in the GMR.
If a different bank of DRAM is accessed, followed by an access to a DRAM bank on which
page mode is selected, then the DRAM controller negates the RAS signal to the other bank
and asserts the particular RAS line for the page mode bank, followed by the rest of the
DRAM access. This is called a page mode normal cycle.
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On each access to a DRAM bank in which the page mode is enabled and the previous
DRAM cycle was to that bank, the address of the last access to this bank is compared to the
current address. If the two addresses fall within the same page, then the access cycle
begins immediately with the assertion of the column address and CAS signal. This is called
a page hit.
In case of a page miss (the address of the last access and current address do not fall within
the same page), the RAS signal must be negated and held high for a period that matches
the value programmed in the WBTQ control field of the current DRAM region, and then a full
cycle (including row and column phases) is executed. This is the slowest DRAM access
since the RAS signal must first be negated, followed by the precharge time.
Since it is difficult to predict the performance impact of page mode, the user may wish to try
the application software with and without page mode enabled, and compare the results. The
ability to concentrate the code/data accesses into the same page of the DRAM is central to
achieving a performance improvement.
Some systems will need an additional wait state to perform write cycles during a page hit.
To gain a wait state, set the delay write cycle for the QUICC DWQ bit in the GMR of the
DRAM bank.
NOTES
Page mode is supported only for the internal QUICC cycles or
external MC68030/QUICC cycles.
If any two DRAM banks overlap each other in their address
space, page mode must not be selected for either of those
banks.
6.12.3 DRAM Burst Access Support
The DRAM controller supports burst accesses made by an external MC68EC040 (or other
MC68040 family member) if the BACK40 bit is set in the BR. The MC68EC040 requests a
burst to be performed with a line-fill indication on the SIZx pins (SIZ = 11) and the TTx pins.
In this case, the DRAM controller performs a normal access (RAS and CAS), followed by
requests to the DRAM for the next three sequential long-word operands (CAS only). The
DRAM controller automatically increments the addresses to the DRAM using the BADDR3–
BADDR2 pins.
The length of an MC68EC040 burst cycle can be distinguished from the length of the initial
access with the BCYC bits of the OR.
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6.12.4 DRAM Bank Parity
Parity can be configured for any DRAM bank. Parity is generated and checked on a per-byte
basis using PRTY3–PRTY0 if the PAREN bit is set in the BR. The OPAR bit in the GMR
determines the type of parity (odd or even), and the PBEE bit in the GMR determines if an
internal master should generate an error as a result of a parity error. Any parity error activates the PERR pin until the associated PERx bit in the MSTAT is cleared.
NOTE
Asynchronous external masters do not have parity support.
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Parity is not supported for bus cycles terminated with external
assertion of DSACK or TA.
6.12.5 Refresh Operation
The DRAM controller uses CAS-before-RAS refresh cycles. The refresh cycles are timed
using a dedicated refresh timer. In the CAS-before-RAS method, the DRAMs have an internal refresh row address counter, so row addresses need not be supplied by the DRAM controller. These DRAMs recognize the assertion of CAS before the assertion of RAS and
perform the refresh using their internal refresh row address value.
Each time the refresh timer expires, the DRAMC performs a refresh cycle. At the first opportunity after acquiring bus mastership, the DRAM controller requests the bus with the highest
bus arbitration priority level 6. In addition, it asserts the BCLRO signal to minimize the delay
before the refresh cycle begins, assuming the external bus master recognizes this signal
and clears itself off the bus. Once the DRAM controller obtains the bus, it performs a refresh
bus cycle to the DRAM bank.
If more than one bank of DRAM exists in the system, the user should program the refresh
controller to request the bus more often (N times as often, where N is the number of banks).
For instance, typical DRAMs require a refresh every 15.6 µs. If 2 banks of DRAM exist in the
system, the DRAM controller should be programmed to refresh every 7.8 µs. In the two bank
case, the DRAM controller will alternate between the banks, using the CAS-before-RAS
technique on each bank every 7.8 µs.
The DRAM controller will automatically stack up to seven refresh requests before receiving
the bus mastership. Once it receives the bus, it will perform all stacked cycles (up to seven),
as sequential, back-to-back refresh bus cycles.
Refresh cycles are executed only when the RFEN bit in the GMR is set. The refresh cycle
length (three to six clocks) is programmed by the RCYC bits in the GMR. The time between
refreshes is programmed in the RCNT bits in the GMR (see 6.13.1 Global Memory Register
(GMR)).
NOTE
DRAM banks normally need eight read cycles and some delay
time after a power-on reset. After enabling the DRAM bank, the
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user can either perform the reads in software or wait for the
DRAM refresh controller to perform these reads.
6.12.6 DRAM Bank External Master Support
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The DRAM controller supports an external MC68EC040 as well as external MC68030-type
masters, including an external QUICC.
Whenever an external master is supported, external address multiplexing must be provided
by the user. The DRAM controller controls the multiplexing with the AMUX pin. On a normal
access, AMUX defaults high, and the upper address lines (row) should be multiplexed to the
DRAM first. After the external master outputs the full address, it asserts the AS/TS signal to
the QUICC. The DRAM controller then performs the address comparison, detects that the
access is to one of its DRAM banks, and issues the corresponding RAS signal. After the
assertion of the RAS signal, the DRAM controller continues the access and negates the
AMUX signal, controls the CAS and RAS timing, and generates the DSACK/TA signals to
terminate the access. Refer to Section 9 Applications for a description of an external master
system.
NOTE
To support the MC68030 cache fill operations, the DRAM controller asserts all four CAS signals during every QUICC/
MC68030-type external master read cycle to a DRAM bank.
(This includes byte or word reads by the MC68030.)
The DRAM controller supports the MC68EC040 in an optimized way. The DRAM controller
supports burst accesses made by an external MC68EC040 (or other M68040 family member) if the BACK40 bit is set in the BR. The MC68EC040 requests a burst to be performed
with a line-fill indication on the SIZx (SIZ = 11) and TTx pins. In this case, the DRAM controller performs a normal access (RAS and CAS), followed by requests to the DRAM for the
next three sequential long-word operands (CAS only). The DRAM controller automatically
increments the addresses to the DRAM using the BADDR3–BADDR2 pins.
6.12.7 Double-Drive RAS Lines
RAS1 and RAS2 have a special capability. To increase the available drive strength of these
pins, the RAS1 and RAS2 signals may be output simultaneously on two pins each. The extra
signals, called RAS1DD and RAS2DD, increase the effective drive strength of the RAS signals. This selection is made in the PEPAR.
6.12.8 DRAM Bus Error
The BERR signal may be asserted by the DRAM controller in the case of a parity error or by
the bus monitor of the SIM60 as a result of a write-protect violation. In addition, if the BERR
signal is asserted externally, it should not be asserted until at least S2 of the bus cycle if TSS
= 0 in the GMR, and until at least S4 of the bus cycle if TSS = 1 in the GMR.
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6.13 PROGRAMMING MODEL
The user interfaces with the memory controller using eight identical sets of two registers, the
BR and OR. There are also two global registers in the memory controller: the GMR and the
MSTAT.
6.13.1 Global Memory Register (GMR)
The 32-bit read-write GMR contains selections that are common to the entire memory controller: DRAM refresh properties, DRAM bank properties, SRAM bank properties, and some
global SRAM/DRAM properties. The reserved bits (4–0) should be written with zero.
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31
RCNT7
0
30
RCNT6
0
29
RCNT5
0
28
RCNT4
0
27
RCNT3
0
26
RCNT2
0
25
RCNT1
0
24
RCNT0
0
23
RFEN
0
22
21
RCYC1 RCYC0
0
0
20
PGS2
0
19
PGS1
0
18
PGS0
0
17
DPS1
0
16
DPS0
0
SUPERVISOR SPACE ONLY
15
WBT40
0
14
WBTQ
0
13
SYNC
0
12
EMWS
1
11
OPAR
0
10
PBEE
0
9
TSS40
1
8
NCS
0
7
DWQ
0
6
DW40
0
5
GAMX
0
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
The following bits are used for DRAM refresh properties.
RCNT7–RCNT0—Refresh Counter Period
These bits determine the refresh period according to the following equation:
Refresh period
=
RFCNT+1
System clk/16
Example: For a 25-MHz system clock and a required refresh rate of 15.6 µs per row, the
RFCNT value should be 24 (decimal). 24/(25 MHz/16) = 15.36 µs, which is less than the
required refresh period of 15.6 µs.
RFEN—Refresh Enable
0 = DRAM refresh is disabled.
1 = DRAM refresh is enabled.
RCYC1–RCYC0—Refresh Cycle Length
These bits determine the length of a refresh cycle.
00 = The refresh cycle is 4 clocks long, and RAS is negated for 3 phases prior to being
asserted.
01 = The refresh cycle is 6 clocks long, and RAS is negated for 5 phases prior to being
asserted.
10 = The refresh cycle is 7 clocks long, and RAS is negated for 5 phases prior to being
asserted.
11 = The refresh cycle is 8 clocks long, and RAS is negated for 5 phases prior to being
asserted.
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The following bits are used for DRAM bank properties:
PGS2–PGS0—Page Size
This attribute determines the page size for the DRAM controller (see Table 6-9). The page
size is the smallest DRAM size the user needs to support with page mode capability.
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Table 6-9. DRAM Page Size
PGS2-PGS0
Address Lines Used
# Address/Page in Page Compare
000
A10-25(32), A9-25(16)
256 Addresses
001
A11-25(32), A10-25(16)
512 Addresses
010
A11-25(32), A10-25(16)
512 Addresses
011
A12-25(32), A11-25(16)
1024 Addresses
100
A12-25(32), A11-25(16)
1024 Addresses
101
A13-25(32), A12-25(16)
2048 Addresses
110
A13-25(32), A12-25(16)
2048 Addresses
110
A14-25(32), A13-25(16)
4096 Addresses
For instance, PGS = 001 (256K) should be used for a 32-bit-wide memory composed of
four 256K × 8 devices, a 16-bit-wide memory composed of two 256K × 8 devices, or sixteen 256K × 1 devices. In all cases, the width of the DRAMs is irrelevant.
DPS1–DPS0—DRAM Port Size
This attribute determines the DRAM bank port size (see Table 6-10). The DRAM controller
asserts the appropriate DSACKx lines according to these bits. If an MC68EC040 access
is performed using this DRAM bank and SPS = 00 or 01, the DRAM controller operates
the same way, but asserts TA instead of DSACK.
Table 6-10. DRAM Port Size
DPS1–DPS0
Result
00
DRAM Port Size Is 32 Bits
01
DRAM Port Size Is 16 Bits
10
Reserved
11
External DSACKx Support
NOTES
The internal DRAM address multiplexer and the page logic support only a port size of 32 bits or 16 bits. An 8-bit DRAM port size
is not allowed.
The DRAM controller does not support an external DSACKx response for a bank on which page mode is used. Also, an external DSACK response may not occur before RAS is asserted.
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The DRAM controller does not support an external TA response
for the MC68040 burst mode. Also, for non-burst MC68040 cycles, TA cannot be externally asserted before RAS is asserted.
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WBT40—Wait Between Transfers (MC68EC040)
This attribute guarantees a minimum negation time for RAS when the QUICC DRAM controller is used by an external MC68EC040 master. It is used to comply with the RAS precharge time in DRAMs.
The user would normally decide whether to set the TSS40 bit before setting this bit.
0 = RAS is negated for 4 phases of the QUICC system clock (3 phases if
TSS40 = 1).
1 = RAS is negated for 6 phases (5 phases if TSS40 = 1).
NOTE
TSS40 affects the WBT40 value in order to gain back one of the
two phases that was lost by setting TSS40 = 1. This “gain back”
only applies to back-to-back DRAM cycles.
WBTQ—Wait Between Transfers (QUICC-Type)
This attribute guarantees a minimum negation time for RAS when the QUICC DRAM controller is used by one of the internal masters or by an external master of the MC68030type (includes an external QUICC). It is used to comply with the RAS precharge time in
DRAMs.
0 = RAS is negated for 4 phases (3 phases in page mode—PGME = 1).
1 = RAS is negated for 6 phases (5 phases in page mode—PGME = 1).
DWQ—Delay Write for QUICC (DRAM Bank Only)
This attribute is used to add a clock to the assertion and negation of the CAS signal on
DRAM page hit write cycles. The write cycle lasts one additional clock in this case. This
attribute is applicable to an internal QUICC master and to an external MC68030/QUICC.
0 = Reads and writes are the same length.
1 = Add one clock to write cycles for DRAM banks where TCYC is set to 01.
NOTE
This bit must be set by the user if page mode is enabled for this
DRAM bank (PGME = 1), or else the DRAM may latch invalid
data during writes.
The following bits are used for SRAM bank properties:
DW40—Delay Write for 040 (SRAM Bank Only)
This attribute should be set if an additional wait state is necessary for SRAM write cycles.
This attribute is applicable only to an external MC68040 writing to a non-DRAM bank.
0 = Reads and writes are the same length.
1 = Insert one additional wait state to MC68040 write cycles to SRAM banks.
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EMWS—External Master Wait State (SRAM Bank Only)
This attribute should be set if an additional wait state is necessary when an asynchronous
external MC68030-type device or external QUICC is accessing SRAM banks (see Table
6-11). This bit is only used if SYNC = 0.
0 = Normal operation.
1 = Insert one additional wait state for external QUICC/MC68030-type masters on their
accesses to all SRAM banks.)
Table 6-11. External MC68030-Type Cycle Length
(SRAM Bank in Asynchronous Operation
External QUICC/MC68030-Type Bus Cycle Length
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Synchronous Bus Timing
(BSTM = 1)
TCYC =
Asynchronous Bus Timing
(BSTM = 0)
EMWS = 0
EMWS = 1
EMWS = 0
EMWS = 1
0
3
3
3
3
1
3
4
3
5
2
4
5
5
6
3
5
6
6
7
4
6
7
7
8
5
7
8
8
9
6
8
9
9
10
…
15
…
…
…
…
17
18
18
19
NOTE: The BSTM bit is located in the MCR of the SI60.
The following bits are used for both DRAM and SRAM memory:
SYNC—Synchronous External Access MC68030-Type
This attribute applies only to an external MC68030-type device or external QUICC that
uses the on-chip memory controller. It determines how the memory controller will assert
its signals in response to what it sees from the external master.
0 = Asynchronous operation of the memory controller (external MC68030-type master
only).
When the SRAM controller is used, CS and DSACK assertion and negation timings are
asynchronous. They are asserted and negated in relation to the external master’s AS line.
The CSNTQ and the TRLXQ attributes are ignored. When EMWS is set, one wait state is
added to the programmed TCYC.
When the DRAM controller is used, CAS and DSACK are negated asynchronously with
the negation of the external master’s AS.
NOTE
The DRAM controller’s assertion of RAS and CAS is always synchronous to the QUICC clock. When asynchronous external
masters are using the DRAM controller, the BSTM bit in the
MCR should be cleared.
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1 = Synchronous operation of the memory controller (external MC68030-type
master only).
When the SRAM controller is used, CS and DSACK assertion and negation timings are
synchronous. The CSNTQ and the TRLXQ attributes may be set as desired.
When the DRAM controller is used, CAS and DSACK are negated synchronously to the
QUICC clock.
Only when the SYNC bit is set, is parity support possible for an external MC68030-type
master.
Table 6-12 summarizes the effects of the various combinations of the SYNC bit in the GMR
and the BSTM bit in the MCR.)
Freescale Semiconductor, Inc...
Table 6-12. SYNC-BSTM Bit Combination Summary
(MC68030-Type External Master)
SYNC-BSTM
Result
00
MC68030-type master and QUICC can be asynchronous. Lowest performance, since the external AS signal is synchronized prior to being used. Parity support is not available.
01
External MC68030-type master is running synchronously with the QUICC, and the user desires
to make external-to-external SRAM accesses as fast as possible. The CSNTQ and TRLXQ attributes may not be used. Does not affect DRAM performance. Parity support is not available.
10
Do not use.
11
Not as fast as case 01, but CSNTQ and TRLXQ attributes may be used. Parity support is available.
NOTES:
If Synchronous bus mode is selected, glue logic is required for external MC68030-type bus master (including
MC68360) ensuring that proper set up time for address strobe assertion is met
OPAR—Odd Parity
This attribute is used to program odd or even parity. It may also be used to generate parity
errors for testing purposes by writing the DRAM/SRAM with OPAR = 1 and reading the
DRAM/SRAM with OPAR = 0.
0 = Even parity
1 = Odd parity
PBEE—Parity Bus Error Enable
This attribute is used to enable an internal bus error if a parity error is detected. It is applicable only when the QUICC is the bus master; if in slave mode the PERR will be asserted if the parity function is enabled but it will not cause bus error regardless of the
setting of this bit. The BERR signal will be internally asserted on the memory read cycle.
0 = Disable internal bus error.
1 = Enable internal bus error.
NOTE
Using the internal bus error requires a longer data setup time for
read cycles.
TSS40—TS Sample (MC68EC040)
This attribute is used to control the MC68EC040 cycles. When the MC68EC040 address
to clock setup timing does not meet the memory controller decoding time, the memory
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controller may sample TS with a one-clock-phase delay. This will delay the assertion of
the CS or RAS in the MC68EC040 memory cycle by one clock phase. It will delay the rest
of the bus cycle by one clock (effectively adding one extra clock cycle per bus cycle).
NOTE
In general, the user determines whether this bit must be set before to selecting the WBT40 and TCYC bits.
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0 = Do not sample TS.
1 = Sample TS prior to using it.
NCS—No CPU Space
This attribute specifies whether the CS/RAS signal will assert on a CPU space access cycle. If both supervisor data and program accesses are desired, while ignoring CPU space
accesses, then this bit should be set. (Note that an interrupt acknowledge cycle is a CPU
space access, but a user or supervisor read/write cycle is not.) A CPU space access has
the function code value 0111.
0 = Assert CS/RAS on CPU space accesses (default).
1 = Suppress CS/RAS on CPU space accesses.
NOTE
In default state, user should program the FC3-FC0 in both the
Option Registers and Base Registers so that CS/RAS will not
get asserted in an undesirable address range.
GAMX—Global Address Mux Enable
This attribute determines whether the QUICC will provide internal address multiplexing for
DRAM banks. If not, the address multiplexing must be provided externally, with the
QUICC’s AMUX pin being used to control the multiplexers. AMUX is high to signify the
row, low to signify the column address, and then negated (high) at the end of the DRAM
bus cycle.
There are two situations in which the user may wish to provide address multiplexing externally. First, external multiplexers are required when an external master exists in the
system and that external master needs to access the DRAM. Second, using external address multiplexing causes the clock to address valid timing as slightly accelerated, which
may be beneficial in certain high-performance situations.
0 = Disable internal address multiplexing for all DRAM banks.
1 = Enable internal address multiplexing for all DRAM banks.
Bits 4–0—Reserved
6.13.2 Memory Controller Status Register (MSTAT)
The MSTAT register reports memory controller error information to the user. These bits are
set, regardless of whether an internal or external master originated the cycle. Bits are reset
by writing a one to that bit; writing a zero has no effect. The register may be read at any time
and is cleared by reset. No interrupts are generated from this register; however, an internal
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master may generate a bus error as a result of this register, and for parity errors, the PERR
pin may be externally connected to an interrupt input.
15
—
14
—
13
—
12
—
11
—
10
—
9
—
8
WPER
7
PER7
6
PER6
5
PER5
4
PER4
3
PER3
2
PER2
1
PER1
0
PER0
Bits 15–9—Reserved
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WPER—Write Protect Error
This bit is asserted when a write protect error occurs. A bus monitor (BERR assertion) will
(if enabled) prompt the user to read this register if no DSACK is provided on a write cycle.
The accessed address will be in the BERR exception descriptor. WPER is cleared by writing one to this bit or by performing a system reset. Writing a zero has no effect on WPER.
PERx—Parity Error
These bits indicate that a parity error was detected when reading from bank N. BERR is
internally asserted if PBEE in the GMR is set and if an internal master performs this cycle.
The PERR signal is continuously asserted until all PERx bits are cleared. PERx is cleared
by writing one or by performing a system reset. Writing a zero has no effect on PERx.
NOTE
If external masters of the MC68030-type (including QUICCs) are
chosen to be asynchronous (configured by clearing the SYNC
bit in the GMR), then they have no parity support.
6.13.3 Base Register (BR)
This register is used for both DRAM and SRAM banks. Most bits are valid for both the DRAM
and SRAM banks, but some bits are only valid for SRAM banks. This register is a 32-bit
read-write register that may be accessed at any time.
31
BA31
0
30
BA30
0
29
BA29
0
28
BA28
0
27
BA27
0
26
BA26
0
25
BA25
0
24
BA24
0
23
BA23
0
22
BA22
0
15
BA15
0
14
BA14
0
13
BA13
0
12
BA12
0
11
BA11
0
10
FC3
0
9
FC2
0
8
FC1
0
7
FC0
0
6
TRLXQ
1
21
BA21
0
20
BA20
0
5
4
BACK40 CSNT40
0
1
19
BA19
0
18
BA18
0
17
BA17
0
16
BA16
0
3
CSNTQ
0
2
PAREN
0
1
WP
0
0
V
0
V—Valid Bit
This bit indicates that the contents of the BR and OR pair are valid. The CS/RAS signal
will not assert until the V-bit is set.
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NOTE
An access to a region that has no V-bit set may cause a bus
monitor timeout.
0 = This DRAM/SRAM bank is invalid.
1 = This DRAM/SRAM bank is valid.
NOTE
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Following a system reset, the V-bit is set in BR0 if the global chip
select is enabled. See the CONFIG pins for more details.
WP—Write Protection
This bit can restrict write accesses within the address range of a BR. An attempt to write
to the range of addresses specified in a BR that has this bit set can cause the BERR signal
to be asserted by the bus monitor logic (if enabled), causing termination of this cycle.
0 = Both read and write accesses are allowed.
1 = Only read accesses are allowed. The RAS/CS signal, TA, and DSACK will not be
asserted by the QUICC on write cycles to this memory bank. WPER will be set in
the MSTAT register if a write to this memory bank is attempted.
PAREN—Parity Checking Enable
This bit is used to enable checking of parity on either an SRAM or DRAM bank.
0 = Parity checking is disabled.
1 = Parity checking is enabled.
NOTE
Parity checking is not possible for asynchronous external masters.
CSNTQ—CS Negate Timing QUICC (SRAM Bank Only)
This bit is used to determine when CS is negated during an internal QUICC or external
QUICC/MC68030-type bus master write cycle. This is helpful to meet address/data hold
time requirements for slow memories and peripherals (see Figure 6-13 and Figure 6-14).
0 = CS is negated normally (as late as possible).
1 = CS is negated one phase earlier, but the cycle length is not affected.
NOTE
CSNTQ is ignored for an SRAM cycle by an external master if
the SYNC bit is cleared. CSNTQ = 1 is not valid for external
DSACK assertion
CSNT40—CS Negate Timing MC68EC040 (SRAM Bank Only)
This bit is used to determine when CS is negated during an MC68EC040 write cycle. This
is helpful to meet address/data hold time requirements (see Figure 6-15).
0 = CS is negated normally (as late as possible).
1 = CS is negated one phase earlier, but the cycle length is not affected.
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NOTE
CSNT40 is ignored for an SRAM cycle by an external master if
the SYNC bit is cleared. CSNT40 = 1 is not valid for external
DSACK assertion
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BACK40—Burst Acknowledge MC68EC040
This bit is used to acknowledge a burst cycle to the MC68040. If set, bursts are enabled
in this bank. The QUICC generates address lines 2,3 on the BADDR3–BADDR2 pins.
0 = Do not acknowledge burst.
1 = Acknowledge burst; MC68040 bursts are handled by the memory controller for this
bank.
TRLXQ—Timing Relax
This bit delays the beginning of the internal QUICC or external QUICC/MC68030-type bus
master cycle to relax the timing constraints on the user. This attribute is useful for slow
peripherals that require additional address setup time. Chip selects are delayed by one
phase, and the cycle is delayed by one clock. For accesses to DRAM, RAS is delayed by
one phase, and CAS and AMUX are delayed by two phases, giving a total cycle increase
of one clock. See Figures 6-16 and 6-17 for timing diagrams of different cases.
0 = Do not relax timing.
1 = Relax timing at the beginning of the cycle. One additional clock cycle is added
when this bit is set.
NOTE
TRLXQ is ignored for an SRAM cycle by an external master if
the SYNC bit is cleared.
To relax the MC68EC040 cycles, use the TSS40 bit in the GMR.
User should avoid setting both TRLXQ and CSNTQ = 1, when
TCYC = 0. This bit combination will result in a bus cycle without
CS assertion.
FC3–FC0—Function Code
This field can be used to specify that accesses with the memory bank be limited to a certain address space type. These bits are used in conjunction with the FCM3–FCM0 bits in
the OR.
BA31–BA11—Base Address
The base address field, the upper 21 bits of each BR, and the function code field are compared to the address on the address bus to determine if a DRAM/SRAM region is being
accessed by an internal QUICC master.
If the SRAM/DRAM region is being accessed by an external master and the WE lines are
not used, then A31–A28 address lines and the BA31–BA28 bits are also used in the comparison. If, however, the SRAM/DRAM region is being accessed by an external master
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and the A31–A28 lines are configured as WE lines, then the user should write zeros to the
BA31–BA28 bits so that A31–A28 will be masked by the address comparison logic.
CLKO1
S4
S5
S0
AS (OUTPUT)
CS BEFORE
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CS NOW
Figure 6-13. CSNTQ = 1 During an Internal Cycle
CLKO1
S4
S5
S0
AS (INPUT)
CS BEFORE
CS NOW
Figure 6-14. CSNTQ = 1 During an External QUICC/MC68EC030 Cycle
CLKO1
C2
C3
C0
TA (OUTPUT)
CS BEFORE
CS NOW
Figure 6-15. CSNT40 = 1 During an External MC68EC040 Cycle
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S1
S2
S3
ADDRESS
RAS CS
TRLXQ = 1
TRLXQ = 0
AMUX
CAS
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DSACK
Figure 6-16. TRLXQ = 1 During an Internal Cycle
CLKO1
S1
S0
S2
S3
S4
S5
ADDRESS
AS
RAS CS
TRLXQ = 1
AMUX
TRLXQ = 0
CAS
DSACK
Figure 6-17. TRLXQ = 1 During an External QUICC/MC68030 Cycle
6.13.4 Option Register (OR)
This register is used for both DRAM and SRAM banks. Most bits are valid for both banks,
but some bits are only valid for DRAM banks, and others are only valid for SRAM banks.
This register is a 32-bit read-write register that may be accessed at any time.
31
TCYC3
1
30
TCYC2
1
29
TCYC1
1
28
TCYC0
1
27
AM27
0
26
AM26
0
25
AM25
0
24
AM24
0
23
AM23
0
22
AM22
0
21
AM21
0
20
AM20
0
19
AM19
0
18
AM18
0
17
AM17
0
16
AM16
0
15
AM15
0
14
AM14
0
13
AM13
0
12
AM12
0
11
AM11
0
10
FCM3
0
9
FCM2
0
8
FCM1
0
7
FCM0
0
6
BCYC1
0
5
BCYC0
0
4
—
0
3
PGME
0
2
SPS1
0/1
1
SPS0
0/1
0
DSSEL
0
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DSSEL—Dynamic RAM Select
This bit determines if the bank is a DRAM or SRAM, which impacts a number of signals:
1) the length of the cycle is different; 2) address muxing is performed if GAMX = 1; and 3)
the previous RAS is negated if a page bank miss occurs and DSSEL = 1 (for the new
bank).
0 = SRAM bank (i.e., SRAM, EPROM, peripherals, etc.)
1 = DRAM bank
SPS1–SPS0—SRAM Port Size (SRAM Bank Only)
This attribute determines whether a given chip select responds with DSACKx and, if so,
what port size is returned (see Table 6-13).
If the cycle is terminated by using the internal wait-state attributes, the QUICC drives the
DSACKx lines according to those bits. If the internal wait-state attributes are not used, the
cycle should be terminated with external DSACKx. In this case, the QUICC does not drive
the DSACKx lines, but rather samples them at every falling edge of the clock.
If an MC68EC040 access is performed using this SRAM bank and SPS= 00, 01, or 10,
the SRAM controller operates in the same way, except it asserts TA instead of DSACKx.
If SPS= 11, TA is sampled at every rising edge of the clock.
Table 6-13. SRAM Port Size
SPS1–SPS0
Result
00
32-Bit Port Size
01
16-Bit Port Size
10
8-Bit Port Size
11
External DSACKx Response
NOTES
If DSACK is provided internally, then the DSACKx lines are still
sampled externally, and can be asserted externally to end the
cycle. However, in this case of external DSACKx assertion, external DSACKx should be asserted and negated prior to when
internal DSACK would have been asserted by the QUICC. This
is easily accomplished on the boot chip select since the QUICC
default value is 14 wait states.
The SRAM controller does not support an external TA response
for MC68040 burst mode. Also, for non-burst MC68040 cycles,
TA cannot be externally asserted before CS is asserted.
PGME—Page Mode Enabled (DRAM Banks Only)
This bit is used to enable page mode accesses to a DRAM bank. Page mode accesses
are performed only for an internal QUICC or an external QUICC/MC68030-type master.
0 = Page mode is disabled.
1 = Page mode is enabled.
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NOTE
When the DRAM controller supports MC68EC040 cycles,
PGME must be cleared by the user, or erratic behavior may occur.
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Bit 4—Reserved
BCYC1–BCYC0—Burst Length Cycle in Clocks
These bits determine the number of wait states inserted in an MC68040 burst cycle. This
attribute is for the second, third, and fourth access of the burst cycle. Program TCYC3–
TCYC0 for the first access.
00 = The burst cycles are 1 clock in length (x,1,1,1).
01 = The burst cycles are 2 clocks in length (x,2,2,2).
10 = The burst cycles are 3 clocks in length (x,3,3,3).
11 = The burst cycles are 4 clocks in length (x,4,4,4).
FCM0–FCM3—Function Code Mask
This field can be used to mask certain function code bits, allowing more than one address
space type to be assigned to a chip select. Any set bit causes the corresponding function
code pin to be used as part of the address comparison. Any cleared bit masks the corresponding function code bit. If both supervisor data and program accesses are desired,
while ignoring CPU space accesses, then the NCS bit in the GMR should be set.
NOTE
Clear the FCM bits to ignore function codes as part of the address comparison.
Regardless of the setting in this register, an external encoding of
X111 of the function code pins will be taken as a CPU space access.
AM27–AM11—Address Mask
The address mask field, bits 27–11 of each OR, provides for masking any of the corresponding bits in the associated BR. By masking the address bits independently, external
devices of different address range sizes can be used. Any cleared bit masks the corresponding address bit. Any set bit causes the corresponding address bit to be used in the
comparison with the address pins. Address mask bits can be set or cleared in any order
in the field, allowing a resource to reside in more than one area of the address map. This
field can be read or written at any time.
NOTES
When address lines A31–A28 are multiplexed with the WE lines,
the A31–A28 lines are still used in the comparison by an internal
QUICC master. See the base address bit description in 6.13.3
Base Register (BR).
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If two chip selects are programmed to assert in the same address region, only the lower chip select (or RAS line) will assert.
For example, CS1 has priority over CS4.
TCYC3–TCYC0—Cycle Length in Clocks
This field determines the length of a bus cycle (see Table 6-14). Both internal masters and
external masters use this field for their accesses to a given memory bank. In addition, an
external MC68040 uses this field for the first access of a burst access sequence.
Although TCYC3–TCYC0 is the main parameter for determining cycle length since it selects the number of wait states inserted in the cycle, the total cycle length may vary for
other reasons, such as a DRAM page hit, DRAM page miss, or whether the bus master
is internal or external to the QUICC. Besides TCYC, other bits that can affect the total cycle length in certain situations are WBT40, WBTQ, DWQ, DW40, EMWS, SYNC, and
TSS40 in the GMR, and TRLXQ, PGME, and BCYC in the OR. CSNTQ and CSNT40 affect the CS timing, but do not affect the total cycle length.
If the user has selected an external DSACKx or TA response for this memory bank, with
the SPS or DPS bits, then TCYC3–TCYC0 are not used.
Table 6-14. Cycle Length in Clocks
Internal QUICC Master Memory Bus Cycle Length
Number of Clocks
Number of Wait States
(SRAM)
Number of Wait States
(DRAM)
TCYC =
Number
Comments
Number
Comments
Numbers
0
2
Fast Termination
*
Undefined
3
1
3
Normal
0
4
2
4
1
5
3
5
2
6
4
6
3
7
5
7
4
8
6
8
5
9
…
…
…
…
15
17
14
18
NOTES
External cycles are always three clocks or longer. SeeTable 611 for more details.
Normal DRAM cycles are three clocks when TCYC=0 and four
clocks when TCYC=1, etc. Therefore fast termination is not possible during the initial access to DRAM. Two clock DRAM cycles
are only possible when page mode is enabled for an internal
master.
If an external DSACK response is selected with either DPS in
the GMR or SPS in the OR, TCYC should not be set to zero.
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6.13.5 DRAM-SRAM Performance Summary;
Table 6-15 lists the performance results possible when setting TCYC = 0, assuming a 25MHz system clock, 60-ns DRAMs, and 15-ns SRAMs. The items marked with a dash are not
applicable to the situation.)
Table 6-15. Maximum DRAM/SRAM Performance (25 MHz
External QUICC/
MC68030 Type
External MC68040
(TSS40 = 0)
External
MC68EC040
(TSS40 = 1)
2 (See note 2)
3
2
3
Burst
—
—
2, 1, 1,1
3,1,1,1
DRAM Normal
3*
4
3*
4
DRAM Normal Back-toBack Access
4*
4
4*
5
Page Hit
2
3
—
—
Page Miss
4*
5
—
—
Line Fill
—
—
3*, 2, 2, 2
4,2,2,2
Memory Move
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SRAM Normal
Internal Master
NOTES:
1.For 70-ns DRAMs, items marked with an asterisk should have one additional clock added.
2.For the internal master case, the QUICC also supports two-clock accesses with 20-ns SRAMs.
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SECTION 7
COMMUNICATION PROCESSOR MODULE (CPM)
INTRODUCTION
The CPM includes many blocks that work together to allow an extremely flexible and integrated approach to solving many communications problems. The CPM (see Figure 7-1) includes the following modules:
Freescale Semiconductor, Inc...
• RISC Controller
• Four Full-Duplex Serial Communication Controllers (SCCs) Support the Following Protocols:
—IEEE 802.3/Ethernet (Optional Feature on SCC)
—High-Level/Synchronous Data Link Control (HDLC/SDLC)
—HDLC Bus (Multidrop Bus Configuration of HDLC)
—AppleTalk (HDLC-Based Local Area Network (LAN) Protocol)
—Universal Asynchronous Receiver Transmitter (UART)
—Synchronous UART (Isochronous, 1x Clock Mode)
—Binary Synchronous Communication (BISYNC)
—Totally Transparent Operation
—Signaling System #7 (HDLC-Based Protocol. RAM Microcode Option Only)
— Profibus (RAM Microcode Option Only)
—Asynchronous HDLC (RAM Microcode Option Only)
—Multiple Chanel GCI (RAM Microcode Option Only)
—ATM Framing (RAM Microcode Option Only)
—Enhanced Ethernet Filtering (RAM Microcode Option Only)
• Four Independent Baud Rate Generators
• Two Serial Management Controllers (SMCs) Provide Additional UART and Totally
Transparent Functionality or Support the GCI Channel 0 and 1 Monitor and C/I Channels in Integrated Services Digital Network (ISDN)
• Serial Interface Provides Nonmultiplexed Serial Interface (NMSI) for the Four SCCs (includes TXD, RXD, TCLK, RCLK, RTS, CTS, and CD pins)
• Time Slot Assigner (TSA) Supports Multiplexing of Data from any of the Four SCCs and
Two SMCs onto Two Time-Division Multiplexed (TDM) Interfaces. The TSA Supports
the Following TDM Formats:
—T1/CEPT Lines
—Pulse Code Modulation (PCM) Highway Interface
—ISDN Primary Rate
—Motorola Interchip Digital Link (IDL)
—General Circuit Interface (GCI), also known as IOM-2
—User-Defined Interfaces
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Introduction
• Serial Peripheral Interface (SPI) for Synchronous Interchip Communication
• Fourteen Serial Direct Memory Access (SDMA) Channels Support the SCC, SMCs,
and SPI
• Two Independent Direct Memory Access (IDMA) Channels Support External Memory
and Peripherals
• A Command Set Register Supports the RISC, IDMA, SCCs, SMCs, and SPI
• Four General-Purpose 16-Bit Timers or Two 32-Bit Timers
• Internal Timers to Implement Up to 16 Additional Timers
• General-Purpose Parallel Port for Parallel Protocols such as Centronics (Can Also Be
Used as Standard Parallel I/O)
• 2.5-kbyte Dual-Port RAM
• Twelve Parallel I/O Lines with Interrupt Capability
IMB
CPM
PAR
I/O
BRG
PARALLEL
INTERFACE
PORT (PIP)
DUAL-PORT
RAM
INTERRUPT
CONTROLLER
FOUR
TIMERS
TWO
IDMAs
32-BIT RISC
INTERNAL TIMER
SPI
SMC2
SMC1
SCC4
SCC3
SCC2
PERIPHERAL BUS
SCC1
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• CPM Interrupt Controller
FOURTEEN
SDMAs
SERIAL INTERFACE
TIME SLOT ASSIGNER
NOTE: The term "CP" refers to the nonshaded portion of the CPM.
Figure 7-1. CPM Block Diagram
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RISC Controller
7.1 RISC CONTROLLER
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The RISC controller is the 32-bit central controller of the communication processor module
(CPM). Since its execution occurs on a separate bus that is hidden from the user, it does
not impact CPU32+ core performance. The RISC controller works with the serial channels
and parallel interface port (PIP) to implement the user-chosen protocols and to manage the
SDMA channels that transfer data between the SCCs and memory. The RISC controller
contains an internal timer that can be used to implement up to 16 additional timers for the
user application software. These features are collectively known as the communication processor (CP), which is a subset of the overall CPM. Additionally, the RISC controller can
manage the operation of the IDMA channels, if desired. The 32-bit RISC handles the lower
layer tasks and DMA control activities, leaving the 32-bit CPU32+ core (or other external
processor) free to handle higher layer activities. Thus, the QUICC can be thought of as a
dual 32-bit processor system.
The RISC controller communicates with the host (CPU32+ core or other external processor)
in several ways. First, many parameters are exchanged through the dual-port RAM. In the
case of simultaneous accesses (at least one of which is a write operation), the RISC controller may be delayed by one clock in its access to the dual-port RAM. The host is never
delayed. Second, the RISC controller can execute special commands issued by the host.
These commands are only required to be issued in special situations. Third, the RISC controller can generate interrupts through the CPM interrupt controller. Fourth, status/event registers, which show events that have occurred within the RISC, may be read at any time by
the CPU32+ or an external processor.
The RISC controller has the ability to control a set of up to 16 timers. These timers are separate and distinct from the four general-purpose timers and baud rate generators in the
CPM. The 16 timers are ideally used in protocols that do not require extreme precision, but
in which it is desirable to off-load the host CPU from having to scan the timer tables that are
created in software. These timers are clocked from an internal timer used only by the RISC
controller.
The RISC controller uses the peripheral bus to communicate with all of its peripherals. Each
SCC has a separate receive and transmit FIFO. The SCC1 FIFOs are 32-bytes each; the
other SCC FIFOs are 16-bytes each. The SMC and SPI FIFO sizes are double-buffered.
The PIP is a single register interface.
The following priority scheme determines the processing priority of the RISC controller. It is
as follows:
1. Reset in CP Command Register or System Reset
2. DMA Bus Error
3. Commands Issued to the CP Command Register
4. CC1 Rx
5. SCC1 Tx
6. SCC2 Rx
7. SCC2 Tx
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RISC Controller
8. CC3 Rx
9. SCC3 Tx
10. SCC4 Rx
11. SCC4 Tx
12. SMC1 Rx
13. SMC1 Tx
14. SMC2 Rx
15. SMC2 Tx
16. SPI Rx
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17. SPI Tx
18. PIP
19. RISC Timer Tables
The RISC controller has an option to execute microcode from a portion of user RAM, located
in the on-chip dual-port RAM. In this mode, either 512 bytes or 1024 bytes of the user RAM
cannot be accessed by the host or another bus master and are used exclusively by the
RISC. In this mode, the RISC controller can fetch instructions from both the dual-port RAM
and its private ROM. This mode allows Motorola to add new protocols or enhancements to
the QUICC in the form of Motorola-supplied RAM microcodes. The binary microcode is
obtained from Motorola and then loaded by the user into the dual-port RAM.
The RISC controller contains one configuration register described in the following paragraph.
7.1.1 RISC Controller Configuration Register (RCCR)
The 16-bit, memory-mapped, read-write RCCR is used to configure the RISC processor and
controls the RISC internal timer. This register is initialized to zero at reset. Bits 0-7 should
not be modified unless the user is downloading a Motorola-supplied RAM microcode package..
15
TIME
14
—
13
12
11
10
TIMEP
9
8
7
6
5
4
3
RESERVED
2
1
0
TIME—Timer Enable
This bit enables the RISC controller internal timer. The timer will generate a tick to the
RISC based on the value programmed into the TIMEP bit. TIME may be modified at any
time to start or stop the scanning of the RISC timer tables.
Bit 14—Reserved
TIMEP—Timer Period
This field controls the RISC controller timer tick. The RISC timer tables are scanned on
each timer tick. The input to this timer tick generator is the general system clock divided
by 1024. The formula is (TIMEP + 1) × 1024 = (general system clock period). Thus, a val7-4
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Command Set
ue of 0 stored in these bits gives a timer tick of 1 × (1024) = 1024 general system clocks.
A value of 63 (decimal) stored in these bits gives a timer tick of 64 × (1024) = 65536 general system clocks.
Bits 7-0—Reserved - set to zero.
7.1.2 RISC Microcode Revision Number
The RISC controller writes a revision number stored in its ROM to a dual-port RAM location
called REV_num. REV_num is located in the miscellaneous parameter RAM. The other
locations are reserved for future use. The microcode rivision number only reflect the revision
of the micro code. It dose not always refrect the MASK number.
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Address
Name
Width
Description
Misc Base + 00
REV_num
Word
Microcode Revision Number
Misc Base + 02
RES
Word
Reserved
Misc Base + 04
RES
Long
Reserved
Misc Base + 08
RES
Long
Reserved
7.2 COMMAND SET
The host processor (CPU32+ or other external processor) issues commands to the RISC by
writing to the command register (CR). The CR only needs to be accessed on rare occasions.
For instance, to terminate the transmission of a frame by an SCC without waiting until the
end of the frame, a STOP TX command can be issued to an SCC through the command
register. The commands are described in general terms in the following paragraphs; they
are described in specific terms when the protocol or feature is described in detail.
The host should set the FLG bit in the CR when it issues commands. The CP clears FLG
after completing the command to indicate to the host that it is ready for the next command.
Subsequent commands to the CR may be given only after FLG is cleared. The software
reset command (issued by setting the RST bit) may be given regardless of the state of FLG,
but the host should still set FLG when setting RST.
The CR, a 16-bit, memory-mapped, read-write register, is cleared by reset.
15
RST
14
13
—
12
11
10
9
OPCODE
8
7
6
5
4
CH NUM
3
2
—
1
0
FLG
RST—Software Reset Command
This bit is set by the host and cleared by the CP. On execution of this command, the RST
bit and the FLG bit are cleared within two general system clocks. The RISC reset routine
is approximately 60 clocks long, but the user can begin initialization of the CP immediately
after this command is given. This command is useful when the host wants to reset the registers and parameters for all the channels (SCCs, SMCs, SPI, and PIP) as well as the
RISC processor and RISC timer tables. This command does not affect the serial interface
(SI) or the parallel I/O registers.
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Command Set
Bits 14–12, 3–1—Reserved
OPCODE—Operation Code
The opcodes are listed in Table 7-1.
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Table 7-1. Opcodes
Opcode
SCC
SMC (UART/Trans)
SMC (GCI)
SPI
0000
INIT RX & TX
PARAMS
INIT RX & TX PARAMS
INIT RX & TX
PARAMS
INIT RX & TX
PARAMS
0001
INIT RX
PARAMS
INIT RX PARAMS
INIT RX
PARAMS
0010
INIT TX PARAMS
INIT TX PARAMS
INIT TX PARAMS
0011
ENTER HUNT
MODE
ENTER HUNT MODE
0100
STOP TX1
STOP TX
0101
GR STOP TX2
0110
RESTART TX
RESTART TX
0111
CLOSE RX BD
CLOSE RX BD
1000
SET GROUP
ADDR
Timer
INIT IDMA
CLOSE RX BD
SET TIMER
1001
1010
IDMA
GCI TIMEOUT
RESET BCS
GCI ABORT REQ
1011
1100
U
U
U
U
U
U
1101
U
U
U
U
U
U
1110
U
U
U
U
U
U
1111
U
U
U
U
U
U
NOTES:
1.STOP TX = MC68302 original STOP TRANSMIT command.
2.GR STOP TX = GRACEFUL STOP TRANSMIT command.
INIT TX and RX PARAMETERS. This command initializes the transmit and receive parameters in the parameter RAM to the values that they had after the last reset of the CP.
This command is especially useful when switching protocols on a given serial channel.
INIT RX PARAMETERS. This command initializes the receive parameters of the serial
channel.
INIT TX PARAMETERS. This command initializes the transmit parameters of the serial
channel.
ENTER HUNT MODE. This command causes the receiver to stop receiving and begin
looking for a new frame. The exact operation of this command may vary depending on the
protocol used.
STOP TX. This command aborts the transmission from this channel as soon as the transmit FIFO has been emptied. It should be used in cases where transmission needs to be
stopped as quickly as possible. Transmission will proceed when the RESTART command
is issued.
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Command Set
GRACEFUL STOP TX. This command stops the transmission from this channel as soon
as the current frame has been fully transmitted from the transmit FIFO. Transmission will
proceed once the RESTART command is issued and the R-bit is set in the next transmit
buffer descriptor.
RESTART TX. When the STOP TX command has been issued, this command can be
used to restart the transmission at the current buffer descriptor.
CLOSE RX BD. This command causes the receiver to simply close the current receive
buffer descriptor, making the receive buffer immediately available for manipulation by the
user. Reception continues normally using the next available buffer descriptor. This command may be used to access the data buffer without waiting until the data buffer is completely filled by the SCCµSET TIMER. This command activates, deactivates, or
reconfigures one of the 16 timers in the RISC timer table.
SET GROUP ADDRESS. This command sets a bit in the hash table for the Ethernet logical group address recognition function.
GCI ABORT REQUEST. The GCI receiver sends an abort request on the E-bit.
GCI TIMEOUT. The GCI performs the timeout function.
RESET BCS. This command is used in BISYNC mode to reset the block check sequence
calculation.
Undefined (U). Reserved for use by Motorola-supplied RAM microcodes.
CH NUM—Channel Number
These bits are set by the host to define the specific sub-block on which the command is
to operate. Some sub-blocks share channel number encodings if their commands are mutually exclusive.
0000 SCC1
0001
0010
0011
0100 SCC2
0101 SPI/RISC Timers
0110
0111
1000 SCC3
1001 SMC1/IDMA1
1010
1011
1100 SCC4
1101 SMC2/IDMA2
1110
1111
FLG—Command Semaphore Flag
The bit is set by the host and cleared by the CP.
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0 = The CP is ready to receive a new command.
1 = The CR contains a command that the CP is currently processing. The CP clears
this bit at the end of the command execution or after reset.
7.2.1 Command Register Examples
To perform a complete reset of the CP, the value $8001 should be written to the CR. Following this command, the CR will return the value $0000 in two clocks.
To execute an ENTER HUNT MODE command to SCC3, the value $0381 should be written
to the CR. While the command is executing, the CR will return the value $0381. When the
command has been completely executed, the CR will return the value $0380.
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7.2.2 Command Execution Latency
The worst-case command execution latency is 120 clocks. The typical command execution
latency is about 40 clocks.
7.3 DUAL-PORT RAM
The CPM has 2560 bytes of static RAM configured as dual-port memory. The dual-port RAM
memory map is shown in Figure 7-2, and a block diagram is shown in Figure 7-3.
0
TOTAL 2560 BYTES
BDs/DATA/UCODE—512 BYTES
MBAR POINTS
TO THE BASE
0.5K
BDs/DATA/UCODE—512 BYTES
1K
BDs/DATA—512 BYTES
1.5K
BDs/DATA/UCODE—256 BYTES
2K
2.5K
3K
PARAMETER RAM—768 BYTES
3.5K
BDs/DATA IN ANY UNUSED SPACE
4K
Figure 7-2. Dual-Port RAM Memory Map
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Dual-Port RAM
SYSTEM
RAM
1792 BYTES
512
BYTES
ADDRESS
SELECTOR
CP MICROCODE
ADDRESS
512
BYTES
CP MICROCODE DATA
256
BYTES
PERIPHERAL
DATA BUS
INTERNAL
PERIPHERAL
ADDRESS
IMB
ADDRESS
BUS
ADDRESS
SELECTOR
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512
BYTES
PARMETER
RAM
768 BYTES
IMB
DATA BUS
Figure 7-3. Dual-Port RAM Block Diagram
The dual-port RAM can be accessed by the RISC or one of four bus masters: CPU32+ core,
IDMAs, SDMAs, or external bus master. When the dual-port RAM is accessed by an external bus master, CPU32+ core, IDMA, or SDMA channel, it is accessed in three clocks. When
the dual-port RAM is accessed by the RISC, it is accessed in one clock. In the case of simultaneous access (with at least one write operation), the RISC is delayed by one clock.
When the dual-port RAM is accessed by the CPU32+ core, IDMAs, SDMAs, or external bus
master, the data and address are taken from the IMB. The data is then presented on the IMB
data bus. The RISC has access to the entire dual-port RAM for data fetches and portions of
the system RAM for microcode instruction fetches.
The dual-port RAM is used for five possible tasks; any two tasks can occur simultaneously.
The first use is to store parameters associated with the SCCs, SMCs, SPI, and IDMAs in the
768-byte parameter RAM. The second use is to store the buffer descriptors that describe
where data is to be received and transmitted from. The third use is to store data from the
serial channels. This usage is optional since data may also be stored externally in the system memory. The fourth use is to store RAM microcode for the RISC processor. This feature
allows additional protocols to be added by Motorola in the future. The fifth use is for additional scratchpad RAM space for the user program.
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Only the parameters in the parameter RAM and the microcode RAM option require fixed
addresses to be used. The buffer descriptors, buffer data, and scratchpad RAM may be
located in the internal system RAM or in any unused parameter RAM (for instance, in the
available area when a serial channel or sub-block is not being used).
When a microcode from RAM is executed, certain portions of the system RAM are no longer
available. This includes either the first 512-byte block and the last 256-byte block for a small
RAM microcode, and the first two 512-byte blocks and the last 256-byte block for a large
RAM microcode. The third 512-byte block is always available as system RAM.
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7.3.1 Buffer Descriptors
The SCCs, SMCs, SPI always use buffer descriptors for controlling data buffers. The buffer
descriptor format of the SCCs, SMCs, and SPI is identical. The buffer descriptor format for
these channels is shown in the following illustration.
150
OFFSET + 0
STATUS AND CONTROL
OFFSET + 2
DATA LENGTH
OFFSET + 4
HIGH-ORDER DATA BUFFER POINTER
OFFSET + 6
LOW-ORDER DATA BUFFER POINTER
If the IDMA is used in the buffer chaining or auto buffer mode, the IDMA channel also uses
buffer descriptors. The buffer descriptors for the IDMA are described in 7.6.1 IDMA Key Features;.
7.3.2 Parameter RAM
The CP maintains a section of dual-port RAM called the parameter RAM. This RAM contains
many parameters for the operation of the SCCs, SMCs, SPI, and the IDMA channels. An
overview of the parameter RAM structure is shown in Figure 7-4. The exact definition of the
parameter RAM is contained in each subsection describing a device that uses a parameter
RAM.
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3k
RISC Timer Tables
TOTAL 768 BYTES
SCC1/MISC
192 BYTES
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SCC2/SPI
192 BYTES
256 BYTES/PAGE
SCC3/SMC1/IDMA1
192 BYTES
SCC4/SMC2/IDMA2
192 BYTES
4k
Figure 7-4. Parameter RAM Overview
7.4 RISC TIMER TABLES
The RISC controller has the ability to control up to 16 timers. These timers are separate from
the four general-purpose timers and baud rate generators in the CPM. The 16 timers are
ideally used in protocols that do not require extreme precision, but in which it is desirable to
off-load the host CPU from having to scan the timer tables that are created in software.
These timers are clocked from an internal timer used only by the RISC.
The features of the RISC timer tables are as follows:
• Up to 16 Timers Supported
• Two Timer Modes: One-Shot and Restart
• Maskable Interrupt on Timer Expiration
• Programmable Timer Resolution As Low As 41 µs at 25 MHz
• Maximum Timeout Period of 172 Sec at 25 MHz
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• Continuously Updated Reference Counter
All operations on the RISC timer tables are based on a fundamental "tick" of the RISC internal timer, which is programmed in the RISC RCCR. The tick is a multiple of 1024 general
system clocks. (See 7.1 RISC Controller for more details.)
The RISC timer tables have the lowest priority of all RISC operations. Therefore, if the RISC
is so busy with other tasks that it does not have time to service the timer during a tick interval,
one or more of the timers may not be updated during a tick.
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This behavior can actually be used to estimate the worst-case loading of the RISC processor. (See Table 7-2 for more details.)
The RISC timer tables are configured in the RCCR, the RISC timer table parameter RAM,
and by the SET TIMER command issued to the CP command register, the RISC timer event
register, and the RISC timer mask register.
7.4.1 RISC Timer Table Parameter RAM
Two areas of internal RAM are used for the RISC timer tables: the RISC timer table parameter RAM and RISC timer table entries (see Figure 7-5). The RISC timer table parameter
RAM area begins at the RISC timer base address (see Table 7-2). This area is used for the
general timer parameters.
INTERNAL DUAL-PORT RAM
CAN BE ANYWHERE IN
THE DUAL-PORT RAM
16 RISC
TIMER
TABLE
ENTRIES
(UP TO 64 BYTES)
POINTER
TM_BASE
ALWAYS THE SAME LOCATION
IN PARAMETER RAM
RISC
TIMER
TABLE
PARAMETER
RAM
(14 BYTES)
Figure 7-5. RISC Timer Table RAM Usage
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RISC Timer Tables
Table 7-2. RISC Timer Table Parameter RAM
Address
Name
Width
Description
Timer Base + 00
TM_BASE
Word
RISC Timer Table Base Address
Timer Base + 02
TM_ptr
Word
RISC Timer Table Pointer
Timer Base + 04
R_TMR
Word
RISC Timer Mode Register
Timer Base + 06
R_TMV
Word
RISC Timer Valid Register
Timer Base + 08
TM_cmd
Long
RISC Timer Command Register
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Timer Base + 0C
TM_cnt
Long
RISC Timer Internal Count
NOTE: Boldfaced items are initialized by the user.
TM_BASE. The actual RISC timers are located by the user as a small block of memory in
the dual-port RAM. TM_BASE is the offset from the beginning of dual-port RAM where that
block resides. The user should allocate 4 bytes at TM_BASE for each timer used (64 bytes
at TM_BASE if all 16 timers are used). If less than 16 timers are used, the timers should
always be allocated in ascending order (RISC timer 0, RISC timer 1, etc.) to save space. For
example, if the user only needs two timers, then 8 bytes are required at location TM_BASE
as long as the user only enables RISC timer 0 and RISC timer 1.
NOTE
TM_BASE should always be aligned to a long-word boundary
(i.e., evenly divisible by 4).
TM_ptr. This value is used exclusively by the RISC to point to the next timer to be accessed
in the timer table. It should not be modified by the user.
R_TMR. This value is used exclusively by the RISC to store the mode of the timer: one-shot
(bit is zero) or restart (bit is one). R_TMR should not be modified by the user. The SET
TIMER command should be used instead.
R_TMV. This value is used exclusively by the RISC to store whether a timer is currently
enabled. A bit is a one if the corresponding timer is enabled. R_TMV should not be modified
by the user. The SET TIMER command should be used instead.
TM_cmd. This value is used as a parameter location when the SET TIMER command is
issued. The user should write this location prior to issuing the SET TIMER command. This
parameter is defined as follows:
31
30
V
R
29
20
—
19
16
15
TIMER NUMBER
0
TIMER PERIOD (16 BITS)
V—Valid
This bit should be set to enable the timer and cleared to disable the timer.
R—Restart
This bit should be set for an automatic restart or cleared for a one-shot operation of the
timer.
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Bits 29–20—Reserved
These bits should be written with zeros.
Bits 19–16—Timer Number
The timer number is a value from 0 to 15 that signifies the timer is configured.
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Bits 15–0—Timer Period
The timer period is the 16-bit timeout value of the timer. The maximum value is 65536,
which is programmed by writing $0000 to the timer period.
TM_cnt. This value is simply a tick counter that is updated by the RISC after each tick. It is
updated if the RISC internal timer is enabled, regardless of whether any of the 16 timers are
enabled. It can be used to track the number of ticks that the RISC has received and
responded to. This value is updated only after the RISC scans the timer table.
7.4.2 RISC Timer Table Entries
The actual 16 timers themselves are located in the block of memory following the TM_BASE
location. Each timer occupies 4 bytes. The first word forms the initial value of the timer written during the execution of the SET TIMER command, and the next word is the current value
of the timer, which is decremented until it reaches zero. These locations should not be modified by the user; they are documented only as a debugging aid for user code.
7.4.3 RISC Timer Event Register (RTER)
This 16-bit register is used to report events recognized by the 16 timers and to generate
interrupts. Bit 0 corresponds to timer 0, and bit 15 corresponds to timer 15. Note that an
interrupt will only be generated if the RISC timer table bit is set in the CPM interrupt mask
register. RTER may be read at any time. A bit is cleared by writing a one (writing a zero does
not affect a bit’s value), and more than one bit may be cleared at a time. This register is
cleared at reset.
7.4.4 RISC Timer Mask Register (RTMR)
This 16-bit register is used to enable interrupts that may be generated in the RISC timer
event register. If a bit is set, it enables the corresponding interrupt in the RTER. If a bit is
cleared, it masks the corresponding interrupt in the RTER. Note that an interrupt will only be
generated if the RISC timer table bit is set in the CPM interrupt mask register. This readwrite register is cleared at reset.
7.4.5 SET TIMER Command
This command is used to enable, disable, and configure the 16 timers in the RISC timer table. The SET TIMER command is issued to the CR. This means the value $0851 should be
written to CR. However, before writing this value, the TM_cmd value should be set up by the user. See 7.4.1
RISC Timer Table Parameter RAM for details.
7.4.6 RISC Timer Initialization Sequence
The following sequence initializes the RISC timers:
1. Configure the RCCR to determine the desired tick interval that will be used for the en-
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RISC Timer Tables
tire timer table. The TIME bit would normally be turned on at this time; however, it can
be turned on later if it is required that all RISC timers be synchronized.
2. Determine the maximum number of timers to be located in the timer table and configure TM_BASE in the RISC timer table parameter RAM to point to a location in the dual
port RAM with 4 × N bytes available, where N is the number of timers. If N is less than
16, use timer 0 through timer N–1 (for space efficiency).
3. Clear the TM_cnt in the RISC timer table parameter RAM to show how many ticks
have elapsed since the RISC internal timer was enabled. This step is optional.
4. Clear the RISC timer event register if it is not already cleared. (Ones are written to
clear this register.)
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5. Configure the RTMR to enable those timers that should generate interrupts. (Ones enable interrupts.)
6. Set the RISC timer table bit in the CPM interrupt mask register to generate interrupts
to the system. (The CPM interrupt controller may require other initialization not mentioned here.)
7. Configure the TM_cmd field of the RISC timer table parameter RAM. At this point, determine whether a timer is to be enabled or disabled, one-shot or restart, and what its
timeout period should be. If the timer is being disabled, the parameters (other than the
timer number) are ignored.
8. Issue the SET TIMER command by writing $0861 to the CR.
9. Repeat the preceding two steps for each timer to be enabled or disabled.
7.4.7 RISC Timer Initialization Example
The following sequence initializes RISC timer 0 to generate an interrupt approximately every
second using a 25-MHz general system clock:
1. Write the TIMEP bits of the RCCR with 111111 to generate the slowest clock. This value will generate a tick every 65536 clocks, which is every 2.6 ms at 25 MHz.
2. Configure TM_BASE in the RISC timer table parameter RAM to point to a location in
the dual-port RAM with 4 bytes available. Assuming the beginning of dual-port RAM is
available, write $0000 to TM_BASE.
3. Write $0000 to TM_cnt in the RISC timer table parameter RAM to see how many ticks
have elapsed since the RISC internal timer was enabled. This step is optional.
4. Write $FFFF to the RTER to clear any previous events.
5. Write $0001 to the RTMR to enable RISC timer 0 to generate an interrupt.
6. Write $00020000 to the CPM interrupt mask register to allow the RISC timers to generate a system interrupt. Initialize the CPM interrupt configuration register.
7. Write $C0000EE6 to the TM_cmd field of the RISC timer table parameter RAM. This
enables RISC timer 0 to time out after 3814 (decimal) ticks of the timer. The timer will
automatically restart after it times out.
8. Write $0851 to the CR to issue the SET TIMER command.
9. Set the TIME bit in the RCCR to enable the RISC timer to begin operation.
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RISC Timer Tables
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7.4.8 RISC Timer Interrupt Handling
The following sequence describes what would normally occur within an interrupt handler for
the RISC timer tables:
1. Once an interrupt occurs, read the RISC timer event register to see which timer or timers have caused interrupts. The RISC timer event bits would normally be cleared at
this time.
2. Issue additional SET TIMER commands at this time or later, as desired. Nothing need
be done if the timer is being restarted automatically for a repetitive interrupt.
3. Clear the R-TT bit in the CPM interrupt status register.
Freescale Semiconductor, Inc...
4. Execute the RTE instruction.
7.4.9 RISC Timer Table Algorithm
The RISC scans the timer table once every tick. For each valid timer in the timer table, the
RISC decrements the count and checks for a timeout. If no timeout occurs, it moves to the
next timer. If a timeout occurs, the RISC sets the corresponding event bit in the RISC timer
event register. It checks to see if the timer is to be restarted. If so, it leaves the timer valid
bit set in the R_TMV location and resets the current count to the initial count; otherwise, it
clears the R_TMV bit. Once the timer table is scanned, the RISC updates the TM_cnt value
in the RISC timer table parameter RAM and ceases working on the timer tables until the next
tick.
If a SET TIMER command is issued, the RISC controller makes the appropriate modifications to the timer table and parameter RAM, but does not scan the timer table until the next
tick of the internal timer. It is important to use the SET TIMER command to properly synchronize the timer table alterations to the execution of the RISC.
7.4.10 RISC Timer Table Application: Track the RISC Loading
The RISC timers can be used to track the loading of the RISC controller. The following
sequence gives a method for using the 16 RISC timers to determine if the RISC controller
ever exceeds the 96% utilization level during any tick interval. Removing the timers then
adds a 4% margin to the RISC utilization level. The aggressive user can use this technique
to push the RISC performance to its limit in an application.
The user should use the standard initialization sequence, with the following differences:
1. Program the tick of the RISC timers to be 1024 x 16 = 16384.
2. Disable RISC timer interrupts, if desired.
3. Using the SET TIMER command, initialize all 16 RISC timers to have a timer period of
$0000, which equates to 65536.
4. Program one of the four general-purpose timers to increment once every tick. The general-purpose timer should be free-running and should have a timeout of 65536.
5. After hours of operation, compare the general-purpose timer to the current count of
RISC timer 15. If RISC timer 15 is more than two ticks different from the general-purpose timer, the RISC controller has, during some tick interval, exceeded the 96% uti-
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Timers
lization level.
NOTE
The general-purpose timers are up-counters, but the RISC timers are down-counters. The user should consider this fact when
comparing timer counts.
Freescale Semiconductor, Inc...
7.5 TIMERS
The CPM includes four identical, 16-bit, general-purpose timers or two 32-bit timers. Each
general-purpose timer consists of a timer mode register (TMR), a timer capture register
(TCR), a timer counter (TCN), a timer reference register (TRR), and a timer event register
(TER). The TMR contains the prescaler value programmed by the user. In addition, there is
one timer global configuration register (TGCR). The timer block diagram is shown in Figure
7-6.
TGCR
GLOBAL CONFIGURATION REGISTER
TER1
TMR1
EVENT REGISTER
GENERAL
SYSTEM
CLOCK
TIMER
CLOCK
GENERATOR
MODE REGISTER
PRESCALER
MODE BITS
DIVIDER
TGATE1
TGATE2
TIN1
TIN2
TIN3
CLOCK
TIN4
TCN1
TIMER COUNTER
TRR1
REFERENCE REGISTER
CAPTURE
DETECTION
TOUT1
TOUT2
TCR1
CAPTURE REGISTER
TOUT3
TOUT4
TIMER1
TIMER2
TIMER3
TIMER4
Figure 7-6. Timer Block Diagram
7.5.1 Timer Key Features
The four identical general-purpose timers have the following features:
• Maximum Period of 10.7 Sec (at 25 MHz)
• 40-ns Resolution (at 25 MHz)
• Programmable Sources for the Clock Input
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Timers
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• Input Capture Capability
• Output Compare with Programmable Mode for the Output Pin
• Two Timers Internally or Externally Cascadable To Form a 32-Bit Timer
• Free Run and Restart Modes
• Functionally Compatible with Timer 1 and Timer 2 on the MC68302
7.5.2 General-Purpose Timer Units
Freescale Semiconductor, Inc...
The clock input to the prescaler may be selected from three sources: the general system
clock, the general system clock divided by 16, or the corresponding TINx pin. Each option
is discussed in the following paragraphs.
The general system clock is generated in the clock synthesizer and defaults to the system
frequency (for instance, 25 MHz). However, the general system clock has the option to be
divided before it leaves the clock synthesizer. This mode, called slow go, is used to save
power. Whatever the resulting frequency of the general system clock, the user may choose
either that frequency or that frequency divided by 16 as the input to the prescaler of each
timer.
Alternatively, the user may choose the TINx pin to be the clock source. TINx is internally synchronized to the internal clock. If the user has chosen to internally cascade two 16-bit timers
to a 32-bit timer, then a timer may internally use the clock generated by the output of another
timer.
The clock input source is selected by the ICLK bits of the corresponding TMR. The prescaler
is programmed to divide the clock input by values from 1 to 256. The output of the prescaler
is used as an input to the 16-bit counter.
The best resolution of the timer is one clock cycle (40 ns at 25 MHz). The maximum period
(when the reference value is all ones) is 268,435,456 cycles (10.7 sec at 25 MHz). Both values assume that the general system clock is the full 25 MHz.
Each timer may be configured to count until a reference is reached and then either begin a
new time count immediately or continue to run. The FRR bit of the corresponding TMR
selects each mode. Upon reaching the reference value, the corresponding TER bit is set,
and an interrupt is issued if the ORI bit in the TMR is set.
Each timer may output a signal on the timer output pin (TOUT1, TOUT2, TOUT3, or TOUT4)
when the reference value is reached (selected by the OM bit of the corresponding TMR).
This signal can be an active-low pulse or a toggle of the current output. The output can also
be internally connected to the input of another timer, resulting in a 32-bit timer.
Each timer has a 16-bit TCR, which is used to latch the value of the counter when a defined
transition of TIN1, TIN2, TIN3, or TIN4 is sensed by the corresponding input capture edge
detector. The type of transition triggering the capture is selected by the CE bits in the corresponding TMR. Upon a capture or reference event, the corresponding TER bit is set, and a
maskable interrupt request is issued to the CPM interrupt controller.
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Timers
The timers may be gated/restarted by an external gate signal. There are two gate pins:
TGATE1 controls timer 1 and/or timer 2; TGATE2 controls timer 3 and/or timer 4.
Normal gate mode enables the count on a falling edge of the TGATEx pin and disables the
count on the rising edge of the TGATEx pin. Normal gate mode allows the timer to count
conditionally based on the state of the TGATEx pin.
Freescale Semiconductor, Inc...
Restart gate mode performs the same function as normal mode, except that it also resets
the counter on the falling edge of the TGATEx pin. The restart gate mode has applications
in pulse interval measurement and bus monitoring:
• Pulse Measurement—The restart gate mode can measure a low pulse on the TGATEx
pin. The rising edge of the TGATEx pin completes the measurement, and if TGATEx is
externally connected to TINx, causes the timer to capture the count value and generate
a rising-edge interrupt.
• Bus Monitoring—The restart gate mode can detect a signal that is abnormally stuck low.
The bus signal should be connected to the TGATEx pin. The timer count is reset on the
falling edge of the bus signal, and if the bus signal does not go high again within the
number of user-defined clocks, an interrupt can be generated.
The gate function is enabled in the TMR, and the gate operating mode is selected in the
TGCR.
NOTE:
TGATE is internally synchronized to the system clock. If TGATE
meets the asynchronous input setup time (spec #47A) then,
when working with the internal clock, the counter will begin
counting after 1 system clock.
7.5.2.1 CASCADED MODE. In this mode (see Figure 7-7) two 16-bit timers can be internally cascaded to form a 32-bit counter. Timer 1 may be internally cascaded to timer 2, and
timer 3 may be internally cascaded to timer 4. Since, the decision to cascade timers is made
independently, the user may select such options as two 16-bit timers and one 32-bit timer.
The TGCR is used to put the timers into cascaded mode.
TIMER1
TIMER2
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31–16
CAPTURE
TIMER3
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 15–0
TIMER4
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 31–16
CAPTURE
CLOCK
CLOCK
TRR, TCR, TCN CONNECTED TO DATA BUS
PINS 15–0
Figure 7-7. Timer Cascaded Mode Block Diagram
If the CAS bit is set in the TGCR, the two timers function as a one 32-bit timer with one 32bit TRR, one 32-bit TCR, and one 32-bit TCN. In this case, TMR1 and/or TMR3 are ignored,
and the modes are defined using TMR2 and/or TMR4. The capture will be controlled from
TIN2 or TIN4. Interrupts will be generated from TER2 or TER4.
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Timers
When working in the cascaded mode, the cascaded TRR, TCR, and TCN should always be
referenced with 32-bit bus cycles.
7.5.2.2 TIMER GLOBAL CONFIGURATION REGISTER (TGCR). The TGCR is a 16-bit,
memory-mapped, read/write register that contains configuration parameters used by all four
timers. It allows starting and stopping any number of timers simultaneously if one bus cycle
is used to access TGCR. The TGCR is cleared by reset.
Freescale Semiconductor, Inc...
15
CAS4
14
FRZ4
13
STP4
12
RST4
11
GM2
10
FRZ3
9
STP3
8
RST3
7
CAS2
6
FRZ2
5
STP2
4
RST2
3
GM1
2
FRZ1
1
STP1
0
RST1
CAS4—Cascade Timers
0 = Normal Operation.
1 = Timers 3 and 4 are cascaded to form a 32-bit timer.
CAS2—Cascade Timers
0 = Normal Operation.
1 = Timers 1 and 2 are cascaded to form a 32-bit timer.
FRZ—Freeze
0 = The corresponding timer ignores the FREEZE pin.
1 = Halt the corresponding timer if the FREEZE pin is asserted. (The FREEZE pin is
asserted in background debug mode when the CPU32+ is enabled.)
STP —Stop Timer
0 = Normal operation.
1 = Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock from the IMB interface, which allows the user to read and write timer
registers. The clocks to the timer remain stopped until the user clears this bit or a
hardware reset occurs.
RST—Reset Timer
0 = Reset the corresponding timer (a software reset is identical to an external reset).
1 = Enable the corresponding timer if the STP bit is cleared.
GM2—Gate Mode for Pin 2
This bit is only valid if the gate function is enabled in TMR3 or TMR4.
0 = Restart gate mode. The TGATE2 pin is used to enable/disable the count. The falling edge of TGATE2 enables and restarts the count, and the rising edge of
TGATE2 disables the count.
1 = Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2
does not restart the count value in TCN.
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Timers
GM1—Gate Mode for Pin 1
This bit is only valid if the gate function is enabled in TMR1 or TMR2.
0 = Restart gate mode. The TGATE1 pin is used to enable/disable count. A falling
TGATE1 pin enables and restarts the count, and a rising edge of TGATE1 disables
the count.
1 = Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1
does not restart the count value in TCN.
7.5.2.3 TIMER MODE REGISTER (TMR1, TMR2, TMR3, TMR4). TMR1–TMR4 are identical 16-bit, memory-mapped, read/write registers. These registers are cleared by reset.
Freescale Semiconductor, Inc...
NOTE
The TGCR should be initialized prior to the TMRs, or erratic behavior may occur. The only exception is the RST bit in the
TGCR, which may be modified at any time.
15
14
13
12
11
PS
10
9
8
7
6
CE
5
OM
4
ORI
3
FRR
2
1
ICLK
0
GE
PS—Prescaler Value
The prescaler is programmed to divide the clock input by values from 1 to 256. The value
00000000 divides the clock by 1; the value 11111111 divides the clock by 256.
CE—Capture Edge and Enable Interrupt
00 = Disable interrupt on capture event; capture function is disabled.
01 = Capture on rising TINx edge only and enable interrupt on capture event.
10 = Capture on falling TINx edge only and enable interrupt on capture event.
11 = Capture on any TINx edge and enable interrupt on capture event.
OM—Output Mode
0 = Active-low pulse on TOUTx for one timer input clock cycle as defined by the ICLK
bits. Thus, TOUTx may be low for one general system clock period, one general
system clock/16 period, or one TINx pin clock cycle period. TOUTx changes occur
on the rising edge of the system clock.
1 = Toggle the TOUTx pin. TOUTx changes occur on the rising edge of the system
clock.
ORI—Output Reference Interrupt Enable
0 = Disable interrupt for reference reached (does not affect interrupt on capture function).
1 = Enable interrupt upon reaching the reference value.
FRR—Free Run/Restart
0 = Free run. The timer count continues to increment after the reference value is
reached.
1 = Restart. The timer count is reset immediately after the reference value is reached.
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Timers
ICLK—Input Clock Source for the Timer
00 = Internally cascaded input.
For TMR1, the timer 1 input is the output of timer 2.
For TMR3, the timer 3 input is the output of timer 4.
For TMR2 and TMR4, this selection means no input clock is provided to the timer.
01 = Internal general system clock.
10 = Internal general system clock divided by 16.
11 = Corresponding TIN pin: TIN1, TIN2, TIN3, or TIN4 (falling edge).
Freescale Semiconductor, Inc...
GE—Gate Enable
0 = The TGATE signal is ignored.
1 = The TGATE signal is used to control the timer.
7.5.2.4 TIMER REFERENCE REGISTERS (TRR1, TRR2, TRR3, TRR4). Each TRR is a
16-bit, memory-mapped, read-write register containing the reference value for the timeout.
TRR1–TRR4 are set to all ones by reset. The reference value is not reached until TCN increments to equal TRR.
7.5.2.5 TIMER CAPTURE REGISTERS (TCR1, TCR2, TCR3, TCR4). Each TCR is a 16bit register used to latch the value of the counter. TCR1–TCR4 appear as memory- mapped,
read-only registers to the user. TCR1–TCR4 are cleared by reset.
7.5.2.6 TIMER COUNTER (TCN1, TCN2, TCN3, TCN4). Each TCN is a 16-bit, memorymapped, read-write up-counter. A read cycle to TCN1–TCN4 yields the current value of the
timer, but does not affect the counting operation. A write cycle to TCN1–TCN4 sets the register to the written value, causing its corresponding prescaler to be reset.
NOTE
Write operation to this register while the timer is not running may
not update the register correctry. User should always use timer
refrence register to define desired count value.
7.5.2.7 TIMER EVENT REGISTERS (TER1, TER2, TER3, TER4). Each TER is a 16-bit
register used to report events recognized by any of the timers. On recognition of an output
reference event, the timer sets the REF bit in the TER, regardless of the corresponding ORI
in the TMR. The capture event will be set only if enabled by the CE bits in the TMR. TER1–
TER4, which appear to the user as memory-mapped registers, may be read at any time.
15
14
13
12
11
10
9
8
7
6
5
4
—
3
2
1
REF
0
CAP
A bit is reset by writing a one to that bit (writing a zero does not affect a bit’s value). More
than one bit may be reset at a time. Both bits must be reset before the timer will negate the
interrupt to the CPM interrupt controller. This register is cleared by reset.
Bits 15–2—Reserved
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REF—Output Reference Event
The counter has reached the TRR value. The ORI bit in the TMR is used to enable the
interrupt request caused by this event.
CAP—Capture Event
The counter value has been latched into the TCR. The CE bits in the TMR are used to
enable generation of this event.
7.5.3 Timer Examples
Freescale Semiconductor, Inc...
The following example lists the required initialization sequence of timer 2 to generate an interrupt every 10 µs, assuming a general system clock of 25 MHz. This means that an interrupt should be generated every 250 system clocks.
1. TGCR = $0000. Put timer 2 into the reset state. Do not use cascaded mode.
2. TMR2 = $001A. Enable the prescaler of the timer to divide-by-1 and the clock source
to general system clock. Enable an interrupt when the reference value is reached, and
restart the timer to repeatedly generate 10-µs interrupts.
3. TCN2 = $0000. Initialize the timer 2 count to zero. This is the default state of this register.
4. TRR2 = $00FA. Initialize the timer 2 reference value to 250 (decimal).
5. TER2 = $FFFF. Clear TER2 of any bits that might have been set.
6. CIMR = $00040000. Enable the timer 2 interrupt in the CPM interrupt controller. Initialize the CPM interrupt configuration register.
7. TGCR = $0010. Enable timer 2 to begin counting.
To implement the same function with a 32-bit timer using timer 1 and timer 2, the following
sequence may be used:
1. TGCR = $0080. Cascade timer 1 and timer 2. Put timer 1 and timer 2 in the reset state.
2. TMR2 = $001A. Enable the prescaler of timer 2 to divide-by-1 and the clock source to
general system clock. Enable an interrupt when the reference value is reached, and
restart the timer to repeatedly generate 10 µs interrupts.
3. TMR1 = $0000. Enable timer 1 to use the output of timer 2 as its input, which is the
default state of this register.
4. TCN1 = $0000, TCN2 = $0000. Initialize the combined timer 1 and timer 2 count to
zero which is the default state of this register. (This can be accomplished with one 32bit data move to TCN1.)
5. TRR1 = $0000, TRR2 = $00FA. Initialize the combined timer 1 and timer 2 reference
value to 250 (decimal). (This can be accomplished with one 32-bit data move to
TRR1.)
6. TER2 = $FFFF. Clear TER2 of any bits that might have been set.
7. CIMR = $00040000. Enable the timer 2 interrupt in the CPM interrupt controller. Initialize the CPM interrupt configuration register.
8. TGCR = $0091. Enable timer 1 and timer 2 to begin counting. Leave the timers in cas-
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IDMA Channels
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caded mode.
7.6 IDMA CHANNELS
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The QUICC includes a number of DMA channels, including 14 SDMA channels for the four
SCCs, two SMCs, and SPI and two general-purpose IDMA controllers. The SDMA channels
are discussed in 7.7 SDMA Channels. The IDMA channels are discussed in the following
paragraphs.
The two general-purpose IDMA controllers can operate in different modes of data transfer
as programmed by the user. The IDMA can transfer data between any combination of memory and I/O. In addition, data may be transferred in either byte, word, or long-word quantities,
and the source and destination addresses may be either odd or even. The most efficient
packing algorithms are used in the IDMA transfers. The single address mode gives the highest performance, allowing data to be transferred between memory and a peripheral in a single bus cycle. The chip-select and wait-state generation logic on the QUICC may be used
with the IDMA.
The IDMA supports three buffer handling modes: single buffer, auto buffer, and buffer chaining. Single buffer mode is that of the traditional DMA controller. The auto buffer mode allows
blocks of data to be repeatedly moved from one location to another without user intervention. The buffer chaining mode allows a chain of blocks to be moved. The user specifies the
data movement using buffer descriptors that are similar to those used by an SCC. These
buffer descriptions reside in the dual-port RAM.
If the single buffer mode of the IDMA is used, programming the IDMA is very similar
(although not exactly software compatible) to that of the IDMA on the MC68302 or the DMA
controller on the MC68340. The auto buffer and buffer chaining modes, however, are not
available on those devices, and the single address mode is not available on the MC68302.
The maximum transfer rate of the IDMA is 50 Mbyte/sec. This assumes a 32-bit data transfer
from memory to peripheral using fast termination (2 clocks per bus cycle) timing and single
address mode: (4 Bytes × 25 MHz Clocks/sec)/(2 Clocks per Transfer) = 50 Mbyte/sec.
The maximum transfer rate of the IDMA in dual address mode is 25 Mbyte/sec. This
assumes a 32-bit source and destination, fast termination (2 clocks per bus cycle) timing,
and two bus cycles for each transfer: (4 Bytes × 25 MHz Clocks/sec)/(4 Clocks per Transfer)
= 25 Mbyte/sec.
The IDMA controller block diagram is shown in Figure 7-8.
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FUNCTION CODE REGISTER
FCR
CHANNEL CONFIGURATION
REGISTER
ICCR
IDMA Channels
THE RISC
CAN CLEAR THE
STR BIT
CHANNEL MODE REGISTER
CMR
Freescale Semiconductor, Inc...
CMAR
IMB
CHANNEL STATUS REGISTER
CSR
SOURCE ADDRESS
POINTER REGISTER
SAPR
DESTINATION ADDRESS
POINTER REGISTER
DAPR
BYTE COUNT REGISTER
DATA HOLDING REGISTER
BUS ARBITRATION
RISC CONTROLLER ACCESS
CHANNEL MASK REGISTER
BCR
DHR
DMA
CONTROL
MACHINE
IDMA REQUESTS
(DREQx PINS)
BUS CONTROL
Figure 7-8. IDMA Controller Block Diagram
7.6.1 IDMA Key Features;
The IDMA contains the following features:
• Two Independent, Fully Programmable DMA Channels
• Dual Address or Single Address Transfers with 32-Bit Address and 32-Bit Data Capability
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IDMA Channels
• Up to 50 Mbyte/sec Transfer Rates in Single Address Mode and 25 Mbyte/sec in Dual
Address Mode (assuming a 25-MHz system clock)
• 32-Bit Byte Transfer Counters
• 32-Bit Address Pointers That Can Increment or Remain Constant
• Operand Packing and Unpacking for Dual Address Transfers using the Most Efficient
Techniques
• Supports All Bus-Termination Modes
• Provides Full DMA Handshake for Cycle Steal and Burst Transfers
• Supports Fixed and Rotating Priority Between IDMA Channels
Freescale Semiconductor, Inc...
• Buffer Handling Modes: Single Buffer, Auto Buffer, and Buffer Chaining
7.6.2 IDMA Registers
Each IDMA channel has eight registers that define its specific operation. These registers
include a 32-bit source address pointer register (SAPR), a 32-bit destination address pointer
register (DAPR), an 8-bit function code register (FCR), a 32-bit byte count register (BCR), a
16-bit channel mode register (CMR), an 16-bit channel configuration register (ICCR), an 8bit channel status register (CSR), and an 8-bit channel mask register (CMAR). These registers provide the addresses, transfer count, and configuration information necessary to set
up a transfer. They also provide a means of controlling the IDMA channel and monitoring its
status. All registers can be modified by the CPU32+ core.
For the auto buffer and buffer chaining modes, the RISC controller uses a buffer descriptor
ring to automatically initialize the DAPR, SAPR, and BCR. The buffer descriptor ring resides
in dual-port RAM so that it may be accessed by the RISC controller without bus overhead.
The IDMA channel also includes a 32-bit data holding register (DHR), which is not accessible to the CPU32+ core and is used by the IDMA for temporary data storage.
7.6.2.1 IDMA CHANNEL CONFIGURATION REGISTER (ICCR). The 16-bit ICCR configures both IDMA channels. It is always readable and writable in the supervisor mode,
although writing is not recommended unless the module is disabled. It is initialized to $0000
at reset.
15
STP
14
13
FRZ
12
11
ARBP
10
9
ISM
8
7
—
6
5
IAID
4
3
2
1
0
—
STP—Stop Bit
0 = The system clock operates normally within the IDMA.
1 = Stop the system clock to the IDMA channels. This setting is used to conserve power when both IDMAs are unused.
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IDMA Channels
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FRZ1–FRZ0—Freeze
These bits determine the action to be taken when the FREEZE signal is asserted. The
IDMA negates its internal bus request and keeps it negated until FREEZE is negated or
the IDMA is reset.
00 = The IDMA channels ignore the FREEZE signal.
01 = Reserved.
10 = The IDMA channels freeze on the next bus cycle.
11 = Reserved.
ARBP—Arbitration Priority
These two bits select the arbitration priority between the two IDMA channels.
00 = IDMA channel 1 has priority over channel 2.
01 = IDMA channel 2 has priority over channel 1.
10 = Rotating priority.
11 = Reserved.
ISM—Interrupt Service Mask
These bits contain the interrupt service mask. When the interrupt service level on the IMB
is greater than the interrupt service mask, the IDMA vacates the bus and negates its bus
request to the IMB until the interrupt level service is less than or equal to the interrupt service mask.
NOTE
The user should program ISM to 7 for typical user applications.
This gives the IDMA priority over all interrupt handlers. These
bits MUST be set to 7 if the QUICC is in slave mode.
Bits 7, 3–0—Reserved
IAID—IDMA Arbitration ID
These bits establish bus arbitration priority level among sub-blocks that have the capability of becoming bus master. In the QUICC, the IDMAs, the SDMAs, and the SIM60 DRAM
refresh controller can become bus masters. An arbitration ID uses a number (0–7) to decide the priority of multiple bus masters that are requesting the IMB. A 0 is the lowest priority and a 7 is the highest priority.
The value programmed into the IAID bits is the arbitration ID of the highest priority IDMA
channel. The arbitration ID of the lowest priority IDMA channel is IAID minus 2. The ARBP
bits determine which IDMA channel has the higher priority. If round-robin priority is selected, then the IDMA channels alternate between the two IAID values.
Example: If ARBP = 00, selecting IDMA channel 1 to always have the highest priority, the
IAID values are:
IDMA channel 1 arbitration ID = IAID
IDMA channel 2 arbitration ID = IAID – 2
NOTES
The user should program IAID to 2 in typical user applications.
IAID should not be programmed to a value less than 2. This val-
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IDMA Channels
ue should be less than the SDMA arbitration ID so that the
SDMA channels have priority over the IDMA channels. User
must program this field to 7 when the QUICC is configured in
slave mode.
7.6.2.2 CHANNEL MODE REGISTER (CMR). Each IDMA channel contains a 16-bit CMR
that is reset to $0000. It is used to configure most of the IDMA options.
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15
ECO
14
SRM
13
S/D
12
RCI
11
10
REQG
9
SAPI
8
DAPI
7
6
SSIZE
5
4
DSIZE
3
2
BT
1
RST
0
STR
ECO — External Control Option
Dual Address Mode: this bit defines which device is connected to the control signals.
0 = The control signals (DREQx, DACKx, and DONEx) are associated with the destination (write) portion of the transfer.
1 = The control signals (DREQx, DACKx, and DONEx) are associated with the source
(read) portion of the transfer.
Single Address Mode: this bit defines the direction of the transfer.
0 = The device writes to memory, and the control signals (DREQx, DACKx, and DONEx) are used by the device to provide data during the destination (write) portion of
the transfer.
1 = The device reads from memory, and the control signals (DREQx, DACKx, and
DONEx) are used by the device to write data during the source (read) portion of
the transfer.
NOTE
If REQG is programmed to be internal (REQG = 0X), DREQx is
ignored.
SRM — Synchronous Request Mode
This bit controls how external devices may use the DREQx pin for IDMA service. This bit
is only relevant for applications that use external request mode or use the external DONEx
pin to terminate the IDMA operation.
0 = Asynchronous request mode is selected. The DREQx and DONEx input signals
are internally synchronized to the IDMA clock before they are used by the IDMA.
1 = Synchronous request mode is selected. The DREQx and DONEx input signals are
used by the IDMA without first being internally synchronized. This results in faster
operation, but should only be used if setup and hold times can be met.
S/D — Single/Dual Address Transfer
0 = The IDMA channel runs standard dual address transfers. Each transfer requires at
least two bus cycles. Data packing is performed using the DHR.
1 = The IDMA channel runs single address transfers from a peripheral to memory or
from memory to a peripheral. The transfer requires one bus cycle. The DHR is not
used for these transfers because the data is transferred directly into the destination
location.
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RCI — RISC Controls IDMA
0 = Single Buffer Mode. The user programs all IDMA registers for each buffer transfer.
1 = Auto buffer or buffer chaining mode. The RISC reconfigures the IDMA channel at
the end of each buffer transfer according to the buffer descriptor ring. The choice
between auto buffer and buffer chaining is made in the buffer descriptor itself.
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REQG — Request Generation
The REQG bits define what generates the requests for IDMA activity over the bus.
00 = Internal request at limited rate (limited burst bandwidth) set by BT bits
01 = Internal request at maximum rate (one burst)
10 = External request burst transfer mode (DREQx is level sensitive)
11 = External request cycle steal (DREQx is edge sensitive)
SAPI — SAPR Increment
0 = SAPR is not incremented after each transfer.
1 = SAPR is incremented by one, two, or four after each transfer, according to the
SSIZE bits. (SAPR may be incremented by an amount less than the SSIZE value
at the beginning or end of a block transfer, depending on the source starting address or byte count.)
DAPI — DAPR Increment
0 = DAPR is not incremented after each transfer.
1 = DAPR is incremented by one, two, or four after each transfer, according to the
DSIZE bits. (DAPR may be incremented by an amount less than the DSIZE value
at the beginning or end of a block transfer, depending on the destination starting
address or byte count.)
SSIZE — Source Size
The following decoding shows the definitions for the SSIZE bits. The user should set these
bits to the port size of the source (e.g., choose byte for an 8-bit peripheral).
00 = Long word
01 = Byte
10 = Word
11 = Reserved
DSIZE — Destination Size
The following decoding shows the definitions for the DSIZE bits. The user should set
these bits to the port size of the destination (e.g., choose byte for an 8-bit peripheral).
00 = Long word
01 = Byte
10 = Word
11 = Reserved
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BT — Burst Transfer
The BT bits control the maximum percentage of the IMB that the IDMA can use during
each 1024 clock cycle period after enabling the IDMA.
00 = IDMA gets up to 75% of the bus bandwidth.
01 = IDMA gets up to 50% of the bus bandwidth.
10 = IDMA gets up to 25% of the bus bandwidth.
11 = IDMA gets up to 12.5% of the bus bandwidth.
NOTE
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These percentages are valid only when using internal request
generation (REQG = 00).
RST—Software Reset
This bit resets the IDMA to the same state as an external reset. The IDMA clears RST
when the reset is complete.
0 = Normal operation.
1 = The channel aborts any external pending or running bus cycles and terminates
channel operation. Setting RST clears all bits in the CSR and CMR.
NOTE
The user should reset the IDMA channel prior to issuing the LPSTOP instruction.
STR—Start Operation
This bit starts the IDMA transfer if the REQG bits are programmed for an internal request.
If the REQG bits are programmed for an external request, this bit must be set before the
IDMA will recognize the first request on the DREQx input.
0 = Stop channel. Clearing this bit causes the IDMA to stop transferring data at the end
of the current bus cycle. The IDMA internal state is not altered.
1 = Start channel. Setting this bit allows the IDMA to start transferring data (or continue
if previously stopped).
NOTES
STR is cleared automatically when the transfer is complete.
If the STR bit is cleared by software during the middle of an
IDMA operand transfer, the IDMA will continue to hold the bit in
a one state until the operand transfer has completed. Thus, if the
user waits for the STR bit to be cleared after clearing it in software, he is assured that the values of SAPR, DAPR, and BCR
accurately show the current state of the IDMA transfer.
7.6.2.3 SOURCE ADDRESS POINTER REGISTER (SAPR). The SAPR contains 32
address bits of the source operand used by the IDMA to access memory or memorymapped peripheral controller registers. During the IDMA read cycle, the address on the
master address bus is driven from this register. The SAPR may be programmed by the SAPI
bits to be incremented or remain constant after each operand transfer.
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The register is incremented using unsigned arithmetic and will roll over if an overflow occurs.
For example, if a register contains $FFFFFFFF and is incremented by one, it will roll over to
$00000000. This register can be incremented by one, two, or four, depending on the SSIZE
bits and the starting address in this register.
The SAPR may be initialized by the host processor or by the RISC controller via a buffer
descriptor's ring structure when the RCI bit is set for special buffer handling modes.
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7.6.2.4 DESTINATION ADDRESS POINTER REGISTER (DAPR). The DAPR contains 32
address bits of the destination operand used by the IDMA to access memory or memorymapped peripheral controller registers. During the IDMA write cycle, the address on the
master address bus is driven from this register. The DAPR may be programmed by the DAPI
bits to be incremented or remain constant after each operand transfer.
The register is incremented using unsigned arithmetic and will roll over if overflow occurs.
For example, if a register contains $FFFFFFFF and is incremented by one, it will roll over to
$00000000. This register can be incremented by one, two, or four, depending on the DSIZE
bit and the starting address.
The DAPR may be initialized by the host processor or by the RISC controller via a buffer
descriptor's ring structure when the RCI bit is set for special buffer handling modes.
7.6.2.5 FUNCTION CODE REGISTER (FCR). Each IDMA channel has an 8-bit FCR that is
initialized to $00 at reset.
7
6
5
DFC3–DFC0
4
3
2
1
SFC3–SFC0
0
During an IDMA bus cycle, the SFC and DFC bits define the source and destination function
code values that are output by the IDMA and the appropriate address registers. The address
space on the function code lines may be used by an external memory management unit
(MMU) or other memory-protection device to translate the IDMA logical addresses to proper
physical addresses. The function code value programmed into the FCR is placed on pins
FC3–FC0 during a bus cycle to further qualify the address bus value.
NOTES
This register is typically set to 1xxx1xxxb to cause the IDMA to
operate in the DMA function code space, as opposed to a CPU
program or data space.
To keep interrupt acknowledge cycles unique in the system, do
not set this register to $77.
7.6.2.6 BYTE COUNT REGISTER (BCR). This 32-bit register specifies the number of bytes
of data to be transferred by the IDMA. The largest value that can be specified is 4 Gbytes
(BCR = $00000000). This register is decremented once for each byte transferred successfully, for a total of 1, 2, or 4 per operand transfer. BCR may be even or odd as desired. The
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IDMA channel will terminate the transfer of a block of memory if this register reaches zero
during operation.
7.6.2.7 CHANNEL STATUS REGISTER (CSR). The CSR is an 8-bit register used to report
events recognized by the IDMA controller. On recognition of an event, the IDMA sets its corresponding bit in the CSR, regardless of the corresponding bits in the CMAR. The CSR is a
memory-mapped register that may be read at any time. A bit is reset by writing a one and is
left unchanged by writing a zero. More than one bit may be reset at a time, and the register
is cleared by reset.
7
6
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—
5
AD
4
BRKP
3
OB
2
BES
1
BED
0
DONE
Bits 7–6—Reserved
AD—Auxiliary Done
This bit is valid in auto buffer and buffer chaining modes. It is set when the IDMA channel
has completed a buffer transfer for a buffer descriptor (BD) that has its I-bit set. For AD to
be set, the BCR must have been decremented to zero with no errors occurring during any
IDMA transfer bus cycle. The IDMA will then move to the next BD and continue to transfer
data.
BRKP—Breakpoint
This bit indicates that the breakpoint signal was asserted during an IDMA transfer. This
bit is cleared by writing a one or by reset. Writing a zero has no effect on BRKP.
OB—Out of Buffers
This bit is valid only when the RISC controls the IDMA (RCI bit in the CMR is set). It is set
when working with the RISC controller and there are no more valid buffers out of which to
transfer data.
BES—Bus Error Source
This bit indicates that the IDMA channel terminated with an error during the read cycle.
The channel terminates the IDMA operation without setting DONE. BES is cleared by writing a one or by setting RST in the CMR. Writing a zero has no effect on BES.
BED—Bus Error Destination
This bit indicates that the IDMA channel terminated with an error during the write cycle.
The channel terminates the IDMA operation without setting DONE. BED is cleared by writing a one or by setting RST in the CMR. Writing a zero has no effect on BED.
DONE—Normal Channel Transfer Done
This bit indicates that the IDMA channel has terminated normally. Normal channel termination is defined as follows:
1. In single buffer mode, the BCR has decremented to zero, and no errors have
occurred during any IDMA transfer bus cycle.
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IDMA Channels
2. In buffer chaining or auto buffer modes, the BCR has decremented to zero, the L-bit
in the BD has been set, and no errors have occurred during any IDMA transfer bus
cycle.
3. An external peripheral has asserted DONEx during an access by the IDMA to that
peripheral and no errors have occurred during any IDMA transfer bus cycle.
DONE will not be set if the channel terminates due to an error. DONE is cleared by writing
a one or by setting RST in the CMR. Writing a zero has no effect on DONE.
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7.6.2.8 CHANNEL MASK REGISTER (CMAR). The CMAR is an 8-bit, memory-mapped,
read-write register that has the same bit format as the CSR. If a bit in the CMAR is a one,
the corresponding interrupt in the CSR will be enabled. If the bit is a zero, the corresponding
interrupt in the CSR will be masked. CMAR is cleared at reset.
7.6.2.9 DATA HOLDING REGISTER (DHR). This 7-byte register serves as a buffer register
for the data being transferred during dual address IDMA cycles. No address for DHR is given
since this register cannot be addressed by the programmer. The DHR allows the data to be
packed and unpacked by the IDMA during the transfer. For example, if the source operand
size is byte and the destination operand size is word, then two-byte read cycles occur, followed by a one-word write cycle. The two bytes of data are buffered in the DHR until the
word write cycle occurs. The DHR allows for packing and unpacking of operands for all possible combinations: bytes to words, bytes to long words, words to long words, words to
bytes, long words to bytes, and long words to words.
7.6.3 Interface Signals
The IDMA has three dedicated control signals per channel: DMA request (DREQx), DMA
acknowledge (DACKx), and end of IDMA transfer (DONEx). The peripheral used with these
signals may be either a source or a destination of the IDMA transfers.
NOTE
DREQ must be level sensitive if IDMA uses buffer chaining
mode.
7.6.3.1 DREQ AND DACK. These are the handshake signals between the peripheral
requiring service and the QUICC. When the peripheral requires IDMA service, it asserts
DREQx, and the QUICC begins the IDMA process. When the IDMA service is in progress,
DACKx is asserted during accesses to the device. DREQx is ignored when the IDMA is programmed to one of the internal request modes.
7.6.3.2 DONEX. This bidirectional open-drain signal is used to indicate the last IDMA transfer. DONEx is always an output of the IDMA if the transfer count is exhausted.
DONEx may also operate as an input. If DONEx is externally asserted during internal
request modes, the IDMA transfer is terminated. With external request modes, DONEx may
be used as an input to the IDMA controller to indicate that the device being serviced requires
no more transfers and the transmission is to be terminated.
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7.6.4 IDMA Operation
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Every IDMA operation involves the following steps: IDMA channel initialization, data transfer, and block termination. In the initialization phase, the core (or external processor) loads
the registers with control information, initializes the IDMA BDs (if auto buffer or buffer chaining is used), and then starts the channel. In the transfer phase, the IDMA accepts requests
for operand transfers and provides addressing and bus control for the transfers. The termination phase occurs when the operation is complete and the IDMA interrupts the core if
interrupts are enabled.
To initialize a block transfer operation, the user must initialize the IDMA registers. For the
auto buffer and buffer chaining modes, the IDMA BDs must be initialized with information
describing the data block, device type, request generation method, and other special control
options. See 7.6.2 IDMA Registers and 7.6.4.2.3 IDMA Commands (INIT_IDMA) for further
details.
7.6.4.1 SINGLE BUFFER. The single buffer mode is used to transfer only one buffer of
data. When the buffer has been completely transferred (transfer count exhausted or DONEx
is asserted), the IDMA channel operation is terminated, STR is cleared, and a maskable
interrupt is generated by the DONE bit in the CSR.
7.6.4.2 AUTO BUFFER AND BUFFER CHAINING. The auto buffer and the buffer chaining
modes are supported with the RISC controller by setting the RCI bit in the CMR. The host
processor should initialize the IDMA BD ring (see Figure 7-9) with the appropriate buffer
handling mode, source address, destination address, and block length. The user then sets
the STR bit in the CMR. All transfer modes described in 7.6.4.4.4 External Cycle Steal are
still valid. The function codes for the source and destination addresses are programmed as
described in 7.5.2.5 Timer Capture Registers (TCR1, TCR2, TCR3, TCR4).
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IDMA Channels
IDMA BD BASE
ADDRESS (IBASE)
BD 0
SOURCE DEVICE OR
DATA BUFFER 0
DESTINATION DEVICE
OR DATA BUFFER 0
BD 1
BD 2
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SOURCE DEVICE OR
DATA BUFFER 1
DESTINATION DEVICE
OR DATA BUFFER 1
SOURCE DEVICE OR
DATA BUFFER 2
DESTINATION DEVICE
OR DATA BUFFER 2
BD N
DESTINATION DEVICE
OR DATA BUFFER N
SOURCE DEVICE OR
DATA BUFFER N
Figure 7-9. IDMA BD Ring
The data associated with each IDMA channel for the auto buffer and buffer chaining modes
is stored in buffers. Each buffer is referenced by a BD. The BDs use a ring structure located
in the dual-port RAM.
7.6.4.2.1 IDMA Parameter RAM. When an IDMA channel is configured to the auto buffer or
buffer chaining mode, the QUICC uses the IDMA parameters listed in Table 7-2.T
Table 7-3. IDMA Parameter RAM
Address
Name
Width
Description
IDMA Base + 00
IBASE
Word
IDMA BD Base Address
IDMA Base + 02
IBPTR
Word
IDMA BD Pointer
IDMA Base + 04
ISTATE
Long
IDMA Internal State
IDMA Base + 08
ITEMP
Long
IDMA Temp
NOTE: The entry in boldface must be initialized by the user.
The IBASE entry defines the starting location in the dual-port RAM for the set of IDMA BDs.
It is an offset from the beginning of the dual-port RAM. The user must initialize this entry
before enabling the IDMA channel. Furthermore, the user should not overlap BD tables of
two enabled serial channels or IDMA channels, or erratic operation will result. IBASE should
contain a value that is divisible by 16.
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IDMA Channels
The IBPTR entry points to the next BD that the IDMA will transfer data to when it is in IDLE
state or points to the current BD during transfer processing. After a reset or when the end of
an IDMA BD table is reached, the CP initializes this pointer to the value programmed in the
IBASE entry.
ISTATE and ITEMP are for RISC use only.
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7.6.4.2.2 IDMA Buffer Descriptors (BDs). Source addresses, destination addresses, and
byte counts are presented to the RISC controller using special IDMA BDs. The RISC controller reads the BDs, programs the IDMA channel, and notifies the CPU32+ about the completion of a buffer transfer using the IDMA BDs. This concept is like that used for the serial
channels on the QUICC, except that the BD is larger to contain additional information.
OFFSET + 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V
—
W
I
L
—
CM
—
—
—
—
—
—
SE
DE
DA
OFFSET + 2
OFFSET + 4
DATA LENGTH
OFFSET + 6
OFFSET + 8
SOURCE DATA BUFFER POINTER
OFFSET + A
OFFSET + C
DESTINATION DATA BUFFER POINTER
OFFSET + E
NOTE: Entries in boldface must be initialized by the user.
The following bits are prepared by the user before transfer and are set by the RISC controller
after the buffer has been transferred.
V—Valid
0 = The data buffers associated with this BD are not currently ready for transfer. The
user is free to manipulate this BD or its associated data buffer. When it is not in
auto buffer mode, the RISC controller clears this bit after the buffer has been transferred (or after an error condition is encountered).
1 = The data buffers have been prepared for transfer by the user. (Note that only one
data buffer needs to be prepared if the source/destination is a peripheral device.)
It may be only the source data buffer when the destination is a device or the destination data buffer when the source is a device. No fields of this BD may be written
by the user once this bit is set.
NOTE
The only difference between auto buffer mode and buffer chaining mode is that the V-bit is not cleared by the RISC controller in
the auto buffer mode. Auto buffer mode is enabled by the CM bit.
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W—Wrap (Final BD in Table)
0 = This is not the last BD in the table.
1 = This is the last BD in the table. After the associated buffer has been used, the RISC
controller will transfer data from the first BD in the table (pointed to by IBASE). The
number of BDs in this table is programmable and is determined only by the W-bit
and the overall space constraints of the dual-port RAM.
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I—Interrupt
0 = No interrupt is generated after this buffer has been serviced.
1 = When this buffer has been serviced by the RISC controller the AD bit in the CSR
will be set, which can cause an interrupt.
L—Last
0 = This is not the last buffer to be transferred in the buffer chaining mode. The I-bit
may be used to generate an interrupt when this buffer has been serviced.
1 = This is the last buffer to be transferred in the buffer chaining mode. When the transfer count is exhausted, the START bit will be reset and an interrupt (DONE) will be
generated, regardless of the I-bit.
CM—Continuous Mode
0 = Buffer chaining mode. The RISC will clear the V-bit after this BD is serviced. The
buffer chaining mode is used for transferring large quantities of data into noncontiguous buffer areas. The user can initialize BDs ahead of time, if desired. The
RISC controller automatically reloads the IDMA registers from the next BD’s values
when the transfer is terminated. If DONEx is asserted by an external peripheral,
the buffer will be closed, the STR bit will be reset, and the DONE bit will be set in
the CSR, which can cause an interrupt.
1 = Auto buffer mode (continuous mode). The RISC will not clear the V-bit after this BD
is serviced. This is the only difference between auto buffer mode and buffer chaining mode behavior. The auto buffer mode is used to transfer multiple groups of data
to/from a buffer ring. This mode does not require reprogramming. The RISC controller automatically reloads the IDMA registers from the next BD values when the
transfer is terminated. Either a single BD or multiple BDs may be used in this mode
to create an infinite loop of repeated data moves.
NOTE
The I-bit may still be used to generate an interrupt in this mode.
The following bits are written by the RISC controller after it has finished receiving data from
the associated data buffer.
SE—Source Access Bus Error
The buffer was closed due to a bus error on the source access. An interrupt (BES) will be
generated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
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DE—Destination Access Bus Error
The buffer was closed due to a bus error on the destination access. An interrupt (BED)
will be generated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
DA—Done Asserted During Transfer
The buffer was closed due to the assertion of DONEx. An interrupt (DONE) will be generated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
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Data Length
The data length is the number of bytes that the IDMA should transfer from/to this BD’s
data buffer. The data length should be programmed to a value greater than zero.
Source Buffer Pointer
The source buffer pointer contains the address of the associated source data buffer. The
buffer may reside in either internal or external memory.
NOTE
In single address mode when the source is a device, this field is
ignored. In dual address mode when the source is a device, this
field should contain the device address.
Destination Buffer Pointer
The destination buffer pointer contains the address of the associated destination data
buffer. The buffer may reside in either internal or external memory.
NOTE
In single address mode when the destination is a device, this
field is ignored. In dual address mode when the destination is a
device, this field should contain the device address.
7.6.4.2.3 IDMA Commands (INIT_IDMA). This command causes the RISC controller to
reinitialize its IDMA internal state to the condition it had after a system reset. The IDMA BD
pointer is reinitialized to the top of BD ring. When in the auto buffer and buffer chaining
modes, the IDMA can be reset by setting the RST bit in the CMR and issuing the INIT_IDMA
command. The INIT_IDMA command should only be executed in conjunction with the setting of the RST bit in the CMR.
7.6.4.3 STARTING THE IDMA. Once the channel has been initialized with all parameters
required for a transfer operation, it is started by setting the STR bit in the CMR. After the
channel has been started, any register that describes the current operation may be read but
not modified (SAPR, DAPR, FCR, or BCR).
Once STR has been set, the channel is active and either accepts operand transfer requests
in external mode or generates requests automatically in internal mode. When the first valid
external request is recognized, the IDMA arbitrates for the bus. The DREQx input is ignored
until STR is set.
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For the single buffer mode, STR is cleared automatically when the BCR reaches zero or
when DONEx is asserted externally. For the other buffer handling modes see 7.6.4.8.2 Auto
Buffer Mode Termination. and 7.6.4.8.3 Buffer Chaining Mode Termination. The STR is
cleared in all modes if the IDMA cycle is terminated by a bus error.
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Channel transfer operation may be suspended at any time by clearing STR in software. In
response, any operand transfer in progress will be completed, and the bus will be released.
No further bus cycles will be started while STR remains cleared. During this time, the
CPU32+ core may access IDMA internal registers to determine channel status or to alter
operation. When STR is set again, if a transfer request is pending, the IDMA will arbitrate
for the bus and continue normal operation.
Interrupts from the IDMA are sent to the interrupt controller. In the interrupt handler, the
unmasked bits in the CSR should be cleared (by writing them with a one) to negate the interrupt request to the CPM interrupt controller.
7.6.4.4 REQUESTING IDMA TRANSFERS. Once the IDMA has been started, the transfers
can be requested to the IDMA.
IDMA transfers may be initiated by either internally or externally generated requests. Internally generated requests can be initiated by setting STR in the CMR or, in auto buffer and
buffer chaining modes, by also setting RCI in the CMR and preparing a data buffer to the
RISC controller. Externally generated transfers are those requested by an external device
using DREQx in conjunction with the activation of STR.
7.6.4.4.1 Internal Maximum Rate. The first method of internal request generation is a nonstop transfer until the transfer count is exhausted. If this method is chosen, the IDMA will
arbitrate for the bus and begin transferring data after STR is set and the IDMA becomes the
bus master. During each access to the device (determined by the ECO bit in the CMR), the
IDMA will assert DACKx to indicate to the device that it is being serviced. If no exception
occurs, all operands in the data block will be transferred in one burst with the IDMA using
100% of the available bus bandwidth (unless a higher priority bus master requests the bus
or a higher priority interrupt requests service). See 7.6.2.2 Channel Mode Register (CMR)
for more detail.
7.6.4.4.2 Internal Limited Rate. To guarantee that the IDMA will not use all the available
system bus bandwidth during a transfer, internal requests can be limited to the amount of
bus bandwidth allocated to the IDMA. Programming the REQG bits to internal limited rate
and the BT bits to determine the percentage of bandwidth achieves this result. The options
are 12.5%, 25%, 50%, or 75% of the bus. As soon as STR is set, the IDMA module arbitrates
for the bus and begins to transfer data when it becomes bus master. During each access to
the device (determined by the ECO bit in the CMR), the IDMA will assert DACKx to indicate
that it is being serviced. If no exception occurs, transfers will continue normally, but the
IDMA will not exceed the percentage of bus bandwidth programmed into the control register.
The percentage is calculated over each ensuing 1024 internal clock cycle period.
For example, if 12.5% is chosen, the IDMA will attempt to use the bus for the first 128 clocks
of each 1024 clock cycle period. However, because of other bus masters or higher priority
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interrupts, the IDMA may not be able to take its 128 clock allotment in a single burst. If, for
whatever reason, the IDMA is not able to take its full 128 clock allotment in a 1024 clock
cycle period, the IDMA is still only granted a 128 clock allotment in the next 1024 clock cycle
period.
Freescale Semiconductor, Inc...
7.6.4.4.3 External Burst Mode. For external devices requiring very high data transfer
rates, the external burst mode allows the IDMA to use all of the bus bandwidth to service the
device (see Figure 7-10). In the burst mode, the DREQx input to the IDMA is level-sensitive
and is sampled at falling edges of the clock to determine when a valid request is asserted
by the device. The device requests service by asserting DREQx and leaving it asserted. In
response, the IDMA begins to arbitrate for the system bus. If DREQx is negated prior to the
IDMA winning the bus, the IDMA will cease requesting the bus. If DREQx is negated long
enough for the IDMA to win the bus, cycles will continue as long as DREQx is asserted and
no higher priority bus master or interrupt occurs.
OTHER CYCLE
S0
S2
IDMA READ
S4
S0
S2
S4
IDMA WRITE
S0
S2
S4
IDMA READ
S0
S2
S4
IDMA WRITE
S0
S2
S4
CLKO1
AS
(OUTPUT)
DSACKx
(I/O)
DREQx
(INPUT)
DREQ SAMPLED CONTINUE
LOW
BURST
STOP
BURST
DACKx
(OUTPUT)
ECO = 1; PERIPHERAL IS READ.
DREQx
(INPUT)
CONTINUE
BURST
DREQ SAMPLED
LOW
STOP
BURST
DACKx
(OUTPUT)
ECO = 0; PERIPHERAL IS WRITTEN.
NOTES:
1. This example assumes dual address mode. In single address mode, the DREQx sample points would occur
in every IDMA cycle.
2. This example assumes SRM = 1 in the CMR. If SRM = 0, DREQx would have to be asserted and negated one
clock earlier that what is shown to allow it to be internally synchronized by the IDMA before it is used.
Alternatively, the timing shown would be correct for the SRM = 0 case if a wait state were included (between
S3 and S4) in all cycles shown above.
Figure 7-10. External Burst Requests;
Each time the IDMA issues a bus cycle to either read or write the device, the IDMA will output the DACKx signal. The device is either the source or destination of the transfers, as
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determined by the ECO bit in the CMR. The DACKx timing is similar to the timing of the AS
pin. Thus, DACKx is the acknowledgment of the original burst request given on the DREQx
pin.
During each access to the device (i.e., DACKx is asserted), the IDMA will sample DREQx
at the S3 falling edge of the bus cycle to determine whether the burst should continue. If
DREQx is asserted, the burst continues. If DREQx is negated, the burst ceases, and another
operand transfer to/from the device does not occur until DREQx is asserted again. If DREQx
is negated, but not in time to stop the burst on this bus cycle, one additional bus cycle to the
device will occur before the IDMA stops the burst.
Freescale Semiconductor, Inc...
NOTES
Because DACKx timing is similar to AS timing, the user typically
uses the assertion of DACKx as an indication that DREQx is negated.
To meet the S3 sampling time, DREQx should be negated no
later than DSACKx because DSACKx pins are also sampled at
falling S3 to determine the end of the bus cycle.
The previous paragraphs discuss the general rules; however, important special cases are
discussed in the following points:
1. The sample point at the S3 falling edge means the last S3 before the S4 edge that
completes the cycle. Thus, if wait states are inserted in the bus cycle, the sample point
is later in the cycle.
2. The sample point at S3 assumes that the required setup time is met, as defined in Section 10 Electrical Characteristics.
3. If SRM is cleared in the CMR (default condition), then DREQx is synchronized internally before it is used; therefore, DREQx must be negated one clock earlier than the
S3 falling edge to be recognized on that cycle.
4. If operand packing is performed, the user does not need to negate DREQx on any particular access to the device. For instance, if the source is a 32-bit memory and the destination is an 8-bit peripheral, DREQx can be negated on the first, second, third, or
fourth byte access to the peripheral. In each case, if the DREQx negation timings are
met, the IDMA will stop accessing the peripheral immediately with no additional bus
cycles to the peripheral. Accesses to the peripheral will resume when DREQx is asserted.
5. If operand packing is performed and the peripheral is the source and DREQx is negated to stop the burst, the IDMA will attempt to empty the contents of the DHR (by performing one additional write cycle to memory) before giving up the bus. The IDMA
attempts to minimize the contents of the DHR between burst requests.
6. If the access to the device is a fast termination access, the DREQx negation timing
cannot be met, and one additional bus cycle will always occur to the device before the
burst stops.
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7.6.4.4.4 External Cycle Steal. For external devices that generate a pulsed signal for each
operand to be transferred, the external cycle steal mode should be used. In external cycle
steal mode, the IDMA moves one operand for each falling edge of the DREQx input (see
Figure 7-11). In this mode, DREQx is sampled at each falling edge of the clock to determine
when a valid request is asserted by the device. When the IDMA detects a falling edge on
DREQx, a request becomes pending and remains pending until it is serviced by the IDMA.
Further falling edges on DREQx are ignored until the request begins to be serviced. The servicing of the request results in one operand being transferred. The operand will be transferred in back-to-back read and write cycles as long as no other higher priority bus master
or interrupt occurs between the bus cycles.
OTHER CYCLE
Freescale Semiconductor, Inc...
S0
S2
S4
IDMA WRITE
IDMA READ
S0
S2
S4
S0
S2
S4
IDMA READ
S0
S2
S4
IDMA WRITE
S0
S2
S4
CLKO1
AS
(OUTPUT)
DSACKx
(I/O)
CYCLE STEAL
REQUEST
ANOTHER
REQUEST
DREQx
(INPUT)
DACKx
(OUTPUT)
ECO = 1; PERIPHERAL IS READ.
CYCLE STEAL
REQUEST
ANOTHER
REQUEST
DREQx
(INPUT)
DACKx
(OUTPUT)
ECO = 0; PERIPHERAL IS WRITTEN.
NOTES:
1. This example assumes dual address mode. In single address mode, the DREQx sample points would occur in
every IDMA cycle.
2. This example assumes SRM = 1 in the CMR. If SRM = 0, DREQx would have to be asserted one clock earlier and
remain asserted for one clock longer than what is shown to allow it to be internally synchronized by the IDMA
before it is used. Alternatively, the user could assert DREQx as shown and keep DREQx asserted for one
additional clock in the SRM = 0 case, if a wait state were included (between S3 and S4) in all cycles shown above.
3. The sample point for "ANOTHER REQUEST" determines that another IDMA transfer will occur following the current
IDMA operand transfer. During that time, if the IDMA remains the highest priority bus master of the IMB, the transfers will occur back-to-back as shown.
Figure 7-11. External Cycle Steal
Each time the IDMA issues a bus cycle to either read or write the device, the IDMA will output the DACKx signal. The device is either the source or destination of the transfers, as
determined by the ECO bit in the CMR. The DACKx timing is similar to the timing of the AS
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pin. Thus, DACKx is the acknowledgment of the original cycle steal request given on the
DREQx pin.
It is possible to cause the IDMA to perform back-to-back cycle steal requests. To achieve
this, DREQx should be asserted to generate the first request, negated, and reasserted during the access to the device. If the IDMA detects that DREQx is reasserted prior to the S3
falling edge of the bus cycle to the device (i.e., bus cycle when DACKx is asserted), then
another back-to-back cycle steal request will be performed. Otherwise, the bus is relinquished. If DREQx was not reasserted soon enough, a new request will be made to the
IDMA, but the bus will be relinquished and re-requested by the IDMA.
Freescale Semiconductor, Inc...
NOTE
To generate back-to-back cycle steal requests, DREQx should
be reasserted after DACKx is asserted, but before the S3 falling
edge. Instead of saying before the S3 falling edge, one could
also say before or with the assertion of DSACKx because the
DSACKx pins are also sampled at falling S3 to determine the
end of the bus cycle.
The previous paragraphs discuss the general rules; however, important special cases are
discussed in the following points:
1. The sample point at the S3 falling edge means the last S3 before the S4 edge that
completes the cycle. Thus, if wait states are inserted in the bus cycle, the sample point
is later in the cycle.
2. The sample point at S3 assumes that the required setup time is met, as defined in Section 10 Electrical Characteristics.
3. If SRM is cleared in the CMR (default condition), then DREQx is synchronized internally before it is used; therefore, DREQx must be reasserted one clock earlier than the
S3 falling edge to be recognized on that cycle and generate a back-to-back request.
7.6.4.5 IDMA BUS ARBITRATION. Once the IDMA receives a request for a transfer, it
begins arbitrating for the IMB. (The four request types are internal maximum rate, internal
limited rate, external burst, and external cycle steal.)
On the QUICC, the IDMAs, SDMAs, and DRAM refresh controller, called internal masters,
have the capability to become bus master. To determine the relative priority of these masters, each is given an arbitration ID. The user programs the arbitration ID (a value between
0 and 7) of the IDMAs into the ICCR. The arbitration IDs of the two IDMAs must be different
by a value of 2 (e.g., IDMA1 ID = 2 and IDMA2 ID = 0). These values are used to determine
the relative priority of the IDMA channel and the other internal bus masters.
NOTE
Typically, the IDMA IDs are configured by the user to be the lowest of the internal bus masters.
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IMB bus masters request bus ownership on a per-cycle basis. Thus, on each bus cycle, the
IMB is given to the highest priority bus master requesting the bus. External bus masters may
also request the bus and obtain priority over the internal bus masters.
Freescale Semiconductor, Inc...
In addition, on the QUICC, interrupts may take priority over bus masters. Thus, another condition for the IDMA to obtain the bus is for the interrupt service level on the IMB to be less
than or equal to the interrupt service mask (ISM bits) in the ICCR.
If the CPU32+ is enabled, the IDMA bus arbitration sequence is like that shown in Figure 712. The BR, BG, and BGACK signals are not affected during the arbitration sequence. The
only external indication of an IDMA bus request is the bus clear out (BCLRO) pin. BCLRO
is only available externally if programmed in the SIM60 port E pin assignment register. Additionally, BCLRO is only asserted if the IDMA ID for that channel is greater than the value
programmed into the BCLROID2-BCLROID0 bits in the SIM60 module configuration register. BCLRO can be used to clear off an external bus master from the external bus, if desired.
For instance, BCLRO can be connected through logic to the external master’s HALT signal,
and then negated externally when the external master’s AS signal is negated. BCLRO is
negated during S2 of the final IDMA bus cycle before it relinquishes the bus.
OTHER CYCLE
S0
S2
S4
IDMA READ
S0
S2
IDMA WRITE
S4
S0
S2
S4
S0
CLKO1
AS
(OUTPUT)
DSACKx
(I/O)
DREQx
(INPUT)
DREQ SAMPLED
LOW
DACKx
(OUTPUT)
BCLRO
(OUTPUT)
BR
(INPUT)
BG
(OUTPUT)
BGACK
(I/O)
NOTES:
1. The BCLRO signal is only asserted if the IDMA bus arbitration ID is greater than
the BCLROID2–BCLROID0 bits in the SIM60 module configuration register.
2. Note that the BR, BG, and BGACK signals are not affected by the IDMA bus arbitration process if the CPU32+ is enabled.
Figure 7-12. IDMA Bus Arbitration (Normal Operation)
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The relative priority between the two IDMAs and SDMA channels is user programmable.
Regardless of the system configuration, if the SDMA is a bus master when a higher priority
IDMA channel needs to transfer over the bus, the IDMA will steal cycles from the SDMA with
no arbitration overhead.
Freescale Semiconductor, Inc...
When the QUICC is in slave mode (CPU32+ disabled), the IDMA can steal cycles from the
SDMA with no arbitration overhead. See Section 4 Bus Operation for diagrams of bus arbitration by an internal master in slave mode.
Additionally, when the QUICC is in slave mode, the BCLRI pin can be used to force the
IDMA and other internal bus masters off the bus. The BCLRI pin is assigned an arbitration
ID in slave mode to allow a selection of which internal bus masters are allowed to be forced
off the bus. An application of this capability is to connect the BCLRO pin of a QUICC in normal operation to the BCLRI pin of a QUICC in slave mode. This configuration allows the user
to implement capabilities such as giving all SDMA channels priority over all IDMA channels
in the system.
7.6.4.6 IDMA OPERAND TRANSFERS. Once the IDMA successfully arbitrates for the bus,
it can begin making operand transfers. The source IDMA bus cycle has timing identical to
an internal master read bus cycle. The destination IDMA bus cycle has timing identical to an
internal master write bus cycle.
The two-channel IDMA module supports dual and single address transfers. The dual
address operand transfer consists of a source operand read and a destination operand
write. Each single address operand transfer consists of one external bus cycle, which allows
either a read or a write cycle to occur.
7.6.4.6.1 Dual Address Mode. The two IDMA channels can each be programmed to operate in a dual address transfer mode (see Figure 7-13). In this mode, the operand is read from
the source address specified in the SAPR and placed in the DHR. The operand read may
take up to four bus cycles to complete because of differences in operand sizes of the source
and destination. The operand is then written to the address specified in the DAPR. This
transfer may also be up to four bus cycles long. In this manner, various combinations of
peripheral, memory, and operand sizes may be used.
The dual address transfers can be started either by the internal request mode or by an external device using DREQx. When the external device uses DREQx, the channel can be programmed to operate in either the cycle steal or burst transfer modes. See 7.6.4.4.3 External
Burst Mode and 7.6.4.4.4 External Cycle Steal for information about these modes.
Dual Address Source Read. During this type of IDMA cycle, the SAPR drives the address
bus, the FCR drives the source function codes, and the CMR drives the size control. Data
is read from the memory or peripheral and placed in the DHR when the bus cycle is terminated. When the complete operand has been read, the SAPR is incremented by 1, 2, or 4,
depending on the address and size information specified by the SAPI and SSIZE bits of the
CMR. See 7.6.2.3 Source Address Pointer Register (SAPR) for more information.
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DATA
BUS
QUICC
MEMORY
1
IDMA
ADDR.
1
DHR
DACKx
AND
ADDR.
PERIPHERAL
2
Freescale Semiconductor, Inc...
TWO BUS CYCLES
REQUIRED
Figure 7-13. Dual Address Transfer Example
Dual Address Destination Write. During this type of IDMA cycle, the data in the DHR is
written to the device or memory selected by the address in the DAPR, the destination function codes in the FCR, and the size in the CMR. The same options exist for operand size
and alignment as in the dual address source read. When the complete operand is written,
the DAPR is incremented by 1, 2, or 4, according to the DAPI and DSIZE bits of the CMR,
and the BTC is decremented by the number of bytes transferred. If the BTC is equal to zero,
the DONEx signal for the IDMA handshake is asserted, and if the transfer is completed with
no errors, the DONE bit in the CSR is set. See 7.5.2.4 Timer Reference Registers (TRR1,
TRR2, TRR3, TRR4) and 7.6.2.6 Byte Count Register (BCR) for more information.
Dual Address Packing. When dual address mode is selected, the IDMA can perform packing. Regardless of the source size, destination size, source starting address, or destination
starting address, the IDMA will use the most efficient packing algorithm possible to perform
the transfer in the fewest possible number of bus cycles.
NOTE
The packing algorithms are subject to the restriction that the
IDMA never performs 3-byte transfers.
Three examples of the packing technique follow.
Example 1. This simple example shows how packing is performed when the source and destination sizes are the same—word. The source address is $00000001, and the destination
address is $20000000. The number of bytes to be transferred is 4.
IDMA channel 1 initialization required for this example:
—ICCR = $0720. Recommended normal configuration.
—FCR1 = $89. Source function code is 1000; destination function code is 1001.
—SAPR1 = $00000001. Source address.
—DAPR1 = $20000000. Destination address.
—BCR1 = $00000003. Byte transfer count.
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—CSR1 = $FF. Clear any CSR bits that are currently set.
—CMAR1 = $00. Disable interrupts for this example.
—CMR1 = $47A1. Internal maximum transfer rate; starts IDMA.
Bus Access #
Address (Hex)
Operation
No. Bytes
No. Bytes in DHR
1
$00000001
Read
1
1
2
$00000002
Read
2
3
3
$20000000
Write
2
1
4
$00000002
Write
1
0
Example 2. This more complicated example shows how packing is performed when the
source and destination sizes are the same—long word. This example also shows the entire
7-byte DHR in use. The source address is $00000000, and the destination address is
$20000003. The number of bytes to be transferred is 16.
IDMA channel 1 initialization required for this example:
• ICCR = $0720. Recommended normal configuration.
• FCR1 = $89. Source function code is 1000; destination function code is 1001.
• SAPR1 = $00000000. Source address.
• DAPR1 = $20000003. Destination address.
• BCR1 = $00000010. Byte transfer count.
• CSR1 = $FF. Clear any CSR bits that are currently set.
• CMAR1 = $00. Disable interrupts for this example.
• CMR1 = $4701. Internal maximum transfer rate; starts IDMA.
Bus Access #
Address (Hex)
Operation
No. Bytes
No. Bytes in DHR
1
$00000000
Read
4
4
2
$20000003
Write
1
3
3
$00000004
Read
4
7
4
$20000004
Write
4
3
5
$00000008
Read
4
7
6
$20000008
Write
4
3
7
$0000000C
Read
4
7
8
$2000000C
Write
4
3
9
$20000010
Write
2
1
10
$20000012
Write
1
0
Example 3. This example shows how packing operates when the source and destination
sizes are different. The source address is $00000002, and the destination address is
$20000002. The source size is long word, and the destination size is byte. The number of
bytes to be transferred is 8.
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IDMA Channels
IDMA channel 1 initialization required for this example:
• ICCR = $0720. Recommended normal configuration.
• FCR1 = $89. Source function code is 1000; destination function code is 1001.
• SAPR1 = $00000002. Source address.
• DAPR1 = $20000002. Destination address.
• BCR1 = $00000008. Byte transfer count.
• CSR1 = $FF. Clear any CSR bits that are currently set.
• CMAR1 = $00. Disable interrupts for this example.
Freescale Semiconductor, Inc...
• CMR1 = $4711. Internal maximum transfer rate; starts IDMA.
Bus Access #
Address (Hex)
Operation
No. Bytes
No. Bytes in DHR
1
$00000002
Read
2
2
2
$20000002
Write
1
1
3
$20000003
Write
1
0
4
$00000004
Read
4
4
5
$20000004
Write
1
3
6
$20000005
Write
1
2
7
$20000006
Write
1
1
8
$20000007
Write
1
0
9
$00000008
Read
2
2
10
$20000008
Write
1
1
11
$20000009
Write
1
0
7.6.4.6.2 Single Address Mode (Flyby Transfers). Each IDMA channel can be independently programmed to provide single address transfers. Figure 7-14 illustrates a transfer
from memory to a peripheral. The DHR is not used by the IDMA, since the transfer occurs
directly from a device to memory. This mode is often referred to as "flyby" mode because
the DHR is not used.
DATA
BUS
QUICC
IDMA
MEMORY
1
ADDR.
DACKx
PERIPHERAL
1
JUST ONE BUS CYCLE
REQUIRED
Figure 7-14. Single Address Transfer Example
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Both internal and external request modes can be used to start a transfer when the single
address mode is selected (see Figure 7-15). The ECO bit in the CMR controls whether a
source read or a destination write cycle occurs on the data bus. If the ECO bit is set, the
external handshake signals are used with the source operand, and a single address source
read occurs. If the ECO bit is cleared, the external handshake signals are used with the destination operand, and a single address destination write occurs.
NOTE
Single address mode does not support access to the internal
dual port ram of MC68360. In order to transfer from/to internal
dual port ram, user should use dual address mode.
Freescale Semiconductor, Inc...
OTHER CYCLE
S0
S2
S4
IDMA
MEMORY READ
PERIPHERAL WRITE
S0
S2
S4
IDMA
MEMORY READ
PERIPHERAL WRITE
S0
S2
S4
S0
CLKO1
AS
(OUTPUT)
DSACKx
(I/O)
R/W
(OUTPUT)
ANOTHER
TRANSFER
CYCLE STEAL
REQUEST
DREQx
(INPUT)
CYCLE STEAL
REQUEST
DREQx
(INPUT)
BURST MODE
REQUEST
DREQ SAMPLED
LOW
CONTINUE
BURST
STOP
BURST
DACKx
(OUTPUT)
NOTE:
1. This example assumes the peripheral is being written. If the peripheral is being read,
R/W would be low during the transfers.
2. This example shows the operation of DREQ in two different modes.
3. This example assumes that SRM = 0 in the CMR. Otherwise, DREQx would not be
recognized by the IDMA until it had been sampled on two consecutive falling edges of
the clock.
Figure 7-15. Single Address Mode Timing
Single Address Source Read. During the single address source read cycle, the device or
memory selected by the address in the SAPR, the source function codes in the FCR, and
the size in the CMR provides the data and control signals on the data bus. This bus cycle
operates like a normal read bus cycle. The destination device is controlled by the IDMA
handshake signals (DREQx, DACKx, and DONEx). The assertion of DACKx provides the
write control to the destination device. For more details about the IDMA handshake signals,
see 7.6.3 Interface Signals.
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Single Address Destination Write. During the single address destination write cycle, the
source device is controlled by the IDMA handshake signals (DREQx, DACKx, and DONEx).
When the source device requests service from the IDMA channel, the IDMA asserts of
DACKx to allow the source device to drive data onto the data bus. The data is written to the
device or to memory selected by the address in the DAPR, the destination function codes in
the FCR, and the size in the CMR. The data bus is placed in a high-impedance state for this
write cycle. For more details about the IDMA handshake signals, see 7.6.3 Interface Signals.
7.6.4.6.3 Fast-Termination Option. While in the operand transfer phase, the IDMA supports an option to achieve a transfer in the shortest possible number of clocks (see Figure
7-16).
IDMA READ
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OTHER CYCLE
S0
S2
S4
IDMA
FAST
TERMINATION
WRITE
S0
S2
S4
S0
S4
S0
CLKO1
AS
(OUTPUT)
DSACKx
(I/O)
R/W
(OUTPUT)
DREQx
(INPUT)
CYCLE STEAL
REQUEST
DACKx
(OUTPUT)
ECO = 1
PERIPHERAL IS
BEING READ
DACKx
(OUTPUT)
ECO = 0
PERIPHERAL IS
BEING WRITTEN
NOTE: This example shows a fast termination on the write cycle. The fast termination
may occur on the read, write, or both.
Figure 7-16. Fast Termination Example
Using the SIM60 chip-select logic, the fast-termination option can be employed to give a fast
bus access of two clock cycles rather than the standard three-cycle access time. The fasttermination option is described in Section 6 System Integration Module (SIM60) and in Section 4 Bus Operation.
If the fast-termination option is used with external request burst mode, an extra IDMA cycle
results on every burst transfer. In the burst mode with fast termination selected, a new cycle
starts even if DREQx negation and DACKx assertion occur simultaneously.
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IDMA Channels
7.6.4.6.4 Externally Recognizing IDMA Operand Transfers. There are several methods
to externally determine that a bus cycle is being executed by the IDMA:
1. The function code lines may be programmed to a unique function code that identifies
an IDMA transfer.
2. The BCLRO pin can be used to show when the bus request is made. BCLRO is negated during the final access by the IDMA before relinquishing the bus.
3. The DACKx signal shows accesses to the peripheral device. DACKx will operate even
in the internal request modes and will activate on either the source or destination bus
cycles, depending on the ECO bit in the CMR.
NOTE
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Items 1 and 2 may also be used by the SDMA channels.
7.6.4.7 BUS EXCEPTIONS. While the IDMA has the bus and is performing operand transfers, it is possible for bus exceptions to occur.
In any computer system, the possibility exists that an error will occur during a bus cycle due
to a hardware failure, random noise, or an improper access. When an asynchronous bus
structure, such as that supported by the M68000 is used, it is easy to make provisions allowing a bus master to detect and respond to errors during a bus cycle. The IDMA recognizes
the same bus exceptions as the CPU32+ core: reset, bus error, halt, and retry.
7.6.4.7.1 Reset. Upon an external reset, the IDMA immediately aborts the channel operation, returns to the idle state, and clears CSR and CMR (including the STR bit). If a bus cycle
is in progress when reset is detected, the cycle is terminated, the control and address/data
pins are three-stated, and bus ownership is released. The IDMA can also be reset by RST
in the CMR.
7.6.4.7.2 Bus Error. When a fatal error occurs during a bus cycle, a bus error exception is
used to abort the cycle and systematically terminate that channel’s operation. The IDMA terminates the current bus cycle, signals an error in the CSR using either the BES or BED bit,
and signals an interrupt if the corresponding bit in the CMAR is set. The IDMA clears STR
and waits for a restart of the channel and the negation of BERR before starting any new bus
cycles. Any data that was previously read from the source into the DHR will be lost.
NOTE
Any device that is the source or destination of the operand under
IDMA handshake control for single address transfers may need
to monitor BERR to detect a bus exception for the current bus
cycle. BERR terminates the cycle immediately and negates
DACKx, which is used to control the transfer to or from the device.
7.6.4.7.3 Retry. When HALT and BERR are asserted during a bus cycle, the IDMA terminates the bus cycle, releases the bus, and suspends further operation until these signals are
negated. When HALT and BERR are negated, the IDMA will arbitrate for the bus, re-execute
the previous bus cycle, and continue normal operation.
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If the IDMA has obtained the IMB and is also waiting to obtain the external bus, but the external bus master performs an access to a location internal to the QUICC, the IDMA will relinquish the IMB and retry the cycle once it has obtained the IMB.
7.6.4.8 ENDING THE IDMA TRANSFER. If no bus exceptions occur, the IDMA eventually
finishes the transfer of a block of data. These paragraphs describe normal termination in
more detail. (Termination by error is discussed in 7.6.4.7.2 Bus Error.)
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The IDMA channel operation experiences normal termination when the BCR is decremented to zero or the external device signals a termination of the transfer using DONEx.
These terminations are independent of how requests are generated to the IDMA.
Additionally, the user may stop the IDMA channel by clearing STR. However, this is considered a suspension of activity, rather than normal termination, since the transfer resumes
when STR is set once again.
The user may also terminate the transfer by setting the RST bit in the CMR; however, this
is not a normal termination of IDMA activity.
Further description of normal termination depends on the mode of the IDMA: single buffer
mode, auto buffer mode, and buffer chaining. These modes are described in the following
paragraphs.
7.6.4.8.1 Single Buffer Mode Termination. The following methods may be used to terminate an IDMA transfer in the single buffer mode. They may also be used to terminate a current BD transfer in the auto buffer and buffer chaining modes.
Transfer Count Exhausted. When the channel performs an operand transfer, it decrements the BCR for each byte transferred successfully. When the BCR is decremented to
zero, the transfer is terminated. When the last bus cycle of the transfer occurs (either a byte,
word, or long-word access), DONEx is asserted during that bus cycle. If the device is the
source, further destination accesses will take place after DONEx is asserted. If the device
is the destination, DONEx will be asserted on the final bus cycle of the destination write.
NOTE
This behavior of DONEx also applies to memory-to-memory
transfers. DONEx is asserted on either the last source or destination bus cycle, as determined by the ECO bit in the CMR.
When the operand transfer has completed and the BCR has been decremented to zero, the
channel operation is terminated, STR is cleared, and a DONE bit interrupt is generated if the
corresponding CMAR bit is set. The SAPR and/or DAPR are also incremented in the normal
fashion.
NOTE
If the channel was started with the BCR value set to zero, the
channel will transfer 4 Gbytes before the transfer count is exhausted.
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IDMA Channels
External Device Termination. If the DONEx pin is asserted externally, a transfer may be
terminated by the device even before the BCR is decremented to zero. DONEx is sampled
by the IDMA on the access to the device.
NOTE
This behavior of DONEx also applies to memory-to-memory
transfers. DONEx is sampled on either the source or destination
bus cycles, as determined by the ECO bit in the CMR.
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If DONEx is asserted on a bus cycle to a source device, the destination accesses will be
performed before the IDMA terminates transfers. If DONEx is asserted during a bus cycle
to a destination device, no further IDMA bus cycles occur, and the IDMA terminates transfers.
The IDMA samples DONEx on the S3 falling edge of the bus cycle. Thus, the user should
assert DONEx at least one setup time before the S3 falling edge for DONEx to be recognized on that bus cycle.
NOTES
Because DACKx timing is similar to AS timing, the user uses the
assertion of DACKx as an indication that DONEx is asserted.
To meet the S3 sampling time, DONEx should be asserted no
later than DSACKx because the DSACKx pins are also sampled
at falling S3 to determine the end of the bus cycle.
The previous paragraphs discuss the general rules; however, important special cases are
discussed in the following points:
1. The sample point at the S3 falling edge means the last S3 before the S4 edge that
completes the cycle. Thus, if wait states are inserted in the bus cycle, the sample point
is later in the cycle.
2. The sample point at S3 assumes that the required setup time is met, as defined in Section 10 Electrical Characteristics.
3. If SRM is cleared in the CMR (default condition), then DONEx is synchronized internally before it is used; therefore, DONEx must be negated one clock earlier than the
S3 falling edge to be recognized on that cycle.
4. If the device is configured to be the source and dual address mode, the sample point
used by the IDMA is S5 rather than S3. This gives the user one additional clock to assert the DONEx signal.
When the operand transfer has terminated, STR is cleared, and a DONE bit interrupt is generated if the corresponding CMAR bit is set. The SAPR and/or DAPR are also incremented
in the normal fashion, and the BCR is decremented.
7.6.4.8.2 Auto Buffer Mode Termination. The user can suspend a transfer in auto buffer
mode by clearing the STR bit in the CMR. When STR is set once again, the transfer will continue.
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The user can terminate the transfer by setting the RST bit in the CMR and then issuing the
INIT_IDMA command.
The user can terminate the transfer with an "out of buffers" error if the V-bit of one of the BDs
is cleared by the user. When the RISC reaches this IDMA BD, it will terminate activity. This
technique is useful when the IDMA is required to stop transfers after fully completing a BD
transfer.
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If the BCR is decremented to zero, the transfer from this BD completes, but the RISC controller reloads the IDMA registers with the values from the next IDMA BD, and the IDMA
transfer continues. Thus, the fact that the BCR is decremented to zero does not terminate a
transfer in auto buffer mode; it only terminates the current BD transfer.
If DONEx is asserted externally, the transmission from this BD is terminated and the following actions are performed by the RISC controller:
1. Sets the Done Bit in the status register
2. Sets the DA bit in the BD
3. Clears the Valid bit in the BD
4. Resets the start bit in the CMR
Thus the current buffer is closed immediately and all IDMA operation ceases.
7.6.4.8.3 Buffer Chaining Mode Termination. The user can suspend a transfer in auto
buffer mode by clearing the STR bit in the CMR. When STR is set once again, the transfer
will continue.
The user can terminate the transfer by setting the RST bit in the CMR and then issuing the
INIT_IDMA command.
The user can also terminate the transfer by setting the L-bit in the IDMA BD. When processing of this BD has completed, the transmission will terminate with the DONE bit being set in
the CSR. This can cause an interrupt if the corresponding bit in the CMAR is set.
If the BCR is decremented to zero, the transfer from this BD completes, but the RISC controller reloads the IDMA registers with the values from the next IDMA BD, and the IDMA
transfer continues. Thus, the fact that the BCR is decremented to zero does not terminate a
transfer in buffer chaining mode; it only terminates the current BD transfer.
If DONEx is asserted externally, the transmission from this BD is terminated and the following actions are performed by the RISC controller.
1. Sets the Done Bit in the status register
2. Sets the Abort bit in the BD
3. Clears the Ready bit in the BD
4. Resets the start bit in the CMR
5. Sets the Reset bit in the CMR
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IDMA Channels
7.6.5 IDMA Examples
The following paragraphs provide IDMA examples.
7.6.5.1 SINGLE BUFFER EXAMPLES. To see three examples of single buffer operation,
see the 7.6.4.6.1 Dual Address Mode.
7.6.5.2 BUFFER CHAINING EXAMPLE. •The following example shows the setup required
to initialize IDMA channel 1 to perform three buffer transfers using the buffer chaining
mode. This example will move 16 bytes from address 0 to address $1000, then 16 bytes
from address $100 to $1100, and then 16 bytes from address 200 to $1200.
1. Initialize basic IDMA channel 1 registers:
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2. ICCR = $0720. Recommended normal configuration.
3. FCR1 = $89. Source function code is 1000; destination function code is 1001.
4. SAPR1 not initialized. Will be initialized later by RISC controller.
5. DAPR1 not initialized. Will be initialized later by RISC controller.
6. BCR1 not initialized. Will be initialized later by RISC controller.
7. CSR1 = $FF. Clear any CSR bits that are currently set.
8. CMAR1 = $00. Disable interrupts for this example.
9. CMR1 = $530C. The RISC controls the IDMA activity (RCI bit is set). The IDMA
channel uses 12.5% of the bus bandwidth. The source and destination size are
long word. Do not set the STR bit yet.
10. Issue the INIT_IDMA command to the RISC controller. This command is not required
unless the IDMA was reset with the CMR RST bit while in the buffer chaining or auto
buffer modes.
11. CR = $0591. Issue INIT_IDMA command to IDMA channel 1.
12. Initialize the IDMA channel 1 parameter RAM:
13. IBASE = $0000. This points the beginning of the IDMA BDs. The value of $0000
means that the first IDMA BD is located at the beginning of the internal dual-port
RAM.
14. Initialize the first IDMA BD:
15. BD1_STATUS = $0000. This is offset 0 from the BD. Set up all bits except the
V-bit.
16. BD1_Data_Length = $00000010. Transfer 16 bytes.
17. BD1_Source_Pointer = $00000000. Source address.
18. BD1_Destination_Pointer = $00001000. Destination address.
19. BD1_STATUS = $8000. Set the V-bit. It is good practice to set the V-bit last;
however, in this example the IDMA channel is not yet enabled, so it could have
been set earlier.
20. Initialize the second IDMA BD:
21. BD2_STATUS = $0000. This is offset 0 from the BD. Set up all bits except the
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V-bit.
22. BD2_Data_Length = $00000010. Transfer 16 bytes.
23. BD2_Source_Pointer = $00000100. Source address.
24. BD2_Destination_Pointer = $00001100. Destination address.
25. BD2_STATUS = $8000. Set the V-bit. It is good practice to set the V-bit last;
however, in this example the IDMA channel is not yet enabled, so it could have
been set earlier.
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26. Initialize the third IDMA BD:
27. BD3_STATUS = $2800. This is offset 0 from the BD. Set up all bits except the
V-bit. In this case, set the L-bit to indicate that the IDMA should stop after this BD,
and set the DONE bit in the CSR. Additionally, set the W-bit to cause the RISC to
point to the first BD when done. The W-bit should always be set in the last BD of
the list.
28. BD3_Data_Length = $00000010. Transfer 16 bytes.
29. BD3_Source_Pointer = $00000200. Source address.
30. BD3_Destination_Pointer = $00001200. Destination address.
31. BD3_STATUS = $A800. Set the V-bit. It is good practice to set the V-bit last;
however, in this example the IDMA channel is not yet enabled, so it could have
been set earlier.
32. Start the IDMA channel:
33. CMR1 = $530D. Set the STR bit of this register. The IDMA now begins
transferring all three BDs.
34. Check for successful completion:
35. Read the CMR and wait for the STR bit to be cleared, indicating the end of the
transfer. Read the CSR to see what status has been set. In this case, only the
DONE bit should be set. The AD bit would only be set if the I-bit of the
BD_STATUS field had been set.
7.6.5.3 AUTO BUFFER EXAMPLE. The previous buffer chaining example can be easily
modified to show the auto buffer operation. Simply set the CM bit in the BD_STATUS words
of each of the three BDs, and for the sake of clarity, clear the L-bit of the third BD. The IDMA
channel will then repeatedly transfer groups of 16 bytes until the STR bit is cleared in software, the IDMA is reset, or the V-bit is cleared in one of the IDMA BDs.
NOTE
Use of the IDMA internal maximum rate option in the auto buffer
mode is not recommended because the CPU32+ would only be
able to execute instructions during the brief period that the RISC
is configuring the IDMA channel between BDs. These bits MUST
be set to 7 if the QUICC is in slave mode.
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SDMA Channels
7.7 SDMA CHANNELS
Fourteen SDMA channels are present on the QUICC. Eight are associated with the four fullduplex SCCs. The other six are assigned to the service of the SPI and the two SMCs. Each
channel is permanently assigned to service either the receive or transmit operation of an
SCC, SMC, or SPI.
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Figure 7-17 shows the paths of the data flow. Data from the SCCs, SMCs, and SPI may be
routed to the external RAM (path 1) or the internal dual-port RAM (path 2). In both cases,
however, the IMB is used for the data transfer. On a path 1 access, the IMB and the external
system bus must be acquired by the SDMA channel. On a path 2 access, only the IMB
needs to be acquired, and the access will not be seen on the external system bus unless
the QUICC is configured into the "show cycles" mode of the SIM60. Thus, the transfer on
the IMB can occur while other operations occur simultaneously on the external system bus.
Each SDMA channel may be programmed to output one of 16 function codes. The function
codes are used to identify the channel that is currently accessing memory. Also, the SDMA
channel may be assigned a big endian (Motorola) or little endian format for accessing buffer
data. These features are programmed in the receive and transmit function code registers
associated with the SCCs, SMCs, and SPI.
If a bus error occurs on an access by the SDMA, the CPM generates a unique interrupt in
the SDMA status register. The interrupt service routine then reads the SDMA address register to determine the address on which the bus error occurred. The channel that caused the
bus error is determined by reading the Rx internal data pointer and Tx internal data pointers
from the specific protocol parameters area in the parameter RAM for the serial channels. If
an SDMA bus error occurs, all CP activity ceases, and the entire CP must be reset in the
command register.
7.7.1 SDMA Bus Arbitration and Bus Transfers
On the QUICC, the SDMA, IDMA, and DRAM refresh controller can become internal bus
masters. To determine the relative priority of these masters, each is given an arbitration ID.
The 14 SDMA channels share the same ID, which is programmed by the user. Therefore,
any SDMA channel can arbitrate for the bus against the other internal masters and any
external masters that are present.
Once an SDMA channel obtains the system bus, it remains the bus master for one longword transfer before relinquishing the bus. This feature, in combination with the zero clock
arbitration overhead provided by the IMB, allows the simultaneous benefits of bus efficiency
and low bus latency.
In the case of character-oriented protocols, the SDMA writes characters to memory (it does
not wait for multiple characters to be received before writing), but the SDMA always reads
long words. This is consistent with the goal of providing low-latency operation on characteroriented protocols that tend to be used at slower rates.
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SDMA Channels
EXTERNAL
RAM
CPU32+
CORE
SIM60
1
INTERNAL IMB
2
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14 SDMA
CHANNELS
RISC
CONTROLLER
EXTERNAL
ROM
INTERNAL
DUAL-PORT
RAM
SERIAL CHANNEL DATA FLOW
4 SCCs
2 SMCs
1 SPI
QUICC
Figure 7-17. SDMA Data Paths
The read or write operation may take multiple bus cycles if the memory provides less than
a 32-bit port size. For instance, a 32-bit long-word read from a 16-bit memory will take two
SDMA bus cycles. As long as a higher priority bus master does not require the bus during
an SDMA transfer, the entire operand (32 bits on reads and 8, 16, or 32 bits on writes) will
be transferred in back-to-back bus cycles before the SDMA relinquishes the bus. If a higher
priority bus master requests the bus during an operand transfer, it will be granted the bus at
the end of that SDMA bus cycle. Once the higher priority bus master relinquishes the bus,
the SDMA will reacquire the bus and continue any outstanding bus cycles.
The SDMA can steal cycles with no arbitration overhead when the QUICC is in master mode
(i.e., the CPU32+ is enabled) and the external bus is not currently being held by an external
master (see Figure 7-18). Note that in normal operation, the BR, BG, and BGACK signals
are not affected by the SDMA; however, an indication of the SDMA internal bus request can
be obtained from the BCLRO signal.
The SDMA will assert the BCLRO signal when it requests the bus if this capability is programmed in the SIM60 module configuration register and port E pin assignment register.
BCLRO can be used to clear an external bus master from the external bus, if desired. For
instance, BCLRO can be connected through logic to the external master’s HALT signal, and
then be negated externally when the external master’s AS signal is negated. BCLRO, as
seen from the QUICC, is negated by the SDMA during its access to memory.
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SDMA READ
(32 BITS)
OTHER CYCLE
S0
S2
S4
S0
S2
S4
SDMA Channels
OTHER CYCLE
S0
S2
S4
S0
CLKO1
AS
(OUTPUT)
DSACKx
(I/O)
BCLRO
(OUTPUT)
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BR
(INPUT)
BG
(OUTPUT)
BGACK
(I/O)
SDMA INTERNALLY
REQUESTS BUS
NEGATED DURING
FINAL SDMA
BUS CYCLE
NOTES:
1. The BCLRO signal is only asserted if the SDMA bus arbitration ID is greater than
the BCLROID2–BCLROID0 bits in the SIM60 module configuration register.
2. The BR, BG, and BGACK signals are not affected by the SDMA bus arbitration
process if the CPU32+ is enabled.
Figure 7-18. SDMA Bus Arbitration (Normal Operation)
The relative priority between the two IDMAs and the SDMA channels is user programmable.
Regardless of system configuration, if the IDMA is a bus master when a higher priority
SDMA channel needs to transfer over the bus, the SDMA will steal cycles from the IDMA
with no arbitration overhead.
When the QUICC is in slave mode (CPU32+ is disabled) the SDMA can steal cycles from
the IDMA with no arbitration overhead. See Section 4 Bus Operation for diagrams of bus
arbitration by an internal master in slave mode.
7.7.2 SDMA Registers
The SDMA channels have one configuration register; otherwise, they are controlled transparently to the user, through the configuration of the SCCs, SMCs, and SPI. The only useraccessible registers associated with the SDMA are the SDMA configuration register
(SDCR), SDMA address register (SDAR), a read-only register used for diagnostics in case
of an SDMA bus error, and the SDMA status register (SDSR).
7.7.2.1 SDMA CONFIGURATION REGISTER (SDCR). The 16-bit SDCR is used to configure all 14 SDMA channels. It is always readable and writable in the supervisor mode,
although writing the SDCR is not recommended unless the CP is disabled. SDCR is cleared
at reset.
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SDMA Channels
15
—
14
13
FRZ
12
11
10
—
9
SISM
8
7
—
6
5
SAID
4
3
2
—
1
INTE
0
INTB
Bits 15, 12, 11, 7, 2—Reserved
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FRZ1–FRZ0—Freeze
These bits determine the action to be taken when the FREEZE signal is asserted. The
SDMA negates BR and keeps it negated until FREEZE is negated or a reset occurs.
00 = The SDMA channels ignore the FREEZE signal.
01 = Reserved.
10 = The SDMA channels freeze on the next bus cycle.
11 = Reserved.
SISM—SDMA Interrupt Service Mask
These bits contain the interrupt service mask. When the interrupt service level on the IMB
is greater than the interrupt service mask, the SDMA relinquishes the bus and negates
the internal bus request to the IMB until the interrupt level service is less than or equal to
the interrupt service mask.
NOTE
This value should be programmed to 7 for typical user applications. This level gives the SDMA channels priority over all interrupt handlers.
SAID—SDMA Arbitration ID
These bits establish bus arbitration priority level among modules that have the capability
of becoming bus master. In the QUICC, the DRAM refresh controller, IDMAs, SDMAs, and
external bus masters can obtain bus mastership. The SDMA channel arbitration ID is determined by these bits. Zero is the lowest priority, and seven is the highest priority.
NOTE
This value should be programmed to 4 for typical user applications. This value should always be programmed to a value larger
than the arbitration IDs for the two IDMA channels. The user
must program this field to 7 when the QUICC is configured in
slave mode.
INTE—Interrupt Error
This bit enables the SBER status bit in the SDSR.
0 = A zero masks the interrupt generated by the corresponding bit in the SDSR. If a
bus error occurs while the SDMA is bus master, the channel does not generate an
interrupt to the QUICC interrupt controller. The SBER bit is still set in the SDSR.
1 = If a bus error occurs while the SDMA is bus master, the channel generates an interrupt to the QUICC interrupt controller and sets the SBER bit in the SDSR.
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SDMA Channels
NOTE
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An interrupt will only be generated if the SDMA bit is set in the
CP interrupt mask register.
INTB—Interrupt Breakpoint
This bit is the enable bit for the SBKP status bit in the SDSR.
0 = A zero masks the interrupt generated by the corresponding bit in the SDSR. When
a breakpoint is recognized while the SDMA is bus master, the channel does not
generate an interrupt to the QUICC interrupt controller. The SBKP bit is still set in
the SDSR.
1 = When a breakpoint is recognized while the SDMA is bus master, the channel generates an interrupt to the QUICC interrupt controller and sets the SBKP bit in the
SDSR.
NOTE
An interrupt will only be generated if the SDMA bit is set in the
CP interrupt mask register. The interrupt can suspend SDMA activity immediately if it is programmed to be at a higher level than
the SDMA channels. Alternatively, the interrupt can be processed after the SDMA transfer is complete.
7.7.2.2 SDMA STATUS REGISTER (SDSR). Shared by all 14 SDMA channels, the SDSR
is an 8-bit register used to report events recognized by the SDMA controller. On recognition
of an event, the SDMA sets its corresponding bit in the SDSR (regardless of the INTE, INTB,
and INTR bits in the SDCR). The SDSR is a memory-mapped register that may be read at
any time. A bit is reset by writing a one and is left unchanged by writing a zero. More than
one bit may be reset at a time, and the register is cleared by reset.
7
6
5
—
4
3
2
RINT
1
SBER
0
SBKP
Bits 7–3—Reserved
RINT—Reserved Interrupt
This status bit is reserved for factory testing. RINT is cleared by writing a one; writing a
zero has no effect.
SBER—SDMA Channel Bus Error
This bit indicates that the SDMA channel terminated with an error during a read or write
cycle. The SDMA bus error address can be read from the SDAR. SBER is cleared by writing a one; writing a zero has no effect.
SBKP—SDMA Breakpoint
This bit indicates that the breakpoint signal was asserted during an SDMA transfer. SBKP
is cleared by writing a one; writing a zero has no effect.
7.7.2.3 SDMA ADDRESS REGISTER (SDAR). The 32-bit read-only SDAR shows the system address that was accessed during an SDMA bus error. It is undefined at reset.
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7.8 SERIAL INTERFACE WITH TIME SLOT ASSIGNER
The SI connects the physical layer serial lines to the four SCCs and two SMCs (see Figure
7-19). In its simplest configuration, the SI allows the four SCCs and two SMCs to be connected their own set of individual pins. Each SCC or SMC that connects to the external world
in this way is said to connect to an NMSI. In the NMSI configuration, the SI provides a flexible
clocking assignment for each SCC and SMC from a bank of external clock pins and/or internal baud rate generators.
Freescale Semiconductor, Inc...
However, the main feature of the SI is its TSA. The TSA allows any combination of SCCs
and SMCs to multiplex their data together on either one or two TDM channels. TDM is used
in this manual as the generic term that describes any serial channel that is divided into channels separated by time. Common examples of TDMs are the T1 lines in Japan and the
United States and the CEPT lines in Europe.
Even if the TSA is not used in its intended capacity, it may still be used to generate complex
waveforms on four output pins. For instance, these pins can be programmed by the TSA to
implement stepper motor control or variable duty cycle and period control on these pins. Any
programmed configuration may be changed on the fly.
7.8.1 SI Key Features
The two major features of the SI are the TSA and the NMSI. The TSA contains the following
features:
• Can Connect to Two Independent TDM channels. Each TDM May Be One of the Following:
—T1 or CEPT Line
—PCM Highway
—ISDN Primary Rate
—ISDN Basic Rate—IDL
—ISDN Basic Rate—GCI
—User-Defined Interfaces
• Independent, Programmable Transmit and Receive Routing Paths
• Independent Transmit and Receive Frame Syncs Allowed
• Independent Transmit and Receive Clocks Allowed
• Selection of Rising/Falling Clock Edges for the Frame Sync and Data Bits
• Supports 1× and 2× Input Clocks (i.e., 1 or 2 Clocks per Data Bit)
• Selectable Delay (0–3 Bits) Between Frame Sync and Frame Start
• Four Programmable Strobe Outputs and Two (2×) Clock Output Pins
• 1- or 8-Bit Resolution in Routing, Masking, and Strobe Selection
• Supports Frames Up to 8192 Bits Long
• Internal Routing and Strobe Selection Can Be Dynamically Programmed
• Supports Automatic Echo and Loopback Mode for Each TDM
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IMB
R CLOCKS
TX/RX
TX/RX
T CLOCKS
MODE
REGISTER
COMMAND
REGISTER
STATUS
REGISTER
CLOCK
ROUTE
TO SMC1
TO SMC2
TO SCC1
TO SCC2
TO SCC3
MUX
MUX
MUX
MUX
MUX
TO SCC4
MUX
TDM A&B
STROBES
T CLOCKS
R SYNC
TIME SLOT
ASSIGNER
T SYNC
Freescale Semiconductor, Inc...
R CLOCKS
TX/RX
RAM
CONTROL
ROUTE
RAM
SMC1
PINS
TDM A&B
PINS
SMC2
PINS
SCC1
PINS
SCC2
PINS
SCC3
PINS
SCC4
PINS
NONMULTIPLEXED SERIAL INTERFACE (NMSI)
NOTE: NMSI clocking paths are not shown.
Figure 7-19. SI Block Diagram
The NMSI contains the following features:
• Each SCC and SMC Can Be Independently Programmed To Work with Its Own Set of
Pins in a Nonmultiplexed Manner.
• Each SCC Can Have Its Own Set of Modem Control Pins (TXD, RXD, TCLK, RCLK,
RTS, CTS, and CD).
• Each SMC Can Have Its Own Set of Four Pins (SMTXD, SMRXD, CLK, and SMSYN).
• Each SCC and SMC Can Derive Clocks Externally from a Bank of Eight Clock Pins
(CLK1–CLK8) or a Bank of Four Baud Rate Generators (BRG1–BRG4).
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7.8.2 TSA Overview
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The TSA implements both the internal route selection and time-division multiplexing for multiplexed serial channels. The TSA supports the serial bus rate and format for most standard
TDM buses, including the T1 and CEPT highways, the PCM highway, and the ISDN buses
in both basic and primary rates. The two popular ISDN basic rate buses, IDL and GCI (also
known as IOM-2), are supported. An additional level of flexibility is provided by the TSA in
that it supports two TDMs. It is therefore possible to simultaneously support one T1 line and
one CEPT line, one basic rate and one primary rate ISDN channel, etc.
TSA programming is completely independent of the protocol used by the SCC or SMC. For
instance, the fact that SCC2 may programmed for the HDLC protocol has no impact on the
programming of the TSA. The purpose of the TSA is to route the data from the specified pins
to the desired SCC or SMC at the correct time. It is the job of the SCC or SMC to handle the
data it receives.
In its simplest mode, the TSA identifies the frame using one sync pulse and one clock signal
provided externally by the user. This can be enhanced to allow independent routing of the
receive and transmit data on the TDM. Additionally, the definition of a time slot need not be
limited to 8 bits or even limited to a single contiguous position within the frame. Finally, the
user may provide separate receive and transmit syncs as well as receive and transmit
clocks. These various configurations are illustrated in Figure 7-20.
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Simplest TDM Example
QUICC
1 TDM SYNC
1 TDM CLOCK
TSA
SCC2
SMC1
TDM Tx
SLOT 3
SLOT N
TDM Rx
SLOT 3
SLOT N
SCC2
SMC1
TDM
More Complex TDM Example—Unique Routing
Freescale Semiconductor, Inc...
QUICC
1 TDM SYNC
1 TDM CLOCK
TSA
SCC2
TDM
TDM Tx
SMC1
SLOT 1 SLOT 2
TDM Rx
SLOT 3
SLOT N
SCC2
SMC1
Even More Complex TDM Example—Multiple Time Slots per Channel with Varying Sizes of Time Slots
QUICC
1 TDM SYNC
1 TDM CLOCK
SCC2
TSA
SMC1
SCC2
TDM
TDM Tx
TDM Rx
SCC2
SMC1
SCC2
NOTE: The two shaded areas of SCC2 Rx are received as one high-speed data stream by SCC2 and stored
together in the same data buffers.
Most Complex TDM Example—Totally Independent Rx and Tx
QUICC
TDM Tx SYNC
TDM Tx CLOCK
TSA
SCC2
TDM
SMC1
SCC2
TDM Tx
TDM Rx SYNC
TDM Rx CLOCK
TDM Rx
SCC2
SMC1
Figure 7-20. Various Configurations of a Single TDM Channel
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The TSA also allows two TDM channels to be supported simultaneously. Thus, in its most
flexible mode, the TSA can provide two separate TDM channels, each with an independent
receive and transmit routing assignment and independent sync pulse and clock inputs (see
Figure 7-21). Thus, the TSA can support four, independent, half-duplex TDM sources, two
in reception and two in transmission, using four sync inputs and four clock inputs.
TDMa Tx SYNC
TDMa Tx CLOCK
SCC2
SMC1
SCC2
Freescale Semiconductor, Inc...
TDMa Tx
TDMa Rx SYNC
QUICC
TDMa Rx CLOCK
TDMa Rx
TSA
TDMa
SCC3
SMC1
TDMb
TDMb Tx SYNC
TDMb Tx CLOCK
SCC3
SCC4
TDMb Tx
TDMb Rx SYNC
TDMb Rx CLOCK
TDMb Rx
SCC2
NOTE: SCCs may receive on one TDM and transmit on another (e.g., SCC2 and SCC3).
Figure 7-21. Dual TDM Channel Example
In addition to channel programming, the TSA supports up to four strobe outputs that may be
asserted on a bit basis or a byte basis. These strobes are completely independent from the
channel routing used by the SCCs and SMCs. They are useful for interfacing to other
devices that do not support the multiplexed interface or for enabling/disabling three-state I/
O buffers in a multi-transmitter architecture. (Note that open-drain programming on the
TXDx pins to support a multi-transmitter architecture is programmed in the parallel I/O
block.) These strobes can also be used for generating output waveforms to support such
applications as stepper motor control.
Most TSA programming is accomplished in two SI RAMs, each of size 64 × 16 bits. These
SI RAMs are directly accessible by the host processor in the internal register section of the
QUICC and are not associated with the dual-port RAM. One SI RAM is always used to pro-
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gram the transmit routing, and the other SI RAM is always used to program the receive routing. With the SI RAMs, the user can define the number of bits/bytes that are to be routed to
which SCC or SMC and the times the external strobes are to be asserted and negated. The
size of the SI RAM that is available for time-slot programming depends on the configuration.
If two TDM channels are selected, the SI RAM entries available per channel are reduced by
one-half. If on-the-fly changes are also allowed, the SI RAM entries are further reduced by
one-half. Even in a configuration with two TDM channels and on-the-fly changes allowed,
the SI RAM size is still sufficient to allow extensive time-slot programming flexibility. The
maximum frame length that can be supported in any configuration is 8192 bits.
The SI supports two testing modes: echo and loopback. Echo mode provides a return signal
from the physical interface by retransmitting the signal it has received. The physical interface
echo mode differs from the individual SCC echo mode in that it can operate on the entire
TDM signal rather than just on a particular SCC channel. Loopback mode causes the physical interface to receive the same signal it is transmitting. The SI loopback mode checks
more than the individual SCC loopback; it checks the SI and the internal channel routes.
The maximum clock that can be input to the TSA depends on the internal SyncCLK rate.
SyncCLK, which is generated in the QUICC clock synthesizer specifically for the SCCs,
SMCs, and TSA, defaults to the system frequency (for instance, 25 MHz). However, the
clock synthesizer in the SIM60 has an option to divide SyncCLK by 1, 4, 16, or 64 before it
leaves the clock synthesizer. Whatever the resulting frequency of SyncCLK, the maximum
external serial clock that may be an input to the TSA is SyncCLK/2.5.
The ability to reduce the frequency of SyncCLK before it ever leaves the clock synthesizer
is useful for two reasons. First, in a low-power mode, the TSA clocking could potentially be
a significant factor in overall QUICC power consumption. Thus, if the TSA does not need to
operate at high frequencies, the user may choose a lower frequency SyncCLK as the input
to the TSA. (In making this decision, the user must also consider the needs of the other
SCCs and SMCs not connected to the TSA and select a sufficiently high SyncCLK value for
their use.) Second, the user may wish to dynamically change the general system clock frequency in the clock synthesizer (slow-go mode) while still having the TSA run at the original
frequency. The SyncCLK also allows this configuration.
If an SCC or SMC is operating with the NMSI, then the serial clock rate may be slightly
faster, at a value not to exceed SyncCLK/2.
7.8.3 Enabling Connections to the TSA
Each SCC and SMC may be independently enabled to be connected to the TSA (see Figure
7-22). Note that separate bits enable whether each SCC or SMC is connected to the TSA
or to its own set of external pins. Additionally, the two TDM interfaces must be enabled to
be connected to the TSA.
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ENa = 1 TO ENABLE
TIME SLOT
ASSIGNER
CONTROL LOGIC
TDMa PINS
EN
TDMb PINS
SC1 = 1
SI RAM
EN
SC2 = 1
SC1=0
SC2=0
SC3=0
SC4 = 1
SCC 3
SMC 1
SMC 2
SMC1=0
SMC2 = 1
SCC 4
SC4=0
SMC1 = 1
Freescale Semiconductor, Inc...
SCC 2
ENb = 1 TO ENABLE
SC3 = 1
SCC 1
MULTIPLEXED
I/F
SMC2=0
SCC1 PINS
SCC2 PINS
SCC3 PINS
NONMULTIPLEXED
I/F
SCC4 PINS
SMC1 PINS
SMC2 PINS
NOTES:
1. The ENx bits are located in SIGMR.
2. The SCx bits are located in SICR.
3. The SMCx bits are located in SIMODE.
4. The clocking paths are not shown for the nonmultiplexed I/F (see Figure 7-35 for more details).
Figure 7-22. Enabling Connections Through the SI
Once the connections are made, the exact routing decisions are made in the SI RAM, as
described in the following paragraphs.
7.8.4 SI RAM
The SI has two 64 × 16 static RAMs used to control the routing of the TDM channels to the
SCCs and SMCs. The RAMs are uninitialized after power-on. For proper operation, the host
should program the RAMs before enabling the multiplexed channels, or undesired results
may occur.
The RAM consists of 16-bit entries that are used to define the routing control. Each entry
can control from 1 to 16 bits or from 1 to 16 bytes at a time as determined in the entry. In
addition to the routing, up to four strobe pins may be asserted according to the programming
of the RAM. The strobes are active high.
The two SI RAMs can be configured in four different ways to support various TDM channels.
The four possible cases are discussed in the following paragraphs.
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7.8.4.1 ONE MULTIPLEXED CHANNEL WITH STATIC FRAMES. With this configuration
(see Figure 7-23), there are 64 entries in the SI RAM for transmit data and strobe routing
and 64 entries for receive data and strobe routing. This configuration should be chosen
when only one TDM is required and the routing on that TDM does not need to be changed
dynamically.
RDM = 00
ONE CHANNEL WITH INDEPENDENT
Rx AND Tx ROUTE
FRAMING SIGNALS
Freescale Semiconductor, Inc...
SI RAM ADDRESS: 0
(16-BITS WIDE)
L1RCLKa
L1RSYNCa
64 ENTRIES
RXa
ROUTE
127
128
L1TCLKa
L1TSYNCa
64 ENTRIES
TXa
ROUTE
256
Figure 7-23. SI RAM: One TDM with Static Frames
7.8.4.2 ONE MULTIPLEXED CHANNEL WITH DYNAMIC FRAMES. With this configuration (see Figure 7-24), there is one multiplexed channel. The channel has 32 entries for
transmit data and strobe routing and 32 entries for receive data and strobe routing. In each
RAM, one of the partitions is the current-route RAM, and the other is a shadow RAM used
to allow the user to change the serial routing. After programming the shadow RAM, the user
sets the CSRx bit of the associated channel in the SI CR. When the next frame sync arrives,
the SI will automatically exchange the current-route RAM for the shadow RAM. Refer to
7.8.4.7 SI RAM Dynamic Changes for more details on how to dynamically change the channel's route. This configuration should be chosen when only one TDM is required but the routing on that TDM may need to be changed dynamically.
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RDM = 01
ONE CHANNEL WITH SHADOW RAM
FOR DYNAMIC ROUTE CHANGE
FRAMING SIGNALS
SI RAM ADDRESS: 0
(16-BITS WIDE)
64
L1RCLKa
L1RSYNCa
32 ENTRIES
RXa
ROUTE
Freescale Semiconductor, Inc...
63
128
127
192
L1TCLKa
L1TSYNCa
32 ENTRIES
TXa
ROUTE
191
255
Figure 7-24. SI RAM: One TDM with Dynamic Frames
7.8.4.3 TWO MULTIPLEXED CHANNELS WITH STATIC FRAMES. With this configuration (see Figure 7-25), there are 32 entries for transmit data and strobe routing and 32
entries for receive data and strobe routing. This configuration should be chosen when two
TDMs are required and the routing on that TDM does not need to be changed dynamically.
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RDM = 10
TWO CHANNELS WITH INDEPENDENT
RX AND TX ROUTE
FRAMING SIGNALS
L1RCLKa
SI RAM ADDRESS: 0
(16-BITS WIDE)
FRAMING SIGNALS
64
32 ENTRIES
RXa
ROUTE
63
128
Freescale Semiconductor, Inc...
L1RCLKb
L1RSYNCb
L1RSYNCa
32 ENTRIES
RXb
ROUTE
127
L1TCLKa
L1TCLKb
L1TSYNCb
192
L1TSYNCa
32 ENTRIES
TXa
ROUTE
191
32 ENTRIES
TXb
ROUTE
255
Figure 7-25. SI RAM: Two TDMs with Static Frames
7.8.4.4 TWO MULTIPLEXED CHANNELS WITH DYNAMIC FRAMES. With this configuration (see Figure 7-26), there are two multiplexed channels. Each channel has 16 entries
for transmit data and strobe routing and 16 entries for receive data and strobe routing. In
each RAM, one of the partitions is the current-route RAM, and the other is a shadow RAM
used to allow the user to change the serial routing. After programming the shadow RAM, the
user sets the CSRx bit of the associated channel in the SI CR. When the next frame sync
arrives, the SI will automatically exchange the current-route RAM for the shadow RAM.
Refer to 7.8.4.7 SI RAM Dynamic Changes for more details on how to dynamically change
the channel's route. This configuration should be chosen when two TDMs are required and
the routing on each TDM may need to be changed dynamically.
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RDM = 11
TWO CHANNELS WITH SHADOW RAM
FOR DYNAMIC ROUTE CHANGE
FRAMING SIGNALS
SI RAM ADDRESS: 0
(16-BITS WIDE)
32
96
L1RCLKb
L1RCLKa
L1RSYNCa
16 ENTRIES
RXa
ROUTE
30
128
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FRAMING SIGNALS
64
94
192
62
160
126
224
L1TCLKa
L1TSYNCa
16 ENTRIES
TXa
ROUTE
158
L1RSYNCb
16 ENTRIES
RXb
ROUTE
L1TCLKb
L1TSYNCb
16 ENTRIES
TXb
ROUTE
222
190
254
Figure 7-26. Two TDMs with Dynamic Frames
7.8.4.5 PROGRAMMING SI RAM ENTRIES. The programming of each word within the
RAM determines the routing of the serial bits (or bit groups) and the assertion of strobe outputs. The RAM programming codes are as follows:
15
LOOP1
14
SWTR
13
12
11
SSEL1–SSEL4
10
9
—
8
7
CSEL
6
5
4
3
CNT
2
1
BYT
0
LST
NOTES:
1: Only available on REV C mask or later. NOT Available on REV A or B.
Rev A mask is C63T
Rev B mask are C69T, and F35G
Current Rev C mask are E63C, E68C and F15W
Bit 15 LOOP (Loop back this time slot)
0 = normal mode
1 = loop back mode for this time slot
SWTR—Switch Tx and Rx
The SWTR bit is only valid in the receive route RAM and is ignored in the transmit route
RAM. This bit affects the operation of both the L1RXD and L1TXD pins
The SWTR bit would only be set in a special situation where the user desires to receive
data from a transmit pin and transmit data on a receive pin. For instance, consider the situation where devices A and B are connected to the same TDM, each with different time
slots. Normally, there is no opportunity for stations A and B to communicate with each other directly over the TDM, since they both receive the same TDM receive data and transmit
on the same TDM transmit signal (see Figure 7-27).
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TDM RECEIVE DATA
TDM TRANSMIT DATA
RX
TX
STATION A
RX
TX
STATION B
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Figure 7-27. Using the SWTR Feature
The SWTR option gives station B the opportunity to listen to transmissions from station A
and to transmit data to Station A. To do this, station B would set the SWTR bit in its receive
route RAM. For this entry, receive data is taken from the L1TXD pin and data is transmitted on the L1RXD pin. If the user only wants to listen to Station A’s transmissions and not
transmit data on L1RXD, then the CSEL bits in the corresponding transmit route RAM entry should be cleared to prevent transmission on the L1RXD pin.
It is also possible for station B to transmit data to station A by setting the SWTR bit of the
entry in its receive route RAM. Data is transmitted on the L1RXD pin rather than the
L1TXD pin, according to the transmit route RAM. Note that this configuration could cause
collisions with other data on the L1RXD pin unless care is taken to choose an available
(quiet) time slot. If the user only wants to transmit on L1RXD and not receive data on
L1TXD, then the CSEL bits in the receive route RAM should be cleared to prevent reception of data on L1TXD.
NOTE
If the transmit and receive sections of the TDM do not use a single clock source, this feature will give erratic results.
0 = Normal operation of the L1TXD and L1RXD pins.
1 = Data is transmitted on the L1RXD pin and is received from the L1TXD pin for the
duration of this entry.
SSEL1–SSEL4—Strobe Select
The four strobes (L1STA1, L1STA2, L1STB1, and L1STB2) may be assigned to the receive RAM and asserted/negated with L1RCLKa or L1RCLKb or assigned to the transmit
RAM and asserted/negated with L1TCLKa or L1TCLKb. Each bit corresponds to the value
the strobe should have during this bit/byte group. Multiple strobes can be asserted simultaneously, if desired.
If a strobe is configured to be asserted in two consecutive SI RAM entries, then it will remain continuously asserted during the processing of both SI RAM entries. If a strobe is
asserted on the last entry in the table, the strobe will be negated after the processing of
that last entry is complete.
Bit 9—Reserved
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NOTES
Each strobe is changed with the corresponding RAM clock and
will be output only if the corresponding parallel I/O is configured
as a dedicated pin.
Freescale Semiconductor, Inc...
If a strobe is programmed to be asserted in more than one set of
entries (e.g., the SI Rx route for the TDMa entries and the SI Tx
route for TDMb entries both select the same strobe), then the assertion of the strobe corresponds to the logical OR of all possible
sources. This use of the strobes is not useful for most applications. It is recommended that a given strobe be selected in only
one set of SI RAM entries.
CSEL—Channel Select
000 = The bit/byte group is not supported within the QUICC. The transmit data pin is
three-stated, and the receive data pin is ignored.
001 = The bit/byte group is routed to SCC1.
010 = The bit/byte group is routed to SCC2.
011 = The bit/byte group is routed to SCC3.
100 = The bit/byte group is routed to SCC4.
101 = The bit/byte group is routed to SMC1.
110 = The bit/byte group is routed to SMC2.
111 = The bit/byte group is not supported within the QUICC. This code is also used in
SCIT mode as the D channel grant (refer to 7.8.7.2.2 SCIT Programming.)
CNT—Count
This value indicates the number of bits/bytes (according to the BYT bit) that the routing
and strobe select of this entry controls. If CNT = 0000, then 1 bit/byte is chosen; if
CNT = 1111, then 16 bits/bytes are selected.
BYT—Byte Resolution
0 = Bit resolution—the CNT value indicates the number of bits in this group.
1 = Byte resolution—the CNT value indicates the number of bytes in this group.
LST—Last Entry in the RAM
Whenever the SI RAM is used, this bit must be set in one of the Tx or Rx entries of each
group that is used. Even if all entries of a group are used, this bit must still be set in the
last entry.
0 = This is not the last entry in this section of the route RAM.
1 = This is the last entry in this RAM. After this entry, the SI will wait for the sync signal
to start the next frame.
NOTE
If a second sync signal is received before the end of a frame (as
defined by the last SI RAM entry), an error occurs. The SI will terminate SI RAM processing, and cease transmitting or receiving
data until a third sync signal is received.
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7.8.4.6 SI RAM PROGRAMMING EXAMPLE. This example shows how to program the
RAM to support the 10-bit IDL bus (see Figure 7-33 for the 10-bit IDL bus format).
In this example, the TSA supports the B1 channel with SCC2, the D channel with SCC1, the
first 4 bits of the B2 channel with an external device (using a strobe to enable the external
device), and the last 4 bits of B2 with SCC4. Additionally, the TSA will mark the D channel
with another strobe signal.
First, divide the frame from the start (i.e., the sync) to the end of the frame according to the
support that is required:
1. 8 bits (B1)—SCC2
2. 1 bit (D)—SCC1 + strobe1
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3. 1 bit—no support
4. 4 bits (B2)—strobe2
5. 4 bits (B2)—SCC4
6. 1 bit (D)—SCC1 + strobe1
Each of these six divisions can be supported by just one SI RAM entry. Thus, a total of only
six entries is needed in the SI RAM:
Entry
RAM WORD
No.
SWTR
SSEL
CSEL
CNT
BYT
LST
description
1
0
0000
010
0000
1
0
8 Bits SCC2
2
0
0001
001
0000
0
0
1 Bit SCC1 Strobe1
3
0
0000
000
0000
0
0
1 Bit No Support
4
0
0010
000
0011
0
0
4 Bits Strobe2
5
0
0000
100
0011
0
0
4 Bits SCC4
6
0
0001
001
0000
0
1
1 Bit SCC1 Strobe1
NOTE
Since IDL requires the same routing for both receive and transmit, an exact duplicate of the above entries should be written to
both the receive and transmit sections of the SI RAM. Then the
CRTx bit in the SIMODE register can be used to instruct the SI
RAM to use the same clock and sync to simultaneously control
both sets of SI RAM entries.
7.8.4.7 SI RAM DYNAMIC CHANGES. The SI RAM, described in 7.8.4.5 Programming SI
RAM Entries, has four operating modes:
1. One TDM with a static routing definition. SI RAM divided into two parts (Rx and Tx).
2. One TDM allowing dynamic changes. SI RAM divided into four parts.
3. Two TDMs with static routing definition. SI RAM divided into four parts.
4. Two TDMs allowing dynamic changes. SI RAM divided into eight parts.
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Dynamic changes mean that the routing definition of a TDM can be modified while the
SCCs/SMCs are connected to the TDM. With fixed routing, a change to the routing requires
that all SCCs/SMCs connected to the TSA be disabled, the SI routing be modified, and then
all SCCs/SMCs connected to the TSA be reenabled before the new routing takes effect.
Freescale Semiconductor, Inc...
Dynamic changes divide portions of the SI RAM into current-route RAM and shadow RAM.
Once the current-route RAM is programmed, the TSA and SI channels can be enabled, and
TSA operation can begin. When the user decides that a change in routing is required, the
user programs the shadow RAM with the new route and sets the CSRx bit in the SI CR. As
a result, the SI will exchange the shadow RAM and the current-route RAM as soon as the
corresponding sync arrives and will reset the CSRx bit to signify that the operation is complete. At this time, the user may change the routing again. Note that the original currentroute RAM is now the shadow RAM and vice versa. Figure 7-28 illustrates an example of
the shadow RAM exchange process.
If one TDM with dynamic changes is programmed, the initial current-route RAM addresses
in the SI RAM are as follows:
• 0–63 RXa Route
• 128–191TXa Route
and the shadow RAMs are at addresses:
• 64–127 RXa Route
• 192–255TXa Route
If two TDMs with dynamic changes are programmed, the initial current-route RAM addresses in the SI RAM are as follows:
• 0–31 RXa Route
• 64–93 RXb Route
• 128–159TXa Route
• 192–223TXb Route
and the shadow RAMs are at addresses:
• 32–63 RXa Route
• 96–93 RXb Route
• 160–191TXa Route
• 224–255TXb Route
The user can read any RAM at any time, but for proper operation of the SI, the user must
not attempt to write the current-route RAM. The user can read the SI status register (SISTR)
to find which part of the RAM is the current-route RAM.
Beyond knowing which RAM is the current-route RAM, the user may wish to know which
entry that the TSA is currently using within the current-route RAM. This information is provided in the SI RAM pointer register (SIRP). The user may also externally connect one of
the four strobes to an interrupt pin to generate an interrupt on a particular SI RAM entry starting or ending execution by the TSA.
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RAM ADDRESS: 0
1) INITIAL STATE
THE TSA USES THE FIRST PART OF
THE RAM, AND THE SHADOW IS
THE SECOND PART OF THE RAM.
CSRxn = 0
FRAMING SIGNALS:
CSRRa = 0
CSRTa = 0
CSRRb = 0
CSRTb = 0
Freescale Semiconductor, Inc...
16 TXa
SHADOW
CSRRa = 1
CSRTa = 1
CSRRb = 1
CSRTb = 1
RAM ADDRESS: 128
159 160
0
RAM ADDRESS:
191 192
16 TXa
SHADOW
16 RXb
SHADOW
223 224
16 TXb
ROUTE
63 64
16 TXb
SHADOW
95 96
127
16 RXb
ROUTE
16 RXb
SHADOW
16 RXa
ROUTE
L1RCLKa
L1RSYNCa
FRAMING SIGNALS:
255
L1TCLKb
L1TSYNCb
31 32
16 RXa
SHADOW
THE SI EXCHANGES BETWEEN THE
SHADOW RAM AND THE CURRENTROUTE RAM AND RESETS CSRxn.
127
95 96
16 RXb
ROUTE
L1TCLKa
L1TSYNCa
FRAMING SIGNALS:
16 TXb
SHADOW
L1RCLKb
L1RSYNCb
16 TXa
ROUTE
1) EXCHANGE
63 64
L1RCLKa
L1RSYNCa
FRAMING SIGNALS:
255
L1TCLKb
L1TSYNCb
16 RXa
SHADOW
16 RXa
ROUTE
THE USER PROGRAMS THE
SHADOW RAM FOR THE NEW
Rx AND Tx ROUTE AND SETS CSRxn.
224
16 TXb
ROUTE
31 32
RAM ADDRESS: 0
223
191 192
L1TCLKa
L1TSYNCa
FRAMING SIGNALS:
127
16 RXb
SHADOW
L1RCLKb
L1RSYNCb
159 160
16 TXa
ROUTE
95 96
16 RXb
ROUTE
16 RXa
SHADOW
L1RCLKa
L1RSYNCa
RAM ADDRESS: 128
1) PROGRAMMING
63 64
31 32
16 RXa
ROUTE
L1RCLKb
L1RSYNCb
CSRRa = 0
RAM ADDRESS: 128
CSRTa = 0
159 160
16 TXa
SHADOW
CSRRb = 0
CSRTb = 0
191 192
16 TXa
ROUTE
16 TXb
SHADOW
L1TCLKa
L1TSYNCa
FRAMING SIGNALS:
255
223 224
16 TXb
ROUTE
L1TCLKb
L1TSYNCb
Figure 7-28. SI RAM Dynamic Changes
7.8.5 SI Registers
The following paragraphs describe the SI registers.
7.8.5.1 SI GLOBAL MODE REGISTER (SIGMR). The 8-bit SIGMR defines the RAM division modes. The SIGMR appears to the user as a memory-mapped, read-write register and
is cleared at reset.
7
6
5
—
4
3
ENb
2
ENa
1
0
RDM1–RDM0
Bits 7–4—Reserved
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ENb—Enable Channel b
0 = Channel b is disabled. The SI RAMs and TDM routing are in a state of reset, but
all other SI functions still operate.
1 = The SI is enabled.
Freescale Semiconductor, Inc...
ENa—Enable Channel a
0 = Channel a is disabled. The SI RAMs and TDM routing are in a state of reset, but
all other SI functions still operate.
1 = The SI is enabled.
RDM1–RDM0—RAM Division Mode
These bits define the RAM division mode and the number of multiplexed channels supported in the SI.
00 = The SI supports one TDM channel with 64 entries for receive routing and 64 entries for transmit routing.
01 = The SI supports one TDM channel with 32 entries for receive routing and 32 entries for transmit routing. There are an additional 32 shadow entries for the receive
routing and 32 shadow entries for transmit routing that may be used to dynamically change the routing.
10 = The SI supports two TDM channels with 32 entries for the receive routing and 32
entries for transmit routing for each of the two TDMs.
11 = The SI supports two TDM channels with 16 entries for receive routing and 16 entries for transmit routing for each channel. There are an additional 16 shadow entries for receive routing and 16 shadow entries for transmit routing that may be
used to dynamically change the channel routing.
NOTE
TSAa must be used in RDM1—0 if 00 or 01 setting is desired.
7.8.5.2 SI MODE REGISTER (SIMODE). The 32-bit SIMODE defines the SI operation
modes. This register allows the user (in conjunction with the SI RAM) to support any or all
of the ISDN channels independently when in IDL or GCI (IOM-2) mode. Any extra SCC
channel can then be used for other purposes in NMSI mode. SIMODE appears to the user
as a memory-mapped, read-write register and is cleared at reset.
31
SMC2
15
SMC1
30
14
29
SMC2CS
13
SMC1CS
28
27
26
25
SDMb
12
11
10
SDMa
24
RFSDb
9
8
RFSDa
23
DSCb
7
DSCa
22
CRTb
6
CRTa
21
STZb
5
STZa
20
CEb
4
CEa
19
FEb
3
FEa
18
GMb
2
GMa
17
16
TFSDb
1
0
TFSDa
SMCx—SMCx Connection
0 = NMSI mode. The clock source is determined by the SMCxCS bit, and the data
comes from a dedicated pin (SMTXD1 and SMRXD1 for SMC1 or SMTXD2 and
SMRXD2 for SMC2) in the NMSI.
1 = SMCx is connected to the multiplexed SI (TDM channel).
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SMC2CS—SMC2 Clock Source (NMSI mode)
SMC2 can take its clocks from one of the baud rate generators or one of four pins from
the bank of clocks. The SMC2 transmit and receive clocks must be the same when it is
connected to the NMSI.
000 = SMC2 transmit and receive clocks are BRG1.
001 = SMC2 transmit and receive clocks are BRG2.
010 = SMC2 transmit and receive clocks are BRG3.
011 = SMC2 transmit and receive clocks are BRG4.
100 = SMC2 transmit and receive clocks are CLK5.
101 = SMC2 transmit and receive clocks are CLK6.
110 = SMC2 transmit and receive clocks are CLK7.
111 = SMC2 transmit and receive clocks are CLK8.
SMC1CS—SMC1 Clock Source (NMSI mode)
SMC1 can take its clocks from one of the baud rate generators or one of four pins from
the bank of clocks. The SMC1 transmit and receive clocks must be the same when it is
connected to the NMSI.
000 = SMC1 transmit and receive clocks are BRG1.
001 = SMC1 transmit and receive clocks are BRG2.
010 = SMC1 transmit and receive clocks are BRG3.
011 = SMC1 transmit and receive clocks are BRG4.
100 = SMC1 transmit and receive clocks are CLK1.
101 = SMC1 transmit and receive clocks are CLK2.
110 = SMC1 transmit and receive clocks are CLK3.
111 = SMC1 transmit and receive clocks are CLK4.
SDMx—SI Diagnostic Mode for TDM A or B
00 = Normal operation.
01 = Automatic Echo. In this mode, the channel_x transmitter automatically retransmits
the TDM received data on a bit-by-bit basis. The receive section operates normally, but the transmit section can only retransmit received data. In this mode, the
L1GRx line is ignored.
10 = Internal Loopback. In this mode, the TDM transmitter output is internally connected to the TDM receiver input (L1TXDx is connected to L1RXDx). The receiver and
transmitter operate normally. The data appears on the L1TXDx pin. In this mode,
the L1RQx line is asserted normally. The L1GRx line is ignored.
11 = Loopback Control. In this mode, the TDM transmitter output is internally connected to the TDM receiver input (L1TXDx is connected to L1RXDx). The transmitter
output (L1TXDx) and the L1RQx pin will be inactive. This mode is used to accomplish loopback testing of the entire TDM without affecting the external serial lines.
NOTE
In modes 01,10, and 11, the receive and the transmit clocks
should be identical.
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RFSDx—Receive Frame Sync Delay for TDM A or B
These two bits determine the number of clock delays between the receive sync and the
first bit of the receive frame. Even if the CRTx bit is set, these bits do not control the delay
for the transmit frame.
00 = No bit delay (The first bit of the frame is transmitted/received on the same clock
as the sync; use for GCI.)
01 = 1-bit delay (Use for IDL.)
10 = 2-bit delay
11 = 3-bit delay
Refer to Figure 7-29 and Figure 7-30 for an example of the use of these bits.
DSCx—Double-Speed Clock for TDM A or B
Some TDMs such as GCI define the input clock to be 2× faster than the data rate. This bit
controls this option.
0 = The channel clock (L1RCLKx and/or L1TCLKx) is equal to the data clock. (Use for
IDL and most TDM formats.)
1 = The channel clock rate is twice the data rate. (Use for GCI.)
CRTx—Common Receive and Transmit Pins for TDM A or B
This bit is useful when the transmit and receive sections of a given TDM use the same
clock and sync signals. In this mode, L1TCLKx and L1TSYNCx pins can be used as general-purpose I/O pins.
0 = Separate pins. The receive section of this TDM uses L1RCLKx and L1RSYNCx
pins for framing, and the transmit section uses L1TCLKx and L1TSYNCx for framing.
1 = Common pins. The receive and transmit sections of this TDM use L1RCLKx as
clock pin of channel x and L1RSYNCx as the receive and transmit sync pin. (Use
for IDL and GCI.)
STZx—Set L1TXDx to Zero for TDM A or B
0 = Normal operation.
1 = L1TXDx is set to zero until serial clocks are available, which is useful for GCI activation. Refer to 7.8.7.1 SI GCI Activation/Deactivation Procedure.
CEx—Clock Edge for TDM A or B
When DSCx =0
0 = The data is transmitted on the rising edge of the clock and received on the falling
edge. (Use for IDL and GCI.)
1 = The data is transmitted on the falling edge of the clock and received on the rising
edge.
When DSCx = 1
0 = The data is transmitted on the rising edge of the clock and received on the rising
edge. (Use for IDL and GCI.)
1 = The data is transmitted on the falling edge of the clock and received on the falling
edge.
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FEx—Frame Sync Edge for TDM A or B
The L1RSYNCx and L1TSYNCx pulses are sampled with the falling/rising edge of the
channel clock according to this bit.
0 = Falling edge (Use for IDL and GCI.)
1 = Rising edge
GMx—Grant Mode for TDM A or B
0 = GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is internally supported. The grant is one bit from the receive channel. This bit is marked
by programming the channel select bits of the SI RAM with 111 to assert an internal
strobe on it. Refer to 7.8.7.2.2 SCIT Programming.
1 = IDL mode. A GRANT mechanism is supported if the corresponding GR1–GR4 bits
in the SIMODE register are set. The grant is a sample of the L1GRx pin while
L1TSYNCx is asserted. This GRANT mechanism implies the IDL access controls
for transmission on the D channel. Refer to 7.8.6.2 IDL Interface Programming.
TFSDx—Transmit Frame Sync Delay for TDM A or B
These two bits determine the number of clock delays between the transmit sync and the
first bit of the transmit frame. If the CRTx bit is set (recommended with IDL or GCI), then
the transmit sync is not used, and these bits are ignored.
00 = No bit delay (The first bit of the frame is transmitted/received on the same clock
as the sync.)
01 = 1 bit delay
10 = 2 bit delay
11 = 3 bit delay
Refer to Figure 7-29 and Figure 7-30 for an example of the use of these bits.
L1CLK
(CE = 0)
L1SYNC
(FE = 1)
END OF FRAME
DATA
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 0
ONE CLOCK DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
Figure 7-29. One Clock Delay from Sync to Data (RFSD = 01)
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L1CLK
(CE = 0)
L1SYNC
(FE = 1)
DATA
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 0
BIT 1
BIT 2
NO DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
Freescale Semiconductor, Inc...
Figure 7-30. No Delay from Sync to Data (RFSD = 00)
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SFD=1
CE=1
Freescale Semiconductor, Inc...
L1CLK
L1SYNC
(FE=0)
L1SYNC
(FE=1)
L1TXD (bit 0)
L1ST (on bit 0)
L1ST driven from clock hi for both FE settings
Rx sampled here
CE=0
L1CLK
L1SYNC
(FE=0)
L1SYNC
(FE=1)
L1TXD (bit 0)
L1ST (on bit 0)
L1ST is driven from clock lo in both
the FE settings
Rx sampled here
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SFD=0
L1CLK
L1SYNC
(FE=0)
L1TXD (bit 0)
Freescale Semiconductor, Inc...
L1ST (on bit 0)
The L1ST is driven from sync.
Data is driven from clock lo.
Rx sampled here
(FE=0)
L1SYNC
L1TXD (bit 0)
L1ST is driven from clock hi
L1ST (on bit 0)
(FE=1)
L1SYNC
L1TXD (bit 0)
L1ST (on bit 0)
Both data bit 0 and L1ST are
driven from sync
Rx sampled here
(FE=1)
L1SYNC
L1TXD (bit 0)
L1ST and data bit 0
is driven from clock lo
L1ST (on bit 0)
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CE=0
SFD=0
L1CLK
(FE=1)
L1SYNC
L1TXD (bit 0)
Freescale Semiconductor, Inc...
L1ST (on bit 0)
L1ST driven from sync
Data driven from clock hi.
Rx sampled here
(FE=1)
L1SYNC
L1TXD (bit 0)
L1ST (on bit 0)
L1ST driven from clock lo
(FE=0)
L1SYNC
L1TXD (bit 0)
L1ST (on bit 0)
Both the data and L1ST from sync
when asserted during clock hi
L1SYNC
(FE=0)
L1TXD (bit 0)
L1ST (on bit 0)
MOTOROLA
Both the Data and L1ST from the clock
when asserted during clock lo
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7.8.5.3 SI CLOCK ROUTE REGISTER (SICR). The 32-bit SICR is used to define the SCC
clock sources. The clock source can be one of the four baud rate generators or an input from
a bank of clock pins. The SICR appears to the user as a memory-mapped, read-write register and is cleared at reset.
Freescale Semiconductor, Inc...
31
GR4
15
GR2
30
SC4
14
SC2
29
13
28
R4CS
12
R2CS
27
26
11
10
25
T4CS
9
T2CS
24
8
23
GR3
7
GR1
22
SC3
6
SC1
21
5
20
R3CS
4
R1CS
19
18
3
2
17
T3CS
1
T1CS
16
0
GRx—Grant Support of SCCx
0 = SCCx transmitter does not support the grant mechanism. The grant is always asserted internally.
1 = SCCx transmitter supports the grant mechanism as determined by the GMx bit of
its channel.
SCx—SCCx Connection
0 = SCCx is not connected to the multiplexed SI but is either connected directly to the
NMSIx pins or is not used. The choice of general-purpose I/O port pins versus
SCCn pins is made in the parallel I/O control register.
1 = SCCx is connected to the multiplexed SI. The NMSIx receive pins are available for
other purposes.
RxCS—Receive Clock Source for SCCx
These bits are ignored when the SCCx is connected to the TSA (SCx = 1).
000 = SCCx receive clock is BRG1.
001 = SCCx receive clock is BRG2.
010 = SCCx receive clock is BRG3.
011 = SCCx receive clock is BRG4.
100 = SCCx receive clock for x = 1,2 is CLK1 and for x = 3,4 is CLK5.
101 = SCCx receive clock for x = 1,2 is CLK2 and for x = 3,4 is CLK6.
110 = SCCx receive clock for x = 1,2 is CLK3 and for x = 3,4 is CLK7.
111 = SCCx receive clock for x = 1,2 is CLK4 and for x = 3,4 is CLK8.
TxCS—Transmit Clock Source for SCCx
These bits are ignored when SCCx is connected to the TSA (SCx = 1).
000 = SCCx transmit clock is BRG1.
001 = SCCx transmit clock is BRG2.
010 = SCCx transmit clock is BRG3.
011 = SCCx transmit clock is BRG4.
100 = SCCx transmit clock for x = 1,2 is CLK1 and for x = 3,4 is CLK5.
101 = SCCx transmit clock for x = 1,2 is CLK2 and for x = 3,4 is CLK6.
110 = SCCx transmit clock for x = 1,2 is CLK3 and for x = 3,4 is CLK7.
111 = SCCx transmit clock for x = 1,2 is CLK4 and for x = 3,4 is CLK8.
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7.8.5.4 SI COMMAND REGISTER (SICMR). The 8-bit SICMR allows the user to dynamically program the SI RAM. For more information about dynamic programming, refer to
7.8.4.7 SI RAM Dynamic Changes
The contents of this register are valid only in the RAM division mode (RDM1–RDM0 bits in
SIGMR equal 01 or 11). This register is cleared at reset.
Freescale Semiconductor, Inc...
7
CSRRa
6
CSRTa
5
CSRRb
4
CSRTb
3
2
1
0
—
CSRRx—Change Shadow RAM for TDM A or B Receiver
When set, this bit will cause the SI receiver to replace the current route with the shadow
RAM. The bit is set by the user and cleared by the SI.
0 = The receiver shadow RAM is not valid. The user can write into the shadow RAM to
program a new routing.
1 = The receiver shadow RAM is valid. The SI will exchange between the RAMs and
take the new receive routing from the receiver shadow RAM. This bit is cleared as
soon as the switch has completed.
CSRTx—Change Shadow RAM for TDM A or B Transmitter
When set, this bit will cause the SI transmitter to replace the current route with the shadow
RAM. The bit is set by the user and cleared by the SI.
0 = The transmitter shadow RAM is not valid. The user can write into the shadow RAM
to program a new routing.
1 = The transmitter shadow RAM is valid. The SI will exchange between the RAMs and
take the new transmitter routing from the receiver shadow RAM. This bit is cleared
as soon as the switch has completed.
Bits 3–0—Reserved
These bits should be set to zero by the user.
7.8.5.5 SI STATUS REGISTER (SISTR). The 8-bit SISTR indicates to the user which part
of the SI RAM is the current-route RAM. The value of this register is valid only when the corresponding bit in the SIGMR is clear. This register is cleared at reset.
CRORa—Current Route of TDMa Receiver
7
CRORa
6
CROTa
5
CRORb
4
CROTb
3
2
1
0
—
0 = The current-route receiver RAM is in address:
0–63 when the SI supports one TDM (RDM = 01)
0–31 when the SI supports two TDMs (RDM = 11)
1 = The current route receiver RAM is in address:
64–127 when the SI supports one TDM (RDM = 01)
32–63 when the SI supports two TDMs (RDM = 11)
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CROTa—Current Route of TDMa Transmitter
0 = The current-route transmitter RAM is in address:
128–191 when the SI supports one TDM (RDM = 01).
128–159 when the SI supports two TDMs (RDM = 11).
1 = The current-route transmitter RAM is in address:
192–255 when the SI supports one TDM (RDM = 01).
160–191 when the SI supports two TDMs (RDM = 11).
Freescale Semiconductor, Inc...
CRORb—Current Route of TDMb Receiver
This bit is valid only in the RAM division mode (RDM bits in the SIGMR equal 11).
0 = The current-route receiver RAM is in address 64–95.
1 = The current-route receiver RAM is in address 96–127.
CROTb—Current Route of TDMb Transmitter
This bit is valid only in the RAM division mode (RDM bits in the SIGMR equal 11).
0 = The current-route transmitter RAM is in address 192–223.
1 = The current-route transmitter RAM is in address 224–255.
Bits 3–0—Reserved
7.8.5.6 SI RAM POINTERS (SIRP). This 32-bit, read-only register indicates to the user
which RAM entry is currently being serviced. This gives a real-time status of where the SI
current is inside the TDM frame.
Although SIRP does not need to be accessed by most users, it does provide information that
may be helpful for debugging and synchronization of some system activity to the activity on
the TDMs. Reading SISTR should be sufficient for most applications.
The user can determine which RAM entry in the SI RAM is currently in progress, but cannot
determine the status within that entry. For instance, if the RAM entry is programmed to
select four contiguous time slots from the TDM and the SIRP indicates the entry is currently
active, the user does not know which of the four time slots is currently in progress. The SIRP
will, however, change its status immediately when the next SI RAM entry begins to be processed.
NOTE
The user may also connect one of the four strobes externally to
an interrupt pin to generate an interrupt on a particular SI RAM
entry starting or ending execution by the TSA.
The value of this register is changed upon transitions of the serial clocks. Before acting on
the information in this register, the user should perform two reads and verify that the two
reads returned the same value.
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The pointers provided by this register indicate the SI RAM entry word offset that is currently
in progress. The register is cleared at reset.
31
—
15
—
30
—
14
—
29
V
13
V
28
27
12
11
26
RbPTR
10
TbPTR
25
24
9
8
23
—
7
—
22
—
6
—
21
V
5
V
20
19
4
3
18
RaPTR
2
TaPTR
17
16
1
0
Freescale Semiconductor, Inc...
In all cases, the value in the TxPTR or RxPTR increments by one for each entry (i.e., 16-bit
SI RAM word) that is processed by the SI. Since each TxPTR and RxPTR is 5 bits each, the
values in each TxPTR and RxPTR can range from 0 to 31, corresponding to 32 different SI
RAM entries.
The full pointer range may not necessarily be used. For instance, if the last bit is set in the
fifth SI RAM entry, then the pointer will only reflect values from 0 to 4. Once the fifth entry is
processed by the SI, the pointer is reset to 0.
The V-bit in each entry shows that the entry is valid. This information is particularly useful if
the PTR value happens to be zero. Additionally, the V-bits save the user from having to read
both the SIRP and the SISTR to obtain the needed information.
The pointer values are described based on the four possible ways the SI RAM can be configured.
7.8.5.6.1 SIRP When RDM = 00 (One Static TDM). •In this case, since 64 entries cannot
be signified with a single 5-bit pointer, two 5-bit pointers are used—one for the first 32
entries and one for the second 32 entries.
RaPTR and RbPTR contain the address of the RAM entry currently active. When the SI
services entries 1–32, RaPTR will be incremented, and RbPTR will be continuously
cleared. When the SI services entries 33–64, RaPTR will be continuously cleared, and
RbPTR will be incremented.
TaPTR and TbPTR contain the address of the Tx entry currently active. When the SI services entries 1–32, TaPTR will be incremented, and TbPTR will be continuously cleared.
When the SI services entries 33–64, TaPTR will be continuously cleared, and TbPTR will
be incremented.
7.8.5.6.2 SIRP When RDM = 01 (One Dynamic TDM). •For the receiver, either RaPTR or
RbPTR is used, depending on which portion of the SI Rx RAM is currently active. For
the transmitter, either TaPTR or TbPTR is used, depending on which portion of the SI
Tx RAM is currently active.
If its V-bit is set, RaPTR contains the address of the Rx entry currently active. The SI RAM
receive address block in use is 0–63, and CRORa = 0 in SISTR.
If its V-bit is set, RbPTR contains the address of the Rx entry currently active. The SI RAM
receive address block in use is 64–127, and CRORa = 1 in SISTR.
If its V-bit is set, TaPTR contains the address of the Tx entry currently active. The SI RAM
transmit address block in use is 128–191, and CROTa = 0 in SISTR.
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If its V-bit is set, TbPTR contains the address of the Tx entry currently active. The SI RAM
transmit address block in use is 192–255, and CROTa = 1 in SISTR.
7.8.5.6.3 SIRP When RDM = 10 (Two Static TDMs). •This is the simplest case, since each
pointer is continuously used and has only one function.
RaPTR contains the address of the RXa entry currently active.
RbPTR contains the address of the RXb entry currently active.
TaPTR contains the address of the TXa entry currently active.
TbPTR contains the address of the TXb entry currently active.
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7.8.5.6.4 SIRP When RDM = 11 (Two Dynamic TDMs). •In this case, each pointer is continuously used, but points to different sections of the SI RAM, depending on whether
the pointer’s value is in the first half (0–15) or the second half (16–31).
RaPTR contains the address of the RXa entry currently active. If the pointer has a value
from 0–15, the current-route RAM is SI RAM address block 0–31, and CRORa = 0 in SISTR. If the pointer has a value from 16–31, the current-route RAM is SI RAM address block
32–63, and CRORa = 1 in SISTR.
RbPTR contains the address of the RXb entry currently active. If the pointer has a value
from 0–15, the current route RAM is SI RAM address block 64–95, and CRORb = 0 in SISTR. If the pointer has a value from 16–31, the current-route RAM is SI RAM address block
96–127, and CRORb = 1 in SISTR.
TaPTR contains the address of the TXa entry currently active. If the pointer has a value
from 0–15, the current route RAM is SI RAM address block 128–159, and CROTa = 0 in
SISTR. If the pointer has a value from 16–31, the current-route RAM is SI RAM address
block 160–191, and CROTa = 1 in SISTR.
TbPTR contains the address of the TXb entry currently active. If the pointer has a value
from 0–15, the current-route RAM is SI RAM address block 192–223, and CROTb = 0 in
SISTR. If the pointer has a value from 224–255, the current-route RAM is SI RAM address
block 160–191, and CROTb = 1 in SISTR.
7.8.6 SI IDL Interface Support
The IDL interface is a full-duplex ISDN interface used to connect a physical layer device to
the QUICC. The QUICC supports both the basic rate and the primary rate of the IDL bus. In
the basic rate of IDL, data on three channels, B1, B2, and D, is transferred in a 20-bit frame,
providing 160-kbps full-duplex bandwidth. The QUICC is an IDL slave device that is clocked
by the IDL bus master (physical layer device) and has separate receive and transmit sections. Because the QUICC can support two TDMs, it can actually support two independent
IDL buses using separate clocks and sync pulses as shown in Figure 7-31.
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NT
ISDN TE
IDL1
S/T
U
S/T
INTERFACES
QUICC
IDL2
Freescale Semiconductor, Inc...
S/T
S/T
U
INTERFACES
S/T
U
Figure 7-31. Dual IDL Bus Application Example
7.8.6.1 IDL INTERFACE EXAMPLE. An example of the IDL application is the ISDN terminal adaptor shown in Figure 7-32. In such an application, the IDL interface is used to connect
the 2B+D channels between the QUICC, CODEC, and S/T transceiver. One of the QUICC
SCCs would be configured to HDLC mode to handle the D channel; another QUICC SCC
would be used to rate adapt the terminal data stream over the first B channel. That SCC
would be configured for HDLC mode if V.120 rate adaption is required. The second B channel could be routed to the CODEC as a digital voice channel, if desired. The SPI is used to
send initialization commands and periodically check status from the S/T transceiver. The
SCC connected to the terminal would be configured for UART or other protocol depending
on the terminal protocol used. Alternatively, instead of a terminal, a connection to a LAN
could be made via Ethernet.
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SCC
SCC
MC68360
QUICC
ETHERNET
MC68160
EEST
SCC1
SCC
LAN
TSA
SYSTEM BUS (ROM AND RAM)
SPI
B2 + D
IDL
(DATA)
B1
B1 + B2 + D
ICL
(CONTROL)
Freescale Semiconductor, Inc...
MC145474
S/T
TRANSCEIVER
MC145554
PCM
CODEC/FILTER
MONOCIRCUIT
FOUR WIRE
POTS
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Figure 7-32. IDL Terminal Adapter
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The QUICC can identify and support each IDL channel or can output strobe lines for interfacing devices that do not support the IDL bus.
The IDL signals for each transmit and receive channel are as follows:
1. L1RCLKx—IDL clock; input to the QUICC.
2. L1RSYNCx—IDL sync signal; input to the QUICC. This signal indicates that the clock
periods following the pulse designate the IDL frame.
3. L1RXDx—IDL receive data; input to the QUICC. Valid only for the bits that are
supported by the IDL; ignored for other signals that may be present.
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4. L1TXDx—IDL transmit data; output from the QUICC. Valid only for the bits that are
supported by the IDL; three-stated otherwise.
5. L1RQx—IDL request permission to transmit on the D channel; output from the QUICC
on L1RQx pin.
6. L1GRx—IDL grant permission to transmit on the D Channel; input to the QUICC on
L1TSYNCx pin.
NOTE
x = a and b for TDMa and TDMb.
The basic rate IDL bus has three channels:
• B1—64 kbps bearer channel
• B2—64 kbps bearer channel
• D—16 kbps signaling channel
There are two definitions of the IDL bus frame structure: 8 bits and 10 bits (see Figure 7-33).
The difference between them is only the channel order within the frame.
NOTE
Previous versions of Motorola’s IDL-defined bit functions, called
auxiliary (A) and maintenance (M), were eliminated from the IDL
definition when it was decided that the IDL control channel would
be out-of-band. They were defined as a subset of the Motorola
SPI format called serial control port (SCP). If a user wishes to
implement the A and M bit functions as originally defined, the
TSA may be programmed to access these bits and to route them
transparently to an SCC or SMC. To perform the out-of-band
signaling required, the QUICC’s SPI may be used.
The QUICC supports all channels of the IDL bus in the basic rate. Each bit in the IDL frame
can be routed to every SCC and SMC or can assert a strobe output for supporting an external device.
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10-BIT IDL
L1CLK
(CLOCK NOT TO SCALE)
L1SYNC
L1RXD
B1
D1
B2
D2
L1TXD
B1
D1
B2
D2
Freescale Semiconductor, Inc...
8-BIT IDL
L1CLK
(CLOCK NOT TO SCALE)
L1SYNC
L1RXD
B1
B2
D1
D2
L1TXD
B1
B2
D1
D2
NOTE: L1RQx and L1GRx are not shown.
Figure 7-33. IDL Bus Signals
The QUICC supports the request-grant method for contention detection on the D channel of
the IDL basic rate. When the QUICC has data to transmit on the D channel, it asserts
L1RQx. The physical layer device monitors the physical layer bus for activity on the D channel and indicates that the channel is free by asserting L1GRx. The QUICC samples the
L1GRx signal when the IDL sync signal (L1RSYNCx) is asserted. If L1GRx is high (active),
the QUICC transmits the first zero of the opening flag in the first bit of the D channel. If a
collision is detected on the D channel, the physical layer device negates L1GRx. The QUICC
then stops its transmission and retransmits the frame when L1GRx is reasserted. This procedure is handled automatically for the first two buffers of a frame.
For the primary rate IDL, the QUICC can support up to four 8-bit channels in the frame,
determined by the programming of the SI RAM. To support more channels, the user can
route more than one channel to every SCC, which the SCC will treat as one high-speed
stream and store in the same data buffers (this approach is appropriate only for transparent
data). Additionally, the QUICC can be used to assert strobes for support of additional IDL
channels externally.
The IDL interface supports the CCITT I.460 recommendation for data rate adaptation, since
it can separately access each bit of the IDL bus. The current-route RAM specifies which bits
are supported by the IDL interface and by which serial controller. The receiver will receive
only the bits that are enabled by the receiver route RAM. The transmitter will transmit only
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the bits that are enabled by the transmitter route RAM and will three-state L1TXDx otherwise.
7.8.6.2 IDL INTERFACE PROGRAMMING. The user can program the channels used for
the IDL bus interface to the appropriate configuration. First, the user should program the
SIMODE to the IDL grant mode for that channel, using the GMx bits. The user can program
more than one channel to interface to the IDL bus. If the receive and transmit section are
used for interfacing to the same IDL bus, the user can internally connect the receive clock
and sync signals to the SI RAM transmit section, using the CRTx bits. The user has to program the RAM section used for the IDL channels to the desired routing. (An example is
shown in 7.8.4.6 SI RAM Programming Example.) The user should then define the IDL
frame structure to be a delay of 1 bit from frame sync to data, to falling edge sample sync,
and the clock edge to transmit on the rising edge of the clock. The L1TXDx pin should be
programmed to be three-stated when inactive (through the parallel I/O open-drain register).
To support the D channel, the user must program the appropriate GRx bit in SIMODE and
program the RAM entry to route data to that serial controller. The two definitions of IDL, 8
bits and 10 bits, are supported by only modifying the SI RAM programming. In both cases,
the L1GRx pin will be sampled with the L1TSYNCx signal and transferred to the D channel
SCC as a grant indication. The same procedure is valid for supporting an IDL bus in the second channel.
For example, assuming the 7.8.4.6 SI RAM Programming Example, which uses SCC1,
SCC2, and SCC4, connected to the TDMx pins, with no other SCCs connected, the initialization sequence is as follows:
1. Program the SI RAM. Write all entries that are not used with $0001, setting
the LST bit and disabling the routing function.
Entry
RAM Word
No.
SWTR
SSEL
CSEL
CNT
BYT
LST
description
1
0
0000
010
0000
1
0
8 Bits SCC2
2
0
0000
001
0000
0
0
1 Bit SCC1
3
0
0000
000
0000
0
0
1 Bit No Support
4
0
0000
100
0000
1
0
8 Bits SCC4
5
0
0001
001
0000
0
1
1 Bit SCC1 Strobe1
NOTE
Since IDL requires the same routing for both receive and transmit, an exact duplicate of the above entries should be written to
both the receive and transmit sections of the SI RAM beginning
at SI RAM addresses 0 and 128, respectively.
2. SIMODE = $00000145. Only TDMa is used; the SMCs are not connected.
3. SICR = $400040C0. Only SCC4, SCC2, and SCC1 are connected to the TSA.
SCC1 supports the grant mechanism since it is on the D channel.
4. PAODR bit 6 = 1. Configures L1TXDa to an open-drain output.
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5. PAPAR bits 6, 7, and 8 = 1. Configures L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR bits 6 and 7 = 1. PADIR bit 8 = 0. Configures L1TXDa, L1RXDa, and
L1RCLKa.
7. PCPAR bits 3, 10, and 11 = 1. Configures L1RQa, L1TSYNCa, and L1RSYNCa.
8. PCDIR bit 3 = 0. L1RQa is an input. L1TSYNCa will perform the L1GRa function
and is therefore an output, but it does not need to be configured with a PCDIR bit.
L1RSYNCa is an input, but it does not need to be configured with a PCDIR bit.
9. SIGMR = $04. Enable TDMa (one static TDM).
10. 1SICMR is not used.
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11. 1SISTR and SIRP do not need to be read, but can be used for debugging
information once the channels are enabled.
12. 1Enable the SCC1 for HDLC operation (to handle the LAPD protocol of
the D channel), and set SCC2 and SCC4 as desired.
7.8.7 SI GCI Support
The normal mode of the GCI, also known as the ISDN-oriented modular rev 2.2 (IOM-2),
and the SCIT are fully supported by the QUICC. The QUICC also supports the D channel
access control in S/T interface terminals by using the command/indication (C/I) channel for
that function.
The GCI bus consists of four lines: two data lines, a clock, and a frame synchronization line.
Usually, an 8-kHz frame structure defines the various channels within the 256-kbps data
rate. The QUICC can support two independent GCI buses and has independent receive and
transmit sections for each one. The interface can also be used in a multiplexed frame structure on which up to eight physical layer devices multiplex their GCI channels. In this mode,
the data rate would be 2048 kbps.
In the GCI bus, the clock rate is twice the data rate. The SI divides the input clock by two to
produce the data clock.
The QUICC also has data strobe lines, and the 1× data rate clock L1CLKOx output pins.
These signals are used for interfacing devices to GCI that do not support the GCI bus.
The GCI signals for each transmit and receive channel are as follows:
L1RSYNCx—Used as GCI sync signal; input to the QUICC. This signal indicates that
the clock periods following the pulse designate the GCI frame.
L1RCLKx—Used as GCI clock; input to the QUICC. The L1RCLKx signal is twice the
data clock.
L1RXDx—Used as GCI receive data; input to the QUICC.
L1TXDx—Used as GCI transmit data; open-drain output. Valid only for the bits that are
supported by the IDL; three-stated otherwise.
L1CLKOx—Optional signal; output from QUICC. This 1× clock output can be used to
clock devices that do not interface directly to GCI. If the double-speed clock
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is used, (DSCx bit is set in the SIMODE), this output is the L1RCLKx
divided by 2; otherwise, it is simply a 1× output of the L1RCLKx signal.
Note that on the MC68302 this signal was known as GCIDCL.
NOTE
x = a and b for TDMa and TDMb.
Figure 7-34 shows the GCI bus signals.
L1CLK
(2x THE DATA RATE)
(CLOCK NOT TO SCALE)
Freescale Semiconductor, Inc...
L1SYNC
L1RXD
B1
B2
MONITOR
D1 D2
C/I
A
E
L1TXD
B1
B2
MONITOR
D1 D2
C/I
A
E
NOTE: L1CLKOx is not shown.
Figure 7-34. GCI Bus Signals
In addition to the 144-kbps ISDN 2B+D channels, the GCI provides five channels for maintenance and control functions:
• B1—64 kbps bearer channel
• B2—64 kbps bearer channel
• M—64 kbps monitor (M) channel
• D—16 kbps signaling channel
• C/I—48 kbps C/I channel (includes A and E bits)
The M channel is used to transfer data between layer 1 devices and the control unit (i.e., the
CPU32+ core). The C/I channel is used to control activation/deactivation procedures or to
switch test loops by the control unit. The M and C/I channels of the GCI bus should be routed
to SMC1 or SMC2, which have modes to support the M and C/I channel protocols.
The QUICC can support any channel of the GCI bus in the primary rate by modifying the SI
RAM programming.
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation,
since it can access each bit of the GCI separately. The current-route RAM specifies which
bits are supported by the interface and by which serial controller. The receiver will receive
only the bits that are enabled by the SI RAM. The transmitter will transmit only the bits that
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are enabled by the SI RAM and will not drive L1TXDx; otherwise, L1TXDx is an open-drain
output and should be pulled high externally.
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The QUICC supports contention detection on the D channel of the SCIT bus. When the
QUICC has data to transmit on the D channel, it checks a SCIT bus bit that is marked with
a special route code (generally, bit 4 of C/I channel 2). The physical layer device monitors
the physical layer bus for activity on the D channel and indicates on this bit that the channel
is free. If a collision is detected on the D channel, the physical layer device sets bit 4 of C/I
channel 2 to logic high The QUICC then aborts its transmission and retransmits the frame
when this bit is set again. This procedure is handled automatically for the first two buffers of
a frame.
7.8.7.1 SI GCI ACTIVATION/DEACTIVATION PROCEDURE. In the deactivated state, the
clock pulse is disabled and the data line is at a logic one. The layer 1 device activates the
QUICC by enabling the clock pulses and by an indication in the channel 0 C/I channel. The
QUICC will report to the CPU32+ core by a maskable interrupt that a valid indication is in
the SMC receive BD.
When the CPU32+ core activates the line, the data output of L1TXDn is programmed to zero
by setting the STZx bit in the SIMODE register. Code 0 (command timing TIM) will be transmitted on channel 0 C/I channel to the layer 1 device until the STZx bit is reset. The physical
layer device will resume the clock pulses and will give an indication in the channel 0 C/I
channel. The CPU32+ core should reset the STZx bit to enable data output.
7.8.7.2 SI GCI PROGRAMMING. The following paragraphs describe programming for both
the normal mode GCI and SCIT.
7.8.7.2.1 Normal Mode GCI Programming. The user can program the channels used for
the GCI bus interface to the appropriate configuration. First, the user should program the
SIMODE to the GCI/SCIT mode for that channel, using the DSCx, FEx, CEx, and RFSDx
bits. This mode defines the sync pulse to GCI sync for framing and data clock as one-half
the input clock rate. The user can program more than one channel to interface to the GCI
bus. Also, if the receive and transmit section are used for interfacing the same GCI bus, the
user can internally connect the receive clock and sync signals to the SI RAM transmit section, using the CRTx bits. The user should then define the GCI frame routing and strobe
select using the SI RAM. When the receive and transmit section use the same clock and
sync signals, the user should program the receive section as well as the transmit section to
the same configuration. The L1TXDx pin in the I/O register should be programmed to be an
open-drain output. To support the monitor and the C/I channels in GCI, the user should route
those channels to one of the SMCs. To support the D channel when there is no possibility
of collision, the user should clear the GRx bit corresponding to the SCC that supports the D
channel in the SIMODE.
7.8.7.2.2 SCIT Programming. For interfacing the GCI/SCIT bus, the user should program
the SIMODE to the GCI/SCIT mode. The SI RAM is programmed to support a 96-bit frame
length, and the frame sync is programmed to the GCI sync pulse. Generally, the SCIT bus
supports the D channel access collision mechanism. For this purpose, the user should program the receive and transmit sections to use the same clock and sync signals, using the
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CRTx bits, and program the GRx bits to transfer the D channel grant to the SCC that supports this channel. The user should mark the received bit, which is the grant bit, by programming the channel select bits of the SI RAM to 111 for an internal assertion of a strobe on this
bit. This bit will be sampled by the SI and transferred to the D channel SCC as the grant.
The bit is generally bit 4 of the C/I in channel 2 of GCI, but any other bit may be selected
using the SI RAM.
For example, assuming SCC1 is connected to the D channel, SCC2 is connected to the B1
channel, and SCC4 is connected to the B2 channel, SMC1 is used to handle the C/I channels, and the D channel grant is on bit 4 of the C/I on SCIT channel 2, the initialization sequence is as follows:
Freescale Semiconductor, Inc...
1. Program the SI RAM. Write all entries that are not used with $0001, setting
the LST bit and disabling the routing function.
Entry
RAM Word
No.
SWTR
SSEL
CSEL
CNT
BYT
LST
Description
1
0
0000
010
0000
1
0
8 Bits SCC2
2
0
0000
100
0000
1
0
8 Bits SCC4
3
0
0000
101
0000
1
0
8 Bits SMC1
4
0
0000
001
0001
0
0
2 Bits SCC1
5
0
0000
101
0101
0
0
6 Bits SMC1
6
0
0000
000
0110
1
0
Skip 7 Bytes
7
0
0000
000
0001
0
0
Skip 2 Bits
8
0
0000
111
0000
0
1
D Grant Bit
NOTE
Since GCI requires the same routing for both receive and transmit, an exact duplicate of the above entries should be written to
both the receive and transmit sections of the SI RAM beginning
at addresses 0 and 128, respectively.
2. SIMODE = $000080E0. Only TDMa is used; SMC1 is connected. SCIT mode is
used in this example.
NOTE
If SCIT mode is not used, delete the last three entries of the SI
RAM and set the LST bit in the new last entry.
3. SICR = $400040C0. SCC4, SCC2, and SCC1 are connected to the TSA. SCC1
supports the grant mechanism since it is on the D channel.
4. PAODR bit 6 = 1. Configures L1TXDa to an open-drain output.
5. PAPAR bits 6, 7, and 8 = 1. Configures L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR bits 6 and 7 = 1. PADIR bit 8 = 0. Configures L1TXDa, L1RXDa, and
L1RCLKa.
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7. If the 1× GCI data clock is required, set PBPAR bit 11 and PBDIR bit 11, which
configures L1CLKOa as an output.
8. PCPAR bit 11 = 1. Configures L1RSYNCa.
9. SIGMR = $04. Enable TDMa (one static TDM).
10. 1SICMR is not used.
11. 1SISTR and SIRP do not need to be read, but can be used for debugging
information once the channels are enabled.
12. 1Enable the SCC1 for HDLC operation (to handle the LAPD protocol of
the D channel), set SCC2 and SCC4 as desired, and enable SMC1 for SCIT
operation.
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7.8.8 Serial Interface Synchronization
On rev A and B of the QUICC, the SI would reset itself if an unexpected sync pulse was seen
during the middle of a time frame. This would cause the SI to sync again on the following
sync pulse but it would also lead to an unresolved loss of synchronization of an SCC or SMC
operating in transparent or GCI modes (assuming that SCC or SMC was receiving data from
the SI).
In revision C.1 and later of the QUICC, the SI will ignore this unexpected sync pulse and
synchronize on the next sync pulse (it will not reset itself). This may lead to a reception of
one or two “bad” slots but the SCC or SMC will remain synchronized.
NOTE
Rev A mask is C63T
Rev B mask are C69T, and F35G
Current Rev C mask are E63C, E68C and F15W
7.8.9 NMSI Configuration
The SI supports an NMSI mode for each of the SCCs and SMCs. The decision of whether
to connect a given SCC to the NMSI is made in the SICR. The decision of whether to connect a given SMC to the NMSI is made in the SIMODE register.
An SCC or SMC may be connected to the NMSI, regardless of which other channels are
connected to a TDM channel. The user should note, however, that NMSI pins may be multiplexed with other functions at the parallel I/O lines. Therefore, if a combination of TDM and
NMSI channels is used, the decision of which SCCs and SMCs to connect and where to connect them should be made consulting the QUICC pinout. Generally speaking, the TDMa
channel is multiplexed with many of the SCC4 pins; whereas, the TDMb channel is multiplexed with many of the SCC3 pins.
The clocks that are provided to the SCCs and SMCs are derived from twelve sources: four
internal baud rate generators and eight external CLK pins (see Figure 7-35). There are two
main advantages to the bank-of-clocks approach. First, an SCC or SMC is not forced to
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Serial Interface
choose its clock from a pre-defined pin or baud rate generator, which allows flexibility in the
pinout mapping strategy. Second, if a group of SCC receivers and transmitters need the
same clock rate, they can share the same pin. This configuration leaves additional pins for
other functions and minimizes potential skew between multiple clock sources.
Freescale Semiconductor, Inc...
The four baud rate generators also make their clocks available to external logic, regardless
of whether the baud rate generators are being used by an SCC or SMC. Note that the
BRGOx pins are multiplexed with other functions; therefore, all BRGOx pins may not always
be available. Note that BRGO3 has the flexibility to be output on both port A 12 and port B
16. See the pinout description in Section 11 Ordering Information and Mechanical Data for
more details.
There are a few restrictions in the bank-of-clocks mapping. First, only eight of the twelve
sources can be connected to any given SCC receiver or transmitter. Second the SMC transmitter must have the same clock source as the receiver when connected to the NMSI pins.
Once the clock source is selected, the clock is given an internal name. For the SCCs, the
name is RCLKx and TCLKx. For the SMCs, the name is simply SMCLKx. These internal
names are used only in NMSI mode to specify the clock that is sent to the SCC or SMC.
These names do not correspond to any pins on the QUICC.
NOTE
The internal RCLKx and TCLKx may be used as inputs to the
DPLL unit, which is inside the SCC. Thus, the RCLKx and
TCLKx signals are not required to always reflect the actual bit
rate on the line.
The exact pins available to each SCC and SMC in the NMSI mode are summarized in Figure
7-35.
The SCC1 in NMSI mode has its own set of modem control pins:
TXD1
RXD1
TCLK1 <- BRG1–BRG4, CLK1–CLK4
RCLK1 <- BRG1–BRG4, CLK1–CLK4
RTS1
CTS1
CD1
The SCC2 in NMSI mode has its own set of modem control pins:
TXD2
RXD2
TCLK2 <- BRG1–BRG4, CLK1–CLK4
RCLK2 <- BRG1–BRG4, CLK1–CLK4
RTS2
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CTS2
CD2
BRG1
SCC1
RX
BRG2
BRG3
RCLK1
BRG4
BRGO1
BRGO2
BRGO3
BRGO4
SCC1
TX
TCLK1
Freescale Semiconductor, Inc...
SCC2
RX
RCLK2
SCC2
TX
TCLK2
RCLK3
CLK1
CLK2
BANK OF CLOCKS
SELECTION LOGIC
TCLK3
SCC3
RX
CLK3
CLK4
CLK5
CLK6
SCCS CONTROLLED IN THE SICR.
SMCS CONTROLLED IN SIMODE.
CLK7
CLK8
SCC3
TX
SCC4
RX
RCLK4
SCC4
TX
TCLK4
SMC1
SMC2
SMCLK1
SMCLK2
Figure 7-35. Bank of Clocks
The SCC3 in NMSI mode has its own set of modem control pins:
TXD3
RXD3
TCLK3 <- BRG1–BRG4, CLK5–CLK8
RCLK3 <- BRG1–BRG4, CLK5–CLK8
RTS3
CTS3
CD3
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Baud Rate Generators (BRGs)
The SCC4 in NMSI mode has its own set of modem control pins:
Freescale Semiconductor, Inc...
TXD4
RXD4
TCLK4 <- BRG1–BRG4, CLK5–CLK8
RCLK4 <- BRG1–BRG4, CLK5–CLK8
RTS4
CTS4
CD4
The SMC1 in NMSI mode has its own set of modem control pins:
SMTXD1
SMRXD1
SMCLK1 <- BRG1–BRG4, CLK1–CLK4
SMSYN1 (used only in the totally transparent protocol)
The SMC2 in NMSI mode has its own set of modem control pins:
SMTXD2
SMRXD2
SMCLK2 <- BRG1–BRG4, CLK5–CLK8
SMSYN2 (used only in the totally transparent protocol)
Any SCC or SMC that requires fewer pins that those listed may use that pin for another function or configure that pin as a parallel I/O pin.
Since some SCCs use external clock pins CLK1–CLK4 and other SCCs use external clock
pins CLK5–CLK8, it might seem that there is no way to provide one external clock source
on one CLK pin to be used by all four SCCs. However, the QUICC provides a simple clock
bridge function from external CLK8 to the internal CLK4 connection, even if the CLK4 pin is
used for another of its programmable functions. This configuration allows SCC1/SCC2 to
share clocks with SCC3/SCC4 without wasting an external pin. This is shown in the port A
registers in 7.14.4 Port A Registers.
7.9 BAUD RATE GENERATORS (BRGS)
The CPM contains four, independent, identical BRGs that can be used with the SCCs and
SMCs. The clocks produced in the BRG are sent to the bank-of-clocks selection logic, where
they can be routed to the SCCs and/or SMCs. The bank-of-clocks logic is described in 7.8.9
NMSI Configuration. In addition, the output of the BRG may be routed to a pin to be used
externally. The main features of the BRGs are as follows:
• Four, Independent, Identical BRGs
• On-the-Fly Changes Allowed
• Each BRG May Be Routed to One or More SCCs or SMCs
• A 16× Divider Option Allows Slow Baud Rates at High System Frequencies
• Each BRG Contains an Autobaud Support Option
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• Each BRG Output May Be Routed to a Pin (e.g., BRGO1)
Refer to Figure 7-36 for the BRG block diagram.
EXTC
DIV16
CD11–CD0
CLK2
CLK6
PRESCALER
DIVIDE BY
1 OR 16
MUX
12-BIT
COUNTER
1–4096
BRGO1
CLOCK
TO PIN
AND/OR
BANK
OF CLOCKS
Freescale Semiconductor, Inc...
BRGCLK
ATB
RXD1
AUTOBAUD
CONTROL
Figure 7-36. Baud Rate Generator Block Diagram
The clock input to the prescaler may be selected by the EXTC bits to come from one of three
sources: BRGCLK, CLK2, or CLK6. Each source is discussed in the following paragraphs.
The BRGCLK is generated in the QUICC clock synthesizer specifically for the four BRGs
(as well as a fifth BRG that is part of the SPI) and defaults to the system frequency (e.g., 25
MHz). However, the clock synthesizer in the SIM60 has an option to divide the BRGCLK by
1, 4, 16, or 64 before it leaves the clock synthesizer. Whatever the resulting frequency of
BRGCLK, the user may use that frequency as the input to the QUICC BRGs.
The ability to reduce the frequency of BRGCLK before it leaves the clock synthesizer is useful in low-power applications. In a low-power mode, the BRG clocking could be a significant
factor in overall QUICC power consumption. Thus, if the BRGs do not need to generate high
frequencies or do not require a high resolution in the user application, a lower frequency
BRGCLK may be input to the BRGs. The user may wish to dynamically change the general
system clock frequency in the clock synthesizer (slow go mode) while still having the BRG
run at the original frequency. The BRGCLK allows this option also.
NOTE
The BRG configuration register may be written at any time, regardless of the BRGCLK input frequency.
Alternatively, the user may choose the CLK2 or CLK6 pins to be the clock source. An external pin allows flexible baud rate frequency generation, regardless of the system frequency.
Additionally, the CLK2 or CLK6 pins allow a single external frequency to become the input
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Baud Rate Generators (BRGs)
clock for multiple BRGs. The clock signals on the CLK2 and CLK6 pins are not synchronized
internally prior to being used by the BRG.
Next, the BRG provides a divide-by-16 option before the clock reaches the prescaler. This
option is chosen by the DIV16 bit.
Freescale Semiconductor, Inc...
The clock is then divided in the prescaler by up to 4096. This input clock divide ratio can be
programmed on the fly. Two on-the-fly BRG changes should not occur within a time shorter
than the period of at least two BRG input clocks.
The output of the prescaler is sent internally to the bank of clocks and may also be output
externally on the BRGOx pins of either the port A or port B parallel I/O. One BRGOx pin
(BRGO4–BRGO1) is an output from the corresponding BRG. If the BRG divides the clock
by an even value, the transitions of the BRGO pin will always occur on the falling edge of
the input clock to the BRG. If the BRG is programmed to an odd value, the transitions will
alternate between the falling and rising edges of the input clock.
Additionally, the output of the BRG may be sent to the autobaud control block described in
the following paragraphs.
7.9.1 Autobaud Support
In the autobaud process, a UART deduces the baud rate of its received character stream by
looking at the pattern received as well as the timing information of that pattern. The QUICC
BRGs have a built-in autobaud control function that automatically measures the length of a
start bit and modifies the baud rate accordingly. (This capability was only available on the
MC68302 with a special microcode option.)
If the ATB bit in the BRG is set, the autobaud control block starts to search for a low level
on the corresponding RXDx input line (RXD4–RXD1). When it finds a low level on the RXDx
line, it assumes that this is the beginning of a start bit and begins counting the start bit length.
During this time, the BRG output clock toggles for 16 BRG clock cycles at the BRG input
clock rate, and then stops with the BRGO output clock in the low state.
After the RXDx line changes back to the high level, the autobaud control block rewrites the
CD and DIV16 bits in the BRG configuration register to the divide ratio it found. Due to measurement error that can occur at high baud rates, this divide rate written by the autobaud
controller may not be the precise, final baud rate desired by the user (e.g., 56600 could be
the resulting baud rate, rather than 57600). Thus, an interrupt is provided to the user in the
UART SCC event register to signify that the BRG configuration register was rewritten by the
autobaud controller. On recognition of this interrupt, the user should rewrite the BRG configuration register with the desired value. The user is encouraged to do this as quickly as
possible, even prior to the first character being fully received, to ensure that all characters
are recognized correctly by the UART. The first data must have a transition from 1 to 0, then
look for a one again. Thus the first cahracter must be an odd character.
Once a full character is received, the user may check in software to see if the received character matches a predefined value (such as "a" or "A"; it must be an odd character). Software
should then check for other characters (such at "t" or "T") and program the SCC to the
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desired parity mode. Changes in the parity mode may be accomplished in the UART protocol specific mode register (PSMR).
NOTES
The SCC associated with this BRG must be programmed to
UART mode. The SCC must have the TDCR and RDCR bits in
the general SCC mode register set to the 16× option for the autobaud function to operate correctly.
Freescale Semiconductor, Inc...
The input clock that is supplied to the BRG in autobaud mode
should be as fast as possible to improve the accuracy of the start
bit measurement. Input frequencies such as 1.8432MHz,
3.68MHz, 7.36MHz and 14.72MHz should be used.
For autobaud to operate sucessfully, the SCC performing the
autobaud function must be connected to the baud rate generator
for that SCC. In other words, for SCC2 to correctly perform the
autobaud function, it must be clocked by BRG2. Also, for the
SCC to correctly detect an autobaud lock and an interrupt to be
generated, the SCC must receive three full Rx clocks from the
BRG before the autobaud process begins. To do this, first set
the GSMR with the ATB=0 and enable the BRG Rx clock to the
highest frequency. Immediately prior to the start of the autobaud
process (after device initialization) set the ATB bit equal to a
one.
7.9.2 BRG Configuration Register (BRGC)
Each BRGC is a 24-bit, memory-mapped, read/write register that is cleared at reset. A reset
disables the BRG and puts the BRGO output clock to the high level. The BRGC can be written at any time with no need to disable the SCCs or the external devices that are connected
to the BRGO output clock. The BRG changes will occur at the end of the next BRG clock
cycle (no spikes will occur on the BRGO output clock). The BRGC allows on-the-fly
changes. Two on-the-fly changes to the BRG should not occur within a time shorter than the
period of at least two BRG input clocks.
23
22
21
20
19
18
8
CD7
7
CD6
6
CD5
—
11
CD10
10
CD9
9
CD8
17
RST
5
CD4
16
EN
4
CD3
15
14
EXTC1–EXTC0
3
2
CD2
CD1
13
ATB
1
CD0
12
CD11
0
DIV16
Bits 23–18—Reserved
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Baud Rate Generators (BRGs)
RST—Reset BRG
This bit performs a software reset of the BRG identical to that of an external reset. A reset
disables the BRG and sets the BRGO output clock. (This can only be seen externally if
the BRGO function is enabled to reach the corresponding port B parallel I/O pin.)
0 = Enable the BRG.
1 = Reset the BRG (software reset).
Freescale Semiconductor, Inc...
EN—Enable BRG Count
This bit is used to dynamically stop the BRG from counting, which may be useful for lowpower modes.
0 = Stop all clocks to the BRG.
1 = Enable clocks to the BRG.
EXTC1–EXTC0—External Clock Source
The EXTC bits select the BRG input clock from the internal BRGCLK or one of three external pins.
00 = The BRG input clock comes from the BRGCLK (internal clock generated by the
clock synthesizer in the SIM60).
01 = The BRG input clock comes from the CLK2 pin.
10 = The BRG input clock comes from the CLK6 pin.
11 = Reserved.
ATB—Autobaud
When set, this bit selects autobaud operation of the BRG on the corresponding RXDx pin.
0 = Normal operation of the BRG.
1 = When RXDx goes low, the BRG will determine the length of the start bit and synchronize the BRG to the actual baud rate.
NOTE
This bit must remain clear (0) until the SCC receives 3 Rx clocks,
then the user must set this bit to one in order to obtain the correct
baud rate. When the baud rate is obtained and locked it will be
indicated by setting the AB bit in the UART event register.
CD11–CD0—Clock Divider
The clock divider bits, CD11–CD0, and the prescaler determine the BRG output clock
rate. CD11–CD0 are used to preset a 12-bit counter that is decremented at the prescaler
output rate. The counter is not accessible to the user. When the counter reaches zero, it
is reloaded from the clock divider bits. Thus, a value of $FFF in CD11–CD0 produces the
minimum clock rate (divide by 4096), and a value of $0000 produces the maximum clock
rate (divide by 1).
Even when dividing by an odd number, the counter ensures a 50% duty cycle by asserting
the terminal count once on clock low and next on clock high. The terminal count signals
counter expiration and toggles the clock.
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DIV16—BRG Clock Prescaler Divide by 16
The BRG clock prescaler bit selects a divide-by-1 or divide-by-16 prescaler for the clock
divider input.
7.9.3 UART Baud Rate Examples
Freescale Semiconductor, Inc...
For synchronous communication using internal baud rate generator, the BRGO output clock
must never be faster than the SyncCLK frequency divided by 2. Produced in the clock synthesizer in the SIM60, SyncCLK is the frequency used internally by the synchronization circuitry in the SCCs, SMCs, and SPI. It defaults to the main system frequency (e.g., 25 MHz).
Thus, with a 25-MHz system where the SyncCLK is the same as the main system frequency,
the maximum BRGO output clock rate is 12.5 MHz.
The user should program the UART to 16× oversampling (RDCR and TDCR bits in the general SCC mode register) when using the SCC as a UART. (On the QUICC, 8× and 32×
options are also available.) Assuming 16× oversampling is chosen in the UART, a data rate
of 25MHz ÷ 16 = 1.5625 Mbits/sec is the maximum possible UART speed.
Putting this together, the following formula for calculating the bit rate based on a particular
BRG configuration for a UART: async baud rate = (BRGCLK or CLK2 or CLK6) ÷ (clock
divider + 1) ÷ (1 or 16 depending on the DIV16 bit) ÷ (8 or 16 or 32 according to the RDCR
and TDCR bits in the general SCC mode register).
Table 7-3 lists examples of typical bit rates of asynchronous communication. Note that for
this mode, the internal clock rate is assumed to be 16× the baud rate.
Table 7-4. Typical Baud Rates of Asynchronous Communication
QUICC System Frequency (MHz)
20
25
24.5760
Baud
Rates
Div16
Div
Actual
Frequency
Div16
Div
Actual
Frequency
Div16
Div
Actual
Frequency
50
1
1561
50.02
1
1952
50
1
1919
50
75
1
1040
75.05
1
1301
75
1
1279
75
150
1
520
149.954
1
650
150
1
639
150
300
1
259
300.48
1
324
300.5
1
319
300
600
0
2082
600.09
0
2603
600
0
2559
600
1200
0
1040
1200.7
0
1301
1200
0
1279
1200
2400
0
520
2399.2
0
650
2400.1
0
639
2400
4800
0
259
4807.7
0
324
4807.69
0
319
4800
9600
0
129
9615.4
0
162
9585.9
0
159
9600
19200
0
64
19231
0
80
19290
0
79
19200
38400
0
32
37879
0
40
38109
0
39
38400
57600
0
21
56818
0
26
57870
0
26
56889
115200
0
10
113636
0
13
111607
0
12
118154
NOTE: All values are decimal.
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Serial Communication
Controllers (SCCs)
For synchronous communication, the internal clock is identical to the baud rate output. To
get the desired rate, the user can select the appropriate system clock according to the following equation:
sync baud rate = (BRGCLK or CLK2 or CLK6) ÷ (clock divider + 1) ÷ (1 or 16 according to
the DIV16 bit)
For example, to get the rate of 64 kbps, the system clock can be 24.96 MHz, DIV16 = 0, and
the clock divider = 389.
7.10 SERIAL COMMUNICATION CONTROLLERS (SCCS)
Freescale Semiconductor, Inc...
The SCC key features are as follows:
• Implements HDLC/SDLC, HDLC Bus, BISYNC, Synchronous Start/Stop, Asynchronous Start/Stop (UART), AppleTalk (LocalTalk), and Totally Transparent Protocols
• Ethernet Version of QUICC Supports Full 10 Mbps Ethernet/IEEE 802.3 on SCC1
• Additional Protocols Supported Through Motorola-Supplied RAM Microcodes: Profibus, Signaling System#7 (SS7), Async HDLC, DDCMP, V.14, and X.21 (see Appendix
C RISC Microcode from RAM).
• 2 Mbps HDLC, HDLC Bus, and/or Transparent Data Rates Supported on All Four SCCs
Simultaneously (Full Duplex).
• 10 Mbps Ethernet (Half Duplex) on SCC1 and 2 Mbps on the Other SCCs Supported
Simultaneously (Full Duplex)
• A Single HDLC or Transparent Channel Can Be Supported at 8 Mbps (Full Duplex)
• SCC Clocking Rates up to 12.5 MHz at 25 MHz.
• DPLL Circuitry for Clock Recovery with NRZ, NRZI, FM0, FM1, Manchester, and Differential Manchester (Also Known as Differential Biphase-L)
• SCC Clocks May Be Derived from a Baud Rate Generator, an External Pin, or DPLL.
Data Clock May Be as High as 3.125 MHz with a 25-MHz Clock
• Supports Automatic Control of the RTS, CTS, and CD Modem Signals
• Multibuffer Data Structure for Receive and Transmit (up to 224 BDs May Be Partitioned
in Any Way Desired)
• Deep FIFOs (SCC1 Has 32-Byte Rx and Tx FIFOs; SCC2, SCC3, and SCC4 Have 16Byte Rx and Tx FIFOs)
• Transmit-On-Demand Feature Decreases Time to Frame Transmission
• Low FIFO Latency Option for Transmit and Receive in Character-Oriented and Totally
Transparent Protocols
• Frame Preamble Options
• Full-Duplex Operation
• Fully Transparent Option for Receiver/Transmitter While Another Protocol Executes on
the Transmitter/Receiver
• Echo and Local Loopback Modes for Testing
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NOTE
The performance figures listed in the key features assume a 25MHz system clock.
7.10.1 SCC Overview
Freescale Semiconductor, Inc...
The QUICC has four SCCs that can be configured independently to implement different protocols. Together, they can be used to implement bridging functions, routers, gateways, and
interface with a wide variety of standard wide area networks, local area networks, and proprietary networks. The SCCs have many physical interface options such as interfacing to
TDM buses, ISDN buses, and standard modem interfaces (see 7.8 Serial Interface with
Time Slot Assigner).
On the QUICC, the SCC does not include the physical interface, but it is the logic which formats and manipulates the data obtained from the physical interface. That is why the SI section is described separately. The choice of protocol is independent of the choice of physical
interface.
The SCC is described in terms of the protocol that it is chosen to run. When an SCC is programmed to a certain protocol, it implements a certain level of functionality associated with
that protocol. For most protocols, this corresponds to portions of the link layer (layer 2 of the
seven-layer ISO model). Many functions of the SCC are common to all of the protocols.
These functions are described first in the SCC description. Following that, the specific implementation details that make one protocol different from the others are discussed, beginning
with the UART protocol. Thus, the reader should read from this point up to the UART protocol, and then skip to the particular protocol desired. Since the SCCs use similar data structures across all protocols, the reader's learning time will decrease dramatically after
understanding the first protocol.
Each SCC supports a number of protocols: HDLC/SDLC, HDLC bus, BISYNC, asynchronous or synchronous start/stop (UART), totally transparent operation, and AppleTalk (i.e.,
LocalTalk). In addition, Ethernet is available on SCC1 of the Ethernet version of the QUICC.
Although the protocol that is chosen usually applies to both the SCC transmitter and
receiver, the SCCs have an option of running one-half of the SCC with transparent operation
while the other half runs the standard protocol.
Each of the internal clocks (RCLK, TCLK) for each SCC can be programmed with either an
external or internal source. The internal clocks can originate from one of four baud rate generators or one of four external clock pins. These clocks may be as fast as a 1:2 ratio of the
system clock (i.e., 12.5 MHz); however, the SCC’s ability to support a sustained bit stream
depends on the protocol as well as other factors. See Appendix A Serial Performance for
more details.
Associated with each SCC is a digital phase-locked loop (DPLL) for external clock recovery.
The clock recovery options include NRZ, NRZI, FM0, FM1, Manchester, and Differential
Manchester. The DPLL may be configured to NRZ operation in order to pass the clocks and
data to/from the SCCs without modifying them.
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Serial Communication
Controllers (SCCs)
Each SCC may be connected to its own set of pins on the QUICC. This configuration is
called the NMSI and is described in 7.8 Serial Interface with Time Slot Assigner. In this configuration, each SCC can support the standard modem interface signals (RTS, CTS, and
CD) through the port C pins and the CPM interrupt controller (CPIC). Additional handshake
signals may be supported with additional parallel I/O lines.
Refer to the SCC block diagram in Figure 7-37.
IMB
TCLKx
DPLL
AND CLOCK
RECOVERY
Freescale Semiconductor, Inc...
CONTROL
REGISTERS
PERIPHERAL BUS
RCLKx
CLOCK
GENERATOR
INTERNAL CLOCKS
MODEM LINES
RXD
DECODER
RECEIVER
CONTROL
UNIT
RECEIVE
DATA
FIFO
TRANSMIT
DATA
FIFO
TRANSMITTER
CONTROL
UNIT
DELIMITER
SHIFTER
SHIFTER
DELIMITER
MODEM LINES
TXD
ENCODER
Figure 7-37. SCC Block Diagram
7.10.2 General SCC Mode Register (GSMR)
Each SCC contains a GSMR that defines all the options that are common to each SCC,
regardless of the protocol. Detailed descriptions of some of the operations of the GSMR are
given in later sections. GSMR is a read-write register that is cleared at reset. Since GSMR
is 64 bits in length, it is accessed as GSMR_L and GSMR_H. GSMR_L contains the first
(low-order) 32 bits of GSMR; GSMR_H contains the last 32 bits of GSMR.
63
62
47
61
46
31
—
45
REVD
30
29
EDGE
15
14
TCRC
RDCR
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13
60
44
TRX
28
TCI
12
RENC
59
58
43
42
TTX
CDP
27
26
TSNC
11
10
57
41
CTSP
25
RINV
56
—
40
CDS
24
TINV
9
8
TENC
55
54
53
39
CTSS
23
38
TFL
22
TPL
37
RFW
21
7
6
5
4
ENR
ENT
DIAG
52
51
50
49
36
35
34
TXSY
SYNL
20
19
18
TPP
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48
GDE
33
32
RTSM
RSYN
17
16
TDCR
2
1
0
MODE
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Bits 63–49, 31—Reserved
GDE—Glitch Detect Enable
This bit determines whether the SCC will look for glitches on the external receive and
transmit serial clock lines provided to this SCC. If this feature is enabled, the presence of
a glitch will be reported in the SCC event register. Whether or not GDE is set, the SCC
always attempts to clean up the clocks that it uses internally via a Schmitt trigger on the
input lines.
0 = No glitch detection is performed. This option should be chosen if the external serial
clock exceeds the limits of the glitch detection logic (6.25 MHz assuming a 25-MHz
system clock). This option should also be chosen if the SCC clock is provided from
one of the internal baud rate generators. Lastly, this option should be chosen if external clocks are used and it is more important to minimize power consumption
than to watch for glitches.
1 = Glitch detection is performed with a maskable interrupt generated in the SCC event
register.
TCRC—Transparent CRC (Valid for a Totally Transparent Channel Only)
These bits select the type of frame checking that is provided on the transparent channels
of this SCC (either the receiver, transmitter, or both as defined by TTX and TRX). Although this configuration selects a frame check type, the actual decision to send the frame
check is made in the Tx BD. Thus, it is not required to send a frame check in transparent
mode. If a frame check is not used, the user may simply ignore the frame check errors
that are generated on the receiver.
00 = 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1)
01 = CRC16 (BISYNC). (X16 + X15 + X2 + 1)
10 = 32-bit CCITT CRC (Ethernet and HDLC). (X32 + X26 + X23 + X22 + X16 + X12
+ X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1)
11 = Reserved
REVD—Reverse Data (Valid for a Totally Transparent Channel Only)
0 = Normal operation.
1 = When set, this bit will cause the totally transparent channels on this SCC (either
the receiver, transmitter, or both as defined by TTX and TRX) to reverse the bit order, transmitting the MSB of each octet first. See 7.10.20.11 BISYNC Mode Register (PSMR) for the method of reversing the bit order in the BISYNC protocol.
TRX—Transparent Receiver
The QUICC SCCs offer totally transparent operation. However, to increase flexibility, totally transparent operation is not configured with the MODE bits, but with the TTX and
TRX bits. This gives the user the opportunity to implement unique applications, such as
an SCC transmitter configured to UART and the receiver configured to totally transparent
operation. To do this, set MODE = UART, TTX = 0, and TRX = 1.
0 = Normal operation.
1 = The receiver operates in totally transparent mode, regardless of the protocol selected for the transmitter in the MODE bits.
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NOTE
Full-duplex totally transparent operation for an SCC is obtained
by setting both TTX and TRX.
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An SCC cannot operate with Ethernet on its transmitter simultaneously with transparent operation on its receiver, or erratic behavior will result. In other words, if the GSMR MODE = Ethernet,
TTX must equal TRX, or erratic operation will result.
TTX—Transparent Transmitter
The QUICC SCCs offer totally transparent operation. However, to increase flexibility, totally transparent operation is not configured with the MODE bits, but with the TTX and
TRX bits. This gives the user the opportunity to implement unique applications, such as
an SCC receiver configured to HDLC and the transmitter configured to totally transparent
operation. To do this, set MODE = HDLC, TTX = 1, and TRX = 0.
0 = Normal operation.
1 = The transmitter operates in totally transparent mode, regardless of the protocol selected for the receiver in the MODE bits.
NOTE
Full-duplex totally transparent operation for an SCC is obtained
by setting both TTX and TRX.
An SCC cannot operate with Ethernet on its receiver simultaneously with transparent operation on its transmitter, or erratic
behavior will result. In other words, if the GSMR MODE = Ethernet, TTX must equal TRX, or erratic operation will result.
CDP—CD Pulse
0 = Normal operation—envelope mode. The CD pin should envelope the frame, and
negating CD while receiving will cause a CD lost error.
1 = Pulse mode. Once the CD pin is asserted, synchronization has been achieved, and
further transitions of CD will have no effect on reception.
This mode is similar to the way the CD (sync) pin is used on the MC68302 in totally transparent mode. To mimic this behavior on the QUICC, the external sync signal should be
connected to the CD and CTS pins on the QUICC, and the CDP and CTSP bits should be
set.
NOTE
This bit must be set if this SCC is used in TSA.
CTSP—CTS Pulse
0 = Normal operation—envelope mode. The CTS pin should envelope the frame, and
a negation of CTS while transmitting will cause a CTS lost error.
1 = Pulse mode. Once the CTS pin is asserted, synchronization has been achieved,
and further transitions of CTS will have no effect on transmission.
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CDS—CD Sampling
0 = The CD input is assumed to be asynchronous with the data. It is internally synchronized by the SCC, and then data is received.
1 = The CD input is assumed to be synchronous with the data, giving faster operation.
In this mode, CD must transition while the receive clock is in the low state. As soon
as CD is low, data begins being received. This mode is especially useful when connecting QUICCs in transparent mode since it allows the RTS pin of one QUICC to
be directly connected to the CD pin of the other QUICC.
CTSS—CTS Sampling
0 = The CTS input is assumed to be asynchronous with the data. It is internally synchronized by the SCC, and data is then transmitted after several serial clock delays.
1 = The CTS input is assumed to be synchronous with the data, giving faster operation.
In this mode, CTS must transition while the transmit clock is in the low state. As
soon as CTS is low, data immediately begins transmission. This mode is especially
useful when connecting QUICCs in transparent mode since it allows the RTS pin
of one QUICC to be directly connected to the CTS pin of the other QUICC.
TFL—Transmit FIFO Length
0 = Normal operation. The transmit FIFO is 32 bytes for SCC1 and 16 bytes for the other SCCs.
1 = The transmit FIFO is 1 byte. This may be used with character-oriented protocols
such as UART to ensure a minimum FIFO latency at the expense of performance.
RFW—Rx FIFO Width
0 = Rx FIFO is 32-bits wide for maximum performance. Data will not normally be written to receive buffers until at least 32 bits have been received. This configuration
is required for HDLC-type protocols and Ethernet; it is the recommended configuration for high-performance transparent modes. In this mode, the receive FIFO is
32 bytes for SCC1 and 16 bytes for the other SCCs.
1 = Low-latency operation. The Rx FIFO is 8-bits wide, and the receive FIFO is onefourth its normal size (8 bytes for SCC1 and 4 bytes for the other SCCs). This allows data to be written to the data buffer each time a character is received, without
waiting for 32 bits to be received. This configuration must be chosen for characteroriented protocols such as UART and BISYNC. It may also be used for low-performance, low-latency, totally transparent operation if desired. It must not be used
with HDLC, HDLC Bus, AppleTalk, or Ethernet, or erratic behavior may result.
TXSY—Transmitter Synchronized to the Receiver
The TXSY bit is particularly intended for X.21 applications where the transmitted data
must begin an exact multiple of 8-bit periods after the receive data arrives.
0 = No synchronization between receiver and transmitter (default).
1 = The transmit bit stream is synchronized to the receiver. Additionally, if RSYN = 1,
then transmission in the totally transparent mode will not occur until the receiver
has synchronized with the bit stream and the CTS signal is asserted to the SCC.
Assuming CTS is already asserted, transmission will begin eight clocks after the
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receiver begins receiving data. This behavior is similar to the MC68302 totally
transparent mode behavior when the EXSYN bit in its SCC mode register is set.
SYNL—Sync Length (BISYNC and Transparent Mode Only)
These bits determine the operation of an SCC receiver that is configured for BISYNC or
totally transparent operation only. See the data synchronization register definition in the
BISYNC and totally transparent descriptions for more information.
00 = The sync pattern in the DSR is not used. An external sync signal is used instead
(CD pin asserted).
01 = 4-bit sync. The receiver will synchronize on a 4-bit sync pattern stored in DSR.
This character and additional syncs can be programmed to be stripped using the
SYNC character in the parameter RAM. The transmitter will transmit the entire
contents of the DSR prior to each frame.
10 = 8-bit sync. This option should be chosen along with the BISYNC protocol to implement mono-sync. The receiver will synchronize on an 8-bit sync pattern stored
in DSR. The transmitter will transmit the entire contents of the DSR prior to each
frame.
11 = 16-bit sync. Also called BISYNC. The receiver will synchronize on a 16-bit sync
pattern stored in DSR. The transmitter will transmit the DSR prior to each frame.
RTSM—RTS Mode
This bit may be changed on the fly.
0 = Send idles between frames as defined by the protocol and the Tend bit. RTS is negated between frames (default).
1 = Send flags/syncs between frames according to the protocol. RTS is always asserted whenever the SCC is enabled.
RSYN—Receive Synchronization Timing (Valid for a Totally Transparent Channel Only)
0 = Normal operation.
1 = If CDS = 1, then the CD pin should be asserted on the second bit of the receive
frame, rather than the first. This configuration matches the behavior of the
MC68302 totally transparent receiver when its EXSYN bit is set; it is included on
the QUICC for compatibility.
EDGE—Clock Edge
The EDGE bits determine the clock edge used by the DPLL for adjusting the receive sample point due to jitter in the received signal. The selection of the EDGE bits is ignored in
the UART protocol or the x1 mode of the RDCR bits.
00 = Both the positive and negative edges are use for changing the sample point (default).
01 = Positive edge. Only the positive edge of the received signal is used for changing
the sample point.
10 = Negative edge. Only the negative edge of the received signal is used for changing
the sample point.
11 = No adjustment is made to the sample points.
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TCI—Transmit Clock Invert
0 = Normal operation.
1 = The internal transmit clock (TCLK) is inverted by the SCC before it is used. This
option allows the SCC to clock data out one-half clock earlier, on the rising edge of
TCLK rather than the falling edge. In this mode, the SCC offers a minimum and
maximum "rising clock edge to data" specification. Data output by the SCC after
the rising edge of an external transmit clock can be latched by the external receiver
one clock cycle later on the next rising edge of the same transmit clock. This option
is recommended for Ethernet, HDLC, or transparent operation when the clock
rates are high (e.g., above 8 MHz) to improve data setup time for the external receiver.
TSNC—Transmit Sense
This bit indicates the amount of time the internal sense signal will stay active after the last
transition on the RXD pin, indicating that the line is free. For instance, these bits can be
used in the AppleTalk protocol to avoid the spurious CS-changed interrupt that would otherwise occur during the frame sync sequence that precedes the opening flags.
If RDCR is configured to 1× mode, the delay is the greater of the two numbers listed. If
RDCR is configured to 8×, 16×, or 32× mode, the delay is the lesser of the two numbers
listed.
00 = Infinite—carrier sense is always active (default)
01 = 14 or 6.5 bit times as determined by the RDCR bits
10 = 4 or 1.5 bit times as determined by the RDCR bits (normally chosen for AppleTalk)
11 = 3 or 1 bit times as determined by the RDCR bits
RINV—DPLL Receive Input Invert Data
0 = No invert
1 = Invert the data before it is sent to the on-chip DPLL for reception. This setting is
used to produce FM1 from FM0, NRZI space from NRZI mark, etc. It may also be
used in regular NRZ mode to invert the data stream.
NOTE
This bit must be 0 in HDLC BUS mode.
TINV—DPLL Transmit Input Invert Data
0 = No invert
1 = Invert the data before it is sent to the on-chip DPLL for transmission. This setting
is used to produce FM1 from FM0, NRZI space from NRZI mark, etc. It may also
be used in regular NRZ mode to invert the data stream.
NOTE
This bit must be 0 in HDLC BUS mode.
In T1 applications, setting TINV and TEND creates a continuously inverted HDLC data stream.
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TPL—Tx Preamble Length
The TPL bits determine the length of the preamble configured by the TPP bits.
000 = No preamble (default)
001 = 8 bits (1 byte)
010 = 16 bits (2 bytes)
011 = 32 bits (4 bytes)
100 = 48 bits (6 bytes) (Select this setting for Ethernet operation.)
101 = 64 bits (8 bytes)
110 = 128 bits (16 bytes)
111 = Reserved
TPP—Tx Preamble Pattern
The TPP bits determine what, if any, bit pattern should precede the start of each transmit
frame. The preamble pattern will be sent prior to the first flag/sync of the frame. TPP is
ignored if the SCC is programmed to UART mode. The length of the preamble is programmed in TPL. The preamble pattern is typically transmitted to a receiving station that
uses a DPLL for clock recovery. The receiving DPLL uses the regular pattern of the preamble to help it lock onto the received signal in a short, predictable time period.
00 = All zeros
01 = Repeating 10’s (Select this setting for Ethernet operation.)
10 = Repeating 01’s
11 = All ones (Select this setting for LocalTalk operation.)
Tend—Transmitter Frame Ending
This bit is intended particularly for the NMSI transmitter encoding of the DPLL. Tend determines whether the TXD line should idle in a high state or in an encoded ones state
(which may be either high or low). It may, however, be used with other encodings besides
NMSI.
0 = Default operation. The TXD line is encoded only when data is transmitted (including the preamble and opening and closing flags/syncs). When no data is available
to transmit, the line is driven high.
1 = The TXD line is always encoded (even when idles are transmitted).
TDCR—Transmit Divide Clock Rate
The TDCR bits determine the divider rate of the transmitter. If the DPLL is not used, the
1× value should be chosen, except in asynchronous UART mode where 8×, 16×, or 32×
must be chosen. The user should program TDCR to equal RDCR in most applications.
If the DPLL is used in the application, the selection of TDCR depends on the encoding.
NRZI usualy requires 1×; whereas, FM0/FM1, Manchester, and Differential Manchester
allow 8×, 16×, or 32×. The 8× option allows highest speed; whereas, the 32× option provides the greatest resolution. TDCR is usually equal to RDCR to allow the same clock frequency source to control both the transmitter and receiver.
00 = 1× clock mode (Only NRZ or NRZI encodings are allowed.)
01 = 8× clock mode
10 = 16× clock mode (normally chosen for UART and AppleTalk)
11 = 32× clock mode
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RDCR—Receive DPLL Clock Rate
The RDCR bits determine the divider rate of the receive DPLL. If the DPLL is not used,
the 1× value should be chosen, except in asynchronous UART mode where 8×, 16×, or
32× must be chosen. The user should program RDCR to equal TDCR in most applications.
If the DPLL is used in the application, the selection of RDCR depends on the encoding.
NRZI usualy requires 1×; whereas, FM0/FM1, Manchester, and Differential Manchester
allow 8×, 16×, or 32×. The 8× option allows highest speed; whereas, the 32× option provides the greatest resolution.
00 = 1× clock mode (only NRZ or NRZI decodings are allowed.)
01 = 8× clock mode
10 = 16× clock mode (normally chosen for UART and AppleTalk)
11 = 32× clock mode
RENC—Receiver Decoding Method
Select NRZ if the DPLL is not used. The user should program RENC to equal TENC in
most applications. Do not use this internal DPLL for Ethernet mode.
000 = NRZ (default setting if DPLL is not used)
001 = NRZI Mark (set RINV also for NRZI Space)
010 = FM0 (set RINV also for FM1)
011 = Reserved
100 = Manchester
101 = Reserved
110 = Differential Manchester (Differential Biphase-L)
111 = Reserved
TENC—Transmitter Encoding Method
Select NRZ if the DPLL is not used. The user should program TENC to equal RENC in
most applications. Do not use this internal DPLL for Ethernet mode.
000 = NRZ (default setting if DPLL is not used)
001 = NRZI Mark (set TINV also for NRZI Space)
010 = FM0 (set TINV also for FM1)
011 = Reserved
100 = Manchester
101 = Reserved
110 = Differential Manchester (Differential Biphase-L)
111 = Reserved
DIAG—Diagnostic Mode
In normal operation mode, the SCC operates normally. The receive data enters the RXD
pin and the transmit data is shifted out through the TXD pin. The SCC uses the modem
signals (CD and CTS) to automatically enable and disable transmission and reception.
These timings are shown in 7.10.11 SCC Timing Control.
00 =Normal operation (CTS and CD signals under automatic control)
In local loopback mode, the transmitter output is internally connected to the receiver input,
while the receiver and the transmitter operate normally. The value on the RXD pin is ig-
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nored. Data can be programmed to appear on the TXD pin, or the TXD pin can remain
high by programming the port A register. The RTS line can also be programmed to be disabled in the appropriate parallel I/O register. In TDM modes, the L1TXDx and L1RQx lines
can be programmed to be either asserted normally or to remain inactive by programming
the serial interface mode register (SIMODE).
When using local loopback mode, the clock source for the transmitter and the receiver
must be the same. Thus, the same baud rate generator may be used for both transmitter
and receiver, or the same external CLKx pin may be used for both transmitter or receiver.
(Separate CLKx pins may be used with the transmitter and receiver as long as the CLKx
pins are connected to the same external clock signal source.)
01 =Local loopback mode
NOTE
If external loopback is desired, the DIAG bits should be selected
for normal operation, and an external connection should be
made between the TXD and RXD pins. Clocks may be generated internally by a baud rate generator or generated externally.
The user may physically connect the appropriate control signals
(RTS connected to CD, and CTS grounded) or the port C register may be used to cause the CD and CTS pins to be permanently asserted to the SCC.
In automatic echo mode, the channel automatically retransmits the received data on a bitby-bit basis using whatever receive clock is provided. The receiver operates normally and
can receive data if CD is asserted. The transmitter simply transmits received data. In this
mode, the CTS line is ignored.
The echo function may also be accomplished in software by receiving buffers from an
SCC, linking them to Tx BDs and then transmitting them back out of that SCC.
10 = Automatic echo mode
In loopback/echo mode, loopback operation and echo operation occur simultaneously.
The CD pin and CTS pins are ignored. See the loopback bit description for clocking requirements.
11 = Loopback and echo mode
NOTE
Users familiar with the MC68302 may notice that the QUICC
does not contain "software operation" mode. The software operation mode as implemented on the MC68302 can be implemented on the QUICC using parallel I/O port C.
ENR—Enable Receive
This bit enables the receiver hardware state machine for this SCC. When ENR is cleared,
the receiver is disabled, and any data in the receive FIFO is lost. If ENR is cleared during
reception, the receiver aborts the current character. ENR may be set or cleared regard-
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less of whether serial clocks are present. See 7.10.14 Disabling the SCCs on the Fly for
a description of the proper methods to disable and reenable an SCC.
NOTE
Freescale Semiconductor, Inc...
The SCC provides other tools to control reception besides the
ENR bit. They are the ENTER HUNT MODE command, the
CLOSE Rx BD command, and the E-bit in the Rx BD.
ENT—Enable Transmit
This bit enables the transmitter hardware state machine for this SCC. When ENT is
cleared, the transmitter is disabled. If ENT is cleared during transmission, the transmitter
aborts the current character, and the TXD pin returns to the idle state. Data already in the
transmit shift register will not be transmitted. ENT may be set or cleared regardless of
whether serial clocks are present. See 7.10.14 Disabling the SCCs on the Fly for a description of the proper methods to disable and reenable an SCC.
NOTE
The SCC provides other tools to control transmission besides
the ENT bit. They are the STOP TRANSMIT command, the
GRACEFUL STOP TRANSMIT command, the RESTART
TRANSMIT command, the freeze option in UART mode, the
CTS flow control option in UART mode, and the ready (R) bit in
the Tx BD.
MODE—Channel Protocol mode
0000 = HDLC
0001 = Reserved
0010 = AppleTalk (LocalTalk)
0011 = SS7 (reserved for RAM microcode)
0100 = UART
0101 = Profibus (reserved for RAM microcode)
0110 = Async HDLC (reserved for RAM microcode)
0111 = V.14 (reserved for RAM microcode)
1000 = BISYNC
1001 = DDCMP (reserved for RAM microcode)
1010 = Reserved
1011 = Reserved
1100 = Ethernet
11xx = Reserved
7.10.3 SCC Protocol-Specific Mode Register (PSMR)
The functionality of the SCC varies according to the protocol selected by the MODE bits in
the GSMR. Each of the four SCC has an additional 16-bit, memory-mapped, read-write
PSMR that configures the SCC to the special configurations within a chosen mode. A
detailed description of the PSMR bits is contained within each specific protocol. The PSMRs
are cleared at reset.
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7.10.4 SCC Data Synchronization Register (DSR)
Each of the four SCC has a 16-bit, memory-mapped, read-write DSR. The DSR specifies
the pattern used in the frame synchronization procedure in the synchronous protocols. In
the UART protocol, it is used to configure fractional stop bit transmission. In the BISYNC and
totally transparent protocol, it should be programmed with the desired SYNC pattern. In the
Ethernet protocol, it should be programmed with $D555. At reset, it defaults to $7E7E (two
HDLC flags), so it does not need to be written for HDLC mode. When DSR is used to send
out SYNCs (such as in BISYNC or transparent mode), the contents of the DSR are always
transmitted LSB first.
15
14
13
12
11
10
9
8
7
6
5
4
Freescale Semiconductor, Inc...
SYN2
3
2
1
0
SYN1
7.10.5 SCC Transmit on Demand Register (TODR)
If no frame is currently being transmitted by an SCC, the RISC controller periodically polls
the R-bit of the next Tx BD to see if the user has requested a new frame/buffer to be transmitted. This polling algorithm depends on the SCC configuration, but occurs every 8 to 32
serial transmit clocks. The user, however, has an option to request that the RISC begin the
processing of the new frame/buffer immediately, without waiting until the normal polling
time. To obtain immediate processing, the TOD bit in the transmit-on-demand register is set
by the user once the user has set the R-bit in the Tx BD.
This feature, which decreases the transmission latency of the transmit buffer/frame, is particularly useful in LAN-type protocols where maximum interframe GAP times are limited by
the protocol specification. Since the transmit-on-demand feature gives a high priority to the
specified Tx BD, it can conceivably affect the servicing of the other SCC FIFOs. Therefore,
it is recommended that the transmit-on-demand feature only be used when a high-priority
Tx BD has been prepared and transmission on this SCC has not occurred for a period of
time.
The TOD bit does not need to be set if a new Tx BD is added to the circular queue but other
Tx BDs in that queue have not fully completed transmission. In that case, the new Tx BD will
be processed immediately following the completion of the older Tx BD s.
The first bit of the frame will typically be clocked out 5-6 bit times after TOD has been written
to a 1.
TOD—Transmit on Demand
15
TOD
14
13
12
11
10
9
8
7
—
6
5
4
3
2
1
0
0 = Normal operation
1 = The RISC will give a high priority to the current Tx BD and will not wait for the normal polling time to check that the Tx BD’s R-bit has been set. It will begin transmitting the frame. This bit will be cleared automaticaly after one serial clock.
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Bits 14–0—Reserved
These bits should be written with zeros.
7.10.6 SCC Buffer Descriptors
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Data associated with each SCC channel is stored in buffers. Each buffer is referenced by a
BD, which may be located anywhere in internal memory. The QUICC internal memory has
space for 224 BDs to be shared between the four SCCs and any SMCs and SPIs that are
used. However, the allocation of BDs to the transmitter or receiver of a serial channel is
user-defined. Thus, the user may select 100 BDs for the SCC1 receiver, 20 BDs for the
SCC1 transmitter, etc.
The BD table forms a circular queue with a programmable length. The user can program the
start address of each channel BD table in the internal memory (see Figure 7-38). The user
is allowed to allocate the parameter area of an unused channel to the other used channels
as BD tables or as actual buffers.
The format of the BDs is the same for each SCC mode of operation and for both transmit
and receive. The first word in each BD contains a status and control word, which also determines the BD table length. Only this first field (containing the status and control bits) differs
for each protocol. The second word determines the data length referenced to this BD, and
the two last words in the BD contain the 32-bit address pointer that points to the actual buffer
in memory.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
150
STATUS AND CONTROL
DATA LENGTH
HIGH-ORDER DATA BUFFER POINTER
LOW-ORDER DATA BUFFER POINTER
For frame-oriented protocols, a message may reside in as many buffers as necessary
(transmit or receive). Each buffer has a maximum length of (64K–1)bytes. The CP does not
assume that all buffers of a single frame are currently linked to the BD table; it does assume,
however, that the unlinked buffers will be provided by the CPU32+ core in time to be either
transmitted or received. Failure to do so will result in an error condition being reported by
the CP. An underrun error is reported in the case of transmit, and a busy error is reported in
the case of receive.
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Controllers (SCCs)
DUAL-PORT RAM
EXTERNAL MEMORY
TX BUFFER DESCRIPTORS
FRAME STATUS
DATA LENGTH
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SCC1 TX BD
TABLE
DATA POINTER
TX DATA BUFFER
RX BUFFER DESCRIPTORS
SCC1 RX BD
TABLE
FRAME STATUS
DATA LENGTH
SCC1 RX BD
TABLE POINTER
DATA POINTER
RX DATA BUFFER
SCC1 TX BD
TABLE POINTER
Figure 7-38. SCC Memory Structure
All protocols can have their buffer descriptors point to data buffers that are located in internal
dual-port RAM. Typically, however, due to the internal RAM being used for buffer descriptors, it is customary for the data buffers to be located in external RAM, especially if the data
buffers are large in size. In all cases, the IMB is used to transfer the data to the data buffer.
The CP processes the Tx BDs in a straightforward fashion. Once the transmit side of an
SCC is enabled, it starts with the first BD in that SCC’s transmit table. Once the CP detects
that the Tx BD R-bit was set, it will begin processing the buffer. (The CP will detect that the
BD is ready either by polling the R-bit periodically or by the user writing to the transmit-ondemand register (TODR).) Once the data from the BD has been placed in the transmit FIFO,
the CP moves on to the next BD, again waiting for that BD’s R-bit to be set. Thus, the CP
does no look-ahead BD processing, nor does it skip over BDs that are not ready. When the
CP sees the wrap (W) bit set in a BD, it goes back to the beginning of the BD table after
processing of the BD is complete. After using a BD, the CP normally sets the R-bit to not-
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ready; thus, the CP will not use a BD twice until the BD has been confirmed by the CPU32+
core. (The one exception to this rule is that the QUICC supports an option for repeated transmission, called the continuous mode, whereby the R-bit is left in the ready position. This is
available in some protocols.)
The CP uses the Rx BDs in a similar fashion. Once the receive side of an SCC is enabled,
it starts with the first BD in that SCC’s Rx BD table. Once data arrives from the serial line
into the SCC, the CP performs certain required protocol processing on the data and moves
the resultant data to the data buffer pointed to by the first BD. Use of a BD is complete when
there is no more room left in the buffer or when certain events occur, such as detection of
an error or an end-of-frame. Whatever the reason, the buffer is then said to be closed, and
additional data will be stored using the next BD. Whenever the CP needs to begin using a
BD because new data is arriving, it will check the E-bit of that BD. If the current BD is not
empty, it will report a busy error. However, it will not move from the current BD until it
becomes empty. When the CP sees the W-bit set in a BD, it goes back to the beginning of
the BD table after processing of the BD is complete. After using a BD, the CP sets the E-bit
to not-empty; thus, the CP will never use a BD twice until the BD has been processed by the
CPU32+ core. (The one exception to this rule is that the QUICC supports an option for
repeated reception, called the continuous mode, whereby the E-bit is left in the empty position. This is available in some protocols.)
7.10.7 SCC Parameter RAM
Each SCC parameter RAM area begins at the same offset from each SCC base area. The
protocol-specific portions of the SCC parameter RAM are discussed in the specific protocol
descriptions. The part of the SCC parameter RAM that is the same for all SCC protocols is
shown in Table 7-5.
Certain parameter RAM values (marked in boldface) need to be initialized by the user before
the SCC is enabled; other values are initialized/written by the CP. Once initialized, most
parameter RAM values will not need to be accessed in user software since most of the activity is centered around the transmit and Rx BDs, not the parameter RAM. However, if the
parameter RAM is accessed by the user, the following regulations should be noted. The
parameter RAM can be read at any time. The parameter time values related to the SCC
transmitter can only be written whenever the transmitter is disabled (see 7.10.14 Disabling
the SCCs on the Fly), after a STOP TRANSMIT and before a RESTART TRANSMIT command, or after the buffer/frame completes transmission as a result of a GRACEFUL STOP
TRANSMIT command and before a RESTART TRANSMIT command. The parameter RAM
values related to the SCC receiver can only be written when the receiver is disabled (see
7.10.14 Disabling the SCCs on the Fly).
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Controllers (SCCs)
Table 7-5. SCC Parameter RAM Common to All Protocols
Address
Name
Width
SCC Base + 00
RBASE
Word
Rx BD Base Address
SCC Base + 02
TBASE
Word
Tx BD Base Address
SCC Base + 04
RFCR
Byte
Rx Function Code
SCC Base + 05
TFCR
Byte
Tx Function Code
SCC Base + 06
MRBLR
Word
Maximum Receive Buffer Length
SCC Base + 08
RSTATE
Long
Rx Internal State
Long
Rx Internal Data Pointer
Word
Rx BD Pointer
SCC Base + 12
Word
Rx Internal Byte Count
SCC Base + 14
Long
Rx Temp
Long
Tx Internal State
Long
Tx Internal Data Pointer
Word
Tx BD Pointer
SCC Base + 22
Word
Tx Internal Byte Count
SCC Base + 24
Long
Tx Temp
SCC Base + 0C
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SCC Base + 10
RBPTR
SCC Base + 18
TSTATE
SCC Base + 1C
SCC Base + 20
TBPTR
Description
SCC Base + 28
RCRC
Long
Temp Receive CRC
SCC Base + 2C
TCRC
Long
Temp Transmit CRC
SCC Base + 30
First Word of Protocol-Specific Area
SCC Base + xx
Last Word of Protocol-Specific Area
NOTE: The items in boldface should be initialized by the user.
7.10.7.1 BD TABLE POINTER (RBASE, TBASE). The RBASE and TBASE entries define
the starting location in the dual-port RAM for the set of BDs for receive and transmit functions of the SCC. This provides a great deal of flexibility in how BDs for an SCC are partitioned. By selecting RBASE and TBASE entries for all SCCs, and by setting the W-bit in the
last BD in each BD list, the user may select how many BDs to allocate for the transmit and
receive side of every SCC. The user must initialize these entries before enabling the corresponding channel. Furthermore, the user should not configure BD tables of two enabled
SCCs to overlap, or erratic operation will occur.
NOTE
RBASE and TBASE should contain a value that is divisible by 8.
7.10.7.2 SCC FUNCTION CODE REGISTERS (RFCR, TFCR). There are eight separate
function code registers for the four SCC channels: four for receive data buffers (RFCRx) and
four for transmit data buffers (TFCRx). The FC entry contains the value that the user would
like to appear on the function code pins FC3–FC0 when the associated SDMA channel
accesses memory. It also controls the byte-ordering convention to be used in the transfers.
Receive Function Code Register
7
MOTOROLA
6
—
5
4
MOT
3
2
1
FC3–FC0
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Bits 7–5—Reserved
MOT—Motorola
This bit should be set by the user to achieve normal operation. If this bit is modified on the
fly, it will take effect at the beginning of the next frame (Ethernet, HDLC, and transparent)
or at the beginning of the next BD otherwise. MOT must be set if the data buffer is located
in external memory and has a 16-bit wide port size.
0 = Intel convention is used for byte ordering—swapped operation. It is also called little-endian byte ordering. The bytes stored in each buffer word are reversed as
compared to the Motorola mode.
1 = Motorola byte ordering—normal operation. It is also called big-endian byte ordering. As data is received from the serial line and put into the buffer, the most significant byte of the buffer word contains data received earlier than the least significant
byte of the same buffer word.
FC3–FC0—Function Code 3–0
These bits contain the function code value used during this SDMA channel’s memory accesses. It is suggested that the user write bit FC3 with a one, to identify this SDMA channel access as a DMA-type access. Example: FC3–FC0 = 1000 (binary). Do not write the
value 0111 (binary) to these bits.
Transmit Function Code Register
7
6
—
5
4
MOT
3
2
1
FC3–FC0
0
Bits 7–5—Res