Z86E04/E08 1 CMOS Z8 OTP M

P RELIMINARY P RODUCT S PECIFICATION

1

Z86E04/E08

CMOS Z8 OTP M ICROCONTROLLERS

1

PRODUCT DEVICES

Part

Number

Z86E0412PEC

Z86E0412PSC1866

Z86E0412PSC1903

Z86E0412PEC1903

Z86E0412SEC

Z86E0412SSC1866

Z86E0412SSC1903

Z86E0412SEC1903

Z86E0812PEC

Z86E0812PSC1866

Z86E0812PSC1903

Z86E0812PEC1903

Z86E0812SEC

Z86E0812SSC1866

Z86E0812SSC1903

Z86E0812SEC1903

Oscillator

Type

Crystal

Crystal

RC

RC

Crystal

Crystal

RC

RC

Crystal

Crystal

RC

RC

Crystal

Crystal

RC

RC

Operating

V

CC

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

4.5V–5.5V

Operating

Temperature

–40

°

C/105

°

C

0

°

C/70

°

C

0

°

C/70

°

C

–40

°

C/105

°

C

–40

°

C/105

°

C

0

°

C/70

°

C

0

°

C/70

°

C

–40

°

C/105

°

C

–40

°

C/105

°

C

0

°

C/70

°

C

0

°

C/70

°

C

–40

°

C/105

°

C

–40

°

C/105

°

C

0

°

C/70

°

C

0

°

C/70

°

C

–40

°

C/105

°

C

ROM

(KB)

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

Package

18-Pin DIP

18-Pin DIP

18-Pin DIP

18-Pin DIP

18-Pin SOIC

18-Pin SOIC

18-Pin SOIC

18-Pin SOIC

18-Pin DIP

18-Pin DIP

18-Pin DIP

18-Pin DIP

18-Pin SOIC

18-Pin SOIC

18-Pin SOIC

18-Pin SOIC

Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the user’s application requirements.

DS97Z8X1104 P R E L I M I N A R Y 1

Z86E04/E08

CMOS Z8 OTP Microcontrollers

FEATURES

■ 14 Input/Output Lines

■ Six Vectored, Prioritized Interrupts

(3 falling edge, 1 rising edge, 2 timers)

■ Two Analog Comparators

■ Program Options:

– Low Noise

– ROM Protect

– Auto Latch

– Watch-Dog Timer (WDT)

– EPROM/Test Mode Disable

Zilog

■ Two Programmable 8-Bit Counter/Timers, Each with

6-Bit Programmable Prescaler

■ WDT/ Power-On Reset (POR)

■ On-Chip Oscillator that Accepts XTAL, Ceramic

Resonance, LC, RC, or External Clock

■ Clock-Free WDT Reset

■

■

■

Low-Power Consumption (50 mw typical)

Fast Instruction Pointer (1

µ s @ 12 MHz)

RAM Bytes (125)

GENERAL DESCRIPTION

Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time

Programmable (OTP) members of Zilog’s single-chip Z8

®

MCU family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions.

For applications demanding powerful I/O capabilities, the

Z86E04/E08's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel

I/O.

Two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications.

Note: All Signals with an overline, “ ”, are active Low, for example: B/W (WORD is active Low); B/W (BYTE is active

Low, only).

Power connections follow conventional descriptions below:

Connection

Power

Ground

Circuit

V

CC

GND

Device

V

DD

V

SS

2 P R E L I M I N A R Y DS97Z8X1104

Zilog

Input

Port 3

Counter/

Timers (2)

Interrupt

Control

Two Analog

Comparators

Vcc GND

Z86E04/E08


XTAL

1

Machine

Timing & Inst.

Control

ALU

FLAG

OTP

Register

Pointer

General-Purpose

Register File

Program

Counter

Port 2 Port 0

I/O

(Bit Programmable)

I/O

Figure 1. Functional Block Diagram


Z86E04/E08


GENERAL DESCRIPTION (Continued)

D7–0

Z8 MCU

AD 10–0

Address

MUX

AD 10–0

EPROM

D7–0

Data

MUX

Clear

P00

Clock

P01

Address

Counter

3 bits

AD 10–0

PGM

Mode Logic

ROM PROT

Low Noise

D7–0

Z8

Port 2

VPP

P33

EPM

P32

CE

XT1

PGM

P30

Figure 2. EPROM Programming Mode Block Diagram

OE

P31

Zilog


Z86E04/E08

CMOS Z8 OTP Microcontrollers Zilog

PIN DESCRIPTION

D4

D5

D6

D7

V

CC

NC

CE

OE

EPM

1

9

18

10

D3

D2

D1

D0

GND

PGM

CLOCK

CLEAR

V

PP

P24

P25

P26

P27

V

CC

XTAL2

XTAL1

P31

P32

1

9

18

10

P23

P22

P21

P20

GND

P02

P01

P00

P33

Figure 3. 18-Pin EPROM Mode Configuration

Figure 4. 18-Pin DIP/SOIC Mode Configuration

Table 1. 18-Pin DIP Pin Identification

EPROM Programming Mode

Pin # Symbol Function

1–4

5

8

9

6

7

10

11

12

13

14

15–18

D4–D7

V

CC

NC

CE

OE

EPM

V

PP

Clear

Clock

PGM

GND

D0–D3

Data 4, 5, 6, 7

Power Supply

No Connection

Chip Enable

Output Enable

EPROM Prog Mode

Prog Voltage

Clear Clock

Address

Prog Mode

Ground

Data 0,1, 2, 3

Direction

In/Output

Input

Input

Input

Input

Input

Input

Input

In/Output

Table 2. 18-Pin DIP/SOIC Pin Identification

Standard Mode

Pin # Symbol Function

1–4

5

P24–P27 Port 2, Pins 4,5,6,7

V

CC

XTAL2

Power Supply

Crystal Osc. Clock 6

7

8

9

10

XTAL1

P31

P32

P33

Crystal Osc. Clock

Port 3, Pin 1, AN1

Port 3, Pin 2, AN2

Port 3, Pin 3, REF

11–13 P00–P02 Port 0, Pins 0,1,2

14 GND Ground

15–18 P20–P23 Port 2, Pins 0,1,2,3

Direction

In/Output

Output

Input

Input

Input

Input

In/Output

In/Output

1


Z86E04/E08


ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power

Zilog dissipation should not exceed 462 mW for the package.

Power dissipation is calculated as follows:

Total Power Dissipation = V

DD

x [I

DD

–(sum of I

OH

)]

+ sum of [(V

DD

–V

OH

) x I

OH

]

+ sum of (V

0L

x I

0L

)

Parameter Min

Ambient Temperature under Bias

Storage Temperature

–40

–65

Voltage on any Pin with Respect to V

SS

Voltage on V

DD

Pin with Respect to V

SS

–0.7

–0.3

Voltage on Pins 7, 8, 9, 10 with Respect to V

SS

–0.6

Total Power Dissipation

Maximum Allowable Current out of V

SS

Maximum Allowable Current into V

DD

Maximum Allowable Current into an Input Pin –600

–600 Maximum Allowable Current into an Open-Drain Pin

Maximum Allowable Output Current Sinked by Any I/O Pin

Maximum Allowable Output Current Sourced by Any I/O Pin

Total Maximum Output Current Sinked by a Port

Total Maximum Output Current Sourced by a Port

Max

+105

+150

+12

+7

V

DD

+1

1.65

300

220

+600

+600

25

25

60

45

Notes:

1. This applies to all pins except where otherwise noted. Maximum current into pin must be

±

600

µ

A.

2. There is no input protection diode from pin to V

DD

(not applicable to EPROM Mode).

3. This excludes Pin 6 and Pin 7.

4. Device pin is not at an output Low state.

Units Note

V

V

C

C

V

W mA mA

µ

A

µ

A mA mA mA mA

1

2

3

4


Zilog

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to

Ground. Positive current flows into the referenced pin (Figure 5).

From Output

Under Test

Z86E04/E08


150 pF

1

Figure 5. Test Load Diagram

CAPACITANCE

T

A

= 25

°

C, V

CC

= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

Parameter

Input capacitance

Output capacitance

I/O capacitance

Min

0

0

0

Max

10 pF

20 pF

25 pF


Z86E04/E08


DC ELECTRICAL CHARACTERISTICS

Standard Temperature

Zilog

Sym

V

V

V

V

V

V

V

V

INMAX

Parameter

Max Input Voltage

I

V

OFFSET

Comparator Input

Offset Voltage

V

LV

IL

V

CC

Low Voltage

Auto Reset

Input Leakage

(Input Bias Current of

Comparator)

I

OL

Output Leakage

V

CH

CL

IH

IL

OH

OL1

OL2

ICR

Clock Input High

Voltage

Clock Input Low

Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Output Low Voltage

Comparator Input

Common Mode

Voltage Range

V

CC

[4]

4.5V

5.5V

4.5V

T

A

= 0

°

C to +70

°

C

Min Max

0.8 V

CC

12

12

V

CC

+0.3

5.5V

4.5V

5.5V

0.8 V

V

V

SS

SS

CC

V

CC

+0.3

–0.3

0.2 V

–0.3

0.2 V

4.5V

5.5V

0.7 V

CC

0.7 V

CC

4.5V

5.5V

V

SS

–0.3

V

SS

–0.3

4.5V

V

CC

–0.4

5.5V

V

CC

–0.4

4.5V

V

CC

–0.4

5.5V

V

CC

–0.4

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

2.2

–1.0

–1.0

V

CC

+0.3

V

CC

+0.3

0.2 V

CC

0.2 V

CC

0.8

0.4

0.4

0.4

0.8

0.8

25.0

25.0

3.0

1.0

1.0

CC

CC

1.5

1.5

0.1

0.1

0.1

0.8

0.8

10.0

10.0

2.8

4.8

4.8

4.8

4.8

0.1

Typical

@ 25

°

C Units Conditions Notes

V I

In

<250

µ

A 1

V I

In

µ

A 1

2.8

V Driven by External

Clock Generator

2.8

1.7


Clock Generator


Clock Generator

1.7

2.8

2.8

V

V


Clock Generator

V

V

V I

OH

= –2.0 mA

V I

OH

= –2.0 mA

V Low Noise @ I

OH

= –0.5 mA

V Low Noise @ I

OH

= –0.5 mA

V I

OL

= +4.0 mA

V I

OL

= +4.0 mA

V Low Noise @ I

OL

= 1.0 mA

V Low Noise @ I

OL

= 1.0 mA

V I

OL

= +12 mA,

V I

OL

= +12 mA, mV mV

V @ 6 MHz Max.

Int. CLK Freq.

µ

A V

IN

= 0V, V

CC

µ

A V

IN

= 0V, V

CC

5

5

5

5

5

5

4.5V

5.5V

–1.0

–1.0

0 V

1.0

1.0

–1.0

µ

A V

IN

µ

A V

IN

= 0V, V

CC

V

= 0V, V

CC


Zilog

I

Sym Parameter

CC

Supply Current

I

CC1

Standby Current

I

CC

Supply Current

(Low Noise Mode)

Z86E04/E08


V

CC

[4]

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

T

A

= 0

°

C to +70

°

C Typical

Min Max @ 25

°

C Units Conditions

11.0 6.8

11.0

15.0

15.0

20.0

20.0

4.0

4.0

5.0

5.0

7.0

7.0

11.0

11.0

13.0

13.0

15.0

15.0

6.8

8.2

8.2

12.0

12.0

2.5

2.5

3.0

3.0

4.0

4.0

6.8

6.8

7.5

7.5

8.2

8.2

mA All Output and I/O Pins

Floating @ 2 MHz mA All Output and I/O Pins





Floating @ 12 MHz mA HALT Mode V

IN

= 0V,

V

CC

@ 2 MHz mA HALT Mode V

IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC

@ 12 MHz mA All Output and I/O Pins






Floating @ 4 MHz

Notes

5,7

5,7

5,7

5,7

5,7

5,7

5,7

5,7

5,7

5,7

5,7

5,7

7

7

7

7

7

7

1


Z86E04/E08


DC ELECTRICAL CHARACTERISTICS (Continued)

Zilog

I

I

I

I

Sym Parameter

CC1

CC2

ALL

ALH

Standby Current

(Low Noise Mode)

Standby Current

Auto Latch Low

Current

Auto Latch High

Current

V

CC

[4]

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

T

A

= 0

°

C to +70

°

C Typical

Min Max @ 25

°


4.0

2.5

4.0

4.5

4.5

5.0

5.0

10.0

10.0

32.0

32.0

–16.0

–16.0

2.5

2.8

2.8

3.0

3.0

1.0

1.0

16

16

–8.0

–8.0

mA HALT Mode V

IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC

@ 4 MHz

µ

A STOP Mode V

IN

= 0V, V

CC

WDT is not Running

µ

A STOP Mode V

IN

= 0V,V

CC

WDT is not Running

µ

A 0V < V

IN

< V

CC

µ

A 0V < V

IN

< V

CC

µ

A 0V < V

IN

< V

CC

µ

A 0V < V

IN

< V

CC

Notes

7

7

7

7

7

7

7,8

7,8

Notes:

1. Port 2 and Port 0 only

2. V

SS

= 0V = GND

3. The device operates down to V

LV

of the specified frequency for V

LV .

The minimum operational V

CC

is determined on the value of the voltage V

LV

at the ambient temperature. The V

LV

increases as the temperature decreases.

4. V

CC

= 4.5 to 5.5V, typical values measured at V

The V

CC

CC

= 5.0V.

voltage specification of 5.5 V guarantees 5.0 V

±

0.5V with typical values measured at V

CC

= 5.0V.

5. Standard Mode (not Low EMI Mode)

6. Z86E08 only

7. All outputs unloaded and all inputs are at V

CC

or V

SS

level.

8. If analog comparator is selected, then the comparator inputs must be at V

CC

level.


Zilog

DC ELECTRICAL CHARACTERISTICS

Extended Temperature

Z86E04/E08


Sym

V

V

V

INMAX

CH

CL

Parameter

Max Input Voltage

Clock Input High

Voltage

Clock Input Low

Voltage

V

CC

[4]

4.5V

5.5V

5.5V

4.5V

5.5V

V

V

T

A

= –40

°

C to

+105

°

C

Min

4.5V

0.8 V

CC

0.8 V

SS

SS

CC

V

V

Max

12.0

12.0

CC

CC

+0.3

+0.3

–0.3

0.2 V

–0.3

0.2 V

CC

CC

I

I

V

V

V

V

V

IH

IL

OH

OL1

OL2

V

OFFSET

V

LV

IL

OL

V

ICR

Input High Voltage 4.5V

0.7 V

CC

5.5V

V

CC

–0.4

4.5V

V

CC

–0.4

5.5V

V

CC

–0.4

Output Low Voltage 4.5V

V

CC

+0.3

Input Low Voltage

5.5V

0.7 V

CC

V

CC

+0.3

4.5V

V

SS

–0.3

0.2 V

CC

5.5V

V

SS

–0.3

0.2 V

CC

Output High Voltage 4.5V

V

CC

–0.4

0.4

5.5V

4.5V

5.5V

Output Low Voltage 4.5V

Comparator Input

Offset Voltage

V

CC

Low Voltage

Auto Reset

Input Leakage

(Input Bias Current of Comparator)

Output Leakage

Comparator Input

Common Mode

Voltage Range

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

1.8

0.4

0.4

0.4

1.0

1.0

25.0

25.0

3.8

–1.0

–1.0

–1.0

–1.0

0 V

CC

–1.5

Typical

@ 25

°


V I

IN

< 250

µ

A

V I

IN

< 250

µ

A

2.8


Clock Generator

2.8

1.7


Clock Generator


Clock Generator

1.7

2.8


Clock Generator

V

2.8

1.5

1.5

4.8

4.8

0.1

0.1

0.1

0.1

0.3

0.3

10.0

10.0

2.8

1.0

1.0

V

V

V

V I

OH

= –2.0 mA

V I

OH

= –2.0 mA

V Low Noise @ I

OH

= –0.5 mA

V Low Noise @ I

OH

= –0.5 mA

V I

OL

= +4.0 mA

V I

OL

= +4.0 mA

V Low Noise @ I

OL

= 1.0 mA

V Low Noise @ I

OL

= 1.0 mA

V I

OL

= +12 mA,

V I

OL

= +12 mA, mV mV

V @ 6 MHz Max. Int.

CLK Freq.

µ

A V

IN

= 0V, V

CC

µ

A V

IN

= 0V, V

CC

Notes

1

1

5

5

5

5

5

5

3

1.0

1.0

µ

A V

IN

= 0V, V

CC

µ

A V

IN

= 0V, V

CC

V

1


Z86E04/E08


DC ELECTRICAL CHARACTERISTICS (Continued)

I

Sym Parameter

CC

Supply Current

I

CC1

I

CC

Standby Current

Supply Current

(Low Noise Mode)

V

CC

[4]

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

T

A

= –40

°

C to

+105

°

C

Min Max

11.0

11.0

15.0

15.0

20.0

20.0

5.0

5.0

5.0

5.0

7.0

7.0

11.0

11.0

13.0

13.0

15.0

15.0

Typical

@ 25

°

C Units

6.8

6.8

8.2

8.2

12.0

12.0

2.5

2.5

3.0

3.0

4.0

4.0

6.8

6.8

7.5

7.5

8.2

8.2

Conditions mA All Output and I/O Pins






Floating @ 12 MHz mA HALT Mode V

IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC

@ 12 MHz mA All Output and I/O Pins






Floating @ 4 MHz

Zilog

5,7

5,7

5,7

7

7

7

7

7

7

5,7

5,7

5,7

5,7

Notes

5,7

5,7

5,7

5,7

5,7


Zilog

Z86E04/E08


I

I

I

I

Sym

CC1

CC2

ALL

ALH

Parameter

Standby Current

(Low Noise Mode)

Standby Current

Auto Latch Low

Current

Auto Latch High

Current

V

CC

[4]

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

T

A

= –40

°

C to +105

°

C

Min Max

4.0

4.0

4.5

4.5

5.0

5.0

20

20

40

40

–20.0

–20.0

Typical

@ 25

°


2.5

2.5

2.8

2.8

3.0

3.0

1.0

1.0

16

16

–8.0

–8.0

mA HALT Mode V

IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC


IN

= 0V,

V

CC

@ 4 MHz

µ

A STOP Mode V

IN

= 0V, V

CC

WDT is not Running

µ

A STOP Mode V

IN

= 0V, V

CC

WDT is not Running

µ

A 0V < V

IN

< V

CC

µ

A 0V < V

IN

< V

CC

µ

A 0V < V

IN

< V

CC

µ

A 0V < V

IN

< V

CC

Notes

7

7

7

7

7

7

7,8

7,8

Notes:

1. Port 2 and Port 0 only

2. V

SS

= 0V = GND

3. The device operates down to V

LV

of the specified frequency for V

LV .

The minimum operational V

CC

is determined on the value of the voltage V

LV

at the ambient temperature. The V

LV

increases as the temperature decreases.

4. V

CC

= 4.5V to 5.5V, typical values measured at V

CC

= 5.0V

5. Standard Mode (not Low EMI Mode)

6. Z86E08 only

7. All outputs unloaded and all inputs are at V

CC

or V

SS

level.

8. If analog comparator is selected, then the comparator inputs must be at V

CC

level.

1


Z86E04/E08


AC ELECTRICAL CHARACTERISTICS

1

Clock

7 7

2

T

IN

4

6

5

IRQ

N

2

3

8 9

Figure 6. AC Electrical Timing Diagram

3

Zilog


Zilog


Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)

Standard Temperature

Z86E04/E08


1

2

3

4

5

6

7

8

9

10

11

15

No Symbol

TpC

TrC,TfC

TwC

TwTinL

TwTinH

TpTin

TrTin,

TtTin

TwIL

TwIH

Twdt

Tpor

Parameter

Input Clock Period

Clock Input Rise and Fall Times

Input Clock Width

Timer Input Low Width

Timer Input High Width

Timer Input Period

Timer Input Rise and Fall Time

Int. Request Input

Low Time

Int. Request Input

High Time

Watch-Dog Timer

Delay Time for Timeout

Power-On Reset Time

V

CC

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

8 MHz

Min

125

125

62

62

100

70

5TpC

5TpC

70

70

Notes:

1. Timing Reference uses 0.7 V

CC

for a logic 1 and 0.2 V

CC

for a logic 0.

2. Interrupt request through Port 3 (P33–P31).

12

12

20

20

T

A

= 0

°

C to +70

°

C

DC

DC

25

25

83

83

5TpC

5TpC

8TpC 8TpC

8TpC 8TpC

100

100

41

41

100

70

70

70

5TpC 5TpC

5TpC 5TpC

80

80

12

12

20

20

12 MHz

Max Min Max

DC

DC

15

15

100

100

80

80

Units ns ns ns ns ns ns ns ns ms ms ms ms ns ns ns ns

Notes

1

1

1,2

1,2

1

1

1

1

1

1

1

1

1

1

1

1

1,2

1,2

1

1

1

1

1


Z86E04/E08



Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)

Extended Temperature

1

2

3

4

5

6

7

8

9

10

11

No Symbol

TpC

TrC,TfC

TwC

TwTinL

TwTinH

TpTin

TrTin,

TtTin

TwIL

TwIH

Twdt

Tpor

Parameter

Input Clock Period


Input Clock Width



Timer Input Period


Int. Request Input

Low Time

Int. Request Input

High Time

Watch-Dog Timer


Power-On Reset Time

V

CC

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

Min

125

125

70

70

T

A

= –40

°

C to +105

°

C

8 MHz

5TpC

5TpC

8TpC

8TpC

70

70

5TpC

5TpC

10

10

12

12

Notes:


CC


CC

for a logic 0.

2. Interrupt request made through Port 3 (P33–P31).

Max

DC

DC

25

25

62

62

100

100

100

100

Min

83

83

70

70

70

70

5TpC

5TpC

10

10

12

12

12 MHz

5TpC

5TpC

8TpC

8TpC

Max

DC

DC

15

15

41

41

100

100

100

100

Zilog

Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms

1

1

1,2

1,2

1

1

1

1

1

1

1

1

1

1

1

1

1,2

1,2

1

1

1

1


Zilog


Low Noise Mode, Standard Temperature

Z86E04/E08


No

1

2

3

4.

5

6

7

8

9

10

Symbol

TPC

TrC

TfC

TwC

TwTinL

TwTinH

TpTin

TrTin,

TtTin

TwIL

Low Time

TwIH

High Time

Twdt

Parameter

Input Clock Period


Input Clock Width



Timer Input Period


Int. Request Input

Int. Request Input

Watch-Dog Timer


V

CC

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

Notes:


CC


CC

for a logic 0.


500

500

70

70

2.5TpC

2.5TpC

4TpC

4TpC

Min

T

A

= 0

°

C to +70

°

C

1 MHz 4 MHz

Max Min Max

1000

1000

DC

DC

25

25

250

250

DC

DC

25

25

125

125

70

70

2.5TpC

2.5TpC

4TpC

4TpC

100

100

100

100

70

70

2.5TpC

2.5TpC

12

12

70

70

2.5TpC

2.5TpC

12

12

Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ms ms

1

1

1,2

1,2

1

1

1

1

1,2

1,2

1

1

1

1

1

1

1

1

1

1

1


Z86E04/E08


AC ELECTRICAL CHARACTERISTICS (Continued)

Low Noise Mode, Extended Temperature

No

1

2

3

4.

5

6

7

8

9

10

Symbol

TPC

TrC

TfC

TwC

TwTinL

TwTinH

TpTin

TrTin,

TtTin

TwIL

TwIH

Twdt

Parameter

Input Clock Period


Input Clock Width



Timer Input Period


Int. Request Input

Low Time

Int. Request Input

High Time

Watch-Dog Timer


V

CC

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

Notes:


CC


CC

for a logic 0.


Min

T

A

= –40

°

C to +105

°

C

1 MHz 4 MHz

Max Min Max

1000

1000

500

500

70

70

2.5TpC

2.5TpC

70

70

2.5TpC

2.5TpC

10

10

DC

DC

25

25

250

250

2.5TpC

2.5TpC

4TpC 4TpC

4TpC 4TpC

100

100

125

125

70

70

70

70

2.5TpC

2.5TpC

10

10

DC

DC

25

25

100

100

Zilog

Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ms ms

1

1

1,2

1,2

1

1

1

1

1,2

1,2

1

1

1

1

1

1

1

1

1

1


Zilog

LOW NOISE VERSION

Low EMI Emission

The Z86E04/E08 can be programmed to operate in a Low

EMI Emission Mode by means of a mask ROM bit option.

Use of this feature results in:

■ All pre-driver slew rates reduced to 10 ns typical.

■ Internal SCLK/TCLK operation limited to a maximum of

4 MHz–250 ns cycle time.

Z86E04/E08


■ Output drivers have resistances of 500 Ohms (typical).

■ Oscillator divide-by-two circuitry eliminated.

The Low EMI Mode is mask-programmable to be selected by the customer at the time the ROM code is submitted.

1

PIN FUNCTIONS

OTP Programming Mode

D7–D0 Data Bus. Data can be read from, or written to, the

EPROM through this data bus.

V

CC

Power Supply. It is typically 5V during EPROM Read

Mode and 6.4V during the other modes (Program, Program Verify, and so on).

CE Chip Enable (active Low). This pin is active during

EPROM Read Mode, Program Mode, and Program Verify

Mode.

OE Output Enable (active Low). This pin drives the Data

Bus direction. When this pin is Low, the Data Bus is output.

When High, the Data Bus is input.

EPM EPROM Program Mode. This pin controls the different EPROM Program Modes by applying different voltages.

V

PP

Program Voltage. This pin supplies the program voltage.

Clear Clear (active High). This pin resets the internal address counter at the High Level.

Clock Address Clock. This pin is a clock input. The internal address counter increases by one with one clock cycle.

PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the Data Bus.

Application Precaution

The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above V

CC

occur on the XTAL1 pin.

In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the V

PP

, CE, EPM,

OE pins while the microcontroller is in Standard Mode.

Recommendations for dampening voltage surges in both test and OTP Mode include the following:

■

■

Using a clamping diode to V

CC

.

Adding a capacitor to the affected pin.

Note: Programming the EPROM/Test Mode Disable option will prevent accidental entry into EPROM Mode or

Test Mode.


Z86E04/E08


PIN FUNCTIONS (Continued)

XTAL1, XTAL2 Crystal In, Crystal Out (time-based input and output, respectively). These pins connect a parallelresonant crystal, LC, or an external single-phase clock

(8 MHz or 12 MHz max) to the on-chip clock oscillator and buffer.

Port 0, P02–P00. Port 0 is a 3-bit bidirectional, Schmitttriggered CMOS-compatible I/O port. These three I/O lines can be globally configured under software control to be inputs or outputs (Figure 7).

Zilog

Auto Latch. The Auto Latch puts valid CMOS levels on all

CMOS inputs (except P33, P32, P31) that are not externally driven. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer.

On Power-up and Reset, the Auto Latch will set the ports to an undetermined state of 0 or 1. Default condition is

Auto Latches enabled.

Z8 Port 0 (I/O)

OE

PAD

20

Out

In

1.5 2.3 Hysteresis

R 500 k

Ω

Figure 7. Port 0 Configuration

P R E L I M I N A R Y

Auto Latch Option

DS97Z8X1104

Zilog

Port 2, P27–P20. Port 2 is an 8-bit, bit programmable, bidirectional, Schmitt-triggered CMOS-compatible I/O port.

These eight I/O lines can be configured under software

Z86E04/E08

CMOS Z8 OTP Microcontrollers control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 8).

1

Z8

Port 2 (I/O)

DS97Z8X1104

Open-Drain

/OE

PAD

Out

In

1.5 2.3 Hysteresis VCC @ 5.0V

R 500 k

Ω


Auto Latch Option

P R E L I M I N A R Y 21

Z86E04/E08


PIN FUNCTIONS (Continued)

Port 3, P33–P31. Port 3 is a 3-bit, CMOS-compatible port with three fixed input (P33–P31) lines. These three input lines can be configured under software control as digital

Schmitt-trigger inputs or analog inputs.

Zilog

These three input lines are also used as the interrupt sources IRQ0–IRQ3, and as the timer input signal T

IN

(Figure 9).

Z86E04

Z86E08

Port 3

22

PAD

P31 (AN1)

PAD

PAD

P32 (AN2)

P33 (REF)

+

-

+

-

R247 = P3M

0 = Digital

1 = Analog

D1

DIG.

AN.

TIN

P31 Data Latch

IRQ2

IRQ3

P32 Data Latch

IRQ0

V cc

IRQ 0,1,2 = Falling Edge Detection

IRQ3 = Rising Edge Detection


P33 Data Latch

IRQ1

P R E L I M I N A R Y DS97Z8X1104

Zilog

Comparator Inputs. Two analog comparators are added to input of Port 3, P31, and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators.

Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In Analog Mode, P33 input functions serve as a reference voltage to the comparators.

The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP

Z86E04/E08


Mode. The common voltage range is 0–4 V when the V

CC is 5.0V; the power supply and common mode rejection ratios are 90 dB and 60 dB, respectively.

Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's output.

The comparator output is used for interrupt generation,

Port 3 data inputs, or T

IN

through P31. Alternatively, the comparators can be disabled, freeing the reference input

(P33) for use as IRQ1 and/or P33 input.

1

FUNCTIONAL DESCRIPTION

The following special functions have been incorporated into the Z8 devices to enhance the standard Z8 core architecture to provide the user with increased design flexibility.

RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for T

POR

ms, plus 18 clock cycles, then starts program execution at address

000C (Hex) (Figure 10). The Z8 control registers' reset value is shown in Table 3.

INT OSC XTAL OSC

POR

(Cold Start)

P27

(Stop Mode)

Delay Line

TPOR msec

18 CLK

Reset Filiter

Chip Reset

Figure 10. Internal Reset Configuration

Power-On Reset (POR) . A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR timer function. The POR time allows V

CC

and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the four following conditions:

■ Power-bad to power-good status

■ Stop-Mode Recovery

■ WDT time-out

■ WDH time-out

Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an onboard RC oscillator.


Z86E04/E08


FUNCTIONAL DESCRIPTION (Continued)

Zilog

Table 3. Control Registers

Addr.

FF

FD

FC

FB

FA

Reg.

SPL

RP

FLAGS

IMR

IRQ

D7

U

0

0

0

U

D6

U

U

0

0

U

D5

U

U

0

0

0

Reset Condition

D4 D3

0

0

U

U

0

0

0

U

U

0

D2

U

U

0

0

0

D1

U

U

0

0

0

D0 Comments

F5

F4

F3

F2

F1

F9

F8*

F7*

F6*

IPR

P01M

P3M

P2M

PRE0

T0

PRE1

T1

TMR

U

U

U

1

U

U

U

U

0

U

U

U

1

U

U

U

U

0

U

U

U

1

U

U

U

U

0

U

0

U

1

U

U

U

U

0

U

U

U

1

U

U

U

U

0

U

U

U

1

U

U

U

U

0

U

0

0

1

U

U

0

U

0

U

U

0

0

0 IRQ3 is used for positive edge detection

U

1

0

1 Inputs after reset

0

U

0

U

0

Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.


Zilog

Program Memory. The Z86E04/E08 addresses up to

1K/2KB of Internal Program Memory (Figure 11). The first

12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 0–1024/2048 are on-chip one-time programmable ROM.

Z86E04/E08


Register File. The Register File consists of three I/O port registers, 124 general-purpose registers, and 14 control and status registers R0–R3, R4–R127 and R241–R255, respectively (Figure 12). General-purpose registers occupy the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS Z8.

1

1023/2047

Location of

First Byte of

Instruction

Executed

After RESET

12

11

Interrupt

Vector

(Lower Byte)

10

9

8

7

6

Interrupt

Vector

(Upper Byte)

5

4

3

2

1

0

On-Chip

ROM

IRQ5

IRQ5

IRQ4

IRQ4

IRQ3

IRQ3

IRQ2

IRQ2

IRQ1

IRQ1

IRQ0

IRQ0

Identifiers

0CH

0BH

0AH

09H

08H

07H

06H

05H

04H

03H

02H

01H

00H

Location

255 (FFH)

254 (FE)

253 (FD)

252 (FC)

251 (FB)

250 (FA)

249 (F9)

248 (F8)

247 (F7)

246 (F6)

245 (F5)

244 (F4)

243 (F3)

242 (F2)

241 (F1H)

Stack Pointer (Bits 7-0)

General-Purpose Register

Register Pointer

Program Control Flags

Interrupt Mask Register

Interrupt Request Register

Interrupt Priority Register

Ports 0-1 Mode

Port 3 Mode

Port 2 Mode

T0 Prescaler

Timer/Counter 0

T1 Prescaler

Timer/Counter 1

Timer Mode

Not Implemented

IMR

IRQ

IPR

P01M

P3M

P2M

PRE0

T0

PRE1

T1

TMR

Identifiers

SPL

GPR

RP

FLAGS

Figure 11. Program Memory Map

128

127 (7FH)

4

3

2

1

0 (00H)

General-Purpose

Registers

Port 3

Port 2

Reserved

Port 0

Figure 12. Register File

P3

P2

P1

P0


Z86E04/E08



The Z8 instructions can access registers directly or indirectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer.

In the 4-bit mode, the register file is divided into eight working register groups, each occupying 16 continuous locations. The Register Pointer (Figure 13) addresses the starting location of the active working-register group.

FF

F0 r7 r6 r5 r4 r3 r2 r1 r0

The upper nibble of the register file address provided by the register pointer specifies the active working-register group.

R253

(Register Pointer)

Register Group F R15 to R0

7F

70

6F

60

5F

50

4F

40

3F

30

2F

Specified Working

Register Group

The lower nibble of the register file address provided by the instruction points to the specified register.

20

1F

Register Group 1 R15 to R0

10

0F

Register Group 0 R15 to R4*

I/O Ports

00

*Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253(RP).

R3 to R0

Zilog

Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 124 general-purpose registers.

General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the V

CC

voltage-specified operating range. Note:

Register R254 has been designated as a general-purpose register and is set to 00 Hex after any reset or Stop-Mode

Recovery.

Counter/Timer. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 can be driven by the internal clock source only (Figure 14).

The 6-bit prescalers divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ4 (T0) or IRQ5 (T1) is generated.

The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (Single-Pass

Mode) or to automatically reload the initial value and continue counting (Modulo-N Continuous Mode).

The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a gate input for the internal clock.

Figure 13. Register Pointer


Zilog

Z86E04/E08


OSC

÷

2

*

Write

PRE0

Initial Value

Register

Write

Internal Data Bus

T0

Initial Value

Register

Read

T0

Current Value

Register

÷

4

6-Bit

Down

Counter

8-bit

Down

Counter

IRQ4

Internal Clock

External Clock

Clock

Logic

÷

4

6-Bit

Down

Counter

8-Bit

Down

Counter

TIN P31

Internal Clock

Gated Clock

Triggered Clock

Write

PRE1

Initial Value

Register

T1

Initial Value

Register

Write

Internal Data Bus

Read

T1

Current Value

Register

* Note: By passed, if Low EMI Mode is selected.

Figure 14. Counter/Timers Block Diagram

IRQ5

1


Z86E04/E08



Interrupts. The Z8 has six interrupts from six different sources. These interrupts are maskable and prioritized

(Figure 15). The sources are divided as follows: the falling edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge of P32 (AN2), and two counter/timers. The Interrupt Mask

Register globally or individually enables or disables the six interrupt requests (Table 4).

When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z8 interrupts are vectored through locations in program memory. When an

Interrupt machine cycle is activated, an Interrupt Request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the

16-bit starting address of the interrupt service routine for that particular interrupt request.

Zilog

To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service.

Note: User must select any Z86E08 mode in Zilog's C12

ICEBOX

™

emulator. The rising edge interrupt is not supported on the CCP emulator (a hardware/software workaround must be employed).

Table 4. Interrupt Types, Sources, and Vectors

Name Source

IRQ0 AN2(P32)

IRQ1 REF(P33)

IRQ2 AN1(P31)

IRQ3 AN2(P32)

IRQ4 T0

IRQ5 T1

Notes:

F = Falling edge triggered

R = Rising edge triggered

Vector

Location Comments

0,1 External (F)Edge



6,7 External (R)Edge

8,9 Internal

10,11 Internal

IRQ0 - IRQ5

IRQ

28

Interrupt

Request

IMR

Global

Interrupt

Enable

IPR

PRIORITY

LOGIC

Vector Select

Figure 15. Interrupt Block Diagram


6

DS97Z8X1104

Zilog

Clock. The Z8 on-chip oscillator has a high-gain, parallelresonant amplifier for connection to a crystal, LC, RC, ceramic resonator, or any suitable external clock source

(XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, up to 12 MHz max., with a series resistance

(RS) of less than or equal to 100 Ohms.

Z86E04/E08


The crystal should be connected across XTAL1 and

XTAL2 using the vendors crystal recommended capacitors from each pin directly to device ground pin 14 (Figure 16).

Note that the crystal capacitor loads should be connected to V

SS

, Pin 14 to reduce Ground noise injection.

1

C1

*

C2

*

XTAL1

C1

*

XTAL2

C2

*

Ceramic Resonator or

Crystal

C1, C2 = 47 pF TYP *

F = 8 MHz

LC

XTAL1

L

XTAL2

External Clock

* Typical value including pin parasitics

Figure 16. Oscillator Configuration

XTAL1

C1

*

XTAL2

RC

@ 5V Vcc (TYP)

C1 = 100 pF

R = 2K

F = 6 MHz

XTAL1

R

XTAL2


Z86E04/E08



Resistor (R)

1.0M

560K

220K

100K

56K

20K

10K

5K

2K

1K

Notes:

A = STD Mode Frequency.

B = Low EMI Mode Frequency.

33 pFd

A(Hz) B(Hz)

33K 31K

56K

144K

52K

130K

315K

552K

1.4M

2.6M

270K

480K

1M

2M

4.4M

8M

12M

3M

5M

7M

Table 5. Typical Frequency vs. RC Values

V

CC

= 5.0V @ 25

°

C

Load Capacitor

A(Hz)

20K

34K

84K

182K

330K

884K

1.6M

2.8M

6M

8.8M

56 pFd

B(Hz)

20K

32K

78K

164K

300K

740K

1.3M

2M

4M

6M

100 pFd

A(Hz)

12K

20K

48K

100K

185K

500K

980K

1.7K

3.8K

6.3K

B(Hz)

11K

19K

45K

95K

170K

450K

820K

1.3M

2.7M

4.2M

Zilog

A(Hz)

1.4K

2.5K

6K

12K

23K

65K

130K

245K

600K

1.0M

0.00 1

µ

Fd

B(Hz)

1.4K

2.4K

6K

12K

22K

61K

123K

225K

536K

950K

Resistor (R) 33 pFd

1.0M

560K

220K

100K

56K

20K

10K

5K

2K

1K

A(Hz) B(Hz)

18K 18K

30K

70K

150K

268K

690M

1.2M

2M

4.6M

7M

Notes:

A = STD Mode Frequency.

B = Low EMI Mode Frequency.

30K

70K

148K

250K

600K

1M

1.7M

3M

4.6M

Table 6. Typical Frequency vs. RC Values

V

CC

= 3.3V @ 25

°

C

Load Capacitor

A(Hz)

12K

20K

47K

97K

176K

463K

860K

1.5M

3.3M

5M

56 pFd

B(Hz)

12K

20K

47K

96K

170K

416K

730K

1.2M

2.4M

3.6M

A(Hz)

7.4K

12K

30K

60K

100K

286K

540K

950K

2.2M

3.6K

100 pFd

B(Hz)

7.7K

12K

30K

60K

100K

266K

480K

820K

1.6M

2.6M

0.00 1

µ

Fd

A(Hz)

1K

1.6K

4K

8K

15K

40K

80K

151K

360K

660K

B(Hz)

1K

1.6K

4K

8K

15K

40K

76K

138K

316K

565K


Zilog

HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT.

Note: On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT Mode.

STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10

µ

A. The STOP Mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP Mode. Program execution begins at location 000C(Hex). However, when P27 is used to release the STOP Mode, the I/O port Mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the

STOP instruction was executed, from glitching to an unknown state. To use the P27 release approach with STOP

Mode, use the following instruction:

LD

NOP

STOP

P2M, #1XXX XXXXB

X = Dependent on user's application.

Note: A low level detected on P27 pin will take the device out of STOP Mode even if configured as an output.

In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a

NOP (opcode=FFH) immediately before the appropriate

SLEEP instruction, such as:

FF

6F

FF

7F

NOP

STOP or

NOP

HALT

; clear the pipeline

; enter STOP Mode

; clear the pipeline

; enter HALT Mode

Z86E04/E08


Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself,

The WDT instruction affects the flags accordingly; Z=1,

S=0, V=0.

WDT = 5F (Hex)

Opcode WDT (5FH). The first time Opcode 5FH is executed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every T

WDT

; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of T

POR

, plus 18 XTAL clock cycles. The software enabled WDT does not run in STOP Mode.

Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT Mode. A WDH instruction executed without executing WDT (5FH) has no effect.

Permanent WDT. Selecting the hardware enabled Permanent WDT option, will automatically enable the WDT upon exiting reset. The permanent WDT will always run in HALT

Mode and STOP Mode, and it cannot be disabled.

Auto Reset Voltage (V

LV

). The Z8 has an auto-reset builtin. The auto-reset circuit resets the Z8 when it detects the

V

CC

below V

LV

.

Figure 17 shows the Auto Reset Voltage versus temperature. If the V

CC

drops below the VCC operating voltage range, the Z8 will function down to the V

LV

unless the internal clock frequency is higher than the specified maximum

V

LV

frequency.

1


Z86E04/E08



Vcc

(Volts)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

–40

°

C –20

°

C 0

°

C 20

°

C 40

°

C 60

°

C 80

°

C 100

°

C

Figure 17. Typical Auto Reset Voltage

(V

LV

) vs. Temperature

Temp

Zilog


Zilog

Z86E04/E08


Low EMI Emission

The Z8 can be programmed to operate in a low EMI Emission (Low Noise) Mode by means of an EPROM programmable bit option. Use of this feature results in:

■

■

■

■

■

Less than 1 mA consumed during HALT Mode.

All drivers slew rates reduced to 10 ns (typical).

Internal SCLK/TCLK = XTAL operation limited to a maximum of 4 MHz–250 ns cycle time.

Output drivers have resistances of 500 ohms (typical).

Oscillator divide-by-two circuitry eliminated.

ROM Protect. ROM Protect fully protects the Z8 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported

(Z86E04/E08 and Z86C04/C08 do not support the instructions of LDE and LDEI). When the device is programmed for ROM Protect, the Low Noise feature will not automatically be enabled.

Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE pins be clamped to V

CC

through a diode to V

CC

to prevent accidentally entering the OTP Mode. The V

PP

requires both a diode and a 100 pF capacitor.

Auto Latch Disable. Auto Latch Disable option bit when programmed will globally disable all Auto Latches.

In addition to V

DD

and GND (V

SS

), the Z8 changes all its pin functions in the EPROM Mode. XTAL2 has no function,

XTAL1 functions as CE, P31 functions as OE, P32 functions as EPM, P33 functions as V

PP

PGM.

, and P02 functions as

WDT Enable. The WDT Enable option bit, when programmed, will have the hardware enabled Permanent

WDT enabled after exiting reset and can not be stopped in

Halt or Stop Mode.

EPROM/Test Mode Disable. The EPROM/Test Mode

Disable option bit, when programmed, will disable the

EPROM Mode and the Factory Test Mode. Reading, verifying, and programming the Z8 will be disabled. To fully verify that this mode is disabled, the device must be power cycled.

User Modes. Table 7 shows the programming voltage of each mode.

Table 7. OTP Programming Table

Programming Modes

EPROM READ

PROGRAM

PROGRAM VERIFY

EPROM PROTECT

LOW NOISE SELECT

AUTO LATCH DISABLE

WDT ENABLE

EPROM/TEST MODE

V

PP

NU

V

H

V

H

V

H

V

H

V

H

V

H

V

H

EPM

V

H

V

IH

V

V

H

V

IH

V

IH

V

IL

V

IH

IL

CE

Notes:

1. V

H

=12.75V

±

0.25 V

DC

.

2. V

IH

= As per specific Z8 DC specification.

3. V

IL

= As per specific Z8 DC specification.

4. X = Not used, but must be set to V

H

or V

IH

level.

5. NU = Not used, but must be set to either V

IH

or V

IL

level.

6. I

PP

during programming = 40 mA maximum.

7. I

CC

during programming, verify, or read = 40 mA maximum.

8. * V

CC

has a tolerance of

±

0.25V.

V

IL

V

IL

V

IL

V

H

V

H

V

H

V

H

V

H

OE

V

IL

V

IH

V

IL

V

IH

V

IH

V

IL

V

IH

V

IL

PGM

V

IH

V

IL

V

IH

V

IL

V

IL

V

IL

V

IL

V

IL

ADDR

ADDR

ADDR

ADDR

NU

NU

NU

NU

NU

DATA V

CC

In

Out

NU

*

Out 5.0V

6.4V

6.4V

NU 6.4V

NU 6.4V

NU 6.4V

NU 6.4V

6.4V

1


Z86E04/E08



Zilog

Internal Address Counter. The address of Z8 is generated internally with a counter clocked through pin P01

(Clock). Each clock signal increases the address by one and the “high” level of pin P00 (Clear) will reset the address to zero. Figure 18 shows the setup time of the serial address input.

Parameters

1

2

3

4

9

10

11

12

7

8

5

6

13

14

15

16

17

Programming Waveform. Figures 19, 20, 21 and 22 show the programming waveforms of each mode. Table 8 shows the timing of programming waveforms.

Programming Algorithm. Figure 23 shows the flow chart of the Z8 programming algorithm.

Table 8. Timing of Programming Waveforms

Name Min

Address Setup Time

Data Setup Time

V

PP

Setup 2

V

CC

Setup Time 2

Chip Enable Setup Time 2

2

2

Program Pulse Width

Data Hold Time

OE Setup Time

Data Access Time

0.95

2

2

188

Data Output Float Time

Overprogram Pulse Width

EPM Setup Time

PGM Setup Time

Address to OE Setup Time

Option Program Pulse Width

OE Width

Address Valid to OE Low

2.85

2

2

2

78

250

125

Max

100 ns ms

µ s

µ s

µ s ms

Units

µ s

µ s

µ s

µ s

µ s ms

µ s

µ s ns ns ns


Zilog

Z86E04/E08


T2

P01 = Clock

T4

T3

T1

P00 = Clear

Vpp/EPM

T6

T5

Internal

Address

Vih

Data

Vil

Invalid

Legend:

T1 Reset Clock Width

T2 Input Clock High

T3 Input Clock Period

T4 Input Clock Low

T5 Clock to Address Counter Out Delay

T6 Epm/Vpp Set up Time

0 Min

Vali d

9

Invalid

30 ns Min

100 ns Min

200 ns Min

100 ns Min

15 ns Max

40

µ s Min

Vali d

Figure 18. Z86E04/E08 Address Counter Waveform

1


Z86E04/E08



Address

Data

V

PP

EPM

VIH

VIL

VH

VIL

VIH

VIL

VIH

VIL

Invalid

Address Stable

17

Valid

9

Invalid

Address Stable

Valid

12

V

CC

CE

OE

PGM

VIH

VIL

VIH

VIL

5.0V

VIH

VIL

5

16 16

13

Figure 19. Z86E04/E08 Programming Waveform

(EPROM Read)

Zilog


Zilog

V IH

Address

V IL

V IH

Data

V IL

V PP

V H

V IH

EPM

V H

V IL

V

CC

6V

5.0V

V

IH

CE

V IL

V

IH

OE

V IL

V IH

PGM

V IL

3

1

Data

Stable

2

Z86E04/E08


Address

Stable

9

Data Out

Valid

10

1

4 7

5

13

16

6

11

Program

Cycle

8

Figure 20. Z86E04/E08 Programming Waveform

(Program and Verify)

Verify

Cycle


Z86E04/E08



Address

Data

V

IH

V

IL

V

IH

V

IL

V

PP

V

H

V

IH

V

CC

6V

5.0V

CE

V

H

V

IH

OE

V

IH

V

IL

4

5

3

EPM

PGM

V

H

V

IH

V

IL

V

IH

V

IL

12

13

V

IH

12

13

15

EPROM Protect

15

Low Noise Program

Figure 21. Z86E04/E08 Programming Options Waveform

(EPROM Protect and Low Noise Program)

Zilog


Zilog

Address

V

IH

V

IL

V

IH

Data

V

IL

V

PP

V

H

V

IH

V

CC

6V

5.0V

CE

V

H

V

IH

OE

V

IL

V

IH

EPM

V

IL

PGM

V

IH

V

IL

4

5

12

13

3

15

Auto Lat ch

V

IH

12

13

12

13

12

13

Z86E04/E08


15

WDT

15

EPROM/Test

Mode Disabl e

Figure 22. Z86E04/E08 Programming Options Waveform

(Auto Latch Disable, Permanent WDT Enable and

EPROM/Test Mode Disable)

1


Z86E04/E08



Start

Addr =

First Location

40

N = 0

Program

1 ms Pulse

Increment N

N = 25 ?

No

Fail Verify

One Byte

Pass

Prog. One Pulse

3xN ms Duration

Yes

Verify

Byte

Pass

Fail

Increment

Address

No

Last Addr ?

Yes

Verify All

Bytes

Pass

Fail

Device

Failed

Device

Passed

Figure 23. Z86E04/E08 Programming Algorithm


Zilog

DS97Z8X1104

Zilog

Z8 CONTROL REGISTERS

R241 TMR

D7 D6 D5 D4 D3 D2 D1 D0

0 No Function

1 Load T0

0 Disable T0 Count

1 Enable T0 Count

0 No Function

1 Load T1

0 Disable T1 Count

1 Enable T1 Count

TIN Modes

00 External Clock Input

01 Gate Input

10 Trigger Input

(Non-retriggerable)

11 Trigger Input

(Retriggerable)

Reserved (Must be 0)

Figure 24. Timer Mode Register (F1

H

: Read/Write)

Z86E04/E08


R244 T0

D7 D6 D5 D4 D3 D2 D1 D0

(When Written)

(Range: 1-256 Decimal

01-00 HEX)

(When READ)

Figure 27. Counter/Timer 0 Register

(F4

H

: Read/Write)

R245 PRE0

D7 D6 D5 D4 D3 D2 D1 D0

R243 PRE1

D7 D6 D5 D4 D3 D2 D1 D0

Count Mode

Clock Source

Prescaler Modulo


01-00 HEX)

Figure 26. Prescaler 1 Register (F3

H

: Write Only)

R247 P3M

D7 D6 D5 D4 D3 D2 D1 D0

Count Mode

0 T0 Single Pass

1 T0 Modulo N


Prescaler Modulo


01-00 HEX)

R242 T1

D7 D6 D5 D4 D3 D2 D1 D0

(When Written)

(Range 1-256 Decimal

01-00 HEX)

(When READ)

Figure 25. Counter Timer 1 Register (F2

H

: Read/Write)

Figure 28. Prescaler 0 Register (F5

H

: Write Only)

R246 P2M

D7 D6 D5 D4 D3 D2 D1 D0

0 Defines Bit as OUTPUT

1 Defines Bit as INPUT

Figure 29. Port 2 Mode Register (F6

H

: Write Only)

0 Port 2 Open-Drain

1 Port 2 Push-pull

Port 3 Inputs

0 Digital Mode

1 Analog Mode


1

Figure 30. Port 3 Mode Register (F7

H

: Write Only)


Z86E04/E08


Z8 CONTROL REGISTERS (Continued)

Zilog

42

R248 P01M

D7 D6 D5 D4 D3 D2 D1 D0

P0

2

-P0

0

Mode

00 = Output

01 = Input

Reserved (Must be 1.)


Figure 31. Port 0 and 1 Mode Register

(F8

H

: Write Only)

R249 IPR

D7 D6 D5 D4 D3 D2 D1 D0

Interrupt Group Priority

Reserved = 000

C > A > B = 001

A > B > C = 010

A > C > B = 011

B > C > A = 100

C > B > A = 101

B > A > C = 110

Reserved = 111

IRQ1, IRQ4 Priority (Group C)

0 = IRQ1 > IRQ4

1 = IRQ4 > IRQ1

IRQ0, IRQ2 Priority (Group B)

0 = IRQ2 > IRQ0

1 = IRQ0 > IRQ2

IRQ3, IRQ5 Priority (Group A)

0 = IRQ5 > IRQ3

1 = IRQ3 > IRQ5


Figure 32. Interrupt Priority Register

(F9

H

: Write Only)

R251 IMR

D7 D6 D5 D4 D3 D2 D1 D0

1 Enables IRQ0-IRQ5


1 Enables Interrupts

Figure 34. Interrupt Mask Register

(FB

H

: Read/Write)

R252 Flags

D7 D6 D5 D4 D3 D2 D1 D0

User Flag F1

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Flag

Sign Flag

Zero Flag

Carry Flag

Figure 35. Flag Register

(FC

H

: Read/Write)

R253 RP

D7 D6 D5 D4 D3 D2 D1 D0

Expanded Register File

Working Register Pointer

Default After Reset = 00H

Figure 36. Register Pointer

(FD

H

: Read/Write)

R250 IRQ

D7 D6 D5 D4 D3 D2 D1 D0

IRQ0 = P32 Input

IRQ1 = P33 Input

IRQ2 = P31 Input

IRQ3 = P32 Input

IRQ4 = T0

IRQ5 = T1


Figure 33. Interrupt Request Register

(FA

H

: Read/Write)

R255 SPL

D7 D6 D5 D4 D3 D2 D1 D0

Stack Pointer Lower


Figure 37. Stack Pointer

(FF

H

: Read/Write)

DS97Z8X1104

Zilog

PACKAGE INFORMATION

Z86E04/E08


1

18-Pin DIP Package Diagram

DS97Z8X1104

18-Pin SOIC Package Diagram

P R E L I M I N A R Y 43

Z86E04/E08


ORDERING INFORMATION

Z86E04

Standard Temperature

18-Pin DIP

Z86E0412PSC

Z86E0412PEC

18-Pin SOIC

Z86E0412SSC

Z86E0412SEC

Z86E08

Standard Temperature

18-Pin DIP

Z86E0812PSC

Z86E0812PEC

18-Pin SOIC

Z86E0812SSC

Z86E0812SEC

For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.

Codes

Preferred Package

P = Plastic DIP

Longer Lead Time

S = SOIC

Preferred Temperature

S = 0

°

C to +70

°

C

E = –40

°

C to +105

°

C

Speeds

12 =12 MHz

Environmental

C = Plastic Standard

Zilog

Example:

Z 86E04 12 P S C is a Z86E04, 12 MHz, DIP, 0

°

C to +70

°

C, Plastic Standard Flow

Environmental Flow

Temperature

Package

Speed

Product Number

Zilog Prefix

© 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS,

STATUTORY, IMPLIED OR BY DESCRIPTION,

REGARDING THE INFORMATION SET FORTH HEREIN

OR REGARDING THE FREEDOM OF THE DESCRIBED

DEVICES FROM INTELLECTUAL PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY

OF MERCHANTABILITY OR FITNESS FOR ANY

PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.

Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use.

Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

FAX 408 370-8056

Internet: http://www.zilog.com


Z86E04/E08 1 CMOS Z8 OTP M

CMOS Z8 OTP M ICROCONTROLLERS

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