TLK1221

TLK1221

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

ETHERNET TRANSCEIVER

Check for Samples: TLK1221

1

FEATURES

23

• 0.6- to 1.3-Gigabits Per Second (Gbps)

Serializer/Deserializer

• Low Power Consumption 250 mW (typ) at 1.25

Gbps

• LVPECL-Compatible Differential I/O on

High-Speed Interface

• Single Monolithic PLL Design

• Support For 10-Bit Interface

• Fast Relock Times Less Than 256 ns (typ)

Suitable for EPON/GEPON Applications such as OLT and ONU Systems

• Receiver Differential-Input Thresholds, 200-mV

Minimum

• Industrial Temperature Range From –40°C to

85°C

• IEEE 802.3 Gigabit Ethernet Compliant

• Designed in 0.25

μ m CMOS Technology

• No External Filter Capacitors Required

• Comprehensive Suite of Built-In Testability

• 2.5-V Supply Voltage for Lowest-Power

Operation

• 3.3-V Tolerant on LVTTL Inputs

• Hot Plug Protection

• 40-Pin 6-mm × 6-mm QFN PowerPAD™

Package

ENABLE

TD0

TD1

TD2

TD3

VDD

TD4

TD5

TD6

TD7

RHA Package

(Top View)

6

7

4

5

1

2

3

8

9

10

40 39 38 37 36 35 34 33 32 31

GND

11 12 13 14 15 16 17 18 19 20

27

26

25

24

30

29

28

23

22

21

DESCRIPTION

The TLK1221 gigabit Ethernet transceiver provides for high-speed full-duplex point-to-point data transmissions.

These devices are based on the timing requirements of the 10-bit interface specification by the IEEE 802.3

Gigabit Ethernet specification. The TLK1221 supports data rates from 0.6 Gbps through 1.3 Gbps.

The primary application of these devices is to provide building blocks for point-to-point baseband data transmission over controlled-impedance media of 50 Ω . The transmission media can be printed-circuit board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK1221 performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface.

SYNC

RD0

RD1

RD2

VDD

RD3

RD4

RD5

RD6

RD7

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 .......................................................................................................................................

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

This device supports the defined 10-bit interface (TBI). In the TBI mode, the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL-compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.

A comprehensive series of built-in tests is provided for self-test purposes, including loopback and pseudorandom binary sequence (PRBS) generation and verification.

The TLK1221 is housed in a high-performance, thermally enhanced, 40-pin QFN package. Use of this package does not require any special considerations except to note that the pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is required that the TLK1221 pad be soldered to the thermal land on the board as it serves as the main ground connection for the device.

The TLK1221 is characterized for operation from –40°C to 85°C.

This device uses a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply, the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.

The TLK1221 is designed to be hot-plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in the high-impedance state.

Differences Between TLK2201B, TLK2201BI, TLK1221, and TNETE2201

The TLK1221 is the functional equivalent of the TNETE2201. There are several differences between the devices as noted below. See

Figure 12

in the application information section for an example of a typical application circuit.

• V

CC is 2.5 V for the TLK2201B, TLK2201BI, TLK1221, and TLK1201A vs 3.3 V for TNETE2201.

• The PLL filter capacitors on pins 16, 17, 48, and 49 of the TNETE2201 are no longer required. The

TLK2201B, TLK2201BI, TLK1221, and TLK1201A use these pins to provide added test capabilities. The capacitors, if present, do not affect the operation of the device.

• No pulldown resistors are required on the TXP/TXN outputs.

• The TLK1221 is a QFN version of the TLK1211 optimized for TBI-mode operation with no JTAG functionality.

• TLK1221 also has a faster relock time than TLK1201A or TLK2201B.

2

Submit Documentation Feedback

Product Folder Link(s):

TLK1221

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

FUNCTIONAL BLOCK DIAGRAM

PRBSEN

LOOPEN

TD(0–9)

PRBS

Generator

10 Bit

Registers

2:1

MUX

Parallel to

Serial

TXP

TXN

REFCLK

Clock

Phase Generator

ENABLE

Control

Logic

RBC1

RBC0

SYNC/PASS

PRBS

Verification

Interpolator and

Clock Extraction

Clock

2:1

MUX

Clock

RD(0–9)

Serial to Parallel and

Comma Detect

2:1

MUX

Data

RXP

RXN

SYNCEN

RBCMODE

Detailed Description

In the TBI mode, the transmitter portion registers incoming 10-bit-wide data words (8b/10b encoded data,

TD0–TD9) on the rising edge of REFCLK. REFCLK is also used by the serializer, which multiplies the clock by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted sequentially, bits 0 through 9, over the differential high-speed I/O channel.

Transmission Latency

Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit 9. The minimum latency in TBI mode is 20 bit times. The maximum latency in TBI mode is 22 bit times.

10-Bit Code

TXP, TXN b9 t d(Tx latency)

TD(0–9)

10-Bit Code

REFCLK

Figure 1. Transmitter Latency, Full-Rate Mode

Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s):

TLK1221

Submit Documentation Feedback

3

TLK1221

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 .......................................................................................................................................

www.ti.com

Data Reception

The receiver section deserializes the differential serial data. The serial data is retimed based on an interpolated clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with the receive byte clocks (RBC0, RBC1).

Receiver Clock Select Mode

The TLK1221 only supports TBI-mode operation with half-rate and full-rate clocks on RBC0 and RBC1. In TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: 1) full-rate clock on RBC0 and 2) half-rate clocks on RBC0 and RBC1.

RBCMODE

0

1

Table 1. Mode Selection

MODE

TBI half-rate

TBI full-rate

RECEIVE BYTE CLOCK

TLK1221

30–65 MHz

60–130 MHz

In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is output with respect to the two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel bytes using the RBC0 and RBC1 rising edges. For the outputs to the protocol device, byte 0 of the received data is valid on the rising edge of RBC1. Refer to the timing diagram shown in

Figure 2

.

t d(S)

RBC0 t d(S)

RBC1 t d(H)

SYNC t d(H)

RD(0–9)

K28.5

DXX.X

DXX.X

DXX.X

K28.5

DXX.X

Figure 2. Synchronous Timing Characteristic Waveforms (TBI Half-Rate Mode)

The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, ±0.02% (200

PPM) for proper operation.

RBC0 t d(S) t d(H)

SYNC

RD(0–9) K28.5

DXX.X

DXX.X

DXX.X

K28.5

Figure 3. Synchronous Timing Characteristic Waveforms (TBI Full-Rate Mode)

DXX.X

Receiver Word Alignment

These devices use the IEEE 802.3 Gigabit Ethernet defined 10-bit K28.5 character, which contains the 7-bit comma-pattern word alignment scheme. The following sections explain how this scheme works and how it realigns to the proper byte boundary of the data.

4

Submit Documentation Feedback

Product Folder Link(s):

TLK1221

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

Comma Character on Expected Boundary

These devices provide 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial input data to the 7-bit synchronization pattern. The K28.5 character is defined by the 8b/10b coding scheme as a pattern consisting of 0011 1110 10 (a negative number beginning with disparity), with the 7 MSBs (0011 111) referred to as the comma character. The K28.5 character was implemented specifically for aligning data words.

As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly aligned and data realignment is not required.

Figure 2

shows the timing characteristics of RBC0, RBC1, SYNC and RD0–RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1).

Comma Character Not on Expected Boundary

If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in

Figure 4

. The

RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design, the maximum stretch that occurs is 20 bit times. This occurs during a worst-case scenario when the K28.5 is aligned to the falling edge of RBC1 instead of the rising edge.

Figure 4

shows the timing characteristics of the data realignment.

Max Receive

Path Latency

31 Bit

Times

30 Bit

Times (Max)

INPUT DATA

K28.5

DXX.X

DXX.X

K28.5

DXX.X

DXX.X

DXX.X

K28.5

RBC0

RBC1

RD(0–9)

Worst Case

Misaligned K28.5

DXX.X

DXX.X

K28.5

DXX.X

Corrupt Data

DXX.X

K28.5

DXX.X

Misalignment Corrected

DXX.X

DXX.X

K28.5

SYNC

Figure 4. Word Realignment Timing Characteristic Waveforms

Systems that do not require framed data may disable byte alignment by tying SYNCEN low.

When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.

The duration of the SYNC pulse is equal to the duration of the data.

Data Reception Latency

The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RD0 received as the first bit. The minimum latency in TBI mode is 18 bit times and the maximum latency is 24 bit times.

Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s):

TLK1221

Submit Documentation Feedback

5

TLK1221

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 .......................................................................................................................................

www.ti.com

10-Bit Code

RXP, RXN t d(Rx latency)

RD(0–9)

10-Bit Code

RBC0

RBC1

Figure 5. Receiver Latency, TBI Half-Rate Mode Shown

Testability

The loopback function provides for at-speed testing of the transmit/receive section of the circuitry. The enable function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also allows for built-in self-test (BIST).

Loopback Testing

The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loopback path.

Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. (The external differential output is held in a high-impedance state during the loopback testing.)

ENABLE Function

When held low, ENABLE disables all quiescent power in both analog and digital circuitry. This allows an ultralow-power idle state when the link is not active.

PRBS Function

These devices have a built-in 2

7

– 1 PRBS function. When the PRBSEN control bit is set high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester (BERT) or to the receiver of another TLK1221. Because the PRBS is not really random and is really a predetermined sequence of ones and zeros, the data can be captured and checked for errors by a BERT. These devices also have a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive a PRBS pattern and check for errors, and then report the errors by forcing the SYNC/PASS terminal low. The PRBS testing supports two modes (normal and latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the PRBS bit-error-rate test is passed to the SYNC/PASS terminal. When SYNCEN is high, the result of the PRBS verification is latched on the SYNC/PASS output (i.e., a single failure forces SYNC/PASS to remain low).

PIN

I/O

Table 2. PIN FUNCTIONS

DESCRIPTION

NAME

SIGNAL

TXP

TXN

NO.

38

39

PECL

O

Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper or an optical I/F module. TXP and TXN are put in a high-impedance state when

LOOPEN is high and are active when LOOPEN is low.

6

Submit Documentation Feedback

Product Folder Link(s):

TLK1221

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

Table 2. PIN FUNCTIONS (continued)

PIN

NAME

RXP

RXN

REFCLK

TD0–TD9

RD0–RD9

RBC0

RBC1

RBCMODE

SYNCEN

SYNC/PASS

NO.

34

33

14

2–5, 7–12

29–27, 25–19

17

18

13

32

30

I/O

PECL

I

I

I

O

O

I

P/D

(1)

P/U

I

(2)

O

DESCRIPTION

Differential input receive. RXP and RXN together are the differential serial input interface from a copper or an optical I/F module.

Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input data (TD0–TD9) for serialization.

In the TBI mode that data is registered on the rising edge of REFCLK.

Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.

Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1. RD0 is the first bit received.

Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output data on RD0–RD9.

In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and

RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data. In normal-rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned to the rising edge.

Receive clock mode select. When RBCMODE is low, half-rate clocks are output on RBC0 and RBC1. When RBCMODE is high, a full baud-rate clock is output on RBC0, and RBC1 is held low.

Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated. When this function is activated, the transceiver detects the comma pattern

(0011 111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9.

Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS test results (high = pass).

TEST

LOOPEN

PRBSEN

15

31

I

P/D

(3)

I

P/D

(3)

Loop enable. When LOOPEN is high (active), the internal loopback path is activated. The transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the loopback test. LOOPEN is held low during standard operational state with external serial outputs and inputs active.

PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for errors, which are reported by the SYNC/PASS terminal indicating low.

When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP and

TXN are high-impedance. The pullup and pulldown resistors on any input are disabled.

When ENABLE is high, the device operates normally.

ENABLE 1

I

P/U

(2)

POWER

VDD

VDDA

6, 16, 26

37

Supply

Supply

VDDPLL

GROUND

GNDA

GNDQFN

36

35, 40

PAD

Supply

(1) P/D = Internal pulldown resistor

(2) P/U = Internal pullup resistor

(3) P/D = Internal pulldown resistor

Ground

Ground

Digital logic power. Provides power for all digital circuitry and digital I/O buffers

Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter.

PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.

Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.

Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers

Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s):

TLK1221

Submit Documentation Feedback

7

TLK1221

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 .......................................................................................................................................

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

DD

V

I

V

I

ESD

T stg

T

A

Supply voltage

(2)

Input voltage range at TTL terminals

Input voltage range at other terminals

Electrostatic discharge

Storage temperature

Characterized free-air temperature range

VALUE

(1)

–0.3 to 3

–0.5 to 4

–0.3 to V

DD

+ 0.3

CDM: 1, HBM: 2

–65 to 150

–40 to 85

UNIT

V

V

V kV

°C

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

DISSIPATION RATINGS

PACKAGE

RHA

(1) (2)

T

A

≤ 25°C

POWER RATING

2.85 W

DERATING FACTOR

ABOVE T

A

= 25°C

28 mW/°C

T

A

= 70°C

POWER RATING

1.57 W

(1) The thermal resistance junction to ambient of the RHA package is 35°C/W measured on a high-K board.

(2) The thermal resistance junction-to-case (exposed pad) of the RHA package is 5°C/W.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

T

A

= 85°C

POWER RATING

1.4 W

MIN NOM MAX UNIT

V

DD

,

V

DDA

,

V

DDPLL

I

DD

, I

DDA

,

I

DDPLL

P

D

I

DDQ

PLL

T

A

Supply voltage

Total supply current

Frequency = 1.25 Gbps, PRBS pattern;

ENABLE = 1, V

DD

, V

DDPLL and V

DDA

= 2.7 V

Frequency = 1.25 Gbps, PRBS pattern Total power dissipation

Total shutdown current (I

DD

+I

DDA

+ I

DDPLL

) Enable = 0; V

DD

, V

DDPLL and V

DDA

= 2.7 V

Startup lock time V

DD

, V

DDA

= 2.5 V

Operating free-air temperature

2.3

–40

2.5

2.7

V

113 mA

235 305 mW

1000 μ A

500

85

μ s

°C

REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS

f Frequency

Minimum data rate

Maximum data rate

Accuracy

DC Duty cycle

Jitter Random plus deterministic

MIN TYP

TYP – 0.01% 60

MAX

TYP + 0.01%

UNIT

MHz

TYP – 0.01%

–100

130 TYP + 0.01%

100 ppm

40% 50% 60%

40 ps

8

Submit Documentation Feedback

Product Folder Link(s):

TLK1221

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

TTL ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

C

IN

High-level output voltage

Low-level output voltage

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

I

OH

= –400

μ

A

I

OL

= 1 mA

V

DD

= 2.3 V, V

IN

= 2 V

V

DD

= 2.3 V, V

IN

= 0.4 V

MIN TYP MAX UNIT

V

DD

– 0.2

2.3

GND 0.25

1.7

0.5

3.6

0.8

40

V

V

V

V

–40

4

μ A

μ

A pF

TRANSMITTER/RECEIVER CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS

V

(CM)

C

I t

(TJ) t

(DJ) t r

, t f t d(Tx latency) t d(Rx latency)

VOD = |TxD – TxN|

Transmit common mode voltage range

Receiver input voltage requirement,

VID = |RxP – RxN|

Data relock time from application of valid input data stream

Tx latency

Rx latency

Rt = 50

Rt = 50

Receiver common mode voltage range, (RxP + RxN)/2

Receiver input capacitance

Differential output jitter, random + deterministic, PRBS

Serial data total jitter (peak-to-peak) pattern,

R

ω

= 125 MHz

Serial data deterministic jitter

(peak-to-peak)

Differential output jitter, PRBS pattern, R

ω

= 125 MHz

Differential signal rise, fall time (20% R

L to 80%)

= 50 Ω , C

L

= 5 pF, see

Figure 6

and

Figure 8

Serial data jitter tolerance minimum required eye opening, (per

IEEE-802.3 specification)

Receiver data acquisition lock time from power up

Differential input jitter, random + deterministic, R

125 MHz

ω

=

0.75 UI jitter closure with random data ata 1.25 Gbps

0.20 UI jitter closure with 01010.. data at 1.25 Gbps

See

Figure 1

See

Figure 5

and

Figure 7

MIN TYP MAX UNIT

600 850 1100 mV

1000 1250 1400 mV

200

100

0.25

20

18

TX+ t r

80%

50%

20% t f

~

V

~

V

TX–

80%

50%

20% t r

~

V

~

V t f

80%

~

1 V

VOD

0 V

20%

~

–1 V

Figure 6. Differential and Common-Mode Output Voltage Definitions

1600 mV

1000 1250 2250 mV

2 pF

0.24

0.12

250

500

256

128

22

24

UI

UI ps

UI

μ s ns

UI

UI

Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s):

TLK1221

Submit Documentation Feedback

9

TLK1221

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 .......................................................................................................................................

www.ti.com

RXP, RXN

10-Bit Code b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 t d(Rx latency)

RD(0–9)

10-Bit Code

RBC0

Figure 7. Receiver Latency, TBI Normal Mode Shown

CL

5 pF

50 W

50 W

CL

5 pF

Figure 8. Transmitter Test Setup

CLOCK 1.4 V t r t f

DATA

80%

50%

20% t f

2 V

0.8 V t r

Figure 9. TTL Data I/O Valid Levels for AC Measurement

10

Submit Documentation Feedback

Product Folder Link(s):

TLK1221

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

LVTTL OUTPUT SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS

t r t f t r(RBC) t f(RBC)

Clock rise time

Clock fall time

Data rise time

Data fall time

80% to 20% output voltage, C = 5 pF (see

Figure 9

) t su(d1) t h(d1) t su(d3) t h(d3)

Data setup time (RD0–RD9)

Data hold time (RD0–RD9)

Data setup time (RD0–RD9)

Data hold time (RD0–RD9)

TBI normal mode (see

Figure 3

), R

ω to RBC0 rising

= 125 MHz, data valid prior

TBI normal mode (see

Figure 3 ), R

ω prior to RBC0 rising

= 61.44 MHz, data valid

TBI normal mode (see

Figure 3

), R

ω

RBC0 rising

= 125 MHz, data valid after

TBI normal mode (see

Figure 3

), R

ω after RBC0 rising

= 61.44 MHz, data valid

TBI half-rate mode, R

ω

= 125 MHz (see

Figure 2 )

TBI half-rate mode, R

ω

= 125 MHz (see

Figure 2 )

MIN TYP MAX UNIT

0.3

0.3

1.5

1.5

ns ns

0.3

0.3

1.5

1.5

ns ns

2.5

ns

5

2

4

2.5

1.5

ns ns ns ns ns

TRANSMITTER TIMING REQUIREMENTS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS

t su(d4) t h(d4) t r

, t f

Data setup time (TD0–TD9)

Data hold time (TD0–TD9)

TD[0,9] data rise and fall time See

Figure 9

T

A

Table 3. AVAILABLE OPTIONS

–40°C to 85°C

PACKAGE

QFN PLASTIC QUAD FLAT PACK (RHA)

TLK1221RHA

MIN TYP MAX UNIT

1.6

0.8

ns ns

2 ns

Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s):

TLK1221

Submit Documentation Feedback

11

TLK1221

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 .......................................................................................................................................

www.ti.com

APPLICATION INFORMATION

8b/10b Transmission Code

The PCS maps GMII signals into ten-bit code groups and vice versa, using an 8b/10b block coding scheme. The

PCS uses the transmission code to improve the transmission characteristics of information to be transferred across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the likelihood of detecting any single- or multiple-bit errors that may occur during transmission and reception of information. The 8b/10b transmission code specified for use has a high transition density, is run length limited, and is dc-balanced. The transition density of the 8b/10b symbols ranges from 3 to 8 transitions per symbol. The definition of the 8b/10b transmission code is specified in IEEE 802.3 Gigabit Ethernet and ANSI X3.230-1994

(FC-PH), clause 11.

8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit notation of A, B, C, D, E, F, G, H for an unencoded information octet is used in the description of the 8b/10b transmission code-groups, where A is the LSB. Each valid code group has been given a name using the following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups, where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K<HGF.EDCBA>).

Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as 111

11110.

12

Submit Documentation Feedback

Product Folder Link(s):

TLK1221

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

VDD

TXP Z

0

RXP

5 kW

7.5 kW

Z

0

GND

VDD

+

_

Z

0

5 kW

TXN

Z

0

Transmitter Media

RXN

7.5 kW

GND

Receiver

Figure 10. High-Speed I/O Directly Coupled Mode

TXP

TXN

Z

0

Z

0

Z

0

Z

0

RXP

VDD

5 kW

7.5 kW

GND

VDD

5 kW

RXN

7.5 kW

GND

Receiver Transmitter Media

Figure 11. High-Speed I/O AC-Coupled Mode

+

_

Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s):

TLK1221

Submit Documentation Feedback

13

TLK1221

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009 .......................................................................................................................................

www.ti.com

5

W

at 100 MHz

2.5 V

VDD VDDA

40

VDDPLL

GNDQFN

GNDA

TLK1221

GNDA

0.01 µF

2.5 V

Host

Protocol

Device

10

10

2

TD0–TD9

14

REFCLK

31

PRBSEN

15

LOOPEN

32

SYNCEN

30

SYNC/PASS

RD0–RD9

RBC0–RBC1

1

ENABLE

13

RCBMODE

TXP

38

TXN

39

RXP

34

Rt

50

W

Controlled-Impedance

Transmission Line

Controlled-Impedance

Transmission Line

Controlled-Impedance

Transmission Line

RXN

33

Rt

50

W

Controlled-Impedance

Transmission Line

Figure 12. Typical Application Circuit (AC Mode)

14

Submit Documentation Feedback

Product Folder Link(s):

TLK1221

Copyright © 2007–2009, Texas Instruments Incorporated

TLK1221 www.ti.com

.......................................................................................................................................

SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009

REVISION HISTORY

Changes from Original (February 2007) to Revision A ..................................................................................................

Page

• Added Fast Relock Times Less to list of Features ...............................................................................................................

1

• Changed Last two items in the Differenvces list ...................................................................................................................

2

• Changed Data relock time in the Transmitter Characteristics ..............................................................................................

9

Changes from Revision A (June 2007) to Revision B ....................................................................................................

Page

• Changed From: The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. To: The minimum latency in TBI mode is 20 bit times. The maximum latency in TBI mode is 22 bit times .............

3

• Changed From: The minimum latency in TBI mode is 21 bit times and the maximum latency is 31 bit times. To: The minimum latency in TBI mode is 18 bit times and the maximum latency is 24 bit times. ....................................................

5

Changes from Revision B (March 2009) to Revision C ..................................................................................................

Page

• Changed Pin Function Table - Enable Pin I/O From: P/D to P/U .........................................................................................

7

Copyright © 2007–2009, Texas Instruments Incorporated

Product Folder Link(s):

TLK1221

Submit Documentation Feedback

15

PACKAGE OPTION ADDENDUM

www.ti.com

24-Nov-2014

PACKAGING INFORMATION

Orderable Device

TLK1221RHAR

TLK1221RHARG4

Status

(1)

ACTIVE

ACTIVE

Package Type Package

Drawing

VQFN

VQFN

RHA

RHA

Pins Package

40

40

Qty

Eco Plan

(2)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

MSL Peak Temp

(3)

Level-3-260C-168 HR

Op Temp (°C)

-40 to 85

Level-3-260C-168 HR -40 to 85

Device Marking

(4/5)

TLK1221

TLK1221

TLK1221RHAT ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 TLK1221

TLK1221RHATG4 ACTIVE VQFN RHA 40 250 Green (RoHS

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

CU NIPDAU Level-3-260C-168 HR

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

-40 to 85 TLK1221

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

24-Nov-2014

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

13-Mar-2014

*All dimensions are nominal

Device

TLK1221RHAR

TLK1221RHAT

Package

Type

Package

Drawing

VQFN

VQFN

RHA

RHA

Pins

40

40

SPQ

2500

250

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

16.4

180.0

16.4

A0

(mm)

6.3

6.3

B0

(mm)

6.3

6.3

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.5

1.5

12.0

12.0

16.0

16.0

Q2

Q2

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

13-Mar-2014

*All dimensions are nominal

Device

TLK1221RHAR

TLK1221RHAT

Package Type Package Drawing Pins

VQFN

VQFN

RHA

RHA

40

40

SPQ

2500

250

Length (mm) Width (mm) Height (mm)

336.6

213.0

336.6

191.0

28.6

55.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio

Amplifiers

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

Logic

Power Mgmt

Microcontrollers

RFID

OMAP Applications Processors

Wireless Connectivity www.ti.com/audio amplifier.ti.com

dataconverter.ti.com

www.dlp.com

dsp.ti.com

www.ti.com/clocks interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

Medical

Security www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security

Space, Avionics and Defense www.ti.com/space-avionics-defense

Video and Imaging

TI E2E Community

www.ti.com/wirelessconnectivity www.ti.com/video e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2014, Texas Instruments Incorporated

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project