PCA9564 Parallel bus to I C-bus controller 2

INTEGRATED CIRCUITS

PCA9564

Parallel bus to I

2

C-bus controller

Product data sheet

Supersedes data of 2003 Apr 02

2004 Jun 25

Philips

Semiconductors

Philips Semiconductors

Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

FEATURES

•

Parallel-bus to I

2

C-bus protocol converter and interface

•

Both master and slave functions

•

Multi-master capability

•

Internal oscillator reduces external components

•

Operating supply voltage 2.3 V to 3.6 V

•

5 V tolerant I/Os

•

Standard and fast mode I

2

C capable and compatible with SMBus

•

ESD protection exceeds 2000 V HEM per JESD22-A114,

200 V MM per JESD22-A115, and 1000 V CDM per

JESD22-C101

•

Latch-up testing is done to JEDEC Standard JESD78 which exceed 100 mA.

•

Packages offered: DIP20, SO20, TSSOP20, HVQFN20

APPLICATIONS

•

Add I

2

C-bus port to controllers/processors that do not have one

•

Add additional I

2

C-bus ports to controllers/processors that need multiple I

2

C-bus ports

•

Higher frequency, lower voltage migration path for the PCF8584

•

Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire PC board

DESCRIPTION

The PCA9564 is an integrated circuit designed in CMOS technology that serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I

2

C-bus and allows the parallel bus system to communicate bi-directionally with the

I

2

C-bus. The PCA9564 can operate as a master or a slave and can be a transmitter or receiver. Communication with the I

2

C-bus is carried out on a byte-wise basis using interrupt or polled handshake.

The PCA9564 controls all the I

2

C-bus specific sequences, protocol, arbitration and timing with no external timing element required.

The PCA9564 is similar to the PCF8584 but operates at lower voltages and higher I

@

C frequencies. Other enhancements requested by design engineers have also been incorporated.

Characteristic PCA9564 PCF8584

Voltage range 2.3–3.6 V

360 kHz

4.5–5.5 V

Comments

PCA9564 is 5 V tolerant

90 kHz Faster I

2

C interface Maximum

I master mode

2

C frequency

400 kHz 100 kHz Faster I

2

C interface Maximum slave mode I

2

C frequency

Clock source Internal

Parallel interface

Fast

50 MHz

External Less expensive and more flexible with internal oscillator

Slow Compatible with faster processors

While the PCF8584 supported most parallel-bus microcontrollers/ microprocessors including the Intel 8049/8051, Motorola

6800/68000 and the Zilog Z80, the PCA9564 has been designed to be very similar to the Philips standard 80C51 microcontroller I

2

C hardware so the devices are not code compatible. Additionally, the

PCA9564 does not support the bus monitor “Snoop” mode nor the long distance mode and is not footprint compatible with the

PCF8584.

ORDERING INFORMATION

PACKAGES

20-Pin Plastic DIP

20-Pin Plastic SO

20-Pin Plastic TSSOP

20-Pin Plastic HVQFN

TEMPERATURE RANGE

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

ORDER CODE

PCA9564N

PCA9564D

PCA9564PW

PCA9564BS

TOPSIDE MARK

PCA9564N

PCA9564D

PCA9564

9564

Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.

DRAWING NUMBER

SOT146-1

SOT163-1

SOT360-1

SOT662-1

2004 Jun 25 2

Philips Semiconductors

Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

PIN CONFIGURATION — DIP, SO, TSSOP

D0 1

D1 2

D2 3

D3 4

D4 5

D5 6

D6 7

D7 8

DNU 9

V

SS

10

20 V

DD

19 SDA

18 SCL

17 RESET

16 INT

15 A1

14 A0

13 CE

12 RD

11 WR

SW02260

PIN CONFIGURATION — HVQFN

D3

1

D4

2

D5

3

D6

4

D7

5

TOP VIEW

15

SCL

14

RESET

13

INT

12

A1

11

A0

SW02261

PIN DESCRIPTION

PIN NUMBER

DIP, SO, TSSOP

1, 2, 3, 4,

5, 6, 7, 8

HVQFN

1, 2, 3, 4, 5,

18, 19, 20

9

10

11

6

7

8

12

13

14, 15

16

17

18

19

20

9

10

11, 12

13

14

15

16

17

SYMBOL

D0–D7

DNU

V

SS

WR

RD

CE

A0, A1

INT

RESET

SCL

SDA

V

DD

I

I/O

I/O

Pwr

I

I

I

I

TYPE

I/O

Pwr

O

NAME AND FUNCTION

Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the controller and the CPU. D0 is the least significant bit.

Do not use: must be left floating (pulled LOW internally)

Ground

Write Strobe: When LOW and CE is also LOW, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal.

Read Strobe: When LOW and CE is also LOW, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RD.

Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and the controller are enabled on D0–D7 as controlled by the WR, RD and A0–A1 inputs. When HIGH, places the D0–D7 lines in the 3-State condition.

Address Inputs: Selects the controller internal registers and ports for read/write operations.

Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up device.

Reset: A LOW level clears internal registers resets the I

2

C state machine.

I

2

C-bus serial clock input/output (open-drain).

I

2

C-bus serial data input/output (open-drain).

Power Supply: 2.3 to 3.6 V

2004 Jun 25 3


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

D7 D6 D5 D4

DATA

D3 D2 D1 D0

SDA

PCA9564

SDA CONTROL

FILTER

BUS BUFFER

SD7 SD6 SD5 SD4 SD3 SD2 SD1

I2CDAT – DATA REGISTER – READ/WRITE

SD0

SCL

AA ENSIO STA STO SI

FILTER

SCL CONTROL

ENSIO STA STO SI

TE TO6 TO5 TO4 TO3 TO2 TO1

I2CTO – TIMEOUT REGISTER – WRITE ONLY

TO0

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1

I2CADR – OWN ADDRESS – READ/WRITE

BIT0

ST7 ST6 ST5 ST4 ST3 ST2 ST1

I2CSTA – STATUS REGISTER – READ ONLY

ST0

AA ENSIO STA STO SI CR2 CR1

I2CCON – CONTROL REGISTER – READ/WRITE

CR0

CLOCK SELECTOR

OSCILLATOR

CR0

CR1

CR2

A1 A0

0 1

0 0

1 0

0 0

1 1

INTERRUPT CONTROL

CONTROL BLOCK

POWER–ON

RESET

CE WR RD INT

CONTROL SIGNALS

Figure 1. Block diagram

RESET A1 A0 V

DD

SW02262

2004 Jun 25 4


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

FUNCTIONAL DESCRIPTION

General

The PCA9564 acts as an interface device between standard high-speed parallel buses and the serial I

2

C-bus. On the I

2

C-bus, it can act either as master or slave. Bidirectional data transfer between the I

2

C-bus and the parallel-bus microcontroller is carried out on a byte-wise basis, using either an interrupt or polled handshake.

Internal Oscillator

The PCA9564 contains an internal 9 MHz oscillator which is used for all I

2

C timing. The oscillator requires up to 500

µ s to start-up after ENSIO bit is set to “1”.

Registers

The PCA9564 contains four registers which are used to configure the operation of the device as well as to send and receive serial data.

The registers are selected by setting pins A0 and A1 to the appropriate logic levels before a read or write operation is executed.

CAUTION:

Do not write to I

2

C registers while the I

2

C-bus is busy and the SIO is in master or addressed slave mode.

REGISTER

NAME

I2CSTA

REGISTER

FUNCTION

Status

A1

I2CTO Time-out

I2CDAT Data 0

I2CADR Own address 1

I2CCON Control 1

0

0

A0

0

0

1

0

1

READ/

WRITE

R

W

R/W

R/W

R/W

DEFAULT

F8h

FFh

00h

00h

00h

The Time-out Register, I2CTO: The time-out register is used to determine the maximum time that SCL is allowed to be LOW before the I

2

C state machine is reset.

When the I

2

C interface is operating, I2CTO is loaded in the time-out counter at every SCL transition.

I2CTO

7

TE

6

TO6

5

TO5

4

TO4

3

TO3

2

TO2

1

TO1

0

TO0

Time-out value

The most significant bit of I2CTO (TE) is used as a time-out enable/disable. A “1” will enable the time-out function. The time-out period = (I2CTO[6:0] + 1)

×

113.7

µ s. The time-out value may vary some and is an approximate value.

The time-out register can be used in the following cases:

1. When the SIO, in the master mode, wants to send a START condition and the SCL line is held LOW by some other device.

The SIO waits a time period equivalent to the time-out value for the SCL to be released. In case it is not released, the SIO concludes that there is a bus error, loads 90H in the I2CSTA register, generates an interrupt signal and releases the SCL and

SDA lines. After the microcontroller reads the status register, it needs to send an external reset in order to reset the SIO.

2. In the master mode, the time-out feature starts every time the SCL goes LOW. If SCL stays LOW for a time period equal to or greater than the time-out value, the SIO concludes there is a bus error and behaves in the manner described above.

3. In case of a forced access to the I

2

C-bus. (See more details on page 15.)

The Address Register, I2CADR: I2CADR is not affected by the

SIO hardware. The contents of this register are irrelevant when SIO is in a master mode. In the slave modes, the seven most significant bits must be loaded with the microcontroller’s own slave address.

I2CADR

7 6

BIT7 BIT6

5

BIT5

4

BIT4

3

BIT3 own slave address

2

BIT2

1

BIT1 0

0

The most significant bit corresponds to the first bit received from the

I

2

C-bus after a start condition. A logic 1 in I2CADR corresponds to a

HIGH level on the I

2

C-bus, and a logic 0 corresponds to a LOW level on the bus. The least significant bit is not used but should be programmed with a ‘0’.

The Data Register, I2CDAT: I2CDAT contains a byte of serial data to be transmitted or a byte which has just been received. In master mode, this includes the slave address that the master wants to send out on the I

2

C-bus, with the most significant bit of the slave address in the SD7 bit position and the Read/Write bit in the SD0 bit position.

The CPU can read from and write to this 8-bit register while it is not in the process of shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag is set. Data in I2CDAT remains stable as long as SI is set. Whenever the SIO generates an interrupt, the I2CDAT registers contain the data byte that was just transferred on the I

2

C-bus.

NOTE: The I2CDAT register will capture the serial address as data when addressed via the serial bus. Also, the data register will continue to capture data from the serial bus during 38H so the

I2CDAT register will need to be reloaded when the bus becomes free.

7 6 5 4 3 2 1 0

I2CDAT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

•

SD7 - SD0:

Eight bits to be transmitted or just received. A logic 1 in I2CDAT corresponds to a HIGH level on the I

2

C-bus, and a logic 0 corresponds to a LOW level on the bus.

The Control Register, I2CCON: The microcontroller can read from and write to this 8-bit register. Two bits are affected by the SIO hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the

I

2

C-bus. A Write to the I2CCON register via the parallel interface automatically clears the SI bit, which causes the Serial Interrupt line to be de-asserted and the next clock pulse on the SCL line to be generated. Since none of the registers should be written to via the parallel interface once the Serial Interrupt line has been de-asserted, all the other registers that need to be modified should be written to before the content of the I2CCON register is modified.

7 6 5 4 3 2 1 0

I2CCON AA ENSIO

•

ENSIO

, THE

SIO E

NABLE

B

IT

STA STO SI

CR2

CR1 CR0

ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are ignored, SIO is in the “not addressed” slave state.

ENSIO = “1”: When ENSIO is “1”, SIO is enabled.

After the ENSIO bit is set, it takes 500

µ s for the internal oscillator to start up, therefore, the PCA9564 will enter either the master or the slave mode after this time. ENSIO should not be used to temporarily

2004 Jun 25 5


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564 release the PCA9564 from the I

2

C-bus since, when ENSIO is reset, the I

2

C-bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text).

In the following text, it is assumed that ENSIO = “1”.

•

STA

, THE

START F

LAG

STA = “1”: When the STA bit is set to enter a master mode, the SIO hardware checks the status of the I

2

C-bus and generates a START condition if the bus is free. If the bus is not free, then SIO waits for a

STOP condition (which will free the bus) and generates a START condition after the minimum buffer time (t

BUF

) has elapsed.

If STA is set while SIO is already in a master mode and one or more bytes are transmitted or received, SIO transmits a repeated START condition. STA may be set at any time. STA may also be set when

SIO is an addressed slave.

STA = “0”: When the STA bit is reset, no START condition or repeated START condition will be generated.

•

STO

, THE

STOP F

LAG

STO = “1”: When the STO bit is set while SIO is in a master mode, a

STOP condition is transmitted to the I

2

C-bus. When the STOP condition is detected on the bus, the SIO hardware clears the STO flag.

If the STA and STO bits are both set, then a STOP condition is transmitted to the I

2

C-bus if SIO is in a master mode. SIO then transmits a START condition.

STO = “0”: When the STO bit is reset, no STOP condition will be generated.

•

SI

, THE

S

ERIAL

I

NTERRUPT

F

LAG

SI = “1”: When the SI flag is set, then, if the ENSIO bit is also set, a serial interrupt is requested. SI is set by hardware when one of 24 of the 25 possible SIO states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available.

While SI is set, the LOW period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A HIGH level on the

SCL line is unaffected by the serial interrupt flag. SI must be reset by writing “0” to the SI bit. The SI bit cannot be set by the user.

SI = “0”: When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line.

•

AA

, THE

A

SSERT

A

CKNOWLEDGE

F

LAG

AA = “1”: If the AA flag is set, an acknowledge (LOW level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:

– The “own slave address” has been received

– A data byte has been received while SIO is in the master receiver mode

– A data byte has been received while SIO is in the addressed slave receiver mode

AA = “0”: if the AA flag is reset, a not acknowledge (HIGH level to

SDA) will be returned during the acknowledge clock pulse on SCL when:

– A data byte has been received while SIO is in the master receiver mode

– A data byte has been received while SIO is in the addressed slave receiver mode

– “Own slave address” has been received

When SIO is in the addressed slave transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 5).

When SI is cleared, enters the not addressed slave receiver mode, and the SDA line remains at a HIGH level. In state C8H, the AA flag can be set again for future address recognition.

When SIO is in the not addressed slave mode, its own slave address is ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO can be temporarily released from the I

2

C-bus while the bus status is monitored. While

SIO is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag.

•

T

HE

C

LOCK

R

ATE

B

ITS,

CR

2,

CR

1, AND

CR

0

Three bits determine the serial clock frequency when SIO is in master mode. The various serial rates are shown in Table 1.

The clock frequencies only take the HIGH and LOW times into consideration. The rise and fall time will cause the actual measured frequency to be lower than expected.

The frequencies shown in Table 1 are unimportant when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize with any clock frequency up to 400 kHz.

Table 1. Serial Clock Rates

CR2 CR1 CR0

SERIAL CLOCK FREQUENCY

(kHz)

1

1

1

1

0

0

0

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

330

288

217

146

88

1

59

44

36

NOTE:

1. The clock frequency values are approximate and may vary with temperature, supply voltage, process, and SCL output loading. If normal mode I

2

C parameters must be strictly followed

(SCL < 100kHz), it is recommended not to use

CR[2:0] = 100 (SCL = 88kHz) since the clock frequency might be slightly higher than 100 kHz under certain temperature, voltage, and process conditions and use CR[2:0] = 101 (SCL = 59 kHz) instead.

The Status Register, I2CSTA: I2CSTA is an 8-bit read-only register.

The three least significant bits are always zero. The five most significant bits contain the status code. There are 25 possible status codes. When I2CSTA contains F8H, no relevant state information is available and no serial interrupt is requested. All other I2CSTA values correspond to defined SIO states. When each of these states is entered, a serial interrupt is requested (SI = “1”).

2004 Jun 25 6


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

More Information on SIO Operating Modes

The four operating modes are:

– Master Transmitter

– Master Receiver

– Slave Receiver

– Slave Transmitter

Data transfers in each mode of operation are shown in Figures 2–5.

These figures contain the following abbreviations:

Abbreviation

S

SLA

R

W

A

A

Data

P

Explanation

Start condition

7-bit slave address

Read bit (HIGH level at SDA)

Write bit (LOW level at SDA)

Acknowledge bit (LOW level at SDA)

Not acknowledge bit (HIGH level at SDA)

8-bit data byte

Stop condition

In Figures 2-5, circles are used to indicate when the serial interrupt flag is set. A serial interrupt is not generated when I2CSTA = F8H.

This happens on a stop condition. The numbers in the circles show the status code held in the I2CSTA register. At these points, a service routine must be executed to continue or complete the serial transfer.

These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software.

When a serial interrupt routine is entered, the status code in I2CSTA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Tables 2-6.

Master Transmitter Mode: In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see

Figure 2). Before the master transmitter mode can be entered,

I2CCON must be initialized as follows:

I2CCON

7

AA

X

6

ENSIO

1

5

STA

0

4

STO

0

3

SI

0

2

CR2

1

CR1 bit rate

0

CR0

ENSIO must be set to logic 1 to enable SIO. If the AA bit is reset,

SIO will not acknowledge its own slave address in the event of another device becoming master of the bus. In other words, if AA is reset, SIO cannot enter a slave mode. STA, STO, and SI must be reset.

The master transmitter mode may now be entered by setting the

STA bit. The SIO logic will now test the I

2

C-bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (I2CSTA) will be 08H. This status code must be used to vector to an interrupt service routine that loads I2CDAT with the slave address and the data direction bit

(SLA+W). The SI bit in I2CCON must then be reset before the serial transfer can continue.

When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in I2CSTA are possible. There are 18H, 20H, or 38H for the master mode and also

68H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 2. After a repeated start condition (state 10H). SIO may switch to the master receiver mode by loading I2CDAT with

SLA+R).

Note that a master should never transmit its own slave address.

2004 Jun 25 7

Master Receiver Mode: In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 3). The transfer is initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load I2CDAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in I2CCON must then be cleared before the serial transfer can continue.

When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in

I2CSTA are possible. These are 40H, 48H, or 38H for the master mode and also 68H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 3. ENSIO is not affected by the serial transfer and are not referred to in Table 3. After a repeated start condition (state 10H), SIO may switch to the master transmitter mode by loading I2CDAT with SLA+W.

Note that a master should not transmit its own slave address.

Slave Receiver Mode: In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 4). To initiate the slave receiver mode, I2CADR and I2CCON must be loaded as follows:

I2CADR

7 6

BIT7 BIT6

5 4 3

BIT5 BIT4 BIT3 own slave address

2

BIT2

1

BIT1 0

0

The upper 7 bits are the address to which SIO will respond when addressed by a master.

I2CCON

7

AA

1

6

ENSIO

1

5

STA

0

4

STO

0

3

SI

0

2

CR2

X

1

CR1

X

0

CR0

X

ENSIO must be set to logic 1 to enable SIO. The AA bit must be set to enable SIO to acknowledge its own slave address, STA, STO, and SI must be reset.

When I2CADR and I2CCON have been initialized, SIO waits until it is addressed by its own slave address followed by the data direction bit which must be “0” (W) for SIO to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (I) is set and a valid status code can be read from I2CSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 4. The slave receiver mode may also be entered if arbitration is lost while SIO is in the master mode (see status 68H).

If the AA bit is reset during a transfer, SIO will return a not acknowledge (logic 1) to SDA after the next received data byte.

While AA is reset, SIO does not respond to its own slave address.

However, the I

2

C-bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO from the I

2

C-bus.


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

MT

SUCCESSFUL TRANSMISSION

TO A SLAVE RECEIVER

ÇÇÇÇÇÇÇÇ

A

ÇÇÇÇÇÇÇÇ ÇÇÇ ÇÇÇ

A

ÇÇÇ

08H

18H

28H F8

NEXT TRANSFER STARTED WITH A REPEATED START CONDITION

ÇÇÇÇÇÇÇ

S SLA W

ÇÇÇÇÇÇÇ

ÇÇÇÇÇÇÇ

10H

NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS

A

20H

ÇÇÇ

F8H

ÇÇÇ

NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE

A

ÇÇÇ TO MST/REC MODE

ENTRY = MR

ÇÇÇ

30H F8H

ARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTE

A or A

OTHER MST

CONTINUES

38H

A or A

OTHER MST

CONTINUES

38H

ARBITRATION LOST AND ADDRESSED AS SLAVE

A

OTHER MST

CONTINUES

68H

TO CORRESPONDING STATES IN

SLAVE RECEIVER MODE


SLAVE TRANSMITTER MODE

ÇÇÇÇ

FROM MASTER TO SLAVE

ÇÇÇÇ

ÇÇÇÇ

FROM SLAVE TO MASTER

B0H

ÇÇÇ ÇÇÇÇ ÇÇ

Data

ÇÇ ÇÇÇ

A

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS

ÇÇ ÇÇÇ n

THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 2.

NOTE: THE MASTER SHOULD NEVER TRANSMIT ITS OWN SLAVE ADDRESS

Figure 2. Format and states in the master transmitter mode

SW00816

2004 Jun 25 8


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

MR

SUCCESSFUL RECEPTION

ÇÇÇÇÇÇÇÇ

FROM A SLAVE TRANSMITTER

A

ÇÇÇÇÇÇÇÇ

REPEATED START CONDITION

08H

NEXT TRANSFER STARTED WITH A

40H

DATA A DATA A P

ÇÇÇ ÇÇÇÇ ÇÇÇ ÇÇÇ

50H 58H F8H

ÇÇÇÇÇÇÇ

S SLA R

ÇÇÇÇÇÇÇ

ÇÇÇÇÇÇÇ

10H

NOT ACKNOWLEDGE RECEIVED

AFTER THE SLAVE ADDRESS

ÇÇÇ ÇÇÇ

48H F8H

ARBITRATION LOST IN SLAVE ADDRESS

OR ACKNOWLEDGE BIT

A or A

38H

OTHER MST

CONTINUES

ARBITRATION LOST AND ADDRESSED AS SLAVE

A

OTHER MST

CONTINUES

68H

B0H


SLAVE RECEIVER MODE


SLAVE TRANSMITTER MODE

ÇÇÇÇ


ÇÇÇÇ ÇÇÇÇ


ÇÇÇÇ

ÇÇ ÇÇÇÇ

DATA A

ÇÇ

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n


ÇÇÇ

A

OTHER MST

CONTINUES

ÇÇÇ

38H

TO MST/TRX MODE

ENTRY = MT

SW00817

Figure 3. Format and states in the master receiver mode

2004 Jun 25 9


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

RECEPTION OF THE OWN SLAVE ADDRESS

AND ONE OR MORE DATA BYTES

ALL ARE ACKNOWLEDGED.

ÇÇÇÇÇÇÇ

S SLA W

ÇÇÇÇÇÇÇ

A

ÇÇÇÇ ÇÇÇ

DATA A

ÇÇÇÇ ÇÇÇ

ÇÇÇ

DATA

ÇÇÇ

A

ÇÇÇ

P or S

ÇÇÇ

60H

80H 80H A0H

LAST DATA BYTE RECEIVED IS

NOT ACKNOWLEDGED

ARBITRATION LOST AS MST AND

ADDRESSED AS SLAVE

A

ÇÇÇ

A

P or S

ÇÇÇ

ÇÇÇ

88H F8H

ON STOP

ÇÇÇÇ


ÇÇÇÇ ÇÇÇÇ


ÇÇÇÇ

ÇÇÇ ÇÇÇÇ ÇÇ

Data A

ÇÇ ÇÇÇ

68H

ÇÇÇ

P or S

ÇÇÇ

ÇÇÇ

F8

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS

ON STOP n


Figure 4. Format and states in the slave receiver mode

SW00814

RECEPTION OF THE

OWN SLAVE ADDRESS

ÇÇÇÇÇÇÇÇ

AND TRANSMISSION

S SLA R A

OF ONE OR MORE

DATA BYTES

ÇÇÇÇÇÇÇÇ

ÇÇÇÇÇÇÇÇ

A8H

DATA


A DATA A P or S



B8H C0H F8H

ON STOP

ARBITRATION LOST AS MST

AND ADDRESSED AS SLAVE A

ÇÇÇÇ

ÇÇÇÇ

ÇÇÇÇ ÇÇÇÇ


ÇÇÇÇ


B0H

LAST DATA BYTE TRANSMITTED.

SWITCHED TO NOT ADDRESSED

SLAVE (AA BIT IN I2CCON = “0”)

ÇÇÇ

A

ÇÇÇ

All “1”s

ÇÇÇ

C8H

ÇÇ ÇÇÇÇ

DATA A

ÇÇ

ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n

ÇÇ


ÇÇÇ

P or S

ÇÇÇ

ÇÇÇ

F8H

ON STOP

SW00815

Figure 5. Format and states of the slave transmitter mode

2004 Jun 25 10


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

Table 2. Master Transmitter Mode

CODE

08H

10H

18H

20H

28H

30H

38H

A START condition has been transmitted

A repeated START diti h b transmitted

D

STATUS OF THE

b

I

2

b

C BUS AND

SLA+W has been transmitted; ACK has

SLA+W or i d

SLA+W has been transmitted; NOT ACK h

NOT ACK h i b

Arbitration lost in d

Data byte in I2CDAT has been transmitted;

APPLICATION SOFTWARE RESPONSE

TO I2CCON

Load SLA+W

Load SLA+W or

Load SLA+R

Load data byte or no I2CDAT action or no I2CDAT action or no I2CDAT action


NEXT ACTION TAKEN BY SIO HARDWARE

STA STO SI AA

X X 0 X SLA+W will be transmitted;

ACK bit will be received

X

X

0

1

0

1

0

1

0

1

X

X

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

X As above

X SLA+R will be transmitted;

SIO will be switched to MST/REC mode

X Data byte will be transmitted;


X Repeated START will be transmitted;

X STOP condition will be transmitted;

STO flag will be reset

X STOP condition followed by a

START condition will be transmitted;










0 0 0 Data byte in I2CDAT Load data byte or has been transmitted;

ACK h b i d no I2CDAT action or no I2CDAT action or no I2CDAT action


No I2CDAT action or

No I2CDAT action

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

















X I

2

C-bus will be released; not addressed slave will be entered

X A START condition will be transmitted when the bus becomes free (STOP or SCL and SDA high)

2004 Jun 25 11


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

Table 3. Master Receiver Mode

CODE

08H

STATUS OF THE

I

2

C BUS AND


TO I2CCON

Load SLA+R

STA STO SI

X X 0

AA

X

10H

A START condition has been transmitted

A repeated START diti h b transmitted

Load SLA+R or

Load SLA+W

X

X

X

X

0

0

X

X

38H Arbitration lost in

NOT ACK bit

No I2CDAT action or 0 0 0 X

No I2CDAT action 1 0 0 X

40H

48H

50H

58H

38H

SLA+R has been transmitted; ACK has i d

SLA+R has been t itt d NOT ACK has been received

Data byte has been received; ACK has been

Read data byte or read data byte

Data byte has been i d NOT ACK h been returned

Arbitration lost in

SLA+R

No I2CDAT action or no I2CDAT action

No I2CDAT action or no I2CDAT action or no I2CDAT action

Read data byte or read data byte or read data byte

No I2CDAT action or

No I2CDAT action

0

0

0

0

1

0

1

1

0

1

0

1

0

0

0

0

0

1

1

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

X

X

X

X

X

X

X

X


SLA+R will be transmitted;


As above

SLA+W will be transmitted;

SIO will be switched to MST/TRX mode

I

2

C-bus will be released;

SIO will enter a slave mode

A START condition will be transmitted when the bus becomes free

Data byte will be received;

NOT ACK bit will be returned


ACK bit will be returned

Repeated START condition will be transmitted

STOP condition will be transmitted;


STOP condition followed by a




NOT ACK bit will be returned


ACK bit will be returned

Repeated START condition will be transmitted

STOP condition will be transmitted;


STOP condition followed by a



I

2

C-bus will be released; not addressed slave will be entered

A START condition will be transmitted when the bus becomes free

2004 Jun 25 12


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

Table 4. Slave Receiver Mode

CODE

60H

68H

STATUS OF THE

I

2

C BUS AND

Own SLA+W has been received; ACK h b d

Arbitration lost in

SLA+R/W as master;

Own SLA+W has been received, ACK returned

No I2CDAT action or no I2CDAT action

No I2CDAT action or


TO I2CCON NEXT ACTION TAKEN BY SIO HARDWARE

STA STO SI AA

X X 0 0 Data byte will be received and NOT ACK will be returned

X X 0 1 Data byte will be received and ACK will be returned

X X 0 0 Data byte will be received and NOT ACK will be returned no I2CDAT action X X 0 1 Data byte will be received and ACK will be returned

80H Previously addressed with own SLV address; DATA has been received; ACK has been returned

Read data byte or read data byte

X

X

X

X

0

0

0 Data byte will be received and NOT ACK will be returned

1 Data byte will be received and ACK will be returned

88H

A0H

Previously addressed with own SLA; DATA b h b received; NOT ACK

A STOP condition or repeated START di i h b received while still

SLV/REC

Read data byte or read data byte or read data byte or read data byte

No I2CDAT action or

No I2CDAT action or

No I2CDAT action or

No I2CDAT action

0

0

1

1

0

0

1

1

X

X

X

X

X

X

X

X

0

0

0

0

0

0

0

0

0 Switched to not addressed SLV mode; no recognition of own SLA

1 Switched to not addressed SLV mode; Own SLA will be recognized

0 Switched to not addressed SLV mode; no recognition of own SLA. A START condition will be transmitted when the bus becomes free

1 Switched to not addressed SLV mode; Own SLA will be recognized. A START condition will be transmitted when the bus becomes free.





2004 Jun 25 13


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

Table 5. Slave Transmitter Mode

CODE

A8H

B0H

STATUS OF THE

I

2

C BUS AND

Own SLA+R has been received; ACK h b d

Arbitration lost in

SLA+R/W as master;


TO I2CCON

Load data byte or load data byte

Load data byte or


STA STO SI AA

X

X

X

X

0

0

0 Last data byte will be transmitted and ACK bit will be received

1 Data byte will be transmitted; ACK will be received

X X 0 0 Last data byte will be transmitted and ACK bit will be received load data byte X X 0

B8H

C0H

C8H been received, ACK has been returned


ACK h b received


NOT ACK h b received

Last data byte in

I2CDAT has been i d (AA 0)

ACK has been

Load data byte or load data byte

No I2CDAT action or no I2CDAT action or no I2CDAT action or no I2CDAT action

No I2CDAT action or no I2CDAT action or no I2CDAT action or no I2CDAT action

X

X

0

0

1

1

0

0

1

1

X

X

X

X

X

X

X

X

X

X

0

0

0

0

0

0

0

0

0

0

1 Data byte will be transmitted; ACK bit will be received

0 Last data byte will be transmitted and ACK bit will be received

1 Data byte will be transmitted; ACK bit will be received









Table 6. Miscellaneous States

CODE

F8H

70H

STATUS OF THE

I

2

C BUS AND

On reset or STOP


No I2CDAT action

TO I2CCON

STA STO SI AA

1 X 0


X Go into master mode; send START

No I2CDAT action

No I2CDAT action

0

0

X

X

0

0

0

1

No recognition of own SLA

Will recognize own SLA

Reset SIO (Requires reset to return to state F8H)

90H

00H

Bus error

SDA stuck LOW

Bus error

SCL stuck LOW

Bus error during master or slave mode, due to illegal

START or STOP condition



2004 Jun 25 14


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

Slave Transmitter Mode: In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 5).

Data transfer is initialized as in the slave receiver mode. When

I2CADR and I2CCON have been initialized, SIO waits until it is addressed by its own slave address followed by the data direction bit which must be “1” (R) for SIO to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from I2CSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 5. The slave transmitter mode may also be entered if arbitration is lost while SIO is in the master mode (see state B0H).

If the AA bit is reset during a transfer, SIO will transmit the last byte of the transfer and enter state C8H. SIO is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, SIO does not respond to its own slave address. However, the I

2

C-bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO from the

I

2

C-bus.

Miscellaneous States: There are four I2CSTA codes that do not correspond to a defined SIO hardware state (see Table 6). These are discussed below.

I2CSTA = F8H:

This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs on a

STOP condition and when SIO is not involved in a serial transfer.

I2CSTA = 00H:

This status code indicates that a bus error has occurred during an

SIO serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal SIO signals.

When a bus error occurs, SI is set. To recover from a bus error, the microcontroller must send an external reset signal to reset the SIO.

I2CSTA = 70H:

This status code indicates that the SDA line is stuck LOW when the

SIO, in master mode, is trying to send a START condition.

I2CSTA = 90H:

This status code indicates that the SCL line is stuck LOW.

Some Special Cases: The SIO hardware has facilities to handle the following special cases that may occur during a serial transfer:

•

S

IMULTANEOUS

R

EPEATED

START C

ONDITIONS FROM

T

WO

M

ASTERS

A repeated START condition may be generated in the master transmitter or master receiver modes. A special case occurs if another master simultaneously generates a repeated START condition (see Figure 6). Until this occurs, arbitration is not lost by either master since they were both transmitting the same data.

If the SIO hardware detects a repeated START condition on the

I

2

C-bus before generating a repeated START condition itself, it will use the repeated START as its own and continue with the sending of the slave address.

•

D

ATA

T

RANSFER

A

FTER

L

OSS OF

A

RBITRATION

Arbitration may be lost in the master transmitter and master receiver modes. Loss of arbitration is indicated by the following states in

I2CSTA; 38H, 68H, and B0H (see Figures 2 and 3).

NOTE: In order to exit state 38H, a Timeout, Reset, or external

Stop are required.

If the STA flag in I2CCON is set by the routines which service these states, then, if the bus is free again, a START condition (state 08H) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence.

•

F

ORCED

A

CCESS TO THE

I

2

C B

US

In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL.

If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I

2

C-bus stays busy indefinitely. If the

STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I

2

C-bus is possible. If the I

2

C-bus stays idle for a time period equal to the time out period, then the ’64 concludes that no other master is using the bus and sends a START condition.

S SLA W A

08H 18H

DATA A S

28H

BOTH MASTERS CONTINUE

WITH SLA TRANSMISSION

OTHER MASTER SENDS REPEATED

START CONDITION EARLIER

Figure 6. Simultaneous repeated START conditions from 2 masters

SU00975

2004 Jun 25 15


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

TIME OUT

STA FLAG

SDA LINE

SCL LINE

START CONDITION

SU00976

Figure 7. Forced access to a busy I

2

C-bus

•

I

2

C B

US

O

BSTRUCTED BY A

LOW L

EVEL ON

SCL

OR

SDA

An I

2

C-bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the SIO hardware cannot resolve this type of problem. When this occurs, the problem must be resolved by the device that is pulling the SCL bus line LOW.

When the SCL line stays LOW for a period equal to the time-out value, the ’64 concludes that this is a bus error and behaves in a manner described on page 5 under “Time-out Register”.

If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the SCL line (see

Figure 8). The SIO hardware sends out nine clock pulses followed by the STOP condition. If the SDA line is released by the slave pulling it LOW, a normal START condition is transmitted by the SIO, state 08H is entered and the serial transfer continues. If the SDA line is not released by the slave pulling it LOW, then the SIO concludes that there is a bus error, loads 70H in I2CSTA, generates an interrupt signal, and releases the SCL and SDA lines. After the microcontroller reads the status register, it needs to send an external reset signal in order to reset the SIO.

If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the SIO hardware performs the same action as described above. In each case, state 08H is entered after a successful START condition is transmitted and normal serial transfer continues. Note that the CPU is not involved in solving these bus hang-up problems.

•

B

US

E

RROR

A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit.

The SIO hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, SIO releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 00H. This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 6. The microcontroller must send an external reset signal to reset the SIO.

STA FLAG

SDA LINE

SCL LINE

1 2 3 4 5 6 7 8 9

STOP

CONDITION

START

CONDITION su01663

Figure 8. Recovering from a bus obstruction caused by a LOW level on SDA

2004 Jun 25 16


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

I

2

C-BUS TIMING DIAGRAMS

The diagrams (Figures 9 to 12) illustrate typical timing diagrams for the PCA9564 in master/slave functions.

SCL

SDA

INT

7-bit address

R/W = 0

ACK interrupt

START condition from slave receiver

Master PCA9564 writes data to slave transmitter.

first-byte

ACK interrupt nbyte

Figure 9. Bus timing diagram; master transmitter mode

ACK interrupt

STOP condition su01490

SCL

SDA

INT

7-bit address

R/W = 1

ACK interrupt

START condition from slave

Master PCA9564 reads data from slave transmitter.

first-byte

ACK interrupt nbyte from master receiver

Figure 10. Bus timing diagram; master receiver mode

no ACK


2004 Jun 25 17


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

SCL

SDA

INT

7-bit address

R/W = 1

ACK interrupt

START condition from slave PCA9564

External master receiver reads data from PCA9564.

first-byte

ACK interrupt nbyte from master receiver

Figure 11. Bus timing diagram; slave transmitter mode

no ACK interrupt


SCL

SDA

INT

7-bit address

R/W = 0

ACK interrupt

START condition from slave PCA9564 first-byte

ACK interrupt nbyte

Slave PCA9564 is written to by external master transmitter.

Figure 12. Bus timing diagram; slave receiver mode

ACK interrupt

STOP condition interrupt

(after STOP) su01493

2004 Jun 25 18


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

V

DD

80C51

ALE

ADDRESS BUS

DECODER

8

V

DD

V

DD

A0

A1

CE

PCA9564

SCL

D[0:7]

RD

WR

SDA

INT

RESET

V

SS

V

DD

SLAVE

INT RESET

V

DD

V

SS

SD00705

Figure 13. Application diagram using the 80C51

2004 Jun 25 19


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

SPECIFIC APPLICATIONS

The PCA9564 is a parallel bus to I

2

C bus controller that is designed to allow “smart” devices to interface with I

2

C or SMBus components , where the “smart” device does not have an integrated I

2

C port and the designer does not want to “bit-bang” the I

2

C port. The PCA9564 can also be used to add more I

2

C ports to “smart” devices, provide a higher frequency, lower voltage migration path for the PCF8584 and convert 8 bits of parallel data to a serial bus to avoid running multiple traces across the PC board.

ADD I

2

C BUS PORT

As shown in Figure 14, the PCA9564 converts 8-bits of parallel data into a multiple master capable I

2

C port for microcontrollers, microprocessors, custom ASICs, DSPs, etc., that need to interface with I

2

C or SMBus components.

PCA8584 MIGRATION PATH

The PCA9564 does the same type of parallel to serial conversion as the PCF8584. Although not footprint or code compatible, the

PCA9564 provides improvements such as:

1. Operating at 3.3 V and 2.5 V voltage nodes with 5 V tolerant I/Os

2. Allows interface with I

2

C or SMBus components at speeds up to

400 kHz.

3. Built-in oscillator provides a cost effective solution since the external clock input is no longer required.

4. Parallel data can be exchanged at speeds up to 50 MHz allowing the use of faster processors.

SUPPLY VOLTAGE FREQUENCY

2.3 – 3.6 V

<

400 kHz

4.5 – 5.5 V

< 1

00 kHz

PCA9564

OSCILLATOR

SDA

SCL

MICROCONTROLLER,

MICROPROCESSOR,

OR ASIC

CONTROL SIGNALS

8-BITS

PCA9564

SDA

SCL

Figure 14. Adding I

2

C Bus Port Application

SW02108

PCF8584

SDA

SCL

CLOCK INPUT

SW02110

Figure 16. PCF8584 Migration Path

ADD ADDITIONAL I

2

C BUS PORTS

The PCA9564 can be used to convert 8-bit parallel data into additional multiple master capable I

2

C port as shown in Figure 15. It is used if the microcontroller, microprocessor, custom ASIC, DSP, etc., already have an I

2

C port but need one or more additional I

2

C ports to interface with more I

2

C or SMBus components or components that cannot be located on the same bus (e.g., 100 kHz and 400 kHz slaves on different buses so that each bus can operate at its maximum potential).

CONVERT 8 BITS OF PARALLEL DATA INTO I

2

C

SERIAL DATA STREAM

Functioning as a slave transmitter, the PCA9564 can convert 8-bit parallel data into a two-wire I

2

C data stream as is shown in

Figure 17. This would prevent having to run 8 traces across the entire width of the PC board.

SDA

SCL

MICROCONTROLLER,

MICROPROCESSOR,

OR ASIC

CONTROL SIGNALS

PCA9564

SDA

SCL

8-BITS

SW02109

Figure 15. Adding Additional I

2

C Bus Ports Application

MICROCONTROLLER,

MICROPROCESSOR,

OR ASIC

CONTROL

SIGNALS

8-BITS

PCA9564

SDA

SCL

MASTER

SW02111

Figure 17. Converting Parallel to Serial Data Application

2004 Jun 25 20


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN MAX UNIT

V

DD

V

I

I

I

Supply voltage

Voltage range (any input)

DC input current (any input)

–0.3

–0.8

–10

4.6

6.0

10

1

V

V mA

I

O

P tot

DC output current (any output)

Total power dissipation

–10

—

10

300 mA mW

P

O

Power dissipation per output — 50 mW

T amb

Operating ambient temperature –40 +85

°

C

T stg

Storage temperature –65 +150

°

C

NOTE:

1. 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”

Handling MOS devices”.

DC CHARACTERISTICS

V

DD

= 2.3 V to 3.6 V; T amb

= –40 to +85

°

C; unless otherwise specified.

SYMBOL PARAMETER

Supplies

CONDITIONS MIN TYP MAX UNIT

V

I

I

DD

Supply voltage

V

POR

Power-on Reset voltage

Inputs WR, RD, A0, A1, CE, RESET

standby operating – no load

2.3

—

—

—

—

0.1

—

1.8

3.6

3.0

6.0

2.2

V

IL

V

IH

I

L

C

I

LOW level input voltage

HIGH level input voltage

Leakage current

Input capacitance

Inputs/outputs D0 to D7

V

IL

V

IH

I

OH

I

OL



HIGH level output current

LOW level output current

I

L

C

IO

Leakage current

Input/output capacitance

SDA and SCL

Input; V

V

I

V

V

Input; V

V

I

= V

SS

OH

OL

= V

SS

I

= V

I

= 0 V or 5.5 V

or V

DD

= 0.4 V

DD

– 0.4 V

= 0 V or 5.5 V

or V

DD

0

2.0

–1

—

0

2.0

–4.0

4.0

–1

—

—

—

—

1.7

—

—

–7.0

8.0

—

2.4

0.8

5.5

1

3

0.8

5.5

—

—

1

4

1

1

V

V mA mA

µ

A pF

V

IL

V

I

IH



I

OL

C

IO

Outputs INT


Input/output capacitance

Input/output; V

I

= 0 V or 3.6 V

Input/output; V

I

= 5.5 V

V

V

I

OL

= 0.4 V

= V

SS

or V

DD

0

0.7 V

DD

–1

–1

5.0

—

—

—

—

—

8.5

2.5

0.3 V

5.5

1

10

—

4

DD

1

µ

V

V

A mA pF

I

OL

I

L


Leakage current

V

OL

= 0.4 V

V

O

= 0 or 3.6 V

3.0

–1

—

—

—

1 mA

µ

A

C

O

Output capacitance V

I

= V

SS

or V

DD

— 2.1

4

NOTE:

1. 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.

pF

V

V

µ

A pF

V

µ

A mA

V

2004 Jun 25 21


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

SDA t

F t

LOW t

R t

SU;DAT t

F t

HD;STA t

SP t

R t

BUF

SCL

S t

HD;STA t

HD;DAT t

HIGH t

SU;STA

S

R t

SU;STO

P S

SU01755

Figure 18. Definition of timing

I

2

C-BUS TIMING SPECIFICATIONS

All the timing limits are valid within the operating supply voltage and ambient temperature range; V

DD

= 2.5 V

±

0.2 V and 3.3 V

±

0.3 V,

T amb

= –40 to +85

°

C; and refer to V

IL

and V

IH

with an input voltage of V

SS

to V

DD

.

SYMBOL PARAMETER

STANDARD MODE

I

2

C BUS

FAST MODE

I

2

C BUS

UNITS

MIN MAX MIN MAX

f

SCL t

BUF t

HD;STA t

SU;STA t

SU;STO t

HD;DAT t

VD;ACK t

VD;DAT(L) t

VD;DAT(H) t

SU;DAT t

LOW t

HIGH t

F t

R t

SP

Operating frequency

Bus free time between STOP and START conditions

Hold time after (repeated) START condition

Repeated START condition setup time

Setup time for STOP condition

Data in hold time

Valid time for ACK condition

Data out valid time LOW

Data out valid time HIGH

Data setup time

Clock LOW period

Clock HIGH period

Clock/Data fall time

Clock/Data rise time

Pulse width of spikes that must be suppressed by the input filters

0

4.7

4.0

4.7

4.0

0

—

—

—

250

4.7

4.0

—

—

—

100

—

—

0.6

0.6

0.6

—

—

—

0.3

1

—

—

—

50

0

1.3

0.6

0.6

0.6

—

100

1.3

0.6

—

—

0

—

—

—

400

—

—

0.6

0.6

0.6

—

—

—

0.3

0.3

—

—

—

50 ns

µ s

µ s

µ s

µ s ns kHz

µ s

µ s

µ s

µ s ns

µ s

µ s

µ s

2004 Jun 25 22


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

START

ACK OR READ CYCLE

SCL

SDA

30%

RESET

50% t

REC

Dn

Figure 19. Reset timing

50% t

RES

50% t

WRES t

RES

50%

LED OFF

SW02107

A0–A1

CE t

AS t

AH t

CS t

RW

RD

D0–D7

(READ)

FLOAT

WR t

DD

NOT

VALID

D0–D7

(WRITE) t

CH t

RWD

VALID t

DF t

RWD

FLOAT t

DS t

DH

VALID

Figure 20. Bus timing

SD00711

2004 Jun 25 23


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

AC CHARACTERISTICS (3.3 VOLT)

1, 2, 3

V

CC

= 3.3 V

±

3.0 V, T amb

= –40 to +85

°

C, unless otherwise specified. (See page 25 for 2.5 V.)

ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ

LIMITS

SYMBOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Min Max

ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

Reset Timing (See Figure 19)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ t

WRES

Reset pulse width 10 — ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ t

RES

4,5

Time to reset 250 — ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ t

REC

Reset recovery time 0 — ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ

Bus Timing (See Figure 20, 21)

ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ t

AS

A0–A1 setup time to RD, WR LOW 0 — ns


AH

A0–A1 hold time from RD, WR LOW 7 — ns


CS

CE setup time to RD, WR LOW 0 — ns t

CH

CE Hold time from RD, WR LOW 0 — ns t

RW

WR, RD pulse width (Low time)


7 — ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ t

DD

Data valid after RD and CE LOW — 17 ns


DF

Data bus floating after RD or CE HIGH — 17 ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ t

DS

Data bus setup time before WR or CE HIGH (write cycle) 7 — ns


DH

Data hold time after WR HIGH 0 — ns


RWD

High time between read and/or write cycles 12 — ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21.

3. Test conditions for outputs: C pullup to V

DD

.

L

= 50 pF, R

L

= 500

Ω

, except open drain outputs. Test conditions for open drain outputs: C

L

= 50 pF, R

L

4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.

= 1 k

Ω

5. Upon reset, the full delay will be the sum of t

RES

and the RC time constant of the SDA and SCL bus.

2004 Jun 25 24


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

AC CHARACTERISTICS (2.5 VOLT)

1, 2, 3

V

CC

= 2.5 V

±

0.2 V, T amb

= –40 to +85

°

C, unless otherwise specified. (See page 24 for 3.3 V.)

ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ

LIMITS

SYMBOL


Min Max

ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

Reset Timing (See Figure 19)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ t

WRES

Reset pulse width 10 — ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ t

RES

4,5

Time to reset 250 — ns


REC

Reset recovery time 0 — ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ

Bus Timing (See Figure 20, 21)

ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ t

AS

A0–A1 setup time to RD, WR LOW 0 — ns


AH

A0–A hold time from RD, WR LOW 9 — ns


CS

CE setup time to RD, WR LOW 0 — ns t

CH

CE Hold time from RD, WR LOW 0 — ns t

RW

WR, RD pulse width (low time)


9 — ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ t

DD

Data valid after RD and CE LOW — 22 ns


DF

Data bus floating after RD or CE HIGH — 17 ns


DS

Data bus setup time before WR or CE HIGH (write cycle) 8 — ns


DH

Data hold time after WR HIGH 0 — ns


RWD

High time between read and/or write cycles 12 — ns

ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21.

3. Test conditions for outputs: C pullup to V

DD

.

L

= 50 pF, R

L

= 500

Ω

, except open drain outputs. Test conditions for open drain outputs: C

L

= 50 pF, R

L

4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.

= 1 k

Ω

5. Upon reset, the full delay will be the sum of t

RES

and the RC time constant of the SDA and SCL bus.

2004 Jun 25 25


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

RD, CE INPUT

V

I

GND

V

M

V

M t

DF(LZ) t

DD(ZL)

Dn OUTPUT

LOW-TO-FLOAT

FLOAT-TO-LOW

V

CC

V

OL

V

X t

DF(HZ) t

DD(ZH)

V

OH

Dn OUTPUT

HIGH-TO-FLOAT

V

Y

FLOAT-TO-HIGH

GND

OUTPUTS ENABLED

OUTPUTS

FLOATING

V

M

= 1.5 V

V

V

X

= V

Y

=

OL

V

OH

+ 0.3 V

– 0.3 V

V

OL

AND V

OH

ARE TYPICAL OUTPUT VOLTAGE DROPS THAT OCCUR WITH THE OUTPUT LOAD.

Figure 21. t

DD

and t

DF

times

V

M

V

M

OUTPUTS ENABLED

SW02113

VCC

PULSE

GENERATOR

VI

R

T

D.U.T.

VO

CL

50 pF

R

L

= 500

Ω

6.0 V

Open

R

L

= 500

Ω

TEST

t

PLZ/ t

PZL t

PLH/ t

PHL

S1

6 V

Open

DEFINITIONS

R

L

= Load resistor.

C

L

= Load capacitance includes jig and probe capacitance

R

T

= Termination resistance should be equal to the output impedance Z

O

of the pulse generators.

SW02114

Figure 22. Test circuitry for switching times

2004 Jun 25 26


Parallel bus to I

2

C-bus controller

DIP20: plastic dual in-line package; 20 leads (300 mil)

Product data sheet

PCA9564

SOT146-1

2004 Jun 25 27


Parallel bus to I

2

C-bus controller

SO20: plastic small outline package; 20 leads; body width 7.5 mm

Product data sheet

PCA9564

SOT163-1

2004 Jun 25 28


Parallel bus to I

2

C-bus controller

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

Product data sheet

PCA9564

SOT360-1

2004 Jun 25 29


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm SOT662-1

2004 Jun 25 30


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

REVISION HISTORY

Rev Date

_3 20040625

_2

_1

20030402

20030226

Description

Product data sheet (9397 750 13272). Supersedes data of 2003 Apr 02 (9397 750 11353).

•

Add DIP20 package (features, ordering information, pinning, package outline).

•

Block diagram replaced with new drawing.

•

Functional description; Registers; The Control Register, I2CCON: (the last 2) sentences added to paragraph.

Product data (9397 750 11353). ECN 853-2419 29715 Dated 24 March 2003.

Supersedes Objective data of 2003 Feb 26 (9397 750 11153).

Objective data (9397 750 11153).

2004 Jun 25 31


Parallel bus to I

2

C-bus controller

Product data sheet

PCA9564

Purchase of Philips I

2

C components conveys a license under the Philips’ I

2

C patent to use the components in the I

2

C system provided the system conforms to the

I

2

C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.

Data sheet status

I

Level Data sheet status

[1]

Objective data sheet

Product status

[2] [3]

Development

Definitions

II Preliminary data sheet Qualification

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.

III Product data sheet Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825



Koninklijke Philips Electronics N.V. 2004

All rights reserved. Printed in U.S.A.

Date of release: 06-04

For sales offices addresses send e-mail to:

[email protected].

Document order number: 9397 750 13272

Philips

Semiconductors

2004 Jun 25 32

PCA9564 Parallel bus to I C-bus controller 2

INTEGRATED CIRCUITS

Parallel bus to I

C-bus controller

Philips

Semiconductors

Parallel bus to I

2

C-bus controller

PCA9564

Philips

Semiconductors

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