DS1302 Trickle-Charge Timekeeping Chip www.maxim-ic.com FEATURES § § § § § § TOP VIEW TEMP RANGE PIN-PACKAGE 8 VCC1 X1 2 7 SCLK X2 3 6 I/O GND 4 5 CE DS1302 1 DIP (300 mils) VCC2 1 X1 2 X2 3 GND 4 8 VCC1 7 SCLK 6 I/O 5 CE SO (200 mils/150 mils) ORDERING INFORMATION PART VCC2 DS1302S/Z § § § § § Real-Time Clock Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 31 x 8 RAM for Scratchpad Data Storage Serial I/O for Minimum Pin Count 2.0V to 5.5V Full Operation Uses Less than 300nA at 2.0V Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock or RAM Data 8-Pin DIP or Optional 8-Pin SO for Surface Mount Simple 3-Wire Interface TTL-Compatible (VCC = 5V) Optional Industrial Temperature Range: -40°C to +85°C DS1202 Compatible Underwriters Laboratory (UL) Recognized TOP MARK VCC2 1 8 VCC1 N.C 2 7 N.C. 6 SCLK X1 3 N.C. 4 DS1302S § PIN CONFIGURATIONS 5 N.C. 8 I/O 0°C to +70°C 8 PDIP DS1302 X2 1 DS1302N -40°C to +85°C 8 PDIP DS1302* N.C. 2 7 N.C. DS1302S 0°C to +70°C 8 SO (200 mils) DS1302S 3 6 N.C. 8 SO DS1302S* N.C. GND 4 5 CE 8 SO (150 mils) DS1302Z DS1302 DS1302SN DS1302Z -40°C to +85°C 0°C to +70°C SO (300 mils) DS1302Z+ 0°C to +70°C 8 SO (150 mils) + DS1302Z DS1302ZN -40°C to +85°C 8 SO DS1302ZN DS1302ZN+ -40°C to +85°C 8 SO + DS1302ZN DS1302S-16 0°C to +70°C 16 SO (300 mils) DS1302S16 -40°C to +85°C 16 SO (300 mils) DS1302SN16 DS1302SN-16 *An N in the lower right-hand corner of the top mark denotes an industrial part. + = lead-free device. DETAILED DESCRIPTION The DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar and 31 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 13 REV: 072204 DS1302 Trickle-Charge Timekeeping Chip Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1mW. The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for VCC1, and seven additional bytes of scratchpad memory. OPERATION Figure 1 shows the main elements of the serial timekeeper: shift register, control logic, oscillator, real-time clock, and RAM. TYPICAL OPERATING CIRCUIT VCC X1 X2 CE CPU I/O DS1302 SCLK VCC2 VCC VCC1 GND Figure 1. Block Diagram X1 vCC1 vCC 2 GND POWER CONTROL DS1302 X2 OSCILLATOR AND COUNTDOWN CHAIN I/O 1Hz INPUT SHIFT REGISTERS COMMAND AND CONTROL LOGIC REAL-TIME CLOCK 31 x 8 RAM SCLK CE 2 of 13 DS1302 Trickle-Charge Timekeeping Chip TYPICAL OPERATING CHARACTERISTICS (VCC = 3.3V, TA = +25°C, unless otherwise noted.) ICC1T vs. VCC1T ICC2T vs. VCC2T 30 400 25 SUPPLY CURRENT (uA) SUPPLY CURRENT (nA) 350 300 250 200 20 15 10 150 100 5 2.0 3.0 VCC1 (V) 4.0 2.0 5.0 3.0 VCC2 (V) 4.0 5.0 PIN DESCRIPTION PIN 8 16 NAME FUNCTION Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302. 1 1 VCC2 2 3 X1 3 5 X2 4 8 GND 5 9 CE Input. CE signal must be asserted high during a read or a write. This pin has an internal 40kW (typ) pulldown resistor to ground. Note: Previous data sheet revisions referred to CE as RST. The functionality of the pin has not changed. 6 12 I/O Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire interface. This pin has an internal 40kW (typ) pulldown resistor to ground. 7 14 SCLK 8 16 VCC1 — 2, 4, 6, 7, 10, 11, 13, 15 N.C. Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The DS1302 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Ground Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40kW (typ) pulldown resistor to ground. Low-Power Operation in Single Supply and Battery-Operated Systems and LowPower Battery Backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. UL recognized to ensure against reverse charging current when used with a lithium battery. No Connection 3 of 13 DS1302 Trickle-Charge Timekeeping Chip OSCILLATOR CIRCUIT The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 2 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 3 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for detailed information. Table 1. Crystal Specifications* PARAMETER SYMBOL Nominal Frequency MIN fO TYP MAX 32.768 Series Resistance ESR Load Capacitance CL UNITS kHz 45 6 kW pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. Figure 2. Oscillator Circuit Showing Internal Bias Network RTC COUNTDOWN CHAIN CL1 CL2 RTC REGISTERS X2 X1 CRYSTAL Figure 3. Typical PC Board Layout for Crystal LOCAL GROUND PLANE (LAYER 2) X1 CRYSTAL X2 NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFTHAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE. GND 4 of 13 DS1302 Trickle-Charge Timekeeping Chip COMMAND BYTE Figure 4 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0). Figure 4. Address/Command Byte 7 1 6 RAM CK 5 4 3 2 1 A4 A3 A2 A1 A0 0 RD WR CE AND CLOCK CONTROL Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the control logic that allows access to the shift register for the address/command sequence. Second, the CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure 5 shows data transfer. At power-up, CE must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state. DATA INPUT Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. DATA OUTPUT Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tristated upon each rising edge of SCLK. Data is output starting with bit 0. BURST MODE Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not. CLOCK/CALENDAR The time and calendar information is obtained by reading the appropriate register bytes. Table 2 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. 5 of 13 DS1302 Trickle-Charge Timekeeping Chip The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers the rising edge of CE. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be re-initialized whenever the 12/24 bit is changed. CLOCK HALT FLAG Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When this bit is written to logic 0, the clock will start. The initial power-on state is not defined. WRITE-PROTECT BIT Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit should be cleared before attempting to write to the device. TRICKLE-CHARGE REGISTER This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 6 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between VCC2 and VCC1. If DS is 01, one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between VCC2 and VCC1. The resistor selected by the resistor select (RS) bits is as follows: RS BITS RESISTOR 00 01 10 11 None R1 R2 R3 TYPICAL VALUE None 2kW 4kW 8kW If RS is 00, the trickle charger is disabled independently of TCS. Diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum current IMAX would therefore be calculated as follows: IMAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2kW ≈ 2.2mA As the super cap charges, the voltage drop between VCC2 and VCC1 decreases and therefore the charge current decreases. 6 of 13 DS1302 Trickle-Charge Timekeeping Chip CLOCK/CALENDAR BURST MODE The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0. If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode. At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read. RAM The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space. RAM BURST MODE The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0. REGISTER SUMMARY A register data format summary is shown in Table 2. CRYSTAL SELECTION A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6pF. For more information on crystal selection and crystal layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. Figure 5. Data Transfer Summary SINGLE-BYTE READ CE SCLK I/O R/W A0 A1 A2 A3 A4 R/C 1 D1 D0 D2 D3 D4 D5 D6 D7 D3 D4 D5 D6 D7 SINGLE-BYTE WRITE CE SCLK I/O R/W A0 A1 A2 A3 A4 R/ C 1 D0 D1 D2 NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST. 7 of 13 DS1302 Trickle-Charge Timekeeping Chip Table 2. Register Address/Definition RTC READ WRITE BIT 7 81h 83h 80h 82h CH 85h 84h 12/24 87h 86h 0 89h 88h 0 8Bh 8Dh 8Fh 91h 8Ah 8Ch 8Eh 90h 0 WP TCS BIT 6 BIT 5 BIT 4 10 Seconds 10 Minutes 10 Hour 0 AM/PM 0 10 Date 10 0 0 Month 0 0 0 10 Year 0 0 0 TCS TCS TCS BIT 3 BIT 2 0 0 DS BIT 1 BIT 0 RANGE Seconds Minutes 00–59 00–59 Hour 1–12/0–23 Date 1–31 Month 1–12 Day Year 0 0 DS RS 1–7 00–99 — — 0 RS CLOCK BURST BFh BEh RAM C1h C3h C5h . . . FDh C0h C2h C4h . . . FCh 00-FFh 00-FFh 00-FFh . . . 00-FFh RAM BURST FFh FEh Figure 6. Programmable Trickle Charger TRICKLE CHARGE REGISTER (90h write, 91h read) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 TCS 0-3 = TRICKLE CHARGER SELECT DS 0-1 = DIODE SELECT ROUT 0-1 = RESISTOR SELECT 1 0F 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER 1 OF 2 SELECT 1 OF 3 SELECT R1 2K W V CC2 R2 4k W R3 8k W 8 of 13 V CC1 DS1302 Trickle-Charge Timekeeping Chip ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………………….-0.5Vto +7.0V Operating Temperature Range, Commercial………………………………………………………………….0°C to +70°C Operating Temperature Range, Industrial (IND)……………………………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………………………..….-55°C to +125°C Soldering Temperature (leads, 10 seconds)………………………………………………………………..………….260°C Soldering Temperature (surface mount)………………………………………………..…..See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER MIN TYP MAX UNITS NOTES VCC1, VCC2 2.0 3.3 5.5 V 2, 10 Logic 1 Input VIH 2.0 VCC + 0.3 V 2 Logic 0 Input VIL VCC = 2.0V -0.3 +0.3 VCC = 5V -0.3 +0.8 V 2 Supply Voltage VCC1, VCC2 SYMBOL DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage ILI 85 +500 mA 5, 13 I/O Leakage ILO 85 +500 mA 5, 13 V 2 V 2 mA 4, 11 mA 3, 11,13 nA 9, 11, 13 mA 4, 12 mA 3, 12 mA 9, 12 Logic 1 Output (IOH = -1mA) Logic 1 Output (IOH = -0.4mA) Logic 0 Output (IOL = 4mA) Logic 0 Output (IOL = 1.5mA) VOH VOL Active Supply Current ICC1A Timekeeping Current ICC1T Standby Current ICC1S Active Supply Current ICC2A Timekeeping Current ICC2T Standby Current ICC2S VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC1 = 2.0V VCC1 = 5V VCC1 = 2.0V VCC1 = 5V VCC1 = 2.0V VCC1 = 5V IND VCC2 = 2.0V VCC2 = 5V VCC2 = 2.0V VCC2 = 5V VCC2 = 2.0V VCC2 = 5V 1.6 2.4 0.2 0.45 1 1 5 0.4 0.4 0.4 1.2 0.3 1 100 100 200 0.425 1.28 25.3 81 25 80 Trickle-Charge Resistors R1 R2 R3 2 4 8 kW Trickle-Charge Diode Voltage Drop VTD 0.7 V 9 of 13 DS1302 Trickle-Charge Timekeeping Chip CAPACITANCE (TA = +25°C) PARAMETER SYMBOL Input Capacitance I/O Capacitance MIN TYP MAX UNITS CI 10 pF CI/O 15 pF AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL Data to CLK Setup tDC CLK to Data Hold tCDH CLK to Data Delay tCDD CLK Low Time tCL CLK High Time tCH CLK Frequency tCLK CLK Rise and Fall tR, tF CE to CLK Setup tCC CLK to CE Hold tCCH CE Inactive Time tCWH CE to I/O High Impedance tCDZ SCLK to I/O High Impedance tCCZ Note 1: Note 2: Note 3: Note 4: VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V MIN TYP MAX 200 50 280 70 800 200 1000 250 1000 250 DC 0.5 2.0 2000 500 4 1 240 60 4 1 280 70 280 70 UNITS NOTES ns 6 ns 6 ns 6, 7, 8 ns 6 ns 6 MHz 6 ns ms 6 ns 6 ms 6 ns 6 ns 6 Note 5: Note 6: Note 7: Note 8: Note 9: Limits at -40°C are guaranteed by design and are not production tested. All voltages are referenced to ground. ICC1T and ICC2T are specified with I/O open, CE and SCLK set to a logic “0”, and clock halt flag = 0 (oscillator enabled). ICC1A and ICC2A are specified with the I/O pin open, CE high, SCLK = 2MHz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V and clock halt flag = 0 (oscillator enabled). CE, SCLK, and I/O all have 40kW pulldown resistors to ground. Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time. Measured at VOH = 2.4V or VOL = 0.4V. Load capacitance = 50pF. ICC1S and ICC2S are specified with CE, I/O, and SCLK open. The clock halt flag must be set to logic 1 (oscillator disabled). Note 10: Note 11: Note 12: VCC = VCC2, when VCC2 > VCC1 + 0.2V; VCC = VCC1, when VCC1 > VCC2. VCC2 = 0V. VCC1 = 0V. Note 13: Typical values are at +25°C. 10 of 13 DS1302 Trickle-Charge Timekeeping Chip Figure 7. Timing Diagram: Read Data Transfer CE tCC tR tF SCLK t CL t CDH t CCZ t CH t CDZ t CDD t DC I/O 1 D0 R/W A0 W RITE COM M AND BYTE D7 READ DATA BYTE Figure 8. Timing Diagram: Write Data Transfer t CW H CE t CC tR tCCH tF SCLK t CDH I/O t CL tCH t DC 0 1 A0 D0 W RITE COM MAND BYTE W RITE DATA BYTE CHIP INFORMATION TRANSISTOR COUNT: 11,500 THERMAL INFORMATION PACKAGE 8 DIP 8 SO (150) 16 SO (300) THETA-JA (°C/W) 110 170 105 D7 THETA-JC (°C/W) 40 40 22 11 of 13 DS1302 Trickle-Charge Timekeeping Chip PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 12 of 13 8-PIN DIP MIN MAX 0.360 0.400 9.14 10.16 0.240 0.260 6.10 6.60 0.120 0.140 3.05 3.56 0.300 0.325 7.62 8.26 0.015 0.040 0.38 1.02 0.120 0.140 3.04 3.56 0.090 0.110 2.29 2.79 0.320 0.370 8.13 9.40 0.008 0.012 0.20 0.30 0.015 0.021 0.38 0.53 DS1302 Trickle-Charge Timekeeping Chip PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PKG DIM A IN. MM B IN. MM C IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM L IN. MM PHI 8-PIN SO 8-PIN SO (150 MILS) (200 MILS) MIN MAX MIN MAX 0.188 0.196 0.203 0.213 4.78 4.98 5.16 5.41 0.150 0.158 0.203 0.213 3.81 4.01 5.16 5.41 0.048 0.062 0.070 0.074 1.22 1.57 1.78 1.88 0.004 0.010 0.004 0.010 0.10 0.25 0.10 0.25 0.053 0.069 0.074 0.084 1.35 1.75 1.88 2.13 0.050 BSC 1.27 BSC 0.230 0.244 0.302 0.318 5.84 6.20 7.67 8.08 0.007 0.011 0.006 0.010 0.18 0.28 0.15 0.25 0.012 0.020 0.013 0.020 0.30 0.51 0.33 0.51 0.016 0.050 0.019 0.030 0.41 1.27 0.48 0.76 0° 8° 0° 8° 56-G2008-001 56-G4010-001 PKG DIM A IN. MM B IN. MM C IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM L IN. MM PHI 16-PIN SO (300 MILS) MIN MAX 0.398 0.412 10.11 10.46 0.290 0.300 7.37 7.62 0.089 0.095 2.26 2.41 0.004 0.012 0.102 0.30 0.004 0.015 2.39 2.67 0.050 BSC 1.27 BSC 0.398 0.416 10.11 10.57 0.009 0.013 0.229 0.33 0.013 0.020 0.33 0.51 0.016 0.040 0.40 1.02 0° 8° 56-G4009-001 13 of 13 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products · Printed USA are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation.
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