RF5110G 3V GSM POWER AMPLIFIER Features

RF5110G 3V GSM POWER AMPLIFIER Features
RF5110G
3V GSM POWER AMPLIFIER
„
57% Efficiency
„
800MHz to 950MHz Operation
„
Supports GSM and E-GSM
„
„
„
„
„
GPRS Compatible
Commercial and Consumer Systems
Portable Battery-Powered Equipment
FM Radio Applications:
150MHz/220MHz/
450MHz/865MHz/915MHz
VCC
NC
1
12
RF OUT
GND1
2
11
RF OUT
RF IN
3
10
RF OUT
GND2
4
9
RF OUT
3V GSM Cellular Handsets
3V Dual-Band/Triple-Band Handsets
13
VCC1
Applications
„
14
5
6
7
8
2f0
32dB Gain with Analog Gain Control
15
NC
„
+36dBm Output Power at 3.5V
16
VCC2
„
Single 2.7V to 4.8V Supply Voltage
VCC2
„
APC2
Features
APC1
RoHS & Pb-Free Product
Package Style: QFN, 16-Pin, 3 x 3
Functional Block Diagram
Product Description
The RF5110G is a high-power, high-efficiency power amplifier module offering high
performance in GSM OR GPRS applications. The device is manufactured on an
advanced GaAs HBT process, and has been designed for use as the final RF amplifier in GSM hand-held digital cellular equipment and other applications in the
800MHz to 950MHz band. On-board power control provides over 70dB of control
range with an analog voltage input, and provides power down with a logic “low” for
standby operation. The device is self-contained with 50Ω input and the output can
be easily matched to obtain optimum power and efficiency characteristics. The
RF5110G can be used together with the RF5111 for dual-band operation. The
device is packaged in an ultra-small 3mmx3mmx1mm plastic package, minimizing the required board space.
Ordering Information
RF5110G
3V GSM Power Amplifier
RF5110GPCBA-410 Fully Assembled Evaluation Board
9GaAs HBT
GaAs MESFET
InGaP HBT
Optimum Technology Matching® Applied
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.
Rev A4 DS071026
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1 of 22
RF5110G
Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage
-0.5 to +6.0
VDC
Power Control Voltage (VAPC1,2)
-0.5 to +3.0
V
DC Supply Current
2400
mA
Input RF Power
+13
dBm
Duty Cycle at Max Power
50
%
Output Load VSWR
10:1
Operating Case Temperature
-40 to +85
°C
Storage Temperature
-55 to +150
°C
Parameter
Min.
Specification
Typ.
Max.
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied.
RoHS status based on EUDirective2002/95/EC (at time of this document revision).
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.
Unit
Condition
Temp=25°C, VCC =3.6V, VAPC1,2 =2.8V,
PIN =+4.5dBm, Freq=880MHz to 915MHz,
37.5% Duty Cycle, pulse width=1731μs
Overall
Operating Frequency Range
880 to 915
MHz
See evaluation board schematic.
Usable Frequency Range
800 to 950
MHz
Using different evaluation board tune.
Maximum Output Power
33.8
34.5
33.1
Total Efficiency
50
+4.5
57
%
At POUT,MAX, VCC =3.6V
%
POUT =+20dBm
%
POUT =+10dBm
+7.0
Output Noise Power
Forward Isolation
Second Harmonic
-20
Third Harmonic
-25
All Other Non-Harmonic
Spurious
Input Impedance
+9.5
dBm
-72
dBm
RBW=100kHz, 925MHz to 935MHz,
POUT,MIN <POUT <POUT,MAX,
PIN,MIN <PIN <PIN,MAX, VCC =3.3V to 5.0V
-81
dBm
RBW=100kHz, 935MHz to 960MHz,
POUT,MIN <POUT <POUT,MAX,
PIN,MIN <PIN <PIN,MAX, VCC =3.3V to 5.0V
-22
dBm
VAPC1,2 =0.3V, PIN =+9.5dBm
-7
dBm
PIN =+9.5dBm
-7
dBm
PIN =+9.5dBm
-36
dBm
Ω
50
Optimum Source Impedance
Temp=25°C, VCC =3.6V, VAPC1,2 =2.8V
Temp=+60°C, VCC =3.3V, VAPC1,2 =2.8V
12
5
Input Power for Max Output
dBm
dBm
Ω
40+j10
Input VSWR
2.5:1
For best noise performance
POUT,MAX-5dB<POUT <POUT,MAX
4:1
POUT <POUT,MAX-5dB
Output Load VSWR
Stability
8:1
Ruggedness
10:1
Output Load Impedance
2 of 22
Spurious<-36dBm, VAPC1,2 =0.3V to 2.6V,
RBW=100kHz
No damage
2.6-j1.5
Ω
Load Impedance presented at RF OUT pad
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support, contact RFMD at (+1) 336-678-5570 or [email protected]
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Rev A4 DS071026
RF5110G
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
Power Control VAPC1 VAPC2
Power Control “ON”
2.6
Power Control “OFF”
0.2
Power Control Range
75
Gain Control Slope
5
0.5
Maximum POUT, Voltage supplied to the input
Minimum POUT, Voltage supplied to the input
dB
100
APC Input Capacitance
APC Input Current
V
V
4.5
Turn On/Off Time
150
dB/V
VAPC1,2 =0.2V to 2.6V
POUT =-10dBm to +35dBm
10
pF
DC to 2MHz
5
mA
VAPC1,2 =2.8V
25
μA
VAPC1,2 =0V
100
ns
VAPC1,2 =0 to 2.8V
V
Specifications
4.8
V
Nominal operating limits, POUT <+35dBm
5.5
V
With maximum output load VSWR 6:1,
POUT <+35dBm
A
DC Current at POUT,MAX
Power Supply
Power Supply Voltage
3.5
2.7
Power Supply Current
2
15
Rev A4 DS071026
200
335
mA
Idle Current, PIN <-30dBm
1
10
μA
PIN <-30dBm, VAPC1,2 =0.2V
1
10
μA
PIN <-30dBm, VAPC1,2 =0.2V, Temp=+85°C
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RF5110G
Pin
1
Function
VCC1
2
GND1
3
RF IN
Description
Interface Schematic
Power supply for the pre-amplifier stage and interstage matching. This pin
forms the shunt inductance needed for proper tuning of the interstage
match. Refer to the application schematic for proper configuration. Note
that position and value of the components are important.
Ground connection for the pre-amplifier stage. Keep traces physically short
and connect immediately to the ground plane for best performance. It is
important for stability that this pin has it’s own vias to the groundplane, to
minimize any common inductance.
RF Input. This is a 50Ω input, but the actual impedance depends on the
interstage matching network connected to pin 1. An external DC blocking
capacitor is required if this port is connected to a DC path to ground or a
DC voltage.
See pin 3.
See pin 1.
VCC1
RF IN
From Bias
GND1
Stages
4
GND2
5
VCC2
Ground connection for the driver stage. To minimize the noise power at the
output, it is recommended to connect this pin with a trace of about 40mil
to the ground plane. This will slightly reduce the small signal gain, and
lower the noise power. It is important for stability that this pin have it’s own
vias to the ground plane, minimizing common inductance.
Power supply for the driver stage and interstage matching. This pin forms
the shunt inductance needed for proper tuning of the interstage match.
Please refer to the application schematic for proper configuration, and
note that position and value of the components are important.
See pin 3.
VCC2
From Bias
GND2
Stages
6
7
8
VCC2
NC
2F0
9
RF OUT
Same as pin 5.
Not connected.
Connection for the second harmonic trap. This pin is internally connected
to the RF OUT pins. The bonding wire together with an external capacitor
form a series resonator that should be tuned to the second harmonic frequency in order to increase efficiency and reduce spurious outputs.
RF Output and power supply for the output stage. Bias voltage for the final
stage is provided through this wide output pin. An external matching network is required to provide the optimum load impedance.
Same as pin 9.
RF OUT
From Bias
GND
Stages
PCKG BASE
10
11
12
13
14
15
16
RF OUT
RF OUT
RF OUT
NC
VCC
APC2
APC1
Same as pin 9.
Same as pin 9.
Same as pin 9.
Same as pin 9.
Same as pin 9.
Not connected.
Power supply for the bias circuits.
Power Control for the output stage. See pin 16 for more details.
See pin 16.
Power Control for the driver stage and pre-amplifier. When this pin is "low,"
all circuits are shut off. A "low" is typically 0.5V or less at room temperature. A shunt bypass capacitor is required. During normal operation this pin
is the power control. Control range varies from about 1.0V for -10dBm to
2.6V for +35dBm RF output power. The maximum power that can be
achieved depends on the actual output matching; see the application information for more details. The maximum current into this pin is 5mA when
VAPC1 =2.6V, and 0mA when VAPC =0V.
APC
VCC
To RF
S ta g e s
GND
GND
Pkg
Base
4 of 22
GND
Ground connection for the output stage. This pad should be connected to
the ground plane by vias directly under the device. A short path is required
to obtain optimum performance, as well as to provide a good thermal path
to the PCB for maximum heat dissipation.
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support, contact RFMD at (+1) 336-678-5570 or [email protected]
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Rev A4 DS071026
RF5110G
Package Drawing
-A-
0.15 C A
2 PLCS
3.00 SQ.
0.05 C
1.00
0.85
1.50 TYP
0.05
0.01
0.80
0.65
2 PLCS
0.15 C B
12°
MAX
2 PLCS
0.15 C B
-B-C-
1.37 TYP
2 PLCS
0.15 C A
Dimensions in mm.
2.75 SQ.
Shaded lead is pin 1.
0.10 M C A B
0.60
0.24
TYP
0.30
0.18
0.45
0.00
4 PLCS
1.65
SQ.
1.35
0.23
0.13
4 PLCS
0.50
Rev A4 DS071026
SEATING
PLANE
0.55
0.30
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RF5110G
Theory of Operation
General Purpose Radio Applications
RF5110G has seen widespread use in GSM handset applications, but it can also be used as a final transmit PA for general purpose radio (FSK, ASK). The application schematics in this data sheet outline matching for commonly used frequency bands.
Matching is shown for 150MHz, 220MHz, 450MHz, and 865MHz to 928MHz. The standard 900MHz GSM evaluation board
can be easily converted for these bands, using the values indicated. The 865MHZ to 928MHz conversion is the most direct,
with adjustment required only on output match. The others show changes at input, 1st interstage, 2nd interstage, and output.
Common components can be used in most cases. The only key component is the choke seen on RF output. During development of the matches, one goal was to achieve stability (no spurious) into 5:1 output VSWR. The 1μH value and construction
proved essential in achieving this level of stability.
This Theory of Operation applies to an open loop system utilizing no power control. In the traditional GSM application, power is
sampled at the RF5110G’s output and fed back to a log detect function. DAC voltage (VSET) is also input to the log detector. Log
detector output drives the VAPC pin of RF5110G such that output power corresponding to VSET is obtained, with constant input
power>0dBm applied. Power can be set over the full range of defined levels, ranging from small signal to compression. In
addition, the control loop is used for ramping in accordance with GSM specifications. If power control is used in the system
under consideration, most of the open loop constraints covered here will not apply, aside from thermal considerations discussed below.
When used in an open loop system, RF5110G should be operated in compression. When running small signal, some variation
in gain (and therefore output power) will be seen over temperature extremes between -40°C and 85°C. When operated in compression, the impact of this variation is substantially mitigated, making open loop application practical. “Compression” in this
case is defined where efficiency exceeds 45%. In the graph section of this data sheet, curves in each frequency band are
shown for gain/efficiency/junction temperature versus POUT/VCC. As indicated in the graphs, high efficiency can be obtained at
compressed output power with appropriate choice of supply voltage (VCC). For example, see the efficiency curves for 450MHz.
Operation at 31dBm shows efficiency=49% for VCC =2.8V. If 32dBm output is required in design, using VCC =3.3V gives 47%
efficiency. So, the system designer can choose an appropriate supply voltage which provides high efficiency at target POUT.
One important detail to consider is voltage level at VAPC. As noted earlier, VAPC level varies when operating within a power control loop. This voltage controls output power from the PA. In open loop mode, VAPC should be set at 2.8V to ensure consistent
output power from RF5110G in volume production.
Another design consideration is maintaining acceptable junction temperature. In the GSM radio, output power in excess of
34dBm is common. This is allowable due to the limit on transmit duty cycle and pulse width. The worst case condition sees
duty cycle at 50%, with pulse width equal to approximately 2msec. In this situation, the PA cuts off before junction temperature
reaches the maximum that would be seen with longer pulse width. For the non–GSM radio, it is assumed pulse width will
exceed 2msec. Thus, restrictions must be imposed on allowable maximum output power. The most conservative analysis is
used, that for 100% duty cycle. Thermal scans have shown RTH (thermal resistance) of RF5110G+the evaluation board to be
36°C/W. RTH for the evaluation board has been calculated at 10.4°C/W, giving RF5110G RTH_JC =25.6°C/W. Data sheet
curves show projected junction temperatures (TJ) for each general purpose radio frequency band. RTH of RF5110G+the evaluation board is taken into account. A conservative goal is TJ ≤150°C when operating at a maximum specified ambient temperature of 85°C. Maximum output power will then be bounded by that limit. Observing the TJ curves in bands from 150MHz to
928MHz, one sees that 32dBm is always at or below 150°C. This shows that the output load line in each match was intentionally set for high efficiency. To ensure equivalent performance in one’s system, care should be taken to achieve efficiency equal
to or better than that seen in the data. Thermal performance can be predicted with a simple calculation at a desired output
power:
P_DC=VCC xICC
POUT (Watt)=[10^(POUT (dBm)/10)]/1000
6 of 22
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Rev A4 DS071026
RF5110G
Dissipated Power=PDISS =P_DC–POUT
RTH =RTH_JC_RF5110G +RTH_SYSTEM_BOARD (RTH_JC_RF5110G =25.6°C/W)
Junction Temperature @ 85°C ambient=TJ =85°C+PDISS xRTH
Efficiency calculation alone may not suffice, as the system board may be substantially thicker than that of the RF5110G evaluation board. This will increase RTH for the system, and likewise TJ.
Layout considerations are important in repeating RF5110G evaluation board performance in a system design. Via arrangement underneath the part is critical, as are other via arrangements and supply trace routings (see “GSM Applications” section
for the GSM case). Layout files for the RF5110G evaluation board can be obtained by contacting RFMD applications/sales.
As already stated, output match is a primary consideration in achieving desired performance. In moving from the RF5110G
evaluation board to the system board, the first approach would be to implement the same matching topology/values as seen in
application schematics. Performance on the system board can then be checked, particularly with regard to gain and efficiency
at target output power. If needed, matching values can be adjusted to obtain equivalent performance. Observing each output
match from 150MHz to 900MHz, it can be seen that topology takes 1 of 2 possible configurations:
C – L – C: 150MHz, 220MHz, 900MHz
L – C: 450MHz
Other areas which impact response are the 1st and 2nd interstage matches, found at pins 1 and 5/6, respectively. Small signal responses for each match are shown in this data sheet. Checking response on the system board will verify that input/interstage matches are in line (output to some extent as well). This verification can be done by placing SMA connectors at the
input/output of RF5110G, and observing small signal response.
Following the guidelines contained within this section should ensure successful implementation of RF5110G in general radio
applications.
GSM Applications
The RF5110G is a three-stage device with 32 dB gain at full power. Therefore, the drive required to fully saturate the output is
+3dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part requires only a single positive 3V supply to
operate to full specification. Power control is provided through a single pin interface, with a separate Power Down control pin.
The final stage ground is achieved through the large pad in the middle of the backside of the package. First and second stage
grounds are brought out through separate ground pins for isolation from the output. These grounds should be connected
directly with vias to the PCB ground plane, and not connected with the output ground to form a so called “local ground plane”
on the top layer of the PCB. The output is brought out through the wide output pad, and forms the RF output signal path.
The amplifier operates in near Class C bias mode. The final stage is “deep AB”, meaning the quiescent current is very low. As
the RF drive is increased, the final stage self-biases, causing the bias point to shift up and, at full power, draws about 2000mA.
The optimum load for the output stage is approximately 2.6Ω. This is the load at the output collector, and is created by the
series inductance formed by the output bond wires, vias, and microstrip, and 2 shunt capacitors external to the part. The optimum load impedance at the RF Output pad is 2.6-j1.5Ω. With this match, a 50Ω terminal impedance is achieved. The input is
internally matched to 50Ω with just a blocking capacitor needed. This data sheet defines the configuration for GSM operation.
The input is DC coupled; thus, a blocking cap must be inserted in series. Also, the first stage bias may be adjusted by a resistive divider with high value resistors on this pin to VPC and ground. For nominal operation, however, no external adjustment is
necessary as internal resistors set the bias point optimally.
VCC1 and VCC2 provide supply voltage to the first and second stage, as well as provides some frequency selectivity to tune to
the operating band. Essentially, the bias is fed to this pin through a short microstrip. A bypass capacitor sets the inductance
seen by the part, so placement of the bypass cap can affect the frequency of the gain peak. This supply should be bypassed
individually with 100pF capacitors before being combined with VCC for the output stage to prevent feedback and oscillations.
Rev A4 DS071026
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RF5110G
The RF OUT pin provides the output power. Bias for the final stage is fed to this output line, and the feed must be capable of
supporting the approximately 2A of current required. Care should be taken to keep the losses low in the bias feed and output
components. A narrow microstrip line is recommended because DC losses in a bias choke will degrade efficiency and power.
While the part is safe under CW operation, maximum power and reliability will be achieved under pulsed conditions. The data
shown in this data sheet is based on a 12.5% duty cycle and a 600μs pulse, unless specified otherwise.
The part will operate over a 3.0V to 5.0V range. Under nominal conditions, the power at 3.5V will be greater than +34.5dBm at
+90°C. As the voltage is increased, however, the output power will increase. Thus, in a system design, the ALC (Automatic
Level Control) Loop will back down the power to the desired level. This must occur during operation, or the device may be damaged from too much power dissipation. At 5.0V, over +38dBm may be produced; however, this level of power is not recommended, and can cause damage to the device.
The HBT breakdown voltage is >20V, so there are no issue with overvoltage. However, under worst-case conditions, with the RF
drive at full power during transmit, and the output VSWR extremely high, a low load impedance at the collector of the output
transistors can cause currents much higher than normal. Due to the bipolar nature of the devices, there is no limitation on the
amount of current de device will sink, and the safe current densities could be exceeded.
High current conditions are potentially dangerous to any RF device. High currents lead to high channel temperatures and may
force early failures. The RF5110G includes temperature compensation circuits in the bias network to stabilize the RF transistors, thus limiting the current through the amplifier and protecting the devices from damage. The same mechanism works to
compensate the currents due to ambient temperature variations.
To avoid excessively high currents it is important to control the VAPC when operating at supply voltages higher than 4.0V, such
that the maximum output power is not exceeded.
8 of 22
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Rev A4 DS071026
RF5110G
Internal Schematic
VCC1
5Ω
VCC2
RF OUT
4.5 pF
APC1
VCC
APC2
VCC
RF IN
5Ω
400 Ω
300 Ω
1.0 kΩ
APC1
PKG BASE
Rev A4 DS071026
GND2
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support, contact RFMD at (+1) 336-678-5570 or [email protected]
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PKG BASE
9 of 22
RF5110G
Application Schematic
150MHz FM Band
VAPC
VCC
VCC
+
VAPC
10 nF
VCC1
10 nF
1 nF
27 pF
10 nF
47 pF
3.3 μF
8.2 nH
16
100 pF
15
14
13
1 nF
1
12
2
11
3
10
50 mils
9
C10
33 pF
1 μH 1
Taiyo Yuden
NR3012T1R0N
RF IN
180 Ω
4
5
+
3.3 μF
10 nF
7
RF OUT
L4
15 nH
C11 2
56 pF
8
33 nH
0Ω
VCC2
6
100 pF
1 nF
27 pF
1 Requires
2 C11
layout change to standard evaluation board.
adjacent to L4.
Application Schematic
220MHz FM Band
VAPC
VCC
VCC
+
VAPC
10 nF
VCC1
10 nF
1 nF
27 pF
10 nF
47 pF
8.2 nH
16
15
14
13
1 nF
1
12
2
11
3
10
100 pF
RF IN
180 Ω
4
9
5
0Ω
3.3 μF
6
7
1 μH1
Taiyo Yuden
NR3012T1R0N
10 nH
100 pF
RF OUT
C102
33 pF
C113
39 pF
8
33 nH
VCC2
+
3.3 μF
10 nF
1 nF
27 pF
1Requires
layout change to standard evaluation board.
is adjacent to L4.
3C11 is 140 mils from L4.
2C10
10 of 22
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Rev A4 DS071026
RF5110G
Application Schematic
450MHz FM Band
VAPC
VCC
VCC
+
VAPC
10 nF
VCC1
10 nF
1 nF
330 pF
10 nF
47 pF
3.3 μF
18 Ω
16
15
14
13
1 nF
1
12
2
11
3
10
56 pF
RF IN
180 Ω
4
9
5
6
7
47 pF
1 μH1
Taiyo Yuden
NR3012T1R0N
L4
2.7 nH
56 pF
RF OUT
C11
22 pF
2 pF
8
C11 adjacent
to L4.
0Ω
VCC2
+
3.3 μF
1Requires
Rev A4 DS071026
10 nF
1 nF
6.8 nH
330 pF
layout change to standard evaluation board.
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11 of 22
RF5110G
Application Schematic
865MHz and 902MHz to 928MHz ISM Bands
VAPC
VCC
VCC
+
VAPC
10 nF
VCC1
10 nF
1 nF
27 pF
10 nF
47 pF
11 nH
16
15
14
13
1 nF
1
12
2
11
3
10
56 pF
RF IN
180 Ω
4
9
5
10 Ω ?
F errite
6
1.6 nH
3.3 μF
10 nF
1 nF
15 pF
7
8.8 nH
47 pF
27 pF
L4
3.6 nH
56 pF
RF OUT
55 mils
C10
15 pF
C11
5 pF
8
1.5 pF
VCC2
+
3.3 μF
C10 and C11 are
adjacent to L4.
27 pF
Share the same pad.
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Rev A4 DS071026
RF5110G
Evaluation Board Schematic
GSM850 Lumped Element
J3
VAPC
VCC
50 Ω μstrip
VCC
P1
VAPC
1
VCC
1
VAPC
P1-2
2
VCC
2
GND
3
GND
3
GND
4
GND
CON3
+
C18
3.3 μF
VCC1
C2
10 nF
J1
RF IN
C3
1 nF
C19
27 pF
L1
11 nH
C17
10 nF
16
C1
56 pF
50 Ω μstrip
C16
10 nF
R1
180 Ω
2
11
3
10
4
9
C5
10 nF
Rev A4 DS071026
C6
1 nF
7
CON4
C13
1 nF
C14
33 pF
L3
8.8 nH
L4
1.8 nH
60 mils
C9
15 pF
65 mils
C10
2 pF
C12
56 pF
40 mils
50 Ω μstrip
J2
RF OUT
C11
9.1 pF
8
C9 and C10 share
the same pad.
L6
1.6 nH
C20
13 pF
6
P2-1
13
12
C8
1.5 pF
VCC2
+ C21
3.3 μF
14
1
5
L2
10 Ω Ferrite
15
C15
33 pF
P2
P1-1
C7
33 pF
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13 of 22
RF5110G
Evaluation Board Schematic
GSM900 Lumped Element
J3
VAPC
VCC
50 Ω μstrip
VCC
P1
VAPC
1
VCC
1
VAPC
P1-2
2
VCC
2
GND
3
GND
3
GND
GND
CON3
C18
3.3 μF
4
+
C17
10 nF
VCC1
C2
10 nF
J1
RF IN
C3
1 nF
C19
27 pF
L1
11 nH
16
C1
56 pF
50 Ω μstrip
C16
10 nF
R1
180 Ω
15
C5
10 nF
C6
1 nF
C14
47 pF
2
11
L3
8.8 nH
3
10
55 mils
4
9
7
C9
15 pF
L4
3.6 nH
C12
56 pF
50 Ω μstrip
39 mils
C10
11 pF
J2
RF OUT
C11*
5.6 pF
8
C9 and C10 share
the same pad.
L6
1.6 nH
*C11 is
adjacent to L4.
C8
1.5 pF
VCC2
+ C21
3.3 μF
13
12
6
P2-1
CON4
C13
1 nF
1
5
L2
10 Ω Ferrite
14
C15
47 pF
P2
P1-1
C20
15 pF
C23
27 pF
C7
27 pF
C23 and C27 share
the same pad.
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Rev A4 DS071026
RF5110G
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.032”; Board Material FR-4; Multi-Layer
Rev A4 DS071026
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15 of 22
RF5110G
Typical Test Setup
Power Supply
V- V+ S+ S-
RF Generator
Spectrum
Analyzer
3dB
10dB/5W
Buffer
x1 OpAmp
Pulse
Generator
A buffer amplifier is recommended because the current into the VAPC
changes with voltage. As an alternative, the voltage may be
monitored with an oscilloscope.
Notes about testing the RF5110G
The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effect on the signal generator as a result of switching the input impedance of the PA. When VAPC is switched quickly, the resulting input impedance
change can cause the signal generator to vary its output signal, either in output level or in frequency. Instead of an attenuator
an isolator may also be used. The attenuator at the output is to prevent damage to the spectrum analyzer, and should be sized
accordingly to handle the power.
It is important not to exceed the rated supply current and output power. When testing the device at higher than nominal supply
voltage, the VAPC should be adjusted to avoid the output power exceeding +36dBm. During load-pull testing at the output it is
important to monitor the forward power through a directional coupler. The forward power should not exceed +36dBm, and
VAPC needs to be adjusted accordingly. This simulates the behavior for the power control loop. To avoid damage, it is recommended to set the power supply to limit the current during the burst not to exceed the maximum current rating.
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Rev A4 DS071026
RF5110G
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is 3μinch
to 8μinch gold over 180μinch nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested
for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ.
B = 0.28 x 0.64 (mm) Typ.
C = 1.50 (mm) Sq.
Dimensions in
mm.
1.50 Typ.
0.50 Typ.
Pin 16
B
B
B
B
Pin 1
Pin 12
A
A
A
A
0.50 Typ.
C
A
A
A
A
0.75 Typ.
1.50
Typ.
0.55 Typ.
B
B
B
B
Pin 8
0.55 Typ.
0.75 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
Rev A4 DS071026
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17 of 22
RF5110G
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB
metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The
center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be
provided in the master data or requested from the PCB fabrication supplier.
A = 0.74 x 0.38 (mm) Typ.
B = 0.38 x 0.74 (mm) Typ.
C = 1.60 (mm) Sq.
Dimensions in
mm.
1.50
Typ.
0.50
Typ.
Pin 16
B
B
B
B
Pin 1
0.50
Typ.
Pin 12
A
A
A
A
C
0.55
Typ.
A
A
A
A
B
0.55
Typ.
B
B
0.75
Typ.
1.50
Typ.
B
Pin 8
0.75
Typ.
Figure 2. PCB Solder Mask Pattern (Top View)
Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device.
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing
strategies.
The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a
0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the
quantity of vias be increased by a 4:1 ratio to achieve similar results.
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Rev A4 DS071026
RF5110G
RF5110G 153 MHz Junction Temperature Versus POUT/VCC
Ambient Temperature = 85°C
40
80
142
38
75
140
36
70
34
65
32
60
30
55
28
50
26
45
24
40
153 MHz
153 MHz
153 MHz
153 MHz
153 MHz
153 MHz
22
20
27.5
28.0
28.5
29.0
29.5
30.0
30.5
31.0
gain 3.6 V
gain 3.3 V
gain 3.0 V
eff 3.6 V
eff 3.3 V
eff 3.0 V
31.5
32.0
Junction Temperature (°C)
138
Efficiency (%)
Gain (dB)
RF5110G 153 MHz Gain and Efficiency Versus POUT/VCC
136
134
132
130
128
126
153 MHz 3.6 V
124
35
122
30
120
32.5
153 MHz 3.3 V
153 MHz 3.0 V
27.5
28.0
28.5
29.0
POUT (dBm)
30.0
30.5
31.0
31.5
32.0
RF5110G 220 MHz Junction Temperature Versus POUT/VCC
Ambient Temperature = 85°C
60
160
47
55
155
45
50
150
43
45
145
41
40
140
39
35
37
30
35
25
33
20
120
31
15
115
10
110
2.8 V
3.3 V
5
105
3.6 V
0
100
2.8 V gain
3.3 V gain
3.6 V gain
2.8 V eff
3.3 V eff
3.6 V eff
29
27
25
27
28
29
30
31
POUT (dB)
Rev A4 DS071026
32
33
34
35
135
TJ (°C)
Efficiency (%)
49
26
130
125
26
27
28
29
30
31
32
33
34
35
POUT (dBm)
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32.5
POUT (dBm)
RF5110G 220 MHz Gain and Efficiency Versus POUT/VCC
Gain (dB)
29.5
19 of 22
RF5110G
RF5110G 450 MHz Junction Temperature Versus POUT/VCC
Ambient Temperature = 85°C
RF5110G 450 MHz Gain and Efficiency Versus POUT/VCC
48
60
46
55
158
156
154
50
44
152
45
150
40
148
35
38
30
36
25
2.8 V gain
3.3 V gain
2.8 V eff
3.3 V eff
34
146
TJ (°C)
40
Efficiency (%)
Gain (dB)
42
144
142
140
138
20
136
15
32
134
10
2.8 V
3.3 V
132
30
28
26
27
28
29
30
31
32
33
34
5
130
0
128
35
26
27
28
29
POUT (dBm)
55
865 MHz gain 2.8V
865 MHz gain 3.3V
928 MHz gain 3.3V
50
865 MHz gain 3.6V
38
928 MHz gain 3.6V
865 MHz eff 2.8V
37
45
928 MHz eff 2.8V
865 MHz eff 3.3V
928 MHz eff 3.3V
928 MHz eff 3.6V
Gain (dB)
35
34
33
30
32
25
31
30
20
29
15
28
27
10
27
28
29
30
31
PIN (dBm)
20 of 22
32
33
34
TJ (°C)
40
865 MHz eff 3.6V
35
Efficiency (%)
36
33
144
142
140
138
34
35
2.8V 865 MHz
2.8V 928 MHz
136
134
132
130
3.3V 865 MHz
3.3V 928 MHz
3.6V 865 MHz
3.6V 928 MHz
128
126
124
122
120
27
28
29
30
31
32
33
34
PIN (dBm)
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32
160
158
156
154
152
150
148
146
928 MHz gain 2.8V
39
31
RF5110G865 MHz to 928 MHz Junction Temperature Versus POUT/VCC
Ambient Temperature = 85°C
RF5110G 865 MHz to 928 MHz Gain and Efficiency Versus POUT/VCC
40
30
POUT (dBm)
Rev A4 DS071026
RF5110G
Application Schematic Small Signal Response
Rev A4 DS071026
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21 of 22
RF5110G
Tape and Reel Information
Carrier tape basic dimensions are based on EIA481. The pocket is designed to hold the part for shipping and loading onto SMT
manufacturing equipment, while protecting the body and the solder terminals from damaging stresses. The individual pocket
design can vary from vendor to vendor, but width and pitch will be consistent.
Carrier tape is wound or placed onto a shipping reel either 330 mm (13 inches) in diameter or 178 mm (7 inches) in diameter.
The center hub design is large enough to ensure the radius formed by the carrier tape around it does not put unnecessary
stress on the parts.
Prior to shipping, moisture sensitive parts (MSL level 2a-5a) are baked and placed into the pockets of the carrier tape. A cover
tape is sealed over the top of the entire length of the carrier tape. The reel is sealed in a moisture barrier, ESD bag, which is
placed in a cardboard shipping box. It is important to note that unused moisture sensitive parts need to be resealed in the
moisture barrier bag. If the reels exceed the exposure limit and need to be rebaked, most carrier tape and shipping reels are
not rated as bakeable at 125°C. If baking is required, devices may be baked according to section 4, table 4-1, column 8 of
Joint Industry Standard IPC/JEDEC J-STD-033A.
The following table provides useful information for carrier tape and reels used for shipping the devices described in this document.
RFMD Part Number
Reel
Diameter
Inch (mm)
Hub
Diameter
Inch (mm)
Width
(mm)
Pocket Pitch
(mm)
Feed
Units per
Reel
RF5110GTR7
7 (178)
2.4 (61)
12
4
Single
2500
QFN (Carrier Tape Drawing with Part Orientation)
Notes:
Ao = 3.18 ± 0.10
Bo = 3.18 ± 0.10
F = 5.50 ± 0.05
Ko = 1.02 ± 0.10
P = 4.00 ± 0.10
W = 12.00 +0.30/-0.10
1. All dimensions are in millimeters (mm).
2. Unless otherwise specified, all dimension tolerances per EIA-481.
4.00 ± 0.10
Ø1.50±.10
2.00 ± 0.05
15 inch Trailer
Top View
1.75±0.10
15 inch Leader
0.279
±.020
Pin 1
Location
Sprocket holes toward
rear of reel
F
RF
Part Number
Trace Code
RF
Part Number
Trace Code
RF
Part Number
Trace Code
P
RF
Part Number
Trace Code
RF
Part Number
Trace Code
RF
Part Number
Trace Code
RF
Part Number
Trace Code
Ao
W
Bo
Ko
Direction of Feed
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Rev A4 DS071026
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