Owner's Manual Model 2032 32K Static RAM Module California . Computer Systems CCS MODEL 2032 32K STATIC RAM MODULE OWNER'S MANUAL COPYRIGHT 1980 CALIFORNIA COMPUTER SYSTEMS 250 CARIBBEAN DRIVE SUNNYV ALE MANUAL NO. CA 94086 89000-0~032 TABLE OF CONTENTS ............................................... ii CHAPTER 1 SETTING THE 2032 JUMPERS 1.1 SETTING THE MEMORY GROUP ADDRESSES ...... . 1.2 SETTING THE BANK BYTE ................... . 1.3 SETTING THE BANK PORT ADDRESS ..........•. 1.4 SETTING MEMORY GROUP BANK-INDEPENDENCE .. . 1.5 SETTING THE RESET JUMPER ................ . 1.6 SETTING THE PHANTOM JUMPER .............. . 1 • 7 SETTING THE WAIT JUMPER ................. . 1.8 EXAMPLES OF JUMPER SELECTION ...... ~ ..... . 1-1 1-2 1-2 1-3 1-3 1-3 1-4 1-5 CHAPTER 2 THEORY OF OPERATION 2. 1 MEMORY .................................. . 2.2 MEMORY ADDRESSING ....................... . 2 • 3 BANK SELECT I ON .......................... . 2.4 BANK-INDEPENDENCE ....................... . 2 • 5 DATA BUFFERS ............................ . 2.6 WAIT STATES .....•......................... FEATURES 2. 7 RESET •••••••••••••••••••••••••••••••••••• 2-1 2-2 2-2 2-3 2-4 2-4 2-4 CHAPTER 3 TESTING AND TROUBLESHOOTING THE 2032 3.1 FRONT PANEL QUICK CHECKOUT ............... 3-1 3.2 DIAGNOSTIC TEST OVERVIEW ................. 3-3 3.3 PREPARING DRIVER ROUTINES ................ 3-4 3.4 SETTING UP FOR THE TEST .................. 3-5 3.5 LOADING THE DIAGNOSTIC ................... 3-5 3.6 RUNNING THE DIAGNOSTIC ...... '. . . . . . . . . . . .. 3-5 3.7 ERROR PRINTOUT INTERPRETATION ............ 3-8 3.8 SAMPLE MEMORY DIAGNOSTIC RUN ............ 3-10 3.9 MEMORY DIAGNOSTIC LISTING .......•....•.. 3-11 CHAPTER 4 TECHNICAL INFORMATION 4.1 SCHEMATIC/LOGIC DIAGRAM .................. 4.2 ASSEMBLY COMPONENT L~YOUT ................ 4.3 PARTS LIST ................................ 4.4 CONTROL ROM TRUTH TABLE .............•.... 4.5 ADDRESS/CHIP TABLE ...•................... 4.6 2032 BUS CONNECTOR PINOUT ................ APPENDIX A LIMITED WARRANTY i 4-2 4-3 4-4 4-6 4-7 4-8 FEATURES Uses Popular 2114 Static RAMs Available with 200, 300, or 450 nsec RAMs Berg Jumpers Used for Selectable Features 8K Memory Blocks Individually Addressable to Any 8K Boundary Bank Selection by Bank Port and Bank Byte 8K Blocks Individually Bank-Enabled LEDs Indicate Board Active and Bank Active States W~it State Jumper Phantom Line Capability Optional Board-Enabling on Reset Operates on +8 Volts Fully Buffered Meets IEEE Proposed S-100 Signal Standards Diagnostic Software Included FR-4 Epoxy PC Board Solder-Masked on Both Sides Silk Screen of Part Numbers and Reference Designations ii CHAPTER 1 SETTING THE 2032 JUMPERS The CCS 2032 is a 32K byte static RAM board designed for use on S-100 busses. Sixty-four popular 2114 static RAM chips make up the four BK memory groups A through D. Each memory group is individually addressed and bank-enabled, and up to three memory groups can be buried to reconfigure the board to BK, 16K, or 24K. The bank select feature, using a bank port and bank byte, is compatible with Alpha-Micro and Board Activ~ and Cromemco as well as with other systems. Bank Active states are indicated by LEDs. To provide optimum compatibility with a variety of systems, CCS has equipped the 2032 with selectable addressing and several optional features. Selections are hardwired with easy-to-use, reliable Berg jumpers. The addresses for each of the BK memory groups, the bank port address and bank byte, and the bank-dependence or bank-independence of each memory group are jumper-selected by the user to best suit his system. Phantom, Wait, and Reset features can be jumper-enabled as desired. Each jumper-selectable feature is discussed individually below. Further explanation can be found in Chapter 2, "Theory of Operation." Illustrations showing jumper settings and relative locations are provided in Section 1.B. 1.1 SETTING THE MEMORY GROUP ADDRESSES In order to provide maximum flexibility in the location of the 2032's memory groups within a bank, CCS has made the addresses of the four memory g~oups ju~per-selectable. The jumper-set address of a memOl'Y group is compared with the high-order address lines A13-tti5, and if the address SETTING THE 2032 JUMPERS 1-2 matches, the group is selected. The Group Address (GRP ADDR) jumpers are in the upper left corner of the board (with the connector pins at the bottom). Set the jumpers of each group to the three high-order binary digits that specify the multiple of 8K at which you wish to locate the group. For example, the addresses of the block between 16K and 24K are 4000h-5FFFh, so you would locate a group in that block by setting its jumpers to 010. Since a memory group's base address must be a multiple of 8K, an easy way to calculate the jumper settings is to divide the base address by 8K. You can then set the jumpers to the binary equivalent of the result. The memory groups are fully prioritized, with A having the highest priority and D the lowest. This allows you to give two (or more) memory groups the same address. Only the higher-priority group will be selected by that address; the RAMs of the other group(s) will be buried, inaccessible and occupying no memory space until the address jumpers are reset. This allows you to configure the 2032 to 8, 16, or 24K without removing RAMs. 1.2 SETTING THE BANK BYTE The Bank Byte jumpers allow you to hardware-map the 2032 memory board to whichever of the eight memory bank levels 0-7 you choose. They are located at the top of the board. To select a bank level, jumper-set a 1 in the bit that corresponds to the desired bank level and jumper-set all other bits to O. For example, to select bank 3 you would set bit D3 to 1 and DO-D2 and D4-D7 to O. You may enable the 2032 with more than one bank. Set to 1 the Bank Byte jumper corresponding to any bank with which you want the board to be enabled. 1.3 SETTING THE BANK PORT ADDRESS In order to assign the board to a bank, you must output the bank byte to the bank port. Most presently-marketed S-100 products using the bank port/bank byte scheme address the bank port at 40h. We recommend that you use this bank port address unless you have a strong reason for doing, otherwise. The Bank Byte jumpers are at the bottom of the board, just above the connector pins. Remember that A7 is SETTING THE 2032 JUMPERS 1-3 the high-order bit; thus you will set the binary bank port address from right to left on the board. 40h is selected by jumper-setting A6 to 1 and AO-A5 and A7 to O. 1.4 SETTING MEMORY GROUP BANK-INDEPENDENCE Each memory group can be made independent of bank selection, causing it to be enabled whenever it is addressed regardless of which bank is active. This makes it possible, in time-sharing situations, for some groups to be commonly accessible while the remaining bank-dependent groups are. reserved for individual users. The bank-independence jumpers are located at the bottoms of the GRP ADDR columns. Setting a jumper to BE (Bank Enable) makes the corresponding memory group bank-dependent. To enable a memory group independent of bank selection, set its bank-independence jumper toME (Memory Enable). 1.5 SETTING THE RESET JUMPER The Reset jumper, at the top center of the board, controls the activating of the bank-dependent memory groups during system resets. If the Reset jumper is set to B, all 32K of memory will be enabled each time the power is turned on or the system is reset. If the Reset jumper is set to A, the bank-dependent memory groups will be enabled only when the board's bank has been selected. Due to lack of room on the board, the Reset jumper labels may be hard to find. The B position is to the right; the A position is to the left. 1.6 SETTING THE PHANTOM JUMPER The Phantom jumper is in the lower right corner of the board. Setting the jumper to B allows a device that generates a PHANTOM signal to overlay portions of the 2032 memory. For example, CCS peripheral control boards generate Phantom signals when certain ROM locations are addressed; these locations contain code to drive the peripherals. If an identically-addressed location exists on the 2032 board, the Phantom signal will block the output from the board of 1-4 SETTING THE 2032 JUMPERS the contents of that location. This allows you to access the rest of the memory locations within the 8K block that contains the overlayed portion. Without Phantom capability the 2032 would not be able to locate a memory group in that block because the 2032 and the peripheral control board would both put data on the bus when a shared location was addressed. Setting the Phantom jumper to A disables signal. 1.7 the -PHANTOM SETTING THE WAIT JUMPER The Wait jumper allows you to slow down your processor every time the board is addressed. This will be necessary if your processor allows a shorter memory access time than your RAMs require. The jumper is in the upper right corner of the board. Off is the A position; on is B. . If you have a 2032 with 200 nsec or 300 nsec RAMs, you should not need to enable the Wait feature for use with presently-available microprocessors. If you have the 450 nsec RAMs and a processor that operates at 4mHz you will, in theory at least, need to enable Wait. You should experiment, however; in many cases the 450 nsec RAMs will work succesifully with a 4mHz processor without a Wait state. Some 2-80 CPU boards, including the CCS 2810, provide a jumper-selectable Wait feature. Enabling this feature may be preferable to enabling the 2032 Wait feature. The 2032 Wait causes a Wait state to occur in every memory cycle in which the board is addressed; the CCS CPU Wait feature causes a Wait state to occur during theM1 cycle only. Because memory access time in the M1 cycle is half a cloak cycle shorter than in the other machine cycles, a Wait state in this cycle effectively increases the time allowed for memory response without unnecessarily slowing the processor in other memory cycles. However, if your system includes memory boards operating at different speeds, you probably will want to enable the Wait features as necessary on the slower memories rather than enable the processor Wait. This will allow you to operate at maximum speed with the faster memories. To find out what is best for your system, check your CPU manual and, if you're not sure, experiment. SETTING THE 2032 JUMPERS 1.8 1-5 EXAMPLES OF JUMPER SETTINGS The first diagram shows jumper settings for a basic CCS system consisting of a 2810 Z-80 CPU, a 2422 disk controller, and the 2032. The bank port address must be 40h. The board is enabled with bank 0 and on start-up. Memory is loca.ted between 0 and 32K. Phantom and Wai tare . disabled. ICIJ GRP AD DR DeB a: A A I"-CDIO~ (I) C\I"- 0 B 10ccccccc1 1111111111 o CiiI 15 BANK BYTE 0 WAIT IiLJ A B 14 13 1 ME o BE BANK PORT 0 1~~~~ 1~~!~1 <t<t<t <t1 <t<t<t<t In the second diagram, memory groups A and Bare bank-independent and located in the last 16K of memory_ Groups C and D reside in banks 2 and 4 between 24K and 40K. The bank port address is 40h. Only groups A and Bare enabled on start-up. Phantom and Wait are enabled. I- m GRP ADDR 0 C B A A a: Iii:] I"-CDIO~(I)C\I""O B 15 loccccccc 1 1111111111 a BANK BYTE a WAIT C]II B A 14 13 1 ME a BANK PORT a 11!~~~ 1~~~1 ««« <i <C«<t:« <t ~~ c:CL CHAPTER 2 THEORY OF OPERATION This chapter is provided for those users who want a more thorough understanding of the 2032 operation than they need just to make the board function in their systems. Used in conjunction with the Logic Diagram and the Control ROM Truth Table in Chapter 4, it should give you a sound understanding of the design and features of the board. Additional information, if desired, can be obtained from data sheets for the individual chips. 2.1 MEMORY The 2032 uses sixty-four 2114-type RAMs. The memory chips are arranged in two-chip columns in order to provide an eight-bit byte, and the thirty-two columns are divided into four 8K memory groups A through D. Because the 2114 provides 4096 bits of storage organized 1024x4, each RAM requires ten address inputs and four bi-directional data lines. A Chip Select input (-CS) provides for the selection of individual chips in the memory array. To prevent erroneous data from getting into the chip a R/-W input inhibits the data input buffer when-high. Thus data can be written to a memory chip only when both -CS and R/-W are low. The 2032 controls -CS through the Column Select Decoders; R/-W is controlled by the Control ROM through the Read/Write Decoder. 2-2 2.2 THEORY OF OPERATION MEMORY ADDRESSING Addressing a specific memory location on the 2032 involves addressing a location on each chip while enabling only one two-chip column. Address lines AO-A9 address one location on each chip through a common address bus. Column selection is handled by four 3-to-8 decoders. Each decoder selects one of eight columns depending on the conditions of inputs A, B, and C, which are controlled by address lines A10-12. Inputs G1, G2A, and G2B determine whether an individual decoder will be enabled, G2A and B low and G1 high enabling a decoder. The three highest-order address lines determine the 8K block in which a memory group resides. Jumpers are used to select each memory group's base address (see Section 1.1). The jumper settings are compared with the top three bits of the incoming address, and if a group's settings correspond to the address bits that group's output line is pulled low. Each group's output line is tied directly to input G2A of the decoder for that group. Also, low outputs from Group A and Group C disable through G1 the decoders for Groups Band D respectively. In addition, groups C and D are disabled through Gl if the output of the ANDing of Groups A and B is low--i.e., if either Group A or Group B has been addressed. This provides full prioritizing of the memory groups, with A the highest priority and D the lowest. Whenever two or more memory groups are given the same base address, only the highest-priority group will be enabled by that address. The other groups will effectively be buried; they will be unaddressable and will occupy no memory space. The final input for each decoder, G2B, is determined by the Control ROM through -CSE (Column Select Enable). See Section 4.4 for the specific conditions under which -CSE will be low. 2.3 BANK SELECTION The CCS 2032 is bank-selectable by bank port address and bank byte. Thus it is fully compa~ble with Cromemco, AM100, and other port-bank-select systems. IT IS NOT COMPATIBLE WITH ADDRESS-SELECT SYSTEMS SUCH AS IMSAI. You assign the 2032 to a bank by jumper-setting the bank port address and the bank byte. The 2032 compares AO-A7 with the jumper-set bank port address using an open THEORY OF OPERATION ft 2-3 collector set of exclusive-OR gates. A pull-up resistor holds the output high unless a wrong address pulls the output low. The BANK PORT ADDRESS line inputs to the Control ROM. If the conditions of the BANK PORT ADDRESS line and the other Control ROM inputs are right (see Section 4.4), BANK CLK will -pulse low, clocking the Bank Enable flip-flop when it rises to high again. In the meantime the bank byte becomes present on DIO-7 and is inverted. Setting a Bank Byte Select jumper to 1 connects the corresponding inverted DATA IN line to the BANK DATA line. Thus a low signal on an inverted DATA IN line, indicating a 1 in the bank byte, will pullrBANK DATA low if the corresponding Bank Byte Select jumper is set to 1. When the flip-flop is clocked, the condition of BANK DATA, the flip-flop's D input, determines the outputs Q and -Q. Q takes the value of D and -0 is D's complement. When BANK DATA is low, indicating that the bank byte and the Bank Byte Select jumpers specify at least one bank in common, the -Q output is high. The -Q output is tied to BANK ENABLE. When BANK ENABLE iS,high, selection of bank-dependent memory groups is enabled. At the same time, the low output at Q lights the Bank Select LED and pulls -BANK ACTIVE low. When -PORT READ and -BANK ACTIVE are both low, -ACK will be low, acknowledging to the processor that a bank has been enabled. When BANK DATA is high, the low on BANK ENABLE forces all bank~dependent memory groups' slect lines (-GROUP A-D) high. The low on -Q also turns of the Bank Select LED, while the high on -BANK ACTIVE (from Q) ensures that -ACK will be high. Because flip-flop outputs do not change until the flip-flop is re-c+ocked, BANK ENABLE, -BANK ACTIVE, and the Bank Select LED will maintain the same states until the bank port is addressed again, when another bank byte will determine whether a high or a low gets clocked into the Bank Enable flip-flop. 2.4 BANK-INDEPENDENCE The 2032 allows you to make any memory group independent of bank disabling by setting a jumper so that the BANK ENABLE line is not connected to the memory-address-comparison circuitry of the memory group you want to make independent. This prevents that memory group's output from being pulled low when the BANK ENABLE line is low. The memory group will therefore be enabled whenever it is addressed, independent of which bank ha~ been selected. 2-4 2. 5 THEORY OF OPERATION DATA· BUFFERS The DATA IN and DATA OUT lines from the data bus are tied together to form the bi-directional data lines for the HAM chips. DIO-7 and DOO-7 are buffered by 3-state bus drivers. If the drivers are in. the high-impedance state, the lines they drive are disabled. The -RD ENABLE and -WR ENABLE lines, which determine whether the DI or DO buffers will be in the high-impedance state, are controlled through the Read/Write Decoder by the Control ROM. See Section 4.4 for the specific conditions under which -RD ENABLE and -WR ENABLE will be low. 2.6 WAIT STATES A wait state is necessary when a peripheral device takes more time to complete a task than the processor normally allows. Because the 2032 is available with 200, 300, or 450 nsec Rams, and because processor speeds vary, the Wait feature on the 2032 has been made jumper-selectable. If the Wait jumper is set to B, pSYNC is inverted and ORed with -CSE, with the output being the pRDY line. When pHDY goes low, the processor adds an extra clock cycle to each memory read or memory write machine cycle during which the board is selected, thereby increasing thetime that signals remain on the address and data busses. If the jumper is set to A, a high signal is ORed with -CSE, the 2032 does not pull pRDY low, and a Wait state does not occur unless it originates elsewhere. 2.7 RESET The Reset jumper allows you to choose whether or not the 2032 will be enabled when the system is powered up or reset by determining which input of the Bank Enable flip-flop will be controlled by pRESET. Pull-up resistors normally hold both the Preset and Clear inputs high, which they must be for the flip-flop to'set and reset normally. The -pRESET line can be jumper-connedted so that either the Preset input or the Clear input is pulled low whenever the power is turned on or the system is reset. If the Reset jumper is set to position A, -pRESET active pulls the Preset input low, the flip-flop is set, BANK ENABLE is low, and the bank-dependent memory groups are disabled. If the jumper is set to position B, -pRESET active pulls the Clear input low, the flip-flop is reset, BANK ENABLE is high, and the bank-dependent memory groups are enabled. CHAPTER 3 TESTING AND TROUBLESHOOTING THE 2032 3.1 FRONT PANEL QUICK CHECKOUT (If your section.) computer does not have a front panel, skip this Before powering on the computer, set the as follows: 2032 jumpers l- en GRP ADDR A a: ~ r-.. CD LO~ (I') (\1"- 0 B 1ooooocool ~IIIIII~· o o 1 BANK PORT ~~~~ I~~!~ ««« «1 «««« BANK BYTE 0 WAIT CiiI A B 0 1 The priority feature will cause Group A to be selected. Set the Front Panel Adress Switches AO-A15 to the off position (OOOOH). Examine that address. Set the Data Switches D1-D7 to the OFF position and .DO to the ON position (01H). Deposit (write) into memory and compare the Data readout with the switch settings. Now switch DO to OFF and D1 to ON, deposit into memory again, and compare the result with the switch settings. Continue the pattern of one Data TESTING AND TROUBLESHOOTING 3-2 Switch ON and the rest OFF until all data bits have been checked. If any data does not match the switch settings, isolate the malfunction with a logic probe or voltmeter before continuing. After Group A has been checked, power down the computer and set Groups B-D to OO~ as shown: GRP ADDR DeB 15 14 13 BE BE Group B will be selected. Examine 2000H (A13 ON, the rest OFf), and deposit the same data bytes as for Group A. Isolate and correct any malfunctions as they become apparent. To check Group C, Groups C and D to 010: power down the computer and set GRP ADDR DeB 15 14 13 BE Examine 4000H (A14 ON, the Groups A and B. rest OFF~, a~~ test as with TESTING AND TROUBLESHOOTING THE 2032 3-3 Finally, to test Group D, power down and set Group D to 011 : GRP ADDR Examine 6000H (A14 and A13 ON, the rest OFF), and test as before. When all malfunctions have been corrected, proceed to the next test. 3.2 DIAGNOSTIC TEST OVERVIEW: These memory dia~nostics run on 8080 or Z-80 systems and provide a practical test of the 2032 memory board. Two diagnostics are provided: a walking bit test and a burn-in test. The routines have been written so that they do not require RAM other than the system stack and the RAM under test. The routi~es may be executed from either RAM or ROM. Diagnostics in general can be divided into three classes: fault detection, fault isolation, and fault correction. These routines perform fault detection and provide sufficient data for fault isolation. After a fault is isolated, correction is a hardware matter. Errors are displayed on the console device when they are detected. Two formats are used. The first, used by the burn-in test and the first stage of the walking bit test, shows errors as follows: ' xx yyyy zz • Each ,character is a hexadecimal digit; xx is the bad data, yyyy is the address where the bad data occurred, and zz is what the data should have been. 3-4 TESTING AND TROUBLESHOOTING The second stage of the walking bit test logs errors as follows: wwww xx yyyy zz Again, each character is. a hexadecimal digit; wwww is the address where-the error was found, xx is the bad data, yyyy is the address where data was last written, and zz is the last written data. These error displays provide enough information for the problem to be isolated. 3.3 PREPARING DRIVER ROUTINES Except for the system-unique input/output drivers, the memory test routines are capable of standing alone. The drivers must be provided by the user. Three routines are needed: CONIN: Console input. Reads one ASCII character from the console keyboard and sets the parity bit (bit 7) equal to O. The character is returned in the accumulator- (A register). CONOUT: Console output. Writes one ASCII character to the console display device. The character to be output is passed to CONOUT in the C register. If the console output device is sensitive to bit 7, then the user must set/reset bit 7 to what is needed in the CONOUT routine. CONST: Console status. This routine reads the console input status. If data is not available, then the accumulator is set to 0 and the status flags must match. If data is pending, then a -1 (OFFH) should be returned in the accumulator (A register). The status flags must show at least a non-zero condition on the return'. After these routines have been prepared they must be loaded into memory. To allow the diagnostics to find them, three jump instructions are located at the front of the diagnostic: 0103H for CONIN, 0106H for CONOUT, and 0109H for CONST. The use~ should put the addresses of his 1/0 routines into these locations. See lines 51, 52, and 53 in the assembly listings. TESTING AND TROUBLESHOOTING THE 2032 3.4 3-5 SETTING UP FOR THE TEST: When you are ready jumpers as illustrated: to begin the test, set the 2032 .--en GRP ADDR cr A D C B ,...(OLOVC")C\I"-O 100000 00 01 ~OUU"I CiiI 15 o WAIT BANK BYTE 0 c::!iI A B 14 13 o 1 BANK PORT ~~~~ I~~!~ « «« «1 «« «« 0 1 At this point you are ready to install the 2032 in your computer. Make sure that no other memory will respond to addresses in the range 4000H-OBFFFH. 3.5 LOADING THE DIAGNOSTIC: No special precautions are necessary. Use your standard method to load the routines. Load the diagnostic into your system at location 0100H. The diagnostic is small enough to fit into the first lK of memory. It was assembled assuming a 16K block of memory would be available starting at OOOOH; if less memory is available, the only change necessary is to alter the stack location. The stack is currently initialized to 3F76H; a good alternate location would be 0100H. 3.6 RUNNING THE DIAGNOSTIC Transfer control of the The computer will type out: DIAGNOSTIC: computer to location 0100H. 3-6 TESTING AND TROUBLESHOOTING You can now select which diagnostic you want. Current options are "C" for continuous burn-in or "W" for walking bit test. Any other selection will cause ???? to be displayed, after which "DIAGNOSTIC:" will again be printed. For the initial test, type in W. The computer will respond: DIAGNOSTIC: WALKING BIT TEST BLOCK SIZE: Select a small block size ini~ially. This way the read/write circuitry can be checked out without a flood of error printouts. A block size of 2 is suggested. To terminate entry type in a space, a comma, or a carriage return. If you type in the wrong number, continue typing in until the last four digits are correct. The computer will now ask for BASE ADDRESS: Type in the desired base address. (Note: The base address must be a multiple of 1024 (0400H). For the board setup suggested, a base address of 4000H is indicated.) At this time the diagnostic will do its test. On completion it will type out TEST DONE DIAGNOSTIC: It is now ready for the next test. If errors were logged, see the troubleshooting section and correct the malfunction. Rerun the diagnostic until an error-free run is achieved. Rerun the walking bit test with a block size of 1K (400H) and a base address of 4000H. Repeat the test, increasing the base address in 1K (4000H) increments, until base address BCOOH has been tested. This tests all memory chips. If errors are logged, replace the appropriate chip(s). Table 3.1 narrows any error to two chips. If the bad data is in the upper half of the byte, replace the odd-numbered chip. If the bad data is in the lower half of the byte, replace the even-numbered chip. For example, the following error printout indicates chip 11 bad: 5C02 84 5C02 04 After a good run for all thirty-two 1K increments, walking bit test with a block 8i~e of 32K (8aaOH). run the TESTING AND TROUBLESHOOTING THE 2032 ~B~~ AR~BE~§ CHIPS TESTED 3-7 MEMORY GROUP 4000H 4400H 4800H 4COOH 5000H 5400H 5800H 5COOH U67, U65, U63, U61, U77, U75, u73, U71, U68 U66 U64 U62 U78 U76 U74 U72 6000H 6400H 6800H 6COOH 7000H 7400H 7800H 7COOH U49, U47, U45, U43, U57, U55, U53, U51, U50 U48 U46 U44 U58 U56 U54 U52 BOOOH B400H 8800H 8COOH 9000H 9400H 9800H 9COOH U32, u30, U28, U26, U40, U38, U36, U34, U33 U31 U29 U27 U41 u39 U37 U35 e e e AOOOH A400H A800H ACOOH BOOOH B400H BBOOH BeOOH U16, U14, U12, U10, U24, U22, U20, U18, U17 U15 U13 U11 U25 U23 U21 u19 D D D D D D D A A A A A A A A B B B B B B B B e e e e C D TABLE 3.1 At this point, invert the memdry group address jumpers and run a 32K block starting at OOOH. This tests the group-select circuitry completely. The primary chips tested here are U1-U3. When all walking bit tests run error-free, type in e for the continuous burn-in test. Specify a block size of 8000H and the appropriate base address (4000H if you follow the above procedure). Let it run for an hour or two to shake out the weak links (infant mortality). To terminate 3-8 TESTING AND TROUBLESHOOTING this test type in Control C. Errors, if any, will be printed out as they occur. The total number of errors will be printed out upon completion of the test. 3.7 ERROR PRINTOUT INTERPRETATION: Errors may show up in many forms. Table 3.2 on the next page matches typical symptoms with probable causes. The best way to isolate a problem (and correct it at the same time) is to pullout a suspect part and replace it with a part that you know to be good. Then rerun the diagnostic and see if the problem is still present. If a problem persists after all suspect parts are replaced, set up a controlled test condition and troubleshoot the problem with a logic probe or a voltmeter, using the logic diagram to identify test points. TESTING AND TROUBLESHOOTING THE 2032 3-9 ERROR CONDITION PROBABLE CAUSE SUSPECT PARTS Bad data=OFFH, all groups a) bank select b) board select U5, U6, U85 U3, U5, U85 Random data or all o data, all groups bad write control U5, U83, U85 OFFH data, one group only a) b) c) d) U2, U2, U1, U1 , One address line hung (printout: good data, bad address) address buffers U81 (AO-6, A15) U82 (A7-14) grounded data line U83, U84 a) open data line b) data line shorted to +5V U83, U84 U83, U84, memory chips a) memory chip access time Try 'setting Wait jumper to Band rerunning tests. Treat as a hard error and replace suspect parts. One data line hung a) hung 0 (good address, bad data=O) b) hung 1 (good address, bad data=1) Soft errors (random addresses and data, non-repeatable) group group group group A select B select C select D select b) heat-sensitive parts Hard memory errors bad memory chip TABLE 32 U3, U3, U3, U3, U9 U42 U60 U70 See Table 3.1 to identify chip. 3-10 3.8 TESTING AND TROUBLESHOOTING SAMPLE MEMORY DIAGNOSTIC RUN: DIAGNOSTIC: WALKING BIT TEST BLOCK SIZE: 30 BASE ADDRESS: 300 BAD BASE ADDRESS: BASE ADDRESS: 400 TEST DONE DIAGNOSTIC: WALKING BIT TEST BLOCK SIZE: 400 BASE ADDRESS: 400 TEST DONE DIAGNOSTIC: WALKING BIT TEST BLOCK SIZE: 1000 BASE ADDRESS: 400 TEST DONE DIAGNOSTIC: WALKING BIT TEST BLOCK SIZE: 1800 BASE ADDRESS: 400 TEST DONE DIAGNOSTIC: ???? DIAGNOSTIC: WALKING BIT TEST BLOCK SIZE: 519 BASE ADDRESS: 400 TEST DONE DIAGNOSTIC: CONTINUOUS BURNIN BLOCK SIZE: 3165 BASE ADDRESS: 3D3 00 ERRORS TEST DONE DIAGNOSTIC: CONTINUOUS BURNIN BLOCK SIZE: 3ABC BASE ADDRESS: 3EF 00 ERRORS TEST DONE DIAGNOSTIC: Typed in W Block may be any size Base address must be multiple of 1K (400H) New test Equal block size, base address Larger block size test Typed in 1 Odd block size Typed in C No parameter restrictions Up to OFFH (255D) errors shown TESTING AND TROUBLESHOOTING 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0049 0040 0043 0043 0100 0100 0100 0100 0100 0100 0100 0100 0100 0103 0106 0109 010C 010F TITLE 3-11 '2114 MEMORY DIAGNOSTIC VER 1.1' Console input/output support routines These routines are a highly-matured, well-thoughtout set based on Intel's monitor. They provide a significant capability to converse with an BOBO, BOB5, or Z-BO based microprocessor system. The only registers altered are the accumulator and the pass register carrying active parameters upon entry to a routine. The stack is used extensively; sufficient space must be provided by the calling programs. The stack pointer is returned to its original place on exit unless an error was detected (SP=?) or parameters are returned on the stack. In the latter case, the stack is offset by 2 times the requested number of parameters and will be set right after these parameters are popped off the stack. Register use conforms to ICOM and CP/M defined conventions: Output data is passed, in the C register and input data is expected in the A register. These routines require CP/M-compatible CONIN and CONOUT routines as contained in the user's BIOS program, or'CI and CO as in the ICOM Resident ROM. OOOA OOOD 0040 0040 .EQU EQU EQU EQU OAH ODH 40H 40H 0040 ORG 406: C38F03 JMP INIT 0100 ORG 0100H C003 C006 C373 COOO C38F03 C303CO C306CO C373,C3 C300CO LF CR CNTL STACK SYSTEM LINKAGES ; CORII EQU OC003H CONOUT EQU OC006H CORST EQU OC373H USER EQU OCOOOH ,. JMP CONI: JMP CONO: JMP CST: ERR: JMP JMP INIT CONIN CONOUT CONST USER ASCII line feed ASCII carriage return ASCII Cntl offset TESTING AND TROUBLESHOOTING l3-12 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72· 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 010F 010F 010F 010F OlaF 01 OF OlaF OlaF 0110 0112 0115 0115 0115 0115 0115 0115 0115 0115 0115 0115 0115 0117 0119 011A 011 C 011 D 011E 01.1E 011 E 011! 011! 011! 011E 011£ 011! 011! 011£ 011F 0122 0125 0126 0121 0127 012B 012B 012B 012B 012B 012B 012B 012B 012B 012B 012B 012E ., C5 OE20 C34901 Routine BLK prints console device. one Entry parameters: Return parameters: Stack usage: None None 4 bytes BLI: PUSH MVI JHP B C,' , ECH2 blank on the current ; Save (BC) Get an ASCII space Go output it Routine CONY converts a 4 bit binary number to its ASCII equivalent. The high-order 4 accumulator ; bits are lost. ., Entry parametOer: Exit parameter: Stack usage: E60F C690 27 CE40 2"7 C9 CONY: ANI ADI DAA ACI DAA RET OFB 90H ·40B 4 bit binary number in lower half of accumulator ASCII character in (A) o bytes ; Clear high bits Insert partial ASCII ; Zone ; Insert rest of ASCII ; Zone Routine CRLF prints an ASCII carriage return and line feed (in that order) on the console. It follows these with 4 blanks to create a left margin. Entry parameter: Exit parameter: Stack Usage: £5 212701 CRLF: CD~l £1 C9 ~ ODOA20AO ; CRHSG: None None 8 bytes Save (H,L) Get message address Print message ; Restore (HL) PUSH LXI CALL POP RET H DB CR,LF,' • , '+80H H,CRMSG PRTlIrA H Routine DEPRT prints the contents of the (DE) register pair as a 4-digit hexadecimal number on the console. Entry parameter: Exit parameter: Stack usage: cnlEOl (DE) = 4 digit hex number to be printed on console. Hone 10 bytes DEPRT: CALL CRLF ; Print a CR, LF ; Alternate entry point if no CR, LF wanted 3-13 TESTING AND TROUBLESHOOTING 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 16~ 162 163 164 165 012E 012F 0132 0133 0133 0133 0134 0135 0136 0137 0138 013B 013C 013C 013C 013F 0142 0142 0142 0142 0142 0142 0142 0 "42 0142 0142 0142 0145 0145 0146 0148 0149 01-49 014C 014D 014E 014E 014E 014E 014E 014E 014E 014E 014E 014E 0151 0151 0152 0155 0156 0157 0157 0157 0157 0157 71 CD3301 7B F5 OF. OF OF OF CD3COl F1 CD1501 C34501 DEPR1: HOV A,D CALL HEI2 HOV A,E Alternate entry point ; digits HEI2: PUSH PSW RRC RRC RRC RRC CALL HEXl POP PSW Alternate entry point on console HEX 1 : CALL CONV JMP ECHl ; Get high order byte ; Print 2 numbers ; Get low order byte to print (A) as two hex Save low order byte ; Move high order nibble to lower half of (A) ; Print the nibble ;_Get low nibble back to print low order nibble ; Convert to ASCII ; Go print it Routine ECHO reads one character from the calling routine and then echoes it. back. It is assumed that the console is in a full duplex mode. Entry parameter: Exit parameter: Stack usage: CD0301 C5. ~67F 4F CD0601 Cl C9 ECHO: CALL CONI ; Alternate entry point ECH1: PUSH B ANI 7FH MOV C,A Alternate entry point ECH2:CALL CONO POP B RET None CA) = Character read from the console keyboard 4 bytes ; Bead a character to print CA) ; Save (BC) ; Strip off parity bit ; Put character into eC) for BLI routine ; Output it ; Restore (BC) Routine HLPRT prints the contents of the (HL) ; register as 4 hexadecimal digits on the console. ., ; Entry parameter: j ; Exit parameter: j Stack usage: ., CD1EOl EB CD2EOl EB C9 HLPRT: CALL CRLF ; Alternate entry point HLPRA: ICHG CALL DEPRA XC.HG RET (BL) = 4 hex digit number to be printed lone 10 bytes ; Print a (CR,LF) ir no CR,LF wanted ; S v a p (HL), ( DE) ; Go print (DE) ; Unswap (BL), (DE) Routine PCHK reads a character from the console and checks whether it is a valid delimiter (space, ; comma, or carriage returri). If so, a zero is ; returned in the status flags. If the character is TESTING AND TROUBLESHOOTING 1-14 166 0157 167 0157 168 0157 169 0157 170 0157 171 0157 172 0157 173 0157 174 0157 CD4201 175 015A 176 015A FE20 177 015C C8 178 015D FE2C 179 015F C8 180 0160 FEOD 181 ·0162. 182 0162 37 183 0163 C8 184 0164 3F 185 0165 C9 186 0166 187 0166 188 0166 189 0166 190 0166 191 0166 192 0166 193 0166 194 0166 195 0166 196 0166 197 0166 198 0166 199 0166 200 0166 201 0166 202 0166 203 0166 204 0166 205 0166 206 0166 207 0166 208 0166 209 *,0166 210 0166 211 0166 212 0166 OEOl 213 0168 214 0168 210000 215 016B CD4201 216 016E 47 217 016F CD9901 218 0172 DA7EOl 219 0175 29 220 0176 29 ; a carriage return, the carry bit is set also. If ; it is not a delimiter, a non-zero, no-carry ; indication is required. ·, Entry parameters: None Exit Parameters: See description above. ; Stack usage: 6 bytes ; PCBK: CALL ECHO ;Read a character , Alternate entry, point if CHAR already in (A) , PCH2: Check for a blank CPI RZ Return if (SO) ,,, CPI Check for a comma , Return if (SO) RZ CPI 'M'-CNTL Check for a CAR RET Set the carry flag STC Return if CAR RET RZ Reset the carry flag CHe ·RET · . Routine PRM reads characters from the console and pushes them onto the stack. Multiple parameters may be read: values are delimited by a space or comma. If a carriage return is entered, PRM stops reading values and returns to the caller. Only ,the last 4 characters of a string are saved; to ; correct an error, type until the last four ; characters are correct. The caller may retrieve the values by popping them from the stack, last-entered character first. ·,, · ·;, Entry parameter: Exit parameters: ; ; ; ; ·, (C) = number of expected parameters (C) Parameters on stack: If a bad value was entered, I????' is printed and control transferred to a user provided error handler. The stack pointer value 1s indeterminate and needs to be reset 4 + 2 = (C) bytes ; Stack usage: ; Alternate entry point it only one parameter is ; desired. C, 1 PARM1: HYI ; Normal entry point Set (BL) = 0 H,O PRM: LXI Get a character ECHO PRA: CALL Save input character B,A PRB: MOY CALL NIBBL Check it and CVB PRC Not hex, see if delim JC Multiply (HL) by 16 H DAD DAD H TESTING AND TROUBLESHOOTING 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 0177 0178 0179 017A 017B 017E 017E 017F 0180 0181 0184 0187 0188 0189 018C 018D 0190 0191 0191 0191 0191 0193 0196 0199 0199 0199 0199 0199 0199 0199 0199 0199 0199 0199 0199 0199 019B 019C 01 9 E 019F 01Al 01A4 0 "A6 01A7 01A9 01AA 01AB 01AB OlAB 01AB OlAB 01AB OlAB 01AB 275 01AB 29 29 B5 6F C36B01 E3 E5 78 CD5AOl D28901 OD C8 C2C401 OD C26801 C9 OEOl 210000 C36EOl 3-15 DAD DAD ORA H L MOV L,A ., JMP PRA PRC: XTHL PUSH H H Go get next character Swap value and RET ADDR ; Resave return address Get last input char See if delimiter' ; Not a carriage return ;-CR, see if all values in Yes, done ; Take error exit it not 0 All in? No, go get another A,B PCH2 PRD MOV PRD: Add on new 4 bits CALL JNC DCR RZ JNZ DCR JNZ RET C QPRT C PRM Alternate entry point if only one parameter ; wanted and first character already in (A). PRF: MVI C,l ; Set up (HL) LXI H,O ; Go get rest ot parameter. JMP PRB Routine NIBBL strips the ASCII zone off a character in the (A) register and verifies that it is a valid hex digit. If so, the binary value is returned to the lower half of the A register; the upper half is set to zero. If not, the carry flag is set and control returned to the caller. ,. D630 DB C6E9 D8 (,," C606 F2A701 C607 DB C60A B7 C9 (A) = ISCII CHAR See description above None Entry Parameter: Exit parameters: Stack usage: HIBBL: :;:; -:1C!ll SUI RC ADI RC ADI JP ala: ADI RC ADI ORA RET ,0' z.. -:o:.Ii:,C btl I J't '0' - , G ' 6 1110 7 10 A Strip otf 0-9 Zone Invalid value RET Strip ott (IF) zone Invalid value RET Sort out in-between values Jump it (IF) Insure it is 0-9 wasn't: Return Adjust binary value Reset carry bit Routine PRTWD prints a character string on the console. Depending on the entry point, a CR and LF may be printed first. Three forms of .; message-end delimiters are accepted: Bit 7=1 in last character to be output; ASCII ETX (CNTRL C) following the last character; or a user-specified delimiter following the last character. If the last option is used, (B) must have the delimiter 3-16 276 01AB 277 01AB 218 01AB 279 01AB 280 01AB 281 01AB 282 01AB 283 01AB 284 01AB 285 01AB 286 01AB 287 01AE 288 01AE 289 01AE 290 OlAF 291 'OlBl 292 01B4 293 01B5 294 01B6 295 01B6 296 01B6 291 01B1 298 01B8 299 01B9 300 01BA 301 01BD 302 01BE 303 01BF 304 01CO 305 01C3 306 01C4 301 01C4 308 01C4 309 01C4 310 01C4 311 01C4 312 01C1 313 OleA 314 01CD 315 01CD 316 01Dl 317 01D1 318 01Dl 319 01Dl 320 01Dl 321 0101 322 01Dl 323 01Dl 324 01Dl 325 01Dl 326 0101 327 01Dl 328 0101 329 01Dl 330 0101 TESTING AND TROUBLESHOOTING on entry to PRTA. Entry Parameters: Exit Parameters: Stack usage: (HL) = Message start address (B) = ETX delimiter (See description above.) None - (BL) is altered ·12 bytes MAX C9 Entry point for CR,LF (will not work with user ; defined ETX delimiter). PRTWD: CALL CRLF ; Entry point for No. CR,LF and a bit 1 or ASCII j ETX Delimiter. PRTWA: PUSH B . Save (BC) f MVI B, 3 t Get an ASCII ETX CALL PRTA Print message POP B Restore (BC) RET 18 4E B9 C8 CD0601 79 23 B1 F2B601 C9 Entry point for user defined ETX delimiter PRTA: MOV A,B Put ETX in A MOV C,H Get next character CMP C EOM? RZ Yes, done CALL CONO No, output it MOV A,C Retrieve CHAR INX H Point to next CHAR .ORA A See if bit 7 is set JP PRTA No, con tinue _, RET CD1EOl C5 0603 CDB601 ~cl Routine QPRT prints "????" and transfers to the user's error- recovery routine. indeterminate on exit. 21CDOl CDAE01 C30C01 QPRT: LXI CALL JMP H,QMSG PRTWA ERR 3F3F3FBF QMSG: DB '???', '?'+80H control (SP) is Message address Print it Go to error recovery Hardware diagnostics can be divided into 3 stages: 1) fault detection 2) fault isolation 3) fault correction These routines automate the first stage only. See the user's manual for guidelines for the second stage. After the second step is completed, fault correction should be no trouble. SUBROUTINES FOR THE MEMORY DIAGNOSTICS When a bad memory cell is detected, this routine TESTING AND TROUBLESHOOTING 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 3~3 384 01D1 01Dl 01Dl 01D1 01Dl 01D1 01D4 01D7 01D8 01DB 01DB 01DB 01DB 01DC 01DF 01EO 01E3 01E6 01E9 01EC 01EF 01FO 01F3 01F3 01F3 01F3 01F3 01F3 01F3 01F3 01F6 01F7 01FA 01FC 01FC 01FD 0200 0203 020·6 0206 0207 0207 020B 020C 020C 020C 020C 020C 020C 020F 0212 0215 0218 0219 021A 3-17 is called to print the bad address, bad data, test ; address, and test d~ta (in that order). With this ; error log, the fault isolation process can be conducted. ; CD2BOl CDOFOl 78 C3E001 F5 CD1E01 F1 CD3301 CDOFOl CDOFOl CD5101 CDOF01 79 C33301 ADPRT: ·;, CALL CALL MOV JMP DEPRT BLI A,B ADPRB ; Print bad address ; Print a blank ; Get a bad data Alternate entry point.when bad address is ; meaningless ADPRA: PUSH PSW ; Do a (CR,LF) CALL CRLF POP PSV Print bad data ADPRB: CALL BE12 CALL BLI CALL BLI ; Print test address CALL BLPRA CALL BLK MOV Get test data A,C JMP BE12 ; Print it ·, Routine BREAK tests the console status to see if a ; character has been typed in. If so, it checks to ; see if it is an ASCII' ETI (CNTRL C). If so, it ; types an "ABORT" message and returns control to the calling routine. CD0901 C8 CD0301 FE03 , ·BREAK: CO 210702 CDAB01 313EOO RRZ LII CALL LII C9 41424F52 DII CALL RZ CALL CPI RET i ABMSG: DB CST CORI 'C'-CRTL ; Character waiting? Ro, return ; Yes, get it See it Cntl C ; 10, return B,ABMSG ; Print out the PRTWD ; 'ABORT' message SP,STACK-2 ; Reset the stack ; Return to exec . 'AB 0 R' , ' T' + 8 0 H Routine PARM reads in the desired test block size and block base address. Both parameters are ; pushed onto the stack. CDAE01 212402 CD1B01 CD6601 £1 £3 E5 ·, POARM: CALL LXI CALL CALL POP ITHL PUSH PRTVA ; Print ealler's Daae H,BZMSG Print BLOCK SIZE aessage PRTWD PARMl ; Get block size H Retrieve it H Save return address TESTING AND TROUBLESHOOTING 3-18 385 021B 213002 PARMA: 386 387 388 389 ., 390 391 392 393 394 395 396 397 39B 399 400 40 i 402 403 ~04 1+05 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 1129 430 431 432 433 434 4?5 021E 0221 0224 0224 0228 022C 0230 0234 0238 023C 023E 023E 023E 023E 023E o23E 023E 023E 023E J23E 023E 023E 023E 023E 023E 023E 023E 023E 023E 023E 023E 023E 0241 0244 0245 0246 0247 0249 024A 024D 024E 0251 0254 0257 025A 025D 0260 0260 0263 0264 0266 0267 026A 026B CDAB01 C36601 424C4F43 4B205349 5A453AAO 42415345 20414444 52455353 3AAO LXI CALL. JMP H,BAMSG PRTWD PARMl BZMSG: DB 'BLOCK SIZE:',' '+80H BAMSG: ADMSG: DB DB 'BASE' , ADDRESS:',' Print BASE ADDRESS message Get it and return '+80H Routine MADT performs a "Walking Bit" test on both the data and address lines of a 2114 pair at the same time. First,it zeros all cells in the specified block, then ensures that they are all zero. It tests each 1K section separately. Detected errors are logged on the console as they occur. The base address, when asked for, must be on a 1K boundary or it will be rejected and another address asked for. The operator can abort the test at any time by typing ETX (CNTRL C) should too many errors be detected. Allowing the test to complete will ensure adequate data for thorough fault isolation. , Without errors, this diagnostic tests a 1K cell in approximately 2 seconds. 217F02 CDOC02 E1 D1 7C E603 B5 CA6002 D5 217B02 CDAB01 213002 CDAE01 CD1B02 C34402 MADT: CD9902 D5 3E04 BA F26B02 57 CDBB02 MADTB: MADTC: MADTA: LXI CALL POP POP MOV ANI ORA JZ PUSH LXI CALL LXI , MADTD: CALL CALL JMP CALL PUSH MVI CMP JP MOV CALL H,WBMSG PARM Sign on Get parameters H Retrieve BASE. ADDRESS Retrieve BLOCK SIZE D A,H 3 L MADTB D H,BEMSG PRTWD H,BAMSG PRTWA' PARMA MADTA ZTBK D A,4 D MADTD D,A WLKAD Test for 1K boundary OK, jump Save block size Reject base address Ask for another Test i t again Zero the block Save block size Set 1K sections See if < lK Yes, test it No, set to 1K Test it 3-19 TESTING AND TROUBLESHOOTING 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 026E 026F 0270 0271 0272 0273 0274 0275 0276 0277 0277 0278 027B 027B 027F 0283 0287 028B 028F 0290 0294 0298 0299 0299 0299 0299 0299 0299 0299 0299 029A 029B 029D 029E 029F 02AO 02A1 02A2 02A5 02A6 02A7 02A8 02A9 02AA 02AB 02AE 02B1 02B2 02B3 02B4 02B5 02B8 02B9 02BA 02BB E1 7D 93 6F 7C 9A 67 C8 EB POP MOY SUB MOY MOY SBB MOV RZ XCHG 09 C36302 DAD JMP B BEHSG: WBMSG: DB DB 'BADt,' '+80H 'WALKING BIT TEST',' '+80H TDMSG: DB 'TEST DON','E'+80H 424144AO 57414C4B 494E4720 42495420 54455354 AO 54455354 20444F4E C5 ., , D5 E5 OEOO 71 23 1B 7B B2 C29D02 E1 D1 D5 E5 7E B9 C4DB01 CDF301 23 lB 7B B2 C2A902 E1 D1. C9 H Get remalnlng size A,L Subtract tested size E L,A A,B D H,A HADTC Return if done (DE) = untested (BL) previous increment ; Set new base address ; - Do 1. t again = Routine ZTBK zeros and tests for a contiguous block of memory. On entry, the (DE) register must have the block size and the (HL) register must have the base address. These values are restored to th~ registers on exit from the routine. ZTBK: ZTBKA: ZTBKB: PUSH PUSH MVI HOV INI DCI MOY ORA JNZ POP POP PUSH PUSH HOY CMP CNZ CALL INX DCI MOY ORA JNZ POP POP RET D H C,O H,C H D Save block size Save base address Write into the block Next address Loop control A,E D ZTBKA H D D Loop if not zeroed Restore registers Save parameters H A',H C ADPRA BREAK H D Read a cell Same as written? Log -error if necessary See if abort wanted Next address Loop control A,E D ZTBKB H D Loop if more to do Restore base address Restore block size 3-20 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502" 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523524 '525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 TESTING AND TROUBLESHOOTING 02BB 02BB 02BB 02BB 02BB 02BB 02BB 02BB 02BC 02BD 02BE 02CO 02C1 02C2 02C3 02C4 02C5 02C6 02C7 02C8 02C9 02CA 02CB 02CC 02CD 02CE 02CF 02DO 02Dl 02D2 02D2 02D5 02D8 02DB 02DE 02DE 02DF 02E2 02E5 02E8 02EB 02EC 02ED 02EE 02EF 02FO 02F1 02F4 02F5 02F6 02F7 02F8 02F9 02FA 02FB ., D5 E5 23 OEll C5 71 E5 33 33 33 33 E1 E5 3B 3B 3B 3B 7E 47 A7 EB E3 C2DE02 CD1703 CCD101 C3E802 B9 C2E502 CD1703 C4D1 0 1 CDF301 E3 EB 23 1B 7B B2 C2CD02 El C1 33 33 Dl D5 3B 3B Routine WLKAD walks a single high bit through each data bit of all addresses in a controlled manner. After a bit is written, all other locations are tested for zeros. .When an error is detected, it is logged as described above. If excess errors occur, abort the test by typing CNTRL C. WLKAD: WLKDA: WLKC: WLKB: PUSH PUSH INI HVI DNZT: BADD: COlT: C, 11 H PUSH B HOV M,C PUSH H INI INI INI INI POP PUSH DCI DCI DCI DCI HOV MOV ANA ICHG XTHL SP SP SP SP H JNZ CALL CZ ,. D H H H SP SP SP SP A,M B,A A JMP DNZT CHLDE ADPRT CONT CMP C JNZ BADD CALL CHLDE CNZ ADPRT CALL BREAK ITHL ICHG IRX B DCI D MOY A,E ORA D JNZ POP POP WLKB INI INI POP PUSH DCI DCX H B Save block size Save address Set AO Set DO, D4 (2114) Save it Write byte into memory Save current address Adjust stack to find base address :Retrieve base address Restore it Readjust stack Read byte Save byte in (B) Test data Get test address Save loop control Non-zero data, jump ; Test addresses Bad cell Continue test See if same as test data Jump if bad data Test addresses See if abort wanted ; Unscramble registers ; Next address Done on this cell? No, jump Get test address Get data SP SP D D SP SF Get block size 3-21 TESTING AND TROUBLESHOOTING 540 02FC 541 02FD 542 02FE 543 02FF 544 0302 545 0303 546 0304 547 0306 548 0307 549 0308 550 0309 551 030A 552030B 553 030C 554 030D 555 0310 556 0311 557 0312 558 0313 559 0314 560 0317 561 0317 562 0317 563 0317 564 0317 565 0318 566 0319 567 031A 568 031B 569 031C 570 031D 571 031D 512 031D 573 031D 574 031D 575 031D 576 031D 577 031D 578 031D 579 031D 580 031D 581 031D 582 031D 583 0320 584 0323 585 0324 586 0325 587 0327 588 0329 79 07 4F D2C002 C1 D1 3600 7D 91 6F 7C 98 67 29 CD1703 FO 09 D5 C5 C3BE02 HOV 032B 032C 032D 032E 0331 HOV C,A JNC WLKC POP POP B D HYI H,O AtL HOV SUB C HOV HOV LtA A,H SBB B HOV DAD H Get data into (A) Shift for next pattern Not done yet Get base address Get block size Reset test cell ; Strip off base address H,A CALL RP CHLDE DAD B D PUSH PUSH JHP B WLKDA Go to next address bit See if done Yes, return Build next address Save block size Save base address Go do it again Compare (HL) register to (DE) register and set flags on result. 7C 92 CO 7D 93 C9 CBLDE~ HOV A,B SUB RNZ D MOV A,L SUB E RET Routine BRNIN continuously writes a sequence of non-zero numbers into a specified memory block and reads them back for comparison. If errors occur, they are logged on the console. A running error total is also maintained. The test may be terminated at any time with a CNTRL C; the error total at this time will be displayed on the console. The test data steps from 1 to 255 decimal, then repeats itself, always skipping O. ., 217703 CDOC02 E1 Dl OEOl 0600 C5 BRNIN: E5 71 OC, C23203 OC LXI CALL POP POP BRNA: 589 032AD5 590 591 592 593 594 A,C RLC BRNB: MYI HYl PUSH PUSH PUSH HOV 1NR JNZ 1NR H,CBMSG PA"RM H D C, 1 B,O B D H H,C C BRNC C Get message address Write it, get parameters Get base address Get block size Seed the data Initialize error count Save data, error count Save bloCK size Save base address Write the data byte Advance data patern Skip 0 Set to 1 TESTING AND TROUBLESHOOTING 3-22 '>95 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 0332 23 0333 lB 0334 7B 0335 B2 0336 C22C03 0339 El 033A Dl 033B Cl 033C D5 033D E5 033E 7E 033F B9 0340 CA4703 0343 04 0344 CDDBOl 0347 OC 0348 C24C03 034B OC 034C 23 034D lB 034E 7B 034F B2 0350 C23E03 0353 El 0354 Dl 0355 CD0901 0358 CA2903 035B CD0301 035E FE03 0360 0360 C22903 0363 CD1E01 0366 78 0367 CD3301 036A 217003 036D C3AE01 0370 0370 20455252 0374 4F52D3 0377434F4E54 037B 494E554F 037F 55532042 0383 55524E49 0387 4EAO 0389 0389 0389 0389 0389 0389 0389 219002 038C CDAB01 038F 3 1 4 0 0 0 6F' f7 0392 21AC03 0395 CDAB01 BRNC: BRND: BRNE: BRRF: INI DCI MOV ORA JNZ POP POP POP PUSH PUSH MOY CMP JZ INR CALL INR JRZ INR INI DCI MOV ORA JNZ POP POP CALL JZ CALL CPI JNZ CALL H D Go to next address Do loop control A,E D BRNB H D B D H A,M C BRNE B ADPRA C BRNF C H D Get base address Get block size Get data seed, error ; Restore them Read data byte ; Check it Skip if OK Error count Log the error Change test data Skip if not zero Reset to 1 Next address ; Loop control A,E D BRND H D CST BRNA CONI 'C'-CNTL Reset base address and block size Time to quit No, do it again ; Get character ETX (Cntl C)? No, continue CALL LXI JMP BRNA CRLF A,B HEI2 H,ERMSG PRTWA ; ERMSG: DB , ERROR','S'+80H CBMSG: DB 'CONTINUOUS BURNIN',' '+80B HOV COUI Error count Print it Get error message add res P~int it and return to E Routines IN!T and EXEC initialize the computer c monitor the console for a command. When a va] ; command is received, control is transferred to t ; appropriate routine. ; RETR: I NIT: EXEC: LII CALL LXI LXI CALL H,TDMSG PRTVD SP,STACK H,DIMSG PRTVD Print 'TEST DORE' ; Set stack point , Print diag message TESTING AND TROUBLESHOOTING 645 646 647 648 649 650 651 652 653 654 0398 039B 039C 039F 218903 E5 CD0301 FE43 03A1 CA1D03 03A4 FE57 03A6 CA3E02 03A9 C3C401 03AC 03AC 44494147 03BO 4E4F5354 03B4 49433Al0 655 03B8 0000 656 03B8 TOTAL ERRORS=OO ., DIMSG: 3-23 Set up return address H,RETN LXI PUSH CALL CPI JZ CPI JZ JMP CONI ' C' BRNIN 'W' MADT QPRT DB 'DIAGNOSTIC:',' '+80H END H ., Wait for command Continuous burn-in Walking bit CHAPTER 4 TECHNICAL INFORMATION 4-2 4.1 TECHNICAL INFORMATION SCHEMATIC/LOGIC DIAGRAM CJ z > CI) Do ,A15n~-1~~':~.- I .............. __~ ·-;":-~.:'--4-44 A 14"~....!·f>.!,-~'--<..-.+----'~r>.."'"-.~--1 A 13"'(,---l·ib~:.!-:__I-+-.!.:D~..O!-'~ i>I~d ~~ i l '2 67 .....5 . , . 77 ;;;;' +5VDC ... ,......' • c •• 'I ~ ~ ~ ~ ~ ,.: .. .~~.'~ A9'" AS" A7" AS" AS" A4JO A3" A2" Al°o AO'" ~ .. .. .... ....-usc> UlO-U17 A 82114 02114 2114 ,"- ...- ..-,' : .-.... ~~ ' - -'... "'",.., ' ..007 00006 "005 -004 .. 003 -002 "001 -000 l...-- -';;'.. .... ,. ~''J''''. '-.... ....... ~.-J ' ,.-?i:= ~6~ ~6c-\IoooI)L- ~6~\~~~------~~1_~~ ~hc:>-~/,(--- -' :; r ~~ -aco ~6~ '-'''fC'kb~ .! Ii ..,' •. ., ~f----- ~'6'o __• .. '-. I v.. 7 . 1 ....- ,r-f,.' ..t-uee ....... ~-- ~ L-----.%,.].!OJ.-..i.)!-..,..-y,-~." MODEL203U 32KSTATIC RAM BOARD "017 .. 016 ..DIS "014 "013 "012 .. 011 "010. 4-3 n~ O r-r. r-c: = N ~: ~UI WCD ~ 41.7u' 41.7 •• ~C) 74LS138 c: ~ .t:' N __~__~__~__~IO W ...• r•... • ~ .. 74LS138 ... ' mm ~13) 74LS138 74LS138 Jc- (:1 (~I o -AD ~C) J CD~ ' Z1 •c: r- _u ( N o ~G)' (0) :x> CJl en [I] 3: !jj L" to< ("') o 3: A1 A2 A Di Di : Z -A4D~~~ A5 A6 U71 U61 U51 U43 U34 U26 U18 U10 U72 U62 U52 U44 U35 U27 U19 U11 U73 U63 U53 U4S U36 U28 U20 U12Z2 U54 U46 U37 U29 . -A7 0 ." o Z tEl Z t-3 L" :x> to< o c::: ~ JD. o D~ c: ~ o" Z m ... .. ~ Z ... en - ....N C m cnNO" cn",C~ <cn mN Z ... r- .. 0> .. O~~ ~I ~~ ... ~w~ o ~ ~ eo NOWc: ..., W»W r- 0l3 N • ~~ ~ en ..., .. .... ~ :. c r- CIJ ~ N ..., U75 U65 U55 U47 U38 U30 U22 o ~ U14 r- en o UI .. ..... ... c: QI o CD • r- Z CIJ ~ N CD _ .__ U76 U66 U58 U48 U31 U31 U23 U1S -< ~ m Z o i~ U77 U87 US7 U49 U40 U32 U24 U18 U18 US8 US8 USO U4' U3l U25 un ~Do PHAHT C9 Z3 " 07 106 05 04 D3 02 4-4 4.3 QTY TECHNICAL INFORMATION PARTS LIST REFERENCE DESCRIPTION CCS PART Tantalum, 4.7uf, 35 vdc, 20% Ceramic, .1uf, 50 vdc, 20% 42804-54756 Network, S1;P, 2.7K x 7 40930-72726 II CAPACITORS 3 C5-7 6 Cl-4,B-9 42142-21046 RESISTORS 3 Zl-3 INTEGRATED CIRCUITS 64 U10-41,43-5B, 61-6B,71-78 MOS 2114 lKx4 Static RAMS 2 U59,69 LM323 +5v regulator 31900-21142 (200nsec) or -21143 (300nsec) or -21144 (450nsec) 32000-03230 2 U79,80 74LS136 quad ex-OR:OC 30000-00136 2 U1,2 74LS20 dual 4-in NAND 30000-00020 2 U7,8 74LS05 hex inverter:OC 30000-00005 4 U9,42,60,70 74LS138 octal decoder 30000-00138 2 U4,B6 75453 dual 2-in OR: OC 30300-00453 1 U6 74LS74 dual D flip-flop 30000-00074 1 U3 74LS08 quad 2-in AND 30000-00008 1 U5 74LS139 2:4 decoders 30000-00139 4 UBl-84 74LS244 Tri buffer 30000-00367 1 UB5 ROM 5623 256x4 30900-05623 TECHNICAL INFORMATION QTY REFERENCE 4-5 DESCRIPTION CCS PART I IC SOCKETS 2 XU4,B6 IC Socket, 8 pin 58102-00080 B XU1-3,6-8,19-BO IC Socket, 14 pin 58102-00140 6 XU5,9,42, 60,70,B5 XU10-41,43-5B, 61-68,11-78 XU81-84 IC Socket, 16 pin 58102-00160 IC Socket, 18 pin 58102-001BO 64 4 ~ IC Socket, 20 pin 58102-00200 35 Header Strip, 1x3 56004-01003 35 Berg Jumper 56200-00001 MISCELLANEOUS 2 CR1,CR2 Diode, Light Emitting 31400-00001 2 XU59,69 Heatsink, Ahamtor 423 60022-00002 Screw, Phillips head (SIMS), 6-32x1116 Nut, hex, 6-32 & lock washer (KEPS) PC Board 11006-32011 Extractor, PCB Non-locking Roll Pin Extractor Mounting Owner's Manual 60100-00000 4 4 1 2 2 1 13006-32001 02032-00002 60100-00001 89000-02032 4.4 CONTROL ROM TRUTH TABLE :z o H ~ '< "~ :z ...J w H (J) c .....:! < U H :z ::z:: u J%l ~ \0 I .:::t X W :r: a: c c < a: < I- m z 0 I DECODER OUTPUTS ROM OUTPUTS CONTROL ROM INPUTS 0:: o rz.. Q. ~ m ::e w !:: a: 3: ::e 0 c a: 3: 0 I CJ Q, I- z z ::l < a: 0 ::: :r: Q. I 0 0 0 c 0 c' m ...... m 3: ...... :E en < W a: ::e w X w AT A6 AS A4 A3 A2 Al AO :r: w m a: W 3: ...... a: m w < 0 w 0 D'l ...... m ~ ...J 0 ~ w z (J) m I < 0 w ...J c m m z< < < w a: w W I- c a: 0 ...J a: I z 3: I OPERATION a: Q. I 04 03 02 01 Y1 V2 Y1 V2 V3 13 0 22 0 32 0 0 0 1 0 0 1 1 6 0 1 1 0 0 1 0 1 1 Ban<-.'ldepeI1dent Memory Read 0 1 0 0 0 1 0 A 1 0 1 0 0 1 1 0 1 Ban<-t1depeI1dent Memory Wrfte (CPU) 0 1 1 0 0 1 0 A 1 0 1 0 0 1 1 0 1 Ban<-t1depeI1dent Memory Wrfte (FP) 46 0 1 0, 0 0 1 1 0 9 1 0 0 1 1 0 1 0 1 Write to Pelt, Memory Selected 53 0 1 0 1 0 0 1 1 6 0 1 1 0 0 1 0 1 1 Ban<-Depelldent Memory Read 56 0 1 0 1 0 1 1 0 C 1 1 0 0 1 1 1 1 0 Read from Port. Memory Selected 62 0 1 1 0 0 0 1 0 A 1 0 1 0 0 1 1 0, 1 Bank-Depenctent Memory Write (CPU) 72 0 1 1 1 0 0 1 0 A 1 0 1 0 0 1 1 0 1 Bank-Dependent Memory Write (FP) C6 1 1 0 0 0 1 1 0 9 1 0 0 1 1 0 1 0 1 Write to Port, No Memory Selected 06 1 1 0 1 0 1 1 0 C 1 1 0 0 1 1 1 1 0 Read from Port, No Memory Selected 0 0 0 0 0 1 1 1 1 1 any other location 4-7 TECHNICAL INFORMATION 4.5 ADDRESS/CHIP TABLE 2032 ADDRESS/CHIP TABLE lOW _BlES LOW COO-FFF 800-Bf'F HIGH LOW 0OO-3FF 400-7FF HIGH LOW HIGH LOW HIGH HIGH GROUF IOBBlE W UI0 un U12 U13 U14 U15 U16 U17 W+1 U18 U19 U20 U21 U22 U23 U24 U25 x U26 U27 U28 U29 U30 U31 U32 U33 X+1 U34 U35 U36 U37 U38 U39 U40 U41 Y U43 U44 U45 U46 U47 U48 U49 USO Y+1 U51 U52 U53 U54 U55 U56 U57 U5B z U61 U62 U63 U64 U65 U66 U67 Z+1 U71 un U73 U74 U75 U76 I un I I 1 U68 U78 I 4-8 4.6 TECHNICAL INFORMATION 2032 BUS CONNECTOR PINOUT +8V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AS A4 A3 A15 A12 A9 001 000 A10 004 DOS 006 012 013 017 sOUT slNP sUEUR GNO 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 +8V 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TOP VIEW PHANTOM IIWRITE pROY pRESET pSYNC iiW'ft AO A1 A2 A6 A7 A8 A13 A14 A11 002 003 007 014 DIS 016 011 010 GNO APPENDIX A LIMITED WARRANTY California Computer Systems (CCS) original purchaser of its products that warrants to the (1) its CCS assembled and tested products will be free from materials defects for a period of one (1) year, and be free from defects of workmanship for a period of ninety (90) days; and (2) its kit products will be free from materials defects for a period of ninety (90) days. The responsibility of CCS hereunder, and the sole and exclusive remedy of the original purchaser for a breach of any warranty hereunder, is limited to the correction or replacement by CCS at CCS's option, at CCS's service facility, of any product or part which has been returned to CCS and in which there is a defect covered by this warranty; provided, however, that in the case of CCS assembled and tested products, CCS will correct any defect in materials and workmanship free of charge if the product is returned to CCS within ninety (90) days of original purchase from CCS; and CCS will correct defects in materials in its products and restore the product to an operational status for a labor charge of $25.00, provided that the product is returned to CCS within ninety (90) days in the case of kit products, or one (1) year in the case of CCS assembled and tested products. All such returned products shall be shipped prepaid and insured by original purchaser to: Warranty Service Department California Computer Systems 250 Caribbean Drive Sunnyvale, California 94086 LIMITED WARRANTY A-2 CCS shall have the right of final determination as to the existence and cause of a defect, and CCS shall have the sole right to decide whether the product should be repaired or replaced. This warranty shall not apply to any product or any part thereof which has been subject to (1) accident, misuse; neglect, negligence, abuse or (2) any maintenance, overhaul, installation, storage, operation, or use, which is improper; or (3) any alteration, modification, or anyone other than CCS or its representative. repair by authorized THIS WARRANTY IS EXPRESSLY IN LIEU OF ALL OTHER WARRANTIES EXPRESSED OR IMPLIED OR STATUTORY INCLUDING THE WARRANTIES OF DESIGN, MERCHANTABILITY, OR FITNESS OR SUITABILITY FOR USE OR INTENDED PURPOSE AND OF ALL OTHER OBLIGATIONS OR LIABILITIES OF CCS. To any extent that this warranty cannot exclude or disclaim implied warranties, such warranties are limited to the duration of this express warranty or to any shorter time p~rmitted by law. CCS expressly disclaims any and all liability arising from the use and/or operation of its products sold in any and all applications not specifically recommended, tested, or certified by CCS, in writing. With respect to applications not specifically recommended, tested, or certified by CCS, the original purchaser acknowledges that he has examined the products to which this warranty attaches, and their specifications and descriptions, and is familiar with the operational characteristics thereof. The original purchaser has not relied upon the judgement or any representations of CCS as to the suitability of any CCS product and acknowledges that CCS has no knowledge of the intended use of its products. CCS EXPRESSLY DISCLAIMS ANY LIABILITY ARISING FROM THE USE AND/OR OPERATION OF ITS PRODUCTS, AND SHALL NOT BE LIABLE FOR ANY CONSEQUENTIAL OR INCIDENTAL OR COLLATERAL DAMAGES OR INJURY TO PERSONS OR PROPERTY. CCS's obligations under this warranty are conditioned on the original purchaser's maintenance of explicit records which will accurately reflect operating conditions and maintenance preformed on ees's products and establish the nature of any unsatisfactory condition of CCS's products. CCS, at its request, shall be given access to such records LIMITED WARRANTY A-3 for substantiating warranty claims.' No action may be brought for breach of any express or implied warranty after one (1) year from the expiration of this express warranty's applicable warranty period. CCS assumes no liability for any events which may arise from the use of technical information on the application of its products supplied by CCS. ces makes no warranty whatsoever in respect to accessories or parts not supplied by CCS, or to the extent that any defect is attributable to any part not supplied by ees. ecs neither assumes nor authorizes any person other than a duly authorized officer or representative to assume for CCS any other liability or extension or alteration of this warranty in connection with the sale or any shipment of CCS's products. Any such assumption of liability or modification of warranty must be in writing and signed by such duly authorized officer or representative to be enforceable. These warranties apply to the orginal purchaser only, and do not run to successors, assigns, or subsequent purchasers or owners; AS TO ALL PERSONS OR ENTITIES OTHER THAN THE ORIGINAL PURCHASER, ecs MAKES NO WARRANTIES WHATSOEVER, EXPRESS OR IMPLIED OR STATUTORY. The term "original purchaser" as used in this warranty shall be deemed to mean only that person to whom its product is originally sold by CCS. Unless otherwise agreed, in writing, and except as may be necessary to comply with this warranty, ces reserves the right to make changes in its products without any obligation to incorporate such changes in any product manufactured theretofore. This warranty is limited to the terms stated herein. CCS disclaims all liability for incidental or consequential damages. Some states do riot allow limitations on how long an implied warranty lasts and some do not allow the 'exclusion or limitation of incidental or consequential damages so the above limitations and exclusions may·not apply to you. This warranty gives you specific legal rights, and you may also have other rights which vary from' state to state.
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