MRV11-0 Universal PROM Module User Guide EK-MRV1 D-UG-001

MRV11-0 Universal PROM Module User  Guide EK-MRV1 D-UG-001
EK-MRV1 D-UG-001
MRV11-0 Universal
PROM Module
User Guide
EK-MRV1 D-UG-001·
MRV11-DUniversal
PROM Module
User Guide
Prepared by Educational Services
of
Digital Equipment Corporation
First Edition, May 1983
Copyright © 1983 by Digital Equipment Corporation. All Rights Reserved.
Printed in U.S.A
The reproduction of this material, in part or whole, is strictly prohibited For
copy information, contact the Educational Services Departmen~ Digital
Equipment Corporation, Maynard, Massachusetts 01754.
The information in this document is subjectto cl"1ange without notice. Digital
Equipment Corporation assumes no responsibility for any errors that may
appear in this document
UniPak is a trademark of Data I/O Corporation.
The following are trademarks of Digital Equipment Corporation, Maynard,
Massach usetts.
~D~DD~D
DEC
DECmate
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DECwriter
DIGITAL
LA
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MASSBUS
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PIOS
Professional
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RSTS
RSX
RT
UNIBUS
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VT
Work Processor
CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.6
1.6.1
1.6.2
CHAPTER 2
2.1
2.2
2.3
2.4
CHAPTER 3
3.1
3.2
3.2.1
3.3
CHAPTER 4
4.1
4.2
4.3
SYSTEM DESCRIPTION
General................................................... 1
Features ......................................... -......... 2
Configuration .............. '" ...................... , , . . .. . 2
Addressing Modes ........................................ 4
Direct Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Page Mode Addressing .............................. 5
Bootstrap ............................................ 5
Physical and Environmental Specifications . . . . . . . . . . . . . . . . 7
Physical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Temperature ......................................... 8
Relative Humidity....... ............................. 9
Altitude............................................... 9
Sea Level Operating Airflow. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanical Shock ................................... 9
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power................................................ 9
Technology .......................................... , 10
FUNCTIONAL DESCRIPTION
Introduction ...............................................
Direct Mode ............................. " ................
Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bootstrap Mode ................................ , . " .......
11
11
14
16
JUMPER CONFIGURATIONS
Introduction ......................... ,.....................
Configuration .. '" .............. " ... " .. , .... , ............
Installing MXV11-B2 ROM on MRV11-D ..............
PROM Sizes and Pinouts ..................................
21
22
22
37
PROGRAMMING
Introduction ............................................... 39
Executing Windowed Programs ........................... 39
Transferring Application Programs from ROM to RAM ..... 41
iii
iv
CONTENTS
CHAPTER 5
5.1
5.2
5.3
5.4
5.5
PROGRAMMING THE ARRAY DECODER
Introduction ...............................................
Decoder Programming Hardware ..........................
Array Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Guidelines and Restrictions ...............................
Designing an Array Decoder ..............................
CHAPTER 6
6.1
6.2
6.3
4~
43
44
47
47
MAINTENANCE
Introduction ............................................... 57
Troubleshooting ......................................... " 57
Console ODT ............................................. 58
APPENDIX A
MODULE CONFIGURATION
FIGURES
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
3-3
3-4
3-5
4-1
4-2
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-_8
A-1
Page Mode Addressing.. .... . . . ..... ......... .... ....... . .
Page Mode Bootstrap .....................................
Direct Mode Block Diagram ...............................
Direct Mode Addressing .................... , ............ "
Chip Select and Out-of-Range Functions (Direct Mode) '"
Page Mode Block Diagram ................................
Bootstrap Mode Block Diagram ...........................
Bootstrap Access to Window 0 (I/O Page) .................
Bootstrap Access to Window 1 (110 Page) .................
MRV11-~ Chip Set Locations .............................
Jumper Configuration Flowchart ..........................
Jumper and Switch Locations .............................
PROM Sizes and Types ...................................
Insertion of 24-Pin PROM Chips ..........................
JSR and JMP Control Routines for Window Mapping ......
Bootstrap Loader for Standalone Programs in RT-11
.SAV Format ...............................................
2K Array Decoder .........................................
Pattern Select ........................................... "
Pin Designations for Array Decoder .......................
Direct Mode Format for Array Decoder .................. "
Page Mode Format for Array Decoder ................... "
Array Decoder Design - Example 1 ........................
Array Decoder Design - Example 2 ........................
Array Decoder Design - Example 3 ...................... "
Module Configuration .....................................
6
8
11
13
13
15
17
18
19
21
23
25
37
38
40
41
45
45
45
49
50
51
53
55
64
CONTENTS
v
TABLES
1-1
1-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
5-1
5-2
6-1
6-2
Storage Capacity Per ROM Chip Size and Number
of Chips ............................ :......................
Typical EPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Backup Shunt (W1, W2) ...........................
System Size Jumpers (W3) ................................
ROM/RAM Selection Jumpers (W4, W5) ...................
DATO Jumper Connection (W6) ...........................
Device Size Jumpers (W7, W8) ............................
Power Jumper Connections (W9, W10, W11, W12) ........
Read Timing Jumper (W13) ................................
Enable Bootstrap Jumper (W14) ...........................
Standard Decoder Pattern Select Jumpers ................
PCR Address Switches ....................................
Starting Address Switches ................................
Array Decoder Programming Hardware ....................
Chip Select and Range Bits for Fully Populated Module ...
Console ODT Commands ..................................
Console ODT States and Valid Input Characters ..........
3
4·
26
27
28
29
30
31
32
33
34
35
36
43
46
58
59
SYSTEM DESCRIPTION
1.1 GENERAL
The MRV11-D is a universal, programmable read only memory (PROM) module. It
is a flexible, high-density, dual-size module for 16-, 18-, or 22-bit Q-bus systems.
The MRV11-D can be used in PDP-11/02, PDP-11/03, SBC-11/21 single board
computer, PDP-11/23A, or PDP-11 123B systems. The module contains sixteen 28pin sockets that accept static random access memory (RAM) and a variety of usersupplied ROMs, such as fusible link PROMs. ultraviolet erasable (UV E) PROMs,
and masked ROMs. It accepts several device densities up to and including 32K by
8. With sixteen 32K devices, memory capacity is 512 kilobytes.
The contents of the module can be accessed in one of two modes, direct mode
addressing or page mode addressing, which emplpys a window-mapping
technique.
Direct mode addressing provides immediate access to all memory locations on the
module. Page mode addressing, or window mapping, provides two 2-kilobyte windows in bus address space that map a 2-kilobyte page each of the memory array.
The page that is viewed or accessed through each window (2 kilobytes per window) can be varied under program control through a page control register (PCR).
The PCR must be written with the desired page number before the access. A
bootstrap feature allows 64 kilobytes of bootstrap code.
2
SYSTEM DESCRIPTION
1.2 FEATURES
The MRV11-D has the following features.
• Full 22-bit Q-bus addressing capability as well as 16- or 18-bit Q-bus
addressing
• Four-kilobyte starting address boundaries
• Directmode or page"mode addressing
• . MXV11-B2 bootstrap PROM option
• Sixteen different page control register locations
• Bootstrap page control register
• Standard bootstrap
• Bootstrap disable
• ROM sockets that house 2K, 4K, 8K, 16K, or 32K by 8 ROMs as well as static
RAM
• Normal or optional high-performance timir:lg
• Optional battery backup for static RAM
• Capacity of 0 to 0.5 megabytes
1.3 CONFIGURATION
The MRV11-D contains 41 jumper posts, 2 switch packs, and 16 memory chip
sockets. The user can configure desired features by connecting the jumper posts
with the 13 jumper clips that are supplied with the module. The module is shipped
from the factory with all jumper clips installed.
The following features can be configured by means of the jumper clips or by the
two switch packs on the module.
Page/direct mode addressing
Location of PCR
Bootstrap enable/disable
Use of multiple MRV11-0 modules
Normal/high-performance timing
Switch-selectable starting address
Allow/inhibit DATa bus cycle
Memory array size and response pattern
Small system/large system
Static RAM
SYSTEM DESCRIPTION
3
The size of the memory array is determined by the size of the memory devices
installed. The MRV11-D is shipped with no memory devioes installed, so the user
must provide and install them.
Digital Equipment Corporation supplies a standard array decoder on the module
that is a preprogrammed fusible link PROM. In the basic configuration with this
array decoder installed, all memory chips must be the same size (2K by 8, 4K by 8,
or 8K by 8). The pin configuration of the chips must conform to the Joint Electron
Device Engineering Council (JEDEC) standard pinout for byte-wide devices. The
following four patterns are available with the standard array decoder supplied by
Digital.
2K by 8 half-populated (socket sets 0-3)
2K by 8 fully populated
4K by 8 fully populated
8K by 8 fully populated
The user can populate the module with many other combinations of devices by
programming his own array decoder. (See Chapter 5.) There are certain device
mixtures that are restricted. Chapters 3 and 5 describe these restrictions.
The user can also configure a system with more than one MRV11-D. Table 1-1
shows the storage capacity per module as a function of device size and number of
device chips. This table lists the capacities for configurations with similar device
sizes. It does not account for the configurations with mixed device sizes that can
be used if the customer programs his own array decoder.
Table 1-2 lists typical UV PROMs and PROMs that can be installed on the MRV11D. Other UV PROMs or PROMs that conform to the JEDEC pinout can also be
used.
Chapter 3 describes how to configure the MRV11-D. Figure 3-1 shows the physical
location of the 16 memory chip sockets. They are divided into eight chip sets, chip
set 0 through chip set 7. Each chip set is composed of a low byte and a high byte.
4
SYSTEM DESCRIPTION
1.4 ADDRESSING MODES
The MRV11-0 can be configured to operate in one of two addressing modes, page
mode and direct mode. Configuration is accomplished by setting a hardware
switch on the module and is not variable under program control.
1.4.1 Direct Address Mode
In direct address mode, each memory location on the MRV11-0 has a corresponding location on the system bus. The number of system bus address locations allocated to the module is equal to the module's configured capacity. For example, an
MRV11-0 that is fully populated (16 devices) with 4K by 8 PROMs (64 kilobytes)
corresponds to 64 kilobytes of the system bus. The starting address of the module
and the array decoder pattern d.etermine the boundaries of the module's address
range.
The starting address of the MRV11-0 can be placed on any 4-kilobyte boundary
from address 08 to 177700008. However, the module's main memory does not
respond to any 1/0 page accesses, even if the address range overlaps the 1/0
page. Only the bootstrap areas and the bootstrap PCR, if enabled, respond in the
1/0 page under direct mode addressing.
SYSTEM DESCRIPTION
5
1.4.2 Page Mode Addressing
Page mode addressing is a virtual addressing scheme that extends the addressing
capability of the system bus. A 4-kilobyte segment of the system bus and an I/O
register called the page control register (peR) are assigned to the MRV11-0. The
MRV11-0's starting address determines the beginning of the module's portion of
the system bus. The user configures the peR address to 1 of 16 locations in the
I/O section of the system bus.
The MRV11-0's portion of the system bus is further divided into two sections called
windows. Each window is 2 kilobytes long and can contain any 2-kilobyte page of
data on the module. The two pages of data that are currently available to the system have their page numbers stored, one in each byte of the peR. To move a different page into the window, simply change the contents of the corresponding peR
byte to the number of the desired page.
Figure 1-1 displays the page mode function. The MRV11-0 has been assigned to
the bus addresses from 166500008 through 166577768. Its peR is at 177770368.
In this example page 1 appears in window 0 and page 5 appears in window 1.
Notice that the low byte of the peR contains a 1 and the high byte contains a 5,
controlling windows 0 and 1 respectively.
Bits 7 and 15 are not part of the page numbers. Bit 7 is unused and bit 15 is the
window control bit. When bit 15 is asserted (1), the windows are open and the
pages in the windows can be accessed. When bit 15 is not asserted (0), the windows are closed and attempted accesses through the windows produce a bus
timeout.
Upon power:-up and restart, the peR bits are cleared to O. Both windows contain
the data from page 0, but they are closed because bit 15 of the peR is also O. Bit
15 must be setto open the windows.
1.4.3 Bootstrap
The MRV11-0 bootstrap operation is similar to page mode addressing. It is independent of 1he address mode chosen for the module. The bootstrap windows are
split. Window 0 begins at 177730008 and runs through 177737768. Windciw 1
begins at 177650008 and runs through 177657768. The bootstrap peR is located
at 177775208. There are, however, the following important differences between
page mode and bootstrap.
1. The bootstrap windows and pages are 512 bytes long. In page mode, the
windows and pages are 2 kilobytes long.
2. Bit 15 of the bootstrap peR is not a control bit. The windows are always
open. In page mode, the windows are open only when bit 15 is a 1.
3. The bootstrap peR address is fixed at 177775208. The page mode peR
address is configured by the user between 177770008 and 177770368.
6
SYSTEM DESCRIPTION
PAGE CONTROL REGISTER
l1j
1413 12 11 10
9
8
0
0
1
0
0
0
1
6
5
4
3
2
1
0
I 10
7
0
0
0
0
0
1
WINDOW #1
DEFAULT PCR
ADDRESS 177 77036
"~II~~ 17777776
17777036
_
WINDOW #0
W INlow
~~~~ 17760000
PAGE 127
EN ABLE
PAGE 126
•
•
•
•
•
PAGE 7
PAGE 6
PAGE 5
, ,
,
............................
.................. ~ i - - - - f - - - - - - -
•
•
•
STARTING ADDRESS OF MODULE
ASSUMED TO BE 166500008
FIRST LOCATION OF WINDOW #0
BEGINS AT STARTlr-iG ADDRESS
OF MRV11·D.
PAGE 5
PAGE 2
PAGE 1
'--_ _--'0
PAGE 0
SYSTEM MEMORY
16K BY 8
ROMS ASSUMED
128 PAGES
OF CODE
MRV11D MEMORY
MA 0179·8:3
Figure 1-1
Page Mode Addressing
The bootstrap memory device must be physically installed in chip set 7. (See
Chapter 3.) The device may be any of the JEDEC standard pinout PROMs or
ROMs that meet the requirements listed in Chapter 3. The module must be properly configured to accept the devices.
The bootstrap program size is limited by the size of the memory devices installed.
A pair of 8K by 8 devices can contain a 16-kilobyte bootstrap program. Note, however, that like page mode addressing, only two 512-byte pages are available to the
system at a time. The program must be specially written to turn its own pages. The
MXV11-B2 bootstrap PROM set is written this way and will function if installed and
properly configured on an MRV11-0. (See Chapter 3.)
If the bootstrap program is smaller than 512 bytes, it can be written on one page,
avoiding the need to change pages. In this case, the program should be in the first
512 bytes of the bootstrap devices. Since the bootstrap PCR clears on power-up
and restart, both windows contain page 0 of the bootstrap devices.
SYSTEM DESCRIPTION
7
Nothing defines the last page of the bootstrap device. If a page number that is larger than the maximum page number for the bootstrap device is placed in th!'l
bootstrap PCR, the device in chip set 7 responds with data from the page that is
given by the following formula.
(requested page number) modulo (pages on device) = actual page number
For example, a pair of 4K by 8 bootstrap devices contain 16 pages of bootstrap
program. An access to page 18 is actually an access to page 2.
18 modulo 16 = 2
Similarly, an access to page 34 or 50 using 4K by 8 bootstrap devices is an access
to page 2. With 8K by 8 bootstrap devices (32 pages), an access to page 33 is
actually an access to page 1 (33 modulo 32).
Figure 1-2 represents the bootstrap function. Window 1 holds the data from page
3. The page number (3 or 38) is stored in the high byte of the PCR. Window 0 holds
the data from page 28. The page number (28 or 348) is stored in the low byte of the
PCR.
If the MRV11-D that contains the bootstrap is also used as a page mode module
on the system bus, the page mode PCR is in an undefined state after the bootstrap
operation. Initialize the page mode PCR before attempting to access the module.
NOTE:
When using the MRV11-0 to bootstrap the RSX11-M operating system,
a line time clock register (17777546eJ must exist on another module to ensure
proper operation.
1.5· PHYSICAL AND ENVIRONMENTAL SPECIFICATIONS
The MRV11-D is a c\as~ C module conforming to the specifications described in
the following paragraphs.
1.5.1
Physical Specifications
Height
13.17 cm (5.187 in), double
Width
1.27 cm (0.500 in), single
Length
22.70 cm(8.940 in), bottom of
fingers to top of handle
8
SYSTEM DESCRIPTION
liD PAGE
22-BlT SYSTEM
PAGE CONTROL REGISTER
15 14 13 12 11 10 9
I 10
0
oL
0
0
0
1
6
5
4
3
2
1
0
1.J.O
0
1
1
1
0
0
B 7
WINDOW
WINDOW #1
BOOTSTRAP PC R
ADDRESS (177775201
---
#0
-
17777520
17773776
PAGE 31
WIN
ENA BLE
(NOT USED
IN BOOTSTRAP
MOD E)
17777776
I
/
PAGE 2B
WINDOW
#0
17773000
PAGE 30
/
/
PAGE 29
PAGE 2B
It
•
•
•
•
•
/
/
PA.GE 3
17765776
WINDOW #1
17765000
/
PAGE 3
PAGE 2
•
17760000
•
•
PAGE 1
SYSTEM MEMORY
PAGE 0
BOOTSTRAP
CHIP SET 7
BK BY B ROMS
ASSUMED - 32
PAGES OF BOOT·
STRAP CODE
MRV11-D MEMORY
MA-0172·83
Rgure 1-2
Page Mode Bootstrap
1.5.2 Temperature
Storage temperature
- 40° C to 66° C ( - 40° F to 151 ° F)
range
The module must stabilize at operating temperature for 5 minutes before
operation.
Operating temperature
range
5° C to 60° C (41 ° F to 140° F)
Derate the maximum operating temperature by 1.f' C (3.24° F) for each 1000 m
(3280 ft) above sea level.
SYSTEM DESCRIPTION
1.5.3
Relative Humidity
Storage
10% to 95%
Maximum wet bulb temperature 32° C
Minimum dew point 2° C (36° F)
Operating
1.5.4
(90~
F)
10% to 95%
Maximum wet bulb temperature 32° C (90° F)
Minimum dew pOint 2° C (36° F)
Altitude
Storage
Up to 9.1 km (5.65 mil
Operating
2.4 km (1.5 mil maximum (paragraph 1.5.2)
1.5.5
9·
Sea Level Operating Airflow
Operating temperature
range
0° C to 55° C (32° F to 131 ° F)
Adequate airflow must be provided to limit the temperature rise across the MRV11o to 10° C (18° F).
Operating temperature
range
55° C to 60° C (131 ° F to 140° F)
Adequate airflow must be provided to limit the temperature rise across t~e MRV11o to 5° C (9° F).
1.5.6 Mechanical Shock
The packaged product shall withstand half-sine shock pulses of 40 9 peak for a
duration of 30 ± 10 ms.
1.6 ELECTRICAL SPECIFICATIONS
This section provides the electrical specifications for the MRV11-D.
1.6.1 Power
The following values are measured for an unpopulated MRV11-D. Add operating
current for eactl device installed. Note only one pair of devices operates at any
given time; the rest are in standby mode.
Voltage
Tolerance
Current
Pins
+5Vdc
.±:0.25 V
1.6 A
AA2, BA2, BV1
280mA
1.3A
AV1
AA2, BA2, BV1
Battery Backup Installed
+5VB
+5Vdc
±0.25 V
±0.25 V
10
1.6.2
SYSTEM DESCRIPTION
Technology
Printed Circuit Board
Board type
Etch
Dual-sized, 4-layer board
O.012/0.013-inch technology
Electronics
Latest MSI (medium scaLe integration) and PAL (programmable array logic)
technologies
Software
Window mapping virtual addressing
FUNCTIONAL DESCRIPTION
2.1
INTRODUCTION
This chapter describes the functional operation of the MRV11-D universal PROM
module. The description divides operation into direct mode, page mode, and
bootstrap mode.
For purposes of explanatIQI1. the discussion refers to a 22-bit Q-bus system. The
bus master asserts a 22-bit address on the Q-bus and then asserts the SYNC line
to gain control of the bus. The address IS latched into the MRV11-D by the bus
interface. Decoding begins as soon as the address stabilizes rather thar al the
assertion of the SYNC line.
2.2
DIRECT MODE
Direct mode addressing IS implemented by configuring the PAGE/DIR switch as
DIR. Figure 2-1 is a block diagram showing the address decoding for direct mode
DATA
~
'"
,16
BUS ADDRESS 0·11
ADDRESS
22
DATA,
BUS
INTERFACE
16
BITS 12·18
=>
CD
"
!::
REPLY
SYNC
CD
N
READ/WR ITE
N
BITS
19,20.2' ,
(OUT 0< I
RANGe ·1
•
j
~: ~~
12 18
I
I i"
I
4
DIREjL---PAGE/DIR
SET TO
DIR
\AGE
~MP.A r
DECODER
TO·8
LINE
DECODER
MEMORY
ARRAY
CHIP
SELECT
8
1
ARRAY
ACCESS
TIMING
CIRCUITRY
VA~
WTBT
BUS
INTERFACE
BITS 12·15
,7
NORMALIZER
START
ADDRESS 12·21
DRIVE DATA
ONTO BUS (READ)
(/)
BITS 0·11
12
BUS ADDRESS
12·21
ACCESS
ACCESS
DETECTOR
BUS BANK SEL 7 (BBS7)
CONTROL
LINES
7
"'i
7
'BUS ADDRESS GREATER THAN
START ADDRESS PLUS 256K WORDS
(MAXIMUM MRV"·D CAPACITY)
BITS 19 OR 20 OR 21 = 1
MA-0171·83
Figure 2-1
Direct Mode Block Diagram
11
12
FUNCTIONAL DESCRIPTION
The bus interface blocks receive address and control signals from the Q-bus and
latch the address when the bus master asserts SYNC. If the bus address corresponds to an address configured for the MRV11-0, then the module responds to
the access per the Q-bus protocol. If not, the module does not respond and does
not transmit information on the bus.
The range of the MRV11-0 is determined by the starting address (lower boundary)
ard the decoder PROM (upper boundary). The normalized address (bus address
minus starting address) measures the distance between the bus address and start
addrest>. If this number is negative, the bus address is below the lower boundary of
the module. If the number is positive, but greater than the configured capacity, the
bus arldress is beyond the module's range. The module responds only when the
bus address is greater than the module starting address and les.s than the configured array size.
Bits 0 through 11 of the bus address are directly mapped to bits 0 through 11 of the
me-;,ory array address. Bits 12 through 18 from the normalizer are applied to the
direct input of the PAGE/OIR multiplexer, which is set to OIR. These bits are then
al iJlied to the array decoder, which determines chip select and out-of-range condition. Additional out-of-range conditions occur if either bits 19, 20, 21, or any combination are asserted. If this happens, the access detector does not issue a valid
access signal to the timing circuit and the RPL Y signal is blocked.
If the bus address is within range of the module, the access detector issues a valid
access signal, which causes RPL Y to be asserted on the bus. If a read cycle was
initiated, the timing circuit drives the data onto the bus. If a write cycle was initiated,
the module accepts data from the bus.
If bits 12 through 21 are all 1s, BUS BANK SELECT 7 (BBS7) is asserted to indicate that the access is not to the memory array but to the 1/0 page. Accesses to the
PCR, bootstrap PCR (BPCR), and bootstrap areas are through the 110 page.
Note that bits 0 through 11 of tne bus address are directly applied to the memory
array and bits 12 through 21 of the bus address are applied to the normalizer with
bits 12 through 21 from the starting address switches. The starting address set in
the switches is subtracted from the bus address (Figure 2-2). This operation establishes the starting address as the lower boundary of the array. Normalized bits 12
through 15 are applied directly to the memory array to be decoded by array devices larger than 2K by 8. Bits 12 through 15 are also applied to the array decoder
along with bits 16 through 18. Bits 12 through 18 perform different functions,
depending on the size of the memories, number of memories utilized in the array,
and the configuration.
For example, with a fully populated array of 2K by 8 PROMs, bits 0 through 11
define a particular byte within each 4 kilobyte boundary. Bits 12, 13, and 14 determine the chip set socket selected while bits 15 through 18 are used as out-of-range
bits (Figure 2-3). If any of these bits are asserted, the address is above the upper
boundary.
FUNCTIONAL DESCRIPTION
21
BUS ADDRESS
(12-211
I
I
X X X X X X X X X Xl
I
BUS ADDRESS
I
MEMORY
ARRAY ADDRESS
L...._ _ _ _ _ _ _ _ _ _ _~=====:::;::::=====~ 22-BIT Q-BUS
MINUS
START ADDRESS
(12-211
RESULT
(NORMALIZED
ADDRESSI
a
12 11
X X X X X X X X X X
I
X X X X X X X X X X
DIRECT
MAPPING
BITS
12-15
15
'USED TO DETERMINE
CHIP SELECT AND OUT
OF RANGE CONDITIONS
~
a
12 11
___
~
___________________
~
MA·0167·83
Figure 2-2
Direct Mode Addressing
ARRAY DECODER
PATTERN 1
LOGICAL
EQUIVALENT
13
- ------ ------
14
-
12
------
HI BYTE
3-TO-8
LINE DECODER
CS7
CS5
4
CS3
16
CS2
~l
V
FROM
PATTE
SELECTR NaC
B, f J
SWITCH ES
PATTE RN 1
C~
CS6
C~
CS4
CS!
CS4
C~
CS2
C5,l
CS2
CS3
esa
eSl
esa
eSl
r;S4
15
17
18
CS6
CS6
a
2
LO BYTE
eS1
--
CSO
-
...
--
-
-
CHIP SET SOCKETS'
OUT OF ARRAY RANGE
OUT OF RANGE
FROM
{BIT 19
NORMALIZER BIT 20
BIT 21
OUT OF
MRV11-D
-RANGE
2K BY 8 PROMS FULLY POPULATED
'DOTS ARE CONNECTIONS TO CHIP SET SOCKETS.
MA-0174·83
Figure 2-3
Chip Select and Out-of-Range Functions (Direct Mode)
13
14
FUNCTIONAL DESCRIPTION
Bits 19, 20, or 21 from the normalizer determine an out-of-range condition where
the maximum capacity of the MRV11-D has been exceeded. Bits 15 through 18
are applied to the array decoder to determine an unselected condition when a chip
set socket is configured for no device, or when a small array's capacity has been
exceeded. Bits 19 through 21 and bits 15 through 18 are combined to determine an
out-of-range condition when either of the above described situations occur.
A pair of 2K by 8 PROMs look at 12 address bits (0 through 11) to specify one byte
in a 4-kilobyte block. Therefore, the next three bits (12, 13, 14) are used by the
array decoder to select the desired pair of devices. This is accomplished by programming the array decoder for the desired configuration.
The standard array decoder has four selectable patterns as described in Chapter
1. Select these patterns with the pattern select jumpers as shown below.
Device
Pattern Select
Jumpers
2K by 8 PROMs, half-populated
2K by 8 PROMs, fully populated
4K by 8 PROMs, fully populated
8K by 8 PROMs, fully populated
00
01
10
11
If 4K by 8 PROMs are used instead of the 2K by 8 PROMs, 13 address bits (0
through 12) are required by the devices. In the fully populated case, bits 13, 14,
and 15 determine the chip set sockets where the devices are to be inserted and
bits 16, 17, and 18 are out-of-range bits. Similarly, for 8K by 8 PROMs, 14 address
bits (0 through 13) are required. Consequently, bits 14, 15, and 16 determine the
chip set socket where each device is to be inserted and bits 17 and 18 are out-ofrange bits.
2.3 PAGE MODE
For page mode operation, the PAGE/DIR switch must be configured in the PAGE
position. The page number is stored in the PCR during a previous bus cycle. This
page number supplies the more significant address bits of the array address. For
all window accesses, bit 15 of the PCR must be set to open the window areas.
Figure 2-4 is a functional block diagram showing the page mode data paths.
Bits 0 through 10 of the bus address are directly mapped to bits 0 through 10 of the
memory array address. Bit 11 of the bus address marks the boundary between
window 0 and window 1 of the bus. If bit 11 equals 1, the page of code in window 1
is accessed. If bit 11 equals 0, the page of code in window 0 is accessed.
The starting address is subtracted from the bus address in the normalizer block
and the result is checked against the upper boundary. (In page mode, the upper
boundary equals the starting address plus 4 kilobytes.) If any combination of normalized bits 12 through 21 are asserted, the address is greater than the upper
boundary of the module - out of its range. In this instance, the access detector gets
an out-of-range signal and never issues a valid access signal to the timing chain.
Consequently, the MRV11-D ignores that bus cycle.
FUNCTIONAL DESCRIPTION
~
16/
DATA
DATA
BUS ADDRESS 0-10
1~
BUS ADDRESS 0-10
/
PC R DATA
16L
START
ADDRESS_
12-21
N
READ/WRITE
CIl
::>
BUS
INTERFACE
WTBT
0
6
I I WINDOW #01
I
l
BUS
ADDRESS
BITS 12-21'
OUT OF
RANGE
TIMING
CHAIN
BUS
ADDRESS
BIT 11=0,
WINDOW #0
~
1
)~AGE
PAGE!
DIR
SET TO
PAGE
I
DIRE
MODE SELECTr
VALID
ACCESS
BUS BANK SEL 7
(BBS7)
,- _ _ J
ACCESS
DETECTOR
CONTROL
LINES ,.
WINDOW
ENABLE
ARRAY
ACCESS
PCR 11-15
PCR 12-17
I
ARRAY DECODER
3-TO-8
LINE
DECODER
I
I
7
l-
....
MEMORY
ARRAY
~WINDOW SELECT
;Y-:BIT
11=1, #1
WINDOW
SYNC
REPLY
8
I 1
WINDOW #1
co
N
15 14
NORMALIZER
DRIVE DATA ONTO
BUS (READ)
!:::
I
PAGE CONTROL REGISTER
WINDOW ENABLE
BUS
BUS ADDRESS
INTERFACE 12-21
22'
0
,
11
ADDRESS
co
15
?
f-,
I
I
'IF ANY OF BUS ADDRESS
BITS 12-21 GO TO 1, OUT OF
RANGE CONDITION OCCURS
8/
CHIP
SELECT
MA0!7683
Figure 2-4
Page Mode Block Diagram
The page numbers in the PCR are multiplexed arid controlled by bus address bit
11, Therefore, the appropriate page number for the accessed window is used to
construct the memory array address, This address is applied to the array and array
decoder as in the direct mode example. Note that the PCR window contains 7 bits
and these bits replace normalized bits 11 through 17. These bits are used by the
array decoder f0r chip select decoding and/or out-of-range conditions.
For a half-populated array of 2K by B PROMs, the PROM sets look at 12 address
bits (bits 0 through 11) because this pattern specifies 4 kilobytes for each set. The
next two bits (12 and 13) are used by the array decoder to select one of the four
chip sets, This is accomplished by setting the pattern select jumpers for the
installed device configuration as shown below.
Pattern Select
Jumpers
Device
2K by 8 PROMs,
2K by B PROMs,
4K by B PROMs,
BK by B PROMs,
half-populated
fully populated
fully populated
fully populated
00
01
10
11
16
FUNCTIONAL DESCRIPTION
If a fully populated array of 2K by 8 PROMs is used instead of the half-populated
2K by 8 PROMs, 12 address bits (0 through 11) are required (Figure 2-3). In this
case then, bits 12, 13, and 14 determine the chip set socket where each device
pair is inserted and bits 15 through 18 are out-of-range bits. Similarly, for 4K by 8
PROMs, 13 address bits (0 through 12) are required. Bits 13, 14, and 15 determine
the chip set socket where each device is to be inserted and bits 16 through 18 are
out-of-range bits. For 8K by 8 PROMs, 14 address bits (bits 0 through 13) are
required. Bits 14, 15, and 16 are chip select bits and bits 17 and 18 are out-ofrange bits.
The array address is derived as follows (Figure 2-4). Bus address bits 0 through 10
are directly mapped to memory array address bits 0 through 10. Bus address bit 11
chooses the byte of the peR that serves as array address bits 11 through 17. The
low byte contains the page number for window 0 (bit 7 is unused): The high by1e
contains the page number for window 1 (bit 15 is a window enable bit). Since a
page mode address is limited to 18 bits, the page mode array capacity is limited to
256 kilobytes. Bus address bits 12 through 21 are used solely to determine that the
access is between the base of window 0 (starting address) and the top of window 1
(starting address plus 4 kilobytes).
Bits 11 through 17 of the memory array address are supplied from the peR (peR
bits 0 through 6 for window 0 or peR bits 8 through 14 for window 1). As previously
mentioned, bits 11 through 17 perform different functions depending on the PROM
devices used and the number of PROMs installed.
Bits 12 through 21 from the normalizer determine an out-of-range condition (4
kilobytes greater than starting address) where ~he range of the MRV11-0 memory
array has been exceeded. Bits 15 through 18 applied to the array decoder determine an out-of-range condition when a chip set socket with no device configured
has been addressed or the page limit has been exceeded. Bits 12 through 21 from
the normalizer and bits 15 through 18 from the array decoder are combined to
detect an out-of-range condition if either of the above described situations occur.
2.4 BOOTSTRAP MODE
Figure 2-5 is a functional block diagram of the MRV11-0 in bootstrap mode. Bus
address bits 0 through 8 are directly mapped to memory array address bits 0
through 8 to define one byte within each 512-byte boundary. Bus address bits 9
through 21 must be either 177738 or 177658 for a valid bootstrap access. As a
result of bits 13 through 21 being asserted, BBS7 is also asserted to indicate an I/O
page access. Bits 9 through 12 are decoded as follows.
21-15
AII1s
177
14 13 12
11 10 9
o
8 7 6,
543
210
1
7
3
x
x
x
14 13 12
1 1 0
'11109
1 0 1
5
876
543
210
x
x
x
or
21-15
AII1s
177
6
FUNCTIONAL DESCRIPTION
A
DATA
17
16
16
BUS ADDRESS O-B
DATA
9
ADDRESSj~
BUS
INTERFACE
PCR DATA
'16
PAGE CONTROL REGISTER
(17777520 8 1
22
BUS ADDRESS
,
9-12,
4
15 14
I I WINDOW 1 I I
DRIVE DATA
ONTO BUS (READI
::J
BUS
;\
ADDRESS
BIT 11
ID
0
READ/WRITE
(ALWAYS
READI
ID
N
N
SYNC
REPLY
CONTROL
LINES
TIMING
CHAIN
,
I
CHIP
SET
7
I
WINDOW
SELECT
I
1
ARRAY ADDRESS 9-15,
,
17773XXX OR
17765XXX
IS VALID.
VALID
ACCESS
BUS
INTERFACE
0
WINDOW 0
l
C1)
t
6
8
L __ ...JI
BUS BANK SEL 7
(BBS71
(ALWAYS OflJl
ACCESS
DETECTOR
CH IP SE LECT 7
WTBT
'"
7
MA-01BO·83
Figure 2-5
Bootstrap Mode Block Diagram
The state of bit 11 chooses the byte of the bootstrap PCR that serves as array
address bits 9 through 15. The 17773XXX represents an access to window 0
(BPCR low byte). The 17765XXX represents an access to window 1 (BPCR high
byte). The bootstrap PCR is located at 177775208.
If an 1/0 address other than the above addresses is detected, the MRV11-0 does
not respond.
In bootstrap mode, chip select 7 is always asserted during a bootstrap access.
Consequently, the bootstrap code must always reside in chip set 7.
Figure 2-6 shows how the bus address is mapped for the bootstrap using window 0
(location 177732708, page 3). Bits 0 through 8 of the bus address map directly to
memory array address bits 0 through 8. Bits 12 through 9 of the bus address are
respectively decoded as 1011. When bit 11 equals 0, the low byte of the PCR is
appended to bits 0 through 8 to form the memory array address. The state of bus
address bits 9 through 21 (all asserted) indicate an acces~ to the bootstrap area in
the 1/0 page.
The page number, loaded in bits 0 through 6 of the PCR, is mapped into bits 9
through 15 of the memory array address. Chip select 7 is always asserted on
bootstrap access, so the array address (32708) is applied to the PROMs in chip set
7.
18
FUNCTIONAL DESCRIPTION
BUS
ADDRESS
j
v
270 8
BUS BANK
SELECT 7
(BBS7)
IFBBS7=1
IT IS 1/0
PAGE ACCESS
AND BITS 13
THRU 21 ARE
IF BIT 11 = 0, IT IS
WINDOW #0 ACCESS
AND BITS 0 THRU 6
OF PCR ARE LOADED
INTO B·ITS 9 THRU 15
OF MEMORY ARRAY
ADDRESS.
1'S.
PAGE CONTROL REGISTER (177775208 )
WINDOW #1
WINDOW #0
1
~~~~~~~~~~r.~~~~
PAGE 3
WINDOW #0
EXAMPLE ASSUMES,
1 ACCESS IS TO 1/0
PAGE (BBS7 = 1,
BITS 13-21 = 1)
2
ACCESS IS TO
BOOTSTRAP AREA
IN 1/0 PAGE AS
DECODED BY BITS
9·12
3
LOCATION 270
IN PAGE 3 OF
WINDOW *'0
4
22·BIT Q·BUS
x
= DON'T CARE
Figure 2-6
X
X
X
o
3
o
MA·0166-83
Bootstrap Access to Window 0 (I/O Page)
Figure 2-7 shows a bootstrap access to window 1, location 177654328. Bits 0
through 8 of the bus address map directly to memory array address bits 0 through
8. Bits 12 through 9 of the bus address are respectively decoded as 0101 with bit
11 equal to 1. Since bit 11 equals 1, the page number for window 1 is selected from
the PCR. BBS7 is asserted since bits 13 through 21 are all asserted, indicating an
access to the I/O page.
To address the 1;0 page, BBS7 and bus address bits 13 through 21 must be
asserted.
The page address (348) in window 1 of the PCR is mapped into bits 9 through 15 of
the memory array address. The address 344328 is applied to chip set 7.
FUNCTIONAL DESCRIPTION
BUS
ADDRESS
j
BUS BANK
SELECT 7
(BBS7)
IF BBS7 = 1,
IT IS 1/0 PAGE
ACCESS AND BITS
13 THRU 21 ARE l'S.
IF BIT 11 = 1, IT
IS WINDOW #1 ACCESS,
AND BITS 8 THRU 14
OF PCR ARE LOADED
INTO BITS 9 THRU 15
OF MEMORY ARRAY
ADDRESS.
PAGE CONTROL REGISTER (177775208 1
EXAMPLE ASSUMES:
ACCESS IS TO 1/0
PAGE (BBS7 = 1 &
BITS 13 THRU 21 =
WINDOW #1
WINDOW #0
11
ACCESS IS TO
BOOTSTRAP AREA
IN 1/0 PAGE AS
DECODED BY BITS
9 THRU 12
3
LOCATION 432
IN PAGE 28 OF
WINDOW #1
4
22-BIT Q-BUS
X = DON'T CARE
20 19 18 17
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
'-----.r---' ~'--v---/ '--v----"'--v---''-.r--'
o
3
4
4
3
2
MA-0170-83
Figure 2-7
Bootstrap Access to Window 1 (1/0 Page)
19
JUMPER CONFIGURATIONS
3.1
INTRODUCTION
This chapter describes how to configure the MRV11-D to function properly for your
application. Configuration is accomplished by setting a bank of PCR switches, setting a bank of starting address switches, and connecting a series of jumper posts.
The required jumper"posts are connected by means of jumper clips designated as
W3 through W16. These jumper clips allow two adjacent jumper posts to be connected. Nonfunctional holder posts are provided in many jumper groups to avoid
the loss of jumper clips when not used. There are 16 memory sockets on the module that house 8 possible chip sets. (Each chip set has a high byte device and a low
byte device.) This arrangement is shown in Figure 3-1.
tom
rnrn
rnrn
[TIm
MA·0197·83
Figure 3-1
MRV11-D Chip Set Locations
21
22
JUMPER CONFIGURATIONS
3.2
CONFIGURATION
T~ configure the MRV11-D properly for a specific application, use the flowchart in
Figure 3-2. The tables referenced in this figure provide a,jditional information on
the jumper and switch selections.
Figure 3-3 shows the location of the jumpers and switches on the module. The
figure contains a reference to a table for each jumper and switch bank. Refer to the
appropriate table to determine the actual jumper connections or switch settings.
For example, Figure 3-3 shows the location of the DATO jumper and references
Table 3-4. Table 3-4 shows the actual jumper posts and describes the possible
connections.
NOTE: The MRV11-D can be remotely enabled and disabled by asserting the
spare bus signal SSPARE3 (bus pin AN1). This signal is not bussed in Digital
backplanes, but may be connected in other backplanes supplied by other
manufacturers.
3.2.1 Installing MXV11·B2 ROM on MRV11·D
Perform the following steps to install an MXV11-B2 PROM set on the MRV11-D.
1. Enable the bootstrap function (Table 3-8).
2. Set the row 4 jumper (power jumper) for an 8K by 8 device (Table 3-6).
3. Set the device size jumper to 8K by 8 (Table 3-5).
NOTES: MXV11-B2 bootstrap ROMs cannot be used if the device size jumper
is set for 2K by 8 or if the power jumper connection for row 4 is set for 16K by 8 or
32K by 8 devices.
For additional information on the MXV11-B2 ROM, refer to the MXV11-B2 ROM
Set User Guide (EK-MXVB2-UG).
JUMPER CONFIGURATIONS
TABLE 3-'
TABLE 3-2
TABLE 3-3
TABLE 3-4
TABLE 3-5
TABLE 3-6
TABLE 3-7
NO
DISABLE
BOOT
TABLE 3-B
TABLE 3-B
MA_Ol6B_B3
Figure 3-2
Jumper Configuration Flowchart (Part 1)
.23
24
JUMPER CONFIGURATIONS
YES
~
_ _--,L-_ _ _
TABLE 3-10
STARTING
ADDRESS =
17770000
~
NO
BOARD WILL RESPOND
TO BOOTSTRAP AND
BOOTSTRAP PCR,
_ _ _......_ _ _.J ONL Y_
SET ADDRESS
MODE TO
DIRECT
STD_ DECODER
PATTERN SELECT
JUMPERS
TABLE 3-11
TABLE 3-9
PROGRAM
NEW
DECODER
SEE
CHAPTER 5
PAGE
lJiHLCT
I
j-=-rA-S""'L:-:E,----;:-3----;1-:-1---
Figure 3-2
Jumper Configuration Flowchart (Part 2)
TABLE 3-10
JUMPER CONFIGURATIONS
POWER JUMPERS
(TABLE 3-61
ADDRESS MODE &
PCR ADDR ESS SWITCHES
~ ~ rt:i''''''''01
~H TI """ '00,""" 'UM" ,
r:11ol UU
6
rvl
XE48
l:J l:J
ROM/RAM
SELECTION
JUMPERS
(TABLE 3-31
~~
4
ff:.~==~
XE4Q
1
SYSTEM SIZE JUMPER
(TABLE 3-21
JUMPER (TABLE 3-71
Figure 3-3
I
XE41
,
XE36
XE43
f"1J1 ,-,
I
~
XE37
l:J tJ
1.:1
~
~
XE~
~
-..c::::>~
:-
1::::: 3 5: DECODER
AR
PATTERN SELECT
JUMPERS (TABLE 3-91
tJ l'J rn M '''''''' '"'"'''
,
XE38
~
2
(TABLE 3-BI
DEVICE SIZE JUMPERS
, 00M ~~
B
r-ul rlJl
READ TIMING
XE42
LJ l:J
~
-..c=:::>
r:1 ij
"1
n
CUl
SWITCHES (TABb.E 3-111
f:j
MM
~ ~ B ~ B ~lJrn~ ~ ~
Jumper and Switch Locations
G
:;
~
I
BATTERY BACKUPSHUNT (TABLE 3-11
DATO JUMPER
(TABLE 3-41
25
26
JUMPER CONFIGURATIONS
JUMPER CONFIGURATIONS ·27
T~ble3~2
SYs1em SjzeJumpers {W3)
28
JUMPER CONFIGURATIONS
Table 3-3
ROM/RAM Selection Jumpers (W4, W5)
HI BYTE
J38~}
J37--0
J36~
ROM/RAM
SELECTION
JUMPERS
6
7
XE48
XESO
4
5
XE44
XE4fi
LO BYTE
J3
:}
J31
-2
--0
J30 - - 0
2
o
JUMPER CONNECTION
HI BYTE
WSrO J38
L() J37
o J36
r:o BYTE
6
0
XE49:
7
JUMPER CONFIGURATIONS
29
30
JUMPER CONFIGURATIONS
[[]
6
7
6
7
",g
"00
XE49-
XESr
4
5
4
5.
XE44
XE46
XE45
XE47
2
3
2
XE40
XE42
XE41
XE~
0
1
0
1
XE36
XEJ8
XE37
XE39-
I
10
3,c"
THETABt.E BELOW REFLECTSTHE R£V CAN(}
'~~~~;~:~=f.;::~.~~~~:
BOARO NOMBER IS LOCATED ON THE coMPoNENt: S
"lfANQSlDE.
. " " " ".
.
50152tJe ~ BElle"ETCH"
,"50152130'" REV I1ET.€.H::··
JUMpt;~ OONM!CTi()N\S~;}
JUMPER CONFIGURATIONS
: ~ower Jumper Connections (W9, W1 0, W~ 1, W12)
6
7
fSfOR 2K:SY 8 ANOliK BY B ROMS
THE'POWER JUMI'ER MAY BE IN
B;ROM. THE POSITION
rv'n"''n,",,,,PfN 26. THE CONFIGURING
FQREXAMPLE, IF 4K BY
l'u"'n;H~Ri'lWS:;1,2.3ANO 16K BY 8 ROMS
4 JUMPER WOULO BE
",,,,,Lu'vv,,,nPINSWHILE ALL
iIPl:::~S'~RrE.tlOI\lINEir.::n:o AS SHOWN.
31
32
JUMPER CONFIGURATIONS I
Table3-7 ReadTimingJumper{W13) ..
JUMPER CONFIGURATIONS
33
34
JUMPER CONFIGURATIONS
l
JUMPER CONFIGURATIONS
35
36
JUMPER CONFIGURATIONS
JUMPER CONFIGURATIONS
37
3.3 PROM SIZES AND PINOUTS
The MRV11-D contains sixteen 28-pin sockets to house the various PROMs and
static RAM devices that can be used in the module. The sockets can house 2K by
8, 4K by 8, 8K by 8, 16K by 8, and 32K by 8 PROMs. In addition, the bottom half of
the socket array (chip sets a through 3) can accommodate static RAM. The 2K by 8
and 4K by 8 PROMs contain 24 pins while the others contain 28 pins.
Figure 3-4 shows the pin assignments for the 24- and 28-pin memories using the
JEDEC standard pinout. The 2K by 8 PROM is represented by the 2716 and the
4K by 8 PROM is represented by the 2732. The other PROM types (8K by 8, 16K
by 8, and 32K by 8) are represented by the 2764, 27128, and 27256 respectively.
The 8K by 8 static RAM is also shown. The basic differences on the 2764, 27128,
27256, and static RAM are in the functions of pins 26 and/or 27. Figure 3-4 shows
these differences. Fqr example, on the 16K by 8 PROM (27128), pin 26 is used as
an address pin (A 13). On the 32K by 8 PROM (27256), pins 26 and 27 are used as
address pins (A 13 and A 14, respectively).
INTEL 2764 PIN CONFIGURATION
8K BY 8 PROM
INTEL 2716 PIN CONFIGURATION
2K BY 8 PROM
INTEL 2732A PIN CONFIGURATION
Vee
4K BY 8 PROM
A,
PGM
NC
A,
Vee
A.
As
As
As
A,
A.
As
Vee
As
A.
Vpp
A.
A"
A.
A3
OE
A3
6E
A,
A
A3
A,
A,
AD
00
CE
0 ,
Os
0 ,
Os
O.
03
0,
O.
0,
GND
0 3
GND
A
10
A,
0,
O.
27128 PIN CONFIGURATION
16K BY 8 PROM
10
CE
0,
O.
O.
Vee
V pp
Vee
AI,
A,
PGM
A13
A,4
Os
A.
As
A.
As
As
A9
A11
As
A9
A11
OE
A 10
A3
A,
°,
OE
A 10
V pp
As
A.
A9
A11
A,
OE
A 10
As
CE
A,
AD
O.
O.
0
1
°
Os
Os
0,
O.
0,
°
GND
0 3
GND
0
0
O.
0'3
Vee
WE
CE,OR N.C.
0
7
O.
0 3
STATIC RAM
A13
CE
OE
CE
Vpp
AD
A"
7
0,
27256 PIN CONFIGURATION
32K BY 8 PROM
A13
A.
0
1
0,
CE
°,
O.
Os
O.
0
3
MA·0203·83
Figure 3-4
PROM Sizes and Types
38
JUMPER CONFIGURATIONS
When installing a 24-pin PROM (2K by 8, 4K by 8) in a 28-pin socket, install it with
the notch on top and bottom justified. Pin 1 of the PROM inserts into pin 3 of the
socket (Figure 3-5). On 28-pin devices, pin 28 is the power. pin. For 24-pin devices,
pin 28 of the socket must be strapped to pin 26 of the socket to provide power to
the device. The power jumpers strap these pins together (Table 3-6).
NOTE: If you are using 24-pin devices such as the 2716 (2K by 8 PROM) on a
revision C etch board, you must wire wrap J13 (Vpp) to J40 (pin 26 of row 4). It is
also necessary to jumper J40 to J41 (+ 5 V). However, you cannot use the jumper
clip because a wire wrap exists on J40. Therefore, you must wire wrap, rather than
jumper, J40 to J41. This procedure ensures proper read mode operation (Table
3-5). On a revision 0 etch board, you can install 2K by 8 PROMs without wirewrap
(Table 3-5).
1
2
3
4
5
6
7
8
9
12
13
14
10
11
12
15
14
13
19
18
11
16
15
MA·0307-8:2
Figure 3-5
Insertion of 24-Pin PROM Chips
PROGRAMMING
4.1 INTRODUCTION
The window-mapped mode can be used in two ways in LSI-11 application programs. One way is to code the application program to execute directly from the
windows. The other is to use the window-mapped board to transfer a standalone
application program from ROM into RAM memory at system start-up. This chapter
provides an example of each type.
4.2 EXECUTING WINDOWED PROGRAMS
Executing directly from MRV11-D windows allows large programs of up to 56
kilobytes of RAM on LSI-11/2 systems. However, software executed in this mode
must be specially designed and written in assembly language.
An application designed for window mode execution must have a mechanism for
calling a subroutine or transferring control to another routine that is in a presently
unmapped section of the windowed ROM board. You must use a technique different from the standard JSR or JMP instructions. This technique is illustated in
Figure 4-1.
The routine that processes subroutine calls and jumps to other pages must, of
course, be in a section of memory that is not window mapped. To call a subroutine
using these capabilities, write CALLWO label instead of JSR PC label.
CALLWO label causes the desired subroutine to map into window O. It also causes
the call to execute. Upon subroutine return, which is done with a normal RTS PC
instruction, the original mapping is restored and control returns to the calling program. To invoke a subroutine and have it mapped in window 1, write
CALLW1 label.
Note that the mechapism shown in Figure 4-1 preserves condition codes from the
called routine back to the caller. That is, routines can return status in the condition
codes. Instead of the unconditional jump instruction, write JMPWO label to jump to
a routine, and map it into window O. Write JMPW1 label to transfer control to a
routine that should be mapped into window 1.
39
40
PROGRAMMING
iADRS IS
WOBASE
W1BASE
JMPW
JSRW
0
WI = 2
WO = 0
MRt,JPCR =
RELATIVE TD BEGINNING DF MRVll-D
150000i«STARTING ADDRESS DF 'MRVll-D
154000
177000
.MACRD
TRAP
.WORO
.ENDM
CALLWO ADRS
JSRW + WO + «ADRS/l000) & 774}
WOBASE + (ADRS & 3777)
CALLWO
.MACRO
TRAP
.WORD
.ENDM
JMPWO ADRS
JMPW + WO + «ADRS/l000) & 774)
WOBASE + (ADRS & 3777)
JMPWO
.MACRO
TRAP
.WORD
.ENDM
CALLWI ADRS
JSRW + WI «ADDRS/IOOO) & 774>
W1BASE + (ADRS & 3777)
JMPWI
.MACRO
TRAP
.WORD
.ENDM
JMPWI ADRS
JMPW + WI + «ADRS/l000> & 774)
W1BASE + (ADRS & 3777)
JMPWI
TRPHAN:
MOV
@#MRVCSR.-ISP)
;Save previous Mapping
TST
MOt,!
MOt,!
- I SP)
RO. -ISP)
6ISP).RI)
ADD
MOV
#2. 6ISP)
IRO). 2ISP)
MOt,!
BIC
- I RO). RO
#177601). RO
ASR
ROR
RO
RO
MOV
#MRVPCR. -ISP)
;Reserue space for adrs
iSaue caller's register
;And set RO to address of
;TRAP + 2
;Update return PC beyond adrs
iMoue adrs (follows TRAP
iinstructions)
iRO TRAP instruction itself
iExtract page #. window #.
iJMP/JSR
iMove JMP/JSR to C bit
iPlace window # in C.
iJMP/JSR in bit 15
;Set ,ddress of window 0 in
iMap bits
iAnd update based on window #
;Map new pa~e in selected
i','indo ...
iEnable windo ... s
iJMP/JSR back to C bit
iRestore caller's re~ister
iIf JMP. branch to 1$
iElse JSR to desired routine
iStore returned condition codes
iin old PS
iRe~tore original MaPpin.
ADC @SP
MOtJB RO. @(SP)
BIS
ROL
#[email protected])+
RO
MmJ
ISP)+. RO
BCS 1$
JSR PC. @ISP)+
MFPS 4ISP)
MOV
ISP)+)@#MRVPCR
RTI
$
MmJ
MO',)
RTI
Figure 4-1
;And return after TRAP
iand adrs
ISP)+. @SP.
(SP)+. @SP
iIf JMP. "love adrs
iUp over ol,j (caller's) PC
iAnd ~o to new location
JSR and JMP Control Routines for Window Mapping
PROGRAMMING
41
To use this mechanism, the program should be assembled with .ENABL AMA to
force absolute addressing in the assembly. At start-up, a bootstrap routine must be
executed from the MRV11-0 bootstrap window or elsewhere. This routine copies
the trap handler routine to RAM memory, if necessary. It initializes the trap vector
to contain the address of the trap handling routine ar.ld a new status word of aliOs.
With this type of application, take care not to cross page boundaries without
remapping to the next page. If you encounter a page boundary, use the JMPWO or
JMPW1 pseudo instructions to move to the beginning of the next page.
4.3 TRANSFERRING APPLICATION PROGRAMS FROM ROM TO RAM
In window-mapped mode, the MRV11-0 can also be used as a low-cost, program
load device for standalone applications. This use allows application programs that
cannot be easily segmented into ROM and RAM sections to be loaded from a
ROM environment into RAM for execution. To use the MRV11-0 in this mode,
write a bootstrap loader program to copy the contents of the ROM board into the
RAM area at power-up. Figure 4-2 demonstrates such a program. The program is
designed to load standalone images created by the RT-11 LINK utility. It is also
possible to load an RSX-11 S system image from one or more MRV11-0 boards
into RAM for execution.
MRl..'PCR = 177000
MR\.)j.iIN = 150000
oNEKj.i = 003777
Mol.J
MOl.)
CLR
MOl,)
MOt,)
'CMP
BHIS
BIT
BNE
INC
BR
#[email protected]#MRVPCR
@#MRI.Jj.iI N+50 • R5
R4
#MRl,)1.j IN. R3
(R3J+. (R4J+
R4. R5
3$
#oNEKj.i. R3
2$
@#MRl.JPCR
1$
iEnable & map low lK words
iR5=RT-ll SAV file hi~h limit
iStart copyin~ into location 0
;Reset to base of first window
;COpy one word into RAM
;Moved hi~hest word in program?
;If HIS. ns
;Have reached next 1 Kw boundary?
iIf NE. no
;Else map next lK in window 0
;And continue copyin~
3$
Mol.J
@#40 • PC
iStart at user's transfer address
Figure 4-2
Bootstrap Loader for Standalone Programs in RT-11
SAV Format
LOADER:
1$
2$
PROGRAMMING THE
ARRAY DECODER
5.1 INTRODUCTION
This chapter is for users who want specific applications on the MRV11-D. As previously specified, the module is shipped with a standard array decoder supplied by
Digital. It provides four predefined patterns.
2K by 8 PROMs,
2K by 8 PROMs,
4K by 8 PROMs,
8K by 8 PROMs,
half-populated
fully populated
fully populated
fully populated
Users whose needs are satisfied by this configuration may omit this chapter with
no loss of continuity.
5.2 DECODER PROGRAMMING HARDWARE
Programming the array decoder requires specific hardware. The basic hardware is
the model 1.9 or model 29 programmer from the Data 1/0 Corporation or the PB11
PROM programming option for the LSI-11 from Digital. Table 5-1 lists the 512 by 4
array decoders, vendors, card setslsocket adapters, and UniPak fixtures. Either
the card set and adapter or the UniPak fixture are required in addition to the basic
hardware.
43
44
PROGRAMMING THE ARRAY DECODER
A brief description of each column in Table 5-1 follows.
512 by 4
Array Decoder
Part Number
Vendor's part number of the PROM
PROM
Vendor
Manufacturer of the PROM
Card Set
Programming card set from the Data 1/0
Corporation that is used to program the PROM
Rev.
Required revision of the card set
Socket Adapter
Part number of socket adapter used with the
card set
UniPak Revision
The UniPak fixture plugs into Data 1/0
Corporation's programmer in place of the card
set. The programmer and UniPak can program
MaS and bipolar PROMs. This column lists the
required revision level. For the 5306/6306
MMI PROM, UniPak revision D or later can be
used. For the others, revision A or later is
applicable.
Fam. Code
Family code programmed for the UniPak and the
specified card set
Pin Code
Pin code programmed for the UniPak and the
specified card set
5.3 ARRAY DECODER
Each array decoder location controls a 4-kilobyte segment of array memory. For
example, in a 512by 4 array decoder, there are 512 locations and each location
controls 4 kilobytes of memory. Two pattern select lines (Figure 5-1) allow one of
four patterns to be selected. Each pattern contains 128 locations (512 divided by
4). The pattern select lines are connected to the pattern select jumpers, which
select the desired pattern.
The first location (location 0) of each pattern responds at the starting address of
the module. Location 1 responds at the next address and so on up to location 127.
These 128 locations comprise the first pattern (pattern 0), which is indicated by
both pattern select lines being O. The next 128 locations comprise pattern 1, the
next 128 locations comprise pattern 2, and the final 128 locations comprise pattern
3 (Figure 5-2)..
NOTE: Figure 5-3 shows the pin designations of the array decoder. Refer to
them when you design the array decoder for a special application.
PROGRAMMING THE ARRAY DECODER
LOGICAL EQUIVALENT
OF PATTERN 1
BUS
ADDRESS
LINES
CSO
CSA
CS1
13
CSB
CS2
14
CSC
12
3-TO-B
DECODER
15
CS3
CS4
16
CS5
17
CS6
1B
CS7
CHIP SELECT
LINES TO
CHIP SELECT
SOCKETS
' - - - - - - f - - - - O U T O F RANGE
PATTERN
{"1"
SELECT LINES
FROM PATTE RN
·....:·0:..."-"-_---'
SELECT SWITCHES
MA-0181-83
Figure 5-1
2K Array Decoder
PATTERN SELECT LINES
r-------------,511
SEL B
SEL A
PATTERN 3
~
383
o
PATTERN 2
256
~
o
PATTERN 1
~
127
o
PATTERN 0
L-__________________
o
~O
MA-0177·S3
Figure 5-2
Pattern Select
ARRAY ADDRESS
18
17
16
15
12
13
ARRAY ADDRESS
14
2
3
4
5
6
7
8
A6
VCC
A5
A7
A4
A8
A3
ENB
AO
MO
A1
M1
A2
M2
GND
M3
16-
+5V
15
14
13
12
"
10
9
PATT. SEL A} TO PATTERN
PA TT. SE L B SELECT
JUMPER CLIPS
CSA
CS8 } CHIP SELECT TO
3-TO·8 DECODER
CSC
OUT-OF-RANGE - TO ACCESS
DETECTOR
MA-0176·83
Figure 5-3
Pin Designations for Array Decoder
45
46
PROGRAMMING THE ARRAY DECODER
Three chip select lines from the array decoder are applied to a 3-to-8 line decoder
(Figure 5-1). The 3-to-8 decoder asserts one of eight chip select lines. One line is
associated with each pair of chip sets. The chip select number and the in-range
signal must be asserted to turn on a chip set. Under these conditions, the chip set
is enabled and all other chip sets are turned off.
For the 2K by 8 decoder pattern, each PROM pair monitors bits 0 through 11.
These bits specify a byte within each 4-kilobyte block. Bits 12 through 14 are chip
select lines. Bits 15 through 18 are bits that determine if the address is in the range
of the MRV11-0. A 4K by 8 PROM pair monitors bits 0 through 12. Table 5-2
shows the chip select bits and range bits for fully populated arrays using other size
PROMs. For each PROM size, bit 0 specifies high byte or low byte. As an example,
a 4K by 8 PROM requires 13 address bits. They are address bits 0 through 12,
where bit 0 merely specifies which byte of the chip set is specified.
The least significant bit (LSB) into the array decoder can resolve between 4kilobyte blocks. For example, in the 2K by 8 PROMs, bit 12 controls the first 4kilobyte boundary and is the LSB applied to the array decoder. The remaining
address bits control the memory boundaries as follows.
Bit
Controls
13
14
15
16
17
18
8-kilobyte boundaries
16-kilobyte boundaries
32-kilobyte boundaries
64-kilobyte boundaries
128-kilobyte boundaries
256-kilobyte boundaries
An 8K by 8 PROM pair requires 14 address bits (0 through 13). In this case, bits
14, 15, and 16 are chip select bits and bits 17 and 18 are out-of-range bits.
;~TaDle5":2, .. Chip Select and Range Bits for Fully Populated Modu.te
Chip Select
Bits
13,14,15
1.4,15,1.6
15, 16;11
. J6,11, 18
Out-of-Range
Bits
16,17,18
17,18
18
PROGRAMMING THE ARRAY DECODER
47
5.4 GUIDELINES AND RESTRICTIONS
When programming your own array decoder, you should follow certain guidelines
and restrictions. This section describes them.
• Use only 2K by 8 devices or larger.
• Devices must be in pairs and there must be no mixing within pairs of devices.
For example, you cannot have a 2K by 8 PROM in the high byte of chip set
socket 0 and a 4K by 8 PROM in the low byte of chip set socket O.
• If you are installing a static RAM, you must install it in the lower half of the
array. A 4K by 8 PROM can be mixed with static RAM in the same row, or I(
can be placed elsewhere in the array. The 8K by 8, 16K by 8, or 32K by 8
PROMs cannot be mixed with RAM in the same row and must be installed in
the upper half.
• If you are creating a pattern that includes bootstrap code, the bootstrap code
must reside in chip set 7. The code should not be included in your pattern.
Otherwise, the bootstrap code will appear erroneously.
• Do not mix 2K by 8 devices with any other device sizes on the module.
• You can mix 8K by 8 devices with 4K by 8 devices in the same row or with
16K by 8 devices in the same row.
• If 32K by 8 devices are installed in a chip set, no other device sizes can be
install~d in the row incorporating that chip set. For example, if 32K by 8
devices are installed in chip set 0, chip set 1 can contain only 32K by 8
devices.
• When developing an array decoder pattern to handle a mixture of device
sizes, enable the largest device to be read first. Otherwise, blocks in the
array will be offset because the larger devices sample hiqher order address
lines.
For example, you have an 8K by 8 RAM pair that must be installed in the
lower half of the array and you want to install a 16K by 8 PROM pair. You
must install the 16K by 8 PROM pair in the upper half. In this case. you
should enable the 16K by 8 PROM to be read first, even though RAM is in the
lower half of the array and 16K by 8 PROM is in the upper half of the array.
5.5 DESIGNING AN ARRAY DECODER
This section briefly describes the procedure for designing a decoder PROM for a
specific application. Before proceeding, become familiar with the guidelines and
restrictions described in the preceding section.
The first step is to convert the bus address to the array address. In direct mode,
select a starting address and subtract it from the bus address. To obtain the array
address in page mode, bits 11 through 21 of the bus address are stripped off. Bits
11 through 17 of the bus address are replaced by bits from the peR that represent
the page number for the corresponding window.
48
PROGRAMMING THE ARRAY DECODER
Next, determine the pattern selection and the decoder PROM address. The pattern
select jumpers determine the pattern select lines. The decoder PROM address is
obtained by appending the pattern select bits to bits 12 through 18 of the array,
address.
Finally, determine which device is to be read for each 4-kilobyte block of bus
addresses. Once the chip set number for each block is determined, it is programmed into the array decoder as out-of-range and chip select C, B, and A.
Refer to Figures 5-4 and 5-5 for help in designing the array decoder. Use the form
in Figure 5-4 when you are using direct mode addressing. Use the form in Figure
5-5 when you are using page mode addressing.
This section provides examples that show how to use these forms. The following
points are common to the examples. Keep them in mind when you review the
examples.
• Because of space considerations, the bus address and array address in the
examples are shown in octal format. The decoder address is shown in binary
format. The binary format for the decoder address is used so you can see the
effect of bit. 12 and higher order bits changing individually throughout the
pattern .
• The pattern select bits (appended to bit 18 of the decoder address) take the
value set in the pattern select jumpers.
• The decoder address, bus address, and array address increase sequentially
through a given pattern.
• Bit 12 defines 4-kilobyte boundaries, so each row represents a 4-kilobyte
increase. The bus address and array address increase by 1DODOs in each
row. This increase is equivalent to the 4-kilobyte increase of the decoder
address.
• The decoder data is the data that is programmed into the device at the specified address. This data consists of the out-of-range line and three chip select
lines labeled C, B, and A. The three select lines are supplied to a 3-to-8 line
decoder with each of the eight output lines connected to a different chip set.
• When the pattern is programmed, all other locations remaining in the pattern
represent an out-of-range condition. The out-of-range condition is denoted
by the out-of-range line going to a logic 1. When this occurs, C, B, and A
select lines are marked with Xs indicating a "don't care" condition.
21
•
• 0
~
21 •
"0
~
DECODER DATA
(BINARY)
DECODER ADDRESS (BINARY)
ARRAY ADDRESS (OCTAL)
BUS ADDRESS (OCTAL)
PATTERN
SELECT
B
A
1B
17
16
15
14
13
12
OUTOF
RANGE
C
B
A
-u
:D
0
G)
:D
}>
~
~
Z
G)
-i
I
m
}>
:D
:D
}>
-<
0
m
0
MA-0189-83
0
0
m
:D
Figure 5-4
Direct Mode Format for Array Decoder
.j:>.
<0
50
PROGRAMMING THE ARRAY DECODER
PAGE NUMBER (BINARY)
DECODER DATA
(BINARY)
DECODER ADDRESS (BINARY)
PATIERN
SELECT
17
16
15
14
13
12
11
B
A
18
17
16
15
14
13
OUT-OFRANGE
12
C
8
A
-
MA-0188-8J
Figure 5-5
Page Mode Format for Array Decoder
Example 1
Figure 5-6 shows an example that uses direct mode addressing with 2K by 8
PROMs in chip sets 0 through 3 and 2K by 8 bootstrap PROMs in chip set 7. The
PROMs are to respond in sequential order from chip sets 0 through 3. Chip set 7 is
dedicated for the bootstrap PROM and will not affect the pattern. This chip set is
selected by a bootstrap access only.
Figure 5-6 shows an example with a module starting address of 0 and bus address
of O. Each row of the figure represents a 4-kilobyte segment (equivalent to
100008). With 2K PROMs, bits 12, 13, and 14 are chip select lines and bits 15
through 18 are out-of-range bits. The decoder address consists of bits 12 through
18 plus the two pattern select lines, which reflect the state of the pattern select
jumpers. With both pattern select bits 011 Os, it means that pattern 0 of the decoder
PROM is being programmed.
Each time bit 12 toggles, a new 4-kilobyte segment is introduced. Bit 13 toggles on
8-kilobyte segments and bit 14 toggles on 16-kilobyte segments.
PROGRAMMING THE ARRAY DECODER
CS7
2K BOOT
CS6
-
-
CS7
2K BOOT
C54
CS5
C54
CS5
-
-
-
CS6
-
CS2
2K
CS3
2K
CS2
2K
CS3
2K
CSO
2K
CS1
2K
CSO
2K
CS1
2K
MODE: DIRECT
PATTERN SELECTED:
START ADDRESS: 00000
BUS ADDRESS: 00000
ARRAY ADDRESS: 00000
DEVICES: 2K BY 8 PROMS IN CSO THRU CS3 AND CS7
ORDER OF RESPONSE: CSO, CS1, CS2, CS3
a
BUS ADDRESS
(OCTAL)
21·
ARRAY ADDRESS
(OCTAL)
21·
~
~
•a
•a
aaaaaaaa
51
DECODER ADDRESS (BINARY)
PATTERN
SELECT
,.......-'--..
B
A 18 17 16 15 14 13 12
aaaaaaaa
a a a a a a
0
a a
DECODER DATA
OUT OF
RANGE C B A
a
a
aaa
CHIP SET
2K by 8
PROM PAIR
aaa
1
aaaa
aaa
1
aaaa
a a a a a a a a
1
a
aa
1
CHIP SET 1
2K by 8
PROM PAIR
aaa
2
aaaa
aaa
2
aaaa
a a a a a a a
1
a
a
a
1
a
CHIP SET 2
2K by 8
PROM PAIR
aaa
3
aaaa
aaa
3
aaaa
a a a a a a a
1
1
a
a
1 1
CHIP SET 3
2K by 8
PROM PAIR
aaa
4
aaaa
aaa
4
aaaa
a a a a a a
1
a a
a
1 7 7
aaaa
a a
1
1
-
-
·•
x x X
OUT OF
RANGE
'
a
1 770000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\
1
1
- END OF PATTERN
1
1
1
\
X X X
OUT OF
RANGE
a- - - - - -- - - - - - -
NOTE THAT CHIP SET 7 IS NOT PART OF
THE PATTERN AND IS SELECTED ONLY
BY A BOOTSTRAP ACCESS THROUGH BOOTSTRAP WINDOWS
17773000 - 17773777
OR
17765000 - 17765777
MA-0192-BJ
Figure 5-6
Array Decoder Design - Example 1
Consequently, the pattern increments from 000000008 to 000300008, The out-ofrange condition and the chip select lines (C, B, and A) contain the data programmed into the decoder PROM, The C, B, and A lines are the chip select lines
that enable the proper chip set sockets via a 3-to-8 line decoder,
After pattern 0 of the decoder PROM is programmed (array address equals
000300008), the remaining locations in pattern 0 are considered out-of-range (outof-range bit asserted), The C, B, and A bits at this point are in the "don't care" condition and are indicated by an X in the column,
a
Patterns 1, 2, and 3 are programmed in similar fashion and can be programmed
with different patterns, The pattern select lines reflect the pattern being
programmed.
52
PROGRAMMING THE ARRAY DECODER
Example 2
Figure 5-7 shows an example using direct mode addressing with 4K by 8 PROM
chips in all sockets except for chip set 4, which contains 8K by 8 chip sets. In
accordance with the guidelines previously described, chip set 4 must respond first
since it is the largest memory device included. For this example, the response
order is chip set 4,5, 6, 7, 0, 2, 1, and 3.
In Figure 5-6 the bus address and the starting address are the same. In this example, they are different. The starting address is 200008.
Note that the pattern select bits are 112, indicating pattern 3 is selected. Also, for
4K PROMs, bits 13, 14, and 15 are chip select lines. For 8K PROMs, bits 14, 15,
and 16 are chip select lines. Consequently, bit 12 for the 4K by 8 PROMs and bits
12 and 13 for the 8K by 8 PROMs are ignored while those devices are accessed.
Since each entry in the table represents a 4-kilobyte block, the 8K by 8 PROM pair
(16 kilobytes) requires four entries of 4 kilobytes each. The 4K by 8 PROM pair (8
kilobytes) requires two entries of 4 kilobytes each. The C, B, and A lines are the
binary equivalent of the chip set socket. For example, the C, B, and A lines for chip
set 4 are 1002.
The PROMs are listed in the order they are to respond. When the last chip set is
programmed (chip set 3), the out-of-range bit is asserted and the C, B, and A lines
are contained with .xs denoting a "don't care"· condition. The end of the pattern
occurs when bits 12 through 18 are al11 s as shown ..
This example represents the decoding of one-fourth of the decoder PROM, which
is pattern 3. Patterns 0, 1, and 2 would be similarly programmed, if required, and
the pattern select bits would be changed to reflect each pattern.
PROGRAMMING THE ARRAY DECODER
CS6
4K
CS7
4K
CS6
4K
CS7
4K
CS4
8K
CS5
4K
CS4
8K
CS5
4K
CS2
4K
CS3
4K
CS2
4K
CS3
4K
csa
CSl
4K
CSO
4K
CSl
4K
4K
BUS ADDRESS (OCTAL.)
•a
21-
MODE: DIRECT
PATIERN SELECTED: 3 (11 BINARY)
START ADDRESS: 20000 (OCTAL)
BUS ADDRESS: 20000 (OCTAL)
ARRAY ADDRESS: 00000 (OCTAL.)
DEVICES: 4K BY B PROMS IN ALL CHIP SETS EXCEPT
BK BY B IN CHIP SET 4
ORDER OF RESPONSE: CS4, CS5, CS6, CS7,
ARRAY ADDRESS (OCTAL)
a
a
a
a
2
3
4
5
a
a
a
a
a
a
a
a
aa
aa
aa
aa
aaa
aaa
6
aaaa
aaaa
aaa
aaa
aa
aa
1
1 1
aaaaa
aaaa
aa
aa
1 2
1 3
aa
aa
a
a
a
a
1
1
1
1
a
a
a
a
4
5
aaaa
aaaa
1
1
1
1
a a a a
a a a a
aaa
aaa
6
7
aaaa
aaaa
1
1
1
1
aaaa
aaaa
aa
aa
1
1 1
aaaaa
aaaa
1
1
1 4
1 5
aaaa
aaaa
aa
aa
1 2
1 3
aaaa
aaaa
aa
aa
1 6
1 7
aaaa
aaaa
aa
aa
1 4
1 5
aa
aa
2
2 1
aaaaa
aaaa
aa
aa
1 6
1 7
aa
aa
2 2
2 3
aaaa
aaaa
aa
aa
2
2 1
aa
2 4
aa
2 2
"
I
2
a
1
-- -
aaaa
I
···. ,
aaaaa
aaaaa
a1 aaa
a2 aaa
a3 aaa
,.....-A--.,
1
1
1
1
,
a
a
a
a
DECODER ADDRESS (BINARY) DECODER DATA
PATIERN
SELECT
a
a
a
a
7
a
a
a
a
a
a
a
a
1
1
1
1
a
a
a
a
a
a
a
a
1
1
a a
a 1
a
a
1
1
a
a
1
1
}
a a a a
a a a a
1
1
1
1
a
1
a
a
1 1
1 1
a
a
}
1
1
a a a
a a a
1
1
a a a
a a 1
a
a
1 1 1
1 1 1
}
CHIP SET 7
4K BY 16
1
1
1
1
a a a
a a a
1
1
a
a
1
1
1
a
a
aaa
aaa
}
CHIP SET
4K BY 16
PROM PAIR
aaaa
aaaa
1
1
1
1
a a a
a a a
1
1
1
1
a a
a 1
a
a
aa
aa
1
1
}
CHIP SET 1
4K BY 16
PROM PAIR
aaaa
aaaa
1
1
1
1
a a a
a a a
1
1
1
1
1
1
a
1
a
a
a
a
1
1
a
a
}
CHIP SET 2
4K BY 16
PROM PAIR
aaaaa
aaaa
1
1
1
1
a a
a a
1
1
a a a a
a a a 1
a
a
a
a
1 1
1 1
aaaa
,1
1
a a
1
a a
1
X X X
OUT OF
RANGE
1
X X X
OUT OF
RANGE
..
~
1 7 7
aaaa
-- ----- -- --- -
a
a
a
a
1
1
1
1
···
1
a
a
I
y
,
1
a
a
a
a
}"''''''
a a a
a a 1
a 1 a
a 1 1
'-----v------'
a
CS2, CS1, CS3
OUT OF
B A lB 171615 141312 RANGE C B A
~?
1..14,l;.:S
aa
aa
aa
aa
•a
21"
csa,
\
,
1
1
1
1
END OF PATIERN 3 (11 2 ) - - - - - -
..:
-- -
BK BY 16
PROM PAIR
}
CHIP SET 5
4K BY 16
PROM PAIR
CHIP SET 6
4K BY 16
PROM PAIR
PROM PAIR
a
CHIP SET 3
4K BY 16
PROM PAIR
MA-0191·83
Figure 5-7
Array Decoder Design - Example 2
53
54
PROGRAMMING THE ARRAY DECODER
Example 3
Figure 5-8 shows an example using page mode addressing with 8K by 8 static
RAMs in chip sets 0 and 1 and 4K by 8 PROMs in chip sets 4 and 5. The order of
res'ponse is chip set 0, 1, 5, and 4. Note that the higher capacity device must
respond first as previously described,
In page mode, bits 11 through 21 of the bus address are stripped off, Bits 11
through 17 are replaced with bits from the PCR representing the page number for
the corresponding window,
The bus address lies between the starting address and the starting address plus 4
kilobytes because this is the defined window size,
The page number is designated by bits 11 through 17. However; the decoder
address looks at bits 12 through 17 and ignores bit 11 because this bit defines 2kilobyte boundaries. Note that the pattern select bits are 012 indicating pattern 1 is
selected.
Pages are 2 kilobytes wide. In an 8K by 8 device pair (16 kilobytes), there are eight
2-kilobyte pages. In the 4K by 8 devices, there are four 2-kilobyte pages. The array
decoder looks at 4-kilobyte blocks and each bus address entry is 2 kilobytes.
Therefore, each array decoder address entry repeats to provide 4-kilobyte blocks
in the pattern.
During operation, the page number must be in the corresponding byte of the
desired window. If the page is in window 0, the lower byte of the PCR is designated. If page is in window 1, the upper byte of the PCR is designated.
This example consists of 24 pages. Eight pages are for each of the two 8K by 8
devices, and four pages are for each of the two 4K by 8 devices.
When the twenty-fifth page is reached, the out-of-range bit is asserted and the C,
B, and A lines are denoted with Xs, which indicate the "don't care" condition.
PROGRAMMING THE ARRAY DECODER
CS6 CS7 CS6 CS7
-
-
-
MODE: PAGE
PATTERN SELECTED: 1
START ADDRESS: 60000 (OCTALI
PCR ADDRESS: 17777000 (OCTALI
DEVICES: BK BY B STATIC RAMS IN CSO. CS1;
4K BY 4 PROMS IN CS4' CS5
ORDER OF RESPONSE: CSO. CS1. CS5. CS4
-
CS4 CS5 CS4 CS5
4K 4K 4K 4K
CS2 CS3 CS2 CS3
-
-
,
-
-
CSO CS1 CSO CS1
BK BK BK BK
PAGE NUMBER
17 16 15
DECODER DATA
DECODER ADDRESS
14 13 12
11
X X
PATTERN
SELECT
,..-'--,
B A 1B
OUT OF
17 16 15
141312
RANGE
C B A
000
000
000
000
000
000
000
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 0
1 0
1 0
1 0
1 1
1 ,1
1 1
1 1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1 0
1 0
1 1
1 1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1 0
1 0
1 1
1 1
0
0
0
0
\
I
T
I
1
1
1
- - - -
··,·
·
1
\
I
\
1
- - -
1
1
- - -
- -
-
0
0
0
0
1
1
1
1
I
T
··
·.·
0
1
- - - -
0
1
1
\
1
1
1
1
CHIP SET 0
BK BY 16
RAM
PAIR
o0 1
00
o0
o0
o0
o0
o0
o0
1
1
1
1
1
1
1
CHIP SET 1
BK BY 16
RAM
PAIR
"'}
"'}
1 0 1
1 0 1
1 0 1
1 0 0
100
1 00
~
···
XXX
~
1
END OF PATTERN 1 - - - -
-
-
-
-
CHIP SET 5
4K BY 16
PROM
PAIR
CHIP SET 4
4K BY 16
PROM
PAIR
OUTOF
RA~GE
··
OUT OF
RANGE
MA-0190-83
Figure 5-8
Array Decoder Design - EXample 3
55
MAINTENANCE
6.1
INTRODUCTION
No diagnostic programs are available for the MRV11-0. Each customer supplies
his own firmware. Consequently, each module has a separate configuration, ruling
out a common diagnostic.
In lieu of diagnostics, perform the following procedures to determine whether the
module or the PROMs installed in the module have malfunctioned.
6.2 TROUBLESHOOTING
If there is a malfunction on the MRV11-0 and a set of spare devices is available,
remove the devices from the module and insert the spare set If changing devices
does not solve the problem, perform the following steps.
1. Check the LED on the module. If it is not lit, power is probably not being supplied to·the memory array.
2. Check the battery backup jumper to see that it is correctly positioned. If it is.
the problem is in the power distribution to the backplane.
3. Check the jumper configurations to ensure that the module is properly
configured.
4. If console OOT is available, additional steps can be performed. The following
section describes these steps.
58
MAINTENANCE
6.3 CONSOLE OOT
The console octal debugging technique (OOT) is a portion of the processor microcode that is very useful for debugging and running programs. Console OOT allows·
the processor to respond to commands and information entered from a local or
remote terminal. Communication between the user and processor is generated via
a stream of ASCII characters interpreted by the processor as console commands.
These commands are a subset of OOT-11 (Table 6-1).
Terminal addresses used by console OOT are 1775608 through 1775668. It uses
addresses 7775608 through 7775668 for 18-bit systems and 177775608 through
177775668 for 22-bit systems. These addresses are generated in microcode and
cannot be altered.
The following paragraphs describe the console OOT terminal command set (Table
6-1). These commands are a subset of OOT-11 and use the same command characters. Console OOT has 10 internal states, which are listed in Table 6-2. For each
state, only specific characters are recognized as valid inputs; other inputs invoke a
"?" response.
MAINTENANCE
59
60
MAINTENA.NCE
For additional information on OOT, refer to the Microcomputer and Memories
Handbook (EB-20912-20). If you suspect the module to be malfunctioning, perform the steps in paragraph 6.2. If console OOT is available, perform the following
additional steps. Press the HALT switch on the front panel to initiate OOT.
1. If bootstrap is enabled, open the bootstrap PCR at 177775208 and ensure
that all bits can be read or written.
2. If bootstrap is enabled, you should be able to read bootstrap code at the following locations.
177730008-177737768
177650008 - 177657768
3. If page mode is enabled, you should be able to read and write the page mode
PCR in the location set by the PCR address switches. You should not be able
to read other locations since a timeout should occur and OOT should
respond with a"?"
4. If two MRV11-0s are configured for page mode in the same system, two
unique PCRs should appear in two locations between 177770008 and
177770368.
5. Set PCR bit 15 (window enable) to a 1 and put a desired page number in
each byte of the PCR. You should see the requested pages through window
o (at the starting address) and window 1 (2 kilobytes above the starting
address).
6. Set bit 15 to a: O. Timeout should occur at the locations in step 5 and a"?"
should appear on the terminal.
7. If you exceed the page limit of the MRV11-0 set by the decoder PROM (by
placing a page number in the PCR that is too large), timeout occurs and a "1"
al2pears on the terminal.
8. In direct mode, all unused PCR locations should time out and expected data
should appear from the starting address to the upper boundary of the array
(which is set by the decoder PROM).
9. If RAM is present on the module, it should be read/write. If you are unable to
write RAM, check the following jumpers.
W4 - OATO timeout'
W5 - Write enable (high byte)
W6 - Write enable (low byte)
MAl NTENANCE
61
10. Check voltage at bus pins BV1, AA2, and BA2 for + 5 V.
11. If battery backup is installed, check voltage at bus pin
~ V1
for + 5 V.
If the above steps do not solve the problem, contact the Technical Volume Group
Hotline (617) 467-7787.
The module may be repaired by the Customer Return Center in Woburn,
Massachusetts provided all customer .firmware is removed and the module is properly packaged. For more information, call 1-(800)-225-5385.
MODULE
CONFIGURATION
This appendix summarizes the module configuration given in Chapter 3. Figure 3-2
is a flow diagram that provides the sequence for configuring the module. Figure 3-3
shows the locations of the jumper groups on the modules. Use Figure 3-3 in conjunction with Figure A-1, which represents the location of each jumper pin on the
module.
For example, to configure the device size jumpers, use Figure 3-3 to determine
their location on the module (just to the right of E20 upper-right quadrant of module). Then refer to the device size jumpers listed in Figure A-1. Figure A-1 shows
the dev~ce size jumpers, in detail, as a'set of five jumpers (J14 through J10)
arranged vertically. The orientation is component-side-up with the handles facing
away. It is important to maintain this orientation as the jumpers on the module are
not designated. With this orientation, J14 is the jumper closest to the handles and
J 10 is farthest frorn--the handles. The PCR address switches and start address
switches are shown at the end of Figure A-1.
'63
64
APPENDIX
FUNCTION
JUMPER CONNECTION
BATTERY BACKUP
NO BATTERY BACKUP
(SHIPPED CONFIGURATION
(W2 REMOVED)
BATTERY BACKUP (Wl REMOVED)
W1
o
~HOLESON
W2
601 o
PRINTED
CIRCUIT
BOARD
SYSTEM SIZE
16-BIT, 18-BIT
(SHIPPED CONFIGURATION)
W3
660
J21 J22 J23
W3
22-BIT
066
J21 J22 J23
ROM/RAM SELECT
ALL ROM MEMORY
(SHIPPED CONFIGURATION)
J38~
W5
J37
J360
J32~ W4
';31
J300
ROM/RAM MEMORY
J380
J37~ W5
J36
J320
J31~ W4
J30
DATO JUMPER
DATO CYCLE CAUSES TIMEOUT
(NOT USED WITH RAM)
(SHIPPED CONFIGURATION)
NO DATO CYCLE
RESPONDS TO DATO CYCLES
(USED WITH RAM INSTALLED)
W6
660
J15 J16 J17
W6
066
J15 J16 J17
MA·0201·8:J
Figure A-1
Module Configuration (Part 1)
APPENDIX
FUNCTION
JUMPER CONNECTION
REV O·
REV C·
ETCH
ETCH
0 J14 0
OEVICE SIZE
2K BY 8 DEVICES t{SHIPPED
CONFIGURATION)
W8~
AN~
W7
J13
J12
Jll
gJW8
~AND
W7
Jl0
4K BY B, BK BY B,
OR 16K BY B DEVICES
J14
WBC;
AND
32K BY B DEVICES
0
J13
J12
~WB
~:~D
W7~
Jll
Jl0
0
WB~
J14
J13
~W8
J12
0
Jll
~W7
AN~
W7
0
Jl0
AND
·TO LOCATE THE REVISION OF THE ETCH. REFER TO THE
LEFT SIDE OF THE MODULE. COMPONENT SIDE UP.
REVISION C ETCH - 5015213C
REVISION 0 ETCH - 50152130
no USE 2K BY B DEVICES
(REV C ETCH ONLY).
REMOVE W8AND WIREWRAP PIN J13TO PIN J41
(+5VI.
MA 020083
Figure A-1
Module Configuration Wart 2)
65
66
APPENDIX
FUNCT ,UN
---_.-
JUMPER CONNECTION
POWE R. dMPE RS
2K BY 8AND 4K BY 8 ROMS AND
BK BY 8 STATIC RAM (SHIPPED
CONFIGURATION)
J41
J4D
0-, W12
o-J
ROW4
J390
J35
J34
0-, Wll
o-J ROW 3
J330
J29
J28
0-, WID
o-J R{)W 2
J270
J26
J25
0-, W9
o-J ROW 1
J240
16K BY BAND 32K BY 8 ROMS
18K BY 8 ROMS ARE OPTIONAL AND
MAY.USE EITHER SET OF JUMPER
CONNECTIONS)
J41 0
J40 o-,W12
J39 o-J ROiN 4
J350
J34 o-,Wll
J33
oJ ROW 3
J29
0
J28o-,Wl0
J27
oJ ROW 2
J280
J25 o-,W9
J24
oJ ROW 1
NOTE
THE POWER JUMPERS ARE CONNECTED ON A ROW·BY·ROW
BASIS. FOR EXAMPl.E. IF A 181< BY B OR 32K BY B
DEVICE WERE INSTALLED IN ROW 2. WIOWOULD BE
CONNECTED FROM J28 TO J27 RATHER THAN J29 TO J2B.
MA·a,H·U
Figure A-1
Module Configuration (Part 3)
APPENDIX
FUNCTION-
-JUMPER CONNECTION
READ TIMING
450 ns READ TIME (NORMAL)
(SHIPPED CONFIGURATION)
W13
660
J18 J19 J20
200 ns READ TIME (FAST)
W13
066
J18 J19 J20
ENABLE BOOTSTRAP
BOOTSTRAP ENABLED
(SHIPPED CONFIGURATIONI
J6~ W14
J5
J40
BOOTSTRAP DISABLED
J60
J5o-,W14
J4
o-J
STANDARD DECODER PATTERN SELECT
2K BY B ROMS, HALF POPULATED
J90
J30
J8~ W16
J2~
.
W15
J90
J3~ W15
J7
2K BY 8 ROMS, FULLY POPULATED
J8~ W16
4K BY 8 ROMS, FULLY POPULATED
J2
J7
Jl0
J9~ W16
J30
J8
BK BY B ROMS, FULLY POP,-ULATED
(SHIPPED CONFIGURATION)
Jl
J2~ W15
J70
Jl
J9~ W16
J3~ W15
J70
Jl0
JB
J2
MA-0202-B3
Figure A-1
Module Configuration (Part 4)
67
68
APPENDIX
FUNCTION
SWITCHES
STARTING ADDRESS SWITCHES
PUSHING RIGHT ROCKER OF SWITCH
TURNS SWITCH ON (LOGIC 1l.
PUSHING LEFT ROCKER OF SWITCH
TURNS SWITCH OFF (LOGIC 0).
SET FOR STARTING ADDRESS OF THE
MODULE.
OJo
SA21 MSB
[1]-
SA20
[1]~
SA19
[IJW
SA1B
[1] ..
SA 17
[1]~
SA16
[IJ'"
SA15
[1]--
SA14
[IJ'"
SA13
[1]<0
SA12LSB
PCR ADDRESS SWITCHES
TO SELECT DIRECT MODE, PUSH RIGHT
ROCKER DOWN. TO SELECT PAGE MODE,
PUSH LEFT ROCKER DOWN.
PCRl THROUGH PCR4 REPRESENT THE
ADDRESS OF PCR, PUSHING RIGHT ROCKER
OF SWITCH PRODUCES A LOGICAL 0
(SWITCH OFF). PUSHING LEFT ROCKER OF
SWITCH PRODUCES A LOGICAL 1 (SWITCH ON).
[1]0
[IJ-
ON·DIRECT
OFF PAGE
PCR4
OJ~
PCR3
[IJw
PCR2
ITJ ..
PCRl
NOTE
MODULE ORIENTED WITH HANDLES FACING AWAY.
MA-019S-S3
Figure A-l
Module Configuration (Part 5)
Digital Equipment Corporation. Bedford. MA 01730
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